1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
27
28
29#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
30
31/*
32 * Chip flags
33 */
34enum amd_chip_flags {
35 AMD_ASIC_MASK = 0x0000ffffUL,
36 AMD_FLAGS_MASK = 0xffff0000UL,
37 AMD_IS_MOBILITY = 0x00010000UL,
38 AMD_IS_APU = 0x00020000UL,
39 AMD_IS_PX = 0x00040000UL,
40 AMD_EXP_HW_SUPPORT = 0x00080000UL,
41};
42
43enum amd_ip_block_type {
44 AMD_IP_BLOCK_TYPE_COMMON,
45 AMD_IP_BLOCK_TYPE_GMC,
46 AMD_IP_BLOCK_TYPE_IH,
47 AMD_IP_BLOCK_TYPE_SMC,
48 AMD_IP_BLOCK_TYPE_PSP,
49 AMD_IP_BLOCK_TYPE_DCE,
50 AMD_IP_BLOCK_TYPE_GFX,
51 AMD_IP_BLOCK_TYPE_SDMA,
52 AMD_IP_BLOCK_TYPE_UVD,
53 AMD_IP_BLOCK_TYPE_VCE,
54 AMD_IP_BLOCK_TYPE_ACP,
55 AMD_IP_BLOCK_TYPE_VCN
56};
57
58enum amd_clockgating_state {
59 AMD_CG_STATE_GATE = 0,
60 AMD_CG_STATE_UNGATE,
61};
62
63
64enum amd_powergating_state {
65 AMD_PG_STATE_GATE = 0,
66 AMD_PG_STATE_UNGATE,
67};
68
69
70/* CG flags */
71#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
72#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
73#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
74#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
75#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
76#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
77#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
78#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
79#define AMD_CG_SUPPORT_MC_LS (1 << 8)
80#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
81#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
82#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
83#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
84#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
85#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
86#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
87#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
88#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
89#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
90#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
91#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
92#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
93#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
94#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
95#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24)
96/* PG flags */
97#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
98#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
99#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
100#define AMD_PG_SUPPORT_UVD (1 << 3)
101#define AMD_PG_SUPPORT_VCE (1 << 4)
102#define AMD_PG_SUPPORT_CP (1 << 5)
103#define AMD_PG_SUPPORT_GDS (1 << 6)
104#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
105#define AMD_PG_SUPPORT_SDMA (1 << 8)
106#define AMD_PG_SUPPORT_ACP (1 << 9)
107#define AMD_PG_SUPPORT_SAMU (1 << 10)
108#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
109#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
110#define AMD_PG_SUPPORT_MMHUB (1 << 13)
111#define AMD_PG_SUPPORT_VCN (1 << 14)
112#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
113
114enum PP_FEATURE_MASK {
115 PP_SCLK_DPM_MASK = 0x1,
116 PP_MCLK_DPM_MASK = 0x2,
117 PP_PCIE_DPM_MASK = 0x4,
118 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
119 PP_POWER_CONTAINMENT_MASK = 0x10,
120 PP_UVD_HANDSHAKE_MASK = 0x20,
121 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
122 PP_VBI_TIME_SUPPORT_MASK = 0x80,
123 PP_ULV_MASK = 0x100,
124 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
125 PP_CLOCK_STRETCH_MASK = 0x400,
126 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
127 PP_SOCCLK_DPM_MASK = 0x1000,
128 PP_DCEFCLK_DPM_MASK = 0x2000,
129 PP_OVERDRIVE_MASK = 0x4000,
130 PP_GFXOFF_MASK = 0x8000,
131 PP_ACG_MASK = 0x10000,
132 PP_STUTTER_MODE = 0x20000,
133 PP_AVFS_MASK = 0x40000,
134};
135
136enum DC_FEATURE_MASK {
137 DC_FBC_MASK = 0x1,
138};
139
140/**
141 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
142 */
143struct amd_ip_funcs {
144 /** @name: Name of IP block */
145 char *name;
146 /**
147 * @early_init:
148 *
149 * sets up early driver state (pre sw_init),
150 * does not configure hw - Optional
151 */
152 int (*early_init)(void *handle);
153 /** @late_init: sets up late driver/hw state (post hw_init) - Optional */
154 int (*late_init)(void *handle);
155 /** @sw_init: sets up driver state, does not configure hw */
156 int (*sw_init)(void *handle);
157 /** @sw_fini: tears down driver state, does not configure hw */
158 int (*sw_fini)(void *handle);
159 /** @hw_init: sets up the hw state */
160 int (*hw_init)(void *handle);
161 /** @hw_fini: tears down the hw state */
162 int (*hw_fini)(void *handle);
163 /** @late_fini: final cleanup */
164 void (*late_fini)(void *handle);
165 /** @suspend: handles IP specific hw/sw changes for suspend */
166 int (*suspend)(void *handle);
167 /** @resume: handles IP specific hw/sw changes for resume */
168 int (*resume)(void *handle);
169 /** @is_idle: returns current IP block idle status */
170 bool (*is_idle)(void *handle);
171 /** @wait_for_idle: poll for idle */
172 int (*wait_for_idle)(void *handle);
173 /** @check_soft_reset: check soft reset the IP block */
174 bool (*check_soft_reset)(void *handle);
175 /** @pre_soft_reset: pre soft reset the IP block */
176 int (*pre_soft_reset)(void *handle);
177 /** @soft_reset: soft reset the IP block */
178 int (*soft_reset)(void *handle);
179 /** @post_soft_reset: post soft reset the IP block */
180 int (*post_soft_reset)(void *handle);
181 /** @set_clockgating_state: enable/disable cg for the IP block */
182 int (*set_clockgating_state)(void *handle,
183 enum amd_clockgating_state state);
184 /** @set_powergating_state: enable/disable pg for the IP block */
185 int (*set_powergating_state)(void *handle,
186 enum amd_powergating_state state);
187 /** @get_clockgating_state: get current clockgating status */
188 void (*get_clockgating_state)(void *handle, u32 *flags);
189};
190
191
192#endif /* __AMD_SHARED_H__ */
193