1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef BIF_3_0_D_H
24#define BIF_3_0_D_H
25
26#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
27#define ixPB0_DFT_JIT_INJ_REG0 0x13000
28#define ixPB0_DFT_JIT_INJ_REG1 0x13004
29#define ixPB0_DFT_JIT_INJ_REG2 0x13008
30#define ixPB0_GLB_CTRL_REG0 0x10004
31#define ixPB0_GLB_CTRL_REG1 0x10008
32#define ixPB0_GLB_CTRL_REG2 0x1000C
33#define ixPB0_GLB_CTRL_REG3 0x10010
34#define ixPB0_GLB_CTRL_REG4 0x10014
35#define ixPB0_GLB_CTRL_REG5 0x10018
36#define ixPB0_GLB_OVRD_REG0 0x10030
37#define ixPB0_GLB_OVRD_REG1 0x10034
38#define ixPB0_GLB_OVRD_REG2 0x10038
39#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C
40#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020
41#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024
42#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028
43#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C
44#define ixPB0_HW_DEBUG 0x12004
45#define ixPB0_PIF_CNTL 0x0010
46#define ixPB0_PIF_CNTL2 0x0014
47#define ixPB0_PIF_HW_DEBUG 0x0002
48#define ixPB0_PIF_PAIRING 0x0011
49#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020
50#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032
51#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021
52#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033
53#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034
54#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035
55#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036
56#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037
57#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022
58#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023
59#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024
60#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025
61#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026
62#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027
63#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030
64#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031
65#define ixPB0_PIF_PWRDOWN_0 0x0012
66#define ixPB0_PIF_PWRDOWN_1 0x0013
67#define ixPB0_PIF_PWRDOWN_2 0x0017
68#define ixPB0_PIF_PWRDOWN_3 0x0018
69#define ixPB0_PIF_SC_CTL 0x0016
70#define ixPB0_PIF_SCRATCH 0x0001
71#define ixPB0_PIF_SEQ_STATUS_0 0x0028
72#define ixPB0_PIF_SEQ_STATUS_10 0x003A
73#define ixPB0_PIF_SEQ_STATUS_1 0x0029
74#define ixPB0_PIF_SEQ_STATUS_11 0x003B
75#define ixPB0_PIF_SEQ_STATUS_12 0x003C
76#define ixPB0_PIF_SEQ_STATUS_13 0x003D
77#define ixPB0_PIF_SEQ_STATUS_14 0x003E
78#define ixPB0_PIF_SEQ_STATUS_15 0x003F
79#define ixPB0_PIF_SEQ_STATUS_2 0x002A
80#define ixPB0_PIF_SEQ_STATUS_3 0x002B
81#define ixPB0_PIF_SEQ_STATUS_4 0x002C
82#define ixPB0_PIF_SEQ_STATUS_5 0x002D
83#define ixPB0_PIF_SEQ_STATUS_6 0x002E
84#define ixPB0_PIF_SEQ_STATUS_7 0x002F
85#define ixPB0_PIF_SEQ_STATUS_8 0x0038
86#define ixPB0_PIF_SEQ_STATUS_9 0x0039
87#define ixPB0_PIF_TXPHYSTATUS 0x0015
88#define ixPB0_PLL_LC0_CTRL_REG0 0x14480
89#define ixPB0_PLL_LC0_OVRD_REG0 0x14490
90#define ixPB0_PLL_LC0_OVRD_REG1 0x14494
91#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
92#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
93#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
94#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
95#define ixPB0_PLL_RO0_CTRL_REG0 0x14440
96#define ixPB0_PLL_RO0_OVRD_REG0 0x14450
97#define ixPB0_PLL_RO0_OVRD_REG1 0x14454
98#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
99#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
100#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
101#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
102#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000
103#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010
104#define ixPB0_RX_GLB_CTRL_REG0 0x16000
105#define ixPB0_RX_GLB_CTRL_REG1 0x16004
106#define ixPB0_RX_GLB_CTRL_REG2 0x16008
107#define ixPB0_RX_GLB_CTRL_REG3 0x1600C
108#define ixPB0_RX_GLB_CTRL_REG4 0x16010
109#define ixPB0_RX_GLB_CTRL_REG5 0x16014
110#define ixPB0_RX_GLB_CTRL_REG6 0x16018
111#define ixPB0_RX_GLB_CTRL_REG7 0x1601C
112#define ixPB0_RX_GLB_CTRL_REG8 0x16020
113#define ixPB0_RX_GLB_OVRD_REG0 0x16030
114#define ixPB0_RX_GLB_OVRD_REG1 0x16034
115#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
116#define ixPB0_RX_LANE0_CTRL_REG0 0x16440
117#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
118#define ixPB0_RX_LANE10_CTRL_REG0 0x17500
119#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
120#define ixPB0_RX_LANE11_CTRL_REG0 0x17600
121#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
122#define ixPB0_RX_LANE12_CTRL_REG0 0x17840
123#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
124#define ixPB0_RX_LANE13_CTRL_REG0 0x17880
125#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
126#define ixPB0_RX_LANE14_CTRL_REG0 0x17900
127#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
128#define ixPB0_RX_LANE15_CTRL_REG0 0x17A00
129#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
130#define ixPB0_RX_LANE1_CTRL_REG0 0x16480
131#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
132#define ixPB0_RX_LANE2_CTRL_REG0 0x16500
133#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
134#define ixPB0_RX_LANE3_CTRL_REG0 0x16600
135#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
136#define ixPB0_RX_LANE4_CTRL_REG0 0x16800
137#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
138#define ixPB0_RX_LANE5_CTRL_REG0 0x16880
139#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
140#define ixPB0_RX_LANE6_CTRL_REG0 0x16900
141#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
142#define ixPB0_RX_LANE7_CTRL_REG0 0x16A00
143#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
144#define ixPB0_RX_LANE8_CTRL_REG0 0x17440
145#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
146#define ixPB0_RX_LANE9_CTRL_REG0 0x17480
147#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
148#define ixPB0_STRAP_GLB_REG0 0x12020
149#define ixPB0_STRAP_PLL_REG0 0x12030
150#define ixPB0_STRAP_RX_REG0 0x12028
151#define ixPB0_STRAP_RX_REG1 0x1202C
152#define ixPB0_STRAP_TX_REG0 0x12024
153#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
154#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
155#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
156#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
157#define ixPB0_TX_GLB_CTRL_REG0 0x18000
158#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004
159#define ixPB0_TX_GLB_OVRD_REG0 0x18030
160#define ixPB0_TX_GLB_OVRD_REG1 0x18034
161#define ixPB0_TX_GLB_OVRD_REG2 0x18038
162#define ixPB0_TX_GLB_OVRD_REG3 0x1803C
163#define ixPB0_TX_GLB_OVRD_REG4 0x18040
164#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
165#define ixPB0_TX_LANE0_CTRL_REG0 0x18440
166#define ixPB0_TX_LANE0_OVRD_REG0 0x18444
167#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
168#define ixPB0_TX_LANE10_CTRL_REG0 0x19500
169#define ixPB0_TX_LANE10_OVRD_REG0 0x19504
170#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
171#define ixPB0_TX_LANE11_CTRL_REG0 0x19600
172#define ixPB0_TX_LANE11_OVRD_REG0 0x19604
173#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
174#define ixPB0_TX_LANE12_CTRL_REG0 0x19840
175#define ixPB0_TX_LANE12_OVRD_REG0 0x19844
176#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
177#define ixPB0_TX_LANE13_CTRL_REG0 0x19880
178#define ixPB0_TX_LANE13_OVRD_REG0 0x19884
179#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
180#define ixPB0_TX_LANE14_CTRL_REG0 0x19900
181#define ixPB0_TX_LANE14_OVRD_REG0 0x19904
182#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
183#define ixPB0_TX_LANE15_CTRL_REG0 0x19A00
184#define ixPB0_TX_LANE15_OVRD_REG0 0x19A04
185#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
186#define ixPB0_TX_LANE1_CTRL_REG0 0x18480
187#define ixPB0_TX_LANE1_OVRD_REG0 0x18484
188#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
189#define ixPB0_TX_LANE2_CTRL_REG0 0x18500
190#define ixPB0_TX_LANE2_OVRD_REG0 0x18504
191#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
192#define ixPB0_TX_LANE3_CTRL_REG0 0x18600
193#define ixPB0_TX_LANE3_OVRD_REG0 0x18604
194#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
195#define ixPB0_TX_LANE4_CTRL_REG0 0x18840
196#define ixPB0_TX_LANE4_OVRD_REG0 0x18844
197#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
198#define ixPB0_TX_LANE5_CTRL_REG0 0x18880
199#define ixPB0_TX_LANE5_OVRD_REG0 0x18884
200#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
201#define ixPB0_TX_LANE6_CTRL_REG0 0x18900
202#define ixPB0_TX_LANE6_OVRD_REG0 0x18904
203#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
204#define ixPB0_TX_LANE7_CTRL_REG0 0x18A00
205#define ixPB0_TX_LANE7_OVRD_REG0 0x18A04
206#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
207#define ixPB0_TX_LANE8_CTRL_REG0 0x19440
208#define ixPB0_TX_LANE8_OVRD_REG0 0x19444
209#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
210#define ixPB0_TX_LANE9_CTRL_REG0 0x19480
211#define ixPB0_TX_LANE9_OVRD_REG0 0x19484
212#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
213#define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C
214#define ixPB1_DFT_JIT_INJ_REG0 0x13000
215#define ixPB1_DFT_JIT_INJ_REG1 0x13004
216#define ixPB1_DFT_JIT_INJ_REG2 0x13008
217#define ixPB1_GLB_CTRL_REG0 0x10004
218#define ixPB1_GLB_CTRL_REG1 0x10008
219#define ixPB1_GLB_CTRL_REG2 0x1000C
220#define ixPB1_GLB_CTRL_REG3 0x10010
221#define ixPB1_GLB_CTRL_REG4 0x10014
222#define ixPB1_GLB_CTRL_REG5 0x10018
223#define ixPB1_GLB_OVRD_REG0 0x10030
224#define ixPB1_GLB_OVRD_REG1 0x10034
225#define ixPB1_GLB_OVRD_REG2 0x10038
226#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C
227#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020
228#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024
229#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028
230#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C
231#define ixPB1_HW_DEBUG 0x12004
232#define ixPB1_PIF_CNTL 0x0010
233#define ixPB1_PIF_CNTL2 0x0014
234#define ixPB1_PIF_HW_DEBUG 0x0002
235#define ixPB1_PIF_PAIRING 0x0011
236#define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020
237#define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032
238#define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021
239#define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033
240#define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034
241#define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035
242#define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036
243#define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037
244#define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022
245#define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023
246#define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024
247#define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025
248#define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026
249#define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027
250#define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030
251#define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031
252#define ixPB1_PIF_PWRDOWN_0 0x0012
253#define ixPB1_PIF_PWRDOWN_1 0x0013
254#define ixPB1_PIF_PWRDOWN_2 0x0017
255#define ixPB1_PIF_PWRDOWN_3 0x0018
256#define ixPB1_PIF_SC_CTL 0x0016
257#define ixPB1_PIF_SCRATCH 0x0001
258#define ixPB1_PIF_SEQ_STATUS_0 0x0028
259#define ixPB1_PIF_SEQ_STATUS_10 0x003A
260#define ixPB1_PIF_SEQ_STATUS_1 0x0029
261#define ixPB1_PIF_SEQ_STATUS_11 0x003B
262#define ixPB1_PIF_SEQ_STATUS_12 0x003C
263#define ixPB1_PIF_SEQ_STATUS_13 0x003D
264#define ixPB1_PIF_SEQ_STATUS_14 0x003E
265#define ixPB1_PIF_SEQ_STATUS_15 0x003F
266#define ixPB1_PIF_SEQ_STATUS_2 0x002A
267#define ixPB1_PIF_SEQ_STATUS_3 0x002B
268#define ixPB1_PIF_SEQ_STATUS_4 0x002C
269#define ixPB1_PIF_SEQ_STATUS_5 0x002D
270#define ixPB1_PIF_SEQ_STATUS_6 0x002E
271#define ixPB1_PIF_SEQ_STATUS_7 0x002F
272#define ixPB1_PIF_SEQ_STATUS_8 0x0038
273#define ixPB1_PIF_SEQ_STATUS_9 0x0039
274#define ixPB1_PIF_TXPHYSTATUS 0x0015
275#define ixPB1_PLL_LC0_CTRL_REG0 0x14480
276#define ixPB1_PLL_LC0_OVRD_REG0 0x14490
277#define ixPB1_PLL_LC0_OVRD_REG1 0x14494
278#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
279#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
280#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
281#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
282#define ixPB1_PLL_RO0_CTRL_REG0 0x14440
283#define ixPB1_PLL_RO0_OVRD_REG0 0x14450
284#define ixPB1_PLL_RO0_OVRD_REG1 0x14454
285#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
286#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
287#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
288#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
289#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000
290#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010
291#define ixPB1_RX_GLB_CTRL_REG0 0x16000
292#define ixPB1_RX_GLB_CTRL_REG1 0x16004
293#define ixPB1_RX_GLB_CTRL_REG2 0x16008
294#define ixPB1_RX_GLB_CTRL_REG3 0x1600C
295#define ixPB1_RX_GLB_CTRL_REG4 0x16010
296#define ixPB1_RX_GLB_CTRL_REG5 0x16014
297#define ixPB1_RX_GLB_CTRL_REG6 0x16018
298#define ixPB1_RX_GLB_CTRL_REG7 0x1601C
299#define ixPB1_RX_GLB_CTRL_REG8 0x16020
300#define ixPB1_RX_GLB_OVRD_REG0 0x16030
301#define ixPB1_RX_GLB_OVRD_REG1 0x16034
302#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028
303#define ixPB1_RX_LANE0_CTRL_REG0 0x16440
304#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448
305#define ixPB1_RX_LANE10_CTRL_REG0 0x17500
306#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508
307#define ixPB1_RX_LANE11_CTRL_REG0 0x17600
308#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608
309#define ixPB1_RX_LANE12_CTRL_REG0 0x17840
310#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848
311#define ixPB1_RX_LANE13_CTRL_REG0 0x17880
312#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888
313#define ixPB1_RX_LANE14_CTRL_REG0 0x17900
314#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908
315#define ixPB1_RX_LANE15_CTRL_REG0 0x17A00
316#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08
317#define ixPB1_RX_LANE1_CTRL_REG0 0x16480
318#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488
319#define ixPB1_RX_LANE2_CTRL_REG0 0x16500
320#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508
321#define ixPB1_RX_LANE3_CTRL_REG0 0x16600
322#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608
323#define ixPB1_RX_LANE4_CTRL_REG0 0x16800
324#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848
325#define ixPB1_RX_LANE5_CTRL_REG0 0x16880
326#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888
327#define ixPB1_RX_LANE6_CTRL_REG0 0x16900
328#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908
329#define ixPB1_RX_LANE7_CTRL_REG0 0x16A00
330#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08
331#define ixPB1_RX_LANE8_CTRL_REG0 0x17440
332#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448
333#define ixPB1_RX_LANE9_CTRL_REG0 0x17480
334#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488
335#define ixPB1_STRAP_GLB_REG0 0x12020
336#define ixPB1_STRAP_PLL_REG0 0x12030
337#define ixPB1_STRAP_RX_REG0 0x12028
338#define ixPB1_STRAP_RX_REG1 0x1202C
339#define ixPB1_STRAP_TX_REG0 0x12024
340#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014
341#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018
342#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C
343#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020
344#define ixPB1_TX_GLB_CTRL_REG0 0x18000
345#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004
346#define ixPB1_TX_GLB_OVRD_REG0 0x18030
347#define ixPB1_TX_GLB_OVRD_REG1 0x18034
348#define ixPB1_TX_GLB_OVRD_REG2 0x18038
349#define ixPB1_TX_GLB_OVRD_REG3 0x1803C
350#define ixPB1_TX_GLB_OVRD_REG4 0x18040
351#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010
352#define ixPB1_TX_LANE0_CTRL_REG0 0x18440
353#define ixPB1_TX_LANE0_OVRD_REG0 0x18444
354#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448
355#define ixPB1_TX_LANE10_CTRL_REG0 0x19500
356#define ixPB1_TX_LANE10_OVRD_REG0 0x19504
357#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508
358#define ixPB1_TX_LANE11_CTRL_REG0 0x19600
359#define ixPB1_TX_LANE11_OVRD_REG0 0x19604
360#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608
361#define ixPB1_TX_LANE12_CTRL_REG0 0x19840
362#define ixPB1_TX_LANE12_OVRD_REG0 0x19844
363#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848
364#define ixPB1_TX_LANE13_CTRL_REG0 0x19880
365#define ixPB1_TX_LANE13_OVRD_REG0 0x19884
366#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888
367#define ixPB1_TX_LANE14_CTRL_REG0 0x19900
368#define ixPB1_TX_LANE14_OVRD_REG0 0x19904
369#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908
370#define ixPB1_TX_LANE15_CTRL_REG0 0x19A00
371#define ixPB1_TX_LANE15_OVRD_REG0 0x19A04
372#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08
373#define ixPB1_TX_LANE1_CTRL_REG0 0x18480
374#define ixPB1_TX_LANE1_OVRD_REG0 0x18484
375#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488
376#define ixPB1_TX_LANE2_CTRL_REG0 0x18500
377#define ixPB1_TX_LANE2_OVRD_REG0 0x18504
378#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508
379#define ixPB1_TX_LANE3_CTRL_REG0 0x18600
380#define ixPB1_TX_LANE3_OVRD_REG0 0x18604
381#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608
382#define ixPB1_TX_LANE4_CTRL_REG0 0x18840
383#define ixPB1_TX_LANE4_OVRD_REG0 0x18844
384#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848
385#define ixPB1_TX_LANE5_CTRL_REG0 0x18880
386#define ixPB1_TX_LANE5_OVRD_REG0 0x18884
387#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888
388#define ixPB1_TX_LANE6_CTRL_REG0 0x18900
389#define ixPB1_TX_LANE6_OVRD_REG0 0x18904
390#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908
391#define ixPB1_TX_LANE7_CTRL_REG0 0x18A00
392#define ixPB1_TX_LANE7_OVRD_REG0 0x18A04
393#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08
394#define ixPB1_TX_LANE8_CTRL_REG0 0x19440
395#define ixPB1_TX_LANE8_OVRD_REG0 0x19444
396#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448
397#define ixPB1_TX_LANE9_CTRL_REG0 0x19480
398#define ixPB1_TX_LANE9_OVRD_REG0 0x19484
399#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488
400#define ixPCIE_BUS_CNTL 0x0021
401#define ixPCIE_CFG_CNTL 0x003C
402#define ixPCIE_CI_CNTL 0x0020
403#define ixPCIE_CNTL 0x0010
404#define ixPCIE_CNTL2 0x001C
405#define ixPCIE_CONFIG_CNTL 0x0011
406#define ixPCIE_DEBUG_CNTL 0x0012
407#define ixPCIE_ERR_CNTL 0x006A
408#define ixPCIE_F0_DPA_CAP 0x00E0
409#define ixPCIE_F0_DPA_CNTL 0x00E5
410#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4
411#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7
412#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8
413#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9
414#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA
415#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB
416#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC
417#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED
418#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE
419#define ixPCIE_FC_CPL 0x0062
420#define ixPCIE_FC_NP 0x0061
421#define ixPCIE_FC_P 0x0060
422#define ixPCIE_HW_DEBUG 0x0002
423#define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A
424#define ixPCIE_I2C_REG_DATA 0x003B
425#define ixPCIE_INT_CNTL 0x001A
426#define ixPCIE_INT_STATUS 0x001B
427#define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9
428#define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2
429#define ixPCIE_LC_CDR_CNTL 0x00B3
430#define ixPCIE_LC_CNTL 0x00A0
431#define ixPCIE_LC_CNTL2 0x00B1
432#define ixPCIE_LC_CNTL3 0x00B5
433#define ixPCIE_LC_CNTL4 0x00B6
434#define ixPCIE_LC_CNTL5 0x00B7
435#define ixPCIE_LC_FORCE_COEFF 0x00B8
436#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA
437#define ixPCIE_LC_LANE_CNTL 0x00B4
438#define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2
439#define ixPCIE_LC_N_FTS_CNTL 0x00A3
440#define ixPCIE_LC_SPEED_CNTL 0x00A4
441#define ixPCIE_LC_STATE0 0x00A5
442#define ixPCIE_LC_STATE10 0x0026
443#define ixPCIE_LC_STATE1 0x00A6
444#define ixPCIE_LC_STATE11 0x0027
445#define ixPCIE_LC_STATE2 0x00A7
446#define ixPCIE_LC_STATE3 0x00A8
447#define ixPCIE_LC_STATE4 0x00A9
448#define ixPCIE_LC_STATE5 0x00AA
449#define ixPCIE_LC_STATE6 0x0022
450#define ixPCIE_LC_STATE7 0x0023
451#define ixPCIE_LC_STATE8 0x0024
452#define ixPCIE_LC_STATE9 0x0025
453#define ixPCIE_LC_STATUS1 0x0028
454#define ixPCIE_LC_STATUS2 0x0029
455#define ixPCIE_LC_TRAINING_CNTL 0x00A1
456#define ixPCIE_P_BUF_STATUS 0x0041
457#define ixPCIE_P_CNTL 0x0040
458#define ixPCIE_P_DECODER_STATUS 0x0042
459#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093
460#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094
461#define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087
462#define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084
463#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090
464#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A
465#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D
466#define ixPCIE_PERF_CNTL_TXCLK 0x0081
467#define ixPCIE_PERF_CNTL_TXCLK2 0x0095
468#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088
469#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085
470#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091
471#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B
472#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E
473#define ixPCIE_PERF_COUNT0_TXCLK 0x0082
474#define ixPCIE_PERF_COUNT0_TXCLK2 0x0096
475#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089
476#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086
477#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092
478#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C
479#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F
480#define ixPCIE_PERF_COUNT1_TXCLK 0x0083
481#define ixPCIE_PERF_COUNT1_TXCLK2 0x0097
482#define ixPCIE_PERF_COUNT_CNTL 0x0080
483#define ixPCIEP_HW_DEBUG 0x0002
484#define ixPCIE_P_MISC_STATUS 0x0043
485#define ixPCIEP_PORT_CNTL 0x0010
486#define ixPCIE_P_PORT_LANE_STATUS 0x0050
487#define ixPCIE_PRBS_CLR 0x00C8
488#define ixPCIE_PRBS_ERRCNT_0 0x00D0
489#define ixPCIE_PRBS_ERRCNT_10 0x00DA
490#define ixPCIE_PRBS_ERRCNT_1 0x00D1
491#define ixPCIE_PRBS_ERRCNT_11 0x00DB
492#define ixPCIE_PRBS_ERRCNT_12 0x00DC
493#define ixPCIE_PRBS_ERRCNT_13 0x00DD
494#define ixPCIE_PRBS_ERRCNT_14 0x00DE
495#define ixPCIE_PRBS_ERRCNT_15 0x00DF
496#define ixPCIE_PRBS_ERRCNT_2 0x00D2
497#define ixPCIE_PRBS_ERRCNT_3 0x00D3
498#define ixPCIE_PRBS_ERRCNT_4 0x00D4
499#define ixPCIE_PRBS_ERRCNT_5 0x00D5
500#define ixPCIE_PRBS_ERRCNT_6 0x00D6
501#define ixPCIE_PRBS_ERRCNT_7 0x00D7
502#define ixPCIE_PRBS_ERRCNT_8 0x00D8
503#define ixPCIE_PRBS_ERRCNT_9 0x00D9
504#define ixPCIE_PRBS_FREERUN 0x00CB
505#define ixPCIE_PRBS_HI_BITCNT 0x00CF
506#define ixPCIE_PRBS_LO_BITCNT 0x00CE
507#define ixPCIE_PRBS_MISC 0x00CC
508#define ixPCIE_PRBS_STATUS1 0x00C9
509#define ixPCIE_PRBS_STATUS2 0x00CA
510#define ixPCIE_PRBS_USER_PATTERN 0x00CD
511#define ixPCIE_P_RCV_L0S_FTS_DET 0x0050
512#define ixPCIEP_RESERVED 0x0000
513#define ixPCIEP_SCRATCH 0x0001
514#define ixPCIEP_STRAP_LC 0x00C0
515#define ixPCIEP_STRAP_MISC 0x00C1
516#define ixPCIE_RESERVED 0x0000
517#define ixPCIE_RX_CNTL 0x0070
518#define ixPCIE_RX_CNTL2 0x001D
519#define ixPCIE_RX_CNTL3 0x0074
520#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082
521#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081
522#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080
523#define ixPCIE_RX_EXPECTED_SEQNUM 0x0071
524#define ixPCIE_RX_LAST_TLP0 0x0031
525#define ixPCIE_RX_LAST_TLP1 0x0032
526#define ixPCIE_RX_LAST_TLP2 0x0033
527#define ixPCIE_RX_LAST_TLP3 0x0034
528#define ixPCIE_RX_NUM_NAK 0x000E
529#define ixPCIE_RX_NUM_NAK_GENERATED 0x000F
530#define ixPCIE_RX_VENDOR_SPECIFIC 0x0072
531#define ixPCIE_SCRATCH 0x0001
532#define ixPCIE_STRAP_F0 0x00B0
533#define ixPCIE_STRAP_F1 0x00B1
534#define ixPCIE_STRAP_F2 0x00B2
535#define ixPCIE_STRAP_F3 0x00B3
536#define ixPCIE_STRAP_F4 0x00B4
537#define ixPCIE_STRAP_F5 0x00B5
538#define ixPCIE_STRAP_F6 0x00B6
539#define ixPCIE_STRAP_F7 0x00B7
540#define ixPCIE_STRAP_I2C_BD 0x00C4
541#define ixPCIE_STRAP_MISC 0x00C0
542#define ixPCIE_STRAP_MISC2 0x00C1
543#define ixPCIE_STRAP_PI 0x00C2
544#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026
545#define ixPCIE_TX_CNTL 0x0020
546#define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032
547#define ixPCIE_TX_CREDITS_ADVT_NP 0x0031
548#define ixPCIE_TX_CREDITS_ADVT_P 0x0030
549#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037
550#define ixPCIE_TX_CREDITS_INIT_CPL 0x0035
551#define ixPCIE_TX_CREDITS_INIT_NP 0x0034
552#define ixPCIE_TX_CREDITS_INIT_P 0x0033
553#define ixPCIE_TX_CREDITS_STATUS 0x0036
554#define ixPCIE_TX_LAST_TLP0 0x0035
555#define ixPCIE_TX_LAST_TLP1 0x0036
556#define ixPCIE_TX_LAST_TLP2 0x0037
557#define ixPCIE_TX_LAST_TLP3 0x0038
558#define ixPCIE_TX_REPLAY 0x0025
559#define ixPCIE_TX_REQUESTER_ID 0x0021
560#define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023
561#define ixPCIE_TX_SEQ 0x0024
562#define ixPCIE_TX_VENDOR_SPECIFIC 0x0022
563#define ixPCIE_WPR_CNTL 0x0030
564#define mmBACO_CNTL 0x14E5
565#define mmBF_ANA_ISO_CNTL 0x14C7
566#define mmBIF_BACO_DEBUG 0x14DF
567#define mmBIF_BACO_DEBUG_LATCH 0x14DC
568#define mmBIF_BACO_MSIC 0x14DE
569#define mmBIF_BUSNUM_CNTL1 0x1525
570#define mmBIF_BUSNUM_CNTL2 0x152B
571#define mmBIF_BUSNUM_LIST0 0x1526
572#define mmBIF_BUSNUM_LIST1 0x1527
573#define mmBIF_BUSY_DELAY_CNTR 0x1529
574#define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F
575#define mmBIF_DEBUG_CNTL 0x151C
576#define mmBIF_DEBUG_MUX 0x151D
577#define mmBIF_DEBUG_OUT 0x151E
578#define mmBIF_DEVFUNCNUM_LIST0 0x14E8
579#define mmBIF_DEVFUNCNUM_LIST1 0x14E7
580#define mmBIF_FB_EN 0x1524
581#define mmBIF_FEATURES_CONTROL_MISC 0x14C2
582#define mmBIF_PERFCOUNTER0_RESULT 0x152D
583#define mmBIF_PERFCOUNTER1_RESULT 0x152E
584#define mmBIF_PERFMON_CNTL 0x152C
585#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F
586#define mmBIF_RESET_EN 0x1511
587#define mmBIF_SCRATCH0 0x150E
588#define mmBIF_SCRATCH1 0x150F
589#define mmBIF_SSA_DISP_LOWER 0x14D2
590#define mmBIF_SSA_DISP_UPPER 0x14D3
591#define mmBIF_SSA_GFX0_LOWER 0x14CA
592#define mmBIF_SSA_GFX0_UPPER 0x14CB
593#define mmBIF_SSA_GFX1_LOWER 0x14CC
594#define mmBIF_SSA_GFX1_UPPER 0x14CD
595#define mmBIF_SSA_GFX2_LOWER 0x14CE
596#define mmBIF_SSA_GFX2_UPPER 0x14CF
597#define mmBIF_SSA_GFX3_LOWER 0x14D0
598#define mmBIF_SSA_GFX3_UPPER 0x14D1
599#define mmBIF_SSA_MC_LOWER 0x14D4
600#define mmBIF_SSA_MC_UPPER 0x14D5
601#define mmBIF_SSA_PWR_STATUS 0x14C8
602#define mmBIF_XDMA_HI 0x14C1
603#define mmBIF_XDMA_LO 0x14C0
604#define mmBIOS_SCRATCH_0 0x05C9
605#define mmBIOS_SCRATCH_10 0x05D3
606#define mmBIOS_SCRATCH_1 0x05CA
607#define mmBIOS_SCRATCH_11 0x05D4
608#define mmBIOS_SCRATCH_12 0x05D5
609#define mmBIOS_SCRATCH_13 0x05D6
610#define mmBIOS_SCRATCH_14 0x05D7
611#define mmBIOS_SCRATCH_15 0x05D8
612#define mmBIOS_SCRATCH_2 0x05CB
613#define mmBIOS_SCRATCH_3 0x05CC
614#define mmBIOS_SCRATCH_4 0x05CD
615#define mmBIOS_SCRATCH_5 0x05CE
616#define mmBIOS_SCRATCH_6 0x05CF
617#define mmBIOS_SCRATCH_7 0x05D0
618#define mmBIOS_SCRATCH_8 0x05D1
619#define mmBIOS_SCRATCH_9 0x05D2
620#define mmBUS_CNTL 0x1508
621#define mmCAPTURE_HOST_BUSNUM 0x153C
622#define mmCLKREQB_PAD_CNTL 0x1521
623#define mmCONFIG_APER_SIZE 0x150C
624#define mmCONFIG_CNTL 0x1509
625#define mmCONFIG_F0_BASE 0x150B
626#define mmCONFIG_MEMSIZE 0x150A
627#define mmCONFIG_REG_APER_SIZE 0x150D
628#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
629#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
630#define mmHOST_BUSNUM 0x153D
631#define mmHW_DEBUG 0x1515
632#define mmIMPCTL_RESET 0x14F5
633#define mmINTERRUPT_CNTL 0x151A
634#define mmINTERRUPT_CNTL2 0x151B
635#define mmMASTER_CREDIT_CNTL 0x1516
636#define mmMM_CFGREGS_CNTL 0x1513
637#define mmMM_DATA 0x0001
638#define mmMM_INDEX 0x0000
639#define mmMM_INDEX_HI 0x0006
640#define mmNEW_REFCLKB_TIMER 0x14EA
641#define mmNEW_REFCLKB_TIMER_1 0x14E9
642#define mmPCIE_DATA 0x000D
643#define mmPCIE_INDEX 0x000C
644#define mmPEER0_FB_OFFSET_HI 0x14F3
645#define mmPEER0_FB_OFFSET_LO 0x14F2
646#define mmPEER1_FB_OFFSET_HI 0x14F1
647#define mmPEER1_FB_OFFSET_LO 0x14F0
648#define mmPEER2_FB_OFFSET_HI 0x14EF
649#define mmPEER2_FB_OFFSET_LO 0x14EE
650#define mmPEER3_FB_OFFSET_HI 0x14ED
651#define mmPEER3_FB_OFFSET_LO 0x14EC
652#define mmPEER_REG_RANGE0 0x153E
653#define mmPEER_REG_RANGE1 0x153F
654#define mmSLAVE_HANG_ERROR 0x153B
655#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
656#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
657#define mmSMBCLK_PAD_CNTL 0x1523
658#define mmSMBDAT_PAD_CNTL 0x1522
659#define mmSMBUS_BACO_DUMMY 0x14C6
660
661#endif
662