1/*
2 * BIF_4_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef BIF_4_1_D_H
25#define BIF_4_1_D_H
26
27#define mmMM_INDEX 0x0
28#define mmMM_INDEX_HI 0x6
29#define mmMM_DATA 0x1
30#define mmBUS_CNTL 0x1508
31#define mmCONFIG_CNTL 0x1509
32#define mmCONFIG_MEMSIZE 0x150a
33#define mmCONFIG_F0_BASE 0x150b
34#define mmCONFIG_APER_SIZE 0x150c
35#define mmCONFIG_REG_APER_SIZE 0x150d
36#define mmBIF_SCRATCH0 0x150e
37#define mmBIF_SCRATCH1 0x150f
38#define mmBX_RESET_EN 0x1514
39#define mmMM_CFGREGS_CNTL 0x1513
40#define mmHW_DEBUG 0x1515
41#define mmMASTER_CREDIT_CNTL 0x1516
42#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
43#define mmBX_RESET_CNTL 0x1518
44#define mmINTERRUPT_CNTL 0x151a
45#define mmINTERRUPT_CNTL2 0x151b
46#define mmBIF_DEBUG_CNTL 0x151c
47#define mmBIF_DEBUG_MUX 0x151d
48#define mmBIF_DEBUG_OUT 0x151e
49#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
50#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
51#define mmCLKREQB_PAD_CNTL 0x1521
52#define mmSMBUS_SLV_CNTL 0x14fd
53#define mmSMBUS_SLV_CNTL1 0x14fe
54#define mmSMBDAT_PAD_CNTL 0x1522
55#define mmSMBCLK_PAD_CNTL 0x1523
56#define mmBIF_XDMA_LO 0x14c0
57#define mmBIF_XDMA_HI 0x14c1
58#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
59#define mmBIF_DOORBELL_CNTL 0x14c3
60#define mmBIF_SLVARB_MODE 0x14c4
61#define mmBIF_FB_EN 0x1524
62#define mmBIF_BUSNUM_CNTL1 0x1525
63#define mmBIF_BUSNUM_LIST0 0x1526
64#define mmBIF_BUSNUM_LIST1 0x1527
65#define mmBIF_BUSNUM_CNTL2 0x152b
66#define mmBIF_BUSY_DELAY_CNTR 0x1529
67#define mmBIF_PERFMON_CNTL 0x152c
68#define mmBIF_PERFCOUNTER0_RESULT 0x152d
69#define mmBIF_PERFCOUNTER1_RESULT 0x152e
70#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
71#define mmGPU_HDP_FLUSH_REQ 0x1537
72#define mmGPU_HDP_FLUSH_DONE 0x1538
73#define mmSLAVE_HANG_ERROR 0x153b
74#define mmCAPTURE_HOST_BUSNUM 0x153c
75#define mmHOST_BUSNUM 0x153d
76#define mmPEER_REG_RANGE0 0x153e
77#define mmPEER_REG_RANGE1 0x153f
78#define mmPEER0_FB_OFFSET_HI 0x14f3
79#define mmPEER0_FB_OFFSET_LO 0x14f2
80#define mmPEER1_FB_OFFSET_HI 0x14f1
81#define mmPEER1_FB_OFFSET_LO 0x14f0
82#define mmPEER2_FB_OFFSET_HI 0x14ef
83#define mmPEER2_FB_OFFSET_LO 0x14ee
84#define mmPEER3_FB_OFFSET_HI 0x14ed
85#define mmPEER3_FB_OFFSET_LO 0x14ec
86#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
87#define mmSMBUS_BACO_DUMMY 0x14c6
88#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
89#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
90#define mmBACO_CNTL 0x14e5
91#define mmBF_ANA_ISO_CNTL 0x14c7
92#define mmMEM_TYPE_CNTL 0x14e4
93#define mmBIF_BACO_DEBUG 0x14df
94#define mmBIF_BACO_DEBUG_LATCH 0x14dc
95#define mmBACO_CNTL_MISC 0x14db
96#define mmBIF_SSA_PWR_STATUS 0x14c8
97#define mmBIF_SSA_GFX0_LOWER 0x14ca
98#define mmBIF_SSA_GFX0_UPPER 0x14cb
99#define mmBIF_SSA_GFX1_LOWER 0x14cc
100#define mmBIF_SSA_GFX1_UPPER 0x14cd
101#define mmBIF_SSA_GFX2_LOWER 0x14ce
102#define mmBIF_SSA_GFX2_UPPER 0x14cf
103#define mmBIF_SSA_GFX3_LOWER 0x14d0
104#define mmBIF_SSA_GFX3_UPPER 0x14d1
105#define mmBIF_SSA_DISP_LOWER 0x14d2
106#define mmBIF_SSA_DISP_UPPER 0x14d3
107#define mmBIF_SSA_MC_LOWER 0x14d4
108#define mmBIF_SSA_MC_UPPER 0x14d5
109#define mmIMPCTL_RESET 0x14f5
110#define mmGARLIC_FLUSH_CNTL 0x1401
111#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
112#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
113#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
114#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
115#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
116#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
117#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
118#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
119#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
120#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
121#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
122#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
123#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
124#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
125#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
126#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
127#define mmGARLIC_FLUSH_REQ 0x1412
128#define mmGPU_GARLIC_FLUSH_REQ 0x1413
129#define mmGPU_GARLIC_FLUSH_DONE 0x1414
130#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415
131#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416
132#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417
133#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418
134#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419
135#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a
136#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b
137#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c
138#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d
139#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e
140#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f
141#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420
142#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421
143#define mmBIOS_SCRATCH_0 0x5c9
144#define mmBIOS_SCRATCH_1 0x5ca
145#define mmBIOS_SCRATCH_2 0x5cb
146#define mmBIOS_SCRATCH_3 0x5cc
147#define mmBIOS_SCRATCH_4 0x5cd
148#define mmBIOS_SCRATCH_5 0x5ce
149#define mmBIOS_SCRATCH_6 0x5cf
150#define mmBIOS_SCRATCH_7 0x5d0
151#define mmBIOS_SCRATCH_8 0x5d1
152#define mmBIOS_SCRATCH_9 0x5d2
153#define mmBIOS_SCRATCH_10 0x5d3
154#define mmBIOS_SCRATCH_11 0x5d4
155#define mmBIOS_SCRATCH_12 0x5d5
156#define mmBIOS_SCRATCH_13 0x5d6
157#define mmBIOS_SCRATCH_14 0x5d7
158#define mmBIOS_SCRATCH_15 0x5d8
159#define mmVENDOR_ID 0x0
160#define mmDEVICE_ID 0x0
161#define mmCOMMAND 0x1
162#define mmSTATUS 0x1
163#define mmREVISION_ID 0x2
164#define mmPROG_INTERFACE 0x2
165#define mmSUB_CLASS 0x2
166#define mmBASE_CLASS 0x2
167#define mmCACHE_LINE 0x3
168#define mmLATENCY 0x3
169#define mmHEADER 0x3
170#define mmBIST 0x3
171#define mmBASE_ADDR_1 0x4
172#define mmBASE_ADDR_2 0x5
173#define mmBASE_ADDR_3 0x6
174#define mmBASE_ADDR_4 0x7
175#define mmBASE_ADDR_5 0x8
176#define mmBASE_ADDR_6 0x9
177#define mmROM_BASE_ADDR 0xc
178#define mmCAP_PTR 0xd
179#define mmINTERRUPT_LINE 0xf
180#define mmINTERRUPT_PIN 0xf
181#define mmADAPTER_ID 0xb
182#define mmMIN_GRANT 0xf
183#define mmMAX_LATENCY 0xf
184#define mmVENDOR_CAP_LIST 0x12
185#define mmADAPTER_ID_W 0x13
186#define mmPMI_CAP_LIST 0x14
187#define mmPMI_CAP 0x14
188#define mmPMI_STATUS_CNTL 0x15
189#define mmPCIE_CAP_LIST 0x16
190#define mmPCIE_CAP 0x16
191#define mmDEVICE_CAP 0x17
192#define mmDEVICE_CNTL 0x18
193#define mmDEVICE_STATUS 0x18
194#define mmLINK_CAP 0x19
195#define mmLINK_CNTL 0x1a
196#define mmLINK_STATUS 0x1a
197#define mmDEVICE_CAP2 0x1f
198#define mmDEVICE_CNTL2 0x20
199#define mmDEVICE_STATUS2 0x20
200#define mmLINK_CAP2 0x21
201#define mmLINK_CNTL2 0x22
202#define mmLINK_STATUS2 0x22
203#define mmMSI_CAP_LIST 0x28
204#define mmMSI_MSG_CNTL 0x28
205#define mmMSI_MSG_ADDR_LO 0x29
206#define mmMSI_MSG_ADDR_HI 0x2a
207#define mmMSI_MSG_DATA_64 0x2b
208#define mmMSI_MSG_DATA 0x2a
209#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
210#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
211#define mmPCIE_VENDOR_SPECIFIC1 0x42
212#define mmPCIE_VENDOR_SPECIFIC2 0x43
213#define mmPCIE_VC_ENH_CAP_LIST 0x44
214#define mmPCIE_PORT_VC_CAP_REG1 0x45
215#define mmPCIE_PORT_VC_CAP_REG2 0x46
216#define mmPCIE_PORT_VC_CNTL 0x47
217#define mmPCIE_PORT_VC_STATUS 0x47
218#define mmPCIE_VC0_RESOURCE_CAP 0x48
219#define mmPCIE_VC0_RESOURCE_CNTL 0x49
220#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
221#define mmPCIE_VC1_RESOURCE_CAP 0x4b
222#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
223#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
224#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
225#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
226#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
227#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
228#define mmPCIE_UNCORR_ERR_STATUS 0x55
229#define mmPCIE_UNCORR_ERR_MASK 0x56
230#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
231#define mmPCIE_CORR_ERR_STATUS 0x58
232#define mmPCIE_CORR_ERR_MASK 0x59
233#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
234#define mmPCIE_HDR_LOG0 0x5b
235#define mmPCIE_HDR_LOG1 0x5c
236#define mmPCIE_HDR_LOG2 0x5d
237#define mmPCIE_HDR_LOG3 0x5e
238#define mmPCIE_TLP_PREFIX_LOG0 0x62
239#define mmPCIE_TLP_PREFIX_LOG1 0x63
240#define mmPCIE_TLP_PREFIX_LOG2 0x64
241#define mmPCIE_TLP_PREFIX_LOG3 0x65
242#define mmPCIE_BAR_ENH_CAP_LIST 0x80
243#define mmPCIE_BAR1_CAP 0x81
244#define mmPCIE_BAR1_CNTL 0x82
245#define mmPCIE_BAR2_CAP 0x83
246#define mmPCIE_BAR2_CNTL 0x84
247#define mmPCIE_BAR3_CAP 0x85
248#define mmPCIE_BAR3_CNTL 0x86
249#define mmPCIE_BAR4_CAP 0x87
250#define mmPCIE_BAR4_CNTL 0x88
251#define mmPCIE_BAR5_CAP 0x89
252#define mmPCIE_BAR5_CNTL 0x8a
253#define mmPCIE_BAR6_CAP 0x8b
254#define mmPCIE_BAR6_CNTL 0x8c
255#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
256#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
257#define mmPCIE_PWR_BUDGET_DATA 0x92
258#define mmPCIE_PWR_BUDGET_CAP 0x93
259#define mmPCIE_DPA_ENH_CAP_LIST 0x94
260#define mmPCIE_DPA_CAP 0x95
261#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
262#define mmPCIE_DPA_STATUS 0x97
263#define mmPCIE_DPA_CNTL 0x97
264#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
265#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
266#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
267#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
268#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
269#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
270#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
271#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
272#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
273#define mmPCIE_LINK_CNTL3 0x9d
274#define mmPCIE_LANE_ERROR_STATUS 0x9e
275#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
276#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
277#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
278#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
279#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
280#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
281#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
282#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
283#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
284#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
285#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
286#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
287#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
288#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
289#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
290#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
291#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
292#define mmPCIE_ACS_CAP 0xa9
293#define mmPCIE_ACS_CNTL 0xa9
294#define mmPCIE_ATS_ENH_CAP_LIST 0xac
295#define mmPCIE_ATS_CAP 0xad
296#define mmPCIE_ATS_CNTL 0xad
297#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
298#define mmPCIE_PAGE_REQ_CNTL 0xb1
299#define mmPCIE_PAGE_REQ_STATUS 0xb1
300#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
301#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
302#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
303#define mmPCIE_PASID_CAP 0xb5
304#define mmPCIE_PASID_CNTL 0xb5
305#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
306#define mmPCIE_TPH_REQR_CAP 0xb9
307#define mmPCIE_TPH_REQR_CNTL 0xba
308#define mmPCIE_MC_ENH_CAP_LIST 0xbc
309#define mmPCIE_MC_CAP 0xbd
310#define mmPCIE_MC_CNTL 0xbd
311#define mmPCIE_MC_ADDR0 0xbe
312#define mmPCIE_MC_ADDR1 0xbf
313#define mmPCIE_MC_RCV0 0xc0
314#define mmPCIE_MC_RCV1 0xc1
315#define mmPCIE_MC_BLOCK_ALL0 0xc2
316#define mmPCIE_MC_BLOCK_ALL1 0xc3
317#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
318#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
319#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
320#define mmPCIE_LTR_CAP 0xc9
321#define mmPCIE_INDEX 0xe
322#define mmPCIE_DATA 0xf
323#define mmPCIE_INDEX_2 0xc
324#define mmPCIE_DATA_2 0xd
325#define ixPCIE_RESERVED 0x1400000
326#define ixPCIE_SCRATCH 0x1400001
327#define ixPCIE_HW_DEBUG 0x1400002
328#define ixPCIE_RX_NUM_NAK 0x140000e
329#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
330#define ixPCIE_CNTL 0x1400010
331#define ixPCIE_CONFIG_CNTL 0x1400011
332#define ixPCIE_DEBUG_CNTL 0x1400012
333#define ixPCIE_INT_CNTL 0x140001a
334#define ixPCIE_INT_STATUS 0x140001b
335#define ixPCIE_CNTL2 0x140001c
336#define ixPCIE_RX_CNTL2 0x140001d
337#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
338#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
339#define ixPCIE_CI_CNTL 0x1400020
340#define ixPCIE_BUS_CNTL 0x1400021
341#define ixPCIE_LC_STATE6 0x1400022
342#define ixPCIE_LC_STATE7 0x1400023
343#define ixPCIE_LC_STATE8 0x1400024
344#define ixPCIE_LC_STATE9 0x1400025
345#define ixPCIE_LC_STATE10 0x1400026
346#define ixPCIE_LC_STATE11 0x1400027
347#define ixPCIE_LC_STATUS1 0x1400028
348#define ixPCIE_LC_STATUS2 0x1400029
349#define ixPCIE_WPR_CNTL 0x1400030
350#define ixPCIE_RX_LAST_TLP0 0x1400031
351#define ixPCIE_RX_LAST_TLP1 0x1400032
352#define ixPCIE_RX_LAST_TLP2 0x1400033
353#define ixPCIE_RX_LAST_TLP3 0x1400034
354#define ixPCIE_TX_LAST_TLP0 0x1400035
355#define ixPCIE_TX_LAST_TLP1 0x1400036
356#define ixPCIE_TX_LAST_TLP2 0x1400037
357#define ixPCIE_TX_LAST_TLP3 0x1400038
358#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
359#define ixPCIE_I2C_REG_DATA 0x140003b
360#define ixPCIE_CFG_CNTL 0x140003c
361#define ixPCIE_P_CNTL 0x1400040
362#define ixPCIE_P_BUF_STATUS 0x1400041
363#define ixPCIE_P_DECODER_STATUS 0x1400042
364#define ixPCIE_P_MISC_STATUS 0x1400043
365#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
366#define ixPCIE_OBFF_CNTL 0x1400061
367#define ixPCIE_TX_LTR_CNTL 0x1400060
368#define ixPCIE_PERF_COUNT_CNTL 0x1400080
369#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
370#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
371#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
372#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
373#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
374#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
375#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
376#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
377#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
378#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
379#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
380#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
381#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
382#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
383#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
384#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
385#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
386#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
387#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
388#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
389#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
390#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
391#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
392#define ixPCIE_STRAP_F0 0x14000b0
393#define ixPCIE_STRAP_F1 0x14000b1
394#define ixPCIE_STRAP_F2 0x14000b2
395#define ixPCIE_STRAP_F3 0x14000b3
396#define ixPCIE_STRAP_F4 0x14000b4
397#define ixPCIE_STRAP_F5 0x14000b5
398#define ixPCIE_STRAP_F6 0x14000b6
399#define ixPCIE_STRAP_F7 0x14000b7
400#define ixPCIE_STRAP_MISC 0x14000c0
401#define ixPCIE_STRAP_MISC2 0x14000c1
402#define ixPCIE_STRAP_PI 0x14000c2
403#define ixPCIE_STRAP_I2C_BD 0x14000c4
404#define ixPCIE_PRBS_CLR 0x14000c8
405#define ixPCIE_PRBS_STATUS1 0x14000c9
406#define ixPCIE_PRBS_STATUS2 0x14000ca
407#define ixPCIE_PRBS_FREERUN 0x14000cb
408#define ixPCIE_PRBS_MISC 0x14000cc
409#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
410#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
411#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
412#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
413#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
414#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
415#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
416#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
417#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
418#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
419#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
420#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
421#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
422#define ixPCIE_PRBS_ERRCNT_10 0x14000da
423#define ixPCIE_PRBS_ERRCNT_11 0x14000db
424#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
425#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
426#define ixPCIE_PRBS_ERRCNT_14 0x14000de
427#define ixPCIE_PRBS_ERRCNT_15 0x14000df
428#define ixPCIE_F0_DPA_CAP 0x14000e0
429#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
430#define ixPCIE_F0_DPA_CNTL 0x14000e5
431#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
432#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
433#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
434#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
435#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
436#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
437#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
438#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
439#define ixPCIEP_RESERVED 0x10010000
440#define ixPCIEP_SCRATCH 0x10010001
441#define ixPCIEP_HW_DEBUG 0x10010002
442#define ixPCIEP_PORT_CNTL 0x10010010
443#define ixPCIE_TX_CNTL 0x10010020
444#define ixPCIE_TX_REQUESTER_ID 0x10010021
445#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
446#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
447#define ixPCIE_TX_SEQ 0x10010024
448#define ixPCIE_TX_REPLAY 0x10010025
449#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
450#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
451#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
452#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
453#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
454#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
455#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
456#define ixPCIE_TX_CREDITS_STATUS 0x10010036
457#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
458#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
459#define ixPCIE_FC_P 0x10010060
460#define ixPCIE_FC_NP 0x10010061
461#define ixPCIE_FC_CPL 0x10010062
462#define ixPCIE_ERR_CNTL 0x1001006a
463#define ixPCIE_RX_CNTL 0x10010070
464#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
465#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
466#define ixPCIE_RX_CNTL3 0x10010074
467#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
468#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
469#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
470#define ixPCIE_LC_CNTL 0x100100a0
471#define ixPCIE_LC_CNTL2 0x100100b1
472#define ixPCIE_LC_CNTL3 0x100100b5
473#define ixPCIE_LC_CNTL4 0x100100b6
474#define ixPCIE_LC_CNTL5 0x100100b7
475#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
476#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
477#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
478#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
479#define ixPCIE_LC_SPEED_CNTL 0x100100a4
480#define ixPCIE_LC_CDR_CNTL 0x100100b3
481#define ixPCIE_LC_LANE_CNTL 0x100100b4
482#define ixPCIE_LC_FORCE_COEFF 0x100100b8
483#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
484#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
485#define ixPCIE_LC_STATE0 0x100100a5
486#define ixPCIE_LC_STATE1 0x100100a6
487#define ixPCIE_LC_STATE2 0x100100a7
488#define ixPCIE_LC_STATE3 0x100100a8
489#define ixPCIE_LC_STATE4 0x100100a9
490#define ixPCIE_LC_STATE5 0x100100aa
491#define ixPCIEP_STRAP_LC 0x100100c0
492#define ixPCIEP_STRAP_MISC 0x100100c1
493#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
494#define ixPB0_GLB_CTRL_REG0 0x1200004
495#define ixPB0_GLB_CTRL_REG1 0x1200008
496#define ixPB0_GLB_CTRL_REG2 0x120000c
497#define ixPB0_GLB_CTRL_REG3 0x1200010
498#define ixPB0_GLB_CTRL_REG4 0x1200014
499#define ixPB0_GLB_CTRL_REG5 0x1200018
500#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
501#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
502#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
503#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
504#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
505#define ixPB0_GLB_OVRD_REG0 0x1200030
506#define ixPB0_GLB_OVRD_REG1 0x1200034
507#define ixPB0_GLB_OVRD_REG2 0x1200038
508#define ixPB0_HW_DEBUG 0x1202004
509#define ixPB0_STRAP_GLB_REG0 0x1202020
510#define ixPB0_STRAP_TX_REG0 0x1202024
511#define ixPB0_STRAP_RX_REG0 0x1202028
512#define ixPB0_STRAP_RX_REG1 0x120202c
513#define ixPB0_STRAP_PLL_REG0 0x1202030
514#define ixPB0_STRAP_PIN_REG0 0x1202034
515#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
516#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
517#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
518#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
519#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
520#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
521#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
522#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
523#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
524#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
525#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
526#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
527#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
528#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
529#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
530#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
531#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
532#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
533#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
534#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
535#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
536#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
537#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
538#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
539#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
540#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
541#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
542#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
543#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
544#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
545#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
546#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
547#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
548#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
549#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
550#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
551#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
552#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
553#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
554#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
555#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
556#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
557#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
558#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
559#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
560#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
561#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
562#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
563#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
564#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
565#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
566#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
567#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
568#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
569#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
570#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
571#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
572#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
573#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
574#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
575#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
576#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
577#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
578#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
579#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
580#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
581#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
582#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
583#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
584#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
585#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
586#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
587#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
588#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
589#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
590#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
591#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
592#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
593#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
594#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
595#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
596#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
597#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
598#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
599#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
600#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
601#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
602#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
603#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
604#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
605#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
606#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
607#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
608#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
609#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
610#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
611#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
612#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
613#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
614#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
615#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
616#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
617#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
618#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
619#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
620#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
621#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
622#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
623#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
624#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
625#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
626#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
627#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
628#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
629#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
630#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
631#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
632#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
633#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
634#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
635#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
636#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
637#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
638#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
639#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
640#define ixPB1_GLB_CTRL_REG0 0x2200004
641#define ixPB1_GLB_CTRL_REG1 0x2200008
642#define ixPB1_GLB_CTRL_REG2 0x220000c
643#define ixPB1_GLB_CTRL_REG3 0x2200010
644#define ixPB1_GLB_CTRL_REG4 0x2200014
645#define ixPB1_GLB_CTRL_REG5 0x2200018
646#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
647#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
648#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
649#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
650#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
651#define ixPB1_GLB_OVRD_REG0 0x2200030
652#define ixPB1_GLB_OVRD_REG1 0x2200034
653#define ixPB1_GLB_OVRD_REG2 0x2200038
654#define ixPB1_HW_DEBUG 0x2202004
655#define ixPB1_STRAP_GLB_REG0 0x2202020
656#define ixPB1_STRAP_TX_REG0 0x2202024
657#define ixPB1_STRAP_RX_REG0 0x2202028
658#define ixPB1_STRAP_RX_REG1 0x220202c
659#define ixPB1_STRAP_PLL_REG0 0x2202030
660#define ixPB1_STRAP_PIN_REG0 0x2202034
661#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
662#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
663#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
664#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
665#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
666#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
667#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
668#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
669#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
670#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
671#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
672#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
673#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
674#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
675#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
676#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
677#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
678#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
679#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
680#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
681#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
682#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
683#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
684#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
685#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
686#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
687#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
688#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
689#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
690#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
691#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
692#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
693#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
694#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
695#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
696#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
697#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
698#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
699#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
700#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
701#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
702#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
703#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
704#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
705#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
706#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
707#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
708#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
709#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
710#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
711#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
712#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
713#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
714#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
715#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
716#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
717#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
718#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
719#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
720#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
721#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
722#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
723#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
724#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
725#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
726#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
727#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
728#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
729#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
730#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
731#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
732#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
733#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
734#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
735#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
736#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
737#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
738#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
739#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
740#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
741#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
742#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
743#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
744#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
745#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
746#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
747#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
748#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
749#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
750#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
751#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
752#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
753#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
754#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
755#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
756#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
757#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
758#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
759#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
760#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
761#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
762#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
763#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
764#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
765#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
766#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
767#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
768#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
769#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
770#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
771#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
772#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
773#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
774#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
775#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
776#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
777#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
778#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
779#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
780#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
781#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
782#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
783#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
784#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
785#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
786#define ixPB0_PIF_SCRATCH 0x1100001
787#define ixPB0_PIF_HW_DEBUG 0x1100002
788#define ixPB0_PIF_PRG6 0x1100003
789#define ixPB0_PIF_PRG7 0x1100004
790#define ixPB0_PIF_CNTL 0x1100010
791#define ixPB0_PIF_PAIRING 0x1100011
792#define ixPB0_PIF_PWRDOWN_0 0x1100012
793#define ixPB0_PIF_PWRDOWN_1 0x1100013
794#define ixPB0_PIF_CNTL2 0x1100014
795#define ixPB0_PIF_TXPHYSTATUS 0x1100015
796#define ixPB0_PIF_SC_CTL 0x1100016
797#define ixPB0_PIF_PWRDOWN_2 0x1100017
798#define ixPB0_PIF_PWRDOWN_3 0x1100018
799#define ixPB0_PIF_SC_CTL2 0x1100019
800#define ixPB0_PIF_PRG0 0x110001a
801#define ixPB0_PIF_PRG1 0x110001b
802#define ixPB0_PIF_PRG2 0x110001c
803#define ixPB0_PIF_PRG3 0x110001d
804#define ixPB0_PIF_PRG4 0x110001e
805#define ixPB0_PIF_PRG5 0x110001f
806#define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020
807#define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021
808#define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022
809#define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023
810#define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024
811#define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025
812#define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026
813#define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027
814#define ixPB0_PIF_SEQ_STATUS_0 0x1100028
815#define ixPB0_PIF_SEQ_STATUS_1 0x1100029
816#define ixPB0_PIF_SEQ_STATUS_2 0x110002a
817#define ixPB0_PIF_SEQ_STATUS_3 0x110002b
818#define ixPB0_PIF_SEQ_STATUS_4 0x110002c
819#define ixPB0_PIF_SEQ_STATUS_5 0x110002d
820#define ixPB0_PIF_SEQ_STATUS_6 0x110002e
821#define ixPB0_PIF_SEQ_STATUS_7 0x110002f
822#define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030
823#define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031
824#define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032
825#define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033
826#define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034
827#define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035
828#define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036
829#define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037
830#define ixPB0_PIF_SEQ_STATUS_8 0x1100038
831#define ixPB0_PIF_SEQ_STATUS_9 0x1100039
832#define ixPB0_PIF_SEQ_STATUS_10 0x110003a
833#define ixPB0_PIF_SEQ_STATUS_11 0x110003b
834#define ixPB0_PIF_SEQ_STATUS_12 0x110003c
835#define ixPB0_PIF_SEQ_STATUS_13 0x110003d
836#define ixPB0_PIF_SEQ_STATUS_14 0x110003e
837#define ixPB0_PIF_SEQ_STATUS_15 0x110003f
838#define ixPB1_PIF_SCRATCH 0x2100001
839#define ixPB1_PIF_HW_DEBUG 0x2100002
840#define ixPB1_PIF_PRG6 0x2100003
841#define ixPB1_PIF_PRG7 0x2100004
842#define ixPB1_PIF_CNTL 0x2100010
843#define ixPB1_PIF_PAIRING 0x2100011
844#define ixPB1_PIF_PWRDOWN_0 0x2100012
845#define ixPB1_PIF_PWRDOWN_1 0x2100013
846#define ixPB1_PIF_CNTL2 0x2100014
847#define ixPB1_PIF_TXPHYSTATUS 0x2100015
848#define ixPB1_PIF_SC_CTL 0x2100016
849#define ixPB1_PIF_PWRDOWN_2 0x2100017
850#define ixPB1_PIF_PWRDOWN_3 0x2100018
851#define ixPB1_PIF_SC_CTL2 0x2100019
852#define ixPB1_PIF_PRG0 0x210001a
853#define ixPB1_PIF_PRG1 0x210001b
854#define ixPB1_PIF_PRG2 0x210001c
855#define ixPB1_PIF_PRG3 0x210001d
856#define ixPB1_PIF_PRG4 0x210001e
857#define ixPB1_PIF_PRG5 0x210001f
858#define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020
859#define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021
860#define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022
861#define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023
862#define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024
863#define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025
864#define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026
865#define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027
866#define ixPB1_PIF_SEQ_STATUS_0 0x2100028
867#define ixPB1_PIF_SEQ_STATUS_1 0x2100029
868#define ixPB1_PIF_SEQ_STATUS_2 0x210002a
869#define ixPB1_PIF_SEQ_STATUS_3 0x210002b
870#define ixPB1_PIF_SEQ_STATUS_4 0x210002c
871#define ixPB1_PIF_SEQ_STATUS_5 0x210002d
872#define ixPB1_PIF_SEQ_STATUS_6 0x210002e
873#define ixPB1_PIF_SEQ_STATUS_7 0x210002f
874#define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030
875#define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031
876#define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032
877#define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033
878#define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034
879#define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035
880#define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036
881#define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037
882#define ixPB1_PIF_SEQ_STATUS_8 0x2100038
883#define ixPB1_PIF_SEQ_STATUS_9 0x2100039
884#define ixPB1_PIF_SEQ_STATUS_10 0x210003a
885#define ixPB1_PIF_SEQ_STATUS_11 0x210003b
886#define ixPB1_PIF_SEQ_STATUS_12 0x210003c
887#define ixPB1_PIF_SEQ_STATUS_13 0x210003d
888#define ixPB1_PIF_SEQ_STATUS_14 0x210003e
889#define ixPB1_PIF_SEQ_STATUS_15 0x210003f
890#define mmBIF_RFE_SNOOP_REG 0x27
891#define mmBIF_RFE_WARMRST_CNTL 0x1459
892#define mmBIF_RFE_SOFTRST_CNTL 0x1441
893#define mmBIF_RFE_IMPRST_CNTL 0x1458
894#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
895#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
896#define mmBIF_PWDN_COMMAND 0x1444
897#define mmBIF_PWDN_STATUS 0x1445
898#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
899#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
900#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448
901#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
902#define mmBIF_RFE_MMCFG_CNTL 0x144c
903#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
904#define mmBIF_IMPCTL_SMPLCNTL 0x1450
905#define mmBIF_IMPCTL_RXCNTL 0x1451
906#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
907#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
908#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
909#define mmBIF_CLOCKS_BITS 0x1489
910#define mmBIF_LNCNT_RESET 0x1488
911#define mmLNCNT_CONTROL 0x1487
912#define mmNEW_REFCLKB_TIMER 0x1485
913#define mmNEW_REFCLKB_TIMER_1 0x1484
914#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483
915#define mmBIF_RESET_EN 0x1482
916#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481
917#define mmBIF_BACO_MSIC 0x1480
918#define mmBIF_RESET_CNTL 0x1486
919#define mmBIF_RFE_CNTL_MISC 0x148c
920
921#endif /* BIF_4_1_D_H */
922