1/*
2 * BIF_4_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef BIF_4_1_D_H
25#define BIF_4_1_D_H
26
27#define mmMM_INDEX 0x0
28#define mmMM_INDEX_HI 0x6
29#define mmMM_DATA 0x1
30#define mmCC_BIF_BX_FUSESTRAP0 0x14D7
31#define mmBUS_CNTL 0x1508
32#define mmCONFIG_CNTL 0x1509
33#define mmCONFIG_MEMSIZE 0x150a
34#define mmCONFIG_F0_BASE 0x150b
35#define mmCONFIG_APER_SIZE 0x150c
36#define mmCONFIG_REG_APER_SIZE 0x150d
37#define mmBIF_SCRATCH0 0x150e
38#define mmBIF_SCRATCH1 0x150f
39#define mmBX_RESET_EN 0x1514
40#define mmMM_CFGREGS_CNTL 0x1513
41#define mmHW_DEBUG 0x1515
42#define mmMASTER_CREDIT_CNTL 0x1516
43#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
44#define mmBX_RESET_CNTL 0x1518
45#define mmINTERRUPT_CNTL 0x151a
46#define mmINTERRUPT_CNTL2 0x151b
47#define mmBIF_DEBUG_CNTL 0x151c
48#define mmBIF_DEBUG_MUX 0x151d
49#define mmBIF_DEBUG_OUT 0x151e
50#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
51#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
52#define mmCLKREQB_PAD_CNTL 0x1521
53#define mmSMBUS_SLV_CNTL 0x14fd
54#define mmSMBUS_SLV_CNTL1 0x14fe
55#define mmSMBDAT_PAD_CNTL 0x1522
56#define mmSMBCLK_PAD_CNTL 0x1523
57#define mmBIF_XDMA_LO 0x14c0
58#define mmBIF_XDMA_HI 0x14c1
59#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
60#define mmBIF_DOORBELL_CNTL 0x14c3
61#define mmBIF_SLVARB_MODE 0x14c4
62#define mmBIF_FB_EN 0x1524
63#define mmBIF_BUSNUM_CNTL1 0x1525
64#define mmBIF_BUSNUM_LIST0 0x1526
65#define mmBIF_BUSNUM_LIST1 0x1527
66#define mmBIF_BUSNUM_CNTL2 0x152b
67#define mmBIF_BUSY_DELAY_CNTR 0x1529
68#define mmBIF_PERFMON_CNTL 0x152c
69#define mmBIF_PERFCOUNTER0_RESULT 0x152d
70#define mmBIF_PERFCOUNTER1_RESULT 0x152e
71#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
72#define mmGPU_HDP_FLUSH_REQ 0x1537
73#define mmGPU_HDP_FLUSH_DONE 0x1538
74#define mmSLAVE_HANG_ERROR 0x153b
75#define mmCAPTURE_HOST_BUSNUM 0x153c
76#define mmHOST_BUSNUM 0x153d
77#define mmPEER_REG_RANGE0 0x153e
78#define mmPEER_REG_RANGE1 0x153f
79#define mmPEER0_FB_OFFSET_HI 0x14f3
80#define mmPEER0_FB_OFFSET_LO 0x14f2
81#define mmPEER1_FB_OFFSET_HI 0x14f1
82#define mmPEER1_FB_OFFSET_LO 0x14f0
83#define mmPEER2_FB_OFFSET_HI 0x14ef
84#define mmPEER2_FB_OFFSET_LO 0x14ee
85#define mmPEER3_FB_OFFSET_HI 0x14ed
86#define mmPEER3_FB_OFFSET_LO 0x14ec
87#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
88#define mmSMBUS_BACO_DUMMY 0x14c6
89#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
90#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
91#define mmBACO_CNTL 0x14e5
92#define mmBF_ANA_ISO_CNTL 0x14c7
93#define mmMEM_TYPE_CNTL 0x14e4
94#define mmBIF_BACO_DEBUG 0x14df
95#define mmBIF_BACO_DEBUG_LATCH 0x14dc
96#define mmBACO_CNTL_MISC 0x14db
97#define mmBIF_SSA_PWR_STATUS 0x14c8
98#define mmBIF_SSA_GFX0_LOWER 0x14ca
99#define mmBIF_SSA_GFX0_UPPER 0x14cb
100#define mmBIF_SSA_GFX1_LOWER 0x14cc
101#define mmBIF_SSA_GFX1_UPPER 0x14cd
102#define mmBIF_SSA_GFX2_LOWER 0x14ce
103#define mmBIF_SSA_GFX2_UPPER 0x14cf
104#define mmBIF_SSA_GFX3_LOWER 0x14d0
105#define mmBIF_SSA_GFX3_UPPER 0x14d1
106#define mmBIF_SSA_DISP_LOWER 0x14d2
107#define mmBIF_SSA_DISP_UPPER 0x14d3
108#define mmBIF_SSA_MC_LOWER 0x14d4
109#define mmBIF_SSA_MC_UPPER 0x14d5
110#define mmIMPCTL_RESET 0x14f5
111#define mmGARLIC_FLUSH_CNTL 0x1401
112#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
113#define mmGARLIC_FLUSH_ADDR_START_1 0x1404
114#define mmGARLIC_FLUSH_ADDR_START_2 0x1406
115#define mmGARLIC_FLUSH_ADDR_START_3 0x1408
116#define mmGARLIC_FLUSH_ADDR_START_4 0x140a
117#define mmGARLIC_FLUSH_ADDR_START_5 0x140c
118#define mmGARLIC_FLUSH_ADDR_START_6 0x140e
119#define mmGARLIC_FLUSH_ADDR_START_7 0x1410
120#define mmGARLIC_FLUSH_ADDR_END_0 0x1403
121#define mmGARLIC_FLUSH_ADDR_END_1 0x1405
122#define mmGARLIC_FLUSH_ADDR_END_2 0x1407
123#define mmGARLIC_FLUSH_ADDR_END_3 0x1409
124#define mmGARLIC_FLUSH_ADDR_END_4 0x140b
125#define mmGARLIC_FLUSH_ADDR_END_5 0x140d
126#define mmGARLIC_FLUSH_ADDR_END_6 0x140f
127#define mmGARLIC_FLUSH_ADDR_END_7 0x1411
128#define mmGARLIC_FLUSH_REQ 0x1412
129#define mmGPU_GARLIC_FLUSH_REQ 0x1413
130#define mmGPU_GARLIC_FLUSH_DONE 0x1414
131#define mmGARLIC_COHE_CP_RB0_WPTR 0x1415
132#define mmGARLIC_COHE_CP_RB1_WPTR 0x1416
133#define mmGARLIC_COHE_CP_RB2_WPTR 0x1417
134#define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418
135#define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419
136#define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a
137#define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b
138#define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c
139#define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d
140#define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e
141#define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f
142#define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420
143#define mmGARLIC_COHE_VCE_RB_WPTR 0x1421
144#define mmBIOS_SCRATCH_0 0x5c9
145#define mmBIOS_SCRATCH_1 0x5ca
146#define mmBIOS_SCRATCH_2 0x5cb
147#define mmBIOS_SCRATCH_3 0x5cc
148#define mmBIOS_SCRATCH_4 0x5cd
149#define mmBIOS_SCRATCH_5 0x5ce
150#define mmBIOS_SCRATCH_6 0x5cf
151#define mmBIOS_SCRATCH_7 0x5d0
152#define mmBIOS_SCRATCH_8 0x5d1
153#define mmBIOS_SCRATCH_9 0x5d2
154#define mmBIOS_SCRATCH_10 0x5d3
155#define mmBIOS_SCRATCH_11 0x5d4
156#define mmBIOS_SCRATCH_12 0x5d5
157#define mmBIOS_SCRATCH_13 0x5d6
158#define mmBIOS_SCRATCH_14 0x5d7
159#define mmBIOS_SCRATCH_15 0x5d8
160#define mmVENDOR_ID 0x0
161#define mmDEVICE_ID 0x0
162#define mmCOMMAND 0x1
163#define mmSTATUS 0x1
164#define mmREVISION_ID 0x2
165#define mmPROG_INTERFACE 0x2
166#define mmSUB_CLASS 0x2
167#define mmBASE_CLASS 0x2
168#define mmCACHE_LINE 0x3
169#define mmLATENCY 0x3
170#define mmHEADER 0x3
171#define mmBIST 0x3
172#define mmBASE_ADDR_1 0x4
173#define mmBASE_ADDR_2 0x5
174#define mmBASE_ADDR_3 0x6
175#define mmBASE_ADDR_4 0x7
176#define mmBASE_ADDR_5 0x8
177#define mmBASE_ADDR_6 0x9
178#define mmROM_BASE_ADDR 0xc
179#define mmCAP_PTR 0xd
180#define mmINTERRUPT_LINE 0xf
181#define mmINTERRUPT_PIN 0xf
182#define mmADAPTER_ID 0xb
183#define mmMIN_GRANT 0xf
184#define mmMAX_LATENCY 0xf
185#define mmVENDOR_CAP_LIST 0x12
186#define mmADAPTER_ID_W 0x13
187#define mmPMI_CAP_LIST 0x14
188#define mmPMI_CAP 0x14
189#define mmPMI_STATUS_CNTL 0x15
190#define mmPCIE_CAP_LIST 0x16
191#define mmPCIE_CAP 0x16
192#define mmDEVICE_CAP 0x17
193#define mmDEVICE_CNTL 0x18
194#define mmDEVICE_STATUS 0x18
195#define mmLINK_CAP 0x19
196#define mmLINK_CNTL 0x1a
197#define mmLINK_STATUS 0x1a
198#define mmDEVICE_CAP2 0x1f
199#define mmDEVICE_CNTL2 0x20
200#define mmDEVICE_STATUS2 0x20
201#define mmLINK_CAP2 0x21
202#define mmLINK_CNTL2 0x22
203#define mmLINK_STATUS2 0x22
204#define mmMSI_CAP_LIST 0x28
205#define mmMSI_MSG_CNTL 0x28
206#define mmMSI_MSG_ADDR_LO 0x29
207#define mmMSI_MSG_ADDR_HI 0x2a
208#define mmMSI_MSG_DATA_64 0x2b
209#define mmMSI_MSG_DATA 0x2a
210#define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
211#define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
212#define mmPCIE_VENDOR_SPECIFIC1 0x42
213#define mmPCIE_VENDOR_SPECIFIC2 0x43
214#define mmPCIE_VC_ENH_CAP_LIST 0x44
215#define mmPCIE_PORT_VC_CAP_REG1 0x45
216#define mmPCIE_PORT_VC_CAP_REG2 0x46
217#define mmPCIE_PORT_VC_CNTL 0x47
218#define mmPCIE_PORT_VC_STATUS 0x47
219#define mmPCIE_VC0_RESOURCE_CAP 0x48
220#define mmPCIE_VC0_RESOURCE_CNTL 0x49
221#define mmPCIE_VC0_RESOURCE_STATUS 0x4a
222#define mmPCIE_VC1_RESOURCE_CAP 0x4b
223#define mmPCIE_VC1_RESOURCE_CNTL 0x4c
224#define mmPCIE_VC1_RESOURCE_STATUS 0x4d
225#define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
226#define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
227#define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
228#define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
229#define mmPCIE_UNCORR_ERR_STATUS 0x55
230#define mmPCIE_UNCORR_ERR_MASK 0x56
231#define mmPCIE_UNCORR_ERR_SEVERITY 0x57
232#define mmPCIE_CORR_ERR_STATUS 0x58
233#define mmPCIE_CORR_ERR_MASK 0x59
234#define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
235#define mmPCIE_HDR_LOG0 0x5b
236#define mmPCIE_HDR_LOG1 0x5c
237#define mmPCIE_HDR_LOG2 0x5d
238#define mmPCIE_HDR_LOG3 0x5e
239#define mmPCIE_TLP_PREFIX_LOG0 0x62
240#define mmPCIE_TLP_PREFIX_LOG1 0x63
241#define mmPCIE_TLP_PREFIX_LOG2 0x64
242#define mmPCIE_TLP_PREFIX_LOG3 0x65
243#define mmPCIE_BAR_ENH_CAP_LIST 0x80
244#define mmPCIE_BAR1_CAP 0x81
245#define mmPCIE_BAR1_CNTL 0x82
246#define mmPCIE_BAR2_CAP 0x83
247#define mmPCIE_BAR2_CNTL 0x84
248#define mmPCIE_BAR3_CAP 0x85
249#define mmPCIE_BAR3_CNTL 0x86
250#define mmPCIE_BAR4_CAP 0x87
251#define mmPCIE_BAR4_CNTL 0x88
252#define mmPCIE_BAR5_CAP 0x89
253#define mmPCIE_BAR5_CNTL 0x8a
254#define mmPCIE_BAR6_CAP 0x8b
255#define mmPCIE_BAR6_CNTL 0x8c
256#define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
257#define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
258#define mmPCIE_PWR_BUDGET_DATA 0x92
259#define mmPCIE_PWR_BUDGET_CAP 0x93
260#define mmPCIE_DPA_ENH_CAP_LIST 0x94
261#define mmPCIE_DPA_CAP 0x95
262#define mmPCIE_DPA_LATENCY_INDICATOR 0x96
263#define mmPCIE_DPA_STATUS 0x97
264#define mmPCIE_DPA_CNTL 0x97
265#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
266#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
267#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
268#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
269#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
270#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
271#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
272#define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
273#define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
274#define mmPCIE_LINK_CNTL3 0x9d
275#define mmPCIE_LANE_ERROR_STATUS 0x9e
276#define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
277#define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
278#define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
279#define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
280#define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
281#define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
282#define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
283#define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
284#define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
285#define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
286#define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
287#define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
288#define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
289#define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
290#define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
291#define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
292#define mmPCIE_ACS_ENH_CAP_LIST 0xa8
293#define mmPCIE_ACS_CAP 0xa9
294#define mmPCIE_ACS_CNTL 0xa9
295#define mmPCIE_ATS_ENH_CAP_LIST 0xac
296#define mmPCIE_ATS_CAP 0xad
297#define mmPCIE_ATS_CNTL 0xad
298#define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
299#define mmPCIE_PAGE_REQ_CNTL 0xb1
300#define mmPCIE_PAGE_REQ_STATUS 0xb1
301#define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
302#define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
303#define mmPCIE_PASID_ENH_CAP_LIST 0xb4
304#define mmPCIE_PASID_CAP 0xb5
305#define mmPCIE_PASID_CNTL 0xb5
306#define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
307#define mmPCIE_TPH_REQR_CAP 0xb9
308#define mmPCIE_TPH_REQR_CNTL 0xba
309#define mmPCIE_MC_ENH_CAP_LIST 0xbc
310#define mmPCIE_MC_CAP 0xbd
311#define mmPCIE_MC_CNTL 0xbd
312#define mmPCIE_MC_ADDR0 0xbe
313#define mmPCIE_MC_ADDR1 0xbf
314#define mmPCIE_MC_RCV0 0xc0
315#define mmPCIE_MC_RCV1 0xc1
316#define mmPCIE_MC_BLOCK_ALL0 0xc2
317#define mmPCIE_MC_BLOCK_ALL1 0xc3
318#define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
319#define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
320#define mmPCIE_LTR_ENH_CAP_LIST 0xc8
321#define mmPCIE_LTR_CAP 0xc9
322#define mmPCIE_INDEX 0xe
323#define mmPCIE_DATA 0xf
324#define mmPCIE_INDEX_2 0xc
325#define mmPCIE_DATA_2 0xd
326#define ixPCIE_RESERVED 0x1400000
327#define ixPCIE_SCRATCH 0x1400001
328#define ixPCIE_HW_DEBUG 0x1400002
329#define ixPCIE_RX_NUM_NAK 0x140000e
330#define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
331#define ixPCIE_CNTL 0x1400010
332#define ixPCIE_CONFIG_CNTL 0x1400011
333#define ixPCIE_DEBUG_CNTL 0x1400012
334#define ixPCIE_INT_CNTL 0x140001a
335#define ixPCIE_INT_STATUS 0x140001b
336#define ixPCIE_CNTL2 0x140001c
337#define ixPCIE_RX_CNTL2 0x140001d
338#define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
339#define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
340#define ixPCIE_CI_CNTL 0x1400020
341#define ixPCIE_BUS_CNTL 0x1400021
342#define ixPCIE_LC_STATE6 0x1400022
343#define ixPCIE_LC_STATE7 0x1400023
344#define ixPCIE_LC_STATE8 0x1400024
345#define ixPCIE_LC_STATE9 0x1400025
346#define ixPCIE_LC_STATE10 0x1400026
347#define ixPCIE_LC_STATE11 0x1400027
348#define ixPCIE_LC_STATUS1 0x1400028
349#define ixPCIE_LC_STATUS2 0x1400029
350#define ixPCIE_WPR_CNTL 0x1400030
351#define ixPCIE_RX_LAST_TLP0 0x1400031
352#define ixPCIE_RX_LAST_TLP1 0x1400032
353#define ixPCIE_RX_LAST_TLP2 0x1400033
354#define ixPCIE_RX_LAST_TLP3 0x1400034
355#define ixPCIE_TX_LAST_TLP0 0x1400035
356#define ixPCIE_TX_LAST_TLP1 0x1400036
357#define ixPCIE_TX_LAST_TLP2 0x1400037
358#define ixPCIE_TX_LAST_TLP3 0x1400038
359#define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
360#define ixPCIE_I2C_REG_DATA 0x140003b
361#define ixPCIE_CFG_CNTL 0x140003c
362#define ixPCIE_P_CNTL 0x1400040
363#define ixPCIE_P_BUF_STATUS 0x1400041
364#define ixPCIE_P_DECODER_STATUS 0x1400042
365#define ixPCIE_P_MISC_STATUS 0x1400043
366#define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
367#define ixPCIE_OBFF_CNTL 0x1400061
368#define ixPCIE_TX_LTR_CNTL 0x1400060
369#define ixPCIE_PERF_COUNT_CNTL 0x1400080
370#define ixPCIE_PERF_CNTL_TXCLK 0x1400081
371#define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
372#define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
373#define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
374#define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
375#define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
376#define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
377#define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
378#define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
379#define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
380#define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
381#define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
382#define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
383#define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
384#define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
385#define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
386#define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
387#define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
388#define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
389#define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
390#define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
391#define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
392#define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
393#define ixPCIE_STRAP_F0 0x14000b0
394#define ixPCIE_STRAP_F1 0x14000b1
395#define ixPCIE_STRAP_F2 0x14000b2
396#define ixPCIE_STRAP_F3 0x14000b3
397#define ixPCIE_STRAP_F4 0x14000b4
398#define ixPCIE_STRAP_F5 0x14000b5
399#define ixPCIE_STRAP_F6 0x14000b6
400#define ixPCIE_STRAP_F7 0x14000b7
401#define ixPCIE_STRAP_MISC 0x14000c0
402#define ixPCIE_STRAP_MISC2 0x14000c1
403#define ixPCIE_STRAP_PI 0x14000c2
404#define ixPCIE_STRAP_I2C_BD 0x14000c4
405#define ixPCIE_PRBS_CLR 0x14000c8
406#define ixPCIE_PRBS_STATUS1 0x14000c9
407#define ixPCIE_PRBS_STATUS2 0x14000ca
408#define ixPCIE_PRBS_FREERUN 0x14000cb
409#define ixPCIE_PRBS_MISC 0x14000cc
410#define ixPCIE_PRBS_USER_PATTERN 0x14000cd
411#define ixPCIE_PRBS_LO_BITCNT 0x14000ce
412#define ixPCIE_PRBS_HI_BITCNT 0x14000cf
413#define ixPCIE_PRBS_ERRCNT_0 0x14000d0
414#define ixPCIE_PRBS_ERRCNT_1 0x14000d1
415#define ixPCIE_PRBS_ERRCNT_2 0x14000d2
416#define ixPCIE_PRBS_ERRCNT_3 0x14000d3
417#define ixPCIE_PRBS_ERRCNT_4 0x14000d4
418#define ixPCIE_PRBS_ERRCNT_5 0x14000d5
419#define ixPCIE_PRBS_ERRCNT_6 0x14000d6
420#define ixPCIE_PRBS_ERRCNT_7 0x14000d7
421#define ixPCIE_PRBS_ERRCNT_8 0x14000d8
422#define ixPCIE_PRBS_ERRCNT_9 0x14000d9
423#define ixPCIE_PRBS_ERRCNT_10 0x14000da
424#define ixPCIE_PRBS_ERRCNT_11 0x14000db
425#define ixPCIE_PRBS_ERRCNT_12 0x14000dc
426#define ixPCIE_PRBS_ERRCNT_13 0x14000dd
427#define ixPCIE_PRBS_ERRCNT_14 0x14000de
428#define ixPCIE_PRBS_ERRCNT_15 0x14000df
429#define ixPCIE_F0_DPA_CAP 0x14000e0
430#define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
431#define ixPCIE_F0_DPA_CNTL 0x14000e5
432#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
433#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
434#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
435#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
436#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
437#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
438#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
439#define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
440#define ixPCIEP_RESERVED 0x10010000
441#define ixPCIEP_SCRATCH 0x10010001
442#define ixPCIEP_HW_DEBUG 0x10010002
443#define ixPCIEP_PORT_CNTL 0x10010010
444#define ixPCIE_TX_CNTL 0x10010020
445#define ixPCIE_TX_REQUESTER_ID 0x10010021
446#define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
447#define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
448#define ixPCIE_TX_SEQ 0x10010024
449#define ixPCIE_TX_REPLAY 0x10010025
450#define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
451#define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
452#define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
453#define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
454#define ixPCIE_TX_CREDITS_INIT_P 0x10010033
455#define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
456#define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
457#define ixPCIE_TX_CREDITS_STATUS 0x10010036
458#define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
459#define ixPCIE_P_PORT_LANE_STATUS 0x10010050
460#define ixPCIE_FC_P 0x10010060
461#define ixPCIE_FC_NP 0x10010061
462#define ixPCIE_FC_CPL 0x10010062
463#define ixPCIE_ERR_CNTL 0x1001006a
464#define ixPCIE_RX_CNTL 0x10010070
465#define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
466#define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
467#define ixPCIE_RX_CNTL3 0x10010074
468#define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
469#define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
470#define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
471#define ixPCIE_LC_CNTL 0x100100a0
472#define ixPCIE_LC_CNTL2 0x100100b1
473#define ixPCIE_LC_CNTL3 0x100100b5
474#define ixPCIE_LC_CNTL4 0x100100b6
475#define ixPCIE_LC_CNTL5 0x100100b7
476#define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
477#define ixPCIE_LC_TRAINING_CNTL 0x100100a1
478#define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
479#define ixPCIE_LC_N_FTS_CNTL 0x100100a3
480#define ixPCIE_LC_SPEED_CNTL 0x100100a4
481#define ixPCIE_LC_CDR_CNTL 0x100100b3
482#define ixPCIE_LC_LANE_CNTL 0x100100b4
483#define ixPCIE_LC_FORCE_COEFF 0x100100b8
484#define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
485#define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
486#define ixPCIE_LC_STATE0 0x100100a5
487#define ixPCIE_LC_STATE1 0x100100a6
488#define ixPCIE_LC_STATE2 0x100100a7
489#define ixPCIE_LC_STATE3 0x100100a8
490#define ixPCIE_LC_STATE4 0x100100a9
491#define ixPCIE_LC_STATE5 0x100100aa
492#define ixPCIEP_STRAP_LC 0x100100c0
493#define ixPCIEP_STRAP_MISC 0x100100c1
494#define ixPCIEP_BCH_ECC_CNTL 0x100100d0
495#define ixPB0_GLB_CTRL_REG0 0x1200004
496#define ixPB0_GLB_CTRL_REG1 0x1200008
497#define ixPB0_GLB_CTRL_REG2 0x120000c
498#define ixPB0_GLB_CTRL_REG3 0x1200010
499#define ixPB0_GLB_CTRL_REG4 0x1200014
500#define ixPB0_GLB_CTRL_REG5 0x1200018
501#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
502#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
503#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
504#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
505#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
506#define ixPB0_GLB_OVRD_REG0 0x1200030
507#define ixPB0_GLB_OVRD_REG1 0x1200034
508#define ixPB0_GLB_OVRD_REG2 0x1200038
509#define ixPB0_HW_DEBUG 0x1202004
510#define ixPB0_STRAP_GLB_REG0 0x1202020
511#define ixPB0_STRAP_TX_REG0 0x1202024
512#define ixPB0_STRAP_RX_REG0 0x1202028
513#define ixPB0_STRAP_RX_REG1 0x120202c
514#define ixPB0_STRAP_PLL_REG0 0x1202030
515#define ixPB0_STRAP_PIN_REG0 0x1202034
516#define ixPB0_DFT_JIT_INJ_REG0 0x1203000
517#define ixPB0_DFT_JIT_INJ_REG1 0x1203004
518#define ixPB0_DFT_JIT_INJ_REG2 0x1203008
519#define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
520#define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
521#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
522#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
523#define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
524#define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
525#define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
526#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
527#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
528#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
529#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
530#define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
531#define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
532#define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
533#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
534#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
535#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
536#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
537#define ixPB0_RX_GLB_CTRL_REG0 0x1206000
538#define ixPB0_RX_GLB_CTRL_REG1 0x1206004
539#define ixPB0_RX_GLB_CTRL_REG2 0x1206008
540#define ixPB0_RX_GLB_CTRL_REG3 0x120600c
541#define ixPB0_RX_GLB_CTRL_REG4 0x1206010
542#define ixPB0_RX_GLB_CTRL_REG5 0x1206014
543#define ixPB0_RX_GLB_CTRL_REG6 0x1206018
544#define ixPB0_RX_GLB_CTRL_REG7 0x120601c
545#define ixPB0_RX_GLB_CTRL_REG8 0x1206020
546#define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
547#define ixPB0_RX_GLB_OVRD_REG0 0x1206030
548#define ixPB0_RX_GLB_OVRD_REG1 0x1206034
549#define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
550#define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
551#define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
552#define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
553#define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
554#define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
555#define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
556#define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
557#define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
558#define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
559#define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
560#define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
561#define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
562#define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
563#define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
564#define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
565#define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
566#define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
567#define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
568#define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
569#define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
570#define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
571#define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
572#define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
573#define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
574#define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
575#define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
576#define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
577#define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
578#define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
579#define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
580#define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
581#define ixPB0_TX_GLB_CTRL_REG0 0x1208000
582#define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
583#define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
584#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
585#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
586#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
587#define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
588#define ixPB0_TX_GLB_OVRD_REG0 0x1208030
589#define ixPB0_TX_GLB_OVRD_REG1 0x1208034
590#define ixPB0_TX_GLB_OVRD_REG2 0x1208038
591#define ixPB0_TX_GLB_OVRD_REG3 0x120803c
592#define ixPB0_TX_GLB_OVRD_REG4 0x1208040
593#define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
594#define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
595#define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
596#define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
597#define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
598#define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
599#define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
600#define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
601#define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
602#define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
603#define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
604#define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
605#define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
606#define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
607#define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
608#define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
609#define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
610#define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
611#define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
612#define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
613#define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
614#define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
615#define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
616#define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
617#define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
618#define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
619#define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
620#define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
621#define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
622#define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
623#define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
624#define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
625#define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
626#define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
627#define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
628#define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
629#define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
630#define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
631#define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
632#define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
633#define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
634#define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
635#define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
636#define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
637#define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
638#define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
639#define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
640#define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
641#define ixPB1_GLB_CTRL_REG0 0x2200004
642#define ixPB1_GLB_CTRL_REG1 0x2200008
643#define ixPB1_GLB_CTRL_REG2 0x220000c
644#define ixPB1_GLB_CTRL_REG3 0x2200010
645#define ixPB1_GLB_CTRL_REG4 0x2200014
646#define ixPB1_GLB_CTRL_REG5 0x2200018
647#define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
648#define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
649#define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
650#define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
651#define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
652#define ixPB1_GLB_OVRD_REG0 0x2200030
653#define ixPB1_GLB_OVRD_REG1 0x2200034
654#define ixPB1_GLB_OVRD_REG2 0x2200038
655#define ixPB1_HW_DEBUG 0x2202004
656#define ixPB1_STRAP_GLB_REG0 0x2202020
657#define ixPB1_STRAP_TX_REG0 0x2202024
658#define ixPB1_STRAP_RX_REG0 0x2202028
659#define ixPB1_STRAP_RX_REG1 0x220202c
660#define ixPB1_STRAP_PLL_REG0 0x2202030
661#define ixPB1_STRAP_PIN_REG0 0x2202034
662#define ixPB1_DFT_JIT_INJ_REG0 0x2203000
663#define ixPB1_DFT_JIT_INJ_REG1 0x2203004
664#define ixPB1_DFT_JIT_INJ_REG2 0x2203008
665#define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
666#define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
667#define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
668#define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
669#define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
670#define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
671#define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
672#define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
673#define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
674#define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
675#define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
676#define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
677#define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
678#define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
679#define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
680#define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
681#define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
682#define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
683#define ixPB1_RX_GLB_CTRL_REG0 0x2206000
684#define ixPB1_RX_GLB_CTRL_REG1 0x2206004
685#define ixPB1_RX_GLB_CTRL_REG2 0x2206008
686#define ixPB1_RX_GLB_CTRL_REG3 0x220600c
687#define ixPB1_RX_GLB_CTRL_REG4 0x2206010
688#define ixPB1_RX_GLB_CTRL_REG5 0x2206014
689#define ixPB1_RX_GLB_CTRL_REG6 0x2206018
690#define ixPB1_RX_GLB_CTRL_REG7 0x220601c
691#define ixPB1_RX_GLB_CTRL_REG8 0x2206020
692#define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
693#define ixPB1_RX_GLB_OVRD_REG0 0x2206030
694#define ixPB1_RX_GLB_OVRD_REG1 0x2206034
695#define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
696#define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
697#define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
698#define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
699#define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
700#define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
701#define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
702#define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
703#define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
704#define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
705#define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
706#define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
707#define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
708#define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
709#define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
710#define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
711#define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
712#define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
713#define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
714#define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
715#define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
716#define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
717#define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
718#define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
719#define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
720#define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
721#define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
722#define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
723#define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
724#define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
725#define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
726#define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
727#define ixPB1_TX_GLB_CTRL_REG0 0x2208000
728#define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
729#define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
730#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
731#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
732#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
733#define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
734#define ixPB1_TX_GLB_OVRD_REG0 0x2208030
735#define ixPB1_TX_GLB_OVRD_REG1 0x2208034
736#define ixPB1_TX_GLB_OVRD_REG2 0x2208038
737#define ixPB1_TX_GLB_OVRD_REG3 0x220803c
738#define ixPB1_TX_GLB_OVRD_REG4 0x2208040
739#define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
740#define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
741#define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
742#define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
743#define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
744#define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
745#define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
746#define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
747#define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
748#define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
749#define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
750#define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
751#define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
752#define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
753#define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
754#define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
755#define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
756#define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
757#define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
758#define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
759#define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
760#define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
761#define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
762#define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
763#define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
764#define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
765#define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
766#define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
767#define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
768#define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
769#define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
770#define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
771#define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
772#define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
773#define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
774#define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
775#define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
776#define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
777#define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
778#define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
779#define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
780#define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
781#define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
782#define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
783#define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
784#define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
785#define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
786#define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
787#define ixPB0_PIF_SCRATCH 0x1100001
788#define ixPB0_PIF_HW_DEBUG 0x1100002
789#define ixPB0_PIF_PRG6 0x1100003
790#define ixPB0_PIF_PRG7 0x1100004
791#define ixPB0_PIF_CNTL 0x1100010
792#define ixPB0_PIF_PAIRING 0x1100011
793#define ixPB0_PIF_PWRDOWN_0 0x1100012
794#define ixPB0_PIF_PWRDOWN_1 0x1100013
795#define ixPB0_PIF_CNTL2 0x1100014
796#define ixPB0_PIF_TXPHYSTATUS 0x1100015
797#define ixPB0_PIF_SC_CTL 0x1100016
798#define ixPB0_PIF_PWRDOWN_2 0x1100017
799#define ixPB0_PIF_PWRDOWN_3 0x1100018
800#define ixPB0_PIF_SC_CTL2 0x1100019
801#define ixPB0_PIF_PRG0 0x110001a
802#define ixPB0_PIF_PRG1 0x110001b
803#define ixPB0_PIF_PRG2 0x110001c
804#define ixPB0_PIF_PRG3 0x110001d
805#define ixPB0_PIF_PRG4 0x110001e
806#define ixPB0_PIF_PRG5 0x110001f
807#define ixPB0_PIF_PDNB_OVERRIDE_0 0x1100020
808#define ixPB0_PIF_PDNB_OVERRIDE_1 0x1100021
809#define ixPB0_PIF_PDNB_OVERRIDE_2 0x1100022
810#define ixPB0_PIF_PDNB_OVERRIDE_3 0x1100023
811#define ixPB0_PIF_PDNB_OVERRIDE_4 0x1100024
812#define ixPB0_PIF_PDNB_OVERRIDE_5 0x1100025
813#define ixPB0_PIF_PDNB_OVERRIDE_6 0x1100026
814#define ixPB0_PIF_PDNB_OVERRIDE_7 0x1100027
815#define ixPB0_PIF_SEQ_STATUS_0 0x1100028
816#define ixPB0_PIF_SEQ_STATUS_1 0x1100029
817#define ixPB0_PIF_SEQ_STATUS_2 0x110002a
818#define ixPB0_PIF_SEQ_STATUS_3 0x110002b
819#define ixPB0_PIF_SEQ_STATUS_4 0x110002c
820#define ixPB0_PIF_SEQ_STATUS_5 0x110002d
821#define ixPB0_PIF_SEQ_STATUS_6 0x110002e
822#define ixPB0_PIF_SEQ_STATUS_7 0x110002f
823#define ixPB0_PIF_PDNB_OVERRIDE_8 0x1100030
824#define ixPB0_PIF_PDNB_OVERRIDE_9 0x1100031
825#define ixPB0_PIF_PDNB_OVERRIDE_10 0x1100032
826#define ixPB0_PIF_PDNB_OVERRIDE_11 0x1100033
827#define ixPB0_PIF_PDNB_OVERRIDE_12 0x1100034
828#define ixPB0_PIF_PDNB_OVERRIDE_13 0x1100035
829#define ixPB0_PIF_PDNB_OVERRIDE_14 0x1100036
830#define ixPB0_PIF_PDNB_OVERRIDE_15 0x1100037
831#define ixPB0_PIF_SEQ_STATUS_8 0x1100038
832#define ixPB0_PIF_SEQ_STATUS_9 0x1100039
833#define ixPB0_PIF_SEQ_STATUS_10 0x110003a
834#define ixPB0_PIF_SEQ_STATUS_11 0x110003b
835#define ixPB0_PIF_SEQ_STATUS_12 0x110003c
836#define ixPB0_PIF_SEQ_STATUS_13 0x110003d
837#define ixPB0_PIF_SEQ_STATUS_14 0x110003e
838#define ixPB0_PIF_SEQ_STATUS_15 0x110003f
839#define ixPB1_PIF_SCRATCH 0x2100001
840#define ixPB1_PIF_HW_DEBUG 0x2100002
841#define ixPB1_PIF_PRG6 0x2100003
842#define ixPB1_PIF_PRG7 0x2100004
843#define ixPB1_PIF_CNTL 0x2100010
844#define ixPB1_PIF_PAIRING 0x2100011
845#define ixPB1_PIF_PWRDOWN_0 0x2100012
846#define ixPB1_PIF_PWRDOWN_1 0x2100013
847#define ixPB1_PIF_CNTL2 0x2100014
848#define ixPB1_PIF_TXPHYSTATUS 0x2100015
849#define ixPB1_PIF_SC_CTL 0x2100016
850#define ixPB1_PIF_PWRDOWN_2 0x2100017
851#define ixPB1_PIF_PWRDOWN_3 0x2100018
852#define ixPB1_PIF_SC_CTL2 0x2100019
853#define ixPB1_PIF_PRG0 0x210001a
854#define ixPB1_PIF_PRG1 0x210001b
855#define ixPB1_PIF_PRG2 0x210001c
856#define ixPB1_PIF_PRG3 0x210001d
857#define ixPB1_PIF_PRG4 0x210001e
858#define ixPB1_PIF_PRG5 0x210001f
859#define ixPB1_PIF_PDNB_OVERRIDE_0 0x2100020
860#define ixPB1_PIF_PDNB_OVERRIDE_1 0x2100021
861#define ixPB1_PIF_PDNB_OVERRIDE_2 0x2100022
862#define ixPB1_PIF_PDNB_OVERRIDE_3 0x2100023
863#define ixPB1_PIF_PDNB_OVERRIDE_4 0x2100024
864#define ixPB1_PIF_PDNB_OVERRIDE_5 0x2100025
865#define ixPB1_PIF_PDNB_OVERRIDE_6 0x2100026
866#define ixPB1_PIF_PDNB_OVERRIDE_7 0x2100027
867#define ixPB1_PIF_SEQ_STATUS_0 0x2100028
868#define ixPB1_PIF_SEQ_STATUS_1 0x2100029
869#define ixPB1_PIF_SEQ_STATUS_2 0x210002a
870#define ixPB1_PIF_SEQ_STATUS_3 0x210002b
871#define ixPB1_PIF_SEQ_STATUS_4 0x210002c
872#define ixPB1_PIF_SEQ_STATUS_5 0x210002d
873#define ixPB1_PIF_SEQ_STATUS_6 0x210002e
874#define ixPB1_PIF_SEQ_STATUS_7 0x210002f
875#define ixPB1_PIF_PDNB_OVERRIDE_8 0x2100030
876#define ixPB1_PIF_PDNB_OVERRIDE_9 0x2100031
877#define ixPB1_PIF_PDNB_OVERRIDE_10 0x2100032
878#define ixPB1_PIF_PDNB_OVERRIDE_11 0x2100033
879#define ixPB1_PIF_PDNB_OVERRIDE_12 0x2100034
880#define ixPB1_PIF_PDNB_OVERRIDE_13 0x2100035
881#define ixPB1_PIF_PDNB_OVERRIDE_14 0x2100036
882#define ixPB1_PIF_PDNB_OVERRIDE_15 0x2100037
883#define ixPB1_PIF_SEQ_STATUS_8 0x2100038
884#define ixPB1_PIF_SEQ_STATUS_9 0x2100039
885#define ixPB1_PIF_SEQ_STATUS_10 0x210003a
886#define ixPB1_PIF_SEQ_STATUS_11 0x210003b
887#define ixPB1_PIF_SEQ_STATUS_12 0x210003c
888#define ixPB1_PIF_SEQ_STATUS_13 0x210003d
889#define ixPB1_PIF_SEQ_STATUS_14 0x210003e
890#define ixPB1_PIF_SEQ_STATUS_15 0x210003f
891#define mmBIF_RFE_SNOOP_REG 0x27
892#define mmBIF_RFE_WARMRST_CNTL 0x1459
893#define mmBIF_RFE_SOFTRST_CNTL 0x1441
894#define mmBIF_RFE_IMPRST_CNTL 0x1458
895#define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
896#define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
897#define mmBIF_PWDN_COMMAND 0x1444
898#define mmBIF_PWDN_STATUS 0x1445
899#define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
900#define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
901#define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448
902#define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
903#define mmBIF_RFE_MMCFG_CNTL 0x144c
904#define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
905#define mmBIF_IMPCTL_SMPLCNTL 0x1450
906#define mmBIF_IMPCTL_RXCNTL 0x1451
907#define mmBIF_IMPCTL_TXCNTL_pd 0x1452
908#define mmBIF_IMPCTL_TXCNTL_pu 0x1453
909#define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
910#define mmBIF_CLOCKS_BITS 0x1489
911#define mmBIF_LNCNT_RESET 0x1488
912#define mmLNCNT_CONTROL 0x1487
913#define mmNEW_REFCLKB_TIMER 0x1485
914#define mmNEW_REFCLKB_TIMER_1 0x1484
915#define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483
916#define mmBIF_RESET_EN 0x1482
917#define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481
918#define mmBIF_BACO_MSIC 0x1480
919#define mmBIF_RESET_CNTL 0x1486
920#define mmBIF_RFE_CNTL_MISC 0x148c
921
922#endif /* BIF_4_1_D_H */
923

source code of linux/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h