| 1 | /* |
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| 2 | * BIF_5_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef BIF_5_0_D_H |
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| 25 | #define BIF_5_0_D_H |
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| 26 | |
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| 27 | #define mmMM_INDEX 0x0 |
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| 28 | #define mmMM_INDEX_HI 0x6 |
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| 29 | #define mmMM_DATA 0x1 |
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| 30 | #define mmCC_BIF_BX_FUSESTRAP0 0x14D7 |
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| 31 | #define mmCC_BIF_BX_STRAP2 0x152A |
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| 32 | #define mmBIF_MM_INDACCESS_CNTL 0x1500 |
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| 33 | #define mmBIF_DOORBELL_APER_EN 0x1501 |
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| 34 | #define mmBUS_CNTL 0x1508 |
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| 35 | #define mmCONFIG_CNTL 0x1509 |
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| 36 | #define mmCONFIG_MEMSIZE 0x150a |
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| 37 | #define mmCONFIG_RESERVED 0x1502 |
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| 38 | #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 |
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| 39 | #define mmCONFIG_F0_BASE 0x150b |
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| 40 | #define mmCONFIG_APER_SIZE 0x150c |
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| 41 | #define mmCONFIG_REG_APER_SIZE 0x150d |
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| 42 | #define mmBIF_SCRATCH0 0x150e |
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| 43 | #define mmBIF_SCRATCH1 0x150f |
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| 44 | #define mmBIF_RLC_INTR_CNTL 0x1510 |
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| 45 | #define mmBIF_BME_STATUS 0x1511 |
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| 46 | #define mmBIF_ATOMIC_ERR_LOG 0x1512 |
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| 47 | #define mmBX_RESET_EN 0x1514 |
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| 48 | #define mmMM_CFGREGS_CNTL 0x1513 |
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| 49 | #define mmHW_DEBUG 0x1515 |
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| 50 | #define mmMASTER_CREDIT_CNTL 0x1516 |
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| 51 | #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 |
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| 52 | #define mmBX_RESET_CNTL 0x1518 |
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| 53 | #define mmINTERRUPT_CNTL 0x151a |
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| 54 | #define mmINTERRUPT_CNTL2 0x151b |
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| 55 | #define mmBIF_DEBUG_CNTL 0x151c |
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| 56 | #define mmBIF_DEBUG_MUX 0x151d |
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| 57 | #define mmBIF_DEBUG_OUT 0x151e |
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| 58 | #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 |
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| 59 | #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 |
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| 60 | #define mmCLKREQB_PAD_CNTL 0x1521 |
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| 61 | #define mmCLKREQB_PERF_COUNTER 0x1522 |
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| 62 | #define mmBIF_XDMA_LO 0x14c0 |
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| 63 | #define mmBIF_XDMA_HI 0x14c1 |
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| 64 | #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 |
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| 65 | #define mmBIF_DOORBELL_CNTL 0x14c3 |
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| 66 | #define mmBIF_SLVARB_MODE 0x14c4 |
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| 67 | #define mmBIF_CLK_CTRL 0x14c5 |
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| 68 | #define mmBIF_FB_EN 0x1524 |
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| 69 | #define mmBIF_BUSNUM_CNTL1 0x1525 |
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| 70 | #define mmBIF_BUSNUM_LIST0 0x1526 |
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| 71 | #define mmBIF_BUSNUM_LIST1 0x1527 |
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| 72 | #define mmBIF_BUSNUM_CNTL2 0x152b |
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| 73 | #define mmBIF_BUSY_DELAY_CNTR 0x1529 |
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| 74 | #define mmBIF_PERFMON_CNTL 0x152c |
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| 75 | #define mmBIF_PERFCOUNTER0_RESULT 0x152d |
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| 76 | #define mmBIF_PERFCOUNTER1_RESULT 0x152e |
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| 77 | #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 |
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| 78 | #define mmGPU_HDP_FLUSH_REQ 0x1537 |
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| 79 | #define mmGPU_HDP_FLUSH_DONE 0x1538 |
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| 80 | #define mmSLAVE_HANG_ERROR 0x153b |
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| 81 | #define mmCAPTURE_HOST_BUSNUM 0x153c |
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| 82 | #define mmHOST_BUSNUM 0x153d |
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| 83 | #define mmPEER_REG_RANGE0 0x153e |
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| 84 | #define mmPEER_REG_RANGE1 0x153f |
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| 85 | #define mmPEER0_FB_OFFSET_HI 0x14f3 |
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| 86 | #define mmPEER0_FB_OFFSET_LO 0x14f2 |
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| 87 | #define mmPEER1_FB_OFFSET_HI 0x14f1 |
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| 88 | #define mmPEER1_FB_OFFSET_LO 0x14f0 |
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| 89 | #define mmPEER2_FB_OFFSET_HI 0x14ef |
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| 90 | #define mmPEER2_FB_OFFSET_LO 0x14ee |
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| 91 | #define mmPEER3_FB_OFFSET_HI 0x14ed |
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| 92 | #define mmPEER3_FB_OFFSET_LO 0x14ec |
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| 93 | #define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb |
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| 94 | #define mmBIF_MST_TRANS_PENDING 0x14ea |
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| 95 | #define mmBIF_SLV_TRANS_PENDING 0x14e9 |
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| 96 | #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 |
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| 97 | #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 |
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| 98 | #define mmBACO_CNTL 0x14e5 |
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| 99 | #define mmBF_ANA_ISO_CNTL 0x14c7 |
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| 100 | #define mmMEM_TYPE_CNTL 0x14e4 |
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| 101 | #define mmBIF_BACO_DEBUG 0x14df |
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| 102 | #define mmBIF_BACO_DEBUG_LATCH 0x14dc |
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| 103 | #define mmBACO_CNTL_MISC 0x14db |
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| 104 | #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 |
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| 105 | #define mmBIF_VDDGFX_GFX0_LOWER 0x1428 |
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| 106 | #define mmBIF_VDDGFX_GFX0_UPPER 0x1429 |
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| 107 | #define mmBIF_VDDGFX_GFX1_LOWER 0x142a |
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| 108 | #define mmBIF_VDDGFX_GFX1_UPPER 0x142b |
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| 109 | #define mmBIF_VDDGFX_GFX2_LOWER 0x142c |
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| 110 | #define mmBIF_VDDGFX_GFX2_UPPER 0x142d |
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| 111 | #define mmBIF_VDDGFX_GFX3_LOWER 0x142e |
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| 112 | #define mmBIF_VDDGFX_GFX3_UPPER 0x142f |
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| 113 | #define mmBIF_VDDGFX_GFX4_LOWER 0x1430 |
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| 114 | #define mmBIF_VDDGFX_GFX4_UPPER 0x1431 |
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| 115 | #define mmBIF_VDDGFX_GFX5_LOWER 0x1432 |
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| 116 | #define mmBIF_VDDGFX_GFX5_UPPER 0x1433 |
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| 117 | #define mmBIF_VDDGFX_RSV1_LOWER 0x1434 |
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| 118 | #define mmBIF_VDDGFX_RSV1_UPPER 0x1435 |
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| 119 | #define mmBIF_VDDGFX_RSV2_LOWER 0x1436 |
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| 120 | #define mmBIF_VDDGFX_RSV2_UPPER 0x1437 |
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| 121 | #define mmBIF_VDDGFX_RSV3_LOWER 0x1438 |
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| 122 | #define mmBIF_VDDGFX_RSV3_UPPER 0x1439 |
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| 123 | #define mmBIF_VDDGFX_RSV4_LOWER 0x143a |
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| 124 | #define mmBIF_VDDGFX_RSV4_UPPER 0x143b |
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| 125 | #define mmBIF_VDDGFX_FB_CMP 0x143c |
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| 126 | #define mmBIF_SMU_INDEX 0x143d |
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| 127 | #define mmBIF_SMU_DATA 0x143e |
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| 128 | #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc |
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| 129 | #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd |
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| 130 | #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe |
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| 131 | #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff |
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| 132 | #define mmIMPCTL_RESET 0x14f5 |
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| 133 | #define mmGARLIC_FLUSH_CNTL 0x1401 |
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| 134 | #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 |
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| 135 | #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 |
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| 136 | #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 |
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| 137 | #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 |
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| 138 | #define mmGARLIC_FLUSH_ADDR_START_4 0x140a |
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| 139 | #define mmGARLIC_FLUSH_ADDR_START_5 0x140c |
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| 140 | #define mmGARLIC_FLUSH_ADDR_START_6 0x140e |
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| 141 | #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 |
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| 142 | #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 |
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| 143 | #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 |
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| 144 | #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 |
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| 145 | #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 |
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| 146 | #define mmGARLIC_FLUSH_ADDR_END_4 0x140b |
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| 147 | #define mmGARLIC_FLUSH_ADDR_END_5 0x140d |
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| 148 | #define mmGARLIC_FLUSH_ADDR_END_6 0x140f |
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| 149 | #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 |
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| 150 | #define mmGARLIC_FLUSH_REQ 0x1412 |
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| 151 | #define mmGPU_GARLIC_FLUSH_REQ 0x1413 |
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| 152 | #define mmGPU_GARLIC_FLUSH_DONE 0x1414 |
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| 153 | #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 |
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| 154 | #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 |
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| 155 | #define mmBIOS_SCRATCH_0 0x5c9 |
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| 156 | #define mmBIOS_SCRATCH_1 0x5ca |
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| 157 | #define mmBIOS_SCRATCH_2 0x5cb |
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| 158 | #define mmBIOS_SCRATCH_3 0x5cc |
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| 159 | #define mmBIOS_SCRATCH_4 0x5cd |
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| 160 | #define mmBIOS_SCRATCH_5 0x5ce |
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| 161 | #define mmBIOS_SCRATCH_6 0x5cf |
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| 162 | #define mmBIOS_SCRATCH_7 0x5d0 |
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| 163 | #define mmBIOS_SCRATCH_8 0x5d1 |
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| 164 | #define mmBIOS_SCRATCH_9 0x5d2 |
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| 165 | #define mmBIOS_SCRATCH_10 0x5d3 |
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| 166 | #define mmBIOS_SCRATCH_11 0x5d4 |
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| 167 | #define mmBIOS_SCRATCH_12 0x5d5 |
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| 168 | #define mmBIOS_SCRATCH_13 0x5d6 |
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| 169 | #define mmBIOS_SCRATCH_14 0x5d7 |
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| 170 | #define mmBIOS_SCRATCH_15 0x5d8 |
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| 171 | #define mmBIF_RB_CNTL 0x1530 |
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| 172 | #define mmBIF_RB_BASE 0x1531 |
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| 173 | #define mmBIF_RB_RPTR 0x1532 |
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| 174 | #define mmBIF_RB_WPTR 0x1533 |
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| 175 | #define mmBIF_RB_WPTR_ADDR_HI 0x1534 |
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| 176 | #define mmBIF_RB_WPTR_ADDR_LO 0x1535 |
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| 177 | #define mmMAILBOX_INDEX 0x14c6 |
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| 178 | #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 |
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| 179 | #define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9 |
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| 180 | #define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca |
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| 181 | #define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb |
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| 182 | #define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc |
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| 183 | #define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd |
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| 184 | #define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce |
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| 185 | #define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf |
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| 186 | #define mmMAILBOX_CONTROL 0x14d0 |
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| 187 | #define mmMAILBOX_INT_CNTL 0x14d1 |
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| 188 | #define mmBIF_VIRT_RESET_REQ 0x14d2 |
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| 189 | #define mmVM_INIT_STATUS 0x14d3 |
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| 190 | #define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5 |
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| 191 | #define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6 |
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| 192 | #define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8 |
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| 193 | #define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c |
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| 194 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d |
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| 195 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e |
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| 196 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f |
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| 197 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420 |
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| 198 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421 |
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| 199 | #define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422 |
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| 200 | #define mmBIF_GPU_IDLE_LATENCY 0x1415 |
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| 201 | #define mmBIF_MMIO_MAP_RANGE0 0x1416 |
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| 202 | #define mmBIF_MMIO_MAP_RANGE1 0x1417 |
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| 203 | #define mmBIF_MMIO_MAP_RANGE2 0x1418 |
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| 204 | #define mmBIF_MMIO_MAP_RANGE3 0x1419 |
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| 205 | #define mmBIF_MMIO_MAP_RANGE4 0x141a |
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| 206 | #define mmBIF_MMIO_MAP_RANGE5 0x141b |
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| 207 | #define mmVENDOR_ID 0x0 |
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| 208 | #define mmDEVICE_ID 0x0 |
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| 209 | #define mmCOMMAND 0x1 |
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| 210 | #define mmSTATUS 0x1 |
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| 211 | #define mmREVISION_ID 0x2 |
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| 212 | #define mmPROG_INTERFACE 0x2 |
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| 213 | #define mmSUB_CLASS 0x2 |
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| 214 | #define mmBASE_CLASS 0x2 |
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| 215 | #define mmCACHE_LINE 0x3 |
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| 216 | #define mmLATENCY 0x3 |
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| 217 | #define 0x3 |
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| 218 | #define mmBIST 0x3 |
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| 219 | #define mmBASE_ADDR_1 0x4 |
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| 220 | #define mmBASE_ADDR_2 0x5 |
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| 221 | #define mmBASE_ADDR_3 0x6 |
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| 222 | #define mmBASE_ADDR_4 0x7 |
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| 223 | #define mmBASE_ADDR_5 0x8 |
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| 224 | #define mmBASE_ADDR_6 0x9 |
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| 225 | #define mmROM_BASE_ADDR 0xc |
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| 226 | #define mmCAP_PTR 0xd |
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| 227 | #define mmINTERRUPT_LINE 0xf |
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| 228 | #define mmINTERRUPT_PIN 0xf |
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| 229 | #define mmADAPTER_ID 0xb |
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| 230 | #define mmMIN_GRANT 0xf |
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| 231 | #define mmMAX_LATENCY 0xf |
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| 232 | #define mmVENDOR_CAP_LIST 0x12 |
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| 233 | #define mmADAPTER_ID_W 0x13 |
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| 234 | #define mmPMI_CAP_LIST 0x14 |
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| 235 | #define mmPMI_CAP 0x14 |
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| 236 | #define mmPMI_STATUS_CNTL 0x15 |
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| 237 | #define mmPCIE_CAP_LIST 0x16 |
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| 238 | #define mmPCIE_CAP 0x16 |
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| 239 | #define mmDEVICE_CAP 0x17 |
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| 240 | #define mmDEVICE_CNTL 0x18 |
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| 241 | #define mmDEVICE_STATUS 0x18 |
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| 242 | #define mmLINK_CAP 0x19 |
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| 243 | #define mmLINK_CNTL 0x1a |
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| 244 | #define mmLINK_STATUS 0x1a |
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| 245 | #define mmDEVICE_CAP2 0x1f |
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| 246 | #define mmDEVICE_CNTL2 0x20 |
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| 247 | #define mmDEVICE_STATUS2 0x20 |
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| 248 | #define mmLINK_CAP2 0x21 |
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| 249 | #define mmLINK_CNTL2 0x22 |
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| 250 | #define mmLINK_STATUS2 0x22 |
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| 251 | #define mmMSI_CAP_LIST 0x28 |
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| 252 | #define mmMSI_MSG_CNTL 0x28 |
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| 253 | #define mmMSI_MSG_ADDR_LO 0x29 |
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| 254 | #define mmMSI_MSG_ADDR_HI 0x2a |
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| 255 | #define mmMSI_MSG_DATA_64 0x2b |
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| 256 | #define mmMSI_MSG_DATA 0x2a |
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| 257 | #define mmMSI_MASK 0x2b |
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| 258 | #define mmMSI_PENDING 0x2c |
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| 259 | #define mmMSI_MASK_64 0x2c |
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| 260 | #define mmMSI_PENDING_64 0x2d |
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| 261 | #define mmMSIX_CAP_LIST 0x30 |
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| 262 | #define mmMSIX_MSG_CNTL 0x30 |
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| 263 | #define mmMSIX_TABLE 0x31 |
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| 264 | #define mmMSIX_PBA 0x32 |
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| 265 | #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 |
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| 266 | #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 |
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| 267 | #define mmPCIE_VENDOR_SPECIFIC1 0x42 |
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| 268 | #define mmPCIE_VENDOR_SPECIFIC2 0x43 |
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| 269 | #define mmPCIE_VC_ENH_CAP_LIST 0x44 |
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| 270 | #define mmPCIE_PORT_VC_CAP_REG1 0x45 |
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| 271 | #define mmPCIE_PORT_VC_CAP_REG2 0x46 |
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| 272 | #define mmPCIE_PORT_VC_CNTL 0x47 |
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| 273 | #define mmPCIE_PORT_VC_STATUS 0x47 |
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| 274 | #define mmPCIE_VC0_RESOURCE_CAP 0x48 |
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| 275 | #define mmPCIE_VC0_RESOURCE_CNTL 0x49 |
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| 276 | #define mmPCIE_VC0_RESOURCE_STATUS 0x4a |
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| 277 | #define mmPCIE_VC1_RESOURCE_CAP 0x4b |
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| 278 | #define mmPCIE_VC1_RESOURCE_CNTL 0x4c |
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| 279 | #define mmPCIE_VC1_RESOURCE_STATUS 0x4d |
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| 280 | #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 |
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| 281 | #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 |
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| 282 | #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 |
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| 283 | #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 |
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| 284 | #define mmPCIE_UNCORR_ERR_STATUS 0x55 |
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| 285 | #define mmPCIE_UNCORR_ERR_MASK 0x56 |
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| 286 | #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 |
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| 287 | #define mmPCIE_CORR_ERR_STATUS 0x58 |
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| 288 | #define mmPCIE_CORR_ERR_MASK 0x59 |
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| 289 | #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a |
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| 290 | #define mmPCIE_HDR_LOG0 0x5b |
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| 291 | #define mmPCIE_HDR_LOG1 0x5c |
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| 292 | #define mmPCIE_HDR_LOG2 0x5d |
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| 293 | #define mmPCIE_HDR_LOG3 0x5e |
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| 294 | #define mmPCIE_TLP_PREFIX_LOG0 0x62 |
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| 295 | #define mmPCIE_TLP_PREFIX_LOG1 0x63 |
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| 296 | #define mmPCIE_TLP_PREFIX_LOG2 0x64 |
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| 297 | #define mmPCIE_TLP_PREFIX_LOG3 0x65 |
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| 298 | #define mmPCIE_BAR_ENH_CAP_LIST 0x80 |
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| 299 | #define mmPCIE_BAR1_CAP 0x81 |
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| 300 | #define mmPCIE_BAR1_CNTL 0x82 |
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| 301 | #define mmPCIE_BAR2_CAP 0x83 |
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| 302 | #define mmPCIE_BAR2_CNTL 0x84 |
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| 303 | #define mmPCIE_BAR3_CAP 0x85 |
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| 304 | #define mmPCIE_BAR3_CNTL 0x86 |
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| 305 | #define mmPCIE_BAR4_CAP 0x87 |
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| 306 | #define mmPCIE_BAR4_CNTL 0x88 |
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| 307 | #define mmPCIE_BAR5_CAP 0x89 |
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| 308 | #define mmPCIE_BAR5_CNTL 0x8a |
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| 309 | #define mmPCIE_BAR6_CAP 0x8b |
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| 310 | #define mmPCIE_BAR6_CNTL 0x8c |
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| 311 | #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 |
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| 312 | #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 |
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| 313 | #define mmPCIE_PWR_BUDGET_DATA 0x92 |
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| 314 | #define mmPCIE_PWR_BUDGET_CAP 0x93 |
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| 315 | #define mmPCIE_DPA_ENH_CAP_LIST 0x94 |
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| 316 | #define mmPCIE_DPA_CAP 0x95 |
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| 317 | #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 |
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| 318 | #define mmPCIE_DPA_STATUS 0x97 |
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| 319 | #define mmPCIE_DPA_CNTL 0x97 |
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| 320 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 |
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| 321 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 |
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| 322 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 |
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| 323 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 |
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| 324 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 |
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| 325 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 |
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| 326 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 |
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| 327 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 |
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| 328 | #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c |
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| 329 | #define mmPCIE_LINK_CNTL3 0x9d |
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| 330 | #define mmPCIE_LANE_ERROR_STATUS 0x9e |
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| 331 | #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f |
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| 332 | #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f |
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| 333 | #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 |
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| 334 | #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 |
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| 335 | #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 |
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| 336 | #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 |
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| 337 | #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 |
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| 338 | #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 |
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| 339 | #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 |
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| 340 | #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 |
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| 341 | #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 |
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| 342 | #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 |
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| 343 | #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 |
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| 344 | #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 |
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| 345 | #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 |
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| 346 | #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 |
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| 347 | #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 |
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| 348 | #define mmPCIE_ACS_CAP 0xa9 |
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| 349 | #define mmPCIE_ACS_CNTL 0xa9 |
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| 350 | #define mmPCIE_ATS_ENH_CAP_LIST 0xac |
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| 351 | #define mmPCIE_ATS_CAP 0xad |
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| 352 | #define mmPCIE_ATS_CNTL 0xad |
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| 353 | #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 |
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| 354 | #define mmPCIE_PAGE_REQ_CNTL 0xb1 |
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| 355 | #define mmPCIE_PAGE_REQ_STATUS 0xb1 |
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| 356 | #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 |
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| 357 | #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 |
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| 358 | #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 |
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| 359 | #define mmPCIE_PASID_CAP 0xb5 |
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| 360 | #define mmPCIE_PASID_CNTL 0xb5 |
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| 361 | #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 |
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| 362 | #define mmPCIE_TPH_REQR_CAP 0xb9 |
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| 363 | #define mmPCIE_TPH_REQR_CNTL 0xba |
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| 364 | #define mmPCIE_MC_ENH_CAP_LIST 0xbc |
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| 365 | #define mmPCIE_MC_CAP 0xbd |
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| 366 | #define mmPCIE_MC_CNTL 0xbd |
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| 367 | #define mmPCIE_MC_ADDR0 0xbe |
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| 368 | #define mmPCIE_MC_ADDR1 0xbf |
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| 369 | #define mmPCIE_MC_RCV0 0xc0 |
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| 370 | #define mmPCIE_MC_RCV1 0xc1 |
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| 371 | #define mmPCIE_MC_BLOCK_ALL0 0xc2 |
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| 372 | #define mmPCIE_MC_BLOCK_ALL1 0xc3 |
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| 373 | #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 |
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| 374 | #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 |
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| 375 | #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 |
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| 376 | #define mmPCIE_LTR_CAP 0xc9 |
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| 377 | #define mmPCIE_ARI_ENH_CAP_LIST 0xca |
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| 378 | #define mmPCIE_ARI_CAP 0xcb |
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| 379 | #define mmPCIE_ARI_CNTL 0xcb |
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| 380 | #define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc |
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| 381 | #define mmPCIE_SRIOV_CAP 0xcd |
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| 382 | #define mmPCIE_SRIOV_CONTROL 0xce |
|---|
| 383 | #define mmPCIE_SRIOV_STATUS 0xce |
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| 384 | #define mmPCIE_SRIOV_INITIAL_VFS 0xcf |
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| 385 | #define mmPCIE_SRIOV_TOTAL_VFS 0xcf |
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| 386 | #define mmPCIE_SRIOV_NUM_VFS 0xd0 |
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| 387 | #define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0 |
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| 388 | #define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1 |
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| 389 | #define mmPCIE_SRIOV_VF_STRIDE 0xd1 |
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| 390 | #define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2 |
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| 391 | #define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3 |
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| 392 | #define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4 |
|---|
| 393 | #define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5 |
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| 394 | #define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6 |
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| 395 | #define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7 |
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| 396 | #define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8 |
|---|
| 397 | #define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9 |
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| 398 | #define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda |
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| 399 | #define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb |
|---|
| 400 | #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100 |
|---|
| 401 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101 |
|---|
| 402 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102 |
|---|
| 403 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103 |
|---|
| 404 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104 |
|---|
| 405 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105 |
|---|
| 406 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106 |
|---|
| 407 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107 |
|---|
| 408 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108 |
|---|
| 409 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109 |
|---|
| 410 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a |
|---|
| 411 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b |
|---|
| 412 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c |
|---|
| 413 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d |
|---|
| 414 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e |
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| 415 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f |
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| 416 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110 |
|---|
| 417 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111 |
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| 418 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112 |
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| 419 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113 |
|---|
| 420 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114 |
|---|
| 421 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115 |
|---|
| 422 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116 |
|---|
| 423 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117 |
|---|
| 424 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118 |
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| 425 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119 |
|---|
| 426 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a |
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| 427 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b |
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| 428 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c |
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| 429 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d |
|---|
| 430 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e |
|---|
| 431 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f |
|---|
| 432 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120 |
|---|
| 433 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121 |
|---|
| 434 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122 |
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| 435 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124 |
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| 436 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125 |
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| 437 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126 |
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| 438 | #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127 |
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| 439 | #define mmPCIE_INDEX 0xe |
|---|
| 440 | #define mmPCIE_DATA 0xf |
|---|
| 441 | #define mmPCIE_INDEX_2 0xc |
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| 442 | #define mmPCIE_DATA_2 0xd |
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| 443 | #define ixPCIE_HOLD_TRAINING_A 0x1500820 |
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| 444 | #define ixLNCNT_CONTROL 0x1508030 |
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| 445 | #define ixCFG_LNC_WINDOW 0x1508031 |
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| 446 | #define ixLNCNT_QUAN_THRD 0x1508032 |
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| 447 | #define ixLNCNT_WEIGHT 0x1508033 |
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| 448 | #define ixLNC_TOTAL_WACC 0x1508034 |
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| 449 | #define ixLNC_BW_WACC 0x1508035 |
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| 450 | #define ixLNC_CMN_WACC 0x1508036 |
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| 451 | #define mmPCIE_EFUSE 0xfc0 |
|---|
| 452 | #define mmPCIE_EFUSE2 0xfc1 |
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| 453 | #define mmPCIE_EFUSE3 0xfc2 |
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| 454 | #define mmPCIE_EFUSE4 0xfc3 |
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| 455 | #define mmPCIE_EFUSE5 0xfc4 |
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| 456 | #define mmPCIE_EFUSE6 0xfc5 |
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| 457 | #define mmPCIE_EFUSE7 0xfc6 |
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| 458 | #define ixPCIE_WRAP_SCRATCH1 0x1308001 |
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| 459 | #define ixPCIE_WRAP_SCRATCH2 0x1308002 |
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| 460 | #define ixPCIE_WRAP_REG_TARG_MISC 0x1308005 |
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| 461 | #define ixPCIE_WRAP_DTM_MISC 0x1308006 |
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| 462 | #define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 |
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| 463 | #define ixPCIE_WRAP_MISC 0x1308008 |
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| 464 | #define ixPCIE_WRAP_PIF_MISC 0x1308009 |
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| 465 | #define ixPCIE_RXDET_OVERRIDE 0x130800a |
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| 466 | #define ixREG_ADAPT_pciecore0_CONTROL 0x1308090 |
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| 467 | #define ixREG_ADAPT_pwregt_CONTROL 0x1308096 |
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| 468 | #define ixREG_ADAPT_pwregr_CONTROL 0x1308097 |
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| 469 | #define ixREG_ADAPT_pif0_CONTROL 0x1308098 |
|---|
| 470 | #define ixPCIE_RESERVED 0x1400000 |
|---|
| 471 | #define ixPCIE_SCRATCH 0x1400001 |
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| 472 | #define ixPCIE_HW_DEBUG 0x1400002 |
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| 473 | #define ixPCIE_RX_NUM_NAK 0x140000e |
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| 474 | #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f |
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| 475 | #define ixPCIE_CNTL 0x1400010 |
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| 476 | #define ixPCIE_CONFIG_CNTL 0x1400011 |
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| 477 | #define ixPCIE_DEBUG_CNTL 0x1400012 |
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| 478 | #define ixPCIE_INT_CNTL 0x140001a |
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| 479 | #define ixPCIE_INT_STATUS 0x140001b |
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| 480 | #define ixPCIE_CNTL2 0x140001c |
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| 481 | #define ixPCIE_RX_CNTL2 0x140001d |
|---|
| 482 | #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e |
|---|
| 483 | #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f |
|---|
| 484 | #define ixPCIE_CI_CNTL 0x1400020 |
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| 485 | #define ixPCIE_BUS_CNTL 0x1400021 |
|---|
| 486 | #define ixPCIE_LC_STATE6 0x1400022 |
|---|
| 487 | #define ixPCIE_LC_STATE7 0x1400023 |
|---|
| 488 | #define ixPCIE_LC_STATE8 0x1400024 |
|---|
| 489 | #define ixPCIE_LC_STATE9 0x1400025 |
|---|
| 490 | #define ixPCIE_LC_STATE10 0x1400026 |
|---|
| 491 | #define ixPCIE_LC_STATE11 0x1400027 |
|---|
| 492 | #define ixPCIE_LC_STATUS1 0x1400028 |
|---|
| 493 | #define ixPCIE_LC_STATUS2 0x1400029 |
|---|
| 494 | #define ixPCIE_WPR_CNTL 0x1400030 |
|---|
| 495 | #define ixPCIE_RX_LAST_TLP0 0x1400031 |
|---|
| 496 | #define ixPCIE_RX_LAST_TLP1 0x1400032 |
|---|
| 497 | #define ixPCIE_RX_LAST_TLP2 0x1400033 |
|---|
| 498 | #define ixPCIE_RX_LAST_TLP3 0x1400034 |
|---|
| 499 | #define ixPCIE_TX_LAST_TLP0 0x1400035 |
|---|
| 500 | #define ixPCIE_TX_LAST_TLP1 0x1400036 |
|---|
| 501 | #define ixPCIE_TX_LAST_TLP2 0x1400037 |
|---|
| 502 | #define ixPCIE_TX_LAST_TLP3 0x1400038 |
|---|
| 503 | #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a |
|---|
| 504 | #define ixPCIE_I2C_REG_DATA 0x140003b |
|---|
| 505 | #define ixPCIE_CFG_CNTL 0x140003c |
|---|
| 506 | #define ixPCIE_LC_PM_CNTL 0x140003d |
|---|
| 507 | #define ixPCIE_P_CNTL 0x1400040 |
|---|
| 508 | #define ixPCIE_P_BUF_STATUS 0x1400041 |
|---|
| 509 | #define ixPCIE_P_DECODER_STATUS 0x1400042 |
|---|
| 510 | #define ixPCIE_P_MISC_STATUS 0x1400043 |
|---|
| 511 | #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 |
|---|
| 512 | #define ixPCIE_OBFF_CNTL 0x1400061 |
|---|
| 513 | #define ixPCIE_TX_LTR_CNTL 0x1400060 |
|---|
| 514 | #define ixPCIE_IDLE_STATUS 0x1400062 |
|---|
| 515 | #define ixPCIE_PERF_COUNT_CNTL 0x1400080 |
|---|
| 516 | #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 |
|---|
| 517 | #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 |
|---|
| 518 | #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 |
|---|
| 519 | #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 |
|---|
| 520 | #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 |
|---|
| 521 | #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 |
|---|
| 522 | #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 |
|---|
| 523 | #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 |
|---|
| 524 | #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 |
|---|
| 525 | #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a |
|---|
| 526 | #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b |
|---|
| 527 | #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c |
|---|
| 528 | #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d |
|---|
| 529 | #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e |
|---|
| 530 | #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f |
|---|
| 531 | #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 |
|---|
| 532 | #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 |
|---|
| 533 | #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 |
|---|
| 534 | #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 |
|---|
| 535 | #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 |
|---|
| 536 | #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 |
|---|
| 537 | #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 |
|---|
| 538 | #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 |
|---|
| 539 | #define ixPCIE_STRAP_F0 0x14000b0 |
|---|
| 540 | #define ixPCIE_STRAP_F1 0x14000b1 |
|---|
| 541 | #define ixPCIE_STRAP_F2 0x14000b2 |
|---|
| 542 | #define ixPCIE_STRAP_F3 0x14000b3 |
|---|
| 543 | #define ixPCIE_STRAP_F4 0x14000b4 |
|---|
| 544 | #define ixPCIE_STRAP_F5 0x14000b5 |
|---|
| 545 | #define ixPCIE_STRAP_F6 0x14000b6 |
|---|
| 546 | #define ixPCIE_STRAP_MSIX 0x14000b7 |
|---|
| 547 | #define ixPCIE_STRAP_MISC 0x14000c0 |
|---|
| 548 | #define ixPCIE_STRAP_MISC2 0x14000c1 |
|---|
| 549 | #define ixPCIE_STRAP_PI 0x14000c2 |
|---|
| 550 | #define ixPCIE_STRAP_I2C_BD 0x14000c4 |
|---|
| 551 | #define ixPCIE_PRBS_CLR 0x14000c8 |
|---|
| 552 | #define ixPCIE_PRBS_STATUS1 0x14000c9 |
|---|
| 553 | #define ixPCIE_PRBS_STATUS2 0x14000ca |
|---|
| 554 | #define ixPCIE_PRBS_FREERUN 0x14000cb |
|---|
| 555 | #define ixPCIE_PRBS_MISC 0x14000cc |
|---|
| 556 | #define ixPCIE_PRBS_USER_PATTERN 0x14000cd |
|---|
| 557 | #define ixPCIE_PRBS_LO_BITCNT 0x14000ce |
|---|
| 558 | #define ixPCIE_PRBS_HI_BITCNT 0x14000cf |
|---|
| 559 | #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 |
|---|
| 560 | #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 |
|---|
| 561 | #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 |
|---|
| 562 | #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 |
|---|
| 563 | #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 |
|---|
| 564 | #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 |
|---|
| 565 | #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 |
|---|
| 566 | #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 |
|---|
| 567 | #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 |
|---|
| 568 | #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 |
|---|
| 569 | #define ixPCIE_PRBS_ERRCNT_10 0x14000da |
|---|
| 570 | #define ixPCIE_PRBS_ERRCNT_11 0x14000db |
|---|
| 571 | #define ixPCIE_PRBS_ERRCNT_12 0x14000dc |
|---|
| 572 | #define ixPCIE_PRBS_ERRCNT_13 0x14000dd |
|---|
| 573 | #define ixPCIE_PRBS_ERRCNT_14 0x14000de |
|---|
| 574 | #define ixPCIE_PRBS_ERRCNT_15 0x14000df |
|---|
| 575 | #define ixPCIE_F0_DPA_CAP 0x14000e0 |
|---|
| 576 | #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 |
|---|
| 577 | #define ixPCIE_F0_DPA_CNTL 0x14000e5 |
|---|
| 578 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 |
|---|
| 579 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 |
|---|
| 580 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 |
|---|
| 581 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea |
|---|
| 582 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb |
|---|
| 583 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec |
|---|
| 584 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed |
|---|
| 585 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee |
|---|
| 586 | #define mmSWRST_COMMAND_STATUS 0x14a0 |
|---|
| 587 | #define mmSWRST_GENERAL_CONTROL 0x14a1 |
|---|
| 588 | #define mmSWRST_COMMAND_0 0x14a2 |
|---|
| 589 | #define mmSWRST_COMMAND_1 0x14a3 |
|---|
| 590 | #define mmSWRST_CONTROL_0 0x14a4 |
|---|
| 591 | #define mmSWRST_CONTROL_1 0x14a5 |
|---|
| 592 | #define mmSWRST_CONTROL_2 0x14a6 |
|---|
| 593 | #define mmSWRST_CONTROL_3 0x14a7 |
|---|
| 594 | #define mmSWRST_CONTROL_4 0x14a8 |
|---|
| 595 | #define mmSWRST_CONTROL_5 0x14a9 |
|---|
| 596 | #define mmSWRST_CONTROL_6 0x14aa |
|---|
| 597 | #define mmSWRST_EP_COMMAND_0 0x14ab |
|---|
| 598 | #define mmSWRST_EP_CONTROL_0 0x14ac |
|---|
| 599 | #define mmCPM_CONTROL 0x14b8 |
|---|
| 600 | #define mmGSKT_CONTROL 0x14bf |
|---|
| 601 | #define ixSWRST_COMMAND_1 0x1400103 |
|---|
| 602 | #define ixLM_CONTROL 0x1400120 |
|---|
| 603 | #define ixLM_PCIETXMUX0 0x1400121 |
|---|
| 604 | #define ixLM_PCIETXMUX1 0x1400122 |
|---|
| 605 | #define ixLM_PCIETXMUX2 0x1400123 |
|---|
| 606 | #define ixLM_PCIETXMUX3 0x1400124 |
|---|
| 607 | #define ixLM_PCIERXMUX0 0x1400125 |
|---|
| 608 | #define ixLM_PCIERXMUX1 0x1400126 |
|---|
| 609 | #define ixLM_PCIERXMUX2 0x1400127 |
|---|
| 610 | #define ixLM_PCIERXMUX3 0x1400128 |
|---|
| 611 | #define ixLM_LANEENABLE 0x1400129 |
|---|
| 612 | #define ixLM_PRBSCONTROL 0x140012a |
|---|
| 613 | #define ixLM_POWERCONTROL 0x140012b |
|---|
| 614 | #define ixLM_POWERCONTROL1 0x140012c |
|---|
| 615 | #define ixLM_POWERCONTROL2 0x140012d |
|---|
| 616 | #define ixLM_POWERCONTROL3 0x140012e |
|---|
| 617 | #define ixLM_POWERCONTROL4 0x140012f |
|---|
| 618 | #define ixPB0_GLB_CTRL_REG0 0x1200004 |
|---|
| 619 | #define ixPB0_GLB_CTRL_REG1 0x1200008 |
|---|
| 620 | #define ixPB0_GLB_CTRL_REG2 0x120000c |
|---|
| 621 | #define ixPB0_GLB_CTRL_REG3 0x1200010 |
|---|
| 622 | #define ixPB0_GLB_CTRL_REG4 0x1200014 |
|---|
| 623 | #define ixPB0_GLB_CTRL_REG5 0x1200018 |
|---|
| 624 | #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c |
|---|
| 625 | #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020 |
|---|
| 626 | #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024 |
|---|
| 627 | #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028 |
|---|
| 628 | #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c |
|---|
| 629 | #define ixPB0_GLB_OVRD_REG0 0x1200030 |
|---|
| 630 | #define ixPB0_GLB_OVRD_REG1 0x1200034 |
|---|
| 631 | #define ixPB0_GLB_OVRD_REG2 0x1200038 |
|---|
| 632 | #define ixPB0_HW_DEBUG 0x1202004 |
|---|
| 633 | #define ixPB0_STRAP_GLB_REG0 0x1202020 |
|---|
| 634 | #define ixPB0_STRAP_TX_REG0 0x1202024 |
|---|
| 635 | #define ixPB0_STRAP_RX_REG0 0x1202028 |
|---|
| 636 | #define ixPB0_STRAP_RX_REG1 0x120202c |
|---|
| 637 | #define ixPB0_STRAP_PLL_REG0 0x1202030 |
|---|
| 638 | #define ixPB0_STRAP_PIN_REG0 0x1202034 |
|---|
| 639 | #define ixPB0_STRAP_GLB_REG1 0x1202038 |
|---|
| 640 | #define ixPB0_STRAP_GLB_REG2 0x120203c |
|---|
| 641 | #define ixPB0_DFT_JIT_INJ_REG0 0x1203000 |
|---|
| 642 | #define ixPB0_DFT_JIT_INJ_REG1 0x1203004 |
|---|
| 643 | #define ixPB0_DFT_JIT_INJ_REG2 0x1203008 |
|---|
| 644 | #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c |
|---|
| 645 | #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010 |
|---|
| 646 | #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000 |
|---|
| 647 | #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010 |
|---|
| 648 | #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440 |
|---|
| 649 | #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450 |
|---|
| 650 | #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454 |
|---|
| 651 | #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460 |
|---|
| 652 | #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464 |
|---|
| 653 | #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468 |
|---|
| 654 | #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c |
|---|
| 655 | #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480 |
|---|
| 656 | #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490 |
|---|
| 657 | #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494 |
|---|
| 658 | #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500 |
|---|
| 659 | #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504 |
|---|
| 660 | #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508 |
|---|
| 661 | #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c |
|---|
| 662 | #define ixPB0_RX_GLB_CTRL_REG0 0x1206000 |
|---|
| 663 | #define ixPB0_RX_GLB_CTRL_REG1 0x1206004 |
|---|
| 664 | #define ixPB0_RX_GLB_CTRL_REG2 0x1206008 |
|---|
| 665 | #define ixPB0_RX_GLB_CTRL_REG3 0x120600c |
|---|
| 666 | #define ixPB0_RX_GLB_CTRL_REG4 0x1206010 |
|---|
| 667 | #define ixPB0_RX_GLB_CTRL_REG5 0x1206014 |
|---|
| 668 | #define ixPB0_RX_GLB_CTRL_REG6 0x1206018 |
|---|
| 669 | #define ixPB0_RX_GLB_CTRL_REG7 0x120601c |
|---|
| 670 | #define ixPB0_RX_GLB_CTRL_REG8 0x1206020 |
|---|
| 671 | #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028 |
|---|
| 672 | #define ixPB0_RX_GLB_OVRD_REG0 0x1206030 |
|---|
| 673 | #define ixPB0_RX_GLB_OVRD_REG1 0x1206034 |
|---|
| 674 | #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440 |
|---|
| 675 | #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448 |
|---|
| 676 | #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480 |
|---|
| 677 | #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488 |
|---|
| 678 | #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500 |
|---|
| 679 | #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508 |
|---|
| 680 | #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600 |
|---|
| 681 | #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608 |
|---|
| 682 | #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800 |
|---|
| 683 | #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848 |
|---|
| 684 | #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880 |
|---|
| 685 | #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888 |
|---|
| 686 | #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900 |
|---|
| 687 | #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908 |
|---|
| 688 | #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00 |
|---|
| 689 | #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08 |
|---|
| 690 | #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440 |
|---|
| 691 | #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448 |
|---|
| 692 | #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480 |
|---|
| 693 | #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488 |
|---|
| 694 | #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500 |
|---|
| 695 | #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508 |
|---|
| 696 | #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600 |
|---|
| 697 | #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608 |
|---|
| 698 | #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840 |
|---|
| 699 | #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848 |
|---|
| 700 | #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880 |
|---|
| 701 | #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888 |
|---|
| 702 | #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900 |
|---|
| 703 | #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908 |
|---|
| 704 | #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00 |
|---|
| 705 | #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08 |
|---|
| 706 | #define ixPB0_TX_GLB_CTRL_REG0 0x1208000 |
|---|
| 707 | #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004 |
|---|
| 708 | #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010 |
|---|
| 709 | #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014 |
|---|
| 710 | #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018 |
|---|
| 711 | #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c |
|---|
| 712 | #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020 |
|---|
| 713 | #define ixPB0_TX_GLB_OVRD_REG0 0x1208030 |
|---|
| 714 | #define ixPB0_TX_GLB_OVRD_REG1 0x1208034 |
|---|
| 715 | #define ixPB0_TX_GLB_OVRD_REG2 0x1208038 |
|---|
| 716 | #define ixPB0_TX_GLB_OVRD_REG3 0x120803c |
|---|
| 717 | #define ixPB0_TX_GLB_OVRD_REG4 0x1208040 |
|---|
| 718 | #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440 |
|---|
| 719 | #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444 |
|---|
| 720 | #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448 |
|---|
| 721 | #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480 |
|---|
| 722 | #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484 |
|---|
| 723 | #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488 |
|---|
| 724 | #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500 |
|---|
| 725 | #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504 |
|---|
| 726 | #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508 |
|---|
| 727 | #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600 |
|---|
| 728 | #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604 |
|---|
| 729 | #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608 |
|---|
| 730 | #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840 |
|---|
| 731 | #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844 |
|---|
| 732 | #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848 |
|---|
| 733 | #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880 |
|---|
| 734 | #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884 |
|---|
| 735 | #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888 |
|---|
| 736 | #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900 |
|---|
| 737 | #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904 |
|---|
| 738 | #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908 |
|---|
| 739 | #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00 |
|---|
| 740 | #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04 |
|---|
| 741 | #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08 |
|---|
| 742 | #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440 |
|---|
| 743 | #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444 |
|---|
| 744 | #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448 |
|---|
| 745 | #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480 |
|---|
| 746 | #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484 |
|---|
| 747 | #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488 |
|---|
| 748 | #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500 |
|---|
| 749 | #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504 |
|---|
| 750 | #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508 |
|---|
| 751 | #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600 |
|---|
| 752 | #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604 |
|---|
| 753 | #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608 |
|---|
| 754 | #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840 |
|---|
| 755 | #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844 |
|---|
| 756 | #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848 |
|---|
| 757 | #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880 |
|---|
| 758 | #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884 |
|---|
| 759 | #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888 |
|---|
| 760 | #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900 |
|---|
| 761 | #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904 |
|---|
| 762 | #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908 |
|---|
| 763 | #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00 |
|---|
| 764 | #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04 |
|---|
| 765 | #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08 |
|---|
| 766 | #define ixPB1_GLB_CTRL_REG0 0x2200004 |
|---|
| 767 | #define ixPB1_GLB_CTRL_REG1 0x2200008 |
|---|
| 768 | #define ixPB1_GLB_CTRL_REG2 0x220000c |
|---|
| 769 | #define ixPB1_GLB_CTRL_REG3 0x2200010 |
|---|
| 770 | #define ixPB1_GLB_CTRL_REG4 0x2200014 |
|---|
| 771 | #define ixPB1_GLB_CTRL_REG5 0x2200018 |
|---|
| 772 | #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c |
|---|
| 773 | #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020 |
|---|
| 774 | #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024 |
|---|
| 775 | #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028 |
|---|
| 776 | #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c |
|---|
| 777 | #define ixPB1_GLB_OVRD_REG0 0x2200030 |
|---|
| 778 | #define ixPB1_GLB_OVRD_REG1 0x2200034 |
|---|
| 779 | #define ixPB1_GLB_OVRD_REG2 0x2200038 |
|---|
| 780 | #define ixPB1_HW_DEBUG 0x2202004 |
|---|
| 781 | #define ixPB1_STRAP_GLB_REG0 0x2202020 |
|---|
| 782 | #define ixPB1_STRAP_TX_REG0 0x2202024 |
|---|
| 783 | #define ixPB1_STRAP_RX_REG0 0x2202028 |
|---|
| 784 | #define ixPB1_STRAP_RX_REG1 0x220202c |
|---|
| 785 | #define ixPB1_STRAP_PLL_REG0 0x2202030 |
|---|
| 786 | #define ixPB1_STRAP_PIN_REG0 0x2202034 |
|---|
| 787 | #define ixPB1_STRAP_GLB_REG1 0x2202038 |
|---|
| 788 | #define ixPB1_STRAP_GLB_REG2 0x220203c |
|---|
| 789 | #define ixPB1_DFT_JIT_INJ_REG0 0x2203000 |
|---|
| 790 | #define ixPB1_DFT_JIT_INJ_REG1 0x2203004 |
|---|
| 791 | #define ixPB1_DFT_JIT_INJ_REG2 0x2203008 |
|---|
| 792 | #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c |
|---|
| 793 | #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010 |
|---|
| 794 | #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000 |
|---|
| 795 | #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010 |
|---|
| 796 | #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440 |
|---|
| 797 | #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450 |
|---|
| 798 | #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454 |
|---|
| 799 | #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460 |
|---|
| 800 | #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464 |
|---|
| 801 | #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468 |
|---|
| 802 | #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c |
|---|
| 803 | #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480 |
|---|
| 804 | #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490 |
|---|
| 805 | #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494 |
|---|
| 806 | #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500 |
|---|
| 807 | #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504 |
|---|
| 808 | #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508 |
|---|
| 809 | #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c |
|---|
| 810 | #define ixPB1_RX_GLB_CTRL_REG0 0x2206000 |
|---|
| 811 | #define ixPB1_RX_GLB_CTRL_REG1 0x2206004 |
|---|
| 812 | #define ixPB1_RX_GLB_CTRL_REG2 0x2206008 |
|---|
| 813 | #define ixPB1_RX_GLB_CTRL_REG3 0x220600c |
|---|
| 814 | #define ixPB1_RX_GLB_CTRL_REG4 0x2206010 |
|---|
| 815 | #define ixPB1_RX_GLB_CTRL_REG5 0x2206014 |
|---|
| 816 | #define ixPB1_RX_GLB_CTRL_REG6 0x2206018 |
|---|
| 817 | #define ixPB1_RX_GLB_CTRL_REG7 0x220601c |
|---|
| 818 | #define ixPB1_RX_GLB_CTRL_REG8 0x2206020 |
|---|
| 819 | #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028 |
|---|
| 820 | #define ixPB1_RX_GLB_OVRD_REG0 0x2206030 |
|---|
| 821 | #define ixPB1_RX_GLB_OVRD_REG1 0x2206034 |
|---|
| 822 | #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440 |
|---|
| 823 | #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448 |
|---|
| 824 | #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480 |
|---|
| 825 | #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488 |
|---|
| 826 | #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500 |
|---|
| 827 | #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508 |
|---|
| 828 | #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600 |
|---|
| 829 | #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608 |
|---|
| 830 | #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800 |
|---|
| 831 | #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848 |
|---|
| 832 | #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880 |
|---|
| 833 | #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888 |
|---|
| 834 | #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900 |
|---|
| 835 | #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908 |
|---|
| 836 | #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00 |
|---|
| 837 | #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08 |
|---|
| 838 | #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440 |
|---|
| 839 | #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448 |
|---|
| 840 | #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480 |
|---|
| 841 | #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488 |
|---|
| 842 | #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500 |
|---|
| 843 | #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508 |
|---|
| 844 | #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600 |
|---|
| 845 | #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608 |
|---|
| 846 | #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840 |
|---|
| 847 | #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848 |
|---|
| 848 | #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880 |
|---|
| 849 | #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888 |
|---|
| 850 | #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900 |
|---|
| 851 | #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908 |
|---|
| 852 | #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00 |
|---|
| 853 | #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08 |
|---|
| 854 | #define ixPB1_TX_GLB_CTRL_REG0 0x2208000 |
|---|
| 855 | #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004 |
|---|
| 856 | #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010 |
|---|
| 857 | #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014 |
|---|
| 858 | #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018 |
|---|
| 859 | #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c |
|---|
| 860 | #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020 |
|---|
| 861 | #define ixPB1_TX_GLB_OVRD_REG0 0x2208030 |
|---|
| 862 | #define ixPB1_TX_GLB_OVRD_REG1 0x2208034 |
|---|
| 863 | #define ixPB1_TX_GLB_OVRD_REG2 0x2208038 |
|---|
| 864 | #define ixPB1_TX_GLB_OVRD_REG3 0x220803c |
|---|
| 865 | #define ixPB1_TX_GLB_OVRD_REG4 0x2208040 |
|---|
| 866 | #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440 |
|---|
| 867 | #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444 |
|---|
| 868 | #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448 |
|---|
| 869 | #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480 |
|---|
| 870 | #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484 |
|---|
| 871 | #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488 |
|---|
| 872 | #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500 |
|---|
| 873 | #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504 |
|---|
| 874 | #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508 |
|---|
| 875 | #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600 |
|---|
| 876 | #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604 |
|---|
| 877 | #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608 |
|---|
| 878 | #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840 |
|---|
| 879 | #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844 |
|---|
| 880 | #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848 |
|---|
| 881 | #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880 |
|---|
| 882 | #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884 |
|---|
| 883 | #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888 |
|---|
| 884 | #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900 |
|---|
| 885 | #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904 |
|---|
| 886 | #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908 |
|---|
| 887 | #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00 |
|---|
| 888 | #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04 |
|---|
| 889 | #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08 |
|---|
| 890 | #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440 |
|---|
| 891 | #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444 |
|---|
| 892 | #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448 |
|---|
| 893 | #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480 |
|---|
| 894 | #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484 |
|---|
| 895 | #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488 |
|---|
| 896 | #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500 |
|---|
| 897 | #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504 |
|---|
| 898 | #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508 |
|---|
| 899 | #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600 |
|---|
| 900 | #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604 |
|---|
| 901 | #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608 |
|---|
| 902 | #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840 |
|---|
| 903 | #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844 |
|---|
| 904 | #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848 |
|---|
| 905 | #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880 |
|---|
| 906 | #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884 |
|---|
| 907 | #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888 |
|---|
| 908 | #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900 |
|---|
| 909 | #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904 |
|---|
| 910 | #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908 |
|---|
| 911 | #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00 |
|---|
| 912 | #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04 |
|---|
| 913 | #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08 |
|---|
| 914 | #define ixPB0_PIF_SCRATCH 0x1100001 |
|---|
| 915 | #define ixPB0_PIF_HW_DEBUG 0x1100002 |
|---|
| 916 | #define ixPB0_PIF_STRAP_0 0x1100003 |
|---|
| 917 | #define ixPB0_PIF_CTRL 0x1100004 |
|---|
| 918 | #define ixPB0_PIF_TX_CTRL 0x1100008 |
|---|
| 919 | #define ixPB0_PIF_TX_CTRL2 0x1100009 |
|---|
| 920 | #define ixPB0_PIF_RX_CTRL 0x110000a |
|---|
| 921 | #define ixPB0_PIF_RX_CTRL2 0x110000b |
|---|
| 922 | #define ixPB0_PIF_GLB_OVRD 0x110000c |
|---|
| 923 | #define ixPB0_PIF_GLB_OVRD2 0x110000d |
|---|
| 924 | #define ixPB0_PIF_BIF_CMD_STATUS 0x1100010 |
|---|
| 925 | #define ixPB0_PIF_CMD_BUS_CTRL 0x1100011 |
|---|
| 926 | #define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013 |
|---|
| 927 | #define ixPB0_PIF_LANE0_OVRD 0x1100014 |
|---|
| 928 | #define ixPB0_PIF_LANE0_OVRD2 0x1100015 |
|---|
| 929 | #define ixPB0_PIF_LANE1_OVRD 0x1100016 |
|---|
| 930 | #define ixPB0_PIF_LANE1_OVRD2 0x1100017 |
|---|
| 931 | #define ixPB0_PIF_LANE2_OVRD 0x1100018 |
|---|
| 932 | #define ixPB0_PIF_LANE2_OVRD2 0x1100019 |
|---|
| 933 | #define ixPB0_PIF_LANE3_OVRD 0x110001a |
|---|
| 934 | #define ixPB0_PIF_LANE3_OVRD2 0x110001b |
|---|
| 935 | #define ixPB0_PIF_LANE4_OVRD 0x110001c |
|---|
| 936 | #define ixPB0_PIF_LANE4_OVRD2 0x110001d |
|---|
| 937 | #define ixPB0_PIF_LANE5_OVRD 0x110001e |
|---|
| 938 | #define ixPB0_PIF_LANE5_OVRD2 0x110001f |
|---|
| 939 | #define ixPB0_PIF_LANE6_OVRD 0x1100020 |
|---|
| 940 | #define ixPB0_PIF_LANE6_OVRD2 0x1100021 |
|---|
| 941 | #define ixPB0_PIF_LANE7_OVRD 0x1100022 |
|---|
| 942 | #define ixPB0_PIF_LANE7_OVRD2 0x1100023 |
|---|
| 943 | #define ixPB1_PIF_SCRATCH 0x2100001 |
|---|
| 944 | #define ixPB1_PIF_HW_DEBUG 0x2100002 |
|---|
| 945 | #define ixPB1_PIF_STRAP_0 0x2100003 |
|---|
| 946 | #define ixPB1_PIF_CTRL 0x2100004 |
|---|
| 947 | #define ixPB1_PIF_TX_CTRL 0x2100008 |
|---|
| 948 | #define ixPB1_PIF_TX_CTRL2 0x2100009 |
|---|
| 949 | #define ixPB1_PIF_RX_CTRL 0x210000a |
|---|
| 950 | #define ixPB1_PIF_RX_CTRL2 0x210000b |
|---|
| 951 | #define ixPB1_PIF_GLB_OVRD 0x210000c |
|---|
| 952 | #define ixPB1_PIF_GLB_OVRD2 0x210000d |
|---|
| 953 | #define ixPB1_PIF_BIF_CMD_STATUS 0x2100010 |
|---|
| 954 | #define ixPB1_PIF_CMD_BUS_CTRL 0x2100011 |
|---|
| 955 | #define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013 |
|---|
| 956 | #define ixPB1_PIF_LANE0_OVRD 0x2100014 |
|---|
| 957 | #define ixPB1_PIF_LANE0_OVRD2 0x2100015 |
|---|
| 958 | #define ixPB1_PIF_LANE1_OVRD 0x2100016 |
|---|
| 959 | #define ixPB1_PIF_LANE1_OVRD2 0x2100017 |
|---|
| 960 | #define ixPB1_PIF_LANE2_OVRD 0x2100018 |
|---|
| 961 | #define ixPB1_PIF_LANE2_OVRD2 0x2100019 |
|---|
| 962 | #define ixPB1_PIF_LANE3_OVRD 0x210001a |
|---|
| 963 | #define ixPB1_PIF_LANE3_OVRD2 0x210001b |
|---|
| 964 | #define ixPB1_PIF_LANE4_OVRD 0x210001c |
|---|
| 965 | #define ixPB1_PIF_LANE4_OVRD2 0x210001d |
|---|
| 966 | #define ixPB1_PIF_LANE5_OVRD 0x210001e |
|---|
| 967 | #define ixPB1_PIF_LANE5_OVRD2 0x210001f |
|---|
| 968 | #define ixPB1_PIF_LANE6_OVRD 0x2100020 |
|---|
| 969 | #define ixPB1_PIF_LANE6_OVRD2 0x2100021 |
|---|
| 970 | #define ixPB1_PIF_LANE7_OVRD 0x2100022 |
|---|
| 971 | #define ixPB1_PIF_LANE7_OVRD2 0x2100023 |
|---|
| 972 | #define ixPCIEP_RESERVED 0x10010000 |
|---|
| 973 | #define ixPCIEP_SCRATCH 0x10010001 |
|---|
| 974 | #define ixPCIEP_HW_DEBUG 0x10010002 |
|---|
| 975 | #define ixPCIEP_PORT_CNTL 0x10010010 |
|---|
| 976 | #define ixPCIE_TX_CNTL 0x10010020 |
|---|
| 977 | #define ixPCIE_TX_REQUESTER_ID 0x10010021 |
|---|
| 978 | #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 |
|---|
| 979 | #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 |
|---|
| 980 | #define ixPCIE_TX_SEQ 0x10010024 |
|---|
| 981 | #define ixPCIE_TX_REPLAY 0x10010025 |
|---|
| 982 | #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 |
|---|
| 983 | #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 |
|---|
| 984 | #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 |
|---|
| 985 | #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 |
|---|
| 986 | #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 |
|---|
| 987 | #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 |
|---|
| 988 | #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 |
|---|
| 989 | #define ixPCIE_TX_CREDITS_STATUS 0x10010036 |
|---|
| 990 | #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 |
|---|
| 991 | #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 |
|---|
| 992 | #define ixPCIE_FC_P 0x10010060 |
|---|
| 993 | #define ixPCIE_FC_NP 0x10010061 |
|---|
| 994 | #define ixPCIE_FC_CPL 0x10010062 |
|---|
| 995 | #define ixPCIE_ERR_CNTL 0x1001006a |
|---|
| 996 | #define ixPCIE_RX_CNTL 0x10010070 |
|---|
| 997 | #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 |
|---|
| 998 | #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 |
|---|
| 999 | #define ixPCIE_RX_CNTL3 0x10010074 |
|---|
| 1000 | #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 |
|---|
| 1001 | #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 |
|---|
| 1002 | #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 |
|---|
| 1003 | #define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083 |
|---|
| 1004 | #define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084 |
|---|
| 1005 | #define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085 |
|---|
| 1006 | #define ixPCIE_LC_CNTL 0x100100a0 |
|---|
| 1007 | #define ixPCIE_LC_CNTL2 0x100100b1 |
|---|
| 1008 | #define ixPCIE_LC_CNTL3 0x100100b5 |
|---|
| 1009 | #define ixPCIE_LC_CNTL4 0x100100b6 |
|---|
| 1010 | #define ixPCIE_LC_CNTL5 0x100100b7 |
|---|
| 1011 | #define ixPCIE_LC_CNTL6 0x100100bb |
|---|
| 1012 | #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 |
|---|
| 1013 | #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 |
|---|
| 1014 | #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 |
|---|
| 1015 | #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 |
|---|
| 1016 | #define ixPCIE_LC_SPEED_CNTL 0x100100a4 |
|---|
| 1017 | #define ixPCIE_LC_CDR_CNTL 0x100100b3 |
|---|
| 1018 | #define ixPCIE_LC_LANE_CNTL 0x100100b4 |
|---|
| 1019 | #define ixPCIE_LC_FORCE_COEFF 0x100100b8 |
|---|
| 1020 | #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 |
|---|
| 1021 | #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba |
|---|
| 1022 | #define ixPCIE_LC_STATE0 0x100100a5 |
|---|
| 1023 | #define ixPCIE_LC_STATE1 0x100100a6 |
|---|
| 1024 | #define ixPCIE_LC_STATE2 0x100100a7 |
|---|
| 1025 | #define ixPCIE_LC_STATE3 0x100100a8 |
|---|
| 1026 | #define ixPCIE_LC_STATE4 0x100100a9 |
|---|
| 1027 | #define ixPCIE_LC_STATE5 0x100100aa |
|---|
| 1028 | #define ixPCIEP_STRAP_LC 0x100100c0 |
|---|
| 1029 | #define ixPCIEP_STRAP_MISC 0x100100c1 |
|---|
| 1030 | #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 |
|---|
| 1031 | #define ixPCIEP_HPGI_PRIVATE 0x100100d2 |
|---|
| 1032 | #define ixPCIEP_HPGI 0x100100da |
|---|
| 1033 | #define mmPCIEMSIX_VECT0_ADDR_LO 0x6000 |
|---|
| 1034 | #define mmPCIEMSIX_VECT0_ADDR_HI 0x6001 |
|---|
| 1035 | #define mmPCIEMSIX_VECT0_MSG_DATA 0x6002 |
|---|
| 1036 | #define mmPCIEMSIX_VECT0_CONTROL 0x6003 |
|---|
| 1037 | #define mmPCIEMSIX_VECT1_ADDR_LO 0x6004 |
|---|
| 1038 | #define mmPCIEMSIX_VECT1_ADDR_HI 0x6005 |
|---|
| 1039 | #define mmPCIEMSIX_VECT1_MSG_DATA 0x6006 |
|---|
| 1040 | #define mmPCIEMSIX_VECT1_CONTROL 0x6007 |
|---|
| 1041 | #define mmPCIEMSIX_VECT2_ADDR_LO 0x6008 |
|---|
| 1042 | #define mmPCIEMSIX_VECT2_ADDR_HI 0x6009 |
|---|
| 1043 | #define mmPCIEMSIX_VECT2_MSG_DATA 0x600a |
|---|
| 1044 | #define mmPCIEMSIX_VECT2_CONTROL 0x600b |
|---|
| 1045 | #define mmPCIEMSIX_VECT3_ADDR_LO 0x600c |
|---|
| 1046 | #define mmPCIEMSIX_VECT3_ADDR_HI 0x600d |
|---|
| 1047 | #define mmPCIEMSIX_VECT3_MSG_DATA 0x600e |
|---|
| 1048 | #define mmPCIEMSIX_VECT3_CONTROL 0x600f |
|---|
| 1049 | #define mmPCIEMSIX_PBA 0x6200 |
|---|
| 1050 | #define mmBIF_RFE_SNOOP_REG 0x27 |
|---|
| 1051 | #define mmBIF_RFE_WARMRST_CNTL 0x1459 |
|---|
| 1052 | #define mmBIF_RFE_SOFTRST_CNTL 0x1441 |
|---|
| 1053 | #define mmBIF_RFE_IMPRST_CNTL 0x1458 |
|---|
| 1054 | #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 |
|---|
| 1055 | #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 |
|---|
| 1056 | #define mmBIF_PWDN_COMMAND 0x1444 |
|---|
| 1057 | #define mmBIF_PWDN_STATUS 0x1445 |
|---|
| 1058 | #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446 |
|---|
| 1059 | #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447 |
|---|
| 1060 | #define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448 |
|---|
| 1061 | #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449 |
|---|
| 1062 | #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b |
|---|
| 1063 | #define mmBIF_RFE_MMCFG_CNTL 0x144c |
|---|
| 1064 | #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455 |
|---|
| 1065 | #define mmBIF_IMPCTL_SMPLCNTL 0x1450 |
|---|
| 1066 | #define mmBIF_IMPCTL_RXCNTL 0x1451 |
|---|
| 1067 | #define mmBIF_IMPCTL_TXCNTL_pd 0x1452 |
|---|
| 1068 | #define mmBIF_IMPCTL_TXCNTL_pu 0x1453 |
|---|
| 1069 | #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454 |
|---|
| 1070 | |
|---|
| 1071 | #endif /* BIF_5_0_D_H */ |
|---|
| 1072 | |
|---|
