1/*
2 * BIF_5_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef BIF_5_0_SH_MASK_H
25#define BIF_5_0_SH_MASK_H
26
27#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28#define MM_INDEX__MM_OFFSET__SHIFT 0x0
29#define MM_INDEX__MM_APER_MASK 0x80000000
30#define MM_INDEX__MM_APER__SHIFT 0x1f
31#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33#define MM_DATA__MM_DATA_MASK 0xffffffff
34#define MM_DATA__MM_DATA__SHIFT 0x0
35#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
37#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
38#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
39#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
40#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
41#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
42#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
43#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
44#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
45#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
46#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
47#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
48#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
49#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
50#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
51#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
52#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
53#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
54#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
55#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
56#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
57#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
58#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
59#define BUS_CNTL__SET_MC_TC_MASK 0xe000
60#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
61#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
62#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
63#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
64#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
65#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
66#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
67#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
68#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
69#define CONFIG_CNTL__VGA_DIS_MASK 0x2
70#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
71#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
72#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
73#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
74#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
75#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
76#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
77#define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff
78#define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
79#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1
80#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
81#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000
82#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
83#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
84#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
85#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
86#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
87#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
88#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
89#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
90#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
91#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
92#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
93#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1
94#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0
95#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100
96#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8
97#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1
98#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
99#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000
100#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
101#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1
102#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
103#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2
104#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
105#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000
106#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
107#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000
108#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
109#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
110#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
111#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
112#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
113#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
114#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
115#define BX_RESET_EN__FLR_TWICE_EN_MASK 0x100
116#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8
117#define BX_RESET_EN__FLR_TIMER_SEL_MASK 0x600
118#define BX_RESET_EN__FLR_TIMER_SEL__SHIFT 0x9
119#define BX_RESET_EN__DB_APER_RESET_EN_MASK 0x8000
120#define BX_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
121#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x10000
122#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
123#define BX_RESET_EN__PF_FLR_NEWHDL_EN_MASK 0x20000
124#define BX_RESET_EN__PF_FLR_NEWHDL_EN__SHIFT 0x11
125#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
126#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
127#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
128#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
129#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
130#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
131#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
132#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
133#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
134#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
135#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
136#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
137#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
138#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
139#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
140#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
141#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
142#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
143#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
144#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
145#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
146#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
147#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
148#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
149#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
150#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
151#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
152#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
153#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
154#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
155#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
156#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
157#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
158#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
159#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
160#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
161#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
162#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
163#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
164#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
165#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
166#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
167#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
168#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
169#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
170#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
171#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
172#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
173#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
174#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
175#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
176#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
177#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
178#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
179#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
180#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
181#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
182#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
183#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
184#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
185#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
186#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
187#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
188#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
189#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
190#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
191#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
192#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
193#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
194#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
195#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
196#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
197#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
198#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
199#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
200#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
201#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
202#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
203#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
204#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
205#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
206#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
207#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
208#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
209#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
210#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
211#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
212#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
213#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
214#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
215#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
216#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
217#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
218#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
219#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
220#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
221#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
222#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
223#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
224#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
225#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
226#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
227#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
228#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
229#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
230#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
231#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
232#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
233#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
234#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
235#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
236#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
237#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
238#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
239#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
240#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
241#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
242#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
243#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
244#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
245#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
246#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
247#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
248#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
249#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
250#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
251#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
252#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
253#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
254#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
255#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
256#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
257#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
258#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
259#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
260#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
261#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
262#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
263#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
264#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
265#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
266#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
267#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
268#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
269#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
270#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
271#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
272#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
273#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
274#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
275#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
276#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
277#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
278#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
279#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
280#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
281#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
282#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
283#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
284#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
285#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
286#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
287#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x2000
288#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
289#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER_MASK 0xff000000
290#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18
291#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER_MASK 0xffffffff
292#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0
293#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
294#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
295#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
296#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
297#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
298#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
299#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
300#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
301#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
302#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
303#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
304#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
305#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
306#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
307#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
308#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
309#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
310#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
311#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
312#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
313#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
314#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
315#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
316#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
317#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
318#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
319#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
320#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
321#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
322#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
323#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
324#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
325#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x2000
326#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
327#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x8000
328#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
329#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x10000
330#define BIF_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x10
331#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK 0x20000
332#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11
333#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK 0x40000
334#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12
335#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN_MASK 0x80000
336#define BIF_FEATURES_CONTROL_MISC__SOFT_PF_FLR_UR_CFG_EN__SHIFT 0x13
337#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS_MASK 0x100000
338#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_UR_DIS__SHIFT 0x14
339#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS_MASK 0x200000
340#define BIF_FEATURES_CONTROL_MISC__FLR_OSTD_HDL_DIS__SHIFT 0x15
341#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS_MASK 0x400000
342#define BIF_FEATURES_CONTROL_MISC__FLR_NEWREQ_HDL_DIS__SHIFT 0x16
343#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS_MASK 0x800000
344#define BIF_FEATURES_CONTROL_MISC__FLR_CRS_CFG_DIS__SHIFT 0x17
345#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS_MASK 0x1000000
346#define BIF_FEATURES_CONTROL_MISC__DUMMY_TRANS_CPL_RET_DIS__SHIFT 0x18
347#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
348#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
349#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
350#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
351#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
352#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
353#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
354#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
355#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
356#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
357#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
358#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
359#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
360#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
361#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x1000000
362#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
363#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x2000000
364#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
365#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x4000000
366#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
367#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x8000000
368#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
369#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
370#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
371#define BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK 0x1
372#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0
373#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS_MASK 0x2
374#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1
375#define BIF_FB_EN__FB_READ_EN_MASK 0x1
376#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
377#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
378#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
379#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
380#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
381#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
382#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
383#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
384#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
385#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
386#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
387#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
388#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
389#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
390#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
391#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
392#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
393#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
394#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
395#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
396#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
397#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
398#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
399#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
400#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
401#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
402#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
403#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
404#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
405#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
406#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
407#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
408#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
409#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
410#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
411#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
412#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
413#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
414#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
415#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
416#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
417#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
418#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
419#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
420#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
421#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
422#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
423#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
424#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
425#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
426#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
427#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
428#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
429#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
430#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
431#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
432#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
433#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
434#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
435#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
436#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
437#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
438#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
439#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
440#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
441#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
442#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
443#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
444#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
445#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
446#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
447#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
448#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
449#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
450#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
451#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
452#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
453#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
454#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
455#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
456#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
457#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
458#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
459#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
460#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
461#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
462#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
463#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
464#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
465#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
466#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
467#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
468#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
469#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
470#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
471#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
472#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
473#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
474#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
475#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
476#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
477#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
478#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
479#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
480#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
481#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
482#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
483#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
484#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
485#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
486#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
487#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
488#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
489#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
490#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
491#define HOST_BUSNUM__HOST_ID_MASK 0xffff
492#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
493#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
494#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
495#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
496#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
497#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
498#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
499#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
500#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
501#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
502#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
503#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
504#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
505#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
506#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
507#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
508#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
509#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
510#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
511#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
512#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
513#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
514#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
515#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
516#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
517#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
518#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
519#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
520#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
521#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
522#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
523#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
524#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
525#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN_MASK 0x1
526#define DBG_SMB_BYPASS_SRBM_ACCESS__DBG_SMB_BYPASS_SRBM_EN__SHIFT 0x0
527#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0xffffffff
528#define BIF_MST_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
529#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0xffffffff
530#define BIF_SLV_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x0
531#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
532#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
533#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
534#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
535#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
536#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
537#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
538#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
539#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
540#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
541#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
542#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
543#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
544#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
545#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
546#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
547#define BACO_CNTL__BACO_EN_MASK 0x1
548#define BACO_CNTL__BACO_EN__SHIFT 0x0
549#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
550#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
551#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
552#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
553#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
554#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
555#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
556#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
557#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
558#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
559#define BACO_CNTL__BACO_MODE_MASK 0x40
560#define BACO_CNTL__BACO_MODE__SHIFT 0x6
561#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
562#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
563#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
564#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
565#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
566#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
567#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
568#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
569#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
570#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
571#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
572#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
573#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
574#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
575#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
576#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
577#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
578#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
579#define BACO_CNTL__BACO_BIF_SCLK_SWITCH_MASK 0x40000
580#define BACO_CNTL__BACO_BIF_SCLK_SWITCH__SHIFT 0x12
581#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
582#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
583#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
584#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
585#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
586#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
587#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
588#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
589#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
590#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
591#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
592#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
593#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
594#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
595#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
596#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
597#define BACO_CNTL_MISC__BACO_REFCLK_SEL_MASK 0x10
598#define BACO_CNTL_MISC__BACO_REFCLK_SEL__SHIFT 0x4
599#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
600#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
601#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
602#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
603#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
604#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
605#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
606#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
607#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
608#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
609#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
610#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
611#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
612#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
613#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
614#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
615#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
616#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
617#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
618#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
619#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
620#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
621#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
622#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
623#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
624#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
625#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
626#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
627#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
628#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
629#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
630#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
631#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
632#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
633#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
634#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
635#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
636#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
637#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
638#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
639#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
640#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
641#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
642#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
643#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
644#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
645#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
646#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
647#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
648#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
649#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
650#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
651#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
652#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
653#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
654#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
655#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
656#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
657#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
658#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
659#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
660#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
661#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
662#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
663#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
664#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
665#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
666#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
667#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
668#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
669#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
670#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
671#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
672#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
673#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
674#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
675#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
676#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
677#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
678#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
679#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
680#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
681#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
682#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
683#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
684#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
685#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
686#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
687#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
688#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
689#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
690#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
691#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
692#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
693#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
694#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
695#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
696#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
697#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
698#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
699#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
700#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
701#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
702#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
703#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
704#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
705#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
706#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
707#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
708#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
709#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
710#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
711#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
712#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
713#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
714#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
715#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
716#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
717#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
718#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
719#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
720#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
721#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
722#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
723#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
724#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
725#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
726#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
727#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
728#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
729#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
730#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
731#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
732#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
733#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
734#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
735#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
736#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
737#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
738#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
739#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
740#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
741#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
742#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
743#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
744#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
745#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
746#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
747#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
748#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
749#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
750#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
751#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
752#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
753#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
754#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
755#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
756#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
757#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
758#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
759#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
760#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
761#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
762#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
763#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
764#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
765#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
766#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
767#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
768#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
769#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
770#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
771#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
772#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
773#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
774#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
775#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
776#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
777#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
778#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
779#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
780#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
781#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
782#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
783#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
784#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
785#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
786#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
787#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
788#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
789#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
790#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
791#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
792#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
793#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
794#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
795#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
796#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
797#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
798#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
799#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
800#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
801#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
802#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
803#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
804#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
805#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
806#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
807#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
808#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
809#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
810#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
811#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
812#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
813#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
814#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
815#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
816#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
817#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
818#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
819#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
820#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
821#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
822#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
823#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
824#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
825#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
826#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
827#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
828#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
829#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
830#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
831#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
832#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
833#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
834#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
835#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
836#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
837#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
838#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
839#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
840#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
841#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
842#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
843#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
844#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
845#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
846#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
847#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
848#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
849#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
850#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
851#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
852#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
853#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
854#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
855#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
856#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
857#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
858#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
859#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
860#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
861#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
862#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
863#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
864#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
865#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
866#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
867#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
868#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
869#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
870#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
871#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
872#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
873#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
874#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
875#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
876#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
877#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
878#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
879#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
880#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
881#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
882#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
883#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
884#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
885#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
886#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
887#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
888#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
889#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
890#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
891#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
892#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
893#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
894#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
895#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
896#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
897#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
898#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
899#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
900#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
901#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
902#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
903#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
904#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
905#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
906#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
907#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
908#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
909#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
910#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
911#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
912#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
913#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
914#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
915#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
916#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
917#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
918#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
919#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
920#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
921#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
922#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
923#define BIF_RB_BASE__ADDR_MASK 0xffffffff
924#define BIF_RB_BASE__ADDR__SHIFT 0x0
925#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
926#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
927#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
928#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
929#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
930#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
931#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
932#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
933#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
934#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
935#define MAILBOX_INDEX__MAILBOX_INDEX_MASK 0xf
936#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
937#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xffffffff
938#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
939#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xffffffff
940#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
941#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xffffffff
942#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
943#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xffffffff
944#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
945#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xffffffff
946#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
947#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xffffffff
948#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
949#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xffffffff
950#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
951#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xffffffff
952#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
953#define MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x1
954#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
955#define MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x2
956#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
957#define MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x100
958#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
959#define MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x200
960#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
961#define MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x1
962#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
963#define MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x2
964#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
965#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF_MASK 0xffff
966#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_VF__SHIFT 0x0
967#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF_MASK 0x80000000
968#define BIF_VIRT_RESET_REQ__VIRT_RESET_REQ_SOFTPF__SHIFT 0x1f
969#define VM_INIT_STATUS__VM_INIT_STATUS_MASK 0x1
970#define VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
971#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
972#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
973#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
974#define BIF_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
975#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE_MASK 0xffff
976#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_AVAILABLE__SHIFT 0x0
977#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED_MASK 0xffff0000
978#define BIF_GPUIOV_FB_TOTAL_FB_INFO__TOTAL_FB_CONSUMED__SHIFT 0x10
979#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
980#define BIF_GPUIOV_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
981#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
982#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
983#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
984#define BIF_GPUIOV_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
985#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
986#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
987#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
988#define BIF_GPUIOV_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
989#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
990#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
991#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
992#define BIF_GPUIOV_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
993#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
994#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
995#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
996#define BIF_GPUIOV_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
997#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
998#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
999#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
1000#define BIF_GPUIOV_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
1001#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
1002#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
1003#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
1004#define BIF_GPUIOV_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
1005#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY_MASK 0xffffffff
1006#define BIF_GPU_IDLE_LATENCY__GPU_IDLE_LATENCY__SHIFT 0x0
1007#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER_MASK 0xffff
1008#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_LOWER__SHIFT 0x0
1009#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER_MASK 0xffff0000
1010#define BIF_MMIO_MAP_RANGE0__MMIO_MAP_RANGE0_UPPER__SHIFT 0x10
1011#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER_MASK 0xffff
1012#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_LOWER__SHIFT 0x0
1013#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER_MASK 0xffff0000
1014#define BIF_MMIO_MAP_RANGE1__MMIO_MAP_RANGE1_UPPER__SHIFT 0x10
1015#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER_MASK 0xffff
1016#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_LOWER__SHIFT 0x0
1017#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER_MASK 0xffff0000
1018#define BIF_MMIO_MAP_RANGE2__MMIO_MAP_RANGE2_UPPER__SHIFT 0x10
1019#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER_MASK 0xffff
1020#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_LOWER__SHIFT 0x0
1021#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER_MASK 0xffff0000
1022#define BIF_MMIO_MAP_RANGE3__MMIO_MAP_RANGE3_UPPER__SHIFT 0x10
1023#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER_MASK 0xffff
1024#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_LOWER__SHIFT 0x0
1025#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER_MASK 0xffff0000
1026#define BIF_MMIO_MAP_RANGE4__MMIO_MAP_RANGE4_UPPER__SHIFT 0x10
1027#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER_MASK 0xffff
1028#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_LOWER__SHIFT 0x0
1029#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER_MASK 0xffff0000
1030#define BIF_MMIO_MAP_RANGE5__MMIO_MAP_RANGE5_UPPER__SHIFT 0x10
1031#define VENDOR_ID__VENDOR_ID_MASK 0xffff
1032#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
1033#define DEVICE_ID__DEVICE_ID_MASK 0xffff
1034#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
1035#define COMMAND__IO_ACCESS_EN_MASK 0x1
1036#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
1037#define COMMAND__MEM_ACCESS_EN_MASK 0x2
1038#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
1039#define COMMAND__BUS_MASTER_EN_MASK 0x4
1040#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
1041#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
1042#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
1043#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
1044#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
1045#define COMMAND__PAL_SNOOP_EN_MASK 0x20
1046#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
1047#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
1048#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
1049#define COMMAND__AD_STEPPING_MASK 0x80
1050#define COMMAND__AD_STEPPING__SHIFT 0x7
1051#define COMMAND__SERR_EN_MASK 0x100
1052#define COMMAND__SERR_EN__SHIFT 0x8
1053#define COMMAND__FAST_B2B_EN_MASK 0x200
1054#define COMMAND__FAST_B2B_EN__SHIFT 0x9
1055#define COMMAND__INT_DIS_MASK 0x400
1056#define COMMAND__INT_DIS__SHIFT 0xa
1057#define STATUS__INT_STATUS_MASK 0x8
1058#define STATUS__INT_STATUS__SHIFT 0x3
1059#define STATUS__CAP_LIST_MASK 0x10
1060#define STATUS__CAP_LIST__SHIFT 0x4
1061#define STATUS__PCI_66_EN_MASK 0x20
1062#define STATUS__PCI_66_EN__SHIFT 0x5
1063#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
1064#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
1065#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
1066#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
1067#define STATUS__DEVSEL_TIMING_MASK 0x600
1068#define STATUS__DEVSEL_TIMING__SHIFT 0x9
1069#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
1070#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
1071#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
1072#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
1073#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
1074#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
1075#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
1076#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
1077#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
1078#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
1079#define REVISION_ID__MINOR_REV_ID_MASK 0xf
1080#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
1081#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
1082#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
1083#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
1084#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
1085#define SUB_CLASS__SUB_CLASS_MASK 0xff
1086#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
1087#define BASE_CLASS__BASE_CLASS_MASK 0xff
1088#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
1089#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
1090#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
1091#define LATENCY__LATENCY_TIMER_MASK 0xff
1092#define LATENCY__LATENCY_TIMER__SHIFT 0x0
1093#define HEADER__HEADER_TYPE_MASK 0x7f
1094#define HEADER__HEADER_TYPE__SHIFT 0x0
1095#define HEADER__DEVICE_TYPE_MASK 0x80
1096#define HEADER__DEVICE_TYPE__SHIFT 0x7
1097#define BIST__BIST_COMP_MASK 0xf
1098#define BIST__BIST_COMP__SHIFT 0x0
1099#define BIST__BIST_STRT_MASK 0x40
1100#define BIST__BIST_STRT__SHIFT 0x6
1101#define BIST__BIST_CAP_MASK 0x80
1102#define BIST__BIST_CAP__SHIFT 0x7
1103#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
1104#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
1105#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
1106#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
1107#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
1108#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
1109#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
1110#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
1111#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
1112#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
1113#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
1114#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
1115#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
1116#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
1117#define CAP_PTR__CAP_PTR_MASK 0xff
1118#define CAP_PTR__CAP_PTR__SHIFT 0x0
1119#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
1120#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
1121#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
1122#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
1123#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
1124#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
1125#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
1126#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
1127#define MIN_GRANT__MIN_GNT_MASK 0xff
1128#define MIN_GRANT__MIN_GNT__SHIFT 0x0
1129#define MAX_LATENCY__MAX_LAT_MASK 0xff
1130#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
1131#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
1132#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
1133#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
1134#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
1135#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
1136#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
1137#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
1138#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
1139#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
1140#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
1141#define PMI_CAP_LIST__CAP_ID_MASK 0xff
1142#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
1143#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
1144#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
1145#define PMI_CAP__VERSION_MASK 0x7
1146#define PMI_CAP__VERSION__SHIFT 0x0
1147#define PMI_CAP__PME_CLOCK_MASK 0x8
1148#define PMI_CAP__PME_CLOCK__SHIFT 0x3
1149#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
1150#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
1151#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
1152#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
1153#define PMI_CAP__D1_SUPPORT_MASK 0x200
1154#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
1155#define PMI_CAP__D2_SUPPORT_MASK 0x400
1156#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
1157#define PMI_CAP__PME_SUPPORT_MASK 0xf800
1158#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
1159#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
1160#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
1161#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
1162#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
1163#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
1164#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
1165#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
1166#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
1167#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
1168#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
1169#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
1170#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
1171#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
1172#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
1173#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
1174#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
1175#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
1176#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
1177#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
1178#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
1179#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
1180#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
1181#define PCIE_CAP__VERSION_MASK 0xf
1182#define PCIE_CAP__VERSION__SHIFT 0x0
1183#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
1184#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
1185#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
1186#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
1187#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
1188#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
1189#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
1190#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
1191#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
1192#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
1193#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
1194#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
1195#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
1196#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
1197#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
1198#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
1199#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
1200#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
1201#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
1202#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
1203#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
1204#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
1205#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
1206#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
1207#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
1208#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
1209#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
1210#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
1211#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
1212#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
1213#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
1214#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
1215#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
1216#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
1217#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
1218#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
1219#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
1220#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
1221#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
1222#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
1223#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
1224#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
1225#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
1226#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
1227#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
1228#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
1229#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
1230#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
1231#define DEVICE_STATUS__CORR_ERR_MASK 0x1
1232#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
1233#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
1234#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
1235#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
1236#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
1237#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
1238#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
1239#define DEVICE_STATUS__AUX_PWR_MASK 0x10
1240#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
1241#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
1242#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
1243#define LINK_CAP__LINK_SPEED_MASK 0xf
1244#define LINK_CAP__LINK_SPEED__SHIFT 0x0
1245#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
1246#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
1247#define LINK_CAP__PM_SUPPORT_MASK 0xc00
1248#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
1249#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
1250#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
1251#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
1252#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
1253#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
1254#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
1255#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
1256#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
1257#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
1258#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
1259#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
1260#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
1261#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
1262#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
1263#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
1264#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
1265#define LINK_CNTL__PM_CONTROL_MASK 0x3
1266#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
1267#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
1268#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
1269#define LINK_CNTL__LINK_DIS_MASK 0x10
1270#define LINK_CNTL__LINK_DIS__SHIFT 0x4
1271#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
1272#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
1273#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
1274#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
1275#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
1276#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
1277#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
1278#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
1279#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
1280#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
1281#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
1282#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
1283#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
1284#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
1285#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
1286#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
1287#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
1288#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
1289#define LINK_STATUS__LINK_TRAINING_MASK 0x800
1290#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
1291#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
1292#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
1293#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
1294#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
1295#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
1296#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
1297#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
1298#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
1299#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
1300#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
1301#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
1302#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
1303#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
1304#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
1305#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
1306#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
1307#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
1308#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
1309#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
1310#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
1311#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
1312#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
1313#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
1314#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
1315#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
1316#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
1317#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
1318#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
1319#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
1320#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
1321#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
1322#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
1323#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
1324#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
1325#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
1326#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
1327#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
1328#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
1329#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
1330#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
1331#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
1332#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
1333#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
1334#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
1335#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
1336#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
1337#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
1338#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
1339#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
1340#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
1341#define DEVICE_CNTL2__LTR_EN_MASK 0x400
1342#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
1343#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
1344#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
1345#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
1346#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
1347#define DEVICE_STATUS2__RESERVED_MASK 0xffff
1348#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
1349#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
1350#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
1351#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
1352#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
1353#define LINK_CAP2__RESERVED_MASK 0xfffffe00
1354#define LINK_CAP2__RESERVED__SHIFT 0x9
1355#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
1356#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
1357#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
1358#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
1359#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
1360#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
1361#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
1362#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
1363#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
1364#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
1365#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
1366#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
1367#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
1368#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
1369#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
1370#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
1371#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
1372#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
1373#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
1374#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
1375#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
1376#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
1377#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
1378#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
1379#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
1380#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
1381#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
1382#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
1383#define MSI_CAP_LIST__CAP_ID_MASK 0xff
1384#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
1385#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
1386#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
1387#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
1388#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
1389#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
1390#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
1391#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
1392#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
1393#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
1394#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
1395#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x100
1396#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
1397#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
1398#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
1399#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
1400#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
1401#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
1402#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
1403#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
1404#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
1405#define MSI_MASK__MSI_MASK_MASK 0xffffffff
1406#define MSI_MASK__MSI_MASK__SHIFT 0x0
1407#define MSI_PENDING__MSI_PENDING_MASK 0xffffffff
1408#define MSI_PENDING__MSI_PENDING__SHIFT 0x0
1409#define MSI_MASK_64__MSI_MASK_64_MASK 0xffffffff
1410#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
1411#define MSI_PENDING_64__MSI_PENDING_64_MASK 0xffffffff
1412#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
1413#define MSIX_CAP_LIST__CAP_ID_MASK 0xff
1414#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
1415#define MSIX_CAP_LIST__NEXT_PTR_MASK 0xff00
1416#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
1417#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x7ff
1418#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
1419#define MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000
1420#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
1421#define MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000
1422#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
1423#define MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x7
1424#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
1425#define MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xfffffff8
1426#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
1427#define MSIX_PBA__MSIX_PBA_BIR_MASK 0x7
1428#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
1429#define MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xfffffff8
1430#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
1431#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1432#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1433#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1434#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1435#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1436#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1437#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
1438#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
1439#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
1440#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
1441#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
1442#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
1443#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
1444#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
1445#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
1446#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
1447#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1448#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1449#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1450#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1451#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1452#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1453#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
1454#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
1455#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
1456#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
1457#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
1458#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
1459#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
1460#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
1461#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
1462#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
1463#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
1464#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
1465#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
1466#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
1467#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
1468#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
1469#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
1470#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
1471#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
1472#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
1473#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
1474#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
1475#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
1476#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
1477#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
1478#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
1479#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
1480#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
1481#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
1482#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
1483#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
1484#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
1485#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
1486#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
1487#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
1488#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
1489#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
1490#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
1491#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
1492#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
1493#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1494#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
1495#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
1496#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
1497#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
1498#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
1499#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
1500#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
1501#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
1502#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
1503#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
1504#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
1505#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
1506#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
1507#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
1508#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
1509#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
1510#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
1511#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
1512#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
1513#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
1514#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
1515#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
1516#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
1517#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1518#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
1519#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1520#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1521#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1522#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1523#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1524#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1525#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
1526#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
1527#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
1528#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
1529#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1530#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1531#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1532#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1533#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1534#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1535#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
1536#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
1537#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
1538#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
1539#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
1540#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
1541#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
1542#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
1543#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
1544#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
1545#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
1546#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
1547#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
1548#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
1549#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
1550#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
1551#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
1552#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
1553#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
1554#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
1555#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
1556#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
1557#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
1558#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
1559#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
1560#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
1561#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
1562#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
1563#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
1564#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
1565#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
1566#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
1567#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
1568#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
1569#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
1570#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
1571#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
1572#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
1573#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
1574#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
1575#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
1576#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
1577#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
1578#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
1579#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
1580#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
1581#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
1582#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
1583#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
1584#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
1585#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
1586#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
1587#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
1588#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
1589#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
1590#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
1591#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
1592#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
1593#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
1594#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
1595#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
1596#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
1597#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
1598#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
1599#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
1600#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
1601#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
1602#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
1603#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
1604#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
1605#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
1606#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
1607#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
1608#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
1609#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
1610#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
1611#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
1612#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
1613#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
1614#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
1615#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
1616#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
1617#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
1618#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
1619#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
1620#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
1621#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
1622#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
1623#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
1624#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
1625#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
1626#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
1627#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
1628#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
1629#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
1630#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
1631#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
1632#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
1633#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
1634#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
1635#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
1636#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
1637#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
1638#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
1639#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
1640#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
1641#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
1642#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
1643#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
1644#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
1645#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
1646#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
1647#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
1648#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
1649#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
1650#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
1651#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
1652#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
1653#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
1654#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
1655#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
1656#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
1657#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
1658#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
1659#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
1660#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
1661#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
1662#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
1663#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
1664#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
1665#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
1666#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
1667#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
1668#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
1669#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
1670#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
1671#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
1672#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
1673#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
1674#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
1675#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
1676#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
1677#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
1678#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
1679#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
1680#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
1681#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
1682#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
1683#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
1684#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
1685#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
1686#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
1687#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
1688#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
1689#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
1690#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
1691#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
1692#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
1693#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
1694#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
1695#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1696#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1697#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1698#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1699#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1700#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1701#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1702#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1703#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
1704#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
1705#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1706#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1707#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
1708#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
1709#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1710#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1711#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
1712#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
1713#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1714#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1715#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
1716#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
1717#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1718#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1719#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
1720#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
1721#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1722#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1723#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
1724#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
1725#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1726#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1727#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
1728#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
1729#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1730#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1731#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
1732#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
1733#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1734#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1735#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
1736#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
1737#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1738#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1739#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
1740#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
1741#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1742#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1743#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
1744#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
1745#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1746#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1747#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
1748#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
1749#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1750#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1751#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1752#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1753#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1754#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1755#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
1756#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
1757#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
1758#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
1759#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
1760#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
1761#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
1762#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
1763#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
1764#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
1765#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
1766#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
1767#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
1768#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
1769#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
1770#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
1771#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1772#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1773#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1774#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1775#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1776#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1777#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
1778#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
1779#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
1780#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
1781#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
1782#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
1783#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
1784#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
1785#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
1786#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
1787#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
1788#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
1789#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
1790#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
1791#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
1792#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
1793#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
1794#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
1795#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
1796#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1797#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
1798#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1799#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
1800#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1801#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
1802#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1803#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
1804#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1805#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
1806#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1807#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
1808#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1809#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
1810#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1811#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1812#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1813#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1814#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1815#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1816#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1817#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
1818#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
1819#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
1820#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
1821#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
1822#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
1823#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
1824#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
1825#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
1826#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
1827#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1828#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1829#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1830#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1831#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1832#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1833#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1834#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1835#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1836#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1837#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1838#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1839#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1840#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1841#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1842#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1843#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1844#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1845#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1846#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1847#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1848#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1849#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1850#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1851#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1852#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1853#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1854#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1855#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1856#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1857#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1858#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1859#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1860#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1861#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1862#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1863#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1864#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1865#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1866#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1867#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1868#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1869#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1870#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1871#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1872#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1873#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1874#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1875#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1876#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1877#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1878#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1879#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1880#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1881#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1882#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1883#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1884#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1885#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1886#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1887#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1888#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1889#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1890#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1891#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1892#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1893#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1894#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1895#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1896#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1897#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1898#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1899#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1900#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1901#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1902#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1903#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1904#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1905#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1906#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1907#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1908#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1909#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1910#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1911#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1912#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1913#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1914#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1915#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1916#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1917#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1918#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1919#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1920#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1921#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1922#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1923#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1924#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1925#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1926#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1927#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1928#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1929#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1930#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1931#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1932#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1933#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1934#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1935#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1936#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1937#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1938#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1939#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1940#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1941#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1942#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1943#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1944#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1945#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1946#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1947#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1948#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1949#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1950#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1951#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1952#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1953#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1954#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1955#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1956#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1957#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1958#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1959#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1960#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1961#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1962#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1963#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1964#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1965#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1966#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1967#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1968#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1969#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1970#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1971#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1972#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1973#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1974#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1975#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1976#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1977#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1978#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1979#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1980#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1981#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1982#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1983#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1984#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1985#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1986#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1987#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1988#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1989#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1990#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1991#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1992#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1993#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
1994#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
1995#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
1996#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
1997#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
1998#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
1999#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
2000#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
2001#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
2002#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
2003#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
2004#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
2005#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
2006#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
2007#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
2008#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
2009#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
2010#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
2011#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
2012#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
2013#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
2014#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
2015#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
2016#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
2017#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
2018#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
2019#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
2020#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
2021#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
2022#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
2023#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2024#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2025#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2026#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2027#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2028#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2029#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
2030#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
2031#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
2032#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
2033#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
2034#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
2035#define PCIE_ATS_CNTL__STU_MASK 0x1f
2036#define PCIE_ATS_CNTL__STU__SHIFT 0x0
2037#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
2038#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
2039#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2040#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2041#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2042#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2043#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2044#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2045#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
2046#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
2047#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
2048#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
2049#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
2050#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
2051#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
2052#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
2053#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
2054#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
2055#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
2056#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
2057#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
2058#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
2059#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
2060#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
2061#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2062#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2063#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2064#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2065#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2066#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2067#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
2068#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
2069#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
2070#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
2071#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
2072#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
2073#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
2074#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
2075#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
2076#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
2077#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
2078#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
2079#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2080#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2081#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2082#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2083#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2084#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2085#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
2086#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
2087#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
2088#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
2089#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
2090#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
2091#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
2092#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
2093#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
2094#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
2095#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
2096#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
2097#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
2098#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
2099#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
2100#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
2101#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2102#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2103#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2104#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2105#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2106#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2107#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
2108#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
2109#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
2110#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
2111#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
2112#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
2113#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
2114#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
2115#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
2116#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
2117#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
2118#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
2119#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
2120#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
2121#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
2122#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
2123#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
2124#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
2125#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
2126#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
2127#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
2128#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
2129#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
2130#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
2131#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
2132#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
2133#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
2134#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
2135#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2136#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2137#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2138#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2139#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2140#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2141#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
2142#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
2143#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
2144#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
2145#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
2146#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
2147#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
2148#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
2149#define PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2150#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2151#define PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2152#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2153#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2154#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2155#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x1
2156#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
2157#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x2
2158#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
2159#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xff00
2160#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
2161#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x1
2162#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
2163#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x2
2164#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
2165#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x70
2166#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
2167#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2168#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2169#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2170#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2171#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2172#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2173#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x1
2174#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
2175#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x2
2176#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
2177#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xffe00000
2178#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
2179#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x1
2180#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
2181#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x2
2182#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
2183#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x4
2184#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
2185#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x8
2186#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
2187#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x10
2188#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
2189#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x1
2190#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
2191#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xffff
2192#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
2193#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xffff
2194#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
2195#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xffff
2196#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
2197#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xff
2198#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
2199#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xffff
2200#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
2201#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xffff
2202#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
2203#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xffff
2204#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
2205#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xffffffff
2206#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
2207#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xffffffff
2208#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
2209#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xffffffff
2210#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
2211#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xffffffff
2212#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
2213#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xffffffff
2214#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
2215#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xffffffff
2216#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
2217#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xffffffff
2218#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
2219#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xffffffff
2220#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
2221#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xffffffff
2222#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x0
2223#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0xffff
2224#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
2225#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0xf0000
2226#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
2227#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xfff00000
2228#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
2229#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0xffff
2230#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
2231#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0xf0000
2232#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
2233#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xfff00000
2234#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
2235#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x1
2236#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
2237#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xffff0000
2238#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
2239#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK 0xff
2240#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT 0x0
2241#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK 0xff00
2242#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT 0x8
2243#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK 0xff0000
2244#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT 0x10
2245#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK 0xff
2246#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT 0x0
2247#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x1
2248#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
2249#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK 0xffffffff
2250#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0
2251#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK 0xffffffff
2252#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT 0x0
2253#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK 0x7f
2254#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT 0x0
2255#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x80
2256#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
2257#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK 0xfffc0000
2258#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT 0x12
2259#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xffff
2260#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x0
2261#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0xffff0000
2262#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x10
2263#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
2264#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
2265#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK 0xff00
2266#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT 0x8
2267#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK 0xff0000
2268#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT 0x10
2269#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK 0xff000000
2270#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT 0x18
2271#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK 0xffff
2272#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT 0x0
2273#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK 0xffff0000
2274#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT 0x10
2275#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK 0xffff
2276#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT 0x0
2277#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK 0xffff0000
2278#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT 0x10
2279#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK 0xffff
2280#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT 0x0
2281#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK 0xffff0000
2282#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT 0x10
2283#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK 0xffff
2284#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT 0x0
2285#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK 0xffff0000
2286#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT 0x10
2287#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK 0xffff
2288#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT 0x0
2289#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK 0xffff0000
2290#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT 0x10
2291#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK 0xffff
2292#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT 0x0
2293#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK 0xffff0000
2294#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT 0x10
2295#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK 0xffff
2296#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT 0x0
2297#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK 0xffff0000
2298#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT 0x10
2299#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK 0xffff
2300#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT 0x0
2301#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK 0xffff0000
2302#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT 0x10
2303#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK 0xffff
2304#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT 0x0
2305#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK 0xffff0000
2306#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT 0x10
2307#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK 0xffff
2308#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT 0x0
2309#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK 0xffff0000
2310#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT 0x10
2311#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK 0xffff
2312#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT 0x0
2313#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK 0xffff0000
2314#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT 0x10
2315#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK 0xffff
2316#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT 0x0
2317#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK 0xffff0000
2318#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT 0x10
2319#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK 0xffff
2320#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT 0x0
2321#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK 0xffff0000
2322#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT 0x10
2323#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK 0xffff
2324#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT 0x0
2325#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK 0xffff0000
2326#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT 0x10
2327#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK 0xffff
2328#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT 0x0
2329#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK 0xffff0000
2330#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT 0x10
2331#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK 0xffff
2332#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT 0x0
2333#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK 0xffff0000
2334#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT 0x10
2335#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK 0xffffffff
2336#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT 0x0
2337#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK 0xffff
2338#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT 0x0
2339#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK 0xffff0000
2340#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT 0x10
2341#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK 0xffff
2342#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT 0x0
2343#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK 0xffff0000
2344#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT 0x10
2345#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK 0xffff
2346#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT 0x0
2347#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK 0xffff0000
2348#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT 0x10
2349#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK 0xffff
2350#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT 0x0
2351#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK 0xffff0000
2352#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT 0x10
2353#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK 0xffff
2354#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT 0x0
2355#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK 0xffff0000
2356#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT 0x10
2357#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK 0xffff
2358#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT 0x0
2359#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK 0xffff0000
2360#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT 0x10
2361#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK 0xffffffff
2362#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT 0x0
2363#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK 0xffffffff
2364#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT 0x0
2365#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK 0xffffffff
2366#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT 0x0
2367#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK 0xffffffff
2368#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT 0x0
2369#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
2370#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
2371#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
2372#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
2373#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
2374#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
2375#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
2376#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
2377#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK 0x1
2378#define PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT 0x0
2379#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
2380#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
2381#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
2382#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
2383#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
2384#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
2385#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
2386#define LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
2387#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
2388#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
2389#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
2390#define CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
2391#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
2392#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
2393#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
2394#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
2395#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
2396#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
2397#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
2398#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
2399#define LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
2400#define LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
2401#define LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
2402#define LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
2403#define LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
2404#define LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
2405#define PCIE_EFUSE__PCIE_EFUSE_VALID_MASK 0x2
2406#define PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT 0x1
2407#define PCIE_EFUSE__PPHY_EFUSE_VALID_MASK 0x4
2408#define PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT 0x2
2409#define PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK 0x38
2410#define PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT 0x3
2411#define PCIE_EFUSE__ISTRAP_ARBEN0_MASK 0x40
2412#define PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT 0x6
2413#define PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK 0x7ffff80
2414#define PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT 0x7
2415#define PCIE_EFUSE__CHIP_BIF_MODE_MASK 0x8000000
2416#define PCIE_EFUSE__CHIP_BIF_MODE__SHIFT 0x1b
2417#define PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK 0xf0000000
2418#define PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT 0x1c
2419#define PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK 0xfffffffe
2420#define PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT 0x1
2421#define PCIE_EFUSE3__STRAP_CEC_ID_MASK 0x1fffe
2422#define PCIE_EFUSE3__STRAP_CEC_ID__SHIFT 0x1
2423#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK 0x20000
2424#define PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT 0x11
2425#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK 0xfffc0000
2426#define PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT 0x12
2427#define PCIE_EFUSE4__CC_WRITE_DISABLE_MASK 0x1
2428#define PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT 0x0
2429#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK 0xe
2430#define PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT 0x1
2431#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK 0xffff0
2432#define PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT 0x4
2433#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK 0xf00000
2434#define PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT 0x14
2435#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK 0xf000000
2436#define PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT 0x18
2437#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK 0xf0000000
2438#define PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT 0x1c
2439#define PCIE_EFUSE5__STRAP_AZALIA_DID_MASK 0x1fffe
2440#define PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT 0x1
2441#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK 0xfffe0000
2442#define PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT 0x11
2443#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK 0x1fffe
2444#define PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT 0x1
2445#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK 0xfffe0000
2446#define PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT 0x11
2447#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK 0x1fffe
2448#define PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT 0x1
2449#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK 0xfffe0000
2450#define PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT 0x11
2451#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
2452#define PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
2453#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
2454#define PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
2455#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
2456#define PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
2457#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
2458#define PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
2459#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
2460#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
2461#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
2462#define PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
2463#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK 0x2
2464#define PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT 0x1
2465#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
2466#define PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
2467#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
2468#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
2469#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
2470#define PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
2471#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
2472#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
2473#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
2474#define PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
2475#define PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xffff
2476#define PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
2477#define PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
2478#define PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
2479#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
2480#define REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
2481#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
2482#define REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
2483#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
2484#define REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
2485#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
2486#define REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
2487#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
2488#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
2489#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
2490#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
2491#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
2492#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
2493#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
2494#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
2495#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
2496#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2497#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
2498#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
2499#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
2500#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
2501#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
2502#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
2503#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
2504#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
2505#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
2506#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
2507#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
2508#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
2509#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
2510#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
2511#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
2512#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
2513#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
2514#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
2515#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
2516#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
2517#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
2518#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
2519#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
2520#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
2521#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
2522#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
2523#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
2524#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
2525#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
2526#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
2527#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
2528#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
2529#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
2530#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
2531#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
2532#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
2533#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
2534#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
2535#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
2536#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
2537#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
2538#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
2539#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
2540#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
2541#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
2542#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
2543#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
2544#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
2545#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
2546#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
2547#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
2548#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
2549#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
2550#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
2551#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
2552#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
2553#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
2554#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
2555#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
2556#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
2557#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
2558#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
2559#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
2560#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
2561#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
2562#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
2563#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
2564#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
2565#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
2566#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
2567#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
2568#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
2569#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
2570#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
2571#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
2572#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
2573#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
2574#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
2575#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
2576#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
2577#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
2578#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
2579#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
2580#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
2581#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
2582#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
2583#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
2584#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
2585#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
2586#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
2587#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
2588#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
2589#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
2590#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
2591#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
2592#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
2593#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
2594#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
2595#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
2596#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
2597#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
2598#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
2599#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
2600#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
2601#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
2602#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
2603#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
2604#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
2605#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
2606#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
2607#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
2608#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
2609#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
2610#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
2611#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
2612#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
2613#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
2614#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
2615#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
2616#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
2617#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
2618#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
2619#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
2620#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
2621#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
2622#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
2623#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
2624#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
2625#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
2626#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
2627#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
2628#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
2629#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
2630#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
2631#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
2632#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
2633#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
2634#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
2635#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
2636#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
2637#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
2638#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
2639#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
2640#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
2641#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
2642#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
2643#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
2644#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
2645#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
2646#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
2647#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
2648#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
2649#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
2650#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
2651#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
2652#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
2653#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
2654#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
2655#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
2656#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
2657#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
2658#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
2659#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
2660#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
2661#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
2662#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
2663#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
2664#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
2665#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
2666#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
2667#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
2668#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
2669#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
2670#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
2671#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
2672#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
2673#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
2674#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
2675#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
2676#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
2677#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
2678#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
2679#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
2680#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
2681#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
2682#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
2683#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
2684#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
2685#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
2686#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
2687#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
2688#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
2689#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
2690#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
2691#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
2692#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
2693#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
2694#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
2695#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
2696#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
2697#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
2698#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
2699#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
2700#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
2701#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
2702#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
2703#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
2704#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
2705#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
2706#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
2707#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
2708#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
2709#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
2710#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
2711#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
2712#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
2713#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
2714#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
2715#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
2716#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
2717#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
2718#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
2719#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
2720#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
2721#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
2722#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
2723#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
2724#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
2725#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
2726#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
2727#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
2728#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
2729#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
2730#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
2731#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
2732#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
2733#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
2734#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
2735#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
2736#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
2737#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
2738#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
2739#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
2740#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
2741#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK 0x70000
2742#define PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT 0x10
2743#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
2744#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
2745#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
2746#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
2747#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
2748#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
2749#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
2750#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
2751#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
2752#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
2753#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
2754#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
2755#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
2756#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
2757#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
2758#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
2759#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
2760#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
2761#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
2762#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
2763#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
2764#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
2765#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
2766#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
2767#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
2768#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
2769#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
2770#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
2771#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
2772#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
2773#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
2774#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
2775#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
2776#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
2777#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
2778#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
2779#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
2780#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
2781#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
2782#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
2783#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
2784#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
2785#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
2786#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
2787#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
2788#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
2789#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
2790#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
2791#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
2792#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
2793#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
2794#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
2795#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
2796#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
2797#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
2798#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
2799#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
2800#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
2801#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
2802#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
2803#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
2804#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
2805#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
2806#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
2807#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
2808#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
2809#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
2810#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
2811#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
2812#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
2813#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
2814#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
2815#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
2816#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
2817#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
2818#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
2819#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
2820#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
2821#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
2822#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
2823#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
2824#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
2825#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
2826#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
2827#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
2828#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
2829#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
2830#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
2831#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
2832#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
2833#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
2834#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
2835#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
2836#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
2837#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
2838#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
2839#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
2840#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
2841#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
2842#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
2843#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
2844#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
2845#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
2846#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
2847#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
2848#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
2849#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
2850#define PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
2851#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
2852#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
2853#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
2854#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
2855#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
2856#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
2857#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
2858#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
2859#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
2860#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
2861#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
2862#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
2863#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
2864#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
2865#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
2866#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
2867#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
2868#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
2869#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
2870#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
2871#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
2872#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
2873#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
2874#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
2875#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
2876#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
2877#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
2878#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
2879#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
2880#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
2881#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
2882#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
2883#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
2884#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
2885#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
2886#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
2887#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
2888#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
2889#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
2890#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
2891#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
2892#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
2893#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
2894#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
2895#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
2896#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
2897#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
2898#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
2899#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
2900#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
2901#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
2902#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
2903#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
2904#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
2905#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
2906#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
2907#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
2908#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
2909#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
2910#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
2911#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK 0x80000
2912#define PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13
2913#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
2914#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
2915#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
2916#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
2917#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
2918#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
2919#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
2920#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
2921#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
2922#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
2923#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
2924#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
2925#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
2926#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
2927#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
2928#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
2929#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
2930#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
2931#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x10000
2932#define PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
2933#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK 0x1
2934#define PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT 0x0
2935#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK 0x2
2936#define PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT 0x1
2937#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK 0x4
2938#define PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT 0x2
2939#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK 0x8
2940#define PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT 0x3
2941#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK 0x10
2942#define PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT 0x4
2943#define PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK 0x20
2944#define PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT 0x5
2945#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK 0x40
2946#define PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT 0x6
2947#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK 0x80
2948#define PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT 0x7
2949#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK 0x100
2950#define PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT 0x8
2951#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
2952#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
2953#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
2954#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
2955#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
2956#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
2957#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
2958#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
2959#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
2960#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
2961#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
2962#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
2963#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
2964#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
2965#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
2966#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
2967#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
2968#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
2969#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
2970#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
2971#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
2972#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
2973#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
2974#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
2975#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
2976#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
2977#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
2978#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
2979#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
2980#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
2981#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
2982#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
2983#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
2984#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
2985#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
2986#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
2987#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
2988#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
2989#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
2990#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
2991#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
2992#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
2993#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
2994#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
2995#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
2996#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
2997#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
2998#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
2999#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
3000#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
3001#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
3002#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
3003#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
3004#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
3005#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
3006#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
3007#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
3008#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
3009#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
3010#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
3011#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
3012#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
3013#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
3014#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
3015#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
3016#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
3017#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
3018#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
3019#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
3020#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
3021#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
3022#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
3023#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
3024#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
3025#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
3026#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
3027#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
3028#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
3029#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
3030#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
3031#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
3032#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
3033#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
3034#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
3035#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
3036#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
3037#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
3038#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
3039#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
3040#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
3041#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
3042#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
3043#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
3044#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
3045#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
3046#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
3047#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
3048#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
3049#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
3050#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
3051#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
3052#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
3053#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
3054#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
3055#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
3056#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
3057#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
3058#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
3059#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
3060#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
3061#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
3062#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
3063#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
3064#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
3065#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
3066#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
3067#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
3068#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
3069#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
3070#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
3071#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3072#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3073#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
3074#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
3075#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
3076#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
3077#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
3078#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
3079#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
3080#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
3081#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
3082#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
3083#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
3084#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
3085#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
3086#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
3087#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
3088#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
3089#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
3090#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
3091#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
3092#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
3093#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
3094#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
3095#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
3096#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
3097#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
3098#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
3099#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
3100#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
3101#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3102#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3103#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
3104#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
3105#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
3106#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
3107#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
3108#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
3109#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
3110#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
3111#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
3112#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
3113#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
3114#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
3115#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
3116#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
3117#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
3118#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
3119#define PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
3120#define PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
3121#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
3122#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
3123#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3124#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3125#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
3126#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
3127#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
3128#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
3129#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
3130#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
3131#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
3132#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
3133#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
3134#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
3135#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
3136#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
3137#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
3138#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
3139#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
3140#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
3141#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
3142#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
3143#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
3144#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
3145#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
3146#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
3147#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
3148#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
3149#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
3150#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
3151#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
3152#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
3153#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3154#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3155#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK 0x40000
3156#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT 0x12
3157#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK 0x80000
3158#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT 0x13
3159#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK 0x100000
3160#define PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT 0x14
3161#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK 0xe00000
3162#define PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT 0x15
3163#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
3164#define PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
3165#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3166#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3167#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
3168#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
3169#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
3170#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
3171#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
3172#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
3173#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
3174#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
3175#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
3176#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
3177#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
3178#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
3179#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
3180#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
3181#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
3182#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
3183#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
3184#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
3185#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
3186#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
3187#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
3188#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
3189#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
3190#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
3191#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
3192#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
3193#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
3194#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
3195#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3196#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3197#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK 0x40000
3198#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT 0x12
3199#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK 0x80000
3200#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT 0x13
3201#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK 0x100000
3202#define PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT 0x14
3203#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK 0xe00000
3204#define PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT 0x15
3205#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
3206#define PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
3207#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
3208#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
3209#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
3210#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
3211#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
3212#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
3213#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
3214#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
3215#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK 0x1
3216#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT 0x0
3217#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK 0xe
3218#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT 0x1
3219#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK 0xfffff000
3220#define PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT 0xc
3221#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
3222#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
3223#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
3224#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
3225#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
3226#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
3227#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
3228#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
3229#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
3230#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
3231#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
3232#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
3233#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
3234#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
3235#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
3236#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
3237#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
3238#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
3239#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
3240#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
3241#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
3242#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
3243#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
3244#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
3245#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
3246#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
3247#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
3248#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
3249#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
3250#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
3251#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
3252#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
3253#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
3254#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
3255#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
3256#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
3257#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
3258#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
3259#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
3260#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
3261#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
3262#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
3263#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
3264#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
3265#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
3266#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
3267#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
3268#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
3269#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
3270#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
3271#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
3272#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
3273#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
3274#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
3275#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
3276#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
3277#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
3278#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
3279#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
3280#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
3281#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
3282#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
3283#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
3284#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
3285#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
3286#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
3287#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
3288#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
3289#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
3290#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
3291#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
3292#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
3293#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
3294#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
3295#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
3296#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
3297#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
3298#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
3299#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
3300#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
3301#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
3302#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
3303#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
3304#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
3305#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
3306#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
3307#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
3308#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
3309#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
3310#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
3311#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
3312#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
3313#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
3314#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
3315#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
3316#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
3317#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
3318#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
3319#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
3320#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
3321#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
3322#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
3323#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
3324#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
3325#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
3326#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
3327#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
3328#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
3329#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
3330#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
3331#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
3332#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
3333#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
3334#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
3335#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
3336#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
3337#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
3338#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
3339#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
3340#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
3341#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
3342#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
3343#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x100
3344#define PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
3345#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
3346#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3347#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
3348#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3349#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
3350#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3351#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
3352#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3353#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
3354#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3355#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
3356#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3357#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
3358#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3359#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
3360#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3361#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
3362#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
3363#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
3364#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
3365#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
3366#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
3367#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
3368#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
3369#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
3370#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
3371#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
3372#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
3373#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
3374#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
3375#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
3376#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
3377#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
3378#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
3379#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
3380#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
3381#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
3382#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
3383#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
3384#define SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
3385#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
3386#define SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
3387#define SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
3388#define SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
3389#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
3390#define SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
3391#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN_MASK 0x10000000
3392#define SWRST_GENERAL_CONTROL__EP_COMPLT_CHK_EN__SHIFT 0x1c
3393#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR_MASK 0x60000000
3394#define SWRST_GENERAL_CONTROL__EP_COMPLT_WAIT_TMR__SHIFT 0x1d
3395#define SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
3396#define SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
3397#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
3398#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
3399#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
3400#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
3401#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
3402#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
3403#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
3404#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
3405#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
3406#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
3407#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
3408#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
3409#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
3410#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
3411#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
3412#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
3413#define SWRST_COMMAND_1__RESETPCFG_MASK 0x2
3414#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
3415#define SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
3416#define SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
3417#define SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
3418#define SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
3419#define SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
3420#define SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
3421#define SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
3422#define SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
3423#define SWRST_COMMAND_1__RESETLC_MASK 0x40
3424#define SWRST_COMMAND_1__RESETLC__SHIFT 0x6
3425#define SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
3426#define SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
3427#define SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
3428#define SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
3429#define SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
3430#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
3431#define SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
3432#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
3433#define SWRST_COMMAND_1__RESETCPM_MASK 0x8000
3434#define SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
3435#define SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
3436#define SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
3437#define SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
3438#define SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
3439#define SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
3440#define SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
3441#define SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
3442#define SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
3443#define SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
3444#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
3445#define SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
3446#define SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
3447#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
3448#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
3449#define SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
3450#define SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
3451#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
3452#define SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
3453#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
3454#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
3455#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
3456#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
3457#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
3458#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
3459#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
3460#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
3461#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
3462#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
3463#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
3464#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
3465#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
3466#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
3467#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
3468#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
3469#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
3470#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
3471#define SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
3472#define SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
3473#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
3474#define SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
3475#define SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
3476#define SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
3477#define SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
3478#define SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
3479#define SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
3480#define SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
3481#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
3482#define SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
3483#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
3484#define SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
3485#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
3486#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
3487#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
3488#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
3489#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
3490#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
3491#define SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
3492#define SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
3493#define SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
3494#define SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
3495#define SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
3496#define SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
3497#define SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
3498#define SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
3499#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
3500#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
3501#define SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
3502#define SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
3503#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
3504#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
3505#define SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
3506#define SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
3507#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
3508#define SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
3509#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
3510#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
3511#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
3512#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
3513#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
3514#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
3515#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
3516#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
3517#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
3518#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
3519#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
3520#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
3521#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
3522#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
3523#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
3524#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
3525#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
3526#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
3527#define SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
3528#define SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
3529#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
3530#define SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
3531#define SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
3532#define SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
3533#define SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
3534#define SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
3535#define SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
3536#define SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
3537#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
3538#define SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
3539#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
3540#define SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
3541#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
3542#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
3543#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
3544#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
3545#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
3546#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
3547#define SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
3548#define SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
3549#define SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
3550#define SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
3551#define SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
3552#define SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
3553#define SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
3554#define SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
3555#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
3556#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
3557#define SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
3558#define SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
3559#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
3560#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
3561#define SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
3562#define SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
3563#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
3564#define SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
3565#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
3566#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
3567#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
3568#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
3569#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
3570#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
3571#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
3572#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
3573#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
3574#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
3575#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
3576#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
3577#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
3578#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
3579#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
3580#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
3581#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
3582#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
3583#define SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
3584#define SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
3585#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
3586#define SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
3587#define SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
3588#define SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
3589#define SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
3590#define SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
3591#define SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
3592#define SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
3593#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
3594#define SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
3595#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
3596#define SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
3597#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
3598#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
3599#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
3600#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
3601#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
3602#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
3603#define SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
3604#define SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
3605#define SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
3606#define SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
3607#define SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
3608#define SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
3609#define SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
3610#define SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
3611#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
3612#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
3613#define SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
3614#define SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
3615#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
3616#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
3617#define SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
3618#define SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
3619#define SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
3620#define SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
3621#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
3622#define SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
3623#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x1
3624#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
3625#define SWRST_EP_COMMAND_0__EP_SOFT_RESET_MASK 0x2
3626#define SWRST_EP_COMMAND_0__EP_SOFT_RESET__SHIFT 0x1
3627#define SWRST_EP_COMMAND_0__EP_DRV_RESET_MASK 0x4
3628#define SWRST_EP_COMMAND_0__EP_DRV_RESET__SHIFT 0x2
3629#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x100
3630#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
3631#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x200
3632#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
3633#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x400
3634#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
3635#define SWRST_EP_COMMAND_0__EP_FLR0_RESET_MASK 0x10000
3636#define SWRST_EP_COMMAND_0__EP_FLR0_RESET__SHIFT 0x10
3637#define SWRST_EP_COMMAND_0__EP_FLR1_RESET_MASK 0x20000
3638#define SWRST_EP_COMMAND_0__EP_FLR1_RESET__SHIFT 0x11
3639#define SWRST_EP_COMMAND_0__EP_FLR2_RESET_MASK 0x40000
3640#define SWRST_EP_COMMAND_0__EP_FLR2_RESET__SHIFT 0x12
3641#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x1
3642#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
3643#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN_MASK 0x2
3644#define SWRST_EP_CONTROL_0__EP_SOFT_RESET_EN__SHIFT 0x1
3645#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN_MASK 0x4
3646#define SWRST_EP_CONTROL_0__EP_DRV_RESET_EN__SHIFT 0x2
3647#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x100
3648#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
3649#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x200
3650#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
3651#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x400
3652#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
3653#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN_MASK 0x10000
3654#define SWRST_EP_CONTROL_0__EP_FLR0_RESET_EN__SHIFT 0x10
3655#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN_MASK 0x20000
3656#define SWRST_EP_CONTROL_0__EP_FLR1_RESET_EN__SHIFT 0x11
3657#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN_MASK 0x40000
3658#define SWRST_EP_CONTROL_0__EP_FLR2_RESET_EN__SHIFT 0x12
3659#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN_MASK 0x80000
3660#define SWRST_EP_CONTROL_0__EP_CFG_WR_RESET_EN__SHIFT 0x13
3661#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST_MASK 0xf00000
3662#define SWRST_EP_CONTROL_0__EP_FLR_DISABLE_CFG_RST__SHIFT 0x14
3663#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
3664#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
3665#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
3666#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
3667#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
3668#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
3669#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
3670#define CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
3671#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
3672#define CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
3673#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
3674#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
3675#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
3676#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
3677#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
3678#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
3679#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
3680#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
3681#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
3682#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
3683#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
3684#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
3685#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
3686#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
3687#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
3688#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
3689#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
3690#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
3691#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
3692#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
3693#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
3694#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
3695#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
3696#define CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
3697#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
3698#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
3699#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
3700#define CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
3701#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
3702#define CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
3703#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
3704#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
3705#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
3706#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
3707#define CPM_CONTROL__SPARE_REGS_MASK 0xff000000
3708#define CPM_CONTROL__SPARE_REGS__SHIFT 0x18
3709#define GSKT_CONTROL__GSKT_TxFifoBypass_MASK 0x1
3710#define GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT 0x0
3711#define GSKT_CONTROL__GSKT_TxFifoDelay_MASK 0x2
3712#define GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT 0x1
3713#define GSKT_CONTROL__GSKT_TxFifoDelay2_MASK 0x4
3714#define GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT 0x2
3715#define GSKT_CONTROL__GSKT_SpareRegs_MASK 0xf8
3716#define GSKT_CONTROL__GSKT_SpareRegs__SHIFT 0x3
3717#define LM_CONTROL__LoopbackSelect_MASK 0x1e
3718#define LM_CONTROL__LoopbackSelect__SHIFT 0x1
3719#define LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
3720#define LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
3721#define LM_CONTROL__LoopbackHalfRate_MASK 0xc0
3722#define LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
3723#define LM_CONTROL__LoopbackFifoPtr_MASK 0x700
3724#define LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
3725#define LM_PCIETXMUX0__TXLANE0_MASK 0xff
3726#define LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
3727#define LM_PCIETXMUX0__TXLANE1_MASK 0xff00
3728#define LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
3729#define LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
3730#define LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
3731#define LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
3732#define LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
3733#define LM_PCIETXMUX1__TXLANE4_MASK 0xff
3734#define LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
3735#define LM_PCIETXMUX1__TXLANE5_MASK 0xff00
3736#define LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
3737#define LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
3738#define LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
3739#define LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
3740#define LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
3741#define LM_PCIETXMUX2__TXLANE8_MASK 0xff
3742#define LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
3743#define LM_PCIETXMUX2__TXLANE9_MASK 0xff00
3744#define LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
3745#define LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
3746#define LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
3747#define LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
3748#define LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
3749#define LM_PCIETXMUX3__TXLANE12_MASK 0xff
3750#define LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
3751#define LM_PCIETXMUX3__TXLANE13_MASK 0xff00
3752#define LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
3753#define LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
3754#define LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
3755#define LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
3756#define LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
3757#define LM_PCIERXMUX0__RXLANE0_MASK 0xff
3758#define LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
3759#define LM_PCIERXMUX0__RXLANE1_MASK 0xff00
3760#define LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
3761#define LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
3762#define LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
3763#define LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
3764#define LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
3765#define LM_PCIERXMUX1__RXLANE4_MASK 0xff
3766#define LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
3767#define LM_PCIERXMUX1__RXLANE5_MASK 0xff00
3768#define LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
3769#define LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
3770#define LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
3771#define LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
3772#define LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
3773#define LM_PCIERXMUX2__RXLANE8_MASK 0xff
3774#define LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
3775#define LM_PCIERXMUX2__RXLANE9_MASK 0xff00
3776#define LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
3777#define LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
3778#define LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
3779#define LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
3780#define LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
3781#define LM_PCIERXMUX3__RXLANE12_MASK 0xff
3782#define LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
3783#define LM_PCIERXMUX3__RXLANE13_MASK 0xff00
3784#define LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
3785#define LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
3786#define LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
3787#define LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
3788#define LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
3789#define LM_LANEENABLE__LANE_enable_MASK 0xffff
3790#define LM_LANEENABLE__LANE_enable__SHIFT 0x0
3791#define LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
3792#define LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
3793#define LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
3794#define LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
3795#define LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
3796#define LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
3797#define LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
3798#define LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
3799#define LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
3800#define LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
3801#define LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
3802#define LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
3803#define LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
3804#define LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
3805#define LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
3806#define LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
3807#define LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
3808#define LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
3809#define LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
3810#define LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
3811#define LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
3812#define LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
3813#define LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
3814#define LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
3815#define LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
3816#define LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
3817#define LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
3818#define LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
3819#define LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
3820#define LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
3821#define LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
3822#define LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
3823#define LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
3824#define LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
3825#define LM_POWERCONTROL1__LMTxEn0_MASK 0x1
3826#define LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
3827#define LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
3828#define LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
3829#define LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
3830#define LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
3831#define LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
3832#define LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
3833#define LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
3834#define LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
3835#define LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
3836#define LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
3837#define LM_POWERCONTROL1__LMDeemph0_MASK 0x100
3838#define LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
3839#define LM_POWERCONTROL1__LMTxEn1_MASK 0x200
3840#define LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
3841#define LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
3842#define LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
3843#define LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
3844#define LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
3845#define LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
3846#define LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
3847#define LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
3848#define LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
3849#define LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
3850#define LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
3851#define LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
3852#define LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
3853#define LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
3854#define LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
3855#define LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
3856#define LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
3857#define LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
3858#define LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
3859#define LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
3860#define LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
3861#define LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
3862#define LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
3863#define LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
3864#define LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
3865#define LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
3866#define LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
3867#define LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
3868#define LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
3869#define LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
3870#define LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
3871#define LM_POWERCONTROL2__LMTxEn3_MASK 0x1
3872#define LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
3873#define LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
3874#define LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
3875#define LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
3876#define LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
3877#define LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
3878#define LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
3879#define LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
3880#define LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
3881#define LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
3882#define LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
3883#define LM_POWERCONTROL2__LMDeemph3_MASK 0x100
3884#define LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
3885#define LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
3886#define LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
3887#define LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
3888#define LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
3889#define LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
3890#define LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
3891#define LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
3892#define LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
3893#define LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
3894#define LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
3895#define LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
3896#define LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
3897#define LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
3898#define LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
3899#define LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
3900#define LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
3901#define LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
3902#define LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
3903#define LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
3904#define LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
3905#define LM_POWERCONTROL4__LinkNum0_MASK 0x7
3906#define LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
3907#define LM_POWERCONTROL4__LinkNum1_MASK 0x38
3908#define LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
3909#define LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
3910#define LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
3911#define LM_POWERCONTROL4__LinkNum3_MASK 0xe00
3912#define LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
3913#define LM_POWERCONTROL4__LaneNum0_MASK 0xf000
3914#define LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
3915#define LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
3916#define LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
3917#define LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
3918#define LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
3919#define LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
3920#define LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
3921#define LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
3922#define LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
3923#define LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
3924#define LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
3925#define LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
3926#define LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
3927#define LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
3928#define LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
3929#define PB0_GLB_CTRL_REG0__BACKUP_MASK 0xffff
3930#define PB0_GLB_CTRL_REG0__BACKUP__SHIFT 0x0
3931#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK 0x30000
3932#define PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT 0x10
3933#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK 0x700000
3934#define PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT 0x14
3935#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK 0x800000
3936#define PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT 0x17
3937#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK 0x1000000
3938#define PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT 0x18
3939#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK 0x2000000
3940#define PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT 0x19
3941#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK 0x4000000
3942#define PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT 0x1a
3943#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK 0xc0000000
3944#define PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT 0x1e
3945#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK 0x1
3946#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT 0x0
3947#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK 0x7e
3948#define PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT 0x1
3949#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK 0x80
3950#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT 0x7
3951#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK 0x3f00
3952#define PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT 0x8
3953#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK 0x4000
3954#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT 0xe
3955#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK 0x3f8000
3956#define PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT 0xf
3957#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK 0x400000
3958#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT 0x16
3959#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK 0x3f800000
3960#define PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT 0x17
3961#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK 0x40000000
3962#define PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT 0x1e
3963#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK 0x80000000
3964#define PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT 0x1f
3965#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK 0x1
3966#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT 0x0
3967#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK 0xfe
3968#define PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT 0x1
3969#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK 0x100
3970#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT 0x8
3971#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK 0xfe00
3972#define PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT 0x9
3973#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK 0x10000
3974#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT 0x10
3975#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK 0xfe0000
3976#define PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT 0x11
3977#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK 0x1000000
3978#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT 0x18
3979#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK 0xfe000000
3980#define PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT 0x19
3981#define PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK 0x1f
3982#define PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT 0x0
3983#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK 0x60
3984#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x5
3985#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
3986#define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT 0x7
3987#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
3988#define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT 0x9
3989#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK 0x800
3990#define PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT 0xb
3991#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK 0x1000
3992#define PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT 0xc
3993#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK 0x1c000
3994#define PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT 0xe
3995#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK 0x1c0000
3996#define PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT 0x12
3997#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK 0x200000
3998#define PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT 0x15
3999#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK 0x400000
4000#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x16
4001#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK 0x7800000
4002#define PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x17
4003#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK 0x8000000
4004#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT 0x1b
4005#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK 0x70000000
4006#define PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT 0x1c
4007#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK 0x80000000
4008#define PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT 0x1f
4009#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK 0xffff
4010#define PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT 0x0
4011#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK 0x30000
4012#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT 0x10
4013#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK 0x40000
4014#define PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT 0x12
4015#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK 0x3c00000
4016#define PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT 0x16
4017#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK 0x4000000
4018#define PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT 0x1a
4019#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK 0x8000000
4020#define PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT 0x1b
4021#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK 0x10000000
4022#define PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT 0x1c
4023#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK 0xff
4024#define PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT 0x0
4025#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK 0x1
4026#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT 0x0
4027#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK 0x2
4028#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT 0x1
4029#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK 0x4
4030#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT 0x2
4031#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK 0x8
4032#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT 0x3
4033#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK 0x10
4034#define PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT 0x4
4035#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK 0xf00
4036#define PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT 0x8
4037#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK 0xf000
4038#define PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT 0xc
4039#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK 0xf0000
4040#define PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT 0x10
4041#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK 0x100000
4042#define PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT 0x14
4043#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK 0x1
4044#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT 0x0
4045#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK 0x2
4046#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT 0x1
4047#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK 0x4
4048#define PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT 0x2
4049#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK 0x1000
4050#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT 0xc
4051#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK 0x2000
4052#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT 0xd
4053#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK 0x4000
4054#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT 0xe
4055#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK 0x8000
4056#define PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT 0xf
4057#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK 0x30000
4058#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT 0x10
4059#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK 0xc0000
4060#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT 0x12
4061#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK 0x300000
4062#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT 0x14
4063#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK 0xc00000
4064#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT 0x16
4065#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK 0x3000000
4066#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT 0x18
4067#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK 0xc000000
4068#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT 0x1a
4069#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK 0x30000000
4070#define PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT 0x1c
4071#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK 0xc0000000
4072#define PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT 0x1e
4073#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK 0x1
4074#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT 0x0
4075#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK 0x2
4076#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT 0x1
4077#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK 0x4
4078#define PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT 0x2
4079#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK 0x1000
4080#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT 0xc
4081#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK 0x2000
4082#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT 0xd
4083#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK 0x4000
4084#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT 0xe
4085#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK 0x8000
4086#define PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT 0xf
4087#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK 0x30000
4088#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT 0x10
4089#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK 0xc0000
4090#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT 0x12
4091#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK 0x300000
4092#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT 0x14
4093#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK 0xc00000
4094#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT 0x16
4095#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK 0x3000000
4096#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT 0x18
4097#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK 0xc000000
4098#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT 0x1a
4099#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK 0x30000000
4100#define PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT 0x1c
4101#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK 0xc0000000
4102#define PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT 0x1e
4103#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK 0x1
4104#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT 0x0
4105#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK 0x2
4106#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT 0x1
4107#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK 0x4
4108#define PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT 0x2
4109#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK 0x1000
4110#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT 0xc
4111#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK 0x2000
4112#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT 0xd
4113#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK 0x4000
4114#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT 0xe
4115#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK 0x8000
4116#define PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT 0xf
4117#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK 0x30000
4118#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT 0x10
4119#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK 0xc0000
4120#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT 0x12
4121#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK 0x300000
4122#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT 0x14
4123#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK 0xc00000
4124#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT 0x16
4125#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK 0x3000000
4126#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT 0x18
4127#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK 0xc000000
4128#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT 0x1a
4129#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK 0x30000000
4130#define PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT 0x1c
4131#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK 0xc0000000
4132#define PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT 0x1e
4133#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK 0x1
4134#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT 0x0
4135#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK 0x2
4136#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT 0x1
4137#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK 0x4
4138#define PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT 0x2
4139#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK 0x1000
4140#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT 0xc
4141#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK 0x2000
4142#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT 0xd
4143#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK 0x4000
4144#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT 0xe
4145#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK 0x8000
4146#define PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT 0xf
4147#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK 0x30000
4148#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT 0x10
4149#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK 0xc0000
4150#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT 0x12
4151#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK 0x300000
4152#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT 0x14
4153#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK 0xc00000
4154#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT 0x16
4155#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK 0x3000000
4156#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT 0x18
4157#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK 0xc000000
4158#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT 0x1a
4159#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK 0x30000000
4160#define PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT 0x1c
4161#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK 0xc0000000
4162#define PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT 0x1e
4163#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK 0xffff
4164#define PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT 0x0
4165#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK 0xffff0000
4166#define PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT 0x10
4167#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK 0x1
4168#define PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT 0x0
4169#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK 0x2
4170#define PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT 0x1
4171#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK 0x4
4172#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT 0x2
4173#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK 0x8
4174#define PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT 0x3
4175#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK 0x8000
4176#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT 0xf
4177#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK 0xffff0000
4178#define PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT 0x10
4179#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK 0x1
4180#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT 0x0
4181#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK 0x2
4182#define PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT 0x1
4183#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK 0x4
4184#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT 0x2
4185#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK 0x8
4186#define PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT 0x3
4187#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK 0x10
4188#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT 0x4
4189#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK 0x20
4190#define PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT 0x5
4191#define PB0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
4192#define PB0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
4193#define PB0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
4194#define PB0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
4195#define PB0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
4196#define PB0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
4197#define PB0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
4198#define PB0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
4199#define PB0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
4200#define PB0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
4201#define PB0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
4202#define PB0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
4203#define PB0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
4204#define PB0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
4205#define PB0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
4206#define PB0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
4207#define PB0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
4208#define PB0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
4209#define PB0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
4210#define PB0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
4211#define PB0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
4212#define PB0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
4213#define PB0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
4214#define PB0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
4215#define PB0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
4216#define PB0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
4217#define PB0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
4218#define PB0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
4219#define PB0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
4220#define PB0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
4221#define PB0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
4222#define PB0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
4223#define PB0_HW_DEBUG__HW_16_DEBUG_MASK 0x10000
4224#define PB0_HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
4225#define PB0_HW_DEBUG__HW_17_DEBUG_MASK 0x20000
4226#define PB0_HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
4227#define PB0_HW_DEBUG__HW_18_DEBUG_MASK 0x40000
4228#define PB0_HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
4229#define PB0_HW_DEBUG__HW_19_DEBUG_MASK 0x80000
4230#define PB0_HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
4231#define PB0_HW_DEBUG__HW_20_DEBUG_MASK 0x100000
4232#define PB0_HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
4233#define PB0_HW_DEBUG__HW_21_DEBUG_MASK 0x200000
4234#define PB0_HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
4235#define PB0_HW_DEBUG__HW_22_DEBUG_MASK 0x400000
4236#define PB0_HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
4237#define PB0_HW_DEBUG__HW_23_DEBUG_MASK 0x800000
4238#define PB0_HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
4239#define PB0_HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
4240#define PB0_HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
4241#define PB0_HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
4242#define PB0_HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
4243#define PB0_HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
4244#define PB0_HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
4245#define PB0_HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
4246#define PB0_HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
4247#define PB0_HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
4248#define PB0_HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
4249#define PB0_HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
4250#define PB0_HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
4251#define PB0_HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
4252#define PB0_HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
4253#define PB0_HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
4254#define PB0_HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
4255#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK 0x2
4256#define PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT 0x1
4257#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK 0x4
4258#define PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT 0x2
4259#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK 0x8
4260#define PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT 0x3
4261#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK 0x10
4262#define PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT 0x4
4263#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK 0x60
4264#define PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT 0x5
4265#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK 0xf80
4266#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT 0x7
4267#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK 0x1000
4268#define PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT 0xc
4269#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK 0x2000
4270#define PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT 0xd
4271#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK 0x4000
4272#define PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT 0xe
4273#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK 0x8000
4274#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT 0xf
4275#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK 0xf0000
4276#define PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT 0x10
4277#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK 0x100000
4278#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT 0x14
4279#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK 0x1e00000
4280#define PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT 0x15
4281#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK 0x1e
4282#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT 0x1
4283#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK 0x1e0
4284#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT 0x5
4285#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK 0x3e00
4286#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT 0x9
4287#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK 0x7c000
4288#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT 0xe
4289#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK 0x780000
4290#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT 0x13
4291#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK 0x7800000
4292#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT 0x17
4293#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK 0x8000000
4294#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT 0x1b
4295#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK 0x10000000
4296#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT 0x1c
4297#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK 0x20000000
4298#define PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT 0x1d
4299#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK 0x40000000
4300#define PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT 0x1e
4301#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK 0x1e
4302#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT 0x1
4303#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK 0x20
4304#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT 0x5
4305#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK 0x40
4306#define PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT 0x6
4307#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK 0x80
4308#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT 0x7
4309#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK 0x300
4310#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT 0x8
4311#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK 0xc00
4312#define PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT 0xa
4313#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK 0xf000
4314#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT 0xc
4315#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK 0xf0000
4316#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT 0x10
4317#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK 0xf00000
4318#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT 0x14
4319#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK 0xf000000
4320#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT 0x18
4321#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK 0x70000000
4322#define PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT 0x1c
4323#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK 0x80000000
4324#define PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT 0x1f
4325#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK 0x2
4326#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT 0x1
4327#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK 0x1c
4328#define PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT 0x2
4329#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK 0x60
4330#define PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT 0x5
4331#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK 0x80
4332#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT 0x7
4333#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK 0x700
4334#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT 0x8
4335#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK 0x7800
4336#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT 0xb
4337#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK 0x1ff8000
4338#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT 0xf
4339#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK 0x1e000000
4340#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT 0x19
4341#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK 0x60000000
4342#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT 0x1d
4343#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK 0x80000000
4344#define PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT 0x1f
4345#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK 0xe
4346#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT 0x1
4347#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK 0x1ff0
4348#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT 0x4
4349#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK 0x2000
4350#define PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT 0xd
4351#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK 0x8000
4352#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT 0xf
4353#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK 0xff0000
4354#define PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT 0x10
4355#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK 0x1000000
4356#define PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT 0x18
4357#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK 0x2
4358#define PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT 0x1
4359#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK 0x4
4360#define PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT 0x2
4361#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK 0x6
4362#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT 0x1
4363#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK 0x18
4364#define PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT 0x3
4365#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK 0x60
4366#define PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT 0x5
4367#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK 0x80
4368#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT 0x7
4369#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK 0x300
4370#define PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT 0x8
4371#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK 0x400
4372#define PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT 0xa
4373#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK 0x1800
4374#define PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT 0xb
4375#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK 0x1c
4376#define PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT 0x2
4377#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK 0x60
4378#define PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT 0x5
4379#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK 0x180
4380#define PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT 0x7
4381#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK 0x600
4382#define PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT 0x9
4383#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK 0x1800
4384#define PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT 0xb
4385#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK 0x10000000
4386#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT 0x1c
4387#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK 0x20000000
4388#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT 0x1d
4389#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK 0xc0000000
4390#define PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT 0x1e
4391#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK 0x3f
4392#define PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT 0x0
4393#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK 0x80
4394#define PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT 0x7
4395#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK 0xf00
4396#define PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT 0x8
4397#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK 0x100000
4398#define PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT 0x14
4399#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK 0x200000
4400#define PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT 0x15
4401#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK 0x400000
4402#define PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT 0x16
4403#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK 0x800000
4404#define PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT 0x17
4405#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK 0xff000000
4406#define PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT 0x18
4407#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK 0xff
4408#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT 0x0
4409#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK 0x100
4410#define PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT 0x8
4411#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK 0x10000
4412#define PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT 0x10
4413#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK 0xe0000
4414#define PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT 0x11
4415#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK 0xf00000
4416#define PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT 0x14
4417#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK 0xffff
4418#define PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT 0x0
4419#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK 0x1
4420#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT 0x0
4421#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK 0x3e
4422#define PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT 0x1
4423#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK 0xff
4424#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT 0x0
4425#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK 0xff00
4426#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT 0x8
4427#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK 0x10000
4428#define PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT 0x10
4429#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK 0x1
4430#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT 0x0
4431#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x2
4432#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x1
4433#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x4
4434#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0x2
4435#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x8
4436#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT 0x3
4437#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK 0x10
4438#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT 0x4
4439#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK 0x20
4440#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT 0x5
4441#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK 0x40
4442#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT 0x6
4443#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK 0x80
4444#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT 0x7
4445#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK 0x100
4446#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT 0x8
4447#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK 0x200
4448#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT 0x9
4449#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK 0x400
4450#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT 0xa
4451#define PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK 0x800
4452#define PB0_PLL_RO_G