1/*
2 * BIF_5_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef BIF_5_1_SH_MASK_H
25#define BIF_5_1_SH_MASK_H
26
27#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28#define MM_INDEX__MM_OFFSET__SHIFT 0x0
29#define MM_INDEX__MM_APER_MASK 0x80000000
30#define MM_INDEX__MM_APER__SHIFT 0x1f
31#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33#define MM_DATA__MM_DATA_MASK 0xffffffff
34#define MM_DATA__MM_DATA__SHIFT 0x0
35#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
37#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
38#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
39#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
40#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
41#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
42#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
43#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
44#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
45#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
46#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
47#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
48#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
49#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
50#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
51#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
52#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
53#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
54#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
55#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
56#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
57#define BUS_CNTL__SET_MC_TC_MASK 0xe000
58#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
59#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
60#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
61#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
62#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
63#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
64#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
65#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
66#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
67#define CONFIG_CNTL__VGA_DIS_MASK 0x2
68#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
69#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
70#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
71#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
72#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
73#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
74#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
75#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
76#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
77#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
78#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
79#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
80#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
81#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
82#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
83#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
84#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
85#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
86#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
87#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
88#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
89#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
90#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
91#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
92#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
93#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
94#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
95#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
96#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
97#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
98#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
99#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
100#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
101#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
102#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
103#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
104#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
105#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
106#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
107#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
108#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
109#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
110#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
111#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
112#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
113#define HW_DEBUG__HW_09_DEBUG_MASK 0x200
114#define HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
115#define HW_DEBUG__HW_10_DEBUG_MASK 0x400
116#define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
117#define HW_DEBUG__HW_11_DEBUG_MASK 0x800
118#define HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
119#define HW_DEBUG__HW_12_DEBUG_MASK 0x1000
120#define HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
121#define HW_DEBUG__HW_13_DEBUG_MASK 0x2000
122#define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
123#define HW_DEBUG__HW_14_DEBUG_MASK 0x4000
124#define HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
125#define HW_DEBUG__HW_15_DEBUG_MASK 0x8000
126#define HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
127#define HW_DEBUG__HW_16_DEBUG_MASK 0x10000
128#define HW_DEBUG__HW_16_DEBUG__SHIFT 0x10
129#define HW_DEBUG__HW_17_DEBUG_MASK 0x20000
130#define HW_DEBUG__HW_17_DEBUG__SHIFT 0x11
131#define HW_DEBUG__HW_18_DEBUG_MASK 0x40000
132#define HW_DEBUG__HW_18_DEBUG__SHIFT 0x12
133#define HW_DEBUG__HW_19_DEBUG_MASK 0x80000
134#define HW_DEBUG__HW_19_DEBUG__SHIFT 0x13
135#define HW_DEBUG__HW_20_DEBUG_MASK 0x100000
136#define HW_DEBUG__HW_20_DEBUG__SHIFT 0x14
137#define HW_DEBUG__HW_21_DEBUG_MASK 0x200000
138#define HW_DEBUG__HW_21_DEBUG__SHIFT 0x15
139#define HW_DEBUG__HW_22_DEBUG_MASK 0x400000
140#define HW_DEBUG__HW_22_DEBUG__SHIFT 0x16
141#define HW_DEBUG__HW_23_DEBUG_MASK 0x800000
142#define HW_DEBUG__HW_23_DEBUG__SHIFT 0x17
143#define HW_DEBUG__HW_24_DEBUG_MASK 0x1000000
144#define HW_DEBUG__HW_24_DEBUG__SHIFT 0x18
145#define HW_DEBUG__HW_25_DEBUG_MASK 0x2000000
146#define HW_DEBUG__HW_25_DEBUG__SHIFT 0x19
147#define HW_DEBUG__HW_26_DEBUG_MASK 0x4000000
148#define HW_DEBUG__HW_26_DEBUG__SHIFT 0x1a
149#define HW_DEBUG__HW_27_DEBUG_MASK 0x8000000
150#define HW_DEBUG__HW_27_DEBUG__SHIFT 0x1b
151#define HW_DEBUG__HW_28_DEBUG_MASK 0x10000000
152#define HW_DEBUG__HW_28_DEBUG__SHIFT 0x1c
153#define HW_DEBUG__HW_29_DEBUG_MASK 0x20000000
154#define HW_DEBUG__HW_29_DEBUG__SHIFT 0x1d
155#define HW_DEBUG__HW_30_DEBUG_MASK 0x40000000
156#define HW_DEBUG__HW_30_DEBUG__SHIFT 0x1e
157#define HW_DEBUG__HW_31_DEBUG_MASK 0x80000000
158#define HW_DEBUG__HW_31_DEBUG__SHIFT 0x1f
159#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT_MASK 0x7f
160#define MASTER_CREDIT_CNTL__BIF_MC_RDRET_CREDIT__SHIFT 0x0
161#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
162#define MASTER_CREDIT_CNTL__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
163#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT_MASK 0x1f
164#define SLAVE_REQ_CREDIT_CNTL__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
165#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT_MASK 0x1e0
166#define SLAVE_REQ_CREDIT_CNTL__BIF_VGA_REQ_CREDIT__SHIFT 0x5
167#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT_MASK 0x7c00
168#define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
169#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT_MASK 0x8000
170#define SLAVE_REQ_CREDIT_CNTL__BIF_ROM_REQ_CREDIT__SHIFT 0xf
171#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT_MASK 0x100000
172#define SLAVE_REQ_CREDIT_CNTL__BIF_AZ_REQ_CREDIT__SHIFT 0x14
173#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
174#define SLAVE_REQ_CREDIT_CNTL__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
175#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x1
176#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
177#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x1
178#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
179#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x2
180#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
181#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
182#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
183#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0xf0
184#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
185#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x100
186#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
187#define INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK 0x1e00
188#define INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT 0x9
189#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
190#define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
191#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
192#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
193#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xffffffff
194#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
195#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x1
196#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x0
197#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x2
198#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x1
199#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x4
200#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x2
201#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
202#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x3
203#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x10
204#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x4
205#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x20
206#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x5
207#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN_MASK 0x40
208#define BIF_DEBUG_CNTL__DEBUG_SYNC_EN__SHIFT 0x6
209#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x80
210#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x7
211#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x1f00
212#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
213#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x1f0000
214#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x10
215#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x1000000
216#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x18
217#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
218#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
219#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1_MASK 0x3f
220#define BIF_DEBUG_MUX__DEBUG_MUX_BLK1__SHIFT 0x0
221#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2_MASK 0x3f00
222#define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
223#define BIF_DEBUG_OUT__DEBUG_OUTPUT_MASK 0x1ffff
224#define BIF_DEBUG_OUT__DEBUG_OUTPUT__SHIFT 0x0
225#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x1
226#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
227#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x1
228#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
229#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x1
230#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
231#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x2
232#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
233#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x4
234#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
235#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x18
236#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
237#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x20
238#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
239#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x40
240#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
241#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x80
242#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
243#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x100
244#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
245#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x200
246#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
247#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x400
248#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
249#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x800
250#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
251#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x1000
252#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
253#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A_MASK 0x1
254#define SMBDAT_PAD_CNTL__SMBDAT_PAD_A__SHIFT 0x0
255#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL_MASK 0x2
256#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SEL__SHIFT 0x1
257#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE_MASK 0x4
258#define SMBDAT_PAD_CNTL__SMBDAT_PAD_MODE__SHIFT 0x2
259#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE_MASK 0x18
260#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SPARE__SHIFT 0x3
261#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0_MASK 0x20
262#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN0__SHIFT 0x5
263#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1_MASK 0x40
264#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN1__SHIFT 0x6
265#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2_MASK 0x80
266#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN2__SHIFT 0x7
267#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3_MASK 0x100
268#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SN3__SHIFT 0x8
269#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN_MASK 0x200
270#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SLEWN__SHIFT 0x9
271#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE_MASK 0x400
272#define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
273#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN_MASK 0x800
274#define SMBDAT_PAD_CNTL__SMBDAT_PAD_SCHMEN__SHIFT 0xb
275#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN_MASK 0x1000
276#define SMBDAT_PAD_CNTL__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
277#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A_MASK 0x1
278#define SMBCLK_PAD_CNTL__SMBCLK_PAD_A__SHIFT 0x0
279#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL_MASK 0x2
280#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SEL__SHIFT 0x1
281#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE_MASK 0x4
282#define SMBCLK_PAD_CNTL__SMBCLK_PAD_MODE__SHIFT 0x2
283#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE_MASK 0x18
284#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SPARE__SHIFT 0x3
285#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0_MASK 0x20
286#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN0__SHIFT 0x5
287#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1_MASK 0x40
288#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN1__SHIFT 0x6
289#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2_MASK 0x80
290#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN2__SHIFT 0x7
291#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3_MASK 0x100
292#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SN3__SHIFT 0x8
293#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN_MASK 0x200
294#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SLEWN__SHIFT 0x9
295#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE_MASK 0x400
296#define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
297#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN_MASK 0x800
298#define SMBCLK_PAD_CNTL__SMBCLK_PAD_SCHMEN__SHIFT 0xb
299#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN_MASK 0x1000
300#define SMBCLK_PAD_CNTL__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
301#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
302#define BIF_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
303#define BIF_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000
304#define BIF_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
305#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
306#define BIF_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
307#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x1
308#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
309#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x2
310#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
311#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x4
312#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
313#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x8
314#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
315#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
316#define BIF_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
317#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
318#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
319#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
320#define BIF_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
321#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
322#define BIF_FEATURES_CONTROL_MISC__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
323#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
324#define BIF_FEATURES_CONTROL_MISC__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
325#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
326#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
327#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
328#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
329#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
330#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
331#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
332#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
333#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x1
334#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
335#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x2
336#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
337#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x4
338#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
339#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
340#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
341#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x10
342#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
343#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x20
344#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
345#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
346#define BIF_DOORBELL_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
347#define BIF_SLVARB_MODE__SLVARB_MODE_MASK 0x3
348#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0
349#define BIF_FB_EN__FB_READ_EN_MASK 0x1
350#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0
351#define BIF_FB_EN__FB_WRITE_EN_MASK 0x2
352#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
353#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0xff
354#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
355#define BIF_BUSNUM_LIST0__ID0_MASK 0xff
356#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x0
357#define BIF_BUSNUM_LIST0__ID1_MASK 0xff00
358#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x8
359#define BIF_BUSNUM_LIST0__ID2_MASK 0xff0000
360#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x10
361#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000
362#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x18
363#define BIF_BUSNUM_LIST1__ID4_MASK 0xff
364#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x0
365#define BIF_BUSNUM_LIST1__ID5_MASK 0xff00
366#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x8
367#define BIF_BUSNUM_LIST1__ID6_MASK 0xff0000
368#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x10
369#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000
370#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x18
371#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0xff
372#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
373#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x100
374#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
375#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x10000
376#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
377#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
378#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
379#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x3f
380#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0
381#define BIF_PERFMON_CNTL__PERFCOUNTER_EN_MASK 0x1
382#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0
383#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0_MASK 0x2
384#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1
385#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1_MASK 0x4
386#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2
387#define BIF_PERFMON_CNTL__PERF_SEL0_MASK 0x1f00
388#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8
389#define BIF_PERFMON_CNTL__PERF_SEL1_MASK 0x3e000
390#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
391#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
392#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
393#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT_MASK 0xffffffff
394#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0
395#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL_MASK 0xe
396#define SLAVE_HANG_PROTECTION_CNTL__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
397#define GPU_HDP_FLUSH_REQ__CP0_MASK 0x1
398#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
399#define GPU_HDP_FLUSH_REQ__CP1_MASK 0x2
400#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
401#define GPU_HDP_FLUSH_REQ__CP2_MASK 0x4
402#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
403#define GPU_HDP_FLUSH_REQ__CP3_MASK 0x8
404#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
405#define GPU_HDP_FLUSH_REQ__CP4_MASK 0x10
406#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
407#define GPU_HDP_FLUSH_REQ__CP5_MASK 0x20
408#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
409#define GPU_HDP_FLUSH_REQ__CP6_MASK 0x40
410#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
411#define GPU_HDP_FLUSH_REQ__CP7_MASK 0x80
412#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
413#define GPU_HDP_FLUSH_REQ__CP8_MASK 0x100
414#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
415#define GPU_HDP_FLUSH_REQ__CP9_MASK 0x200
416#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
417#define GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x400
418#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
419#define GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x800
420#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
421#define GPU_HDP_FLUSH_DONE__CP0_MASK 0x1
422#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
423#define GPU_HDP_FLUSH_DONE__CP1_MASK 0x2
424#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
425#define GPU_HDP_FLUSH_DONE__CP2_MASK 0x4
426#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
427#define GPU_HDP_FLUSH_DONE__CP3_MASK 0x8
428#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
429#define GPU_HDP_FLUSH_DONE__CP4_MASK 0x10
430#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
431#define GPU_HDP_FLUSH_DONE__CP5_MASK 0x20
432#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
433#define GPU_HDP_FLUSH_DONE__CP6_MASK 0x40
434#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
435#define GPU_HDP_FLUSH_DONE__CP7_MASK 0x80
436#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
437#define GPU_HDP_FLUSH_DONE__CP8_MASK 0x100
438#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
439#define GPU_HDP_FLUSH_DONE__CP9_MASK 0x200
440#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
441#define GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x400
442#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
443#define GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x800
444#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
445#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR_MASK 0x1
446#define SLAVE_HANG_ERROR__SRBM_HANG_ERROR__SHIFT 0x0
447#define SLAVE_HANG_ERROR__HDP_HANG_ERROR_MASK 0x2
448#define SLAVE_HANG_ERROR__HDP_HANG_ERROR__SHIFT 0x1
449#define SLAVE_HANG_ERROR__VGA_HANG_ERROR_MASK 0x4
450#define SLAVE_HANG_ERROR__VGA_HANG_ERROR__SHIFT 0x2
451#define SLAVE_HANG_ERROR__ROM_HANG_ERROR_MASK 0x8
452#define SLAVE_HANG_ERROR__ROM_HANG_ERROR__SHIFT 0x3
453#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR_MASK 0x10
454#define SLAVE_HANG_ERROR__AUDIO_HANG_ERROR__SHIFT 0x4
455#define SLAVE_HANG_ERROR__CEC_HANG_ERROR_MASK 0x20
456#define SLAVE_HANG_ERROR__CEC_HANG_ERROR__SHIFT 0x5
457#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR_MASK 0x80
458#define SLAVE_HANG_ERROR__XDMA_HANG_ERROR__SHIFT 0x7
459#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR_MASK 0x100
460#define SLAVE_HANG_ERROR__DOORBELL_HANG_ERROR__SHIFT 0x8
461#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR_MASK 0x200
462#define SLAVE_HANG_ERROR__GARLIC_HANG_ERROR__SHIFT 0x9
463#define CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x1
464#define CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
465#define HOST_BUSNUM__HOST_ID_MASK 0xffff
466#define HOST_BUSNUM__HOST_ID__SHIFT 0x0
467#define PEER_REG_RANGE0__START_ADDR_MASK 0xffff
468#define PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
469#define PEER_REG_RANGE0__END_ADDR_MASK 0xffff0000
470#define PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
471#define PEER_REG_RANGE1__START_ADDR_MASK 0xffff
472#define PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
473#define PEER_REG_RANGE1__END_ADDR_MASK 0xffff0000
474#define PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
475#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0xfffff
476#define PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
477#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0xfffff
478#define PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
479#define PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000
480#define PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
481#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0xfffff
482#define PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
483#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0xfffff
484#define PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
485#define PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000
486#define PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
487#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0xfffff
488#define PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
489#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0xfffff
490#define PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
491#define PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000
492#define PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
493#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0xfffff
494#define PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
495#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0xfffff
496#define PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
497#define PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000
498#define PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
499#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
500#define DBG_BYPASS_SRBM_ACCESS__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
501#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD_MASK 0x1e
502#define DBG_BYPASS_SRBM_ACCESS__DBG_APER_AD__SHIFT 0x1
503#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
504#define SMBUS_BACO_DUMMY__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
505#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0xff
506#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
507#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0xff00
508#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
509#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0xff0000
510#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
511#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xff000000
512#define BIF_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
513#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0xff
514#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
515#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0xff00
516#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
517#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0xff0000
518#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
519#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xff000000
520#define BIF_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
521#define BACO_CNTL__BACO_EN_MASK 0x1
522#define BACO_CNTL__BACO_EN__SHIFT 0x0
523#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x2
524#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x1
525#define BACO_CNTL__BACO_ISO_DIS_MASK 0x4
526#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x2
527#define BACO_CNTL__BACO_POWER_OFF_MASK 0x8
528#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
529#define BACO_CNTL__BACO_RESET_EN_MASK 0x10
530#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x4
531#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x20
532#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x5
533#define BACO_CNTL__BACO_MODE_MASK 0x40
534#define BACO_CNTL__BACO_MODE__SHIFT 0x6
535#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x80
536#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x7
537#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x100
538#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x8
539#define BACO_CNTL__PWRGOOD_BF_MASK 0x200
540#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x9
541#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x400
542#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
543#define BACO_CNTL__PWRGOOD_MEM_MASK 0x800
544#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0xb
545#define BACO_CNTL__PWRGOOD_DVO_MASK 0x1000
546#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0xc
547#define BACO_CNTL__PWRGOOD_IDSC_MASK 0x2000
548#define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
549#define BACO_CNTL__BACO_POWER_OFF_DRAM_MASK 0x10000
550#define BACO_CNTL__BACO_POWER_OFF_DRAM__SHIFT 0x10
551#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
552#define BACO_CNTL__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
553#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x1
554#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
555#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x2
556#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
557#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x1
558#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
559#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x1
560#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
561#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x1
562#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x0
563#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x1
564#define BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
565#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x2
566#define BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
567#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
568#define BACO_CNTL_MISC__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
569#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK 0x1
570#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
571#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
572#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
573#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
574#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
575#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
576#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
577#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
578#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
579#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
580#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
581#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
582#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
583#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
584#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
585#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
586#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
587#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
588#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
589#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
590#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
591#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
592#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
593#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
594#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
595#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
596#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
597#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
598#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
599#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
600#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
601#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
602#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
603#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
604#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
605#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
606#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
607#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
608#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
609#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
610#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
611#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
612#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
613#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
614#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
615#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
616#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
617#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
618#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
619#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
620#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
621#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
622#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
623#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
624#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
625#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
626#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
627#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
628#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
629#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
630#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
631#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
632#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
633#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
634#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
635#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
636#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
637#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
638#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
639#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
640#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
641#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
642#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
643#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
644#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
645#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
646#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
647#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
648#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
649#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
650#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
651#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
652#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
653#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
654#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
655#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
656#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
657#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
658#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
659#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
660#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
661#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
662#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
663#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
664#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
665#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK 0x80000000
666#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
667#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
668#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
669#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
670#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
671#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK 0x80000000
672#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
673#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
674#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
675#define BIF_SMU_INDEX__BIF_SMU_INDEX_MASK 0x7fffc
676#define BIF_SMU_INDEX__BIF_SMU_INDEX__SHIFT 0x2
677#define BIF_SMU_DATA__BIF_SMU_DATA_MASK 0x7fffc
678#define BIF_SMU_DATA__BIF_SMU_DATA__SHIFT 0x2
679#define IMPCTL_RESET__IMP_SW_RESET_MASK 0x1
680#define IMPCTL_RESET__IMP_SW_RESET__SHIFT 0x0
681#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK 0x1
682#define GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT 0x0
683#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK 0x2
684#define GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT 0x1
685#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK 0x4
686#define GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT 0x2
687#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK 0x8
688#define GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT 0x3
689#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK 0x10
690#define GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT 0x4
691#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK 0x20
692#define GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT 0x5
693#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK 0x40
694#define GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT 0x6
695#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK 0x80
696#define GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT 0x7
697#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK 0x100
698#define GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT 0x8
699#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK 0x200
700#define GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT 0x9
701#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK 0x400
702#define GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT 0xa
703#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK 0x800
704#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT 0xb
705#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK 0x1000
706#define GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT 0xc
707#define GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK 0x2000
708#define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
709#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK 0x4000
710#define GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT 0xe
711#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK 0x8000
712#define GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT 0xf
713#define GARLIC_FLUSH_CNTL__DISPLAY_MASK 0x10000
714#define GARLIC_FLUSH_CNTL__DISPLAY__SHIFT 0x10
715#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK 0x20000
716#define GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT 0x11
717#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK 0x40000
718#define GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT 0x12
719#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK 0x40000000
720#define GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT 0x1e
721#define GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK 0x80000000
722#define GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT 0x1f
723#define GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK 0x1
724#define GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT 0x0
725#define GARLIC_FLUSH_ADDR_START_0__MODE_MASK 0x2
726#define GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT 0x1
727#define GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK 0xfffffffc
728#define GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT 0x2
729#define GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK 0x1
730#define GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT 0x0
731#define GARLIC_FLUSH_ADDR_START_1__MODE_MASK 0x2
732#define GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT 0x1
733#define GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK 0xfffffffc
734#define GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT 0x2
735#define GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK 0x1
736#define GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT 0x0
737#define GARLIC_FLUSH_ADDR_START_2__MODE_MASK 0x2
738#define GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT 0x1
739#define GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK 0xfffffffc
740#define GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT 0x2
741#define GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK 0x1
742#define GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT 0x0
743#define GARLIC_FLUSH_ADDR_START_3__MODE_MASK 0x2
744#define GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT 0x1
745#define GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK 0xfffffffc
746#define GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT 0x2
747#define GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK 0x1
748#define GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT 0x0
749#define GARLIC_FLUSH_ADDR_START_4__MODE_MASK 0x2
750#define GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT 0x1
751#define GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK 0xfffffffc
752#define GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT 0x2
753#define GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK 0x1
754#define GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT 0x0
755#define GARLIC_FLUSH_ADDR_START_5__MODE_MASK 0x2
756#define GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT 0x1
757#define GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK 0xfffffffc
758#define GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT 0x2
759#define GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK 0x1
760#define GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT 0x0
761#define GARLIC_FLUSH_ADDR_START_6__MODE_MASK 0x2
762#define GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT 0x1
763#define GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK 0xfffffffc
764#define GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT 0x2
765#define GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK 0x1
766#define GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT 0x0
767#define GARLIC_FLUSH_ADDR_START_7__MODE_MASK 0x2
768#define GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT 0x1
769#define GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK 0xfffffffc
770#define GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT 0x2
771#define GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK 0xfffffffc
772#define GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT 0x2
773#define GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK 0xfffffffc
774#define GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT 0x2
775#define GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK 0xfffffffc
776#define GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT 0x2
777#define GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK 0xfffffffc
778#define GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT 0x2
779#define GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK 0xfffffffc
780#define GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT 0x2
781#define GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK 0xfffffffc
782#define GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT 0x2
783#define GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK 0xfffffffc
784#define GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT 0x2
785#define GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK 0xfffffffc
786#define GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT 0x2
787#define GARLIC_FLUSH_REQ__FLUSH_REQ_MASK 0x1
788#define GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT 0x0
789#define GPU_GARLIC_FLUSH_REQ__CP0_MASK 0x1
790#define GPU_GARLIC_FLUSH_REQ__CP0__SHIFT 0x0
791#define GPU_GARLIC_FLUSH_REQ__CP1_MASK 0x2
792#define GPU_GARLIC_FLUSH_REQ__CP1__SHIFT 0x1
793#define GPU_GARLIC_FLUSH_REQ__CP2_MASK 0x4
794#define GPU_GARLIC_FLUSH_REQ__CP2__SHIFT 0x2
795#define GPU_GARLIC_FLUSH_REQ__CP3_MASK 0x8
796#define GPU_GARLIC_FLUSH_REQ__CP3__SHIFT 0x3
797#define GPU_GARLIC_FLUSH_REQ__CP4_MASK 0x10
798#define GPU_GARLIC_FLUSH_REQ__CP4__SHIFT 0x4
799#define GPU_GARLIC_FLUSH_REQ__CP5_MASK 0x20
800#define GPU_GARLIC_FLUSH_REQ__CP5__SHIFT 0x5
801#define GPU_GARLIC_FLUSH_REQ__CP6_MASK 0x40
802#define GPU_GARLIC_FLUSH_REQ__CP6__SHIFT 0x6
803#define GPU_GARLIC_FLUSH_REQ__CP7_MASK 0x80
804#define GPU_GARLIC_FLUSH_REQ__CP7__SHIFT 0x7
805#define GPU_GARLIC_FLUSH_REQ__CP8_MASK 0x100
806#define GPU_GARLIC_FLUSH_REQ__CP8__SHIFT 0x8
807#define GPU_GARLIC_FLUSH_REQ__CP9_MASK 0x200
808#define GPU_GARLIC_FLUSH_REQ__CP9__SHIFT 0x9
809#define GPU_GARLIC_FLUSH_REQ__SDMA0_MASK 0x400
810#define GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT 0xa
811#define GPU_GARLIC_FLUSH_REQ__SDMA1_MASK 0x800
812#define GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT 0xb
813#define GPU_GARLIC_FLUSH_REQ__SDMA2_MASK 0x1000
814#define GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT 0xc
815#define GPU_GARLIC_FLUSH_REQ__SDMA3_MASK 0x2000
816#define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
817#define GPU_GARLIC_FLUSH_DONE__CP0_MASK 0x1
818#define GPU_GARLIC_FLUSH_DONE__CP0__SHIFT 0x0
819#define GPU_GARLIC_FLUSH_DONE__CP1_MASK 0x2
820#define GPU_GARLIC_FLUSH_DONE__CP1__SHIFT 0x1
821#define GPU_GARLIC_FLUSH_DONE__CP2_MASK 0x4
822#define GPU_GARLIC_FLUSH_DONE__CP2__SHIFT 0x2
823#define GPU_GARLIC_FLUSH_DONE__CP3_MASK 0x8
824#define GPU_GARLIC_FLUSH_DONE__CP3__SHIFT 0x3
825#define GPU_GARLIC_FLUSH_DONE__CP4_MASK 0x10
826#define GPU_GARLIC_FLUSH_DONE__CP4__SHIFT 0x4
827#define GPU_GARLIC_FLUSH_DONE__CP5_MASK 0x20
828#define GPU_GARLIC_FLUSH_DONE__CP5__SHIFT 0x5
829#define GPU_GARLIC_FLUSH_DONE__CP6_MASK 0x40
830#define GPU_GARLIC_FLUSH_DONE__CP6__SHIFT 0x6
831#define GPU_GARLIC_FLUSH_DONE__CP7_MASK 0x80
832#define GPU_GARLIC_FLUSH_DONE__CP7__SHIFT 0x7
833#define GPU_GARLIC_FLUSH_DONE__CP8_MASK 0x100
834#define GPU_GARLIC_FLUSH_DONE__CP8__SHIFT 0x8
835#define GPU_GARLIC_FLUSH_DONE__CP9_MASK 0x200
836#define GPU_GARLIC_FLUSH_DONE__CP9__SHIFT 0x9
837#define GPU_GARLIC_FLUSH_DONE__SDMA0_MASK 0x400
838#define GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT 0xa
839#define GPU_GARLIC_FLUSH_DONE__SDMA1_MASK 0x800
840#define GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT 0xb
841#define GPU_GARLIC_FLUSH_DONE__SDMA2_MASK 0x1000
842#define GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT 0xc
843#define GPU_GARLIC_FLUSH_DONE__SDMA3_MASK 0x2000
844#define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
845#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK 0x7fffc
846#define GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT 0x2
847#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK 0x7fffc
848#define GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT 0x2
849#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK 0x7fffc
850#define GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT 0x2
851#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK 0x7fffc
852#define GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT 0x2
853#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
854#define GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
855#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
856#define GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
857#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK 0x7fffc
858#define GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT 0x2
859#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK 0x7fffc
860#define GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT 0x2
861#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK 0x7fffc
862#define GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT 0x2
863#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK 0x7fffc
864#define GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT 0x2
865#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK 0x7fffc
866#define GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT 0x2
867#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK 0x7fffc
868#define GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT 0x2
869#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK 0x7fffc
870#define GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT 0x2
871#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
872#define GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
873#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK 0x7fffc
874#define GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT 0x2
875#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK 0x7fffc
876#define GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT 0x2
877#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK 0x7fffc
878#define GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT 0x2
879#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
880#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
881#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x7fffc
882#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
883#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xffffffff
884#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
885#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xffffffff
886#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
887#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xffffffff
888#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
889#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xffffffff
890#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
891#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xffffffff
892#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
893#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xffffffff
894#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
895#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xffffffff
896#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
897#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xffffffff
898#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
899#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xffffffff
900#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
901#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xffffffff
902#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
903#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xffffffff
904#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
905#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xffffffff
906#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
907#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xffffffff
908#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
909#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xffffffff
910#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
911#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xffffffff
912#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
913#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xffffffff
914#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
915#define BIF_RB_CNTL__RB_ENABLE_MASK 0x1
916#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
917#define BIF_RB_CNTL__RB_SIZE_MASK 0x3e
918#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
919#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
920#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
921#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
922#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
923#define BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x20000
924#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
925#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
926#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
927#define BIF_RB_BASE__ADDR_MASK 0xffffffff
928#define BIF_RB_BASE__ADDR__SHIFT 0x0
929#define BIF_RB_RPTR__OFFSET_MASK 0x3fffc
930#define BIF_RB_RPTR__OFFSET__SHIFT 0x2
931#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x1
932#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
933#define BIF_RB_WPTR__OFFSET_MASK 0x3fffc
934#define BIF_RB_WPTR__OFFSET__SHIFT 0x2
935#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
936#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
937#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
938#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
939#define VENDOR_ID__VENDOR_ID_MASK 0xffff
940#define VENDOR_ID__VENDOR_ID__SHIFT 0x0
941#define DEVICE_ID__DEVICE_ID_MASK 0xffff
942#define DEVICE_ID__DEVICE_ID__SHIFT 0x0
943#define COMMAND__IO_ACCESS_EN_MASK 0x1
944#define COMMAND__IO_ACCESS_EN__SHIFT 0x0
945#define COMMAND__MEM_ACCESS_EN_MASK 0x2
946#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1
947#define COMMAND__BUS_MASTER_EN_MASK 0x4
948#define COMMAND__BUS_MASTER_EN__SHIFT 0x2
949#define COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
950#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
951#define COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
952#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
953#define COMMAND__PAL_SNOOP_EN_MASK 0x20
954#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5
955#define COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
956#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
957#define COMMAND__AD_STEPPING_MASK 0x80
958#define COMMAND__AD_STEPPING__SHIFT 0x7
959#define COMMAND__SERR_EN_MASK 0x100
960#define COMMAND__SERR_EN__SHIFT 0x8
961#define COMMAND__FAST_B2B_EN_MASK 0x200
962#define COMMAND__FAST_B2B_EN__SHIFT 0x9
963#define COMMAND__INT_DIS_MASK 0x400
964#define COMMAND__INT_DIS__SHIFT 0xa
965#define STATUS__INT_STATUS_MASK 0x8
966#define STATUS__INT_STATUS__SHIFT 0x3
967#define STATUS__CAP_LIST_MASK 0x10
968#define STATUS__CAP_LIST__SHIFT 0x4
969#define STATUS__PCI_66_EN_MASK 0x20
970#define STATUS__PCI_66_EN__SHIFT 0x5
971#define STATUS__FAST_BACK_CAPABLE_MASK 0x80
972#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
973#define STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x100
974#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
975#define STATUS__DEVSEL_TIMING_MASK 0x600
976#define STATUS__DEVSEL_TIMING__SHIFT 0x9
977#define STATUS__SIGNAL_TARGET_ABORT_MASK 0x800
978#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
979#define STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000
980#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
981#define STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000
982#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
983#define STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000
984#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
985#define STATUS__PARITY_ERROR_DETECTED_MASK 0x8000
986#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
987#define REVISION_ID__MINOR_REV_ID_MASK 0xf
988#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0
989#define REVISION_ID__MAJOR_REV_ID_MASK 0xf0
990#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
991#define PROG_INTERFACE__PROG_INTERFACE_MASK 0xff
992#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
993#define SUB_CLASS__SUB_CLASS_MASK 0xff
994#define SUB_CLASS__SUB_CLASS__SHIFT 0x0
995#define BASE_CLASS__BASE_CLASS_MASK 0xff
996#define BASE_CLASS__BASE_CLASS__SHIFT 0x0
997#define CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
998#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
999#define LATENCY__LATENCY_TIMER_MASK 0xff
1000#define LATENCY__LATENCY_TIMER__SHIFT 0x0
1001#define HEADER__HEADER_TYPE_MASK 0x7f
1002#define HEADER__HEADER_TYPE__SHIFT 0x0
1003#define HEADER__DEVICE_TYPE_MASK 0x80
1004#define HEADER__DEVICE_TYPE__SHIFT 0x7
1005#define BIST__BIST_COMP_MASK 0xf
1006#define BIST__BIST_COMP__SHIFT 0x0
1007#define BIST__BIST_STRT_MASK 0x40
1008#define BIST__BIST_STRT__SHIFT 0x6
1009#define BIST__BIST_CAP_MASK 0x80
1010#define BIST__BIST_CAP__SHIFT 0x7
1011#define BASE_ADDR_1__BASE_ADDR_MASK 0xffffffff
1012#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
1013#define BASE_ADDR_2__BASE_ADDR_MASK 0xffffffff
1014#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
1015#define BASE_ADDR_3__BASE_ADDR_MASK 0xffffffff
1016#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
1017#define BASE_ADDR_4__BASE_ADDR_MASK 0xffffffff
1018#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
1019#define BASE_ADDR_5__BASE_ADDR_MASK 0xffffffff
1020#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
1021#define BASE_ADDR_6__BASE_ADDR_MASK 0xffffffff
1022#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
1023#define ROM_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
1024#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
1025#define CAP_PTR__CAP_PTR_MASK 0xff
1026#define CAP_PTR__CAP_PTR__SHIFT 0x0
1027#define INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
1028#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
1029#define INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff
1030#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
1031#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0xffff
1032#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
1033#define ADAPTER_ID__SUBSYSTEM_ID_MASK 0xffff0000
1034#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
1035#define MIN_GRANT__MIN_GNT_MASK 0xff
1036#define MIN_GRANT__MIN_GNT__SHIFT 0x0
1037#define MAX_LATENCY__MAX_LAT_MASK 0xff
1038#define MAX_LATENCY__MAX_LAT__SHIFT 0x0
1039#define VENDOR_CAP_LIST__CAP_ID_MASK 0xff
1040#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
1041#define VENDOR_CAP_LIST__NEXT_PTR_MASK 0xff00
1042#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
1043#define VENDOR_CAP_LIST__LENGTH_MASK 0xff0000
1044#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
1045#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0xffff
1046#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
1047#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xffff0000
1048#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
1049#define PMI_CAP_LIST__CAP_ID_MASK 0xff
1050#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0
1051#define PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
1052#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
1053#define PMI_CAP__VERSION_MASK 0x7
1054#define PMI_CAP__VERSION__SHIFT 0x0
1055#define PMI_CAP__PME_CLOCK_MASK 0x8
1056#define PMI_CAP__PME_CLOCK__SHIFT 0x3
1057#define PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x20
1058#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
1059#define PMI_CAP__AUX_CURRENT_MASK 0x1c0
1060#define PMI_CAP__AUX_CURRENT__SHIFT 0x6
1061#define PMI_CAP__D1_SUPPORT_MASK 0x200
1062#define PMI_CAP__D1_SUPPORT__SHIFT 0x9
1063#define PMI_CAP__D2_SUPPORT_MASK 0x400
1064#define PMI_CAP__D2_SUPPORT__SHIFT 0xa
1065#define PMI_CAP__PME_SUPPORT_MASK 0xf800
1066#define PMI_CAP__PME_SUPPORT__SHIFT 0xb
1067#define PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
1068#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
1069#define PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
1070#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
1071#define PMI_STATUS_CNTL__PME_EN_MASK 0x100
1072#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
1073#define PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
1074#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
1075#define PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
1076#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
1077#define PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
1078#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
1079#define PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
1080#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
1081#define PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
1082#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
1083#define PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
1084#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
1085#define PCIE_CAP_LIST__CAP_ID_MASK 0xff
1086#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
1087#define PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
1088#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
1089#define PCIE_CAP__VERSION_MASK 0xf
1090#define PCIE_CAP__VERSION__SHIFT 0x0
1091#define PCIE_CAP__DEVICE_TYPE_MASK 0xf0
1092#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
1093#define PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x100
1094#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
1095#define PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e00
1096#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
1097#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
1098#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
1099#define DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
1100#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
1101#define DEVICE_CAP__EXTENDED_TAG_MASK 0x20
1102#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
1103#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
1104#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
1105#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
1106#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
1107#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
1108#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
1109#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
1110#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
1111#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
1112#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
1113#define DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
1114#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
1115#define DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
1116#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
1117#define DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
1118#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
1119#define DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
1120#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
1121#define DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
1122#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
1123#define DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
1124#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
1125#define DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
1126#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
1127#define DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
1128#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
1129#define DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
1130#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
1131#define DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
1132#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
1133#define DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
1134#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
1135#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
1136#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
1137#define DEVICE_CNTL__INITIATE_FLR_MASK 0x8000
1138#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
1139#define DEVICE_STATUS__CORR_ERR_MASK 0x1
1140#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0
1141#define DEVICE_STATUS__NON_FATAL_ERR_MASK 0x2
1142#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
1143#define DEVICE_STATUS__FATAL_ERR_MASK 0x4
1144#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
1145#define DEVICE_STATUS__USR_DETECTED_MASK 0x8
1146#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
1147#define DEVICE_STATUS__AUX_PWR_MASK 0x10
1148#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4
1149#define DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x20
1150#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
1151#define LINK_CAP__LINK_SPEED_MASK 0xf
1152#define LINK_CAP__LINK_SPEED__SHIFT 0x0
1153#define LINK_CAP__LINK_WIDTH_MASK 0x3f0
1154#define LINK_CAP__LINK_WIDTH__SHIFT 0x4
1155#define LINK_CAP__PM_SUPPORT_MASK 0xc00
1156#define LINK_CAP__PM_SUPPORT__SHIFT 0xa
1157#define LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
1158#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
1159#define LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
1160#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
1161#define LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
1162#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
1163#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
1164#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
1165#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
1166#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
1167#define LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
1168#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
1169#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
1170#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
1171#define LINK_CAP__PORT_NUMBER_MASK 0xff000000
1172#define LINK_CAP__PORT_NUMBER__SHIFT 0x18
1173#define LINK_CNTL__PM_CONTROL_MASK 0x3
1174#define LINK_CNTL__PM_CONTROL__SHIFT 0x0
1175#define LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
1176#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
1177#define LINK_CNTL__LINK_DIS_MASK 0x10
1178#define LINK_CNTL__LINK_DIS__SHIFT 0x4
1179#define LINK_CNTL__RETRAIN_LINK_MASK 0x20
1180#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
1181#define LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
1182#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
1183#define LINK_CNTL__EXTENDED_SYNC_MASK 0x80
1184#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
1185#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
1186#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
1187#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
1188#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
1189#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
1190#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
1191#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
1192#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
1193#define LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf
1194#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
1195#define LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f0
1196#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
1197#define LINK_STATUS__LINK_TRAINING_MASK 0x800
1198#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb
1199#define LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000
1200#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
1201#define LINK_STATUS__DL_ACTIVE_MASK 0x2000
1202#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd
1203#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000
1204#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
1205#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000
1206#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
1207#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
1208#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
1209#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
1210#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
1211#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
1212#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
1213#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
1214#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
1215#define DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
1216#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
1217#define DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
1218#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
1219#define DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
1220#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
1221#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
1222#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
1223#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
1224#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
1225#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
1226#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
1227#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
1228#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
1229#define DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
1230#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
1231#define DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
1232#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
1233#define DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
1234#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
1235#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
1236#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
1237#define DEVICE_CNTL2__LTR_EN_MASK 0x400
1238#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa
1239#define DEVICE_CNTL2__OBFF_EN_MASK 0x6000
1240#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
1241#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
1242#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
1243#define DEVICE_STATUS2__RESERVED_MASK 0xffff
1244#define DEVICE_STATUS2__RESERVED__SHIFT 0x0
1245#define LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
1246#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
1247#define LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
1248#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
1249#define LINK_CAP2__RESERVED_MASK 0xfffffe00
1250#define LINK_CAP2__RESERVED__SHIFT 0x9
1251#define LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
1252#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
1253#define LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
1254#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
1255#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
1256#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
1257#define LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
1258#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
1259#define LINK_CNTL2__XMIT_MARGIN_MASK 0x380
1260#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
1261#define LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
1262#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
1263#define LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
1264#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
1265#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
1266#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
1267#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x1
1268#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
1269#define LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x2
1270#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1
1271#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x4
1272#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2
1273#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x8
1274#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3
1275#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x10
1276#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4
1277#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x20
1278#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5
1279#define MSI_CAP_LIST__CAP_ID_MASK 0xff
1280#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0
1281#define MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
1282#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
1283#define MSI_MSG_CNTL__MSI_EN_MASK 0x1
1284#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
1285#define MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe
1286#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
1287#define MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x70
1288#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
1289#define MSI_MSG_CNTL__MSI_64BIT_MASK 0x80
1290#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
1291#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
1292#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
1293#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
1294#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
1295#define MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
1296#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
1297#define MSI_MSG_DATA__MSI_DATA_MASK 0xffff
1298#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
1299#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1300#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1301#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1302#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1303#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1304#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1305#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
1306#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
1307#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
1308#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
1309#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
1310#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
1311#define PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
1312#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
1313#define PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
1314#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
1315#define PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1316#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1317#define PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1318#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1319#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1320#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1321#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
1322#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
1323#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
1324#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
1325#define PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
1326#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
1327#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
1328#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
1329#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
1330#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
1331#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
1332#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
1333#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
1334#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
1335#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
1336#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
1337#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x1
1338#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
1339#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
1340#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
1341#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
1342#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
1343#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
1344#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
1345#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
1346#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
1347#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
1348#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
1349#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
1350#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
1351#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
1352#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
1353#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
1354#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
1355#define PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
1356#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
1357#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
1358#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
1359#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
1360#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
1361#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1362#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
1363#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
1364#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
1365#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
1366#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
1367#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
1368#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
1369#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
1370#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
1371#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
1372#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
1373#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
1374#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
1375#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
1376#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
1377#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
1378#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
1379#define PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
1380#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
1381#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
1382#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
1383#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x1
1384#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
1385#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x2
1386#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
1387#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1388#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1389#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1390#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1391#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1392#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1393#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
1394#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
1395#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
1396#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
1397#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1398#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1399#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1400#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1401#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1402#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1403#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
1404#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
1405#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
1406#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
1407#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
1408#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
1409#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
1410#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
1411#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
1412#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
1413#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
1414#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
1415#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
1416#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
1417#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
1418#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
1419#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
1420#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
1421#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
1422#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
1423#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
1424#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
1425#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
1426#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
1427#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
1428#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
1429#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
1430#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
1431#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
1432#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
1433#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
1434#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
1435#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
1436#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
1437#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
1438#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
1439#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
1440#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
1441#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
1442#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
1443#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
1444#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
1445#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
1446#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
1447#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
1448#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
1449#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
1450#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
1451#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
1452#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
1453#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
1454#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
1455#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
1456#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
1457#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
1458#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
1459#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
1460#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
1461#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
1462#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
1463#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
1464#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
1465#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
1466#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
1467#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
1468#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
1469#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
1470#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
1471#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
1472#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
1473#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
1474#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
1475#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
1476#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
1477#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
1478#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
1479#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
1480#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
1481#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
1482#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
1483#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
1484#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
1485#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
1486#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
1487#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
1488#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
1489#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
1490#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
1491#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
1492#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
1493#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
1494#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
1495#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
1496#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
1497#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
1498#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
1499#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
1500#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
1501#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
1502#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
1503#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
1504#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
1505#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
1506#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
1507#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
1508#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
1509#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
1510#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
1511#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
1512#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
1513#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
1514#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
1515#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
1516#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
1517#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
1518#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
1519#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
1520#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
1521#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
1522#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
1523#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
1524#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
1525#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
1526#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
1527#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
1528#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
1529#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
1530#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
1531#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
1532#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
1533#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
1534#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
1535#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
1536#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
1537#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
1538#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
1539#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
1540#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
1541#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
1542#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
1543#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
1544#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
1545#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
1546#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
1547#define PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
1548#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
1549#define PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
1550#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
1551#define PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
1552#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
1553#define PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
1554#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
1555#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
1556#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
1557#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
1558#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
1559#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
1560#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
1561#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
1562#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
1563#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1564#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1565#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1566#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1567#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1568#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1569#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1570#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1571#define PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x7
1572#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
1573#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1574#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1575#define PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1f00
1576#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
1577#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1578#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1579#define PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x7
1580#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
1581#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1582#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1583#define PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1f00
1584#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
1585#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1586#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1587#define PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x7
1588#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
1589#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1590#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1591#define PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1f00
1592#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
1593#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1594#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1595#define PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x7
1596#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
1597#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1598#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1599#define PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1f00
1600#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
1601#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1602#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1603#define PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x7
1604#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
1605#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1606#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1607#define PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1f00
1608#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
1609#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xfffff0
1610#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
1611#define PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x7
1612#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
1613#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0xe0
1614#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
1615#define PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1f00
1616#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
1617#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1618#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1619#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1620#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1621#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1622#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1623#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xff
1624#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
1625#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0xff
1626#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
1627#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x300
1628#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
1629#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x1c00
1630#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
1631#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x6000
1632#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
1633#define PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x38000
1634#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
1635#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x1c0000
1636#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
1637#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x1
1638#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
1639#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1640#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1641#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1642#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1643#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1644#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1645#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x1f
1646#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
1647#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
1648#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
1649#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
1650#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
1651#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
1652#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
1653#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
1654#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
1655#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
1656#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
1657#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x1f
1658#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
1659#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x100
1660#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
1661#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1f
1662#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
1663#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
1664#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1665#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
1666#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1667#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
1668#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1669#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
1670#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1671#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
1672#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1673#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
1674#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1675#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
1676#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1677#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
1678#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
1679#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1680#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1681#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1682#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1683#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1684#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1685#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
1686#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
1687#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
1688#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
1689#define PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
1690#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
1691#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
1692#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
1693#define PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
1694#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
1695#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1696#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1697#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1698#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1699#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1700#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1701#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1702#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1703#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1704#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1705#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1706#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1707#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1708#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1709#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1710#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1711#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1712#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1713#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1714#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1715#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1716#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1717#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1718#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1719#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1720#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1721#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1722#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1723#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1724#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1725#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1726#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1727#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1728#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1729#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1730#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1731#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1732#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1733#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1734#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1735#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1736#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1737#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1738#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1739#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1740#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1741#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1742#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1743#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1744#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1745#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1746#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1747#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1748#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1749#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1750#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1751#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1752#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1753#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1754#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1755#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1756#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1757#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1758#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1759#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1760#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1761#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1762#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1763#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1764#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1765#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1766#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1767#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1768#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1769#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1770#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1771#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1772#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1773#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1774#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1775#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1776#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1777#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1778#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1779#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1780#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1781#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1782#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1783#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1784#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1785#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1786#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1787#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1788#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1789#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1790#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1791#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1792#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1793#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1794#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1795#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1796#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1797#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1798#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1799#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1800#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1801#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1802#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1803#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1804#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1805#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1806#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1807#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1808#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1809#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1810#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1811#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1812#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1813#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1814#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1815#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1816#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1817#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1818#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1819#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1820#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1821#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1822#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1823#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1824#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1825#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1826#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1827#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1828#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1829#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1830#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1831#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1832#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1833#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1834#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1835#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1836#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1837#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1838#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1839#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1840#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1841#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1842#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1843#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1844#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1845#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
1846#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
1847#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
1848#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
1849#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
1850#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
1851#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
1852#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
1853#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
1854#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
1855#define PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1856#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1857#define PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1858#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1859#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1860#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1861#define PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
1862#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
1863#define PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
1864#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
1865#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
1866#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
1867#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
1868#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
1869#define PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
1870#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
1871#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
1872#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
1873#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
1874#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
1875#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
1876#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
1877#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x1
1878#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
1879#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x2
1880#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
1881#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x4
1882#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
1883#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x8
1884#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
1885#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x10
1886#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
1887#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x20
1888#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
1889#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x40
1890#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
1891#define PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1892#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1893#define PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1894#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1895#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1896#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1897#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x1f
1898#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
1899#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x20
1900#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
1901#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x40
1902#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
1903#define PCIE_ATS_CNTL__STU_MASK 0x1f
1904#define PCIE_ATS_CNTL__STU__SHIFT 0x0
1905#define PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000
1906#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
1907#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1908#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1909#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1910#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1911#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1912#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1913#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x1
1914#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
1915#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x2
1916#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
1917#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x1
1918#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
1919#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x2
1920#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
1921#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x100
1922#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
1923#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000
1924#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
1925#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xffffffff
1926#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
1927#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xffffffff
1928#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
1929#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1930#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1931#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1932#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1933#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1934#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1935#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2
1936#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
1937#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x4
1938#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
1939#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1f00
1940#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
1941#define PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x1
1942#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
1943#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x2
1944#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
1945#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x4
1946#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
1947#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1948#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1949#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1950#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1951#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1952#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1953#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x1
1954#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
1955#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x2
1956#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
1957#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x4
1958#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
1959#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x100
1960#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
1961#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x600
1962#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
1963#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x7ff0000
1964#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
1965#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x7
1966#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
1967#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x300
1968#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
1969#define PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
1970#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
1971#define PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
1972#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
1973#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
1974#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
1975#define PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
1976#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
1977#define PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3f00
1978#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
1979#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
1980#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
1981#define PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f
1982#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
1983#define PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000
1984#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
1985#define PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
1986#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
1987#define PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
1988#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
1989#define PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
1990#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
1991#define PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
1992#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
1993#define PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
1994#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
1995#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
1996#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
1997#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
1998#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
1999#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
2000#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
2001#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
2002#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
2003#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0xffff
2004#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
2005#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
2006#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
2007#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
2008#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
2009#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x3ff
2010#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
2011#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x1c00
2012#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
2013#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x3ff0000
2014#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
2015#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1c000000
2016#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
2017#define MM_INDEX_IND__MM_OFFSET_MASK 0x7fffffff
2018#define MM_INDEX_IND__MM_OFFSET__SHIFT 0x0
2019#define MM_INDEX_IND__MM_APER_MASK 0x80000000
2020#define MM_INDEX_IND__MM_APER__SHIFT 0x1f
2021#define MM_INDEX_HI_IND__MM_OFFSET_HI_MASK 0xffffffff
2022#define MM_INDEX_HI_IND__MM_OFFSET_HI__SHIFT 0x0
2023#define MM_DATA_IND__MM_DATA_MASK 0xffffffff
2024#define MM_DATA_IND__MM_DATA__SHIFT 0x0
2025#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS_MASK 0x2
2026#define BIF_MM_INDACCESS_CNTL_IND__MM_INDACCESS_DIS__SHIFT 0x1
2027#define BUS_CNTL_IND__BIOS_ROM_WRT_EN_MASK 0x1
2028#define BUS_CNTL_IND__BIOS_ROM_WRT_EN__SHIFT 0x0
2029#define BUS_CNTL_IND__BIOS_ROM_DIS_MASK 0x2
2030#define BUS_CNTL_IND__BIOS_ROM_DIS__SHIFT 0x1
2031#define BUS_CNTL_IND__PMI_IO_DIS_MASK 0x4
2032#define BUS_CNTL_IND__PMI_IO_DIS__SHIFT 0x2
2033#define BUS_CNTL_IND__PMI_MEM_DIS_MASK 0x8
2034#define BUS_CNTL_IND__PMI_MEM_DIS__SHIFT 0x3
2035#define BUS_CNTL_IND__PMI_BM_DIS_MASK 0x10
2036#define BUS_CNTL_IND__PMI_BM_DIS__SHIFT 0x4
2037#define BUS_CNTL_IND__PMI_INT_DIS_MASK 0x20
2038#define BUS_CNTL_IND__PMI_INT_DIS__SHIFT 0x5
2039#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS_MASK 0x40
2040#define BUS_CNTL_IND__VGA_REG_COHERENCY_DIS__SHIFT 0x6
2041#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS_MASK 0x80
2042#define BUS_CNTL_IND__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
2043#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
2044#define BUS_CNTL_IND__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
2045#define BUS_CNTL_IND__SET_AZ_TC_MASK 0x1c00
2046#define BUS_CNTL_IND__SET_AZ_TC__SHIFT 0xa
2047#define BUS_CNTL_IND__SET_MC_TC_MASK 0xe000
2048#define BUS_CNTL_IND__SET_MC_TC__SHIFT 0xd
2049#define BUS_CNTL_IND__ZERO_BE_WR_EN_MASK 0x10000
2050#define BUS_CNTL_IND__ZERO_BE_WR_EN__SHIFT 0x10
2051#define BUS_CNTL_IND__ZERO_BE_RD_EN_MASK 0x20000
2052#define BUS_CNTL_IND__ZERO_BE_RD_EN__SHIFT 0x11
2053#define BUS_CNTL_IND__RD_STALL_IO_WR_MASK 0x40000
2054#define BUS_CNTL_IND__RD_STALL_IO_WR__SHIFT 0x12
2055#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN_MASK 0x1
2056#define CONFIG_CNTL_IND__CFG_VGA_RAM_EN__SHIFT 0x0
2057#define CONFIG_CNTL_IND__VGA_DIS_MASK 0x2
2058#define CONFIG_CNTL_IND__VGA_DIS__SHIFT 0x1
2059#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B_MASK 0x4
2060#define CONFIG_CNTL_IND__GENMO_MONO_ADDRESS_B__SHIFT 0x2
2061#define CONFIG_CNTL_IND__GRPH_ADRSEL_MASK 0x18
2062#define CONFIG_CNTL_IND__GRPH_ADRSEL__SHIFT 0x3
2063#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE_MASK 0xffffffff
2064#define CONFIG_MEMSIZE_IND__CONFIG_MEMSIZE__SHIFT 0x0
2065#define CONFIG_F0_BASE_IND__F0_BASE_MASK 0xffffffff
2066#define CONFIG_F0_BASE_IND__F0_BASE__SHIFT 0x0
2067#define CONFIG_APER_SIZE_IND__APER_SIZE_MASK 0xffffffff
2068#define CONFIG_APER_SIZE_IND__APER_SIZE__SHIFT 0x0
2069#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE_MASK 0xfffff
2070#define CONFIG_REG_APER_SIZE_IND__REG_APER_SIZE__SHIFT 0x0
2071#define BIF_SCRATCH0_IND__BIF_SCRATCH0_MASK 0xffffffff
2072#define BIF_SCRATCH0_IND__BIF_SCRATCH0__SHIFT 0x0
2073#define BIF_SCRATCH1_IND__BIF_SCRATCH1_MASK 0xffffffff
2074#define BIF_SCRATCH1_IND__BIF_SCRATCH1__SHIFT 0x0
2075#define BX_RESET_EN_IND__COR_RESET_EN_MASK 0x1
2076#define BX_RESET_EN_IND__COR_RESET_EN__SHIFT 0x0
2077#define BX_RESET_EN_IND__REG_RESET_EN_MASK 0x2
2078#define BX_RESET_EN_IND__REG_RESET_EN__SHIFT 0x1
2079#define BX_RESET_EN_IND__STY_RESET_EN_MASK 0x4
2080#define BX_RESET_EN_IND__STY_RESET_EN__SHIFT 0x2
2081#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL_MASK 0x7
2082#define MM_CFGREGS_CNTL_IND__MM_CFG_FUNC_SEL__SHIFT 0x0
2083#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN_MASK 0x8
2084#define MM_CFGREGS_CNTL_IND__MM_WR_TO_CFG_EN__SHIFT 0x3
2085#define HW_DEBUG_IND__HW_00_DEBUG_MASK 0x1
2086#define HW_DEBUG_IND__HW_00_DEBUG__SHIFT 0x0
2087#define HW_DEBUG_IND__HW_01_DEBUG_MASK 0x2
2088#define HW_DEBUG_IND__HW_01_DEBUG__SHIFT 0x1
2089#define HW_DEBUG_IND__HW_02_DEBUG_MASK 0x4
2090#define HW_DEBUG_IND__HW_02_DEBUG__SHIFT 0x2
2091#define HW_DEBUG_IND__HW_03_DEBUG_MASK 0x8
2092#define HW_DEBUG_IND__HW_03_DEBUG__SHIFT 0x3
2093#define HW_DEBUG_IND__HW_04_DEBUG_MASK 0x10
2094#define HW_DEBUG_IND__HW_04_DEBUG__SHIFT 0x4
2095#define HW_DEBUG_IND__HW_05_DEBUG_MASK 0x20
2096#define HW_DEBUG_IND__HW_05_DEBUG__SHIFT 0x5
2097#define HW_DEBUG_IND__HW_06_DEBUG_MASK 0x40
2098#define HW_DEBUG_IND__HW_06_DEBUG__SHIFT 0x6
2099#define HW_DEBUG_IND__HW_07_DEBUG_MASK 0x80
2100#define HW_DEBUG_IND__HW_07_DEBUG__SHIFT 0x7
2101#define HW_DEBUG_IND__HW_08_DEBUG_MASK 0x100
2102#define HW_DEBUG_IND__HW_08_DEBUG__SHIFT 0x8
2103#define HW_DEBUG_IND__HW_09_DEBUG_MASK 0x200
2104#define HW_DEBUG_IND__HW_09_DEBUG__SHIFT 0x9
2105#define HW_DEBUG_IND__HW_10_DEBUG_MASK 0x400
2106#define HW_DEBUG_IND__HW_10_DEBUG__SHIFT 0xa
2107#define HW_DEBUG_IND__HW_11_DEBUG_MASK 0x800
2108#define HW_DEBUG_IND__HW_11_DEBUG__SHIFT 0xb
2109#define HW_DEBUG_IND__HW_12_DEBUG_MASK 0x1000
2110#define HW_DEBUG_IND__HW_12_DEBUG__SHIFT 0xc
2111#define HW_DEBUG_IND__HW_13_DEBUG_MASK 0x2000
2112#define HW_DEBUG_IND__HW_13_DEBUG__SHIFT 0xd
2113#define HW_DEBUG_IND__HW_14_DEBUG_MASK 0x4000
2114#define HW_DEBUG_IND__HW_14_DEBUG__SHIFT 0xe
2115#define HW_DEBUG_IND__HW_15_DEBUG_MASK 0x8000
2116#define HW_DEBUG_IND__HW_15_DEBUG__SHIFT 0xf
2117#define HW_DEBUG_IND__HW_16_DEBUG_MASK 0x10000
2118#define HW_DEBUG_IND__HW_16_DEBUG__SHIFT 0x10
2119#define HW_DEBUG_IND__HW_17_DEBUG_MASK 0x20000
2120#define HW_DEBUG_IND__HW_17_DEBUG__SHIFT 0x11
2121#define HW_DEBUG_IND__HW_18_DEBUG_MASK 0x40000
2122#define HW_DEBUG_IND__HW_18_DEBUG__SHIFT 0x12
2123#define HW_DEBUG_IND__HW_19_DEBUG_MASK 0x80000
2124#define HW_DEBUG_IND__HW_19_DEBUG__SHIFT 0x13
2125#define HW_DEBUG_IND__HW_20_DEBUG_MASK 0x100000
2126#define HW_DEBUG_IND__HW_20_DEBUG__SHIFT 0x14
2127#define HW_DEBUG_IND__HW_21_DEBUG_MASK 0x200000
2128#define HW_DEBUG_IND__HW_21_DEBUG__SHIFT 0x15
2129#define HW_DEBUG_IND__HW_22_DEBUG_MASK 0x400000
2130#define HW_DEBUG_IND__HW_22_DEBUG__SHIFT 0x16
2131#define HW_DEBUG_IND__HW_23_DEBUG_MASK 0x800000
2132#define HW_DEBUG_IND__HW_23_DEBUG__SHIFT 0x17
2133#define HW_DEBUG_IND__HW_24_DEBUG_MASK 0x1000000
2134#define HW_DEBUG_IND__HW_24_DEBUG__SHIFT 0x18
2135#define HW_DEBUG_IND__HW_25_DEBUG_MASK 0x2000000
2136#define HW_DEBUG_IND__HW_25_DEBUG__SHIFT 0x19
2137#define HW_DEBUG_IND__HW_26_DEBUG_MASK 0x4000000
2138#define HW_DEBUG_IND__HW_26_DEBUG__SHIFT 0x1a
2139#define HW_DEBUG_IND__HW_27_DEBUG_MASK 0x8000000
2140#define HW_DEBUG_IND__HW_27_DEBUG__SHIFT 0x1b
2141#define HW_DEBUG_IND__HW_28_DEBUG_MASK 0x10000000
2142#define HW_DEBUG_IND__HW_28_DEBUG__SHIFT 0x1c
2143#define HW_DEBUG_IND__HW_29_DEBUG_MASK 0x20000000
2144#define HW_DEBUG_IND__HW_29_DEBUG__SHIFT 0x1d
2145#define HW_DEBUG_IND__HW_30_DEBUG_MASK 0x40000000
2146#define HW_DEBUG_IND__HW_30_DEBUG__SHIFT 0x1e
2147#define HW_DEBUG_IND__HW_31_DEBUG_MASK 0x80000000
2148#define HW_DEBUG_IND__HW_31_DEBUG__SHIFT 0x1f
2149#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT_MASK 0x7f
2150#define MASTER_CREDIT_CNTL_IND__BIF_MC_RDRET_CREDIT__SHIFT 0x0
2151#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT_MASK 0x3f0000
2152#define MASTER_CREDIT_CNTL_IND__BIF_AZ_RDRET_CREDIT__SHIFT 0x10
2153#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT_MASK 0x1f
2154#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_SRBM_REQ_CREDIT__SHIFT 0x0
2155#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT_MASK 0x1e0
2156#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_VGA_REQ_CREDIT__SHIFT 0x5
2157#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT_MASK 0x7c00
2158#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_HDP_REQ_CREDIT__SHIFT 0xa
2159#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT_MASK 0x8000
2160#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_ROM_REQ_CREDIT__SHIFT 0xf
2161#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT_MASK 0x100000
2162#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_AZ_REQ_CREDIT__SHIFT 0x14
2163#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT_MASK 0x7e000000
2164#define SLAVE_REQ_CREDIT_CNTL_IND__BIF_XDMA_REQ_CREDIT__SHIFT 0x19
2165#define BX_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x1
2166#define BX_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x0
2167#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK 0x1
2168#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
2169#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK 0x2
2170#define INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT 0x1
2171#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK 0x8
2172#define INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT 0x3
2173#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK 0xf0
2174#define INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT 0x4
2175#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK 0x100
2176#define INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT 0x8
2177#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK 0x1e00
2178#define INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT 0x9
2179#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK 0x6000
2180#define INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
2181#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK 0x8000
2182#define INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
2183#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK 0xffffffff
2184#define INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT 0x0
2185#define BIF_DEBUG_CNTL_IND__DEBUG_EN_MASK 0x1
2186#define BIF_DEBUG_CNTL_IND__DEBUG_EN__SHIFT 0x0
2187#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN_MASK 0x2
2188#define BIF_DEBUG_CNTL_IND__DEBUG_MULTIBLOCKEN__SHIFT 0x1
2189#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN_MASK 0x4
2190#define BIF_DEBUG_CNTL_IND__DEBUG_OUT_EN__SHIFT 0x2
2191#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL_MASK 0x8
2192#define BIF_DEBUG_CNTL_IND__DEBUG_PAD_SEL__SHIFT 0x3
2193#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1_MASK 0x10
2194#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK1__SHIFT 0x4
2195#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2_MASK 0x20
2196#define BIF_DEBUG_CNTL_IND__DEBUG_BYTESEL_BLK2__SHIFT 0x5
2197#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN_MASK 0x40
2198#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_EN__SHIFT 0x6
2199#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP_MASK 0x80
2200#define BIF_DEBUG_CNTL_IND__DEBUG_SWAP__SHIFT 0x7
2201#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1_MASK 0x1f00
2202#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK1__SHIFT 0x8
2203#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2_MASK 0x1f0000
2204#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_BLK2__SHIFT 0x10
2205#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP_MASK 0x1000000
2206#define BIF_DEBUG_CNTL_IND__DEBUG_IDSEL_XSP__SHIFT 0x18
2207#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL_MASK 0xc0000000
2208#define BIF_DEBUG_CNTL_IND__DEBUG_SYNC_CLKSEL__SHIFT 0x1e
2209#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1_MASK 0x3f
2210#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK1__SHIFT 0x0
2211#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2_MASK 0x3f00
2212#define BIF_DEBUG_MUX_IND__DEBUG_MUX_BLK2__SHIFT 0x8
2213#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT_MASK 0x1ffff
2214#define BIF_DEBUG_OUT_IND__DEBUG_OUTPUT__SHIFT 0x0
2215#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK 0x1
2216#define HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT 0x0
2217#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK 0x1
2218#define HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
2219#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A_MASK 0x1
2220#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_A__SHIFT 0x0
2221#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL_MASK 0x2
2222#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SEL__SHIFT 0x1
2223#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE_MASK 0x4
2224#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_MODE__SHIFT 0x2
2225#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE_MASK 0x18
2226#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SPARE__SHIFT 0x3
2227#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0_MASK 0x20
2228#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN0__SHIFT 0x5
2229#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1_MASK 0x40
2230#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN1__SHIFT 0x6
2231#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2_MASK 0x80
2232#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN2__SHIFT 0x7
2233#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3_MASK 0x100
2234#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SN3__SHIFT 0x8
2235#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN_MASK 0x200
2236#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SLEWN__SHIFT 0x9
2237#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE_MASK 0x400
2238#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_WAKE__SHIFT 0xa
2239#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN_MASK 0x800
2240#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_SCHMEN__SHIFT 0xb
2241#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN_MASK 0x1000
2242#define CLKREQB_PAD_CNTL_IND__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
2243#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A_MASK 0x1
2244#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_A__SHIFT 0x0
2245#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL_MASK 0x2
2246#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SEL__SHIFT 0x1
2247#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE_MASK 0x4
2248#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_MODE__SHIFT 0x2
2249#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE_MASK 0x18
2250#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SPARE__SHIFT 0x3
2251#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0_MASK 0x20
2252#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN0__SHIFT 0x5
2253#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1_MASK 0x40
2254#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN1__SHIFT 0x6
2255#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2_MASK 0x80
2256#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN2__SHIFT 0x7
2257#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3_MASK 0x100
2258#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SN3__SHIFT 0x8
2259#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN_MASK 0x200
2260#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SLEWN__SHIFT 0x9
2261#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE_MASK 0x400
2262#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_WAKE__SHIFT 0xa
2263#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN_MASK 0x800
2264#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_SCHMEN__SHIFT 0xb
2265#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN_MASK 0x1000
2266#define SMBDAT_PAD_CNTL_IND__SMBDAT_PAD_CNTL_EN__SHIFT 0xc
2267#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A_MASK 0x1
2268#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_A__SHIFT 0x0
2269#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL_MASK 0x2
2270#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SEL__SHIFT 0x1
2271#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE_MASK 0x4
2272#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_MODE__SHIFT 0x2
2273#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE_MASK 0x18
2274#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SPARE__SHIFT 0x3
2275#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0_MASK 0x20
2276#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN0__SHIFT 0x5
2277#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1_MASK 0x40
2278#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN1__SHIFT 0x6
2279#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2_MASK 0x80
2280#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN2__SHIFT 0x7
2281#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3_MASK 0x100
2282#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SN3__SHIFT 0x8
2283#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN_MASK 0x200
2284#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SLEWN__SHIFT 0x9
2285#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE_MASK 0x400
2286#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_WAKE__SHIFT 0xa
2287#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN_MASK 0x800
2288#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_SCHMEN__SHIFT 0xb
2289#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN_MASK 0x1000
2290#define SMBCLK_PAD_CNTL_IND__SMBCLK_PAD_CNTL_EN__SHIFT 0xc
2291#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND_MASK 0x1fffffff
2292#define BIF_XDMA_LO_IND__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
2293#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN_MASK 0x80000000
2294#define BIF_XDMA_LO_IND__BIF_XDMA_APER_EN__SHIFT 0x1f
2295#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND_MASK 0x1fffffff
2296#define BIF_XDMA_HI_IND__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
2297#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS_MASK 0x1
2298#define BIF_FEATURES_CONTROL_MISC_IND__MST_BIF_REQ_EP_DIS__SHIFT 0x0
2299#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS_MASK 0x2
2300#define BIF_FEATURES_CONTROL_MISC_IND__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
2301#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS_MASK 0x4
2302#define BIF_FEATURES_CONTROL_MISC_IND__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
2303#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS_MASK 0x8
2304#define BIF_FEATURES_CONTROL_MISC_IND__BIF_MST_CPL_EP_DIS__SHIFT 0x3
2305#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS_MASK 0x10
2306#define BIF_FEATURES_CONTROL_MISC_IND__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4
2307#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK 0x20
2308#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5
2309#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK 0x40
2310#define BIF_FEATURES_CONTROL_MISC_IND__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6
2311#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS_MASK 0x80
2312#define BIF_FEATURES_CONTROL_MISC_IND__PLL_SWITCH_IMPCTL_CAL_DONE_DIS__SHIFT 0x7
2313#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS_MASK 0x100
2314#define BIF_FEATURES_CONTROL_MISC_IND__IGNORE_BE_CHECK_GASKET_COMB_DIS__SHIFT 0x8
2315#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS_MASK 0x200
2316#define BIF_FEATURES_CONTROL_MISC_IND__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9
2317#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS_MASK 0x400
2318#define BIF_FEATURES_CONTROL_MISC_IND__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
2319#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN_MASK 0x800
2320#define BIF_FEATURES_CONTROL_MISC_IND__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb
2321#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN_MASK 0x1000
2322#define BIF_FEATURES_CONTROL_MISC_IND__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
2323#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS_MASK 0x1
2324#define BIF_DOORBELL_CNTL_IND__SELF_RING_DIS__SHIFT 0x0
2325#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS_MASK 0x2
2326#define BIF_DOORBELL_CNTL_IND__TRANS_CHECK_DIS__SHIFT 0x1
2327#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN_MASK 0x4
2328#define BIF_DOORBELL_CNTL_IND__UNTRANS_LBACK_EN__SHIFT 0x2
2329#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x8
2330#define BIF_DOORBELL_CNTL_IND__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
2331#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN_MASK 0x10
2332#define BIF_DOORBELL_CNTL_IND__DOORBELL_MONITOR_EN__SHIFT 0x4
2333#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS_MASK 0x20
2334#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_STATUS__SHIFT 0x5
2335#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR_MASK 0x10000
2336#define BIF_DOORBELL_CNTL_IND__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
2337#define BIF_SLVARB_MODE_IND__SLVARB_MODE_MASK 0x3
2338#define BIF_SLVARB_MODE_IND__SLVARB_MODE__SHIFT 0x0
2339#define BIF_FB_EN_IND__FB_READ_EN_MASK 0x1
2340#define BIF_FB_EN_IND__FB_READ_EN__SHIFT 0x0
2341#define BIF_FB_EN_IND__FB_WRITE_EN_MASK 0x2
2342#define BIF_FB_EN_IND__FB_WRITE_EN__SHIFT 0x1
2343#define BIF_BUSNUM_CNTL1_IND__ID_MASK_MASK 0xff
2344#define BIF_BUSNUM_CNTL1_IND__ID_MASK__SHIFT 0x0
2345#define BIF_BUSNUM_LIST0_IND__ID0_MASK 0xff
2346#define BIF_BUSNUM_LIST0_IND__ID0__SHIFT 0x0
2347#define BIF_BUSNUM_LIST0_IND__ID1_MASK 0xff00
2348#define BIF_BUSNUM_LIST0_IND__ID1__SHIFT 0x8
2349#define BIF_BUSNUM_LIST0_IND__ID2_MASK 0xff0000
2350#define BIF_BUSNUM_LIST0_IND__ID2__SHIFT 0x10
2351#define BIF_BUSNUM_LIST0_IND__ID3_MASK 0xff000000
2352#define BIF_BUSNUM_LIST0_IND__ID3__SHIFT 0x18
2353#define BIF_BUSNUM_LIST1_IND__ID4_MASK 0xff
2354#define BIF_BUSNUM_LIST1_IND__ID4__SHIFT 0x0
2355#define BIF_BUSNUM_LIST1_IND__ID5_MASK 0xff00
2356#define BIF_BUSNUM_LIST1_IND__ID5__SHIFT 0x8
2357#define BIF_BUSNUM_LIST1_IND__ID6_MASK 0xff0000
2358#define BIF_BUSNUM_LIST1_IND__ID6__SHIFT 0x10
2359#define BIF_BUSNUM_LIST1_IND__ID7_MASK 0xff000000
2360#define BIF_BUSNUM_LIST1_IND__ID7__SHIFT 0x18
2361#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL_MASK 0xff
2362#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_SEL__SHIFT 0x0
2363#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN_MASK 0x100
2364#define BIF_BUSNUM_CNTL2_IND__AUTOUPDATE_EN__SHIFT 0x8
2365#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL_MASK 0x10000
2366#define BIF_BUSNUM_CNTL2_IND__HDPREG_CNTL__SHIFT 0x10
2367#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH_MASK 0x20000
2368#define BIF_BUSNUM_CNTL2_IND__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
2369#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT_MASK 0x3f
2370#define BIF_BUSY_DELAY_CNTR_IND__DELAY_CNT__SHIFT 0x0
2371#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN_MASK 0x1
2372#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_EN__SHIFT 0x0
2373#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0_MASK 0x2
2374#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET0__SHIFT 0x1
2375#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1_MASK 0x4
2376#define BIF_PERFMON_CNTL_IND__PERFCOUNTER_RESET1__SHIFT 0x2
2377#define BIF_PERFMON_CNTL_IND__PERF_SEL0_MASK 0x1f00
2378#define BIF_PERFMON_CNTL_IND__PERF_SEL0__SHIFT 0x8
2379#define BIF_PERFMON_CNTL_IND__PERF_SEL1_MASK 0x3e000
2380#define BIF_PERFMON_CNTL_IND__PERF_SEL1__SHIFT 0xd
2381#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
2382#define BIF_PERFCOUNTER0_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
2383#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT_MASK 0xffffffff
2384#define BIF_PERFCOUNTER1_RESULT_IND__PERFCOUNTER_RESULT__SHIFT 0x0
2385#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL_MASK 0xe
2386#define SLAVE_HANG_PROTECTION_CNTL_IND__HANG_PROTECTION_TIMER_SEL__SHIFT 0x1
2387#define GPU_HDP_FLUSH_REQ_IND__CP0_MASK 0x1
2388#define GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT 0x0
2389#define GPU_HDP_FLUSH_REQ_IND__CP1_MASK 0x2
2390#define GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT 0x1
2391#define GPU_HDP_FLUSH_REQ_IND__CP2_MASK 0x4
2392#define GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT 0x2
2393#define GPU_HDP_FLUSH_REQ_IND__CP3_MASK 0x8
2394#define GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT 0x3
2395#define GPU_HDP_FLUSH_REQ_IND__CP4_MASK 0x10
2396#define GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT 0x4
2397#define GPU_HDP_FLUSH_REQ_IND__CP5_MASK 0x20
2398#define GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT 0x5
2399#define GPU_HDP_FLUSH_REQ_IND__CP6_MASK 0x40
2400#define GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT 0x6
2401#define GPU_HDP_FLUSH_REQ_IND__CP7_MASK 0x80
2402#define GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT 0x7
2403#define GPU_HDP_FLUSH_REQ_IND__CP8_MASK 0x100
2404#define GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT 0x8
2405#define GPU_HDP_FLUSH_REQ_IND__CP9_MASK 0x200
2406#define GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT 0x9
2407#define GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK 0x400
2408#define GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
2409#define GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK 0x800
2410#define GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
2411#define GPU_HDP_FLUSH_DONE_IND__CP0_MASK 0x1
2412#define GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT 0x0
2413#define GPU_HDP_FLUSH_DONE_IND__CP1_MASK 0x2
2414#define GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT 0x1
2415#define GPU_HDP_FLUSH_DONE_IND__CP2_MASK 0x4
2416#define GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT 0x2
2417#define GPU_HDP_FLUSH_DONE_IND__CP3_MASK 0x8
2418#define GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT 0x3
2419#define GPU_HDP_FLUSH_DONE_IND__CP4_MASK 0x10
2420#define GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT 0x4
2421#define GPU_HDP_FLUSH_DONE_IND__CP5_MASK 0x20
2422#define GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT 0x5
2423#define GPU_HDP_FLUSH_DONE_IND__CP6_MASK 0x40
2424#define GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT 0x6
2425#define GPU_HDP_FLUSH_DONE_IND__CP7_MASK 0x80
2426#define GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT 0x7
2427#define GPU_HDP_FLUSH_DONE_IND__CP8_MASK 0x100
2428#define GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT 0x8
2429#define GPU_HDP_FLUSH_DONE_IND__CP9_MASK 0x200
2430#define GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT 0x9
2431#define GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK 0x400
2432#define GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
2433#define GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK 0x800
2434#define GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
2435#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR_MASK 0x1
2436#define SLAVE_HANG_ERROR_IND__SRBM_HANG_ERROR__SHIFT 0x0
2437#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR_MASK 0x2
2438#define SLAVE_HANG_ERROR_IND__HDP_HANG_ERROR__SHIFT 0x1
2439#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR_MASK 0x4
2440#define SLAVE_HANG_ERROR_IND__VGA_HANG_ERROR__SHIFT 0x2
2441#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR_MASK 0x8
2442#define SLAVE_HANG_ERROR_IND__ROM_HANG_ERROR__SHIFT 0x3
2443#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR_MASK 0x10
2444#define SLAVE_HANG_ERROR_IND__AUDIO_HANG_ERROR__SHIFT 0x4
2445#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR_MASK 0x20
2446#define SLAVE_HANG_ERROR_IND__CEC_HANG_ERROR__SHIFT 0x5
2447#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR_MASK 0x80
2448#define SLAVE_HANG_ERROR_IND__XDMA_HANG_ERROR__SHIFT 0x7
2449#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR_MASK 0x100
2450#define SLAVE_HANG_ERROR_IND__DOORBELL_HANG_ERROR__SHIFT 0x8
2451#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR_MASK 0x200
2452#define SLAVE_HANG_ERROR_IND__GARLIC_HANG_ERROR__SHIFT 0x9
2453#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN_MASK 0x1
2454#define CAPTURE_HOST_BUSNUM_IND__CHECK_EN__SHIFT 0x0
2455#define HOST_BUSNUM_IND__HOST_ID_MASK 0xffff
2456#define HOST_BUSNUM_IND__HOST_ID__SHIFT 0x0
2457#define PEER_REG_RANGE0_IND__START_ADDR_MASK 0xffff
2458#define PEER_REG_RANGE0_IND__START_ADDR__SHIFT 0x0
2459#define PEER_REG_RANGE0_IND__END_ADDR_MASK 0xffff0000
2460#define PEER_REG_RANGE0_IND__END_ADDR__SHIFT 0x10
2461#define PEER_REG_RANGE1_IND__START_ADDR_MASK 0xffff
2462#define PEER_REG_RANGE1_IND__START_ADDR__SHIFT 0x0
2463#define PEER_REG_RANGE1_IND__END_ADDR_MASK 0xffff0000
2464#define PEER_REG_RANGE1_IND__END_ADDR__SHIFT 0x10
2465#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK 0xfffff
2466#define PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT 0x0
2467#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK 0xfffff
2468#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT 0x0
2469#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK 0x80000000
2470#define PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT 0x1f
2471#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK 0xfffff
2472#define PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT 0x0
2473#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK 0xfffff
2474#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT 0x0
2475#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK 0x80000000
2476#define PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT 0x1f
2477#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK 0xfffff
2478#define PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT 0x0
2479#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK 0xfffff
2480#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT 0x0
2481#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK 0x80000000
2482#define PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT 0x1f
2483#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK 0xfffff
2484#define PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT 0x0
2485#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK 0xfffff
2486#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT 0x0
2487#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK 0x80000000
2488#define PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT 0x1f
2489#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN_MASK 0x1
2490#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_BYPASS_SRBM_ACCESS_EN__SHIFT 0x0
2491#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD_MASK 0x1e
2492#define DBG_BYPASS_SRBM_ACCESS_IND__DBG_APER_AD__SHIFT 0x1
2493#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA_MASK 0xffffffff
2494#define SMBUS_BACO_DUMMY_IND__SMBUS_BACO_DUMMY_DATA__SHIFT 0x0
2495#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0_MASK 0xff
2496#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID0__SHIFT 0x0
2497#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1_MASK 0xff00
2498#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID1__SHIFT 0x8
2499#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2_MASK 0xff0000
2500#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID2__SHIFT 0x10
2501#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3_MASK 0xff000000
2502#define BIF_DEVFUNCNUM_LIST0_IND__DEVFUNC_ID3__SHIFT 0x18
2503#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4_MASK 0xff
2504#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID4__SHIFT 0x0
2505#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5_MASK 0xff00
2506#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID5__SHIFT 0x8
2507#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6_MASK 0xff0000
2508#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID6__SHIFT 0x10
2509#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7_MASK 0xff000000
2510#define BIF_DEVFUNCNUM_LIST1_IND__DEVFUNC_ID7__SHIFT 0x18
2511#define BACO_CNTL_IND__BACO_EN_MASK 0x1
2512#define BACO_CNTL_IND__BACO_EN__SHIFT 0x0
2513#define BACO_CNTL_IND__BACO_BCLK_OFF_MASK 0x2
2514#define BACO_CNTL_IND__BACO_BCLK_OFF__SHIFT 0x1
2515#define BACO_CNTL_IND__BACO_ISO_DIS_MASK 0x4
2516#define BACO_CNTL_IND__BACO_ISO_DIS__SHIFT 0x2
2517#define BACO_CNTL_IND__BACO_POWER_OFF_MASK 0x8
2518#define BACO_CNTL_IND__BACO_POWER_OFF__SHIFT 0x3
2519#define BACO_CNTL_IND__BACO_RESET_EN_MASK 0x10
2520#define BACO_CNTL_IND__BACO_RESET_EN__SHIFT 0x4
2521#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN_MASK 0x20
2522#define BACO_CNTL_IND__BACO_HANG_PROTECTION_EN__SHIFT 0x5
2523#define BACO_CNTL_IND__BACO_MODE_MASK 0x40
2524#define BACO_CNTL_IND__BACO_MODE__SHIFT 0x6
2525#define BACO_CNTL_IND__BACO_ANA_ISO_DIS_MASK 0x80
2526#define BACO_CNTL_IND__BACO_ANA_ISO_DIS__SHIFT 0x7
2527#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE_MASK 0x100
2528#define BACO_CNTL_IND__RCU_BIF_CONFIG_DONE__SHIFT 0x8
2529#define BACO_CNTL_IND__PWRGOOD_BF_MASK 0x200
2530#define BACO_CNTL_IND__PWRGOOD_BF__SHIFT 0x9
2531#define BACO_CNTL_IND__PWRGOOD_GPIO_MASK 0x400
2532#define BACO_CNTL_IND__PWRGOOD_GPIO__SHIFT 0xa
2533#define BACO_CNTL_IND__PWRGOOD_MEM_MASK 0x800
2534#define BACO_CNTL_IND__PWRGOOD_MEM__SHIFT 0xb
2535#define BACO_CNTL_IND__PWRGOOD_DVO_MASK 0x1000
2536#define BACO_CNTL_IND__PWRGOOD_DVO__SHIFT 0xc
2537#define BACO_CNTL_IND__PWRGOOD_IDSC_MASK 0x2000
2538#define BACO_CNTL_IND__PWRGOOD_IDSC__SHIFT 0xd
2539#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM_MASK 0x10000
2540#define BACO_CNTL_IND__BACO_POWER_OFF_DRAM__SHIFT 0x10
2541#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL_MASK 0x20000
2542#define BACO_CNTL_IND__BACO_BF_MEM_PHY_ISO_CNTRL__SHIFT 0x11
2543#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK_MASK 0x1
2544#define BF_ANA_ISO_CNTL_IND__BF_ANA_ISO_DIS_MASK__SHIFT 0x0
2545#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK_MASK 0x2
2546#define BF_ANA_ISO_CNTL_IND__BF_VDDC_ISO_DIS_MASK__SHIFT 0x1
2547#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3_MASK 0x1
2548#define MEM_TYPE_CNTL_IND__BF_MEM_PHY_G5_G3__SHIFT 0x0
2549#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG_MASK 0x1
2550#define BIF_BACO_DEBUG_IND__BIF_BACO_SCANDUMP_FLG__SHIFT 0x0
2551#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG_MASK 0x1
2552#define BIF_BACO_DEBUG_LATCH_IND__BIF_BACO_LATCH_FLG__SHIFT 0x0
2553#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS_MASK 0x1
2554#define BACO_CNTL_MISC_IND__BIF_ROM_REQ_DIS__SHIFT 0x0
2555#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS_MASK 0x2
2556#define BACO_CNTL_MISC_IND__BIF_AZ_REQ_DIS__SHIFT 0x1
2557#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL_MASK 0xc
2558#define BACO_CNTL_MISC_IND__BACO_LINK_RST_WIDTH_SEL__SHIFT 0x2
2559#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF_MASK 0x1
2560#define SMU_BIF_VDDGFX_PWR_STATUS_IND__VDDGFX_GFX_PWR_OFF__SHIFT 0x0
2561#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER_MASK 0x3fffc
2562#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2
2563#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN_MASK 0x40000000
2564#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e
2565#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN_MASK 0x80000000
2566#define BIF_VDDGFX_GFX0_LOWER_IND__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f
2567#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER_MASK 0x3fffc
2568#define BIF_VDDGFX_GFX0_UPPER_IND__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2
2569#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER_MASK 0x3fffc
2570#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2
2571#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN_MASK 0x40000000
2572#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e
2573#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN_MASK 0x80000000
2574#define BIF_VDDGFX_GFX1_LOWER_IND__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f
2575#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER_MASK 0x3fffc
2576#define BIF_VDDGFX_GFX1_UPPER_IND__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2
2577#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER_MASK 0x3fffc
2578#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2
2579#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN_MASK 0x40000000
2580#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e
2581#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN_MASK 0x80000000
2582#define BIF_VDDGFX_GFX2_LOWER_IND__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f
2583#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER_MASK 0x3fffc
2584#define BIF_VDDGFX_GFX2_UPPER_IND__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2
2585#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER_MASK 0x3fffc
2586#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2
2587#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN_MASK 0x40000000
2588#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e
2589#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN_MASK 0x80000000
2590#define BIF_VDDGFX_GFX3_LOWER_IND__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f
2591#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER_MASK 0x3fffc
2592#define BIF_VDDGFX_GFX3_UPPER_IND__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2
2593#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER_MASK 0x3fffc
2594#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2
2595#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN_MASK 0x40000000
2596#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e
2597#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN_MASK 0x80000000
2598#define BIF_VDDGFX_GFX4_LOWER_IND__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f
2599#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER_MASK 0x3fffc
2600#define BIF_VDDGFX_GFX4_UPPER_IND__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2
2601#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER_MASK 0x3fffc
2602#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2
2603#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN_MASK 0x40000000
2604#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e
2605#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN_MASK 0x80000000
2606#define BIF_VDDGFX_GFX5_LOWER_IND__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f
2607#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER_MASK 0x3fffc
2608#define BIF_VDDGFX_GFX5_UPPER_IND__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2
2609#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER_MASK 0x3fffc
2610#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2
2611#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN_MASK 0x40000000
2612#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e
2613#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN_MASK 0x80000000
2614#define BIF_VDDGFX_RSV1_LOWER_IND__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f
2615#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER_MASK 0x3fffc
2616#define BIF_VDDGFX_RSV1_UPPER_IND__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2
2617#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER_MASK 0x3fffc
2618#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2
2619#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN_MASK 0x40000000
2620#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e
2621#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN_MASK 0x80000000
2622#define BIF_VDDGFX_RSV2_LOWER_IND__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f
2623#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER_MASK 0x3fffc
2624#define BIF_VDDGFX_RSV2_UPPER_IND__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2
2625#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER_MASK 0x3fffc
2626#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2
2627#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN_MASK 0x40000000
2628#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e
2629#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN_MASK 0x80000000
2630#define BIF_VDDGFX_RSV3_LOWER_IND__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f
2631#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER_MASK 0x3fffc
2632#define BIF_VDDGFX_RSV3_UPPER_IND__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2
2633#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER_MASK 0x3fffc
2634#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2
2635#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN_MASK 0x40000000
2636#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e
2637#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN_MASK 0x80000000
2638#define BIF_VDDGFX_RSV4_LOWER_IND__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f
2639#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER_MASK 0x3fffc
2640#define BIF_VDDGFX_RSV4_UPPER_IND__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2
2641#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN_MASK 0x1
2642#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0
2643#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN_MASK 0x2
2644#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1
2645#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN_MASK 0x4
2646#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2
2647#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN_MASK 0x8
2648#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3
2649#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN_MASK 0x10
2650#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4
2651#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN_MASK 0x20
2652#define BIF_VDDGFX_FB_CMP_IND__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5
2653#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER_MASK 0xffc
2654#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2
2655#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN_MASK 0x80000000
2656#define BIF_DOORBELL_GBLAPER1_LOWER_IND__DOORBELL_GBLAPER1_EN__SHIFT 0x1f
2657#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER_MASK 0xffc
2658#define BIF_DOORBELL_GBLAPER1_UPPER_IND__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2
2659#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER_MASK 0xffc
2660#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2
2661#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN_MASK 0x80000000
2662#define BIF_DOORBELL_GBLAPER2_LOWER_IND__DOORBELL_GBLAPER2_EN__SHIFT 0x1f
2663#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER_MASK 0xffc
2664#define BIF_DOORBELL_GBLAPER2_UPPER_IND__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2
2665#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX_MASK 0x7fffc
2666#define BIF_SMU_INDEX_IND__BIF_SMU_INDEX__SHIFT 0x2
2667#define BIF_SMU_DATA_IND__BIF_SMU_DATA_MASK 0x7fffc
2668#define BIF_SMU_DATA_IND__BIF_SMU_DATA__SHIFT 0x2
2669#define IMPCTL_RESET_IND__IMP_SW_RESET_MASK 0x1
2670#define IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT 0x0
2671#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK 0x1
2672#define GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT 0x0
2673#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK 0x2
2674#define GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT 0x1
2675#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK 0x4
2676#define GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT 0x2
2677#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK 0x8
2678#define GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT 0x3
2679#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK 0x10
2680#define GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT 0x4
2681#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK 0x20
2682#define GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT 0x5
2683#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK 0x40
2684#define GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT 0x6
2685#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK 0x80
2686#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT 0x7
2687#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK 0x100
2688#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT 0x8
2689#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK 0x200
2690#define GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT 0x9
2691#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK 0x400
2692#define GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT 0xa
2693#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK 0x800
2694#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT 0xb
2695#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK 0x1000
2696#define GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT 0xc
2697#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK 0x2000
2698#define GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT 0xd
2699#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK 0x4000
2700#define GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT 0xe
2701#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK 0x8000
2702#define GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT 0xf
2703#define GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK 0x10000
2704#define GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT 0x10
2705#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK 0x20000
2706#define GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT 0x11
2707#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK 0x40000
2708#define GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT 0x12
2709#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK 0x40000000
2710#define GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT 0x1e
2711#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK 0x80000000
2712#define GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT 0x1f
2713#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK 0x1
2714#define GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT 0x0
2715#define GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK 0x1
2716#define GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT 0x0
2717#define GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK 0x2
2718#define GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT 0x1
2719#define GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK 0x4
2720#define GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT 0x2
2721#define GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK 0x8
2722#define GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT 0x3
2723#define GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK 0x10
2724#define GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT 0x4
2725#define GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK 0x20
2726#define GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT 0x5
2727#define GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK 0x40
2728#define GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT 0x6
2729#define GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK 0x80
2730#define GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT 0x7
2731#define GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK 0x100
2732#define GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT 0x8
2733#define GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK 0x200
2734#define GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT 0x9
2735#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK 0x400
2736#define GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT 0xa
2737#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK 0x800
2738#define GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT 0xb
2739#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK 0x1000
2740#define GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT 0xc
2741#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK 0x2000
2742#define GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT 0xd
2743#define GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK 0x1
2744#define GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT 0x0
2745#define GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK 0x2
2746#define GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT 0x1
2747#define GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK 0x4
2748#define GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT 0x2
2749#define GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK 0x8
2750#define GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT 0x3
2751#define GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK 0x10
2752#define GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT 0x4
2753#define GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK 0x20
2754#define GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT 0x5
2755#define GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK 0x40
2756#define GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT 0x6
2757#define GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK 0x80
2758#define GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT 0x7
2759#define GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK 0x100
2760#define GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT 0x8
2761#define GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK 0x200
2762#define GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT 0x9
2763#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK 0x400
2764#define GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT 0xa
2765#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK 0x800
2766#define GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT 0xb
2767#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK 0x1000
2768#define GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT 0xc
2769#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK 0x2000
2770#define GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT 0xd
2771#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK 0x7fffc
2772#define GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT 0x2
2773#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK 0x7fffc
2774#define GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT 0x2
2775#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK 0x7fffc
2776#define GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT 0x2
2777#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2778#define GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2779#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2780#define GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2781#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2782#define GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2783#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK 0x7fffc
2784#define GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT 0x2
2785#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK 0x7fffc
2786#define GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT 0x2
2787#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK 0x7fffc
2788#define GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT 0x2
2789#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK 0x7fffc
2790#define GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT 0x2
2791#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2792#define GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2793#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK 0x7fffc
2794#define GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT 0x2
2795#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2796#define GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2797#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2798#define GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2799#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK 0x7fffc
2800#define GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT 0x2
2801#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK 0x7fffc
2802#define GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT 0x2
2803#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK 0x7fffc
2804#define GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT 0x2
2805#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
2806#define REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
2807#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK 0x7fffc
2808#define REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT 0x2
2809#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0_MASK 0xffffffff
2810#define BIOS_SCRATCH_0_IND__BIOS_SCRATCH_0__SHIFT 0x0
2811#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1_MASK 0xffffffff
2812#define BIOS_SCRATCH_1_IND__BIOS_SCRATCH_1__SHIFT 0x0
2813#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2_MASK 0xffffffff
2814#define BIOS_SCRATCH_2_IND__BIOS_SCRATCH_2__SHIFT 0x0
2815#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3_MASK 0xffffffff
2816#define BIOS_SCRATCH_3_IND__BIOS_SCRATCH_3__SHIFT 0x0
2817#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4_MASK 0xffffffff
2818#define BIOS_SCRATCH_4_IND__BIOS_SCRATCH_4__SHIFT 0x0
2819#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5_MASK 0xffffffff
2820#define BIOS_SCRATCH_5_IND__BIOS_SCRATCH_5__SHIFT 0x0
2821#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6_MASK 0xffffffff
2822#define BIOS_SCRATCH_6_IND__BIOS_SCRATCH_6__SHIFT 0x0
2823#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7_MASK 0xffffffff
2824#define BIOS_SCRATCH_7_IND__BIOS_SCRATCH_7__SHIFT 0x0
2825#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8_MASK 0xffffffff
2826#define BIOS_SCRATCH_8_IND__BIOS_SCRATCH_8__SHIFT 0x0
2827#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9_MASK 0xffffffff
2828#define BIOS_SCRATCH_9_IND__BIOS_SCRATCH_9__SHIFT 0x0
2829#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10_MASK 0xffffffff
2830#define BIOS_SCRATCH_10_IND__BIOS_SCRATCH_10__SHIFT 0x0
2831#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11_MASK 0xffffffff
2832#define BIOS_SCRATCH_11_IND__BIOS_SCRATCH_11__SHIFT 0x0
2833#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12_MASK 0xffffffff
2834#define BIOS_SCRATCH_12_IND__BIOS_SCRATCH_12__SHIFT 0x0
2835#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13_MASK 0xffffffff
2836#define BIOS_SCRATCH_13_IND__BIOS_SCRATCH_13__SHIFT 0x0
2837#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14_MASK 0xffffffff
2838#define BIOS_SCRATCH_14_IND__BIOS_SCRATCH_14__SHIFT 0x0
2839#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15_MASK 0xffffffff
2840#define BIOS_SCRATCH_15_IND__BIOS_SCRATCH_15__SHIFT 0x0
2841#define BIF_RB_CNTL_IND__RB_ENABLE_MASK 0x1
2842#define BIF_RB_CNTL_IND__RB_ENABLE__SHIFT 0x0
2843#define BIF_RB_CNTL_IND__RB_SIZE_MASK 0x3e
2844#define BIF_RB_CNTL_IND__RB_SIZE__SHIFT 0x1
2845#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE_MASK 0x100
2846#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
2847#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER_MASK 0x3e00
2848#define BIF_RB_CNTL_IND__WPTR_WRITEBACK_TIMER__SHIFT 0x9
2849#define BIF_RB_CNTL_IND__BIF_RB_TRAN_MASK 0x20000
2850#define BIF_RB_CNTL_IND__BIF_RB_TRAN__SHIFT 0x11
2851#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
2852#define BIF_RB_CNTL_IND__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
2853#define BIF_RB_BASE_IND__ADDR_MASK 0xffffffff
2854#define BIF_RB_BASE_IND__ADDR__SHIFT 0x0
2855#define BIF_RB_RPTR_IND__OFFSET_MASK 0x3fffc
2856#define BIF_RB_RPTR_IND__OFFSET__SHIFT 0x2
2857#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW_MASK 0x1
2858#define BIF_RB_WPTR_IND__BIF_RB_OVERFLOW__SHIFT 0x0
2859#define BIF_RB_WPTR_IND__OFFSET_MASK 0x3fffc
2860#define BIF_RB_WPTR_IND__OFFSET__SHIFT 0x2
2861#define BIF_RB_WPTR_ADDR_HI_IND__ADDR_MASK 0xff
2862#define BIF_RB_WPTR_ADDR_HI_IND__ADDR__SHIFT 0x0
2863#define BIF_RB_WPTR_ADDR_LO_IND__ADDR_MASK 0xfffffffc
2864#define BIF_RB_WPTR_ADDR_LO_IND__ADDR__SHIFT 0x2
2865#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
2866#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
2867#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
2868#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
2869#define PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
2870#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
2871#define PCIE_DATA__PCIE_DATA_MASK 0xffffffff
2872#define PCIE_DATA__PCIE_DATA__SHIFT 0x0
2873#define PCIE_INDEX_2__PCIE_INDEX_MASK 0xffffffff
2874#define PCIE_INDEX_2__PCIE_INDEX__SHIFT 0x0
2875#define PCIE_DATA_2__PCIE_DATA_MASK 0xffffffff
2876#define PCIE_DATA_2__PCIE_DATA__SHIFT 0x0
2877#define PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
2878#define PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
2879#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
2880#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
2881#define PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
2882#define PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
2883#define PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
2884#define PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
2885#define PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
2886#define PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
2887#define PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
2888#define PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
2889#define PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
2890#define PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
2891#define PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
2892#define PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
2893#define PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
2894#define PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
2895#define PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
2896#define PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
2897#define PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
2898#define PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
2899#define PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
2900#define PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
2901#define PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
2902#define PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
2903#define PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
2904#define PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
2905#define PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
2906#define PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
2907#define PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
2908#define PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
2909#define PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
2910#define PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
2911#define PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
2912#define PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
2913#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
2914#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
2915#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
2916#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
2917#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
2918#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
2919#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
2920#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
2921#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
2922#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
2923#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
2924#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
2925#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
2926#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
2927#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
2928#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
2929#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
2930#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
2931#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
2932#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
2933#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
2934#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
2935#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
2936#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
2937#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
2938#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
2939#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK 0x100000
2940#define PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT 0x14
2941#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
2942#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
2943#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
2944#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
2945#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
2946#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
2947#define PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
2948#define PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
2949#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
2950#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
2951#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
2952#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
2953#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
2954#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
2955#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
2956#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
2957#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
2958#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
2959#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
2960#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
2961#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
2962#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
2963#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
2964#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
2965#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
2966#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
2967#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
2968#define PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
2969#define PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
2970#define PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
2971#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
2972#define PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
2973#define PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x1
2974#define PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
2975#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x2
2976#define PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
2977#define PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x4
2978#define PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
2979#define PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x8
2980#define PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
2981#define PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x10
2982#define PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
2983#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x40
2984#define PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
2985#define PCIE_INT_CNTL__LINK_BW_INT_EN_MASK 0x80
2986#define PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT 0x7
2987#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK 0x100
2988#define PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT 0x8
2989#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x1
2990#define PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
2991#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x2
2992#define PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
2993#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x4
2994#define PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
2995#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x8
2996#define PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
2997#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x10
2998#define PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
2999#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x40
3000#define PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
3001#define PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK 0x80
3002#define PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT 0x7
3003#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK 0x100
3004#define PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT 0x8
3005#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
3006#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
3007#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
3008#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
3009#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
3010#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
3011#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
3012#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
3013#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
3014#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
3015#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
3016#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
3017#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
3018#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
3019#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
3020#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
3021#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
3022#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
3023#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
3024#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
3025#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
3026#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
3027#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
3028#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
3029#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
3030#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
3031#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
3032#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
3033#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
3034#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
3035#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
3036#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
3037#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
3038#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
3039#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
3040#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
3041#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
3042#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
3043#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
3044#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
3045#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
3046#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
3047#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
3048#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
3049#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
3050#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
3051#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
3052#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
3053#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
3054#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
3055#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
3056#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
3057#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
3058#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
3059#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
3060#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
3061#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
3062#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
3063#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK 0x3
3064#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT 0x0
3065#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK 0xc
3066#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT 0x2
3067#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK 0x30
3068#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT 0x4
3069#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK 0xc0
3070#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT 0x6
3071#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK 0x300
3072#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT 0x8
3073#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK 0xc00
3074#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT 0xa
3075#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK 0x3000
3076#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT 0xc
3077#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK 0x30000
3078#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT 0x10
3079#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK 0xc0000
3080#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT 0x12
3081#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK 0x300000
3082#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT 0x14
3083#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK 0xc00000
3084#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT 0x16
3085#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK 0x3000000
3086#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT 0x18
3087#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK 0xc000000
3088#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT 0x1a
3089#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK 0x30000000
3090#define PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT 0x1c
3091#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
3092#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
3093#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
3094#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
3095#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
3096#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
3097#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
3098#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
3099#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
3100#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
3101#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
3102#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
3103#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
3104#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
3105#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
3106#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
3107#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
3108#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
3109#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK 0x2000
3110#define PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT 0xd
3111#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
3112#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
3113#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
3114#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
3115#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
3116#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
3117#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
3118#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
3119#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
3120#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
3121#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
3122#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
3123#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
3124#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
3125#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
3126#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
3127#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
3128#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
3129#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
3130#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
3131#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
3132#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
3133#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
3134#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
3135#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
3136#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
3137#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
3138#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
3139#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
3140#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
3141#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
3142#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
3143#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
3144#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
3145#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
3146#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
3147#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
3148#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
3149#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
3150#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
3151#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
3152#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
3153#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
3154#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
3155#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
3156#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
3157#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
3158#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
3159#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
3160#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
3161#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
3162#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
3163#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
3164#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
3165#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
3166#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
3167#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
3168#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
3169#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
3170#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
3171#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
3172#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
3173#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
3174#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
3175#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
3176#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
3177#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
3178#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
3179#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
3180#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
3181#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
3182#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
3183#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
3184#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
3185#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
3186#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
3187#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
3188#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
3189#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
3190#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
3191#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
3192#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
3193#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
3194#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
3195#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
3196#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
3197#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
3198#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
3199#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
3200#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
3201#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
3202#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
3203#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
3204#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
3205#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
3206#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
3207#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
3208#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
3209#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
3210#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
3211#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
3212#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
3213#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
3214#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
3215#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
3216#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
3217#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
3218#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
3219#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
3220#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
3221#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
3222#define PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
3223#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
3224#define PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
3225#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
3226#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
3227#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
3228#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
3229#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
3230#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
3231#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
3232#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
3233#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
3234#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
3235#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
3236#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
3237#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
3238#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
3239#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
3240#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
3241#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
3242#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
3243#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
3244#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
3245#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
3246#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
3247#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
3248#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
3249#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
3250#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
3251#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
3252#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
3253#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
3254#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
3255#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
3256#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
3257#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK 0x1
3258#define PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0
3259#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK 0x2
3260#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1
3261#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK 0x4
3262#define PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2
3263#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK 0x8
3264#define PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3
3265#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK 0xf0
3266#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4
3267#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK 0xf00
3268#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8
3269#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK 0xf000
3270#define PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc
3271#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK 0x10000
3272#define PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10
3273#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK 0x20000
3274#define PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11
3275#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK 0x40000
3276#define PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12
3277#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK 0xf00000
3278#define PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14
3279#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x7
3280#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
3281#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x38
3282#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
3283#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x40
3284#define PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
3285#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x380
3286#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
3287#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x1c00
3288#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
3289#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x2000
3290#define PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
3291#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x4000
3292#define PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
3293#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x8000
3294#define PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
3295#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
3296#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
3297#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
3298#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
3299#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
3300#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
3301#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
3302#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
3303#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
3304#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
3305#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
3306#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
3307#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
3308#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
3309#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
3310#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
3311#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
3312#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
3313#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
3314#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
3315#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
3316#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
3317#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
3318#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
3319#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
3320#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
3321#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
3322#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
3323#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
3324#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
3325#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
3326#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
3327#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
3328#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
3329#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
3330#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
3331#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
3332#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
3333#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
3334#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
3335#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
3336#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
3337#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
3338#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
3339#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
3340#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
3341#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
3342#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
3343#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
3344#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
3345#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
3346#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
3347#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
3348#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
3349#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
3350#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
3351#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
3352#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
3353#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
3354#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
3355#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
3356#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
3357#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
3358#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
3359#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
3360#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
3361#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
3362#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
3363#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
3364#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
3365#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
3366#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
3367#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
3368#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
3369#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
3370#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
3371#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
3372#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
3373#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
3374#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
3375#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
3376#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
3377#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
3378#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
3379#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
3380#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
3381#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
3382#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
3383#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
3384#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
3385#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
3386#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
3387#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
3388#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
3389#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
3390#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
3391#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
3392#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
3393#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
3394#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
3395#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
3396#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
3397#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
3398#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
3399#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
3400#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
3401#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
3402#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
3403#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
3404#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
3405#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
3406#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
3407#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
3408#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
3409#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
3410#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
3411#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
3412#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
3413#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
3414#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
3415#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3416#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3417#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
3418#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
3419#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
3420#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
3421#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
3422#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
3423#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
3424#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
3425#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
3426#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
3427#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
3428#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
3429#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
3430#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
3431#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
3432#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
3433#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
3434#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
3435#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
3436#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
3437#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
3438#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
3439#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
3440#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
3441#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
3442#define PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
3443#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
3444#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
3445#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3446#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3447#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
3448#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
3449#define PCIE_STRAP_F1__STRAP_F1_EN_MASK 0x1
3450#define PCIE_STRAP_F1__STRAP_F1_EN__SHIFT 0x0
3451#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3452#define PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3453#define PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK 0x4
3454#define PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT 0x2
3455#define PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK 0x8
3456#define PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT 0x3
3457#define PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK 0x10
3458#define PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT 0x4
3459#define PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK 0x20
3460#define PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT 0x5
3461#define PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK 0x40
3462#define PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT 0x6
3463#define PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK 0x80
3464#define PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT 0x7
3465#define PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK 0x100
3466#define PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT 0x8
3467#define PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK 0x200
3468#define PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT 0x9
3469#define PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK 0x400
3470#define PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT 0xa
3471#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK 0x800
3472#define PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT 0xb
3473#define PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK 0x1000
3474#define PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT 0xc
3475#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK 0x2000
3476#define PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT 0xd
3477#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK 0x4000
3478#define PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT 0xe
3479#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK 0x8000
3480#define PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT 0xf
3481#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3482#define PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3483#define PCIE_STRAP_F2__STRAP_F2_EN_MASK 0x1
3484#define PCIE_STRAP_F2__STRAP_F2_EN__SHIFT 0x0
3485#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK 0x2
3486#define PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
3487#define PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK 0x4
3488#define PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT 0x2
3489#define PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK 0x8
3490#define PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT 0x3
3491#define PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK 0x10
3492#define PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT 0x4
3493#define PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK 0x20
3494#define PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT 0x5
3495#define PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK 0x40
3496#define PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT 0x6
3497#define PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK 0x80
3498#define PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT 0x7
3499#define PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK 0x100
3500#define PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT 0x8
3501#define PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK 0x200
3502#define PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT 0x9
3503#define PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK 0x400
3504#define PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT 0xa
3505#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK 0x800
3506#define PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT 0xb
3507#define PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK 0x1000
3508#define PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT 0xc
3509#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK 0x2000
3510#define PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT 0xd
3511#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK 0x4000
3512#define PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT 0xe
3513#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK 0x8000
3514#define PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT 0xf
3515#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK 0x10000
3516#define PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
3517#define PCIE_STRAP_F3__RESERVED_MASK 0xffffffff
3518#define PCIE_STRAP_F3__RESERVED__SHIFT 0x0
3519#define PCIE_STRAP_F4__RESERVED_MASK 0xffffffff
3520#define PCIE_STRAP_F4__RESERVED__SHIFT 0x0
3521#define PCIE_STRAP_F5__RESERVED_MASK 0xffffffff
3522#define PCIE_STRAP_F5__RESERVED__SHIFT 0x0
3523#define PCIE_STRAP_F6__RESERVED_MASK 0xffffffff
3524#define PCIE_STRAP_F6__RESERVED__SHIFT 0x0
3525#define PCIE_STRAP_F7__RESERVED_MASK 0xffffffff
3526#define PCIE_STRAP_F7__RESERVED__SHIFT 0x0
3527#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK 0xf
3528#define PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT 0x0
3529#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
3530#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
3531#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK 0x1f00
3532#define PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT 0x8
3533#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK 0x2000
3534#define PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0xd
3535#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK 0x4000
3536#define PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT 0xe
3537#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK 0x8000
3538#define PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0xf
3539#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
3540#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
3541#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
3542#define PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
3543#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
3544#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
3545#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
3546#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
3547#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
3548#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
3549#define PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
3550#define PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
3551#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
3552#define PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
3553#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
3554#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
3555#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
3556#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
3557#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
3558#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
3559#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
3560#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
3561#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
3562#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
3563#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
3564#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
3565#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
3566#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
3567#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
3568#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
3569#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
3570#define PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
3571#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
3572#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
3573#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
3574#define PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
3575#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
3576#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
3577#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
3578#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
3579#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
3580#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
3581#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
3582#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
3583#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
3584#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
3585#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x6
3586#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
3587#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x8
3588#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x3
3589#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x10
3590#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x4
3591#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x60
3592#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x5
3593#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0xf80
3594#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x7
3595#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
3596#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
3597#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
3598#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
3599#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
3600#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
3601#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
3602#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
3603#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
3604#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
3605#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
3606#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
3607#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
3608#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
3609#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
3610#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
3611#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
3612#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
3613#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
3614#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
3615#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
3616#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
3617#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
3618#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
3619#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
3620#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
3621#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
3622#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
3623#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
3624#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
3625#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
3626#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
3627#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
3628#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
3629#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
3630#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
3631#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
3632#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
3633#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
3634#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
3635#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
3636#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
3637#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x300
3638#define PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
3639#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x3000
3640#define PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
3641#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0xff0000
3642#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
3643#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xff000000
3644#define PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
3645#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xff
3646#define PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
3647#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x1f
3648#define PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
3649#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xff
3650#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3651#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xff
3652#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3653#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xff
3654#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3655#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xff
3656#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3657#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xff
3658#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3659#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xff
3660#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3661#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xff
3662#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3663#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xff
3664#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
3665#define PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
3666#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
3667#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
3668#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
3669#define PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
3670#define PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
3671#define PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
3672#define PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
3673#define PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
3674#define PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
3675#define PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
3676#define PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
3677#define PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
3678#define PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
3679#define PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
3680#define PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
3681#define PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
3682#define PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
3683#define PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
3684#define PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
3685#define PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
3686#define PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
3687#define PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
3688#define PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
3689#define PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
3690#define PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
3691#define PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
3692#define PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
3693#define PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
3694#define PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
3695#define PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
3696#define PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
3697#define PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
3698#define PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
3699#define PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
3700#define PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
3701#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
3702#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
3703#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
3704#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
3705#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
3706#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
3707#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
3708#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
3709#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
3710#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
3711#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
3712#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
3713#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
3714#define PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
3715#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
3716#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
3717#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
3718#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
3719#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
3720#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
3721#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
3722#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
3723#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
3724#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
3725#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
3726#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
3727#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
3728#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
3729#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
3730#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
3731#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
3732#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
3733#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
3734#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
3735#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
3736#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
3737#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x1000000
3738#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
3739#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x2000000
3740#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
3741#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x4000000
3742#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
3743#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
3744#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
3745#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
3746#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
3747#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
3748#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
3749#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
3750#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
3751#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
3752#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
3753#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
3754#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
3755#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
3756#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
3757#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
3758#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
3759#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
3760#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
3761#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
3762#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
3763#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
3764#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
3765#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
3766#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
3767#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
3768#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
3769#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
3770#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
3771#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
3772#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
3773#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
3774#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
3775#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
3776#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
3777#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
3778#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
3779#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
3780#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
3781#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
3782#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
3783#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
3784#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
3785#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
3786#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
3787#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
3788#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
3789#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
3790#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
3791#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
3792#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
3793#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
3794#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
3795#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
3796#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
3797#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
3798#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
3799#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
3800#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
3801#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
3802#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
3803#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
3804#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
3805#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
3806#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
3807#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
3808#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
3809#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
3810#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
3811#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
3812#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
3813#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
3814#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
3815#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
3816#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
3817#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
3818#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
3819#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
3820#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
3821#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
3822#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
3823#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
3824#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
3825#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
3826#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
3827#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
3828#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
3829#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
3830#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
3831#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
3832#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
3833#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
3834#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
3835#define PCIE_FC_P__PD_CREDITS_MASK 0xff
3836#define PCIE_FC_P__PD_CREDITS__SHIFT 0x0
3837#define PCIE_FC_P__PH_CREDITS_MASK 0xff00
3838#define PCIE_FC_P__PH_CREDITS__SHIFT 0x8
3839#define PCIE_FC_NP__NPD_CREDITS_MASK 0xff
3840#define PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
3841#define PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
3842#define PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
3843#define PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
3844#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
3845#define PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
3846#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
3847#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
3848#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
3849#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
3850#define PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
3851#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
3852#define PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
3853#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
3854#define PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
3855#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
3856#define PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
3857#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
3858#define PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
3859#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
3860#define PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
3861#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
3862#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
3863#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
3864#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
3865#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x1000
3866#define PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0xc
3867#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x2000
3868#define PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0xd
3869#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
3870#define PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
3871#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
3872#define PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
3873#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
3874#define PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
3875#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
3876#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
3877#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
3878#define PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
3879#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
3880#define PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
3881#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
3882#define PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
3883#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
3884#define PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
3885#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
3886#define PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
3887#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
3888#define PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
3889#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
3890#define PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
3891#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
3892#define PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
3893#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
3894#define PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
3895#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
3896#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
3897#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
3898#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
3899#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
3900#define PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
3901#define PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
3902#define PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
3903#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
3904#define PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
3905#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
3906#define PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
3907#define PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
3908#define PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
3909#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
3910#define PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
3911#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
3912#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
3913#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
3914#define PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
3915#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
3916#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
3917#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
3918#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
3919#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
3920#define PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
3921#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
3922#define PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
3923#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
3924#define PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
3925#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
3926#define PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
3927#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
3928#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
3929#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
3930#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
3931#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
3932#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
3933#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
3934#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
3935#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
3936#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
3937#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
3938#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
3939#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
3940#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
3941#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
3942#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
3943#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
3944#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
3945#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
3946#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
3947#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
3948#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
3949#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
3950#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
3951#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
3952#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
3953#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
3954#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
3955#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
3956#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
3957#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
3958#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
3959#define PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
3960#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
3961#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
3962#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
3963#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
3964#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
3965#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
3966#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
3967#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
3968#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
3969#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
3970#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
3971#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
3972#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
3973#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
3974#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
3975#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
3976#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
3977#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
3978#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
3979#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
3980#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
3981#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
3982#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
3983#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
3984#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
3985#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
3986#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
3987#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
3988#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
3989#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
3990#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
3991#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
3992#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
3993#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
3994#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
3995#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
3996#define PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
3997#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
3998#define PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
3999#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
4000#define PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
4001#define PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
4002#define PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
4003#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
4004#define PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
4005#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
4006#define PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
4007#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
4008#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
4009#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
4010#define PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
4011#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
4012#define PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
4013#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
4014#define PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
4015#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
4016#define PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
4017#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
4018#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
4019#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
4020#define PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
4021#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
4022#define PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
4023#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
4024#define PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
4025#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
4026#define PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
4027#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
4028#define PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
4029#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
4030#define PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
4031#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
4032#define PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
4033#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
4034#define PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
4035#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
4036#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
4037#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
4038#define PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
4039#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
4040#define PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
4041#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
4042#define PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
4043#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
4044#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
4045#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
4046#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
4047#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
4048#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
4049#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
4050#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
4051#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
4052#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
4053#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
4054#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
4055#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
4056#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
4057#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
4058#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
4059#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
4060#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
4061#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
4062#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
4063#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
4064#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
4065#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
4066#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
4067#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
4068#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
4069#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
4070#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
4071#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
4072#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
4073#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
4074#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
4075#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
4076#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
4077#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
4078#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
4079#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
4080#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
4081#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
4082#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
4083#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
4084#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
4085#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
4086#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
4087#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
4088#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
4089#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
4090#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
4091#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
4092#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
4093#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
4094#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
4095#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
4096#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
4097#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
4098#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
4099#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
4100#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
4101#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
4102#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
4103#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
4104#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
4105#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
4106#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
4107#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
4108#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
4109#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
4110#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
4111#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
4112#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
4113#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
4114#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
4115#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
4116#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
4117#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
4118#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
4119#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
4120#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
4121#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
4122#define PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
4123#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
4124#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
4125#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
4126#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
4127#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
4128#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
4129#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
4130#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
4131#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
4132#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
4133#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
4134#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
4135#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
4136#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
4137#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
4138#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
4139#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
4140#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
4141#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
4142#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
4143#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
4144#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
4145#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
4146#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
4147#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
4148#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
4149#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
4150#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
4151#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
4152#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
4153#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
4154#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
4155#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
4156#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
4157#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
4158#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
4159#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
4160#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
4161#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
4162#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
4163#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
4164#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
4165#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
4166#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
4167#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
4168#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
4169#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
4170#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
4171#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
4172#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
4173#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
4174#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
4175#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
4176#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
4177#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
4178#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
4179#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
4180#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
4181#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
4182#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
4183#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
4184#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
4185#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
4186#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
4187#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
4188#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
4189#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
4190#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
4191#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
4192#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
4193#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
4194#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
4195#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
4196#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
4197#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
4198#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
4199#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
4200#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
4201#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
4202#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
4203#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
4204#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
4205#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
4206#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
4207#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
4208#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
4209#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
4210#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
4211#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
4212#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
4213#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
4214#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
4215#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
4216#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
4217#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
4218#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
4219#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
4220#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
4221#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
4222#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
4223#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
4224#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
4225#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
4226#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
4227#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
4228#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
4229#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
4230#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
4231#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
4232#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
4233#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
4234#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
4235#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
4236#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
4237#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
4238#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
4239#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
4240#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
4241#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
4242#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
4243#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
4244#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
4245#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
4246#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
4247#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
4248#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
4249#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
4250#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
4251#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
4252#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
4253#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
4254#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
4255#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
4256#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
4257#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
4258#define PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
4259#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
4260#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
4261#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
4262#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
4263#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
4264#define PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
4265#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
4266#define PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
4267#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
4268#define PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
4269#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
4270#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
4271#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
4272#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
4273#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
4274#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
4275#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
4276#define PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
4277#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
4278#define PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
4279#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
4280#define PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
4281#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
4282#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
4283#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
4284#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
4285#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
4286#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
4287#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
4288#define PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
4289#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
4290#define PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
4291#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
4292#define PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
4293#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
4294#define PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
4295#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
4296#define PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
4297#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
4298#define PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
4299#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
4300#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
4301#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
4302#define PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
4303#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
4304#define PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
4305#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
4306#define PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
4307#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
4308#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
4309#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
4310#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
4311#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
4312#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
4313#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
4314#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
4315#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
4316#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
4317#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
4318#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
4319#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
4320#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
4321#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
4322#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
4323#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
4324#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
4325#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
4326#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
4327#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
4328#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
4329#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
4330#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
4331#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
4332#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
4333#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
4334#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
4335#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
4336#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
4337#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
4338#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
4339#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
4340#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
4341#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
4342#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
4343#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
4344#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
4345#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
4346#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
4347#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
4348#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
4349#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
4350#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
4351#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
4352#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
4353#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
4354#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
4355#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
4356#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
4357#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
4358#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
4359#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
4360#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
4361#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
4362#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
4363#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
4364#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
4365#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
4366#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
4367#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
4368#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
4369#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
4370#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
4371#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
4372#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
4373#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
4374#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
4375#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
4376#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
4377#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
4378#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
4379#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
4380#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
4381#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
4382#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
4383#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
4384#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
4385#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
4386#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
4387#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
4388#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
4389#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
4390#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
4391#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
4392#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
4393#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
4394#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
4395#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
4396#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
4397#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
4398#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
4399#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
4400#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
4401#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
4402#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
4403#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
4404#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
4405#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
4406#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
4407#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
4408#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
4409#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
4410#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
4411#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
4412#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
4413#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
4414#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
4415#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
4416#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
4417#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
4418#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
4419#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
4420#define PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
4421#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
4422#define PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
4423#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
4424#define PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
4425#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
4426#define PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
4427#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
4428#define PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
4429#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
4430#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
4431#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
4432#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
4433#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
4434#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
4435#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER_MASK 0x1
4436#define BIF_RFE_SNOOP_REG__REG_SNOOP_ARBITER__SHIFT 0x0
4437#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER_MASK 0x2
4438#define BIF_RFE_SNOOP_REG__REG_SNOOP_ALLMASTER__SHIFT 0x1
4439#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
4440#define BIF_RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
4441#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
4442#define BIF_RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
4443#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
4444#define BIF_RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
4445#define BIF_RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
4446#define BIF_RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
4447#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst_MASK 0x1
4448#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWGBIF_rst__SHIFT 0x0
4449#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst_MASK 0x2
4450#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWGBIF_rst__SHIFT 0x1
4451#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst_MASK 0x4
4452#define BIF_RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWGBIF_rst__SHIFT 0x2
4453#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst_MASK 0x1
4454#define BIF_RFE_MASTER_SOFTRST_TRIGGER__FBU_rst__SHIFT 0x0
4455#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst_MASK 0x2
4456#define BIF_RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWGBIF_rst__SHIFT 0x1
4457#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst_MASK 0x4
4458#define BIF_RFE_MASTER_SOFTRST_TRIGGER__BX_rst__SHIFT 0x2
4459#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd_MASK 0x1
4460#define BIF_PWDN_COMMAND__REG_FBU_pw_cmd__SHIFT 0x0
4461#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd_MASK 0x2
4462#define BIF_PWDN_COMMAND__REG_RWREG_RFEWGBIF_pw_cmd__SHIFT 0x1
4463#define BIF_PWDN_COMMAND__REG_BX_pw_cmd_MASK 0x4
4464#define BIF_PWDN_COMMAND__REG_BX_pw_cmd__SHIFT 0x2
4465#define BIF_PWDN_STATUS__FBU_REG_pw_status_MASK 0x1
4466#define BIF_PWDN_STATUS__FBU_REG_pw_status__SHIFT 0x0
4467#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status_MASK 0x2
4468#define BIF_PWDN_STATUS__RWREG_RFEWGBIF_REG_pw_status__SHIFT 0x1
4469#define BIF_PWDN_STATUS__BX_REG_pw_status_MASK 0x4
4470#define BIF_PWDN_STATUS__BX_REG_pw_status__SHIFT 0x2
4471#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer_MASK 0xff
4472#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkGate_timer__SHIFT 0x0
4473#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer_MASK 0xf00
4474#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_clkSetup_timer__SHIFT 0x8
4475#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer_MASK 0xff0000
4476#define BIF_RFE_MST_FBU_CMDSTATUS__REG_FBU_timeout_timer__SHIFT 0x10
4477#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout_MASK 0x1000000
4478#define BIF_RFE_MST_FBU_CMDSTATUS__FBU_RFE_mstTimeout__SHIFT 0x18
4479#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer_MASK 0xff
4480#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkGate_timer__SHIFT 0x0
4481#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer_MASK 0xf00
4482#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_clkSetup_timer__SHIFT 0x8
4483#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer_MASK 0xff0000
4484#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__REG_RWREG_RFEWGBIF_timeout_timer__SHIFT 0x10
4485#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout_MASK 0x1000000
4486#define BIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS__RWREG_RFEWGBIF_RFE_mstTimeout__SHIFT 0x18
4487#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer_MASK 0xff
4488#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkGate_timer__SHIFT 0x0
4489#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer_MASK 0xf00
4490#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_clkSetup_timer__SHIFT 0x8
4491#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer_MASK 0xff0000
4492#define BIF_RFE_MST_BX_CMDSTATUS__REG_BX_timeout_timer__SHIFT 0x10
4493#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout_MASK 0x1000000
4494#define BIF_RFE_MST_BX_CMDSTATUS__BX_RFE_mstTimeout__SHIFT 0x18
4495#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
4496#define BIF_RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
4497#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x1
4498#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x0
4499#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe
4500#define BIF_RFE_MMCFG_CNTL__CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x1
4501#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN_MASK 0x10
4502#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN__SHIFT 0x4
4503#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL_MASK 0xe0
4504#define BIF_RFE_MMCFG_CNTL__CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL__SHIFT 0x5
4505#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK_MASK 0x1
4506#define BIF_CLOCKS_BITS_IND__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
4507#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN_MASK 0x1
4508#define BIF_LNCNT_RESET_IND__RESET_LNCNT_EN__SHIFT 0x0
4509#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE_MASK 0x1
4510#define LNCNT_CONTROL_IND__LNCNT_ACC_MODE__SHIFT 0x0
4511#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE_MASK 0x6
4512#define LNCNT_CONTROL_IND__LNCNT_REF_TIMEBASE__SHIFT 0x1
4513#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN_MASK 0x1
4514#define NEW_REFCLKB_TIMER_IND__REG_STOP_REFCLK_EN__SHIFT 0x0
4515#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER_MASK 0x1ffffe
4516#define NEW_REFCLKB_TIMER_IND__STOP_REFCLK_TIMER__SHIFT 0x1
4517#define NEW_REFCLKB_TIMER_IND__REFCLK_ON_MASK 0x200000
4518#define NEW_REFCLKB_TIMER_IND__REFCLK_ON__SHIFT 0x15
4519#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER_MASK 0x3ff
4520#define NEW_REFCLKB_TIMER_1_IND__PHY_PLL_PDWN_TIMER__SHIFT 0x0
4521#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN_MASK 0x400
4522#define NEW_REFCLKB_TIMER_1_IND__PLL0_PDNB_EN__SHIFT 0xa
4523#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER_MASK 0x3ff
4524#define BIF_CLK_PDWN_DELAY_TIMER_IND__TIMER__SHIFT 0x0
4525#define BIF_RESET_EN_IND__SOFT_RST_MODE_MASK 0x2
4526#define BIF_RESET_EN_IND__SOFT_RST_MODE__SHIFT 0x1
4527#define BIF_RESET_EN_IND__PHY_RESET_EN_MASK 0x4
4528#define BIF_RESET_EN_IND__PHY_RESET_EN__SHIFT 0x2
4529#define BIF_RESET_EN_IND__COR_RESET_EN_MASK 0x8
4530#define BIF_RESET_EN_IND__COR_RESET_EN__SHIFT 0x3
4531#define BIF_RESET_EN_IND__REG_RESET_EN_MASK 0x10
4532#define BIF_RESET_EN_IND__REG_RESET_EN__SHIFT 0x4
4533#define BIF_RESET_EN_IND__STY_RESET_EN_MASK 0x20
4534#define BIF_RESET_EN_IND__STY_RESET_EN__SHIFT 0x5
4535#define BIF_RESET_EN_IND__CFG_RESET_EN_MASK 0x40
4536#define BIF_RESET_EN_IND__CFG_RESET_EN__SHIFT 0x6
4537#define BIF_RESET_EN_IND__DRV_RESET_EN_MASK 0x80
4538#define BIF_RESET_EN_IND__DRV_RESET_EN__SHIFT 0x7
4539#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN_MASK 0x100
4540#define BIF_RESET_EN_IND__RESET_CFGREG_ONLY_EN__SHIFT 0x8
4541#define BIF_RESET_EN_IND__HOT_RESET_EN_MASK 0x200
4542#define BIF_RESET_EN_IND__HOT_RESET_EN__SHIFT 0x9
4543#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN_MASK 0x400
4544#define BIF_RESET_EN_IND__LINK_DISABLE_RESET_EN__SHIFT 0xa
4545#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN_MASK 0x800
4546#define BIF_RESET_EN_IND__LINK_DOWN_RESET_EN__SHIFT 0xb
4547#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
4548#define BIF_RESET_EN_IND__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
4549#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL_MASK 0xc0000
4550#define BIF_RESET_EN_IND__DRV_RESET_DELAY_SEL__SHIFT 0x12
4551#define BIF_RESET_EN_IND__PIF_RSTB_EN_MASK 0x100000
4552#define BIF_RESET_EN_IND__PIF_RSTB_EN__SHIFT 0x14
4553#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN_MASK 0x200000
4554#define BIF_RESET_EN_IND__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
4555#define BIF_RESET_EN_IND__BIF_COR_RESET_EN_MASK 0x400000
4556#define BIF_RESET_EN_IND__BIF_COR_RESET_EN__SHIFT 0x16
4557#define BIF_RESET_EN_IND__FUNC0_FLR_EN_MASK 0x800000
4558#define BIF_RESET_EN_IND__FUNC0_FLR_EN__SHIFT 0x17
4559#define BIF_RESET_EN_IND__FUNC1_FLR_EN_MASK 0x1000000
4560#define BIF_RESET_EN_IND__FUNC1_FLR_EN__SHIFT 0x18
4561#define BIF_RESET_EN_IND__FUNC2_FLR_EN_MASK 0x2000000
4562#define BIF_RESET_EN_IND__FUNC2_FLR_EN__SHIFT 0x19
4563#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
4564#define BIF_RESET_EN_IND__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
4565#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
4566#define BIF_RESET_EN_IND__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
4567#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
4568#define BIF_RESET_EN_IND__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
4569#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER_MASK 0x7
4570#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL0_ACK_TIMER__SHIFT 0x0
4571#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER_MASK 0x38
4572#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL1_ACK_TIMER__SHIFT 0x3
4573#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER_MASK 0x3c0
4574#define BIF_PIF_TXCLK_SWITCH_TIMER_IND__PLL_SWITCH_TIMER__SHIFT 0x6
4575#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL_MASK 0x1
4576#define BIF_BACO_MSIC_IND__BIF_XTALIN_SEL__SHIFT 0x0
4577#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL_MASK 0x6
4578#define BIF_BACO_MSIC_IND__BACO_LINK_RST_SEL__SHIFT 0x1
4579#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS_MASK 0x10
4580#define BIF_BACO_MSIC_IND__ACPI_BACO_MUX_DIS__SHIFT 0x4
4581#define BIF_RESET_CNTL_IND__STRAP_EN_MASK 0x1
4582#define BIF_RESET_CNTL_IND__STRAP_EN__SHIFT 0x0
4583#define BIF_RESET_CNTL_IND__RST_DONE_MASK 0x2
4584#define BIF_RESET_CNTL_IND__RST_DONE__SHIFT 0x1
4585#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN_MASK 0x4
4586#define BIF_RESET_CNTL_IND__LINK_TRAIN_EN__SHIFT 0x2
4587#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID_MASK 0x8
4588#define BIF_RESET_CNTL_IND__STRAP_ALL_VALID__SHIFT 0x3
4589#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST_MASK 0x100
4590#define BIF_RESET_CNTL_IND__RECAP_STRAP_WARMRST__SHIFT 0x8
4591#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
4592#define BIF_RESET_CNTL_IND__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
4593#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
4594#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
4595#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
4596#define BIF_RFE_CNTL_MISC_IND__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
4597#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
4598#define BIF_RFE_CNTL_MISC_IND__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
4599#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
4600#define BIF_RFE_CNTL_MISC_IND__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
4601#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN_MASK 0x1
4602#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_EN__SHIFT 0x0
4603#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER_MASK 0xffff0000
4604#define BIF_MEM_PG_CNTL_IND__BIF_MEM_SD_TIMER__SHIFT 0x10
4605#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR_MASK 0xffffffff
4606#define NB_GBIF_INDEX__NB_GBIF_IND_ADDR__SHIFT 0x0
4607#define NB_GBIF_DATA__NB_GBIF_DATA_MASK 0xffffffff
4608#define NB_GBIF_DATA__NB_GBIF_DATA__SHIFT 0x0
4609#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK_MASK 0x1
4610#define BIF_CLOCKS_BITS__OBFF_XSL_FORCE_REFCLK__SHIFT 0x0
4611#define BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK 0x1
4612#define BIF_LNCNT_RESET__RESET_LNCNT_EN__SHIFT 0x0
4613#define LNCNT_CONTROL__LNCNT_ACC_MODE_MASK 0x1
4614#define LNCNT_CONTROL__LNCNT_ACC_MODE__SHIFT 0x0
4615#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE_MASK 0x6
4616#define LNCNT_CONTROL__LNCNT_REF_TIMEBASE__SHIFT 0x1
4617#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN_MASK 0x1
4618#define NEW_REFCLKB_TIMER__REG_STOP_REFCLK_EN__SHIFT 0x0
4619#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER_MASK 0x1ffffe
4620#define NEW_REFCLKB_TIMER__STOP_REFCLK_TIMER__SHIFT 0x1
4621#define NEW_REFCLKB_TIMER__REFCLK_ON_MASK 0x200000
4622#define NEW_REFCLKB_TIMER__REFCLK_ON__SHIFT 0x15
4623#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER_MASK 0x3ff
4624#define NEW_REFCLKB_TIMER_1__PHY_PLL_PDWN_TIMER__SHIFT 0x0
4625#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN_MASK 0x400
4626#define NEW_REFCLKB_TIMER_1__PLL0_PDNB_EN__SHIFT 0xa
4627#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x3ff
4628#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x0
4629#define BIF_RESET_EN__SOFT_RST_MODE_MASK 0x2
4630#define BIF_RESET_EN__SOFT_RST_MODE__SHIFT 0x1
4631#define BIF_RESET_EN__PHY_RESET_EN_MASK 0x4
4632#define BIF_RESET_EN__PHY_RESET_EN__SHIFT 0x2
4633#define BIF_RESET_EN__COR_RESET_EN_MASK 0x8
4634#define BIF_RESET_EN__COR_RESET_EN__SHIFT 0x3
4635#define BIF_RESET_EN__REG_RESET_EN_MASK 0x10
4636#define BIF_RESET_EN__REG_RESET_EN__SHIFT 0x4
4637#define BIF_RESET_EN__STY_RESET_EN_MASK 0x20
4638#define BIF_RESET_EN__STY_RESET_EN__SHIFT 0x5
4639#define BIF_RESET_EN__CFG_RESET_EN_MASK 0x40
4640#define BIF_RESET_EN__CFG_RESET_EN__SHIFT 0x6
4641#define BIF_RESET_EN__DRV_RESET_EN_MASK 0x80
4642#define BIF_RESET_EN__DRV_RESET_EN__SHIFT 0x7
4643#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN_MASK 0x100
4644#define BIF_RESET_EN__RESET_CFGREG_ONLY_EN__SHIFT 0x8
4645#define BIF_RESET_EN__HOT_RESET_EN_MASK 0x200
4646#define BIF_RESET_EN__HOT_RESET_EN__SHIFT 0x9
4647#define BIF_RESET_EN__LINK_DISABLE_RESET_EN_MASK 0x400
4648#define BIF_RESET_EN__LINK_DISABLE_RESET_EN__SHIFT 0xa
4649#define BIF_RESET_EN__LINK_DOWN_RESET_EN_MASK 0x800
4650#define BIF_RESET_EN__LINK_DOWN_RESET_EN__SHIFT 0xb
4651#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH_MASK 0x3f000
4652#define BIF_RESET_EN__CFG_RESET_PULSE_WIDTH__SHIFT 0xc
4653#define BIF_RESET_EN__DRV_RESET_DELAY_SEL_MASK 0xc0000
4654#define BIF_RESET_EN__DRV_RESET_DELAY_SEL__SHIFT 0x12
4655#define BIF_RESET_EN__PIF_RSTB_EN_MASK 0x100000
4656#define BIF_RESET_EN__PIF_RSTB_EN__SHIFT 0x14
4657#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN_MASK 0x200000
4658#define BIF_RESET_EN__PIF_STRAP_ALLVALID_EN__SHIFT 0x15
4659#define BIF_RESET_EN__BIF_COR_RESET_EN_MASK 0x400000
4660#define BIF_RESET_EN__BIF_COR_RESET_EN__SHIFT 0x16
4661#define BIF_RESET_EN__FUNC0_FLR_EN_MASK 0x800000
4662#define BIF_RESET_EN__FUNC0_FLR_EN__SHIFT 0x17
4663#define BIF_RESET_EN__FUNC1_FLR_EN_MASK 0x1000000
4664#define BIF_RESET_EN__FUNC1_FLR_EN__SHIFT 0x18
4665#define BIF_RESET_EN__FUNC2_FLR_EN_MASK 0x2000000
4666#define BIF_RESET_EN__FUNC2_FLR_EN__SHIFT 0x19
4667#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL_MASK 0xc000000
4668#define BIF_RESET_EN__FUNC0_RESET_DELAY_SEL__SHIFT 0x1a
4669#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL_MASK 0x30000000
4670#define BIF_RESET_EN__FUNC1_RESET_DELAY_SEL__SHIFT 0x1c
4671#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL_MASK 0xc0000000
4672#define BIF_RESET_EN__FUNC2_RESET_DELAY_SEL__SHIFT 0x1e
4673#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER_MASK 0x7
4674#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL0_ACK_TIMER__SHIFT 0x0
4675#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER_MASK 0x38
4676#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL1_ACK_TIMER__SHIFT 0x3
4677#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER_MASK 0x3c0
4678#define BIF_PIF_TXCLK_SWITCH_TIMER__PLL_SWITCH_TIMER__SHIFT 0x6
4679#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x1
4680#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x0
4681#define BIF_BACO_MSIC__BACO_LINK_RST_SEL_MASK 0x6
4682#define BIF_BACO_MSIC__BACO_LINK_RST_SEL__SHIFT 0x1
4683#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS_MASK 0x10
4684#define BIF_BACO_MSIC__ACPI_BACO_MUX_DIS__SHIFT 0x4
4685#define BIF_RESET_CNTL__STRAP_EN_MASK 0x1
4686#define BIF_RESET_CNTL__STRAP_EN__SHIFT 0x0
4687#define BIF_RESET_CNTL__RST_DONE_MASK 0x2
4688#define BIF_RESET_CNTL__RST_DONE__SHIFT 0x1
4689#define BIF_RESET_CNTL__LINK_TRAIN_EN_MASK 0x4
4690#define BIF_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x2
4691#define BIF_RESET_CNTL__STRAP_ALL_VALID_MASK 0x8
4692#define BIF_RESET_CNTL__STRAP_ALL_VALID__SHIFT 0x3
4693#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST_MASK 0x100
4694#define BIF_RESET_CNTL__RECAP_STRAP_WARMRST__SHIFT 0x8
4695#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS_MASK 0x200
4696#define BIF_RESET_CNTL__HOLD_LKTRN_WARMRST_DIS__SHIFT 0x9
4697#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode_MASK 0x1
4698#define BIF_RFE_CNTL_MISC__ADAPT_pif0_bu_reg_accessMode__SHIFT 0x0
4699#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode_MASK 0x2
4700#define BIF_RFE_CNTL_MISC__ADAPT_pif1_bu_reg_accessMode__SHIFT 0x1
4701#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode_MASK 0x4
4702#define BIF_RFE_CNTL_MISC__ADAPT_pwreg_bu_reg_accessMode__SHIFT 0x2
4703#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode_MASK 0x8
4704#define BIF_RFE_CNTL_MISC__ADAPT_pciecore0_bu_reg_accessMode__SHIFT 0x3
4705#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN_MASK 0x1
4706#define BIF_MEM_PG_CNTL__BIF_MEM_SD_EN__SHIFT 0x0
4707#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER_MASK 0xffff0000
4708#define BIF_MEM_PG_CNTL__BIF_MEM_SD_TIMER__SHIFT 0x10
4709#define C_PCIE_P_INDEX__PCIE_INDEX_MASK 0xffffffff
4710#define C_PCIE_P_INDEX__PCIE_INDEX__SHIFT 0x0
4711#define C_PCIE_P_DATA__PCIE_DATA_MASK 0xffffffff
4712#define C_PCIE_P_DATA__PCIE_DATA__SHIFT 0x0
4713#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
4714#define D2F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
4715#define D2F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
4716#define D2F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
4717#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
4718#define D2F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
4719#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
4720#define D2F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
4721#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
4722#define D2F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
4723#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
4724#define D2F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
4725#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
4726#define D2F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
4727#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
4728#define D2F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
4729#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
4730#define D2F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
4731#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
4732#define D2F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
4733#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
4734#define D2F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
4735#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
4736#define D2F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
4737#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
4738#define D2F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
4739#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
4740#define D2F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
4741#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
4742#define D2F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
4743#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
4744#define D2F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
4745#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
4746#define D2F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
4747#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
4748#define D2F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
4749#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
4750#define D2F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
4751#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
4752#define D2F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
4753#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
4754#define D2F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
4755#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
4756#define D2F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
4757#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
4758#define D2F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
4759#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
4760#define D2F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
4761#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
4762#define D2F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
4763#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
4764#define D2F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
4765#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
4766#define D2F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
4767#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
4768#define D2F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
4769#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
4770#define D2F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
4771#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
4772#define D2F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
4773#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
4774#define D2F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
4775#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
4776#define D2F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
4777#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
4778#define D2F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
4779#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
4780#define D2F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
4781#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
4782#define D2F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
4783#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
4784#define D2F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
4785#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
4786#define D2F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
4787#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
4788#define D2F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
4789#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
4790#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
4791#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
4792#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
4793#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
4794#define D2F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
4795#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
4796#define D2F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
4797#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
4798#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
4799#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
4800#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
4801#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
4802#define D2F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
4803#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
4804#define D2F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
4805#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
4806#define D2F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
4807#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
4808#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
4809#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
4810#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
4811#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
4812#define D2F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
4813#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
4814#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
4815#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
4816#define D2F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
4817#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
4818#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
4819#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
4820#define D2F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
4821#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
4822#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
4823#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
4824#define D2F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
4825#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
4826#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
4827#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
4828#define D2F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
4829#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
4830#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
4831#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
4832#define D2F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
4833#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
4834#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
4835#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
4836#define D2F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
4837#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
4838#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
4839#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
4840#define D2F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
4841#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
4842#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
4843#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
4844#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
4845#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
4846#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
4847#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
4848#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
4849#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
4850#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
4851#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
4852#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
4853#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
4854#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
4855#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
4856#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
4857#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
4858#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
4859#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
4860#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
4861#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
4862#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
4863#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
4864#define D2F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
4865#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
4866#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
4867#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
4868#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
4869#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
4870#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
4871#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
4872#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
4873#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
4874#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
4875#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
4876#define D2F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
4877#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
4878#define D2F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
4879#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
4880#define D2F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
4881#define D2F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
4882#define D2F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
4883#define D2F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
4884#define D2F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
4885#define D2F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
4886#define D2F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
4887#define D2F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
4888#define D2F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
4889#define D2F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
4890#define D2F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
4891#define D2F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
4892#define D2F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
4893#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
4894#define D2F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
4895#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
4896#define D2F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
4897#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
4898#define D2F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
4899#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
4900#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
4901#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
4902#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
4903#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
4904#define D2F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
4905#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
4906#define D2F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
4907#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
4908#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
4909#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
4910#define D2F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
4911#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
4912#define D2F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
4913#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
4914#define D2F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
4915#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
4916#define D2F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
4917#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
4918#define D2F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
4919#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
4920#define D2F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
4921#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
4922#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
4923#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
4924#define D2F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
4925#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
4926#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
4927#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
4928#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
4929#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
4930#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
4931#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
4932#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
4933#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
4934#define D2F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
4935#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
4936#define D2F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
4937#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
4938#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
4939#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
4940#define D2F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
4941#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
4942#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
4943#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
4944#define D2F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
4945#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
4946#define D2F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
4947#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
4948#define D2F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
4949#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
4950#define D2F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
4951#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
4952#define D2F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
4953#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
4954#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
4955#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
4956#define D2F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
4957#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
4958#define D2F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
4959#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
4960#define D2F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
4961#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
4962#define D2F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
4963#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
4964#define D2F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
4965#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
4966#define D2F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
4967#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
4968#define D2F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
4969#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
4970#define D2F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
4971#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
4972#define D2F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
4973#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
4974#define D2F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
4975#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
4976#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
4977#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
4978#define D2F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
4979#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
4980#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
4981#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
4982#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
4983#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
4984#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
4985#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
4986#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
4987#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
4988#define D2F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
4989#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
4990#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
4991#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
4992#define D2F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
4993#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
4994#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
4995#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
4996#define D2F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
4997#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
4998#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
4999#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
5000#define D2F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
5001#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
5002#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
5003#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
5004#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
5005#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
5006#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
5007#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
5008#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
5009#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
5010#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
5011#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
5012#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
5013#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
5014#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
5015#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
5016#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
5017#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
5018#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
5019#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
5020#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
5021#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
5022#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
5023#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
5024#define D2F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
5025#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
5026#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
5027#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
5028#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
5029#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
5030#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
5031#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
5032#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
5033#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
5034#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
5035#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
5036#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
5037#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
5038#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
5039#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
5040#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
5041#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
5042#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
5043#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
5044#define D2F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
5045#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
5046#define D2F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
5047#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
5048#define D2F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
5049#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
5050#define D2F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
5051#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
5052#define D2F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
5053#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
5054#define D2F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
5055#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
5056#define D2F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
5057#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
5058#define D2F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
5059#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
5060#define D2F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
5061#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
5062#define D2F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
5063#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
5064#define D2F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
5065#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
5066#define D2F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
5067#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
5068#define D2F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
5069#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
5070#define D2F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
5071#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
5072#define D2F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
5073#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
5074#define D2F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
5075#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
5076#define D2F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
5077#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
5078#define D2F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
5079#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
5080#define D2F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
5081#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
5082#define D2F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
5083#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
5084#define D2F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
5085#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
5086#define D2F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
5087#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
5088#define D2F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
5089#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
5090#define D2F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
5091#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
5092#define D2F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
5093#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
5094#define D2F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
5095#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
5096#define D2F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
5097#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
5098#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
5099#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
5100#define D2F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
5101#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
5102#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
5103#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
5104#define D2F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
5105#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
5106#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
5107#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
5108#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
5109#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
5110#define D2F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
5111#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
5112#define D2F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
5113#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
5114#define D2F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
5115#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
5116#define D2F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
5117#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
5118#define D2F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
5119#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
5120#define D2F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
5121#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
5122#define D2F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
5123#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
5124#define D2F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
5125#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
5126#define D2F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
5127#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
5128#define D2F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
5129#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
5130#define D2F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
5131#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
5132#define D2F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
5133#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
5134#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
5135#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
5136#define D2F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
5137#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
5138#define D2F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
5139#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
5140#define D2F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
5141#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
5142#define D2F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
5143#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
5144#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
5145#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
5146#define D2F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
5147#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
5148#define D2F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
5149#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
5150#define D2F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
5151#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
5152#define D2F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
5153#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
5154#define D2F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
5155#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
5156#define D2F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
5157#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
5158#define D2F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
5159#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
5160#define D2F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
5161#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
5162#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
5163#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
5164#define D2F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
5165#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
5166#define D2F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
5167#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
5168#define D2F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
5169#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
5170#define D2F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
5171#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
5172#define D2F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
5173#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
5174#define D2F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
5175#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
5176#define D2F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
5177#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
5178#define D2F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
5179#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
5180#define D2F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
5181#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
5182#define D2F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
5183#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
5184#define D2F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
5185#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
5186#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
5187#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
5188#define D2F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
5189#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
5190#define D2F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
5191#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
5192#define D2F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
5193#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
5194#define D2F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
5195#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
5196#define D2F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
5197#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
5198#define D2F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
5199#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
5200#define D2F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
5201#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
5202#define D2F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
5203#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
5204#define D2F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
5205#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
5206#define D2F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
5207#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
5208#define D2F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
5209#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
5210#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
5211#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
5212#define D2F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
5213#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
5214#define D2F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
5215#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
5216#define D2F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
5217#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
5218#define D2F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
5219#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
5220#define D2F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
5221#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
5222#define D2F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
5223#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
5224#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
5225#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
5226#define D2F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
5227#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
5228#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
5229#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
5230#define D2F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
5231#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
5232#define D2F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
5233#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
5234#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
5235#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
5236#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
5237#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
5238#define D2F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
5239#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
5240#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
5241#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
5242#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
5243#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
5244#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
5245#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
5246#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
5247#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
5248#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
5249#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
5250#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
5251#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
5252#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
5253#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
5254#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
5255#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
5256#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
5257#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
5258#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
5259#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
5260#define D2F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
5261#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
5262#define D2F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
5263#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
5264#define D2F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
5265#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
5266#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
5267#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
5268#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
5269#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
5270#define D2F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
5271#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
5272#define D2F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
5273#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
5274#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
5275#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
5276#define D2F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
5277#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
5278#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
5279#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
5280#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
5281#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
5282#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
5283#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
5284#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
5285#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
5286#define D2F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
5287#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
5288#define D2F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
5289#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
5290#define D2F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
5291#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
5292#define D2F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
5293#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
5294#define D2F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
5295#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
5296#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
5297#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
5298#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
5299#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
5300#define D2F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
5301#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
5302#define D2F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
5303#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
5304#define D2F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
5305#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
5306#define D2F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
5307#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
5308#define D2F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
5309#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
5310#define D2F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
5311#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
5312#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
5313#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
5314#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
5315#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
5316#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
5317#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
5318#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
5319#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
5320#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
5321#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
5322#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
5323#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
5324#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
5325#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
5326#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
5327#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
5328#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
5329#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
5330#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
5331#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
5332#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
5333#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
5334#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
5335#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
5336#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
5337#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
5338#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
5339#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
5340#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
5341#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
5342#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
5343#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
5344#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
5345#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
5346#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
5347#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
5348#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
5349#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
5350#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
5351#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
5352#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
5353#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
5354#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
5355#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
5356#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
5357#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
5358#define D2F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
5359#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
5360#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
5361#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
5362#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
5363#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
5364#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
5365#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
5366#define D2F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
5367#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
5368#define D2F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
5369#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
5370#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
5371#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
5372#define D2F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
5373#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
5374#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
5375#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
5376#define D2F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
5377#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
5378#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
5379#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
5380#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
5381#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
5382#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
5383#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
5384#define D2F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
5385#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
5386#define D2F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
5387#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
5388#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
5389#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
5390#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
5391#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
5392#define D2F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
5393#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
5394#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
5395#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
5396#define D2F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
5397#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
5398#define D2F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
5399#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
5400#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
5401#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
5402#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
5403#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
5404#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
5405#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
5406#define D2F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
5407#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
5408#define D2F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
5409#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
5410#define D2F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
5411#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
5412#define D2F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
5413#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
5414#define D2F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
5415#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
5416#define D2F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
5417#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
5418#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
5419#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
5420#define D2F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
5421#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
5422#define D2F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
5423#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
5424#define D2F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
5425#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
5426#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
5427#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
5428#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
5429#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
5430#define D2F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
5431#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
5432#define D2F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
5433#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
5434#define D2F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
5435#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
5436#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
5437#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
5438#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
5439#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
5440#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
5441#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
5442#define D2F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
5443#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
5444#define D2F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
5445#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
5446#define D2F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
5447#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
5448#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
5449#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
5450#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
5451#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
5452#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
5453#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
5454#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
5455#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
5456#define D2F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
5457#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
5458#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
5459#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
5460#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
5461#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
5462#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
5463#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
5464#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
5465#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
5466#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
5467#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
5468#define D2F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
5469#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
5470#define D2F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
5471#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
5472#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
5473#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
5474#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
5475#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
5476#define D2F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
5477#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
5478#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
5479#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
5480#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
5481#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
5482#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
5483#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
5484#define D2F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
5485#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
5486#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
5487#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
5488#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
5489#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
5490#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
5491#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
5492#define D2F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
5493#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
5494#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
5495#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
5496#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
5497#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
5498#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
5499#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
5500#define D2F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
5501#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
5502#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
5503#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
5504#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
5505#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
5506#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
5507#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
5508#define D2F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
5509#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
5510#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
5511#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
5512#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
5513#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
5514#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
5515#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
5516#define D2F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
5517#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
5518#define D2F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
5519#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
5520#define D2F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
5521#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
5522#define D2F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
5523#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
5524#define D2F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
5525#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
5526#define D2F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
5527#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
5528#define D2F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
5529#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
5530#define D2F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
5531#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
5532#define D2F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
5533#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
5534#define D2F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
5535#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
5536#define D2F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
5537#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
5538#define D2F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
5539#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
5540#define D2F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
5541#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
5542#define D2F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
5543#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
5544#define D2F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
5545#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
5546#define D2F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
5547#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
5548#define D2F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
5549#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
5550#define D2F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
5551#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
5552#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
5553#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
5554#define D2F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
5555#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
5556#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
5557#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
5558#define D2F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
5559#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
5560#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
5561#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
5562#define D2F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
5563#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
5564#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
5565#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
5566#define D2F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
5567#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
5568#define D2F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
5569#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
5570#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
5571#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
5572#define D2F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
5573#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
5574#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
5575#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
5576#define D2F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
5577#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
5578#define D2F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
5579#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
5580#define D2F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
5581#define D2F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
5582#define D2F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
5583#define D2F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
5584#define D2F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
5585#define D2F1_COMMAND__IO_ACCESS_EN_MASK 0x1
5586#define D2F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
5587#define D2F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
5588#define D2F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
5589#define D2F1_COMMAND__BUS_MASTER_EN_MASK 0x4
5590#define D2F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
5591#define D2F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
5592#define D2F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
5593#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
5594#define D2F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
5595#define D2F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
5596#define D2F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
5597#define D2F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
5598#define D2F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
5599#define D2F1_COMMAND__AD_STEPPING_MASK 0x80
5600#define D2F1_COMMAND__AD_STEPPING__SHIFT 0x7
5601#define D2F1_COMMAND__SERR_EN_MASK 0x100
5602#define D2F1_COMMAND__SERR_EN__SHIFT 0x8
5603#define D2F1_COMMAND__FAST_B2B_EN_MASK 0x200
5604#define D2F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
5605#define D2F1_COMMAND__INT_DIS_MASK 0x400
5606#define D2F1_COMMAND__INT_DIS__SHIFT 0xa
5607#define D2F1_STATUS__INT_STATUS_MASK 0x80000
5608#define D2F1_STATUS__INT_STATUS__SHIFT 0x13
5609#define D2F1_STATUS__CAP_LIST_MASK 0x100000
5610#define D2F1_STATUS__CAP_LIST__SHIFT 0x14
5611#define D2F1_STATUS__PCI_66_EN_MASK 0x200000
5612#define D2F1_STATUS__PCI_66_EN__SHIFT 0x15
5613#define D2F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
5614#define D2F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
5615#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
5616#define D2F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
5617#define D2F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
5618#define D2F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
5619#define D2F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
5620#define D2F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
5621#define D2F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
5622#define D2F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
5623#define D2F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
5624#define D2F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
5625#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
5626#define D2F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
5627#define D2F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
5628#define D2F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
5629#define D2F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
5630#define D2F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
5631#define D2F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
5632#define D2F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
5633#define D2F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
5634#define D2F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
5635#define D2F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
5636#define D2F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
5637#define D2F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
5638#define D2F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
5639#define D2F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
5640#define D2F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
5641#define D2F1_LATENCY__LATENCY_TIMER_MASK 0xff00
5642#define D2F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
5643#define D2F1_HEADER__HEADER_TYPE_MASK 0x7f0000
5644#define D2F1_HEADER__HEADER_TYPE__SHIFT 0x10
5645#define D2F1_HEADER__DEVICE_TYPE_MASK 0x800000
5646#define D2F1_HEADER__DEVICE_TYPE__SHIFT 0x17
5647#define D2F1_BIST__BIST_COMP_MASK 0xf000000
5648#define D2F1_BIST__BIST_COMP__SHIFT 0x18
5649#define D2F1_BIST__BIST_STRT_MASK 0x40000000
5650#define D2F1_BIST__BIST_STRT__SHIFT 0x1e
5651#define D2F1_BIST__BIST_CAP_MASK 0x80000000
5652#define D2F1_BIST__BIST_CAP__SHIFT 0x1f
5653#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
5654#define D2F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
5655#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
5656#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
5657#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
5658#define D2F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
5659#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
5660#define D2F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
5661#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
5662#define D2F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
5663#define D2F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
5664#define D2F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
5665#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
5666#define D2F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
5667#define D2F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
5668#define D2F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
5669#define D2F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
5670#define D2F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
5671#define D2F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
5672#define D2F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
5673#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
5674#define D2F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
5675#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
5676#define D2F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
5677#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
5678#define D2F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
5679#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
5680#define D2F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
5681#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
5682#define D2F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
5683#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
5684#define D2F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
5685#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
5686#define D2F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
5687#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
5688#define D2F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
5689#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
5690#define D2F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
5691#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
5692#define D2F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
5693#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
5694#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
5695#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
5696#define D2F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
5697#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
5698#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
5699#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
5700#define D2F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
5701#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
5702#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
5703#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
5704#define D2F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
5705#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
5706#define D2F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
5707#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
5708#define D2F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
5709#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
5710#define D2F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
5711#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
5712#define D2F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
5713#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
5714#define D2F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
5715#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
5716#define D2F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
5717#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
5718#define D2F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
5719#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
5720#define D2F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
5721#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
5722#define D2F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
5723#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
5724#define D2F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
5725#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
5726#define D2F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
5727#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
5728#define D2F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
5729#define D2F1_CAP_PTR__CAP_PTR_MASK 0xff
5730#define D2F1_CAP_PTR__CAP_PTR__SHIFT 0x0
5731#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
5732#define D2F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
5733#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
5734#define D2F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
5735#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
5736#define D2F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
5737#define D2F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
5738#define D2F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
5739#define D2F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
5740#define D2F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
5741#define D2F1_PMI_CAP__VERSION_MASK 0x70000
5742#define D2F1_PMI_CAP__VERSION__SHIFT 0x10
5743#define D2F1_PMI_CAP__PME_CLOCK_MASK 0x80000
5744#define D2F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
5745#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
5746#define D2F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
5747#define D2F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
5748#define D2F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
5749#define D2F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
5750#define D2F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
5751#define D2F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
5752#define D2F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
5753#define D2F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
5754#define D2F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
5755#define D2F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
5756#define D2F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
5757#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
5758#define D2F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
5759#define D2F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
5760#define D2F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
5761#define D2F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
5762#define D2F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
5763#define D2F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
5764#define D2F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
5765#define D2F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
5766#define D2F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
5767#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
5768#define D2F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
5769#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
5770#define D2F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
5771#define D2F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
5772#define D2F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
5773#define D2F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
5774#define D2F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
5775#define D2F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
5776#define D2F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
5777#define D2F1_PCIE_CAP__VERSION_MASK 0xf0000
5778#define D2F1_PCIE_CAP__VERSION__SHIFT 0x10
5779#define D2F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
5780#define D2F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
5781#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
5782#define D2F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
5783#define D2F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
5784#define D2F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
5785#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
5786#define D2F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
5787#define D2F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
5788#define D2F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
5789#define D2F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
5790#define D2F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
5791#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
5792#define D2F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
5793#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
5794#define D2F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
5795#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
5796#define D2F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
5797#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
5798#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
5799#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
5800#define D2F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
5801#define D2F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
5802#define D2F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
5803#define D2F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
5804#define D2F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
5805#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
5806#define D2F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
5807#define D2F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
5808#define D2F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
5809#define D2F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
5810#define D2F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
5811#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
5812#define D2F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
5813#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
5814#define D2F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
5815#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
5816#define D2F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
5817#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
5818#define D2F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
5819#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
5820#define D2F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
5821#define D2F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
5822#define D2F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
5823#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
5824#define D2F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
5825#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
5826#define D2F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
5827#define D2F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
5828#define D2F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
5829#define D2F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
5830#define D2F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
5831#define D2F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
5832#define D2F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
5833#define D2F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
5834#define D2F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
5835#define D2F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
5836#define D2F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
5837#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
5838#define D2F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
5839#define D2F1_LINK_CAP__LINK_SPEED_MASK 0xf
5840#define D2F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
5841#define D2F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
5842#define D2F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
5843#define D2F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
5844#define D2F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
5845#define D2F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
5846#define D2F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
5847#define D2F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
5848#define D2F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
5849#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
5850#define D2F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
5851#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
5852#define D2F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
5853#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
5854#define D2F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
5855#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
5856#define D2F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
5857#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
5858#define D2F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
5859#define D2F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
5860#define D2F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
5861#define D2F1_LINK_CNTL__PM_CONTROL_MASK 0x3
5862#define D2F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
5863#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
5864#define D2F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
5865#define D2F1_LINK_CNTL__LINK_DIS_MASK 0x10
5866#define D2F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
5867#define D2F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
5868#define D2F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
5869#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
5870#define D2F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
5871#define D2F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
5872#define D2F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
5873#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
5874#define D2F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
5875#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
5876#define D2F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
5877#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
5878#define D2F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
5879#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
5880#define D2F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
5881#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
5882#define D2F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
5883#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
5884#define D2F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
5885#define D2F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
5886#define D2F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
5887#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
5888#define D2F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
5889#define D2F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
5890#define D2F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
5891#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
5892#define D2F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
5893#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
5894#define D2F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
5895#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
5896#define D2F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
5897#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
5898#define D2F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
5899#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
5900#define D2F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
5901#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
5902#define D2F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
5903#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
5904#define D2F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
5905#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
5906#define D2F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
5907#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
5908#define D2F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
5909#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
5910#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
5911#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
5912#define D2F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
5913#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
5914#define D2F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
5915#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
5916#define D2F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
5917#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
5918#define D2F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
5919#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
5920#define D2F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
5921#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
5922#define D2F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
5923#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
5924#define D2F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
5925#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
5926#define D2F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
5927#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
5928#define D2F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
5929#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
5930#define D2F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
5931#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
5932#define D2F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
5933#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
5934#define D2F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
5935#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
5936#define D2F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
5937#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
5938#define D2F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
5939#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
5940#define D2F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
5941#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
5942#define D2F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
5943#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
5944#define D2F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
5945#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
5946#define D2F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
5947#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
5948#define D2F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
5949#define D2F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
5950#define D2F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
5951#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
5952#define D2F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
5953#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
5954#define D2F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
5955#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
5956#define D2F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
5957#define D2F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
5958#define D2F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
5959#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
5960#define D2F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
5961#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
5962#define D2F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
5963#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
5964#define D2F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
5965#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
5966#define D2F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
5967#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
5968#define D2F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
5969#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
5970#define D2F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
5971#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
5972#define D2F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
5973#define D2F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
5974#define D2F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
5975#define D2F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
5976#define D2F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
5977#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
5978#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
5979#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
5980#define D2F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
5981#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
5982#define D2F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
5983#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
5984#define D2F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
5985#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
5986#define D2F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
5987#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
5988#define D2F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
5989#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
5990#define D2F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
5991#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
5992#define D2F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
5993#define D2F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
5994#define D2F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
5995#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
5996#define D2F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
5997#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
5998#define D2F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
5999#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
6000#define D2F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
6001#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
6002#define D2F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
6003#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
6004#define D2F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
6005#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
6006#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
6007#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
6008#define D2F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
6009#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
6010#define D2F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
6011#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
6012#define D2F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
6013#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
6014#define D2F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
6015#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
6016#define D2F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
6017#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
6018#define D2F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
6019#define D2F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
6020#define D2F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
6021#define D2F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
6022#define D2F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
6023#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
6024#define D2F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
6025#define D2F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
6026#define D2F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
6027#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
6028#define D2F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
6029#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
6030#define D2F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
6031#define D2F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
6032#define D2F1_LINK_CAP2__RESERVED__SHIFT 0x9
6033#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
6034#define D2F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
6035#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
6036#define D2F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
6037#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
6038#define D2F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
6039#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
6040#define D2F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
6041#define D2F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
6042#define D2F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
6043#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
6044#define D2F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
6045#define D2F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
6046#define D2F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
6047#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
6048#define D2F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
6049#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
6050#define D2F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
6051#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
6052#define D2F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
6053#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
6054#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
6055#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
6056#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
6057#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
6058#define D2F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
6059#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
6060#define D2F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
6061#define D2F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
6062#define D2F1_SLOT_CAP2__RESERVED__SHIFT 0x0
6063#define D2F1_SLOT_CNTL2__RESERVED_MASK 0xffff
6064#define D2F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
6065#define D2F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
6066#define D2F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
6067#define D2F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
6068#define D2F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
6069#define D2F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
6070#define D2F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
6071#define D2F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
6072#define D2F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
6073#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
6074#define D2F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
6075#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
6076#define D2F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
6077#define D2F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
6078#define D2F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
6079#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
6080#define D2F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
6081#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
6082#define D2F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
6083#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
6084#define D2F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
6085#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
6086#define D2F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
6087#define D2F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
6088#define D2F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
6089#define D2F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
6090#define D2F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
6091#define D2F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
6092#define D2F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
6093#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
6094#define D2F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
6095#define D2F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
6096#define D2F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
6097#define D2F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
6098#define D2F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
6099#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
6100#define D2F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
6101#define D2F1_MSI_MAP_CAP__EN_MASK 0x10000
6102#define D2F1_MSI_MAP_CAP__EN__SHIFT 0x10
6103#define D2F1_MSI_MAP_CAP__FIXD_MASK 0x20000
6104#define D2F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
6105#define D2F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
6106#define D2F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
6107#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
6108#define D2F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
6109#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
6110#define D2F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
6111#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6112#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6113#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6114#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6115#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6116#define D2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6117#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
6118#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
6119#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
6120#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
6121#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
6122#define D2F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
6123#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
6124#define D2F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
6125#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
6126#define D2F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
6127#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6128#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6129#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6130#define D2F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6131#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6132#define D2F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6133#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
6134#define D2F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
6135#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
6136#define D2F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
6137#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
6138#define D2F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
6139#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
6140#define D2F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
6141#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
6142#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
6143#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
6144#define D2F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
6145#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
6146#define D2F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
6147#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
6148#define D2F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
6149#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
6150#define D2F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
6151#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
6152#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
6153#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
6154#define D2F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
6155#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
6156#define D2F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
6157#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
6158#define D2F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
6159#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
6160#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
6161#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
6162#define D2F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
6163#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
6164#define D2F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
6165#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
6166#define D2F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
6167#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
6168#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
6169#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
6170#define D2F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
6171#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
6172#define D2F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
6173#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
6174#define D2F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
6175#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
6176#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
6177#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
6178#define D2F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
6179#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
6180#define D2F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
6181#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
6182#define D2F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
6183#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
6184#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
6185#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
6186#define D2F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
6187#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
6188#define D2F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
6189#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
6190#define D2F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
6191#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
6192#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
6193#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
6194#define D2F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
6195#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
6196#define D2F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
6197#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
6198#define D2F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
6199#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6200#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6201#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6202#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6203#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6204#define D2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6205#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
6206#define D2F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
6207#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
6208#define D2F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
6209#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6210#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6211#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6212#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6213#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6214#define D2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6215#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
6216#define D2F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
6217#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
6218#define D2F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
6219#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
6220#define D2F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
6221#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
6222#define D2F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
6223#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
6224#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
6225#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
6226#define D2F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
6227#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
6228#define D2F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
6229#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
6230#define D2F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
6231#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
6232#define D2F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
6233#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
6234#define D2F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
6235#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
6236#define D2F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
6237#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
6238#define D2F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
6239#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
6240#define D2F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
6241#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
6242#define D2F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
6243#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
6244#define D2F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
6245#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
6246#define D2F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
6247#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
6248#define D2F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
6249#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
6250#define D2F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
6251#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
6252#define D2F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
6253#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
6254#define D2F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
6255#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
6256#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
6257#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
6258#define D2F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
6259#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
6260#define D2F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
6261#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
6262#define D2F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
6263#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
6264#define D2F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
6265#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
6266#define D2F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
6267#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
6268#define D2F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
6269#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
6270#define D2F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
6271#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
6272#define D2F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
6273#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
6274#define D2F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
6275#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
6276#define D2F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
6277#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
6278#define D2F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
6279#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
6280#define D2F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
6281#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
6282#define D2F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
6283#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
6284#define D2F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
6285#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
6286#define D2F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
6287#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
6288#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
6289#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
6290#define D2F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
6291#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
6292#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
6293#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
6294#define D2F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
6295#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
6296#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
6297#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
6298#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
6299#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
6300#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
6301#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
6302#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
6303#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
6304#define D2F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
6305#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
6306#define D2F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
6307#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
6308#define D2F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
6309#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
6310#define D2F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
6311#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
6312#define D2F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
6313#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
6314#define D2F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
6315#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
6316#define D2F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
6317#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
6318#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
6319#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
6320#define D2F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
6321#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
6322#define D2F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
6323#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
6324#define D2F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
6325#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
6326#define D2F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
6327#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
6328#define D2F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
6329#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
6330#define D2F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
6331#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
6332#define D2F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
6333#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
6334#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
6335#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
6336#define D2F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
6337#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
6338#define D2F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
6339#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
6340#define D2F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
6341#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
6342#define D2F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
6343#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
6344#define D2F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
6345#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
6346#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
6347#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
6348#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
6349#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
6350#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
6351#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
6352#define D2F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
6353#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
6354#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
6355#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
6356#define D2F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
6357#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
6358#define D2F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
6359#define D2F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
6360#define D2F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
6361#define D2F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
6362#define D2F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
6363#define D2F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
6364#define D2F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
6365#define D2F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
6366#define D2F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
6367#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
6368#define D2F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
6369#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
6370#define D2F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
6371#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
6372#define D2F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
6373#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
6374#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
6375#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
6376#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
6377#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
6378#define D2F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
6379#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
6380#define D2F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
6381#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
6382#define D2F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
6383#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
6384#define D2F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
6385#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
6386#define D2F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
6387#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
6388#define D2F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
6389#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
6390#define D2F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
6391#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
6392#define D2F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
6393#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
6394#define D2F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
6395#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
6396#define D2F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
6397#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
6398#define D2F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
6399#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
6400#define D2F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
6401#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6402#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6403#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6404#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6405#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6406#define D2F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6407#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
6408#define D2F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
6409#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
6410#define D2F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
6411#define D2F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
6412#define D2F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
6413#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
6414#define D2F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
6415#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
6416#define D2F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
6417#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6418#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6419#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6420#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6421#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6422#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6423#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6424#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6425#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6426#define D2F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6427#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6428#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6429#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6430#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6431#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6432#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6433#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6434#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6435#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6436#define D2F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6437#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6438#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6439#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6440#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6441#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6442#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6443#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6444#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6445#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6446#define D2F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6447#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6448#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6449#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6450#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6451#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6452#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6453#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6454#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6455#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6456#define D2F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6457#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6458#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6459#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6460#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6461#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6462#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6463#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6464#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6465#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6466#define D2F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6467#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6468#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6469#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6470#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6471#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6472#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6473#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6474#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6475#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6476#define D2F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6477#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6478#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6479#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6480#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6481#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6482#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6483#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6484#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6485#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6486#define D2F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6487#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6488#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6489#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6490#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6491#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6492#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6493#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6494#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6495#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6496#define D2F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6497#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6498#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6499#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6500#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6501#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6502#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6503#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6504#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6505#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6506#define D2F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6507#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6508#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6509#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6510#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6511#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6512#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6513#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6514#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6515#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6516#define D2F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6517#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6518#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6519#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6520#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6521#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6522#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6523#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6524#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6525#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6526#define D2F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6527#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6528#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6529#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6530#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6531#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6532#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6533#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6534#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6535#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6536#define D2F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6537#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6538#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6539#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6540#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6541#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6542#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6543#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6544#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6545#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6546#define D2F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6547#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6548#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6549#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6550#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6551#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6552#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6553#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6554#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6555#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6556#define D2F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6557#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
6558#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
6559#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
6560#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
6561#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
6562#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
6563#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
6564#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
6565#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
6566#define D2F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
6567#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
6568#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
6569#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
6570#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
6571#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
6572#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
6573#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
6574#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
6575#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
6576#define D2F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
6577#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6578#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6579#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6580#define D2F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6581#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6582#define D2F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6583#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
6584#define D2F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
6585#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
6586#define D2F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
6587#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
6588#define D2F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
6589#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
6590#define D2F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
6591#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
6592#define D2F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
6593#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
6594#define D2F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
6595#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
6596#define D2F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
6597#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
6598#define D2F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
6599#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
6600#define D2F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
6601#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
6602#define D2F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
6603#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
6604#define D2F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
6605#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
6606#define D2F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
6607#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
6608#define D2F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
6609#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
6610#define D2F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
6611#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
6612#define D2F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
6613#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
6614#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
6615#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
6616#define D2F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
6617#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
6618#define D2F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
6619#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
6620#define D2F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
6621#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
6622#define D2F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
6623#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
6624#define D2F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
6625#define D2F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
6626#define D2F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
6627#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
6628#define D2F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
6629#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
6630#define D2F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
6631#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
6632#define D2F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
6633#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
6634#define D2F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
6635#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
6636#define D2F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
6637#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
6638#define D2F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
6639#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
6640#define D2F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
6641#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
6642#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
6643#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
6644#define D2F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
6645#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
6646#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
6647#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
6648#define D2F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
6649#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
6650#define D2F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
6651#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
6652#define D2F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
6653#define D2F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
6654#define D2F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
6655#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
6656#define D2F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
6657#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
6658#define D2F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
6659#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
6660#define D2F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
6661#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
6662#define D2F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
6663#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
6664#define D2F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
6665#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
6666#define D2F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
6667#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
6668#define D2F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
6669#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
6670#define D2F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
6671#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
6672#define D2F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
6673#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
6674#define D2F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
6675#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
6676#define D2F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
6677#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
6678#define D2F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
6679#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
6680#define D2F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
6681#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
6682#define D2F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
6683#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
6684#define D2F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
6685#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
6686#define D2F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
6687#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
6688#define D2F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
6689#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
6690#define D2F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
6691#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
6692#define D2F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
6693#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
6694#define D2F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
6695#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
6696#define D2F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
6697#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
6698#define D2F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
6699#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
6700#define D2F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
6701#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
6702#define D2F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
6703#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
6704#define D2F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
6705#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
6706#define D2F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
6707#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
6708#define D2F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
6709#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
6710#define D2F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
6711#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
6712#define D2F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
6713#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
6714#define D2F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
6715#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
6716#define D2F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
6717#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
6718#define D2F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
6719#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
6720#define D2F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
6721#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
6722#define D2F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
6723#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
6724#define D2F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
6725#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
6726#define D2F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
6727#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
6728#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
6729#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
6730#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
6731#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
6732#define D2F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
6733#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
6734#define D2F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
6735#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
6736#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
6737#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
6738#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
6739#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
6740#define D2F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
6741#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
6742#define D2F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
6743#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
6744#define D2F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
6745#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
6746#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
6747#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
6748#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
6749#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
6750#define D2F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
6751#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
6752#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
6753#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
6754#define D2F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
6755#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
6756#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
6757#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
6758#define D2F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
6759#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
6760#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
6761#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
6762#define D2F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
6763#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
6764#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
6765#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
6766#define D2F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
6767#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
6768#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
6769#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
6770#define D2F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
6771#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
6772#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
6773#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
6774#define D2F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
6775#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
6776#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
6777#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
6778#define D2F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
6779#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
6780#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
6781#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
6782#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
6783#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
6784#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
6785#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
6786#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
6787#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
6788#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
6789#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
6790#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
6791#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
6792#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
6793#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
6794#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
6795#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
6796#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
6797#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
6798#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
6799#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
6800#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
6801#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
6802#define D2F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
6803#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
6804#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
6805#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
6806#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
6807#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
6808#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
6809#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
6810#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
6811#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
6812#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
6813#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
6814#define D2F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
6815#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
6816#define D2F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
6817#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
6818#define D2F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
6819#define D2F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
6820#define D2F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
6821#define D2F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
6822#define D2F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
6823#define D2F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
6824#define D2F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
6825#define D2F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
6826#define D2F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
6827#define D2F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
6828#define D2F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
6829#define D2F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
6830#define D2F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
6831#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
6832#define D2F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
6833#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
6834#define D2F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
6835#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
6836#define D2F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
6837#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
6838#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
6839#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
6840#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
6841#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
6842#define D2F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
6843#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
6844#define D2F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
6845#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
6846#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
6847#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
6848#define D2F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
6849#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
6850#define D2F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
6851#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
6852#define D2F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
6853#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
6854#define D2F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
6855#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
6856#define D2F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
6857#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
6858#define D2F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
6859#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
6860#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
6861#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
6862#define D2F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
6863#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
6864#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
6865#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
6866#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
6867#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
6868#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
6869#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
6870#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
6871#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
6872#define D2F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
6873#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
6874#define D2F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
6875#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
6876#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
6877#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
6878#define D2F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
6879#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
6880#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
6881#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
6882#define D2F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
6883#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
6884#define D2F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
6885#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
6886#define D2F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
6887#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
6888#define D2F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
6889#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
6890#define D2F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
6891#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
6892#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
6893#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
6894#define D2F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
6895#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
6896#define D2F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
6897#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
6898#define D2F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
6899#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
6900#define D2F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
6901#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
6902#define D2F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
6903#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
6904#define D2F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
6905#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
6906#define D2F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
6907#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
6908#define D2F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
6909#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
6910#define D2F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
6911#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
6912#define D2F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
6913#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
6914#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
6915#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
6916#define D2F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
6917#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
6918#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
6919#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
6920#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
6921#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
6922#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
6923#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
6924#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
6925#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
6926#define D2F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
6927#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
6928#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
6929#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
6930#define D2F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
6931#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
6932#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
6933#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
6934#define D2F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
6935#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
6936#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
6937#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
6938#define D2F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
6939#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
6940#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
6941#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
6942#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
6943#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
6944#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
6945#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
6946#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
6947#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
6948#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
6949#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
6950#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
6951#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
6952#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
6953#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
6954#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
6955#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
6956#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
6957#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
6958#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
6959#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
6960#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
6961#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
6962#define D2F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
6963#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
6964#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
6965#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
6966#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
6967#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
6968#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
6969#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
6970#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
6971#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
6972#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
6973#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
6974#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
6975#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
6976#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
6977#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
6978#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
6979#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
6980#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
6981#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
6982#define D2F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
6983#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
6984#define D2F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
6985#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
6986#define D2F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
6987#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
6988#define D2F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
6989#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
6990#define D2F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
6991#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
6992#define D2F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
6993#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
6994#define D2F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
6995#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
6996#define D2F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
6997#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
6998#define D2F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
6999#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
7000#define D2F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
7001#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
7002#define D2F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
7003#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
7004#define D2F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
7005#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
7006#define D2F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
7007#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
7008#define D2F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
7009#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
7010#define D2F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
7011#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
7012#define D2F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
7013#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
7014#define D2F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
7015#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
7016#define D2F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
7017#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
7018#define D2F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
7019#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
7020#define D2F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
7021#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
7022#define D2F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
7023#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
7024#define D2F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
7025#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
7026#define D2F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
7027#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
7028#define D2F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
7029#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
7030#define D2F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
7031#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
7032#define D2F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
7033#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
7034#define D2F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
7035#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
7036#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
7037#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
7038#define D2F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
7039#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
7040#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
7041#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
7042#define D2F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
7043#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
7044#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
7045#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
7046#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
7047#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
7048#define D2F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
7049#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
7050#define D2F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
7051#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
7052#define D2F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
7053#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
7054#define D2F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
7055#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
7056#define D2F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
7057#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
7058#define D2F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
7059#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
7060#define D2F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
7061#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
7062#define D2F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
7063#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
7064#define D2F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
7065#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
7066#define D2F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
7067#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
7068#define D2F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
7069#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
7070#define D2F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
7071#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
7072#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
7073#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
7074#define D2F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
7075#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
7076#define D2F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
7077#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
7078#define D2F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
7079#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
7080#define D2F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
7081#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
7082#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
7083#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
7084#define D2F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
7085#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
7086#define D2F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
7087#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
7088#define D2F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
7089#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
7090#define D2F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
7091#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
7092#define D2F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
7093#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
7094#define D2F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
7095#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
7096#define D2F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
7097#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
7098#define D2F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
7099#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
7100#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
7101#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
7102#define D2F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
7103#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
7104#define D2F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
7105#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
7106#define D2F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
7107#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
7108#define D2F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
7109#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
7110#define D2F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
7111#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
7112#define D2F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
7113#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
7114#define D2F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
7115#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
7116#define D2F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
7117#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
7118#define D2F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
7119#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
7120#define D2F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
7121#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
7122#define D2F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
7123#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
7124#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
7125#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
7126#define D2F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
7127#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
7128#define D2F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
7129#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
7130#define D2F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
7131#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
7132#define D2F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
7133#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
7134#define D2F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
7135#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
7136#define D2F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
7137#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
7138#define D2F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
7139#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
7140#define D2F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
7141#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
7142#define D2F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
7143#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
7144#define D2F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
7145#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
7146#define D2F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
7147#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
7148#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
7149#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
7150#define D2F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
7151#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
7152#define D2F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
7153#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
7154#define D2F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
7155#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
7156#define D2F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
7157#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
7158#define D2F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
7159#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
7160#define D2F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
7161#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
7162#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
7163#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
7164#define D2F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
7165#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
7166#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
7167#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
7168#define D2F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
7169#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
7170#define D2F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
7171#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
7172#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
7173#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
7174#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
7175#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
7176#define D2F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
7177#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
7178#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
7179#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
7180#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
7181#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
7182#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
7183#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
7184#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
7185#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
7186#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
7187#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
7188#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
7189#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
7190#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
7191#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
7192#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
7193#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
7194#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
7195#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
7196#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
7197#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
7198#define D2F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
7199#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
7200#define D2F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
7201#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
7202#define D2F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
7203#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
7204#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
7205#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
7206#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
7207#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
7208#define D2F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
7209#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
7210#define D2F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
7211#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
7212#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
7213#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
7214#define D2F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
7215#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
7216#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
7217#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
7218#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
7219#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
7220#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
7221#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
7222#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
7223#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
7224#define D2F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
7225#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
7226#define D2F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
7227#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
7228#define D2F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
7229#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
7230#define D2F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
7231#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
7232#define D2F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
7233#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
7234#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
7235#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
7236#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
7237#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
7238#define D2F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
7239#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
7240#define D2F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
7241#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
7242#define D2F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
7243#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
7244#define D2F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
7245#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
7246#define D2F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
7247#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
7248#define D2F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
7249#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
7250#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
7251#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
7252#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
7253#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
7254#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
7255#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
7256#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
7257#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
7258#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
7259#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
7260#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
7261#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
7262#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
7263#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
7264#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
7265#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
7266#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
7267#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
7268#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
7269#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
7270#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
7271#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
7272#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
7273#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
7274#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
7275#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
7276#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
7277#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
7278#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
7279#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
7280#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
7281#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
7282#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
7283#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
7284#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
7285#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
7286#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
7287#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
7288#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
7289#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
7290#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
7291#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
7292#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
7293#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
7294#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
7295#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
7296#define D2F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
7297#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
7298#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
7299#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
7300#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
7301#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
7302#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
7303#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
7304#define D2F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
7305#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
7306#define D2F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
7307#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
7308#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
7309#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
7310#define D2F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
7311#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
7312#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
7313#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
7314#define D2F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
7315#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
7316#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
7317#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
7318#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
7319#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
7320#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
7321#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
7322#define D2F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
7323#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
7324#define D2F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
7325#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
7326#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
7327#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
7328#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
7329#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
7330#define D2F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
7331#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
7332#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
7333#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
7334#define D2F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
7335#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
7336#define D2F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
7337#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
7338#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
7339#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
7340#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
7341#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
7342#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
7343#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
7344#define D2F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
7345#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
7346#define D2F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
7347#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
7348#define D2F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
7349#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
7350#define D2F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
7351#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
7352#define D2F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
7353#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
7354#define D2F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
7355#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
7356#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
7357#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
7358#define D2F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
7359#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
7360#define D2F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
7361#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
7362#define D2F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
7363#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
7364#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
7365#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
7366#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
7367#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
7368#define D2F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
7369#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
7370#define D2F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
7371#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
7372#define D2F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
7373#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
7374#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
7375#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
7376#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
7377#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
7378#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
7379#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
7380#define D2F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
7381#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
7382#define D2F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
7383#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
7384#define D2F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
7385#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
7386#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
7387#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
7388#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
7389#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
7390#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
7391#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
7392#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
7393#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
7394#define D2F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
7395#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
7396#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
7397#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
7398#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
7399#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
7400#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
7401#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
7402#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
7403#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
7404#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
7405#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
7406#define D2F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
7407#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
7408#define D2F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
7409#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
7410#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
7411#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
7412#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
7413#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
7414#define D2F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
7415#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
7416#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
7417#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
7418#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
7419#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
7420#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
7421#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
7422#define D2F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
7423#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
7424#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
7425#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
7426#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
7427#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
7428#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
7429#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
7430#define D2F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
7431#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
7432#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
7433#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
7434#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
7435#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
7436#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
7437#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
7438#define D2F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
7439#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
7440#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
7441#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
7442#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
7443#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
7444#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
7445#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
7446#define D2F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
7447#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
7448#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
7449#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
7450#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
7451#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
7452#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
7453#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
7454#define D2F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
7455#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
7456#define D2F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
7457#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
7458#define D2F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
7459#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
7460#define D2F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
7461#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
7462#define D2F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
7463#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
7464#define D2F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
7465#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
7466#define D2F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
7467#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
7468#define D2F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
7469#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
7470#define D2F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
7471#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
7472#define D2F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
7473#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
7474#define D2F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
7475#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
7476#define D2F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
7477#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
7478#define D2F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
7479#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
7480#define D2F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
7481#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
7482#define D2F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
7483#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
7484#define D2F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
7485#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
7486#define D2F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
7487#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
7488#define D2F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
7489#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
7490#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
7491#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
7492#define D2F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
7493#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
7494#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
7495#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
7496#define D2F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
7497#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
7498#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
7499#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
7500#define D2F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
7501#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
7502#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
7503#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
7504#define D2F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
7505#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
7506#define D2F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
7507#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
7508#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
7509#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
7510#define D2F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
7511#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
7512#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
7513#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
7514#define D2F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
7515#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
7516#define D2F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
7517#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
7518#define D2F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
7519#define D2F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
7520#define D2F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
7521#define D2F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
7522#define D2F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
7523#define D2F2_COMMAND__IO_ACCESS_EN_MASK 0x1
7524#define D2F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
7525#define D2F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
7526#define D2F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
7527#define D2F2_COMMAND__BUS_MASTER_EN_MASK 0x4
7528#define D2F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
7529#define D2F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
7530#define D2F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
7531#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
7532#define D2F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
7533#define D2F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
7534#define D2F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
7535#define D2F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
7536#define D2F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
7537#define D2F2_COMMAND__AD_STEPPING_MASK 0x80
7538#define D2F2_COMMAND__AD_STEPPING__SHIFT 0x7
7539#define D2F2_COMMAND__SERR_EN_MASK 0x100
7540#define D2F2_COMMAND__SERR_EN__SHIFT 0x8
7541#define D2F2_COMMAND__FAST_B2B_EN_MASK 0x200
7542#define D2F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
7543#define D2F2_COMMAND__INT_DIS_MASK 0x400
7544#define D2F2_COMMAND__INT_DIS__SHIFT 0xa
7545#define D2F2_STATUS__INT_STATUS_MASK 0x80000
7546#define D2F2_STATUS__INT_STATUS__SHIFT 0x13
7547#define D2F2_STATUS__CAP_LIST_MASK 0x100000
7548#define D2F2_STATUS__CAP_LIST__SHIFT 0x14
7549#define D2F2_STATUS__PCI_66_EN_MASK 0x200000
7550#define D2F2_STATUS__PCI_66_EN__SHIFT 0x15
7551#define D2F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
7552#define D2F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
7553#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
7554#define D2F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
7555#define D2F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
7556#define D2F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
7557#define D2F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
7558#define D2F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
7559#define D2F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
7560#define D2F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
7561#define D2F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
7562#define D2F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
7563#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
7564#define D2F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
7565#define D2F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
7566#define D2F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
7567#define D2F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
7568#define D2F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
7569#define D2F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
7570#define D2F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
7571#define D2F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
7572#define D2F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
7573#define D2F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
7574#define D2F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
7575#define D2F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
7576#define D2F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
7577#define D2F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
7578#define D2F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
7579#define D2F2_LATENCY__LATENCY_TIMER_MASK 0xff00
7580#define D2F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
7581#define D2F2_HEADER__HEADER_TYPE_MASK 0x7f0000
7582#define D2F2_HEADER__HEADER_TYPE__SHIFT 0x10
7583#define D2F2_HEADER__DEVICE_TYPE_MASK 0x800000
7584#define D2F2_HEADER__DEVICE_TYPE__SHIFT 0x17
7585#define D2F2_BIST__BIST_COMP_MASK 0xf000000
7586#define D2F2_BIST__BIST_COMP__SHIFT 0x18
7587#define D2F2_BIST__BIST_STRT_MASK 0x40000000
7588#define D2F2_BIST__BIST_STRT__SHIFT 0x1e
7589#define D2F2_BIST__BIST_CAP_MASK 0x80000000
7590#define D2F2_BIST__BIST_CAP__SHIFT 0x1f
7591#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
7592#define D2F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
7593#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
7594#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
7595#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
7596#define D2F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
7597#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
7598#define D2F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
7599#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
7600#define D2F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
7601#define D2F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
7602#define D2F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
7603#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
7604#define D2F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
7605#define D2F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
7606#define D2F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
7607#define D2F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
7608#define D2F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
7609#define D2F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
7610#define D2F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
7611#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
7612#define D2F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
7613#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
7614#define D2F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
7615#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
7616#define D2F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
7617#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
7618#define D2F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
7619#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
7620#define D2F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
7621#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
7622#define D2F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
7623#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
7624#define D2F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
7625#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
7626#define D2F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
7627#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
7628#define D2F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
7629#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
7630#define D2F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
7631#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
7632#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
7633#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
7634#define D2F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
7635#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
7636#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
7637#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
7638#define D2F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
7639#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
7640#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
7641#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
7642#define D2F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
7643#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
7644#define D2F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
7645#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
7646#define D2F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
7647#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
7648#define D2F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
7649#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
7650#define D2F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
7651#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
7652#define D2F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
7653#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
7654#define D2F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
7655#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
7656#define D2F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
7657#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
7658#define D2F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
7659#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
7660#define D2F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
7661#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
7662#define D2F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
7663#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
7664#define D2F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
7665#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
7666#define D2F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
7667#define D2F2_CAP_PTR__CAP_PTR_MASK 0xff
7668#define D2F2_CAP_PTR__CAP_PTR__SHIFT 0x0
7669#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
7670#define D2F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
7671#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
7672#define D2F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
7673#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
7674#define D2F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
7675#define D2F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
7676#define D2F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
7677#define D2F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
7678#define D2F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
7679#define D2F2_PMI_CAP__VERSION_MASK 0x70000
7680#define D2F2_PMI_CAP__VERSION__SHIFT 0x10
7681#define D2F2_PMI_CAP__PME_CLOCK_MASK 0x80000
7682#define D2F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
7683#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
7684#define D2F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
7685#define D2F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
7686#define D2F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
7687#define D2F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
7688#define D2F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
7689#define D2F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
7690#define D2F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
7691#define D2F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
7692#define D2F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
7693#define D2F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
7694#define D2F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
7695#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
7696#define D2F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
7697#define D2F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
7698#define D2F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
7699#define D2F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
7700#define D2F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
7701#define D2F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
7702#define D2F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
7703#define D2F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
7704#define D2F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
7705#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
7706#define D2F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
7707#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
7708#define D2F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
7709#define D2F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
7710#define D2F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
7711#define D2F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
7712#define D2F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
7713#define D2F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
7714#define D2F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
7715#define D2F2_PCIE_CAP__VERSION_MASK 0xf0000
7716#define D2F2_PCIE_CAP__VERSION__SHIFT 0x10
7717#define D2F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
7718#define D2F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
7719#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
7720#define D2F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
7721#define D2F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
7722#define D2F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
7723#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
7724#define D2F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
7725#define D2F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
7726#define D2F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
7727#define D2F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
7728#define D2F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
7729#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
7730#define D2F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
7731#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
7732#define D2F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
7733#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
7734#define D2F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
7735#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
7736#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
7737#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
7738#define D2F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
7739#define D2F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
7740#define D2F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
7741#define D2F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
7742#define D2F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
7743#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
7744#define D2F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
7745#define D2F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
7746#define D2F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
7747#define D2F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
7748#define D2F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
7749#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
7750#define D2F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
7751#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
7752#define D2F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
7753#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
7754#define D2F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
7755#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
7756#define D2F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
7757#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
7758#define D2F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
7759#define D2F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
7760#define D2F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
7761#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
7762#define D2F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
7763#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
7764#define D2F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
7765#define D2F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
7766#define D2F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
7767#define D2F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
7768#define D2F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
7769#define D2F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
7770#define D2F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
7771#define D2F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
7772#define D2F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
7773#define D2F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
7774#define D2F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
7775#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
7776#define D2F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
7777#define D2F2_LINK_CAP__LINK_SPEED_MASK 0xf
7778#define D2F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
7779#define D2F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
7780#define D2F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
7781#define D2F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
7782#define D2F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
7783#define D2F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
7784#define D2F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
7785#define D2F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
7786#define D2F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
7787#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
7788#define D2F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
7789#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
7790#define D2F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
7791#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
7792#define D2F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
7793#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
7794#define D2F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
7795#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
7796#define D2F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
7797#define D2F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
7798#define D2F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
7799#define D2F2_LINK_CNTL__PM_CONTROL_MASK 0x3
7800#define D2F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
7801#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
7802#define D2F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
7803#define D2F2_LINK_CNTL__LINK_DIS_MASK 0x10
7804#define D2F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
7805#define D2F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
7806#define D2F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
7807#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
7808#define D2F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
7809#define D2F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
7810#define D2F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
7811#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
7812#define D2F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
7813#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
7814#define D2F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
7815#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
7816#define D2F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
7817#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
7818#define D2F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
7819#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
7820#define D2F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
7821#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
7822#define D2F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
7823#define D2F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
7824#define D2F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
7825#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
7826#define D2F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
7827#define D2F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
7828#define D2F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
7829#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
7830#define D2F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
7831#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
7832#define D2F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
7833#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
7834#define D2F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
7835#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
7836#define D2F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
7837#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
7838#define D2F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
7839#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
7840#define D2F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
7841#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
7842#define D2F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
7843#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
7844#define D2F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
7845#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
7846#define D2F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
7847#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
7848#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
7849#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
7850#define D2F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
7851#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
7852#define D2F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
7853#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
7854#define D2F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
7855#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
7856#define D2F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
7857#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
7858#define D2F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
7859#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
7860#define D2F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
7861#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
7862#define D2F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
7863#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
7864#define D2F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
7865#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
7866#define D2F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
7867#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
7868#define D2F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
7869#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
7870#define D2F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
7871#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
7872#define D2F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
7873#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
7874#define D2F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
7875#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
7876#define D2F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
7877#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
7878#define D2F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
7879#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
7880#define D2F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
7881#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
7882#define D2F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
7883#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
7884#define D2F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
7885#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
7886#define D2F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
7887#define D2F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
7888#define D2F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
7889#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
7890#define D2F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
7891#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
7892#define D2F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
7893#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
7894#define D2F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
7895#define D2F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
7896#define D2F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
7897#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
7898#define D2F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
7899#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
7900#define D2F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
7901#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
7902#define D2F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
7903#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
7904#define D2F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
7905#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
7906#define D2F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
7907#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
7908#define D2F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
7909#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
7910#define D2F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
7911#define D2F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
7912#define D2F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
7913#define D2F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
7914#define D2F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
7915#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
7916#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
7917#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
7918#define D2F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
7919#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
7920#define D2F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
7921#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
7922#define D2F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
7923#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
7924#define D2F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
7925#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
7926#define D2F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
7927#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
7928#define D2F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
7929#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
7930#define D2F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
7931#define D2F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
7932#define D2F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
7933#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
7934#define D2F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
7935#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
7936#define D2F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
7937#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
7938#define D2F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
7939#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
7940#define D2F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
7941#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
7942#define D2F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
7943#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
7944#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
7945#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
7946#define D2F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
7947#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
7948#define D2F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
7949#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
7950#define D2F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
7951#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
7952#define D2F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
7953#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
7954#define D2F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
7955#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
7956#define D2F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
7957#define D2F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
7958#define D2F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
7959#define D2F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
7960#define D2F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
7961#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
7962#define D2F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
7963#define D2F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
7964#define D2F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
7965#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
7966#define D2F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
7967#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
7968#define D2F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
7969#define D2F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
7970#define D2F2_LINK_CAP2__RESERVED__SHIFT 0x9
7971#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
7972#define D2F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
7973#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
7974#define D2F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
7975#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
7976#define D2F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
7977#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
7978#define D2F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
7979#define D2F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
7980#define D2F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
7981#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
7982#define D2F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
7983#define D2F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
7984#define D2F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
7985#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
7986#define D2F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
7987#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
7988#define D2F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
7989#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
7990#define D2F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
7991#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
7992#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
7993#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
7994#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
7995#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
7996#define D2F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
7997#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
7998#define D2F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
7999#define D2F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
8000#define D2F2_SLOT_CAP2__RESERVED__SHIFT 0x0
8001#define D2F2_SLOT_CNTL2__RESERVED_MASK 0xffff
8002#define D2F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
8003#define D2F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
8004#define D2F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
8005#define D2F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
8006#define D2F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
8007#define D2F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
8008#define D2F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
8009#define D2F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
8010#define D2F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
8011#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
8012#define D2F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
8013#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
8014#define D2F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
8015#define D2F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
8016#define D2F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
8017#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
8018#define D2F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
8019#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
8020#define D2F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
8021#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
8022#define D2F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
8023#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
8024#define D2F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
8025#define D2F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
8026#define D2F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
8027#define D2F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
8028#define D2F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
8029#define D2F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
8030#define D2F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
8031#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
8032#define D2F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
8033#define D2F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
8034#define D2F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
8035#define D2F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
8036#define D2F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
8037#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
8038#define D2F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
8039#define D2F2_MSI_MAP_CAP__EN_MASK 0x10000
8040#define D2F2_MSI_MAP_CAP__EN__SHIFT 0x10
8041#define D2F2_MSI_MAP_CAP__FIXD_MASK 0x20000
8042#define D2F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
8043#define D2F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
8044#define D2F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
8045#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
8046#define D2F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
8047#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
8048#define D2F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
8049#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8050#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8051#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8052#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8053#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8054#define D2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8055#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
8056#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
8057#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
8058#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
8059#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
8060#define D2F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
8061#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
8062#define D2F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
8063#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
8064#define D2F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
8065#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8066#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8067#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8068#define D2F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8069#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8070#define D2F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8071#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
8072#define D2F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
8073#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
8074#define D2F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
8075#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
8076#define D2F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
8077#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
8078#define D2F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
8079#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
8080#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
8081#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
8082#define D2F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
8083#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
8084#define D2F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
8085#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
8086#define D2F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
8087#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
8088#define D2F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
8089#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
8090#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
8091#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
8092#define D2F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
8093#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
8094#define D2F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
8095#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
8096#define D2F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
8097#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
8098#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
8099#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
8100#define D2F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
8101#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
8102#define D2F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
8103#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
8104#define D2F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
8105#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
8106#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
8107#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
8108#define D2F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
8109#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
8110#define D2F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
8111#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
8112#define D2F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
8113#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
8114#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
8115#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
8116#define D2F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
8117#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
8118#define D2F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
8119#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
8120#define D2F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
8121#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
8122#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
8123#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
8124#define D2F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
8125#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
8126#define D2F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
8127#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
8128#define D2F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
8129#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
8130#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
8131#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
8132#define D2F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
8133#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
8134#define D2F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
8135#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
8136#define D2F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
8137#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8138#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8139#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8140#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8141#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8142#define D2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8143#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
8144#define D2F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
8145#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
8146#define D2F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
8147#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8148#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8149#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8150#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8151#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8152#define D2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8153#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
8154#define D2F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
8155#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
8156#define D2F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
8157#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
8158#define D2F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
8159#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
8160#define D2F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
8161#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
8162#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
8163#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
8164#define D2F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
8165#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
8166#define D2F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
8167#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
8168#define D2F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
8169#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
8170#define D2F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
8171#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
8172#define D2F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
8173#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
8174#define D2F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
8175#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
8176#define D2F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
8177#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
8178#define D2F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
8179#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
8180#define D2F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
8181#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
8182#define D2F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
8183#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
8184#define D2F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
8185#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
8186#define D2F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
8187#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
8188#define D2F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
8189#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
8190#define D2F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
8191#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
8192#define D2F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
8193#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
8194#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
8195#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
8196#define D2F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
8197#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
8198#define D2F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
8199#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
8200#define D2F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
8201#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
8202#define D2F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
8203#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
8204#define D2F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
8205#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
8206#define D2F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
8207#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
8208#define D2F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
8209#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
8210#define D2F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
8211#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
8212#define D2F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
8213#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
8214#define D2F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
8215#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
8216#define D2F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
8217#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
8218#define D2F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
8219#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
8220#define D2F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
8221#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
8222#define D2F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
8223#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
8224#define D2F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
8225#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
8226#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
8227#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
8228#define D2F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
8229#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
8230#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
8231#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
8232#define D2F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
8233#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
8234#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
8235#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
8236#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
8237#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
8238#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
8239#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
8240#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
8241#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
8242#define D2F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
8243#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
8244#define D2F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
8245#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
8246#define D2F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
8247#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
8248#define D2F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
8249#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
8250#define D2F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
8251#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
8252#define D2F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
8253#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
8254#define D2F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
8255#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
8256#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
8257#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
8258#define D2F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
8259#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
8260#define D2F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
8261#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
8262#define D2F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
8263#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
8264#define D2F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
8265#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
8266#define D2F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
8267#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
8268#define D2F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
8269#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
8270#define D2F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
8271#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
8272#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
8273#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
8274#define D2F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
8275#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
8276#define D2F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
8277#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
8278#define D2F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
8279#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
8280#define D2F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
8281#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
8282#define D2F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
8283#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
8284#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
8285#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
8286#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
8287#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
8288#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
8289#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
8290#define D2F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
8291#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
8292#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
8293#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
8294#define D2F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
8295#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
8296#define D2F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
8297#define D2F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
8298#define D2F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
8299#define D2F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
8300#define D2F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
8301#define D2F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
8302#define D2F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
8303#define D2F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
8304#define D2F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
8305#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
8306#define D2F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
8307#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
8308#define D2F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
8309#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
8310#define D2F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
8311#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
8312#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
8313#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
8314#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
8315#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
8316#define D2F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
8317#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
8318#define D2F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
8319#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
8320#define D2F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
8321#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
8322#define D2F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
8323#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
8324#define D2F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
8325#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
8326#define D2F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
8327#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
8328#define D2F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
8329#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
8330#define D2F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
8331#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
8332#define D2F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
8333#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
8334#define D2F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
8335#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
8336#define D2F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
8337#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
8338#define D2F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
8339#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8340#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8341#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8342#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8343#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8344#define D2F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8345#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
8346#define D2F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
8347#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
8348#define D2F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
8349#define D2F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
8350#define D2F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
8351#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
8352#define D2F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
8353#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
8354#define D2F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
8355#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8356#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8357#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8358#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8359#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8360#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8361#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8362#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8363#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8364#define D2F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8365#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8366#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8367#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8368#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8369#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8370#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8371#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8372#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8373#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8374#define D2F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8375#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8376#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8377#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8378#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8379#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8380#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8381#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8382#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8383#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8384#define D2F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8385#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8386#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8387#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8388#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8389#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8390#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8391#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8392#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8393#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8394#define D2F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8395#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8396#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8397#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8398#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8399#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8400#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8401#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8402#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8403#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8404#define D2F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8405#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8406#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8407#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8408#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8409#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8410#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8411#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8412#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8413#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8414#define D2F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8415#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8416#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8417#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8418#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8419#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8420#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8421#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8422#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8423#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8424#define D2F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8425#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8426#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8427#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8428#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8429#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8430#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8431#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8432#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8433#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8434#define D2F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8435#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8436#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8437#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8438#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8439#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8440#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8441#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8442#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8443#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8444#define D2F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8445#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8446#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8447#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8448#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8449#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8450#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8451#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8452#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8453#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8454#define D2F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8455#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8456#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8457#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8458#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8459#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8460#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8461#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8462#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8463#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8464#define D2F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8465#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8466#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8467#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8468#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8469#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8470#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8471#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8472#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8473#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8474#define D2F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8475#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8476#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8477#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8478#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8479#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8480#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8481#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8482#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8483#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8484#define D2F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8485#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8486#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8487#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8488#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8489#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8490#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8491#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8492#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8493#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8494#define D2F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8495#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
8496#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
8497#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
8498#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
8499#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
8500#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
8501#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
8502#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
8503#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
8504#define D2F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
8505#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
8506#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
8507#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
8508#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
8509#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
8510#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
8511#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
8512#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
8513#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
8514#define D2F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
8515#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8516#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8517#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8518#define D2F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8519#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8520#define D2F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8521#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
8522#define D2F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
8523#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
8524#define D2F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
8525#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
8526#define D2F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
8527#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
8528#define D2F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
8529#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
8530#define D2F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
8531#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
8532#define D2F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
8533#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
8534#define D2F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
8535#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
8536#define D2F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
8537#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
8538#define D2F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
8539#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
8540#define D2F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
8541#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
8542#define D2F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
8543#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
8544#define D2F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
8545#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
8546#define D2F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
8547#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
8548#define D2F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
8549#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
8550#define D2F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
8551#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
8552#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
8553#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
8554#define D2F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
8555#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
8556#define D2F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
8557#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
8558#define D2F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
8559#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
8560#define D2F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
8561#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
8562#define D2F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
8563#define D2F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
8564#define D2F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
8565#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
8566#define D2F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
8567#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
8568#define D2F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
8569#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
8570#define D2F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
8571#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
8572#define D2F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
8573#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
8574#define D2F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
8575#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
8576#define D2F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
8577#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
8578#define D2F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
8579#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
8580#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
8581#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
8582#define D2F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
8583#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
8584#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
8585#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
8586#define D2F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
8587#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
8588#define D2F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
8589#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
8590#define D2F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
8591#define D2F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
8592#define D2F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
8593#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
8594#define D2F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
8595#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
8596#define D2F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
8597#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
8598#define D2F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
8599#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
8600#define D2F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
8601#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
8602#define D2F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
8603#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
8604#define D2F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
8605#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
8606#define D2F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
8607#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
8608#define D2F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
8609#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
8610#define D2F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
8611#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
8612#define D2F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
8613#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
8614#define D2F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
8615#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
8616#define D2F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
8617#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
8618#define D2F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
8619#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
8620#define D2F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
8621#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
8622#define D2F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
8623#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
8624#define D2F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
8625#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
8626#define D2F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
8627#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
8628#define D2F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
8629#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
8630#define D2F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
8631#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
8632#define D2F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
8633#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
8634#define D2F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
8635#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
8636#define D2F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
8637#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
8638#define D2F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
8639#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
8640#define D2F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
8641#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
8642#define D2F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
8643#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
8644#define D2F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
8645#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
8646#define D2F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
8647#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
8648#define D2F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
8649#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
8650#define D2F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
8651#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
8652#define D2F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
8653#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
8654#define D2F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
8655#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
8656#define D2F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
8657#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
8658#define D2F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
8659#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
8660#define D2F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
8661#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
8662#define D2F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
8663#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
8664#define D2F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
8665#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
8666#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
8667#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
8668#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
8669#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
8670#define D2F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
8671#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
8672#define D2F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
8673#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
8674#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
8675#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
8676#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
8677#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
8678#define D2F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
8679#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
8680#define D2F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
8681#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
8682#define D2F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
8683#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
8684#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
8685#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
8686#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
8687#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
8688#define D2F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
8689#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
8690#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
8691#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
8692#define D2F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
8693#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
8694#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
8695#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
8696#define D2F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
8697#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
8698#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
8699#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
8700#define D2F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
8701#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
8702#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
8703#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
8704#define D2F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
8705#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
8706#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
8707#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
8708#define D2F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
8709#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
8710#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
8711#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
8712#define D2F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
8713#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
8714#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
8715#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
8716#define D2F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
8717#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
8718#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
8719#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
8720#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
8721#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
8722#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
8723#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
8724#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
8725#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
8726#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
8727#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
8728#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
8729#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
8730#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
8731#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
8732#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
8733#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
8734#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
8735#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
8736#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
8737#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
8738#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
8739#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
8740#define D2F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
8741#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
8742#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
8743#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
8744#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
8745#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
8746#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
8747#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
8748#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
8749#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
8750#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
8751#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
8752#define D2F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
8753#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
8754#define D2F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
8755#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
8756#define D2F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
8757#define D2F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
8758#define D2F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
8759#define D2F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
8760#define D2F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
8761#define D2F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
8762#define D2F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
8763#define D2F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
8764#define D2F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
8765#define D2F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
8766#define D2F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
8767#define D2F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
8768#define D2F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
8769#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
8770#define D2F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
8771#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
8772#define D2F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
8773#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
8774#define D2F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
8775#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
8776#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
8777#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
8778#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
8779#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
8780#define D2F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
8781#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
8782#define D2F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
8783#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
8784#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
8785#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
8786#define D2F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
8787#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
8788#define D2F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
8789#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
8790#define D2F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
8791#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
8792#define D2F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
8793#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
8794#define D2F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
8795#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
8796#define D2F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
8797#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
8798#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
8799#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
8800#define D2F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
8801#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
8802#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
8803#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
8804#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
8805#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
8806#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
8807#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
8808#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
8809#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
8810#define D2F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
8811#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
8812#define D2F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
8813#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
8814#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
8815#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
8816#define D2F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
8817#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
8818#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
8819#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
8820#define D2F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
8821#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
8822#define D2F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
8823#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
8824#define D2F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
8825#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
8826#define D2F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
8827#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
8828#define D2F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
8829#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
8830#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
8831#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
8832#define D2F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
8833#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
8834#define D2F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
8835#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
8836#define D2F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
8837#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
8838#define D2F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
8839#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
8840#define D2F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
8841#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
8842#define D2F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
8843#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
8844#define D2F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
8845#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
8846#define D2F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
8847#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
8848#define D2F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
8849#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
8850#define D2F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
8851#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
8852#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
8853#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
8854#define D2F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
8855#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
8856#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
8857#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
8858#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
8859#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
8860#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
8861#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
8862#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
8863#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
8864#define D2F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
8865#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
8866#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
8867#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
8868#define D2F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
8869#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
8870#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
8871#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
8872#define D2F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
8873#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
8874#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
8875#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
8876#define D2F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
8877#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
8878#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
8879#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
8880#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
8881#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
8882#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
8883#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
8884#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
8885#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
8886#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
8887#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
8888#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
8889#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
8890#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
8891#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
8892#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
8893#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
8894#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
8895#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
8896#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
8897#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
8898#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
8899#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
8900#define D2F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
8901#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
8902#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
8903#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
8904#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
8905#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
8906#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
8907#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
8908#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
8909#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
8910#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
8911#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
8912#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
8913#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
8914#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
8915#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
8916#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
8917#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
8918#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
8919#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
8920#define D2F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
8921#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
8922#define D2F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
8923#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
8924#define D2F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
8925#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
8926#define D2F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
8927#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
8928#define D2F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
8929#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
8930#define D2F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
8931#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
8932#define D2F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
8933#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
8934#define D2F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
8935#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
8936#define D2F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
8937#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
8938#define D2F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
8939#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
8940#define D2F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
8941#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
8942#define D2F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
8943#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
8944#define D2F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
8945#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
8946#define D2F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
8947#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
8948#define D2F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
8949#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
8950#define D2F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
8951#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
8952#define D2F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
8953#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
8954#define D2F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
8955#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
8956#define D2F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
8957#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
8958#define D2F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
8959#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
8960#define D2F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
8961#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
8962#define D2F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
8963#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
8964#define D2F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
8965#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
8966#define D2F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
8967#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
8968#define D2F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
8969#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
8970#define D2F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
8971#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
8972#define D2F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
8973#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
8974#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
8975#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
8976#define D2F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
8977#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
8978#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
8979#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
8980#define D2F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
8981#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
8982#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
8983#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
8984#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
8985#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
8986#define D2F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
8987#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
8988#define D2F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
8989#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
8990#define D2F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
8991#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
8992#define D2F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
8993#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
8994#define D2F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
8995#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
8996#define D2F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
8997#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
8998#define D2F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
8999#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
9000#define D2F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
9001#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
9002#define D2F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
9003#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
9004#define D2F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
9005#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
9006#define D2F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
9007#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
9008#define D2F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
9009#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
9010#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
9011#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
9012#define D2F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
9013#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
9014#define D2F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
9015#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
9016#define D2F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
9017#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
9018#define D2F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
9019#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
9020#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
9021#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
9022#define D2F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
9023#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
9024#define D2F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
9025#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
9026#define D2F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
9027#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
9028#define D2F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
9029#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
9030#define D2F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
9031#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
9032#define D2F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
9033#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
9034#define D2F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
9035#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
9036#define D2F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
9037#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
9038#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
9039#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
9040#define D2F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
9041#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
9042#define D2F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
9043#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
9044#define D2F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
9045#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
9046#define D2F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
9047#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
9048#define D2F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
9049#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
9050#define D2F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
9051#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
9052#define D2F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
9053#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
9054#define D2F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
9055#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
9056#define D2F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
9057#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
9058#define D2F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
9059#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
9060#define D2F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
9061#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
9062#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
9063#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
9064#define D2F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
9065#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
9066#define D2F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
9067#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
9068#define D2F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
9069#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
9070#define D2F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
9071#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
9072#define D2F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
9073#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
9074#define D2F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
9075#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
9076#define D2F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
9077#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
9078#define D2F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
9079#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
9080#define D2F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
9081#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
9082#define D2F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
9083#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
9084#define D2F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
9085#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
9086#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
9087#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
9088#define D2F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
9089#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
9090#define D2F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
9091#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
9092#define D2F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
9093#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
9094#define D2F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
9095#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
9096#define D2F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
9097#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
9098#define D2F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
9099#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
9100#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
9101#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
9102#define D2F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
9103#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
9104#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
9105#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
9106#define D2F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
9107#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
9108#define D2F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
9109#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
9110#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
9111#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
9112#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
9113#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
9114#define D2F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
9115#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
9116#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
9117#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
9118#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
9119#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
9120#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
9121#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
9122#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
9123#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
9124#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
9125#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
9126#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
9127#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
9128#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
9129#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
9130#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
9131#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
9132#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
9133#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
9134#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
9135#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
9136#define D2F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
9137#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
9138#define D2F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
9139#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
9140#define D2F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
9141#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
9142#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
9143#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
9144#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
9145#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
9146#define D2F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
9147#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
9148#define D2F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
9149#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
9150#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
9151#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
9152#define D2F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
9153#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
9154#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
9155#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
9156#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
9157#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
9158#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
9159#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
9160#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
9161#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
9162#define D2F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
9163#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
9164#define D2F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
9165#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
9166#define D2F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
9167#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
9168#define D2F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
9169#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
9170#define D2F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
9171#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
9172#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
9173#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
9174#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
9175#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
9176#define D2F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
9177#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
9178#define D2F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
9179#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
9180#define D2F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
9181#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
9182#define D2F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
9183#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
9184#define D2F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
9185#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
9186#define D2F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
9187#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
9188#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
9189#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
9190#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
9191#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
9192#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
9193#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
9194#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
9195#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
9196#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
9197#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
9198#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
9199#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
9200#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
9201#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
9202#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
9203#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
9204#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
9205#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
9206#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
9207#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
9208#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
9209#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
9210#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
9211#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
9212#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
9213#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
9214#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
9215#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
9216#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
9217#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
9218#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
9219#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
9220#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
9221#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
9222#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
9223#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
9224#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
9225#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
9226#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
9227#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
9228#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
9229#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
9230#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
9231#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
9232#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
9233#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
9234#define D2F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
9235#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
9236#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
9237#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
9238#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
9239#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
9240#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
9241#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
9242#define D2F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
9243#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
9244#define D2F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
9245#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
9246#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
9247#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
9248#define D2F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
9249#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
9250#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
9251#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
9252#define D2F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
9253#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
9254#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
9255#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
9256#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
9257#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
9258#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
9259#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
9260#define D2F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
9261#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
9262#define D2F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
9263#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
9264#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
9265#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
9266#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
9267#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
9268#define D2F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
9269#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
9270#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
9271#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
9272#define D2F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
9273#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
9274#define D2F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
9275#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
9276#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
9277#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
9278#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
9279#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
9280#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
9281#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
9282#define D2F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
9283#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
9284#define D2F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
9285#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
9286#define D2F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
9287#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
9288#define D2F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
9289#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
9290#define D2F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
9291#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
9292#define D2F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
9293#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
9294#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
9295#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
9296#define D2F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
9297#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
9298#define D2F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
9299#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
9300#define D2F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
9301#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
9302#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
9303#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
9304#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
9305#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
9306#define D2F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
9307#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
9308#define D2F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
9309#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
9310#define D2F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
9311#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
9312#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
9313#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
9314#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
9315#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
9316#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
9317#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
9318#define D2F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
9319#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
9320#define D2F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
9321#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
9322#define D2F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
9323#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
9324#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
9325#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
9326#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
9327#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
9328#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
9329#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
9330#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
9331#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
9332#define D2F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
9333#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
9334#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
9335#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
9336#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
9337#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
9338#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
9339#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
9340#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
9341#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
9342#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
9343#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
9344#define D2F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
9345#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
9346#define D2F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
9347#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
9348#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
9349#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
9350#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
9351#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
9352#define D2F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
9353#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
9354#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
9355#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
9356#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
9357#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
9358#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
9359#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
9360#define D2F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
9361#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
9362#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
9363#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
9364#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
9365#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
9366#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
9367#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
9368#define D2F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
9369#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
9370#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
9371#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
9372#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
9373#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
9374#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
9375#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
9376#define D2F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
9377#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
9378#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
9379#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
9380#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
9381#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
9382#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
9383#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
9384#define D2F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
9385#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
9386#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
9387#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
9388#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
9389#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
9390#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
9391#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
9392#define D2F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
9393#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
9394#define D2F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
9395#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
9396#define D2F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
9397#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
9398#define D2F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
9399#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
9400#define D2F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
9401#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
9402#define D2F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
9403#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
9404#define D2F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
9405#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
9406#define D2F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
9407#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
9408#define D2F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
9409#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
9410#define D2F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
9411#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
9412#define D2F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
9413#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
9414#define D2F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
9415#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
9416#define D2F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
9417#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
9418#define D2F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
9419#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
9420#define D2F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
9421#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
9422#define D2F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
9423#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
9424#define D2F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
9425#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
9426#define D2F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
9427#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
9428#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
9429#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
9430#define D2F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
9431#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
9432#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
9433#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
9434#define D2F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
9435#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
9436#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
9437#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
9438#define D2F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
9439#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
9440#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
9441#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
9442#define D2F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
9443#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
9444#define D2F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
9445#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
9446#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
9447#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
9448#define D2F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
9449#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
9450#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
9451#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
9452#define D2F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
9453#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
9454#define D2F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
9455#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
9456#define D2F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
9457#define D2F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
9458#define D2F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
9459#define D2F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
9460#define D2F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
9461#define D2F3_COMMAND__IO_ACCESS_EN_MASK 0x1
9462#define D2F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
9463#define D2F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
9464#define D2F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
9465#define D2F3_COMMAND__BUS_MASTER_EN_MASK 0x4
9466#define D2F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
9467#define D2F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
9468#define D2F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
9469#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
9470#define D2F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
9471#define D2F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
9472#define D2F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
9473#define D2F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
9474#define D2F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
9475#define D2F3_COMMAND__AD_STEPPING_MASK 0x80
9476#define D2F3_COMMAND__AD_STEPPING__SHIFT 0x7
9477#define D2F3_COMMAND__SERR_EN_MASK 0x100
9478#define D2F3_COMMAND__SERR_EN__SHIFT 0x8
9479#define D2F3_COMMAND__FAST_B2B_EN_MASK 0x200
9480#define D2F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
9481#define D2F3_COMMAND__INT_DIS_MASK 0x400
9482#define D2F3_COMMAND__INT_DIS__SHIFT 0xa
9483#define D2F3_STATUS__INT_STATUS_MASK 0x80000
9484#define D2F3_STATUS__INT_STATUS__SHIFT 0x13
9485#define D2F3_STATUS__CAP_LIST_MASK 0x100000
9486#define D2F3_STATUS__CAP_LIST__SHIFT 0x14
9487#define D2F3_STATUS__PCI_66_EN_MASK 0x200000
9488#define D2F3_STATUS__PCI_66_EN__SHIFT 0x15
9489#define D2F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
9490#define D2F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
9491#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
9492#define D2F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
9493#define D2F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
9494#define D2F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
9495#define D2F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
9496#define D2F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
9497#define D2F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
9498#define D2F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
9499#define D2F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
9500#define D2F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
9501#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
9502#define D2F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
9503#define D2F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
9504#define D2F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
9505#define D2F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
9506#define D2F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
9507#define D2F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
9508#define D2F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
9509#define D2F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
9510#define D2F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
9511#define D2F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
9512#define D2F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
9513#define D2F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
9514#define D2F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
9515#define D2F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
9516#define D2F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
9517#define D2F3_LATENCY__LATENCY_TIMER_MASK 0xff00
9518#define D2F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
9519#define D2F3_HEADER__HEADER_TYPE_MASK 0x7f0000
9520#define D2F3_HEADER__HEADER_TYPE__SHIFT 0x10
9521#define D2F3_HEADER__DEVICE_TYPE_MASK 0x800000
9522#define D2F3_HEADER__DEVICE_TYPE__SHIFT 0x17
9523#define D2F3_BIST__BIST_COMP_MASK 0xf000000
9524#define D2F3_BIST__BIST_COMP__SHIFT 0x18
9525#define D2F3_BIST__BIST_STRT_MASK 0x40000000
9526#define D2F3_BIST__BIST_STRT__SHIFT 0x1e
9527#define D2F3_BIST__BIST_CAP_MASK 0x80000000
9528#define D2F3_BIST__BIST_CAP__SHIFT 0x1f
9529#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
9530#define D2F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
9531#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
9532#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
9533#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
9534#define D2F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
9535#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
9536#define D2F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
9537#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
9538#define D2F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
9539#define D2F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
9540#define D2F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
9541#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
9542#define D2F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
9543#define D2F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
9544#define D2F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
9545#define D2F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
9546#define D2F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
9547#define D2F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
9548#define D2F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
9549#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
9550#define D2F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
9551#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
9552#define D2F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
9553#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
9554#define D2F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
9555#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
9556#define D2F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
9557#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
9558#define D2F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
9559#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
9560#define D2F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
9561#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
9562#define D2F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
9563#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
9564#define D2F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
9565#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
9566#define D2F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
9567#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
9568#define D2F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
9569#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
9570#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
9571#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
9572#define D2F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
9573#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
9574#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
9575#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
9576#define D2F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
9577#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
9578#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
9579#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
9580#define D2F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
9581#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
9582#define D2F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
9583#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
9584#define D2F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
9585#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
9586#define D2F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
9587#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
9588#define D2F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
9589#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
9590#define D2F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
9591#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
9592#define D2F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
9593#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
9594#define D2F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
9595#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
9596#define D2F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
9597#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
9598#define D2F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
9599#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
9600#define D2F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
9601#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
9602#define D2F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
9603#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
9604#define D2F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
9605#define D2F3_CAP_PTR__CAP_PTR_MASK 0xff
9606#define D2F3_CAP_PTR__CAP_PTR__SHIFT 0x0
9607#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
9608#define D2F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
9609#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
9610#define D2F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
9611#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
9612#define D2F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
9613#define D2F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
9614#define D2F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
9615#define D2F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
9616#define D2F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
9617#define D2F3_PMI_CAP__VERSION_MASK 0x70000
9618#define D2F3_PMI_CAP__VERSION__SHIFT 0x10
9619#define D2F3_PMI_CAP__PME_CLOCK_MASK 0x80000
9620#define D2F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
9621#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
9622#define D2F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
9623#define D2F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
9624#define D2F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
9625#define D2F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
9626#define D2F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
9627#define D2F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
9628#define D2F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
9629#define D2F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
9630#define D2F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
9631#define D2F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
9632#define D2F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
9633#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
9634#define D2F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
9635#define D2F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
9636#define D2F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
9637#define D2F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
9638#define D2F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
9639#define D2F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
9640#define D2F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
9641#define D2F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
9642#define D2F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
9643#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
9644#define D2F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
9645#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
9646#define D2F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
9647#define D2F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
9648#define D2F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
9649#define D2F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
9650#define D2F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
9651#define D2F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
9652#define D2F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
9653#define D2F3_PCIE_CAP__VERSION_MASK 0xf0000
9654#define D2F3_PCIE_CAP__VERSION__SHIFT 0x10
9655#define D2F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
9656#define D2F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
9657#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
9658#define D2F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
9659#define D2F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
9660#define D2F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
9661#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
9662#define D2F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
9663#define D2F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
9664#define D2F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
9665#define D2F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
9666#define D2F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
9667#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
9668#define D2F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
9669#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
9670#define D2F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
9671#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
9672#define D2F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
9673#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
9674#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
9675#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
9676#define D2F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
9677#define D2F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
9678#define D2F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
9679#define D2F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
9680#define D2F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
9681#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
9682#define D2F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
9683#define D2F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
9684#define D2F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
9685#define D2F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
9686#define D2F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
9687#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
9688#define D2F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
9689#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
9690#define D2F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
9691#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
9692#define D2F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
9693#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
9694#define D2F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
9695#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
9696#define D2F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
9697#define D2F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
9698#define D2F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
9699#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
9700#define D2F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
9701#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
9702#define D2F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
9703#define D2F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
9704#define D2F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
9705#define D2F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
9706#define D2F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
9707#define D2F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
9708#define D2F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
9709#define D2F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
9710#define D2F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
9711#define D2F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
9712#define D2F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
9713#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
9714#define D2F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
9715#define D2F3_LINK_CAP__LINK_SPEED_MASK 0xf
9716#define D2F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
9717#define D2F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
9718#define D2F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
9719#define D2F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
9720#define D2F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
9721#define D2F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
9722#define D2F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
9723#define D2F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
9724#define D2F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
9725#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
9726#define D2F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
9727#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
9728#define D2F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
9729#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
9730#define D2F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
9731#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
9732#define D2F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
9733#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
9734#define D2F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
9735#define D2F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
9736#define D2F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
9737#define D2F3_LINK_CNTL__PM_CONTROL_MASK 0x3
9738#define D2F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
9739#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
9740#define D2F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
9741#define D2F3_LINK_CNTL__LINK_DIS_MASK 0x10
9742#define D2F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
9743#define D2F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
9744#define D2F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
9745#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
9746#define D2F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
9747#define D2F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
9748#define D2F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
9749#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
9750#define D2F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
9751#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
9752#define D2F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
9753#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
9754#define D2F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
9755#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
9756#define D2F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
9757#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
9758#define D2F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
9759#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
9760#define D2F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
9761#define D2F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
9762#define D2F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
9763#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
9764#define D2F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
9765#define D2F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
9766#define D2F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
9767#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
9768#define D2F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
9769#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
9770#define D2F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
9771#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
9772#define D2F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
9773#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
9774#define D2F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
9775#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
9776#define D2F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
9777#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
9778#define D2F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
9779#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
9780#define D2F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
9781#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
9782#define D2F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
9783#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
9784#define D2F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
9785#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
9786#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
9787#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
9788#define D2F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
9789#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
9790#define D2F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
9791#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
9792#define D2F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
9793#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
9794#define D2F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
9795#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
9796#define D2F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
9797#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
9798#define D2F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
9799#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
9800#define D2F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
9801#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
9802#define D2F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
9803#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
9804#define D2F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
9805#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
9806#define D2F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
9807#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
9808#define D2F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
9809#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
9810#define D2F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
9811#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
9812#define D2F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
9813#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
9814#define D2F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
9815#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
9816#define D2F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
9817#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
9818#define D2F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
9819#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
9820#define D2F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
9821#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
9822#define D2F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
9823#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
9824#define D2F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
9825#define D2F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
9826#define D2F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
9827#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
9828#define D2F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
9829#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
9830#define D2F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
9831#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
9832#define D2F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
9833#define D2F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
9834#define D2F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
9835#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
9836#define D2F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
9837#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
9838#define D2F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
9839#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
9840#define D2F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
9841#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
9842#define D2F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
9843#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
9844#define D2F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
9845#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
9846#define D2F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
9847#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
9848#define D2F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
9849#define D2F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
9850#define D2F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
9851#define D2F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
9852#define D2F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
9853#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
9854#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
9855#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
9856#define D2F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
9857#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
9858#define D2F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
9859#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
9860#define D2F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
9861#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
9862#define D2F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
9863#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
9864#define D2F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
9865#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
9866#define D2F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
9867#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
9868#define D2F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
9869#define D2F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
9870#define D2F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
9871#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
9872#define D2F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
9873#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
9874#define D2F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
9875#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
9876#define D2F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
9877#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
9878#define D2F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
9879#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
9880#define D2F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
9881#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
9882#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
9883#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
9884#define D2F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
9885#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
9886#define D2F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
9887#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
9888#define D2F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
9889#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
9890#define D2F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
9891#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
9892#define D2F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
9893#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
9894#define D2F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
9895#define D2F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
9896#define D2F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
9897#define D2F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
9898#define D2F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
9899#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
9900#define D2F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
9901#define D2F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
9902#define D2F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
9903#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
9904#define D2F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
9905#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
9906#define D2F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
9907#define D2F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
9908#define D2F3_LINK_CAP2__RESERVED__SHIFT 0x9
9909#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
9910#define D2F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
9911#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
9912#define D2F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
9913#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
9914#define D2F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
9915#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
9916#define D2F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
9917#define D2F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
9918#define D2F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
9919#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
9920#define D2F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
9921#define D2F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
9922#define D2F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
9923#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
9924#define D2F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
9925#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
9926#define D2F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
9927#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
9928#define D2F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
9929#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
9930#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
9931#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
9932#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
9933#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
9934#define D2F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
9935#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
9936#define D2F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
9937#define D2F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
9938#define D2F3_SLOT_CAP2__RESERVED__SHIFT 0x0
9939#define D2F3_SLOT_CNTL2__RESERVED_MASK 0xffff
9940#define D2F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
9941#define D2F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
9942#define D2F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
9943#define D2F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
9944#define D2F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
9945#define D2F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
9946#define D2F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
9947#define D2F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
9948#define D2F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
9949#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
9950#define D2F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
9951#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
9952#define D2F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
9953#define D2F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
9954#define D2F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
9955#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
9956#define D2F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
9957#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
9958#define D2F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
9959#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
9960#define D2F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
9961#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
9962#define D2F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
9963#define D2F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
9964#define D2F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
9965#define D2F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
9966#define D2F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
9967#define D2F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
9968#define D2F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
9969#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
9970#define D2F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
9971#define D2F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
9972#define D2F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
9973#define D2F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
9974#define D2F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
9975#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
9976#define D2F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
9977#define D2F3_MSI_MAP_CAP__EN_MASK 0x10000
9978#define D2F3_MSI_MAP_CAP__EN__SHIFT 0x10
9979#define D2F3_MSI_MAP_CAP__FIXD_MASK 0x20000
9980#define D2F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
9981#define D2F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
9982#define D2F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
9983#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
9984#define D2F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
9985#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
9986#define D2F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
9987#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
9988#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
9989#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
9990#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
9991#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
9992#define D2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
9993#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
9994#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
9995#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
9996#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
9997#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
9998#define D2F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
9999#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
10000#define D2F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
10001#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
10002#define D2F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
10003#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10004#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10005#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10006#define D2F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10007#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10008#define D2F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10009#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
10010#define D2F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
10011#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
10012#define D2F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
10013#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
10014#define D2F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
10015#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
10016#define D2F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
10017#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
10018#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
10019#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
10020#define D2F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
10021#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
10022#define D2F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
10023#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
10024#define D2F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
10025#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
10026#define D2F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
10027#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
10028#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
10029#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
10030#define D2F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
10031#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
10032#define D2F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
10033#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
10034#define D2F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
10035#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
10036#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
10037#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
10038#define D2F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
10039#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
10040#define D2F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
10041#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
10042#define D2F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
10043#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
10044#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
10045#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
10046#define D2F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
10047#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
10048#define D2F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
10049#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
10050#define D2F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
10051#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
10052#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
10053#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
10054#define D2F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
10055#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
10056#define D2F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
10057#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
10058#define D2F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
10059#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
10060#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
10061#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
10062#define D2F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
10063#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
10064#define D2F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
10065#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
10066#define D2F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
10067#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
10068#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
10069#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
10070#define D2F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
10071#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
10072#define D2F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
10073#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
10074#define D2F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
10075#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10076#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10077#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10078#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10079#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10080#define D2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10081#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
10082#define D2F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
10083#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
10084#define D2F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
10085#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10086#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10087#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10088#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10089#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10090#define D2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10091#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
10092#define D2F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
10093#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
10094#define D2F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
10095#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
10096#define D2F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
10097#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
10098#define D2F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
10099#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
10100#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
10101#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
10102#define D2F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
10103#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
10104#define D2F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
10105#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
10106#define D2F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
10107#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
10108#define D2F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
10109#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
10110#define D2F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
10111#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
10112#define D2F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
10113#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
10114#define D2F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
10115#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
10116#define D2F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
10117#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
10118#define D2F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
10119#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
10120#define D2F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
10121#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
10122#define D2F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
10123#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
10124#define D2F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
10125#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
10126#define D2F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
10127#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
10128#define D2F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
10129#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
10130#define D2F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
10131#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
10132#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
10133#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
10134#define D2F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
10135#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
10136#define D2F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
10137#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
10138#define D2F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
10139#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
10140#define D2F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
10141#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
10142#define D2F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
10143#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
10144#define D2F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
10145#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
10146#define D2F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
10147#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
10148#define D2F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
10149#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
10150#define D2F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
10151#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
10152#define D2F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
10153#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
10154#define D2F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
10155#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
10156#define D2F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
10157#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
10158#define D2F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
10159#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
10160#define D2F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
10161#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
10162#define D2F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
10163#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
10164#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
10165#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
10166#define D2F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
10167#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
10168#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
10169#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
10170#define D2F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
10171#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
10172#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
10173#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
10174#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
10175#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
10176#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
10177#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
10178#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
10179#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
10180#define D2F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
10181#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
10182#define D2F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
10183#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
10184#define D2F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
10185#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
10186#define D2F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
10187#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
10188#define D2F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
10189#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
10190#define D2F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
10191#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
10192#define D2F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
10193#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
10194#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
10195#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
10196#define D2F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
10197#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
10198#define D2F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
10199#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
10200#define D2F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
10201#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
10202#define D2F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
10203#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
10204#define D2F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
10205#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
10206#define D2F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
10207#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
10208#define D2F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
10209#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
10210#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
10211#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
10212#define D2F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
10213#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
10214#define D2F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
10215#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
10216#define D2F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
10217#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
10218#define D2F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
10219#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
10220#define D2F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
10221#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
10222#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
10223#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
10224#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
10225#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
10226#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
10227#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
10228#define D2F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
10229#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
10230#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
10231#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
10232#define D2F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
10233#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
10234#define D2F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
10235#define D2F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
10236#define D2F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
10237#define D2F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
10238#define D2F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
10239#define D2F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
10240#define D2F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
10241#define D2F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
10242#define D2F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
10243#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
10244#define D2F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
10245#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
10246#define D2F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
10247#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
10248#define D2F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
10249#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
10250#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
10251#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
10252#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
10253#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
10254#define D2F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
10255#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
10256#define D2F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
10257#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
10258#define D2F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
10259#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
10260#define D2F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
10261#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
10262#define D2F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
10263#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
10264#define D2F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
10265#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
10266#define D2F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
10267#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
10268#define D2F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
10269#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
10270#define D2F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
10271#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
10272#define D2F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
10273#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
10274#define D2F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
10275#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
10276#define D2F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
10277#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10278#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10279#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10280#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10281#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10282#define D2F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10283#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
10284#define D2F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
10285#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
10286#define D2F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
10287#define D2F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
10288#define D2F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
10289#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
10290#define D2F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
10291#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
10292#define D2F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
10293#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10294#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10295#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10296#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10297#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10298#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10299#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10300#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10301#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10302#define D2F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10303#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10304#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10305#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10306#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10307#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10308#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10309#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10310#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10311#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10312#define D2F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10313#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10314#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10315#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10316#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10317#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10318#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10319#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10320#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10321#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10322#define D2F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10323#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10324#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10325#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10326#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10327#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10328#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10329#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10330#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10331#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10332#define D2F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10333#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10334#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10335#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10336#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10337#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10338#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10339#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10340#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10341#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10342#define D2F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10343#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10344#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10345#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10346#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10347#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10348#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10349#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10350#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10351#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10352#define D2F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10353#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10354#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10355#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10356#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10357#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10358#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10359#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10360#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10361#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10362#define D2F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10363#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10364#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10365#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10366#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10367#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10368#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10369#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10370#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10371#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10372#define D2F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10373#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10374#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10375#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10376#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10377#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10378#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10379#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10380#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10381#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10382#define D2F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10383#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10384#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10385#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10386#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10387#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10388#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10389#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10390#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10391#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10392#define D2F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10393#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10394#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10395#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10396#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10397#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10398#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10399#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10400#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10401#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10402#define D2F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10403#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10404#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10405#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10406#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10407#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10408#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10409#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10410#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10411#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10412#define D2F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10413#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10414#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10415#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10416#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10417#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10418#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10419#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10420#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10421#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10422#define D2F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10423#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10424#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10425#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10426#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10427#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10428#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10429#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10430#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10431#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10432#define D2F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10433#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
10434#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
10435#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
10436#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
10437#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
10438#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
10439#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
10440#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
10441#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
10442#define D2F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
10443#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
10444#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
10445#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
10446#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
10447#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
10448#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
10449#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
10450#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
10451#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
10452#define D2F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
10453#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10454#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10455#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10456#define D2F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10457#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10458#define D2F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10459#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
10460#define D2F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
10461#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
10462#define D2F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
10463#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
10464#define D2F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
10465#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
10466#define D2F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
10467#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
10468#define D2F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
10469#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
10470#define D2F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
10471#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
10472#define D2F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
10473#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
10474#define D2F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
10475#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
10476#define D2F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
10477#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
10478#define D2F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
10479#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
10480#define D2F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
10481#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
10482#define D2F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
10483#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
10484#define D2F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
10485#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
10486#define D2F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
10487#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
10488#define D2F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
10489#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
10490#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
10491#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
10492#define D2F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
10493#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
10494#define D2F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
10495#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
10496#define D2F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
10497#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
10498#define D2F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
10499#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
10500#define D2F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
10501#define D2F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
10502#define D2F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
10503#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
10504#define D2F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
10505#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
10506#define D2F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
10507#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
10508#define D2F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
10509#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
10510#define D2F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
10511#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
10512#define D2F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
10513#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
10514#define D2F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
10515#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
10516#define D2F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
10517#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
10518#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
10519#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
10520#define D2F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
10521#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
10522#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
10523#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
10524#define D2F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
10525#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
10526#define D2F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
10527#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
10528#define D2F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
10529#define D2F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
10530#define D2F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
10531#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
10532#define D2F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
10533#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
10534#define D2F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
10535#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
10536#define D2F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
10537#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
10538#define D2F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
10539#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
10540#define D2F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
10541#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
10542#define D2F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
10543#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
10544#define D2F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
10545#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
10546#define D2F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
10547#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
10548#define D2F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
10549#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
10550#define D2F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
10551#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
10552#define D2F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
10553#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
10554#define D2F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
10555#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
10556#define D2F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
10557#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
10558#define D2F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
10559#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
10560#define D2F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
10561#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
10562#define D2F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
10563#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
10564#define D2F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
10565#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
10566#define D2F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
10567#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
10568#define D2F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
10569#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
10570#define D2F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
10571#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
10572#define D2F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
10573#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
10574#define D2F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
10575#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
10576#define D2F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
10577#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
10578#define D2F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
10579#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
10580#define D2F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
10581#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
10582#define D2F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
10583#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
10584#define D2F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
10585#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
10586#define D2F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
10587#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
10588#define D2F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
10589#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
10590#define D2F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
10591#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
10592#define D2F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
10593#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
10594#define D2F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
10595#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
10596#define D2F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
10597#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
10598#define D2F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
10599#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
10600#define D2F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
10601#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
10602#define D2F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
10603#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
10604#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
10605#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
10606#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
10607#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
10608#define D2F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
10609#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
10610#define D2F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
10611#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
10612#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
10613#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
10614#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
10615#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
10616#define D2F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
10617#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
10618#define D2F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
10619#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
10620#define D2F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
10621#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
10622#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
10623#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
10624#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
10625#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
10626#define D2F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
10627#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
10628#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
10629#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
10630#define D2F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
10631#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
10632#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
10633#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
10634#define D2F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
10635#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
10636#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
10637#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
10638#define D2F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
10639#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
10640#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
10641#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
10642#define D2F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
10643#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
10644#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
10645#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
10646#define D2F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
10647#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
10648#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
10649#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
10650#define D2F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
10651#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
10652#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
10653#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
10654#define D2F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
10655#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
10656#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
10657#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
10658#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
10659#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
10660#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
10661#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
10662#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
10663#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
10664#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
10665#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
10666#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
10667#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
10668#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
10669#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
10670#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
10671#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
10672#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
10673#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
10674#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
10675#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
10676#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
10677#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
10678#define D2F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
10679#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
10680#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
10681#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
10682#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
10683#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
10684#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
10685#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
10686#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
10687#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
10688#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
10689#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
10690#define D2F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
10691#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
10692#define D2F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
10693#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
10694#define D2F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
10695#define D2F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
10696#define D2F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
10697#define D2F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
10698#define D2F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
10699#define D2F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
10700#define D2F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
10701#define D2F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
10702#define D2F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
10703#define D2F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
10704#define D2F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
10705#define D2F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
10706#define D2F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
10707#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
10708#define D2F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
10709#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
10710#define D2F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
10711#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
10712#define D2F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
10713#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
10714#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
10715#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
10716#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
10717#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
10718#define D2F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
10719#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
10720#define D2F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
10721#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
10722#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
10723#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
10724#define D2F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
10725#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
10726#define D2F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
10727#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
10728#define D2F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
10729#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
10730#define D2F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
10731#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
10732#define D2F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
10733#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
10734#define D2F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
10735#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
10736#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
10737#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
10738#define D2F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
10739#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
10740#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
10741#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
10742#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
10743#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
10744#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
10745#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
10746#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
10747#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
10748#define D2F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
10749#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
10750#define D2F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
10751#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
10752#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
10753#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
10754#define D2F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
10755#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
10756#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
10757#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
10758#define D2F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
10759#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
10760#define D2F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
10761#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
10762#define D2F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
10763#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
10764#define D2F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
10765#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
10766#define D2F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
10767#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
10768#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
10769#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
10770#define D2F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
10771#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
10772#define D2F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
10773#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
10774#define D2F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
10775#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
10776#define D2F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
10777#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
10778#define D2F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
10779#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
10780#define D2F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
10781#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
10782#define D2F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
10783#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
10784#define D2F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
10785#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
10786#define D2F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
10787#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
10788#define D2F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
10789#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
10790#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
10791#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
10792#define D2F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
10793#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
10794#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
10795#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
10796#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
10797#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
10798#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
10799#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
10800#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
10801#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
10802#define D2F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
10803#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
10804#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
10805#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
10806#define D2F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
10807#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
10808#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
10809#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
10810#define D2F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
10811#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
10812#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
10813#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
10814#define D2F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
10815#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
10816#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
10817#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
10818#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
10819#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
10820#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
10821#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
10822#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
10823#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
10824#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
10825#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
10826#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
10827#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
10828#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
10829#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
10830#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
10831#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
10832#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
10833#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
10834#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
10835#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
10836#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
10837#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
10838#define D2F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
10839#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
10840#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
10841#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
10842#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
10843#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
10844#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
10845#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
10846#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
10847#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
10848#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
10849#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
10850#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
10851#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
10852#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
10853#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
10854#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
10855#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
10856#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
10857#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
10858#define D2F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
10859#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
10860#define D2F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
10861#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
10862#define D2F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
10863#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
10864#define D2F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
10865#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
10866#define D2F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
10867#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
10868#define D2F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
10869#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
10870#define D2F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
10871#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
10872#define D2F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
10873#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
10874#define D2F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
10875#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
10876#define D2F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
10877#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
10878#define D2F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
10879#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
10880#define D2F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
10881#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
10882#define D2F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
10883#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
10884#define D2F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
10885#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
10886#define D2F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
10887#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
10888#define D2F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
10889#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
10890#define D2F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
10891#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
10892#define D2F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
10893#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
10894#define D2F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
10895#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
10896#define D2F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
10897#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
10898#define D2F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
10899#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
10900#define D2F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
10901#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
10902#define D2F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
10903#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
10904#define D2F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
10905#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
10906#define D2F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
10907#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
10908#define D2F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
10909#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
10910#define D2F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
10911#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
10912#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
10913#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
10914#define D2F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
10915#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
10916#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
10917#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
10918#define D2F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
10919#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
10920#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
10921#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
10922#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
10923#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
10924#define D2F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
10925#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
10926#define D2F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
10927#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
10928#define D2F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
10929#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
10930#define D2F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
10931#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
10932#define D2F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
10933#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
10934#define D2F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
10935#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
10936#define D2F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
10937#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
10938#define D2F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
10939#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
10940#define D2F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
10941#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
10942#define D2F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
10943#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
10944#define D2F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
10945#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
10946#define D2F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
10947#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
10948#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
10949#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
10950#define D2F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
10951#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
10952#define D2F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
10953#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
10954#define D2F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
10955#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
10956#define D2F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
10957#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
10958#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
10959#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
10960#define D2F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
10961#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
10962#define D2F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
10963#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
10964#define D2F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
10965#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
10966#define D2F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
10967#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
10968#define D2F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
10969#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
10970#define D2F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
10971#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
10972#define D2F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
10973#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
10974#define D2F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
10975#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
10976#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
10977#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
10978#define D2F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
10979#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
10980#define D2F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
10981#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
10982#define D2F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
10983#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
10984#define D2F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
10985#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
10986#define D2F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
10987#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
10988#define D2F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
10989#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
10990#define D2F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
10991#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
10992#define D2F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
10993#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
10994#define D2F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
10995#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
10996#define D2F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
10997#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
10998#define D2F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
10999#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
11000#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
11001#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
11002#define D2F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
11003#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
11004#define D2F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
11005#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
11006#define D2F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
11007#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
11008#define D2F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
11009#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
11010#define D2F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
11011#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
11012#define D2F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
11013#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
11014#define D2F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
11015#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
11016#define D2F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
11017#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
11018#define D2F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
11019#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
11020#define D2F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
11021#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
11022#define D2F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
11023#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
11024#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
11025#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
11026#define D2F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
11027#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
11028#define D2F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
11029#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
11030#define D2F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
11031#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
11032#define D2F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
11033#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
11034#define D2F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
11035#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
11036#define D2F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
11037#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
11038#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
11039#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
11040#define D2F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
11041#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
11042#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
11043#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
11044#define D2F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
11045#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
11046#define D2F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
11047#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
11048#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
11049#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
11050#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
11051#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
11052#define D2F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
11053#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
11054#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
11055#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
11056#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
11057#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
11058#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
11059#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
11060#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
11061#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
11062#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
11063#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
11064#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
11065#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
11066#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
11067#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
11068#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
11069#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
11070#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
11071#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
11072#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
11073#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
11074#define D2F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
11075#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
11076#define D2F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
11077#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
11078#define D2F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
11079#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
11080#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
11081#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
11082#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
11083#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
11084#define D2F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
11085#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
11086#define D2F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
11087#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
11088#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
11089#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
11090#define D2F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
11091#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
11092#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
11093#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
11094#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
11095#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
11096#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
11097#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
11098#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
11099#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
11100#define D2F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
11101#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
11102#define D2F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
11103#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
11104#define D2F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
11105#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
11106#define D2F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
11107#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
11108#define D2F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
11109#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
11110#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
11111#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
11112#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
11113#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
11114#define D2F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
11115#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
11116#define D2F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
11117#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
11118#define D2F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
11119#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
11120#define D2F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
11121#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
11122#define D2F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
11123#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
11124#define D2F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
11125#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
11126#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
11127#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
11128#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
11129#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
11130#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
11131#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
11132#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
11133#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
11134#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
11135#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
11136#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
11137#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
11138#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
11139#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
11140#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
11141#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
11142#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
11143#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
11144#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
11145#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
11146#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
11147#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
11148#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
11149#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
11150#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
11151#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
11152#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
11153#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
11154#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
11155#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
11156#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
11157#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
11158#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
11159#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
11160#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
11161#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
11162#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
11163#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
11164#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
11165#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
11166#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
11167#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
11168#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
11169#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
11170#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
11171#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
11172#define D2F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
11173#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
11174#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
11175#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
11176#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
11177#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
11178#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
11179#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
11180#define D2F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
11181#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
11182#define D2F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
11183#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
11184#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
11185#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
11186#define D2F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
11187#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
11188#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
11189#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
11190#define D2F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
11191#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
11192#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
11193#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
11194#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
11195#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
11196#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
11197#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
11198#define D2F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
11199#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
11200#define D2F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
11201#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
11202#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
11203#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
11204#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
11205#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
11206#define D2F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
11207#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
11208#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
11209#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
11210#define D2F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
11211#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
11212#define D2F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
11213#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
11214#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
11215#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
11216#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
11217#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
11218#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
11219#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
11220#define D2F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
11221#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
11222#define D2F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
11223#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
11224#define D2F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
11225#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
11226#define D2F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
11227#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
11228#define D2F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
11229#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
11230#define D2F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
11231#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
11232#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
11233#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
11234#define D2F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
11235#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
11236#define D2F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
11237#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
11238#define D2F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
11239#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
11240#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
11241#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
11242#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
11243#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
11244#define D2F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
11245#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
11246#define D2F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
11247#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
11248#define D2F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
11249#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
11250#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
11251#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
11252#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
11253#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
11254#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
11255#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
11256#define D2F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
11257#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
11258#define D2F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
11259#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
11260#define D2F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
11261#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
11262#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
11263#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
11264#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
11265#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
11266#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
11267#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
11268#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
11269#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
11270#define D2F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
11271#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
11272#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
11273#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
11274#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
11275#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
11276#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
11277#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
11278#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
11279#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
11280#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
11281#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
11282#define D2F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
11283#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
11284#define D2F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
11285#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
11286#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
11287#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
11288#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
11289#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
11290#define D2F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
11291#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
11292#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
11293#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
11294#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
11295#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
11296#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
11297#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
11298#define D2F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
11299#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
11300#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
11301#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
11302#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
11303#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
11304#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
11305#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
11306#define D2F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
11307#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
11308#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
11309#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
11310#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
11311#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
11312#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
11313#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
11314#define D2F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
11315#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
11316#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
11317#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
11318#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
11319#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
11320#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
11321#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
11322#define D2F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
11323#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
11324#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
11325#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
11326#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
11327#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
11328#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
11329#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
11330#define D2F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
11331#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
11332#define D2F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
11333#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
11334#define D2F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
11335#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
11336#define D2F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
11337#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
11338#define D2F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
11339#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
11340#define D2F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
11341#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
11342#define D2F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
11343#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
11344#define D2F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
11345#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
11346#define D2F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
11347#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
11348#define D2F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
11349#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
11350#define D2F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
11351#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
11352#define D2F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
11353#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
11354#define D2F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
11355#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
11356#define D2F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
11357#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
11358#define D2F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
11359#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
11360#define D2F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
11361#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
11362#define D2F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
11363#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
11364#define D2F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
11365#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
11366#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
11367#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
11368#define D2F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
11369#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
11370#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
11371#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
11372#define D2F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
11373#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
11374#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
11375#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
11376#define D2F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
11377#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
11378#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
11379#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
11380#define D2F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
11381#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
11382#define D2F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
11383#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
11384#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
11385#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
11386#define D2F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
11387#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
11388#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
11389#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
11390#define D2F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
11391#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
11392#define D2F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
11393#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
11394#define D2F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
11395#define D2F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
11396#define D2F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
11397#define D2F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
11398#define D2F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
11399#define D2F4_COMMAND__IO_ACCESS_EN_MASK 0x1
11400#define D2F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
11401#define D2F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
11402#define D2F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
11403#define D2F4_COMMAND__BUS_MASTER_EN_MASK 0x4
11404#define D2F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
11405#define D2F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
11406#define D2F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
11407#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
11408#define D2F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
11409#define D2F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
11410#define D2F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
11411#define D2F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
11412#define D2F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
11413#define D2F4_COMMAND__AD_STEPPING_MASK 0x80
11414#define D2F4_COMMAND__AD_STEPPING__SHIFT 0x7
11415#define D2F4_COMMAND__SERR_EN_MASK 0x100
11416#define D2F4_COMMAND__SERR_EN__SHIFT 0x8
11417#define D2F4_COMMAND__FAST_B2B_EN_MASK 0x200
11418#define D2F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
11419#define D2F4_COMMAND__INT_DIS_MASK 0x400
11420#define D2F4_COMMAND__INT_DIS__SHIFT 0xa
11421#define D2F4_STATUS__INT_STATUS_MASK 0x80000
11422#define D2F4_STATUS__INT_STATUS__SHIFT 0x13
11423#define D2F4_STATUS__CAP_LIST_MASK 0x100000
11424#define D2F4_STATUS__CAP_LIST__SHIFT 0x14
11425#define D2F4_STATUS__PCI_66_EN_MASK 0x200000
11426#define D2F4_STATUS__PCI_66_EN__SHIFT 0x15
11427#define D2F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
11428#define D2F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
11429#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
11430#define D2F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
11431#define D2F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
11432#define D2F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
11433#define D2F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
11434#define D2F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
11435#define D2F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
11436#define D2F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
11437#define D2F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
11438#define D2F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
11439#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
11440#define D2F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
11441#define D2F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
11442#define D2F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
11443#define D2F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
11444#define D2F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
11445#define D2F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
11446#define D2F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
11447#define D2F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
11448#define D2F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
11449#define D2F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
11450#define D2F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
11451#define D2F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
11452#define D2F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
11453#define D2F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
11454#define D2F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
11455#define D2F4_LATENCY__LATENCY_TIMER_MASK 0xff00
11456#define D2F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
11457#define D2F4_HEADER__HEADER_TYPE_MASK 0x7f0000
11458#define D2F4_HEADER__HEADER_TYPE__SHIFT 0x10
11459#define D2F4_HEADER__DEVICE_TYPE_MASK 0x800000
11460#define D2F4_HEADER__DEVICE_TYPE__SHIFT 0x17
11461#define D2F4_BIST__BIST_COMP_MASK 0xf000000
11462#define D2F4_BIST__BIST_COMP__SHIFT 0x18
11463#define D2F4_BIST__BIST_STRT_MASK 0x40000000
11464#define D2F4_BIST__BIST_STRT__SHIFT 0x1e
11465#define D2F4_BIST__BIST_CAP_MASK 0x80000000
11466#define D2F4_BIST__BIST_CAP__SHIFT 0x1f
11467#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
11468#define D2F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
11469#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
11470#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
11471#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
11472#define D2F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
11473#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
11474#define D2F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
11475#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
11476#define D2F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
11477#define D2F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
11478#define D2F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
11479#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
11480#define D2F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
11481#define D2F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
11482#define D2F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
11483#define D2F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
11484#define D2F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
11485#define D2F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
11486#define D2F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
11487#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
11488#define D2F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
11489#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
11490#define D2F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
11491#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
11492#define D2F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
11493#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
11494#define D2F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
11495#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
11496#define D2F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
11497#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
11498#define D2F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
11499#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
11500#define D2F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
11501#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
11502#define D2F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
11503#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
11504#define D2F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
11505#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
11506#define D2F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
11507#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
11508#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
11509#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
11510#define D2F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
11511#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
11512#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
11513#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
11514#define D2F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
11515#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
11516#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
11517#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
11518#define D2F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
11519#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
11520#define D2F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
11521#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
11522#define D2F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
11523#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
11524#define D2F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
11525#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
11526#define D2F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
11527#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
11528#define D2F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
11529#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
11530#define D2F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
11531#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
11532#define D2F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
11533#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
11534#define D2F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
11535#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
11536#define D2F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
11537#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
11538#define D2F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
11539#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
11540#define D2F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
11541#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
11542#define D2F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
11543#define D2F4_CAP_PTR__CAP_PTR_MASK 0xff
11544#define D2F4_CAP_PTR__CAP_PTR__SHIFT 0x0
11545#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
11546#define D2F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
11547#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
11548#define D2F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
11549#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
11550#define D2F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
11551#define D2F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
11552#define D2F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
11553#define D2F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
11554#define D2F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
11555#define D2F4_PMI_CAP__VERSION_MASK 0x70000
11556#define D2F4_PMI_CAP__VERSION__SHIFT 0x10
11557#define D2F4_PMI_CAP__PME_CLOCK_MASK 0x80000
11558#define D2F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
11559#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
11560#define D2F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
11561#define D2F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
11562#define D2F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
11563#define D2F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
11564#define D2F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
11565#define D2F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
11566#define D2F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
11567#define D2F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
11568#define D2F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
11569#define D2F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
11570#define D2F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
11571#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
11572#define D2F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
11573#define D2F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
11574#define D2F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
11575#define D2F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
11576#define D2F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
11577#define D2F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
11578#define D2F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
11579#define D2F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
11580#define D2F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
11581#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
11582#define D2F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
11583#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
11584#define D2F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
11585#define D2F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
11586#define D2F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
11587#define D2F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
11588#define D2F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
11589#define D2F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
11590#define D2F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
11591#define D2F4_PCIE_CAP__VERSION_MASK 0xf0000
11592#define D2F4_PCIE_CAP__VERSION__SHIFT 0x10
11593#define D2F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
11594#define D2F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
11595#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
11596#define D2F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
11597#define D2F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
11598#define D2F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
11599#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
11600#define D2F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
11601#define D2F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
11602#define D2F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
11603#define D2F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
11604#define D2F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
11605#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
11606#define D2F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
11607#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
11608#define D2F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
11609#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
11610#define D2F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
11611#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
11612#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
11613#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
11614#define D2F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
11615#define D2F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
11616#define D2F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
11617#define D2F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
11618#define D2F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
11619#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
11620#define D2F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
11621#define D2F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
11622#define D2F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
11623#define D2F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
11624#define D2F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
11625#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
11626#define D2F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
11627#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
11628#define D2F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
11629#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
11630#define D2F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
11631#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
11632#define D2F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
11633#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
11634#define D2F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
11635#define D2F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
11636#define D2F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
11637#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
11638#define D2F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
11639#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
11640#define D2F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
11641#define D2F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
11642#define D2F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
11643#define D2F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
11644#define D2F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
11645#define D2F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
11646#define D2F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
11647#define D2F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
11648#define D2F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
11649#define D2F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
11650#define D2F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
11651#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
11652#define D2F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
11653#define D2F4_LINK_CAP__LINK_SPEED_MASK 0xf
11654#define D2F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
11655#define D2F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
11656#define D2F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
11657#define D2F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
11658#define D2F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
11659#define D2F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
11660#define D2F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
11661#define D2F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
11662#define D2F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
11663#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
11664#define D2F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
11665#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
11666#define D2F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
11667#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
11668#define D2F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
11669#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
11670#define D2F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
11671#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
11672#define D2F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
11673#define D2F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
11674#define D2F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
11675#define D2F4_LINK_CNTL__PM_CONTROL_MASK 0x3
11676#define D2F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
11677#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
11678#define D2F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
11679#define D2F4_LINK_CNTL__LINK_DIS_MASK 0x10
11680#define D2F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
11681#define D2F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
11682#define D2F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
11683#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
11684#define D2F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
11685#define D2F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
11686#define D2F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
11687#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
11688#define D2F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
11689#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
11690#define D2F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
11691#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
11692#define D2F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
11693#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
11694#define D2F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
11695#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
11696#define D2F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
11697#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
11698#define D2F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
11699#define D2F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
11700#define D2F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
11701#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
11702#define D2F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
11703#define D2F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
11704#define D2F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
11705#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
11706#define D2F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
11707#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
11708#define D2F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
11709#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
11710#define D2F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
11711#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
11712#define D2F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
11713#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
11714#define D2F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
11715#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
11716#define D2F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
11717#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
11718#define D2F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
11719#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
11720#define D2F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
11721#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
11722#define D2F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
11723#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
11724#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
11725#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
11726#define D2F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
11727#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
11728#define D2F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
11729#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
11730#define D2F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
11731#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
11732#define D2F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
11733#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
11734#define D2F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
11735#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
11736#define D2F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
11737#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
11738#define D2F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
11739#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
11740#define D2F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
11741#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
11742#define D2F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
11743#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
11744#define D2F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
11745#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
11746#define D2F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
11747#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
11748#define D2F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
11749#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
11750#define D2F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
11751#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
11752#define D2F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
11753#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
11754#define D2F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
11755#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
11756#define D2F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
11757#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
11758#define D2F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
11759#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
11760#define D2F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
11761#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
11762#define D2F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
11763#define D2F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
11764#define D2F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
11765#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
11766#define D2F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
11767#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
11768#define D2F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
11769#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
11770#define D2F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
11771#define D2F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
11772#define D2F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
11773#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
11774#define D2F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
11775#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
11776#define D2F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
11777#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
11778#define D2F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
11779#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
11780#define D2F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
11781#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
11782#define D2F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
11783#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
11784#define D2F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
11785#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
11786#define D2F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
11787#define D2F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
11788#define D2F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
11789#define D2F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
11790#define D2F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
11791#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
11792#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
11793#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
11794#define D2F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
11795#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
11796#define D2F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
11797#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
11798#define D2F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
11799#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
11800#define D2F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
11801#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
11802#define D2F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
11803#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
11804#define D2F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
11805#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
11806#define D2F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
11807#define D2F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
11808#define D2F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
11809#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
11810#define D2F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
11811#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
11812#define D2F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
11813#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
11814#define D2F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
11815#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
11816#define D2F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
11817#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
11818#define D2F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
11819#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
11820#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
11821#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
11822#define D2F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
11823#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
11824#define D2F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
11825#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
11826#define D2F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
11827#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
11828#define D2F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
11829#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
11830#define D2F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
11831#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
11832#define D2F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
11833#define D2F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
11834#define D2F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
11835#define D2F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
11836#define D2F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
11837#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
11838#define D2F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
11839#define D2F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
11840#define D2F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
11841#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
11842#define D2F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
11843#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
11844#define D2F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
11845#define D2F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
11846#define D2F4_LINK_CAP2__RESERVED__SHIFT 0x9
11847#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
11848#define D2F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
11849#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
11850#define D2F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
11851#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
11852#define D2F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
11853#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
11854#define D2F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
11855#define D2F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
11856#define D2F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
11857#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
11858#define D2F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
11859#define D2F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
11860#define D2F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
11861#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
11862#define D2F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
11863#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
11864#define D2F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
11865#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
11866#define D2F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
11867#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
11868#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
11869#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
11870#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
11871#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
11872#define D2F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
11873#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
11874#define D2F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
11875#define D2F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
11876#define D2F4_SLOT_CAP2__RESERVED__SHIFT 0x0
11877#define D2F4_SLOT_CNTL2__RESERVED_MASK 0xffff
11878#define D2F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
11879#define D2F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
11880#define D2F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
11881#define D2F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
11882#define D2F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
11883#define D2F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
11884#define D2F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
11885#define D2F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
11886#define D2F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
11887#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
11888#define D2F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
11889#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
11890#define D2F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
11891#define D2F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
11892#define D2F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
11893#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
11894#define D2F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
11895#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
11896#define D2F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
11897#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
11898#define D2F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
11899#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
11900#define D2F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
11901#define D2F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
11902#define D2F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
11903#define D2F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
11904#define D2F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
11905#define D2F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
11906#define D2F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
11907#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
11908#define D2F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
11909#define D2F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
11910#define D2F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
11911#define D2F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
11912#define D2F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
11913#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
11914#define D2F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
11915#define D2F4_MSI_MAP_CAP__EN_MASK 0x10000
11916#define D2F4_MSI_MAP_CAP__EN__SHIFT 0x10
11917#define D2F4_MSI_MAP_CAP__FIXD_MASK 0x20000
11918#define D2F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
11919#define D2F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
11920#define D2F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
11921#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
11922#define D2F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
11923#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
11924#define D2F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
11925#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
11926#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
11927#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
11928#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
11929#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
11930#define D2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
11931#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
11932#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
11933#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
11934#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
11935#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
11936#define D2F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
11937#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
11938#define D2F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
11939#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
11940#define D2F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
11941#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
11942#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
11943#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
11944#define D2F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
11945#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
11946#define D2F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
11947#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
11948#define D2F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
11949#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
11950#define D2F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
11951#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
11952#define D2F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
11953#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
11954#define D2F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
11955#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
11956#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
11957#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
11958#define D2F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
11959#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
11960#define D2F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
11961#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
11962#define D2F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
11963#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
11964#define D2F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
11965#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
11966#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
11967#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
11968#define D2F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
11969#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
11970#define D2F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
11971#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
11972#define D2F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
11973#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
11974#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
11975#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
11976#define D2F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
11977#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
11978#define D2F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
11979#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
11980#define D2F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
11981#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
11982#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
11983#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
11984#define D2F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
11985#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
11986#define D2F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
11987#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
11988#define D2F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
11989#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
11990#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
11991#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
11992#define D2F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
11993#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
11994#define D2F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
11995#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
11996#define D2F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
11997#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
11998#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
11999#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
12000#define D2F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
12001#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
12002#define D2F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
12003#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
12004#define D2F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
12005#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
12006#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
12007#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
12008#define D2F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
12009#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
12010#define D2F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
12011#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
12012#define D2F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
12013#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
12014#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
12015#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
12016#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
12017#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
12018#define D2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
12019#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
12020#define D2F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
12021#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
12022#define D2F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
12023#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
12024#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
12025#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
12026#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
12027#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
12028#define D2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
12029#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
12030#define D2F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
12031#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
12032#define D2F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
12033#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
12034#define D2F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
12035#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
12036#define D2F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
12037#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
12038#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
12039#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
12040#define D2F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
12041#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
12042#define D2F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
12043#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
12044#define D2F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
12045#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
12046#define D2F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
12047#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
12048#define D2F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
12049#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
12050#define D2F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
12051#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
12052#define D2F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
12053#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
12054#define D2F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
12055#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
12056#define D2F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
12057#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
12058#define D2F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
12059#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
12060#define D2F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
12061#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
12062#define D2F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
12063#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
12064#define D2F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
12065#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
12066#define D2F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
12067#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
12068#define D2F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
12069#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
12070#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
12071#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
12072#define D2F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
12073#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
12074#define D2F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
12075#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
12076#define D2F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
12077#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
12078#define D2F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
12079#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
12080#define D2F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
12081#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
12082#define D2F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
12083#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
12084#define D2F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
12085#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
12086#define D2F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
12087#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
12088#define D2F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
12089#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
12090#define D2F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
12091#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
12092#define D2F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
12093#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
12094#define D2F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
12095#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
12096#define D2F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
12097#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
12098#define D2F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
12099#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
12100#define D2F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
12101#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
12102#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
12103#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
12104#define D2F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
12105#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
12106#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
12107#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
12108#define D2F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
12109#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
12110#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
12111#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
12112#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
12113#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
12114#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
12115#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
12116#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
12117#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
12118#define D2F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
12119#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
12120#define D2F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
12121#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
12122#define D2F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
12123#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
12124#define D2F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
12125#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
12126#define D2F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
12127#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
12128#define D2F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
12129#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
12130#define D2F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
12131#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
12132#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
12133#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
12134#define D2F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
12135#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
12136#define D2F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
12137#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
12138#define D2F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
12139#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
12140#define D2F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
12141#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
12142#define D2F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
12143#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
12144#define D2F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
12145#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
12146#define D2F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
12147#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
12148#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
12149#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
12150#define D2F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
12151#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
12152#define D2F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
12153#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
12154#define D2F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
12155#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
12156#define D2F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
12157#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
12158#define D2F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
12159#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
12160#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
12161#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
12162#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
12163#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
12164#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
12165#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
12166#define D2F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
12167#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
12168#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
12169#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
12170#define D2F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
12171#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
12172#define D2F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
12173#define D2F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
12174#define D2F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
12175#define D2F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
12176#define D2F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
12177#define D2F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
12178#define D2F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
12179#define D2F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
12180#define D2F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
12181#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
12182#define D2F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
12183#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
12184#define D2F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
12185#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
12186#define D2F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
12187#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
12188#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
12189#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
12190#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
12191#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
12192#define D2F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
12193#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
12194#define D2F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
12195#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
12196#define D2F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
12197#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
12198#define D2F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
12199#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
12200#define D2F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
12201#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
12202#define D2F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
12203#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
12204#define D2F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
12205#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
12206#define D2F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
12207#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
12208#define D2F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
12209#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
12210#define D2F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
12211#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
12212#define D2F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
12213#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
12214#define D2F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
12215#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
12216#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
12217#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
12218#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
12219#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
12220#define D2F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
12221#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
12222#define D2F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
12223#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
12224#define D2F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
12225#define D2F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
12226#define D2F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
12227#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
12228#define D2F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
12229#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
12230#define D2F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
12231#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12232#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12233#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12234#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12235#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12236#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12237#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12238#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12239#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12240#define D2F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12241#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12242#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12243#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12244#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12245#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12246#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12247#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12248#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12249#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12250#define D2F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12251#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12252#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12253#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12254#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12255#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12256#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12257#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12258#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12259#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12260#define D2F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12261#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12262#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12263#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12264#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12265#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12266#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12267#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12268#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12269#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12270#define D2F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12271#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12272#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12273#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12274#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12275#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12276#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12277#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12278#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12279#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12280#define D2F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12281#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12282#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12283#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12284#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12285#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12286#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12287#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12288#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12289#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12290#define D2F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12291#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12292#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12293#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12294#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12295#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12296#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12297#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12298#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12299#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12300#define D2F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12301#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12302#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12303#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12304#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12305#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12306#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12307#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12308#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12309#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12310#define D2F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12311#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12312#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12313#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12314#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12315#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12316#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12317#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12318#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12319#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12320#define D2F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12321#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12322#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12323#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12324#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12325#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12326#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12327#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12328#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12329#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12330#define D2F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12331#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12332#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12333#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12334#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12335#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12336#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12337#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12338#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12339#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12340#define D2F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12341#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12342#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12343#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12344#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12345#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12346#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12347#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12348#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12349#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12350#define D2F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12351#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12352#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12353#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12354#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12355#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12356#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12357#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12358#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12359#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12360#define D2F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12361#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12362#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12363#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12364#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12365#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12366#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12367#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12368#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12369#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12370#define D2F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12371#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
12372#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
12373#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
12374#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
12375#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
12376#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
12377#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
12378#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
12379#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
12380#define D2F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
12381#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
12382#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
12383#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
12384#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
12385#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
12386#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
12387#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
12388#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
12389#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
12390#define D2F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
12391#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
12392#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
12393#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
12394#define D2F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
12395#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
12396#define D2F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
12397#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
12398#define D2F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
12399#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
12400#define D2F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
12401#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
12402#define D2F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
12403#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
12404#define D2F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
12405#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
12406#define D2F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
12407#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
12408#define D2F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
12409#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
12410#define D2F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
12411#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
12412#define D2F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
12413#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
12414#define D2F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
12415#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
12416#define D2F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
12417#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
12418#define D2F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
12419#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
12420#define D2F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
12421#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
12422#define D2F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
12423#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
12424#define D2F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
12425#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
12426#define D2F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
12427#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
12428#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
12429#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
12430#define D2F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
12431#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
12432#define D2F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
12433#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
12434#define D2F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
12435#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
12436#define D2F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
12437#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
12438#define D2F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
12439#define D2F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
12440#define D2F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
12441#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
12442#define D2F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
12443#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
12444#define D2F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
12445#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
12446#define D2F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
12447#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
12448#define D2F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
12449#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
12450#define D2F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
12451#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
12452#define D2F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
12453#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
12454#define D2F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
12455#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
12456#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
12457#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
12458#define D2F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
12459#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
12460#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
12461#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
12462#define D2F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
12463#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
12464#define D2F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
12465#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
12466#define D2F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
12467#define D2F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
12468#define D2F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
12469#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
12470#define D2F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
12471#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
12472#define D2F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
12473#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
12474#define D2F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
12475#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
12476#define D2F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
12477#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
12478#define D2F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
12479#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
12480#define D2F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
12481#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
12482#define D2F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
12483#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
12484#define D2F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
12485#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
12486#define D2F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
12487#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
12488#define D2F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
12489#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
12490#define D2F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
12491#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
12492#define D2F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
12493#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
12494#define D2F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
12495#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
12496#define D2F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
12497#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
12498#define D2F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
12499#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
12500#define D2F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
12501#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
12502#define D2F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
12503#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
12504#define D2F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
12505#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
12506#define D2F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
12507#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
12508#define D2F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
12509#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
12510#define D2F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
12511#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
12512#define D2F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
12513#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
12514#define D2F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
12515#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
12516#define D2F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
12517#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
12518#define D2F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
12519#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
12520#define D2F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
12521#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
12522#define D2F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
12523#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
12524#define D2F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
12525#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
12526#define D2F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
12527#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
12528#define D2F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
12529#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
12530#define D2F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
12531#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
12532#define D2F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
12533#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
12534#define D2F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
12535#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
12536#define D2F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
12537#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
12538#define D2F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
12539#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
12540#define D2F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
12541#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
12542#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
12543#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
12544#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
12545#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
12546#define D2F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
12547#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
12548#define D2F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
12549#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
12550#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
12551#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
12552#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
12553#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
12554#define D2F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
12555#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
12556#define D2F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
12557#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
12558#define D2F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
12559#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
12560#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
12561#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
12562#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
12563#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
12564#define D2F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
12565#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
12566#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
12567#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
12568#define D2F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
12569#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
12570#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
12571#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
12572#define D2F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
12573#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
12574#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
12575#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
12576#define D2F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
12577#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
12578#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
12579#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
12580#define D2F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
12581#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
12582#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
12583#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
12584#define D2F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
12585#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
12586#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
12587#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
12588#define D2F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
12589#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
12590#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
12591#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
12592#define D2F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
12593#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
12594#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
12595#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
12596#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
12597#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
12598#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
12599#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
12600#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
12601#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
12602#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
12603#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
12604#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
12605#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
12606#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
12607#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
12608#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
12609#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
12610#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
12611#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
12612#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
12613#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
12614#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
12615#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
12616#define D2F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
12617#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
12618#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
12619#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
12620#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
12621#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
12622#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
12623#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
12624#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
12625#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
12626#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
12627#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
12628#define D2F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
12629#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
12630#define D2F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
12631#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
12632#define D2F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
12633#define D2F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
12634#define D2F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
12635#define D2F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
12636#define D2F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
12637#define D2F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
12638#define D2F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
12639#define D2F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
12640#define D2F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
12641#define D2F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
12642#define D2F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
12643#define D2F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
12644#define D2F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
12645#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
12646#define D2F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
12647#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
12648#define D2F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
12649#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
12650#define D2F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
12651#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
12652#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
12653#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
12654#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
12655#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
12656#define D2F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
12657#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
12658#define D2F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
12659#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
12660#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
12661#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
12662#define D2F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
12663#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
12664#define D2F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
12665#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
12666#define D2F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
12667#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
12668#define D2F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
12669#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
12670#define D2F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
12671#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
12672#define D2F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
12673#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
12674#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
12675#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
12676#define D2F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
12677#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
12678#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
12679#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
12680#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
12681#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
12682#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
12683#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
12684#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
12685#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
12686#define D2F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
12687#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
12688#define D2F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
12689#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
12690#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
12691#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
12692#define D2F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
12693#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
12694#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
12695#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
12696#define D2F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
12697#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
12698#define D2F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
12699#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
12700#define D2F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
12701#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
12702#define D2F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
12703#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
12704#define D2F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
12705#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
12706#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
12707#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
12708#define D2F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
12709#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
12710#define D2F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
12711#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
12712#define D2F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
12713#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
12714#define D2F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
12715#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
12716#define D2F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
12717#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
12718#define D2F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
12719#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
12720#define D2F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
12721#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
12722#define D2F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
12723#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
12724#define D2F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
12725#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
12726#define D2F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
12727#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
12728#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
12729#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
12730#define D2F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
12731#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
12732#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
12733#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
12734#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
12735#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
12736#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
12737#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
12738#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
12739#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
12740#define D2F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
12741#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
12742#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
12743#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
12744#define D2F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
12745#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
12746#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
12747#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
12748#define D2F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
12749#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
12750#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
12751#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
12752#define D2F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
12753#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
12754#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
12755#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
12756#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
12757#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
12758#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
12759#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
12760#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
12761#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
12762#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
12763#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
12764#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
12765#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
12766#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
12767#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
12768#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
12769#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
12770#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
12771#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
12772#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
12773#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
12774#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
12775#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
12776#define D2F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
12777#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
12778#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
12779#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
12780#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
12781#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
12782#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
12783#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
12784#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
12785#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
12786#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
12787#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
12788#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
12789#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
12790#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
12791#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
12792#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
12793#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
12794#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
12795#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
12796#define D2F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
12797#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
12798#define D2F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
12799#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
12800#define D2F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
12801#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
12802#define D2F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
12803#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
12804#define D2F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
12805#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
12806#define D2F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
12807#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
12808#define D2F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
12809#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
12810#define D2F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
12811#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
12812#define D2F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
12813#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
12814#define D2F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
12815#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
12816#define D2F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
12817#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
12818#define D2F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
12819#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
12820#define D2F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
12821#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
12822#define D2F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
12823#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
12824#define D2F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
12825#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
12826#define D2F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
12827#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
12828#define D2F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
12829#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
12830#define D2F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
12831#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
12832#define D2F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
12833#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
12834#define D2F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
12835#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
12836#define D2F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
12837#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
12838#define D2F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
12839#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
12840#define D2F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
12841#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
12842#define D2F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
12843#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
12844#define D2F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
12845#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
12846#define D2F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
12847#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
12848#define D2F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
12849#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
12850#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
12851#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
12852#define D2F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
12853#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
12854#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
12855#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
12856#define D2F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
12857#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
12858#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
12859#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
12860#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
12861#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
12862#define D2F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
12863#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
12864#define D2F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
12865#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
12866#define D2F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
12867#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
12868#define D2F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
12869#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
12870#define D2F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
12871#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
12872#define D2F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
12873#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
12874#define D2F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
12875#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
12876#define D2F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
12877#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
12878#define D2F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
12879#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
12880#define D2F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
12881#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
12882#define D2F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
12883#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
12884#define D2F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
12885#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
12886#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
12887#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
12888#define D2F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
12889#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
12890#define D2F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
12891#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
12892#define D2F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
12893#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
12894#define D2F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
12895#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
12896#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
12897#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
12898#define D2F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
12899#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
12900#define D2F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
12901#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
12902#define D2F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
12903#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
12904#define D2F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
12905#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
12906#define D2F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
12907#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
12908#define D2F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
12909#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
12910#define D2F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
12911#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
12912#define D2F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
12913#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
12914#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
12915#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
12916#define D2F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
12917#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
12918#define D2F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
12919#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
12920#define D2F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
12921#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
12922#define D2F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
12923#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
12924#define D2F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
12925#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
12926#define D2F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
12927#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
12928#define D2F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
12929#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
12930#define D2F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
12931#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
12932#define D2F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
12933#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
12934#define D2F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
12935#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
12936#define D2F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
12937#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
12938#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
12939#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
12940#define D2F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
12941#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
12942#define D2F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
12943#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
12944#define D2F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
12945#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
12946#define D2F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
12947#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
12948#define D2F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
12949#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
12950#define D2F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
12951#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
12952#define D2F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
12953#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
12954#define D2F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
12955#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
12956#define D2F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
12957#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
12958#define D2F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
12959#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
12960#define D2F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
12961#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
12962#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
12963#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
12964#define D2F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
12965#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
12966#define D2F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
12967#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
12968#define D2F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
12969#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
12970#define D2F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
12971#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
12972#define D2F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
12973#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
12974#define D2F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
12975#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
12976#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
12977#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
12978#define D2F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
12979#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
12980#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
12981#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
12982#define D2F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
12983#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
12984#define D2F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
12985#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
12986#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
12987#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
12988#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
12989#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
12990#define D2F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
12991#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
12992#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
12993#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
12994#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
12995#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
12996#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
12997#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
12998#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
12999#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
13000#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
13001#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
13002#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
13003#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
13004#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
13005#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
13006#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
13007#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
13008#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
13009#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
13010#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
13011#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
13012#define D2F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
13013#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
13014#define D2F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
13015#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
13016#define D2F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
13017#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
13018#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
13019#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
13020#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
13021#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
13022#define D2F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
13023#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
13024#define D2F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
13025#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
13026#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
13027#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
13028#define D2F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
13029#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
13030#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
13031#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
13032#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
13033#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
13034#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
13035#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
13036#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
13037#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
13038#define D2F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
13039#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
13040#define D2F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
13041#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
13042#define D2F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
13043#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
13044#define D2F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
13045#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
13046#define D2F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
13047#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
13048#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
13049#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
13050#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
13051#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
13052#define D2F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
13053#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
13054#define D2F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
13055#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
13056#define D2F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
13057#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
13058#define D2F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
13059#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
13060#define D2F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
13061#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
13062#define D2F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
13063#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
13064#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
13065#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
13066#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
13067#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
13068#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
13069#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
13070#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
13071#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
13072#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
13073#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
13074#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
13075#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
13076#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
13077#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
13078#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
13079#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
13080#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
13081#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
13082#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
13083#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
13084#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
13085#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
13086#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
13087#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
13088#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
13089#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
13090#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
13091#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
13092#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
13093#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
13094#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
13095#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
13096#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
13097#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
13098#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
13099#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
13100#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
13101#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
13102#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
13103#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
13104#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
13105#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
13106#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
13107#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
13108#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
13109#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
13110#define D2F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
13111#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
13112#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
13113#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
13114#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
13115#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
13116#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
13117#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
13118#define D2F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
13119#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
13120#define D2F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
13121#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
13122#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
13123#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
13124#define D2F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
13125#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
13126#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
13127#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
13128#define D2F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
13129#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
13130#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
13131#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
13132#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
13133#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
13134#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
13135#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
13136#define D2F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
13137#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
13138#define D2F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
13139#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
13140#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
13141#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
13142#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
13143#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
13144#define D2F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
13145#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
13146#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
13147#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
13148#define D2F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
13149#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
13150#define D2F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
13151#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
13152#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
13153#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
13154#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
13155#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
13156#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
13157#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
13158#define D2F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
13159#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
13160#define D2F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
13161#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
13162#define D2F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
13163#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
13164#define D2F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
13165#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
13166#define D2F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
13167#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
13168#define D2F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
13169#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
13170#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
13171#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
13172#define D2F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
13173#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
13174#define D2F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
13175#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
13176#define D2F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
13177#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
13178#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
13179#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
13180#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
13181#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
13182#define D2F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
13183#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
13184#define D2F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
13185#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
13186#define D2F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
13187#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
13188#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
13189#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
13190#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
13191#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
13192#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
13193#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
13194#define D2F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
13195#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
13196#define D2F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
13197#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
13198#define D2F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
13199#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
13200#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
13201#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
13202#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
13203#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
13204#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
13205#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
13206#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
13207#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
13208#define D2F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
13209#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
13210#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
13211#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
13212#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
13213#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
13214#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
13215#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
13216#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
13217#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
13218#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
13219#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
13220#define D2F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
13221#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
13222#define D2F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
13223#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
13224#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
13225#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
13226#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
13227#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
13228#define D2F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
13229#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
13230#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
13231#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
13232#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
13233#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
13234#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
13235#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
13236#define D2F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
13237#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
13238#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
13239#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
13240#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
13241#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
13242#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
13243#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
13244#define D2F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
13245#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
13246#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
13247#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
13248#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
13249#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
13250#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
13251#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
13252#define D2F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
13253#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
13254#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
13255#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
13256#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
13257#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
13258#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
13259#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
13260#define D2F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
13261#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
13262#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
13263#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
13264#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
13265#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
13266#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
13267#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
13268#define D2F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
13269#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
13270#define D2F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
13271#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
13272#define D2F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
13273#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
13274#define D2F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
13275#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
13276#define D2F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
13277#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
13278#define D2F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
13279#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
13280#define D2F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
13281#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
13282#define D2F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
13283#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
13284#define D2F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
13285#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
13286#define D2F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
13287#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
13288#define D2F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
13289#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
13290#define D2F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
13291#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
13292#define D2F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
13293#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
13294#define D2F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
13295#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
13296#define D2F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
13297#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
13298#define D2F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
13299#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
13300#define D2F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
13301#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
13302#define D2F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
13303#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
13304#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
13305#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
13306#define D2F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
13307#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
13308#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
13309#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
13310#define D2F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
13311#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
13312#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
13313#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
13314#define D2F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
13315#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
13316#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
13317#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
13318#define D2F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
13319#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
13320#define D2F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
13321#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
13322#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
13323#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
13324#define D2F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
13325#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
13326#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
13327#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
13328#define D2F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
13329#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
13330#define D2F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
13331#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
13332#define D2F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
13333#define D2F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
13334#define D2F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
13335#define D2F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
13336#define D2F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
13337#define D2F5_COMMAND__IO_ACCESS_EN_MASK 0x1
13338#define D2F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
13339#define D2F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
13340#define D2F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
13341#define D2F5_COMMAND__BUS_MASTER_EN_MASK 0x4
13342#define D2F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
13343#define D2F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
13344#define D2F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
13345#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
13346#define D2F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
13347#define D2F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
13348#define D2F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
13349#define D2F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
13350#define D2F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
13351#define D2F5_COMMAND__AD_STEPPING_MASK 0x80
13352#define D2F5_COMMAND__AD_STEPPING__SHIFT 0x7
13353#define D2F5_COMMAND__SERR_EN_MASK 0x100
13354#define D2F5_COMMAND__SERR_EN__SHIFT 0x8
13355#define D2F5_COMMAND__FAST_B2B_EN_MASK 0x200
13356#define D2F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
13357#define D2F5_COMMAND__INT_DIS_MASK 0x400
13358#define D2F5_COMMAND__INT_DIS__SHIFT 0xa
13359#define D2F5_STATUS__INT_STATUS_MASK 0x80000
13360#define D2F5_STATUS__INT_STATUS__SHIFT 0x13
13361#define D2F5_STATUS__CAP_LIST_MASK 0x100000
13362#define D2F5_STATUS__CAP_LIST__SHIFT 0x14
13363#define D2F5_STATUS__PCI_66_EN_MASK 0x200000
13364#define D2F5_STATUS__PCI_66_EN__SHIFT 0x15
13365#define D2F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
13366#define D2F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
13367#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
13368#define D2F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
13369#define D2F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
13370#define D2F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
13371#define D2F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
13372#define D2F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
13373#define D2F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
13374#define D2F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
13375#define D2F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
13376#define D2F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
13377#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
13378#define D2F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
13379#define D2F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
13380#define D2F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
13381#define D2F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
13382#define D2F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
13383#define D2F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
13384#define D2F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
13385#define D2F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
13386#define D2F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
13387#define D2F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
13388#define D2F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
13389#define D2F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
13390#define D2F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
13391#define D2F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
13392#define D2F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
13393#define D2F5_LATENCY__LATENCY_TIMER_MASK 0xff00
13394#define D2F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
13395#define D2F5_HEADER__HEADER_TYPE_MASK 0x7f0000
13396#define D2F5_HEADER__HEADER_TYPE__SHIFT 0x10
13397#define D2F5_HEADER__DEVICE_TYPE_MASK 0x800000
13398#define D2F5_HEADER__DEVICE_TYPE__SHIFT 0x17
13399#define D2F5_BIST__BIST_COMP_MASK 0xf000000
13400#define D2F5_BIST__BIST_COMP__SHIFT 0x18
13401#define D2F5_BIST__BIST_STRT_MASK 0x40000000
13402#define D2F5_BIST__BIST_STRT__SHIFT 0x1e
13403#define D2F5_BIST__BIST_CAP_MASK 0x80000000
13404#define D2F5_BIST__BIST_CAP__SHIFT 0x1f
13405#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
13406#define D2F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
13407#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
13408#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
13409#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
13410#define D2F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
13411#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
13412#define D2F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
13413#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
13414#define D2F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
13415#define D2F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
13416#define D2F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
13417#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
13418#define D2F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
13419#define D2F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
13420#define D2F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
13421#define D2F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
13422#define D2F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
13423#define D2F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
13424#define D2F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
13425#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
13426#define D2F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
13427#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
13428#define D2F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
13429#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
13430#define D2F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
13431#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
13432#define D2F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
13433#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
13434#define D2F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
13435#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
13436#define D2F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
13437#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
13438#define D2F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
13439#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
13440#define D2F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
13441#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
13442#define D2F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
13443#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
13444#define D2F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
13445#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
13446#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
13447#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
13448#define D2F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
13449#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
13450#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
13451#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
13452#define D2F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
13453#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
13454#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
13455#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
13456#define D2F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
13457#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
13458#define D2F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
13459#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
13460#define D2F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
13461#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
13462#define D2F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
13463#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
13464#define D2F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
13465#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
13466#define D2F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
13467#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
13468#define D2F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
13469#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
13470#define D2F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
13471#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
13472#define D2F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
13473#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
13474#define D2F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
13475#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
13476#define D2F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
13477#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
13478#define D2F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
13479#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
13480#define D2F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
13481#define D2F5_CAP_PTR__CAP_PTR_MASK 0xff
13482#define D2F5_CAP_PTR__CAP_PTR__SHIFT 0x0
13483#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
13484#define D2F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
13485#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
13486#define D2F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
13487#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
13488#define D2F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
13489#define D2F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
13490#define D2F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
13491#define D2F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
13492#define D2F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
13493#define D2F5_PMI_CAP__VERSION_MASK 0x70000
13494#define D2F5_PMI_CAP__VERSION__SHIFT 0x10
13495#define D2F5_PMI_CAP__PME_CLOCK_MASK 0x80000
13496#define D2F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
13497#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
13498#define D2F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
13499#define D2F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
13500#define D2F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
13501#define D2F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
13502#define D2F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
13503#define D2F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
13504#define D2F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
13505#define D2F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
13506#define D2F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
13507#define D2F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
13508#define D2F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
13509#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
13510#define D2F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
13511#define D2F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
13512#define D2F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
13513#define D2F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
13514#define D2F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
13515#define D2F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
13516#define D2F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
13517#define D2F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
13518#define D2F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
13519#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
13520#define D2F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
13521#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
13522#define D2F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
13523#define D2F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
13524#define D2F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
13525#define D2F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
13526#define D2F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
13527#define D2F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
13528#define D2F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
13529#define D2F5_PCIE_CAP__VERSION_MASK 0xf0000
13530#define D2F5_PCIE_CAP__VERSION__SHIFT 0x10
13531#define D2F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
13532#define D2F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
13533#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
13534#define D2F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
13535#define D2F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
13536#define D2F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
13537#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
13538#define D2F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
13539#define D2F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
13540#define D2F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
13541#define D2F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
13542#define D2F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
13543#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
13544#define D2F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
13545#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
13546#define D2F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
13547#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
13548#define D2F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
13549#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
13550#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
13551#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
13552#define D2F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
13553#define D2F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
13554#define D2F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
13555#define D2F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
13556#define D2F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
13557#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
13558#define D2F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
13559#define D2F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
13560#define D2F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
13561#define D2F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
13562#define D2F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
13563#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
13564#define D2F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
13565#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
13566#define D2F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
13567#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
13568#define D2F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
13569#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
13570#define D2F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
13571#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
13572#define D2F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
13573#define D2F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
13574#define D2F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
13575#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
13576#define D2F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
13577#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
13578#define D2F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
13579#define D2F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
13580#define D2F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
13581#define D2F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
13582#define D2F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
13583#define D2F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
13584#define D2F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
13585#define D2F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
13586#define D2F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
13587#define D2F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
13588#define D2F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
13589#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
13590#define D2F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
13591#define D2F5_LINK_CAP__LINK_SPEED_MASK 0xf
13592#define D2F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
13593#define D2F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
13594#define D2F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
13595#define D2F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
13596#define D2F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
13597#define D2F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
13598#define D2F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
13599#define D2F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
13600#define D2F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
13601#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
13602#define D2F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
13603#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
13604#define D2F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
13605#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
13606#define D2F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
13607#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
13608#define D2F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
13609#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
13610#define D2F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
13611#define D2F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
13612#define D2F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
13613#define D2F5_LINK_CNTL__PM_CONTROL_MASK 0x3
13614#define D2F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
13615#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
13616#define D2F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
13617#define D2F5_LINK_CNTL__LINK_DIS_MASK 0x10
13618#define D2F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
13619#define D2F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
13620#define D2F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
13621#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
13622#define D2F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
13623#define D2F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
13624#define D2F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
13625#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
13626#define D2F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
13627#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
13628#define D2F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
13629#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
13630#define D2F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
13631#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
13632#define D2F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
13633#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
13634#define D2F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
13635#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
13636#define D2F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
13637#define D2F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
13638#define D2F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
13639#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
13640#define D2F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
13641#define D2F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
13642#define D2F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
13643#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
13644#define D2F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
13645#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
13646#define D2F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
13647#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
13648#define D2F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
13649#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
13650#define D2F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
13651#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
13652#define D2F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
13653#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
13654#define D2F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
13655#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
13656#define D2F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
13657#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
13658#define D2F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
13659#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
13660#define D2F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
13661#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
13662#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
13663#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
13664#define D2F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
13665#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
13666#define D2F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
13667#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
13668#define D2F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
13669#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
13670#define D2F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
13671#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
13672#define D2F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
13673#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
13674#define D2F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
13675#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
13676#define D2F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
13677#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
13678#define D2F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
13679#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
13680#define D2F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
13681#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
13682#define D2F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
13683#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
13684#define D2F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
13685#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
13686#define D2F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
13687#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
13688#define D2F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
13689#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
13690#define D2F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
13691#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
13692#define D2F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
13693#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
13694#define D2F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
13695#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
13696#define D2F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
13697#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
13698#define D2F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
13699#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
13700#define D2F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
13701#define D2F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
13702#define D2F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
13703#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
13704#define D2F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
13705#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
13706#define D2F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
13707#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
13708#define D2F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
13709#define D2F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
13710#define D2F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
13711#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
13712#define D2F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
13713#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
13714#define D2F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
13715#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
13716#define D2F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
13717#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
13718#define D2F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
13719#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
13720#define D2F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
13721#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
13722#define D2F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
13723#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
13724#define D2F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
13725#define D2F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
13726#define D2F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
13727#define D2F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
13728#define D2F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
13729#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
13730#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
13731#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
13732#define D2F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
13733#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
13734#define D2F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
13735#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
13736#define D2F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
13737#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
13738#define D2F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
13739#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
13740#define D2F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
13741#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
13742#define D2F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
13743#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
13744#define D2F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
13745#define D2F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
13746#define D2F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
13747#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
13748#define D2F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
13749#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
13750#define D2F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
13751#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
13752#define D2F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
13753#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
13754#define D2F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
13755#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
13756#define D2F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
13757#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
13758#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
13759#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
13760#define D2F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
13761#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
13762#define D2F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
13763#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
13764#define D2F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
13765#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
13766#define D2F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
13767#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
13768#define D2F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
13769#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
13770#define D2F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
13771#define D2F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
13772#define D2F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
13773#define D2F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
13774#define D2F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
13775#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
13776#define D2F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
13777#define D2F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
13778#define D2F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
13779#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
13780#define D2F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
13781#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
13782#define D2F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
13783#define D2F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
13784#define D2F5_LINK_CAP2__RESERVED__SHIFT 0x9
13785#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
13786#define D2F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
13787#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
13788#define D2F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
13789#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
13790#define D2F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
13791#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
13792#define D2F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
13793#define D2F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
13794#define D2F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
13795#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
13796#define D2F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
13797#define D2F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
13798#define D2F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
13799#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
13800#define D2F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
13801#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
13802#define D2F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
13803#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
13804#define D2F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
13805#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
13806#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
13807#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
13808#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
13809#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
13810#define D2F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
13811#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
13812#define D2F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
13813#define D2F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
13814#define D2F5_SLOT_CAP2__RESERVED__SHIFT 0x0
13815#define D2F5_SLOT_CNTL2__RESERVED_MASK 0xffff
13816#define D2F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
13817#define D2F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
13818#define D2F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
13819#define D2F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
13820#define D2F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
13821#define D2F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
13822#define D2F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
13823#define D2F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
13824#define D2F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
13825#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
13826#define D2F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
13827#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
13828#define D2F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
13829#define D2F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
13830#define D2F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
13831#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
13832#define D2F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
13833#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
13834#define D2F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
13835#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
13836#define D2F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
13837#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
13838#define D2F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
13839#define D2F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
13840#define D2F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
13841#define D2F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
13842#define D2F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
13843#define D2F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
13844#define D2F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
13845#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
13846#define D2F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
13847#define D2F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
13848#define D2F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
13849#define D2F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
13850#define D2F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
13851#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
13852#define D2F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
13853#define D2F5_MSI_MAP_CAP__EN_MASK 0x10000
13854#define D2F5_MSI_MAP_CAP__EN__SHIFT 0x10
13855#define D2F5_MSI_MAP_CAP__FIXD_MASK 0x20000
13856#define D2F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
13857#define D2F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
13858#define D2F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
13859#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
13860#define D2F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
13861#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
13862#define D2F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
13863#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
13864#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
13865#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
13866#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
13867#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
13868#define D2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
13869#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
13870#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
13871#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
13872#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
13873#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
13874#define D2F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
13875#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
13876#define D2F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
13877#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
13878#define D2F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
13879#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
13880#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
13881#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
13882#define D2F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
13883#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
13884#define D2F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
13885#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
13886#define D2F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
13887#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
13888#define D2F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
13889#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
13890#define D2F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
13891#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
13892#define D2F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
13893#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
13894#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
13895#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
13896#define D2F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
13897#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
13898#define D2F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
13899#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
13900#define D2F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
13901#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
13902#define D2F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
13903#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
13904#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
13905#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
13906#define D2F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
13907#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
13908#define D2F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
13909#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
13910#define D2F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
13911#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
13912#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
13913#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
13914#define D2F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
13915#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
13916#define D2F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
13917#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
13918#define D2F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
13919#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
13920#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
13921#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
13922#define D2F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
13923#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
13924#define D2F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
13925#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
13926#define D2F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
13927#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
13928#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
13929#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
13930#define D2F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
13931#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
13932#define D2F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
13933#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
13934#define D2F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
13935#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
13936#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
13937#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
13938#define D2F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
13939#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
13940#define D2F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
13941#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
13942#define D2F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
13943#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
13944#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
13945#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
13946#define D2F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
13947#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
13948#define D2F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
13949#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
13950#define D2F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
13951#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
13952#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
13953#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
13954#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
13955#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
13956#define D2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
13957#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
13958#define D2F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
13959#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
13960#define D2F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
13961#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
13962#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
13963#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
13964#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
13965#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
13966#define D2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
13967#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
13968#define D2F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
13969#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
13970#define D2F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
13971#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
13972#define D2F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
13973#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
13974#define D2F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
13975#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
13976#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
13977#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
13978#define D2F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
13979#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
13980#define D2F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
13981#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
13982#define D2F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
13983#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
13984#define D2F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
13985#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
13986#define D2F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
13987#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
13988#define D2F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
13989#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
13990#define D2F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
13991#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
13992#define D2F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
13993#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
13994#define D2F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
13995#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
13996#define D2F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
13997#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
13998#define D2F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
13999#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
14000#define D2F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
14001#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
14002#define D2F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
14003#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
14004#define D2F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
14005#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
14006#define D2F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
14007#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
14008#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
14009#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
14010#define D2F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
14011#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
14012#define D2F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
14013#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
14014#define D2F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
14015#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
14016#define D2F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
14017#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
14018#define D2F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
14019#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
14020#define D2F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
14021#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
14022#define D2F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
14023#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
14024#define D2F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
14025#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
14026#define D2F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
14027#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
14028#define D2F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
14029#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
14030#define D2F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
14031#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
14032#define D2F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
14033#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
14034#define D2F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
14035#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
14036#define D2F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
14037#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
14038#define D2F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
14039#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
14040#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
14041#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
14042#define D2F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
14043#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
14044#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
14045#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
14046#define D2F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
14047#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
14048#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
14049#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
14050#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
14051#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
14052#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
14053#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
14054#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
14055#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
14056#define D2F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
14057#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
14058#define D2F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
14059#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
14060#define D2F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
14061#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
14062#define D2F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
14063#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
14064#define D2F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
14065#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
14066#define D2F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
14067#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
14068#define D2F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
14069#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
14070#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
14071#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
14072#define D2F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
14073#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
14074#define D2F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
14075#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
14076#define D2F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
14077#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
14078#define D2F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
14079#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
14080#define D2F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
14081#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
14082#define D2F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
14083#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
14084#define D2F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
14085#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
14086#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
14087#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
14088#define D2F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
14089#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
14090#define D2F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
14091#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
14092#define D2F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
14093#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
14094#define D2F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
14095#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
14096#define D2F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
14097#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
14098#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
14099#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
14100#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
14101#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
14102#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
14103#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
14104#define D2F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
14105#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
14106#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
14107#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
14108#define D2F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
14109#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
14110#define D2F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
14111#define D2F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
14112#define D2F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
14113#define D2F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
14114#define D2F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
14115#define D2F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
14116#define D2F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
14117#define D2F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
14118#define D2F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
14119#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
14120#define D2F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
14121#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
14122#define D2F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
14123#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
14124#define D2F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
14125#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
14126#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
14127#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
14128#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
14129#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
14130#define D2F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
14131#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
14132#define D2F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
14133#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
14134#define D2F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
14135#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
14136#define D2F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
14137#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
14138#define D2F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
14139#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
14140#define D2F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
14141#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
14142#define D2F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
14143#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
14144#define D2F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
14145#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
14146#define D2F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
14147#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
14148#define D2F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
14149#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
14150#define D2F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
14151#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
14152#define D2F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
14153#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
14154#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
14155#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
14156#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
14157#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
14158#define D2F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
14159#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
14160#define D2F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
14161#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
14162#define D2F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
14163#define D2F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
14164#define D2F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
14165#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
14166#define D2F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
14167#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
14168#define D2F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
14169#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14170#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14171#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14172#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14173#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14174#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14175#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14176#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14177#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14178#define D2F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14179#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14180#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14181#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14182#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14183#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14184#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14185#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14186#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14187#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14188#define D2F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14189#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14190#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14191#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14192#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14193#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14194#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14195#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14196#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14197#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14198#define D2F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14199#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14200#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14201#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14202#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14203#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14204#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14205#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14206#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14207#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14208#define D2F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14209#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14210#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14211#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14212#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14213#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14214#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14215#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14216#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14217#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14218#define D2F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14219#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14220#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14221#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14222#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14223#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14224#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14225#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14226#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14227#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14228#define D2F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14229#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14230#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14231#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14232#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14233#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14234#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14235#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14236#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14237#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14238#define D2F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14239#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14240#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14241#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14242#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14243#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14244#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14245#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14246#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14247#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14248#define D2F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14249#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14250#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14251#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14252#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14253#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14254#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14255#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14256#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14257#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14258#define D2F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14259#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14260#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14261#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14262#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14263#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14264#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14265#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14266#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14267#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14268#define D2F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14269#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14270#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14271#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14272#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14273#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14274#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14275#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14276#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14277#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14278#define D2F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14279#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14280#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14281#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14282#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14283#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14284#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14285#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14286#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14287#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14288#define D2F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14289#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14290#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14291#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14292#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14293#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14294#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14295#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14296#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14297#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14298#define D2F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14299#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14300#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14301#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14302#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14303#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14304#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14305#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14306#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14307#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14308#define D2F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14309#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
14310#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
14311#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
14312#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
14313#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
14314#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
14315#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
14316#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
14317#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
14318#define D2F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
14319#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
14320#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
14321#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
14322#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
14323#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
14324#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
14325#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
14326#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
14327#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
14328#define D2F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
14329#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
14330#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
14331#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
14332#define D2F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
14333#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
14334#define D2F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
14335#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
14336#define D2F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
14337#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
14338#define D2F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
14339#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
14340#define D2F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
14341#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
14342#define D2F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
14343#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
14344#define D2F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
14345#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
14346#define D2F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
14347#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
14348#define D2F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
14349#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
14350#define D2F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
14351#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
14352#define D2F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
14353#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
14354#define D2F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
14355#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
14356#define D2F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
14357#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
14358#define D2F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
14359#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
14360#define D2F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
14361#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
14362#define D2F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
14363#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
14364#define D2F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
14365#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
14366#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
14367#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
14368#define D2F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
14369#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
14370#define D2F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
14371#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
14372#define D2F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
14373#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
14374#define D2F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
14375#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
14376#define D2F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
14377#define D2F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
14378#define D2F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
14379#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
14380#define D2F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
14381#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
14382#define D2F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
14383#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
14384#define D2F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
14385#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
14386#define D2F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
14387#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
14388#define D2F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
14389#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
14390#define D2F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
14391#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
14392#define D2F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
14393#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
14394#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
14395#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
14396#define D2F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
14397#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
14398#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
14399#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
14400#define D2F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
14401#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
14402#define D2F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
14403#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
14404#define D3F1_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
14405#define D3F1_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
14406#define D3F1_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
14407#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
14408#define D3F1_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
14409#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
14410#define D3F1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
14411#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
14412#define D3F1_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
14413#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
14414#define D3F1_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
14415#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
14416#define D3F1_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
14417#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
14418#define D3F1_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
14419#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
14420#define D3F1_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
14421#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
14422#define D3F1_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
14423#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
14424#define D3F1_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
14425#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
14426#define D3F1_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
14427#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
14428#define D3F1_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
14429#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
14430#define D3F1_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
14431#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
14432#define D3F1_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
14433#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
14434#define D3F1_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
14435#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
14436#define D3F1_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
14437#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
14438#define D3F1_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
14439#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
14440#define D3F1_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
14441#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
14442#define D3F1_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
14443#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
14444#define D3F1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
14445#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
14446#define D3F1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
14447#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
14448#define D3F1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
14449#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
14450#define D3F1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
14451#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
14452#define D3F1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
14453#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
14454#define D3F1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
14455#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
14456#define D3F1_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
14457#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
14458#define D3F1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
14459#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
14460#define D3F1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
14461#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
14462#define D3F1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
14463#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
14464#define D3F1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
14465#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
14466#define D3F1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
14467#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
14468#define D3F1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
14469#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
14470#define D3F1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
14471#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
14472#define D3F1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
14473#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
14474#define D3F1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
14475#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
14476#define D3F1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
14477#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
14478#define D3F1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
14479#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
14480#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
14481#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
14482#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
14483#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
14484#define D3F1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
14485#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
14486#define D3F1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
14487#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
14488#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
14489#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
14490#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
14491#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
14492#define D3F1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
14493#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
14494#define D3F1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
14495#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
14496#define D3F1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
14497#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
14498#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
14499#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
14500#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
14501#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
14502#define D3F1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
14503#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
14504#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
14505#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
14506#define D3F1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
14507#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
14508#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
14509#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
14510#define D3F1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
14511#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
14512#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
14513#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
14514#define D3F1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
14515#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
14516#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
14517#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
14518#define D3F1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
14519#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
14520#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
14521#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
14522#define D3F1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
14523#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
14524#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
14525#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
14526#define D3F1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
14527#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
14528#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
14529#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
14530#define D3F1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
14531#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
14532#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
14533#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
14534#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
14535#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
14536#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
14537#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
14538#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
14539#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
14540#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
14541#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
14542#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
14543#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
14544#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
14545#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
14546#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
14547#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
14548#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
14549#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
14550#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
14551#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
14552#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
14553#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
14554#define D3F1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
14555#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
14556#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
14557#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
14558#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
14559#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
14560#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
14561#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
14562#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
14563#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
14564#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
14565#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
14566#define D3F1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
14567#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
14568#define D3F1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
14569#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
14570#define D3F1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
14571#define D3F1_PCIE_FC_P__PD_CREDITS_MASK 0xff
14572#define D3F1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
14573#define D3F1_PCIE_FC_P__PH_CREDITS_MASK 0xff00
14574#define D3F1_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
14575#define D3F1_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
14576#define D3F1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
14577#define D3F1_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
14578#define D3F1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
14579#define D3F1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
14580#define D3F1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
14581#define D3F1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
14582#define D3F1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
14583#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
14584#define D3F1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
14585#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
14586#define D3F1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
14587#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
14588#define D3F1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
14589#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
14590#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
14591#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
14592#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
14593#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
14594#define D3F1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
14595#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
14596#define D3F1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
14597#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
14598#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
14599#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
14600#define D3F1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
14601#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
14602#define D3F1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
14603#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
14604#define D3F1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
14605#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
14606#define D3F1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
14607#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
14608#define D3F1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
14609#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
14610#define D3F1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
14611#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
14612#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
14613#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
14614#define D3F1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
14615#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
14616#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
14617#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
14618#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
14619#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
14620#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
14621#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
14622#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
14623#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
14624#define D3F1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
14625#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
14626#define D3F1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
14627#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
14628#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
14629#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
14630#define D3F1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
14631#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
14632#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
14633#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
14634#define D3F1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
14635#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
14636#define D3F1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
14637#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
14638#define D3F1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
14639#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
14640#define D3F1_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
14641#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
14642#define D3F1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
14643#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
14644#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
14645#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
14646#define D3F1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
14647#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
14648#define D3F1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
14649#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
14650#define D3F1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
14651#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
14652#define D3F1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
14653#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
14654#define D3F1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
14655#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
14656#define D3F1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
14657#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
14658#define D3F1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
14659#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
14660#define D3F1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
14661#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
14662#define D3F1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
14663#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
14664#define D3F1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
14665#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
14666#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
14667#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
14668#define D3F1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
14669#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
14670#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
14671#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
14672#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
14673#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
14674#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
14675#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
14676#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
14677#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
14678#define D3F1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
14679#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
14680#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
14681#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
14682#define D3F1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
14683#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
14684#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
14685#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
14686#define D3F1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
14687#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
14688#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
14689#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
14690#define D3F1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
14691#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
14692#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
14693#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
14694#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
14695#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
14696#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
14697#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
14698#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
14699#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
14700#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
14701#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
14702#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
14703#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
14704#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
14705#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
14706#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
14707#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
14708#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
14709#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
14710#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
14711#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
14712#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
14713#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
14714#define D3F1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
14715#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
14716#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
14717#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
14718#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
14719#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
14720#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
14721#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
14722#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
14723#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
14724#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
14725#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
14726#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
14727#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
14728#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
14729#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
14730#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
14731#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
14732#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
14733#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
14734#define D3F1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
14735#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
14736#define D3F1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
14737#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
14738#define D3F1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
14739#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
14740#define D3F1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
14741#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
14742#define D3F1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
14743#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
14744#define D3F1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
14745#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
14746#define D3F1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
14747#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
14748#define D3F1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
14749#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
14750#define D3F1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
14751#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
14752#define D3F1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
14753#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
14754#define D3F1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
14755#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
14756#define D3F1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
14757#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
14758#define D3F1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
14759#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
14760#define D3F1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
14761#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
14762#define D3F1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
14763#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
14764#define D3F1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
14765#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
14766#define D3F1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
14767#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
14768#define D3F1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
14769#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
14770#define D3F1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
14771#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
14772#define D3F1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
14773#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
14774#define D3F1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
14775#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
14776#define D3F1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
14777#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
14778#define D3F1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
14779#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
14780#define D3F1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
14781#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
14782#define D3F1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
14783#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
14784#define D3F1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
14785#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
14786#define D3F1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
14787#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
14788#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
14789#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
14790#define D3F1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
14791#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
14792#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
14793#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
14794#define D3F1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
14795#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
14796#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
14797#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
14798#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
14799#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
14800#define D3F1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
14801#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
14802#define D3F1_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
14803#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
14804#define D3F1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
14805#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
14806#define D3F1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
14807#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
14808#define D3F1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
14809#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
14810#define D3F1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
14811#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
14812#define D3F1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
14813#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
14814#define D3F1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
14815#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
14816#define D3F1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
14817#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
14818#define D3F1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
14819#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
14820#define D3F1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
14821#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
14822#define D3F1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
14823#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
14824#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
14825#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
14826#define D3F1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
14827#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
14828#define D3F1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
14829#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
14830#define D3F1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
14831#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
14832#define D3F1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
14833#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
14834#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
14835#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
14836#define D3F1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
14837#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
14838#define D3F1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
14839#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
14840#define D3F1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
14841#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
14842#define D3F1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
14843#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
14844#define D3F1_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
14845#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
14846#define D3F1_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
14847#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
14848#define D3F1_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
14849#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
14850#define D3F1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
14851#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
14852#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
14853#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
14854#define D3F1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
14855#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
14856#define D3F1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
14857#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
14858#define D3F1_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
14859#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
14860#define D3F1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
14861#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
14862#define D3F1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
14863#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
14864#define D3F1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
14865#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
14866#define D3F1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
14867#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
14868#define D3F1_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
14869#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
14870#define D3F1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
14871#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
14872#define D3F1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
14873#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
14874#define D3F1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
14875#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
14876#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
14877#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
14878#define D3F1_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
14879#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
14880#define D3F1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
14881#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
14882#define D3F1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
14883#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
14884#define D3F1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
14885#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
14886#define D3F1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
14887#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
14888#define D3F1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
14889#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
14890#define D3F1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
14891#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
14892#define D3F1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
14893#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
14894#define D3F1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
14895#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
14896#define D3F1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
14897#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
14898#define D3F1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
14899#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
14900#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
14901#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
14902#define D3F1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
14903#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
14904#define D3F1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
14905#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
14906#define D3F1_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
14907#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
14908#define D3F1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
14909#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
14910#define D3F1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
14911#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
14912#define D3F1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
14913#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
14914#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
14915#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
14916#define D3F1_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
14917#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
14918#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
14919#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
14920#define D3F1_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
14921#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
14922#define D3F1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
14923#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
14924#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
14925#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
14926#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
14927#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
14928#define D3F1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
14929#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
14930#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
14931#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
14932#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
14933#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
14934#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
14935#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
14936#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
14937#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
14938#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
14939#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
14940#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
14941#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
14942#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
14943#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
14944#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
14945#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
14946#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
14947#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
14948#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
14949#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
14950#define D3F1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
14951#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
14952#define D3F1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
14953#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
14954#define D3F1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
14955#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
14956#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
14957#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
14958#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
14959#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
14960#define D3F1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
14961#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
14962#define D3F1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
14963#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
14964#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
14965#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
14966#define D3F1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
14967#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
14968#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
14969#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
14970#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
14971#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
14972#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
14973#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
14974#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
14975#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
14976#define D3F1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
14977#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
14978#define D3F1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
14979#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
14980#define D3F1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
14981#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
14982#define D3F1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
14983#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
14984#define D3F1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
14985#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
14986#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
14987#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
14988#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
14989#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
14990#define D3F1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
14991#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
14992#define D3F1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
14993#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
14994#define D3F1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
14995#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
14996#define D3F1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
14997#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
14998#define D3F1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
14999#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
15000#define D3F1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
15001#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
15002#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
15003#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
15004#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
15005#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
15006#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
15007#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
15008#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
15009#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
15010#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
15011#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
15012#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
15013#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
15014#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
15015#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
15016#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
15017#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
15018#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
15019#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
15020#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
15021#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
15022#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
15023#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
15024#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
15025#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
15026#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
15027#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
15028#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
15029#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
15030#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
15031#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
15032#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
15033#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
15034#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
15035#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
15036#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
15037#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
15038#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
15039#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
15040#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
15041#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
15042#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
15043#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
15044#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
15045#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
15046#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
15047#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
15048#define D3F1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
15049#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
15050#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
15051#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
15052#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
15053#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
15054#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
15055#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
15056#define D3F1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
15057#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
15058#define D3F1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
15059#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
15060#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
15061#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
15062#define D3F1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
15063#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
15064#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
15065#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
15066#define D3F1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
15067#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
15068#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
15069#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
15070#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
15071#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
15072#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
15073#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
15074#define D3F1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
15075#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
15076#define D3F1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
15077#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
15078#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
15079#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
15080#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
15081#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
15082#define D3F1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
15083#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
15084#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
15085#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
15086#define D3F1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
15087#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
15088#define D3F1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
15089#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
15090#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
15091#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
15092#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
15093#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
15094#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
15095#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
15096#define D3F1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
15097#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
15098#define D3F1_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
15099#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
15100#define D3F1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
15101#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
15102#define D3F1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
15103#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
15104#define D3F1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
15105#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
15106#define D3F1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
15107#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
15108#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
15109#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
15110#define D3F1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
15111#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
15112#define D3F1_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
15113#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
15114#define D3F1_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
15115#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
15116#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
15117#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
15118#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
15119#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
15120#define D3F1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
15121#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
15122#define D3F1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
15123#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
15124#define D3F1_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
15125#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
15126#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
15127#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
15128#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
15129#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
15130#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
15131#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
15132#define D3F1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
15133#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
15134#define D3F1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
15135#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
15136#define D3F1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
15137#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
15138#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
15139#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
15140#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
15141#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
15142#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
15143#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
15144#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
15145#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
15146#define D3F1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
15147#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
15148#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
15149#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
15150#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
15151#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
15152#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
15153#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
15154#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
15155#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
15156#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
15157#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
15158#define D3F1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
15159#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
15160#define D3F1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
15161#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
15162#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
15163#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
15164#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
15165#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
15166#define D3F1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
15167#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
15168#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
15169#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
15170#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
15171#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
15172#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
15173#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
15174#define D3F1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
15175#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
15176#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
15177#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
15178#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
15179#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
15180#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
15181#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
15182#define D3F1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
15183#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
15184#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
15185#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
15186#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
15187#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
15188#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
15189#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
15190#define D3F1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
15191#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
15192#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
15193#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
15194#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
15195#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
15196#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
15197#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
15198#define D3F1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
15199#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
15200#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
15201#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
15202#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
15203#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
15204#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
15205#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
15206#define D3F1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
15207#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
15208#define D3F1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
15209#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
15210#define D3F1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
15211#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
15212#define D3F1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
15213#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
15214#define D3F1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
15215#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
15216#define D3F1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
15217#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
15218#define D3F1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
15219#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
15220#define D3F1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
15221#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
15222#define D3F1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
15223#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
15224#define D3F1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
15225#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
15226#define D3F1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
15227#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
15228#define D3F1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
15229#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
15230#define D3F1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
15231#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
15232#define D3F1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
15233#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
15234#define D3F1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
15235#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
15236#define D3F1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
15237#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
15238#define D3F1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
15239#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
15240#define D3F1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
15241#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
15242#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
15243#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
15244#define D3F1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
15245#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
15246#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
15247#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
15248#define D3F1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
15249#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
15250#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
15251#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
15252#define D3F1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
15253#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
15254#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
15255#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
15256#define D3F1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
15257#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
15258#define D3F1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
15259#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
15260#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
15261#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
15262#define D3F1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
15263#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
15264#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
15265#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
15266#define D3F1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
15267#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
15268#define D3F1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
15269#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
15270#define D3F1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
15271#define D3F1_VENDOR_ID__VENDOR_ID_MASK 0xffff
15272#define D3F1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
15273#define D3F1_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
15274#define D3F1_DEVICE_ID__DEVICE_ID__SHIFT 0x10
15275#define D3F1_COMMAND__IO_ACCESS_EN_MASK 0x1
15276#define D3F1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
15277#define D3F1_COMMAND__MEM_ACCESS_EN_MASK 0x2
15278#define D3F1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
15279#define D3F1_COMMAND__BUS_MASTER_EN_MASK 0x4
15280#define D3F1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
15281#define D3F1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
15282#define D3F1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
15283#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
15284#define D3F1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
15285#define D3F1_COMMAND__PAL_SNOOP_EN_MASK 0x20
15286#define D3F1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
15287#define D3F1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
15288#define D3F1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
15289#define D3F1_COMMAND__AD_STEPPING_MASK 0x80
15290#define D3F1_COMMAND__AD_STEPPING__SHIFT 0x7
15291#define D3F1_COMMAND__SERR_EN_MASK 0x100
15292#define D3F1_COMMAND__SERR_EN__SHIFT 0x8
15293#define D3F1_COMMAND__FAST_B2B_EN_MASK 0x200
15294#define D3F1_COMMAND__FAST_B2B_EN__SHIFT 0x9
15295#define D3F1_COMMAND__INT_DIS_MASK 0x400
15296#define D3F1_COMMAND__INT_DIS__SHIFT 0xa
15297#define D3F1_STATUS__INT_STATUS_MASK 0x80000
15298#define D3F1_STATUS__INT_STATUS__SHIFT 0x13
15299#define D3F1_STATUS__CAP_LIST_MASK 0x100000
15300#define D3F1_STATUS__CAP_LIST__SHIFT 0x14
15301#define D3F1_STATUS__PCI_66_EN_MASK 0x200000
15302#define D3F1_STATUS__PCI_66_EN__SHIFT 0x15
15303#define D3F1_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
15304#define D3F1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
15305#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
15306#define D3F1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
15307#define D3F1_STATUS__DEVSEL_TIMING_MASK 0x6000000
15308#define D3F1_STATUS__DEVSEL_TIMING__SHIFT 0x19
15309#define D3F1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
15310#define D3F1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
15311#define D3F1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
15312#define D3F1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
15313#define D3F1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
15314#define D3F1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
15315#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
15316#define D3F1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
15317#define D3F1_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
15318#define D3F1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
15319#define D3F1_REVISION_ID__MINOR_REV_ID_MASK 0xf
15320#define D3F1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
15321#define D3F1_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
15322#define D3F1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
15323#define D3F1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
15324#define D3F1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
15325#define D3F1_SUB_CLASS__SUB_CLASS_MASK 0xff0000
15326#define D3F1_SUB_CLASS__SUB_CLASS__SHIFT 0x10
15327#define D3F1_BASE_CLASS__BASE_CLASS_MASK 0xff000000
15328#define D3F1_BASE_CLASS__BASE_CLASS__SHIFT 0x18
15329#define D3F1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
15330#define D3F1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
15331#define D3F1_LATENCY__LATENCY_TIMER_MASK 0xff00
15332#define D3F1_LATENCY__LATENCY_TIMER__SHIFT 0x8
15333#define D3F1_HEADER__HEADER_TYPE_MASK 0x7f0000
15334#define D3F1_HEADER__HEADER_TYPE__SHIFT 0x10
15335#define D3F1_HEADER__DEVICE_TYPE_MASK 0x800000
15336#define D3F1_HEADER__DEVICE_TYPE__SHIFT 0x17
15337#define D3F1_BIST__BIST_COMP_MASK 0xf000000
15338#define D3F1_BIST__BIST_COMP__SHIFT 0x18
15339#define D3F1_BIST__BIST_STRT_MASK 0x40000000
15340#define D3F1_BIST__BIST_STRT__SHIFT 0x1e
15341#define D3F1_BIST__BIST_CAP_MASK 0x80000000
15342#define D3F1_BIST__BIST_CAP__SHIFT 0x1f
15343#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
15344#define D3F1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
15345#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
15346#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
15347#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
15348#define D3F1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
15349#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
15350#define D3F1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
15351#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
15352#define D3F1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
15353#define D3F1_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
15354#define D3F1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
15355#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
15356#define D3F1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
15357#define D3F1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
15358#define D3F1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
15359#define D3F1_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
15360#define D3F1_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
15361#define D3F1_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
15362#define D3F1_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
15363#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
15364#define D3F1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
15365#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
15366#define D3F1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
15367#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
15368#define D3F1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
15369#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
15370#define D3F1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
15371#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
15372#define D3F1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
15373#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
15374#define D3F1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
15375#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
15376#define D3F1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
15377#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
15378#define D3F1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
15379#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
15380#define D3F1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
15381#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
15382#define D3F1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
15383#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
15384#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
15385#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
15386#define D3F1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
15387#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
15388#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
15389#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
15390#define D3F1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
15391#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
15392#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
15393#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
15394#define D3F1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
15395#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
15396#define D3F1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
15397#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
15398#define D3F1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
15399#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
15400#define D3F1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
15401#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
15402#define D3F1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
15403#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
15404#define D3F1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
15405#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
15406#define D3F1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
15407#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
15408#define D3F1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
15409#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
15410#define D3F1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
15411#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
15412#define D3F1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
15413#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
15414#define D3F1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
15415#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
15416#define D3F1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
15417#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
15418#define D3F1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
15419#define D3F1_CAP_PTR__CAP_PTR_MASK 0xff
15420#define D3F1_CAP_PTR__CAP_PTR__SHIFT 0x0
15421#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
15422#define D3F1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
15423#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
15424#define D3F1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
15425#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
15426#define D3F1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
15427#define D3F1_PMI_CAP_LIST__CAP_ID_MASK 0xff
15428#define D3F1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
15429#define D3F1_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
15430#define D3F1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
15431#define D3F1_PMI_CAP__VERSION_MASK 0x70000
15432#define D3F1_PMI_CAP__VERSION__SHIFT 0x10
15433#define D3F1_PMI_CAP__PME_CLOCK_MASK 0x80000
15434#define D3F1_PMI_CAP__PME_CLOCK__SHIFT 0x13
15435#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
15436#define D3F1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
15437#define D3F1_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
15438#define D3F1_PMI_CAP__AUX_CURRENT__SHIFT 0x16
15439#define D3F1_PMI_CAP__D1_SUPPORT_MASK 0x2000000
15440#define D3F1_PMI_CAP__D1_SUPPORT__SHIFT 0x19
15441#define D3F1_PMI_CAP__D2_SUPPORT_MASK 0x4000000
15442#define D3F1_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
15443#define D3F1_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
15444#define D3F1_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
15445#define D3F1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
15446#define D3F1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
15447#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
15448#define D3F1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
15449#define D3F1_PMI_STATUS_CNTL__PME_EN_MASK 0x100
15450#define D3F1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
15451#define D3F1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
15452#define D3F1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
15453#define D3F1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
15454#define D3F1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
15455#define D3F1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
15456#define D3F1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
15457#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
15458#define D3F1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
15459#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
15460#define D3F1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
15461#define D3F1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
15462#define D3F1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
15463#define D3F1_PCIE_CAP_LIST__CAP_ID_MASK 0xff
15464#define D3F1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
15465#define D3F1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
15466#define D3F1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
15467#define D3F1_PCIE_CAP__VERSION_MASK 0xf0000
15468#define D3F1_PCIE_CAP__VERSION__SHIFT 0x10
15469#define D3F1_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
15470#define D3F1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
15471#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
15472#define D3F1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
15473#define D3F1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
15474#define D3F1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
15475#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
15476#define D3F1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
15477#define D3F1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
15478#define D3F1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
15479#define D3F1_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
15480#define D3F1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
15481#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
15482#define D3F1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
15483#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
15484#define D3F1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
15485#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
15486#define D3F1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
15487#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
15488#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
15489#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
15490#define D3F1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
15491#define D3F1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
15492#define D3F1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
15493#define D3F1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
15494#define D3F1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
15495#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
15496#define D3F1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
15497#define D3F1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
15498#define D3F1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
15499#define D3F1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
15500#define D3F1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
15501#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
15502#define D3F1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
15503#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
15504#define D3F1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
15505#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
15506#define D3F1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
15507#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
15508#define D3F1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
15509#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
15510#define D3F1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
15511#define D3F1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
15512#define D3F1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
15513#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
15514#define D3F1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
15515#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
15516#define D3F1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
15517#define D3F1_DEVICE_STATUS__CORR_ERR_MASK 0x10000
15518#define D3F1_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
15519#define D3F1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
15520#define D3F1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
15521#define D3F1_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
15522#define D3F1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
15523#define D3F1_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
15524#define D3F1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
15525#define D3F1_DEVICE_STATUS__AUX_PWR_MASK 0x100000
15526#define D3F1_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
15527#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
15528#define D3F1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
15529#define D3F1_LINK_CAP__LINK_SPEED_MASK 0xf
15530#define D3F1_LINK_CAP__LINK_SPEED__SHIFT 0x0
15531#define D3F1_LINK_CAP__LINK_WIDTH_MASK 0x3f0
15532#define D3F1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
15533#define D3F1_LINK_CAP__PM_SUPPORT_MASK 0xc00
15534#define D3F1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
15535#define D3F1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
15536#define D3F1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
15537#define D3F1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
15538#define D3F1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
15539#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
15540#define D3F1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
15541#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
15542#define D3F1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
15543#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
15544#define D3F1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
15545#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
15546#define D3F1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
15547#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
15548#define D3F1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
15549#define D3F1_LINK_CAP__PORT_NUMBER_MASK 0xff000000
15550#define D3F1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
15551#define D3F1_LINK_CNTL__PM_CONTROL_MASK 0x3
15552#define D3F1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
15553#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
15554#define D3F1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
15555#define D3F1_LINK_CNTL__LINK_DIS_MASK 0x10
15556#define D3F1_LINK_CNTL__LINK_DIS__SHIFT 0x4
15557#define D3F1_LINK_CNTL__RETRAIN_LINK_MASK 0x20
15558#define D3F1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
15559#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
15560#define D3F1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
15561#define D3F1_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
15562#define D3F1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
15563#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
15564#define D3F1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
15565#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
15566#define D3F1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
15567#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
15568#define D3F1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
15569#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
15570#define D3F1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
15571#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
15572#define D3F1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
15573#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
15574#define D3F1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
15575#define D3F1_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
15576#define D3F1_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
15577#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
15578#define D3F1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
15579#define D3F1_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
15580#define D3F1_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
15581#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
15582#define D3F1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
15583#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
15584#define D3F1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
15585#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
15586#define D3F1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
15587#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
15588#define D3F1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
15589#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
15590#define D3F1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
15591#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
15592#define D3F1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
15593#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
15594#define D3F1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
15595#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
15596#define D3F1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
15597#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
15598#define D3F1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
15599#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
15600#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
15601#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
15602#define D3F1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
15603#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
15604#define D3F1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
15605#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
15606#define D3F1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
15607#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
15608#define D3F1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
15609#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
15610#define D3F1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
15611#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
15612#define D3F1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
15613#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
15614#define D3F1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
15615#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
15616#define D3F1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
15617#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
15618#define D3F1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
15619#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
15620#define D3F1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
15621#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
15622#define D3F1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
15623#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
15624#define D3F1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
15625#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
15626#define D3F1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
15627#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
15628#define D3F1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
15629#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
15630#define D3F1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
15631#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
15632#define D3F1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
15633#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
15634#define D3F1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
15635#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
15636#define D3F1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
15637#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
15638#define D3F1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
15639#define D3F1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
15640#define D3F1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
15641#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
15642#define D3F1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
15643#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
15644#define D3F1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
15645#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
15646#define D3F1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
15647#define D3F1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
15648#define D3F1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
15649#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
15650#define D3F1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
15651#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
15652#define D3F1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
15653#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
15654#define D3F1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
15655#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
15656#define D3F1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
15657#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
15658#define D3F1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
15659#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
15660#define D3F1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
15661#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
15662#define D3F1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
15663#define D3F1_ROOT_STATUS__PME_STATUS_MASK 0x10000
15664#define D3F1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
15665#define D3F1_ROOT_STATUS__PME_PENDING_MASK 0x20000
15666#define D3F1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
15667#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
15668#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
15669#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
15670#define D3F1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
15671#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
15672#define D3F1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
15673#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
15674#define D3F1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
15675#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
15676#define D3F1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
15677#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
15678#define D3F1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
15679#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
15680#define D3F1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
15681#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
15682#define D3F1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
15683#define D3F1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
15684#define D3F1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
15685#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
15686#define D3F1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
15687#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
15688#define D3F1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
15689#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
15690#define D3F1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
15691#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
15692#define D3F1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
15693#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
15694#define D3F1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
15695#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
15696#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
15697#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
15698#define D3F1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
15699#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
15700#define D3F1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
15701#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
15702#define D3F1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
15703#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
15704#define D3F1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
15705#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
15706#define D3F1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
15707#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
15708#define D3F1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
15709#define D3F1_DEVICE_CNTL2__LTR_EN_MASK 0x400
15710#define D3F1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
15711#define D3F1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
15712#define D3F1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
15713#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
15714#define D3F1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
15715#define D3F1_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
15716#define D3F1_DEVICE_STATUS2__RESERVED__SHIFT 0x10
15717#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
15718#define D3F1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
15719#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
15720#define D3F1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
15721#define D3F1_LINK_CAP2__RESERVED_MASK 0xfffffe00
15722#define D3F1_LINK_CAP2__RESERVED__SHIFT 0x9
15723#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
15724#define D3F1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
15725#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
15726#define D3F1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
15727#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
15728#define D3F1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
15729#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
15730#define D3F1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
15731#define D3F1_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
15732#define D3F1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
15733#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
15734#define D3F1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
15735#define D3F1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
15736#define D3F1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
15737#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
15738#define D3F1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
15739#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
15740#define D3F1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
15741#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
15742#define D3F1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
15743#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
15744#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
15745#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
15746#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
15747#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
15748#define D3F1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
15749#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
15750#define D3F1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
15751#define D3F1_SLOT_CAP2__RESERVED_MASK 0xffffffff
15752#define D3F1_SLOT_CAP2__RESERVED__SHIFT 0x0
15753#define D3F1_SLOT_CNTL2__RESERVED_MASK 0xffff
15754#define D3F1_SLOT_CNTL2__RESERVED__SHIFT 0x0
15755#define D3F1_SLOT_STATUS2__RESERVED_MASK 0xffff0000
15756#define D3F1_SLOT_STATUS2__RESERVED__SHIFT 0x10
15757#define D3F1_MSI_CAP_LIST__CAP_ID_MASK 0xff
15758#define D3F1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
15759#define D3F1_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
15760#define D3F1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
15761#define D3F1_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
15762#define D3F1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
15763#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
15764#define D3F1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
15765#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
15766#define D3F1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
15767#define D3F1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
15768#define D3F1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
15769#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
15770#define D3F1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
15771#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
15772#define D3F1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
15773#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
15774#define D3F1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
15775#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
15776#define D3F1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
15777#define D3F1_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
15778#define D3F1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
15779#define D3F1_SSID_CAP_LIST__CAP_ID_MASK 0xff
15780#define D3F1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
15781#define D3F1_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
15782#define D3F1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
15783#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
15784#define D3F1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
15785#define D3F1_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
15786#define D3F1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
15787#define D3F1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
15788#define D3F1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
15789#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
15790#define D3F1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
15791#define D3F1_MSI_MAP_CAP__EN_MASK 0x10000
15792#define D3F1_MSI_MAP_CAP__EN__SHIFT 0x10
15793#define D3F1_MSI_MAP_CAP__FIXD_MASK 0x20000
15794#define D3F1_MSI_MAP_CAP__FIXD__SHIFT 0x11
15795#define D3F1_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
15796#define D3F1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
15797#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
15798#define D3F1_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
15799#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
15800#define D3F1_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
15801#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
15802#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
15803#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
15804#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
15805#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
15806#define D3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
15807#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
15808#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
15809#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
15810#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
15811#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
15812#define D3F1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
15813#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
15814#define D3F1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
15815#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
15816#define D3F1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
15817#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
15818#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
15819#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
15820#define D3F1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
15821#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
15822#define D3F1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
15823#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
15824#define D3F1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
15825#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
15826#define D3F1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
15827#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
15828#define D3F1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
15829#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
15830#define D3F1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
15831#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
15832#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
15833#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
15834#define D3F1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
15835#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
15836#define D3F1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
15837#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
15838#define D3F1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
15839#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
15840#define D3F1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
15841#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
15842#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
15843#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
15844#define D3F1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
15845#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
15846#define D3F1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
15847#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
15848#define D3F1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
15849#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
15850#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
15851#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
15852#define D3F1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
15853#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
15854#define D3F1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
15855#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
15856#define D3F1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
15857#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
15858#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
15859#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
15860#define D3F1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
15861#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
15862#define D3F1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
15863#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
15864#define D3F1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
15865#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
15866#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
15867#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
15868#define D3F1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
15869#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
15870#define D3F1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
15871#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
15872#define D3F1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
15873#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
15874#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
15875#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
15876#define D3F1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
15877#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
15878#define D3F1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
15879#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
15880#define D3F1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
15881#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
15882#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
15883#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
15884#define D3F1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
15885#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
15886#define D3F1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
15887#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
15888#define D3F1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
15889#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
15890#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
15891#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
15892#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
15893#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
15894#define D3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
15895#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
15896#define D3F1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
15897#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
15898#define D3F1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
15899#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
15900#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
15901#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
15902#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
15903#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
15904#define D3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
15905#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
15906#define D3F1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
15907#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
15908#define D3F1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
15909#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
15910#define D3F1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
15911#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
15912#define D3F1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
15913#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
15914#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
15915#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
15916#define D3F1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
15917#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
15918#define D3F1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
15919#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
15920#define D3F1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
15921#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
15922#define D3F1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
15923#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
15924#define D3F1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
15925#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
15926#define D3F1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
15927#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
15928#define D3F1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
15929#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
15930#define D3F1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
15931#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
15932#define D3F1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
15933#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
15934#define D3F1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
15935#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
15936#define D3F1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
15937#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
15938#define D3F1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
15939#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
15940#define D3F1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
15941#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
15942#define D3F1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
15943#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
15944#define D3F1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
15945#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
15946#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
15947#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
15948#define D3F1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
15949#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
15950#define D3F1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
15951#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
15952#define D3F1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
15953#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
15954#define D3F1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
15955#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
15956#define D3F1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
15957#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
15958#define D3F1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
15959#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
15960#define D3F1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
15961#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
15962#define D3F1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
15963#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
15964#define D3F1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
15965#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
15966#define D3F1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
15967#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
15968#define D3F1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
15969#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
15970#define D3F1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
15971#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
15972#define D3F1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
15973#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
15974#define D3F1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
15975#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
15976#define D3F1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
15977#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
15978#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
15979#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
15980#define D3F1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
15981#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
15982#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
15983#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
15984#define D3F1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
15985#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
15986#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
15987#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
15988#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
15989#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
15990#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
15991#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
15992#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
15993#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
15994#define D3F1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
15995#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
15996#define D3F1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
15997#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
15998#define D3F1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
15999#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
16000#define D3F1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
16001#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
16002#define D3F1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
16003#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
16004#define D3F1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
16005#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
16006#define D3F1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
16007#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
16008#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
16009#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
16010#define D3F1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
16011#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
16012#define D3F1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
16013#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
16014#define D3F1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
16015#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
16016#define D3F1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
16017#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
16018#define D3F1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
16019#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
16020#define D3F1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
16021#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
16022#define D3F1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
16023#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
16024#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
16025#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
16026#define D3F1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
16027#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
16028#define D3F1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
16029#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
16030#define D3F1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
16031#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
16032#define D3F1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
16033#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
16034#define D3F1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
16035#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
16036#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
16037#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
16038#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
16039#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
16040#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
16041#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
16042#define D3F1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
16043#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
16044#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
16045#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
16046#define D3F1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
16047#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
16048#define D3F1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
16049#define D3F1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
16050#define D3F1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
16051#define D3F1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
16052#define D3F1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
16053#define D3F1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
16054#define D3F1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
16055#define D3F1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
16056#define D3F1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
16057#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
16058#define D3F1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
16059#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
16060#define D3F1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
16061#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
16062#define D3F1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
16063#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
16064#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
16065#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
16066#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
16067#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
16068#define D3F1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
16069#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
16070#define D3F1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
16071#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
16072#define D3F1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
16073#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
16074#define D3F1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
16075#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
16076#define D3F1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
16077#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
16078#define D3F1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
16079#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
16080#define D3F1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
16081#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
16082#define D3F1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
16083#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
16084#define D3F1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
16085#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
16086#define D3F1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
16087#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
16088#define D3F1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
16089#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
16090#define D3F1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
16091#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
16092#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
16093#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
16094#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
16095#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
16096#define D3F1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
16097#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
16098#define D3F1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
16099#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
16100#define D3F1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
16101#define D3F1_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
16102#define D3F1_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
16103#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
16104#define D3F1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
16105#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
16106#define D3F1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
16107#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16108#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16109#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16110#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16111#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16112#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16113#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16114#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16115#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16116#define D3F1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16117#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16118#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16119#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16120#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16121#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16122#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16123#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16124#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16125#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16126#define D3F1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16127#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16128#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16129#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16130#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16131#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16132#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16133#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16134#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16135#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16136#define D3F1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16137#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16138#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16139#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16140#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16141#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16142#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16143#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16144#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16145#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16146#define D3F1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16147#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16148#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16149#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16150#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16151#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16152#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16153#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16154#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16155#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16156#define D3F1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16157#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16158#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16159#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16160#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16161#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16162#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16163#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16164#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16165#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16166#define D3F1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16167#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16168#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16169#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16170#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16171#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16172#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16173#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16174#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16175#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16176#define D3F1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16177#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16178#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16179#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16180#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16181#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16182#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16183#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16184#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16185#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16186#define D3F1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16187#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16188#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16189#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16190#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16191#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16192#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16193#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16194#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16195#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16196#define D3F1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16197#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16198#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16199#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16200#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16201#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16202#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16203#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16204#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16205#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16206#define D3F1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16207#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16208#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16209#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16210#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16211#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16212#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16213#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16214#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16215#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16216#define D3F1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16217#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16218#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16219#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16220#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16221#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16222#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16223#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16224#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16225#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16226#define D3F1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16227#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16228#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16229#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16230#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16231#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16232#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16233#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16234#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16235#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16236#define D3F1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16237#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16238#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16239#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16240#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16241#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16242#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16243#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16244#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16245#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16246#define D3F1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16247#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
16248#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
16249#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
16250#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
16251#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
16252#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
16253#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
16254#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
16255#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
16256#define D3F1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
16257#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
16258#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
16259#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
16260#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
16261#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
16262#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
16263#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
16264#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
16265#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
16266#define D3F1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
16267#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
16268#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
16269#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
16270#define D3F1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
16271#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
16272#define D3F1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
16273#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
16274#define D3F1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
16275#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
16276#define D3F1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
16277#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
16278#define D3F1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
16279#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
16280#define D3F1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
16281#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
16282#define D3F1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
16283#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
16284#define D3F1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
16285#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
16286#define D3F1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
16287#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
16288#define D3F1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
16289#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
16290#define D3F1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
16291#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
16292#define D3F1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
16293#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
16294#define D3F1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
16295#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
16296#define D3F1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
16297#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
16298#define D3F1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
16299#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
16300#define D3F1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
16301#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
16302#define D3F1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
16303#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
16304#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
16305#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
16306#define D3F1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
16307#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
16308#define D3F1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
16309#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
16310#define D3F1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
16311#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
16312#define D3F1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
16313#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
16314#define D3F1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
16315#define D3F1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
16316#define D3F1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
16317#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
16318#define D3F1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
16319#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
16320#define D3F1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
16321#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
16322#define D3F1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
16323#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
16324#define D3F1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
16325#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
16326#define D3F1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
16327#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
16328#define D3F1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
16329#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
16330#define D3F1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
16331#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
16332#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
16333#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
16334#define D3F1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
16335#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
16336#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
16337#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
16338#define D3F1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
16339#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
16340#define D3F1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
16341#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
16342#define D3F2_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
16343#define D3F2_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
16344#define D3F2_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
16345#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
16346#define D3F2_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
16347#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
16348#define D3F2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
16349#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
16350#define D3F2_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
16351#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
16352#define D3F2_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
16353#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
16354#define D3F2_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
16355#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
16356#define D3F2_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
16357#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
16358#define D3F2_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
16359#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
16360#define D3F2_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
16361#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
16362#define D3F2_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
16363#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
16364#define D3F2_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
16365#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
16366#define D3F2_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
16367#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
16368#define D3F2_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
16369#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
16370#define D3F2_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
16371#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
16372#define D3F2_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
16373#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
16374#define D3F2_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
16375#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
16376#define D3F2_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
16377#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
16378#define D3F2_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
16379#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
16380#define D3F2_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
16381#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
16382#define D3F2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
16383#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
16384#define D3F2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
16385#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
16386#define D3F2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
16387#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
16388#define D3F2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
16389#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
16390#define D3F2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
16391#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
16392#define D3F2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
16393#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
16394#define D3F2_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
16395#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
16396#define D3F2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
16397#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
16398#define D3F2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
16399#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
16400#define D3F2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
16401#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
16402#define D3F2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
16403#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
16404#define D3F2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
16405#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
16406#define D3F2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
16407#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
16408#define D3F2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
16409#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
16410#define D3F2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
16411#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
16412#define D3F2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
16413#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
16414#define D3F2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
16415#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
16416#define D3F2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
16417#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
16418#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
16419#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
16420#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
16421#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
16422#define D3F2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
16423#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
16424#define D3F2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
16425#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
16426#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
16427#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
16428#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
16429#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
16430#define D3F2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
16431#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
16432#define D3F2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
16433#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
16434#define D3F2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
16435#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
16436#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
16437#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
16438#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
16439#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
16440#define D3F2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
16441#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
16442#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
16443#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
16444#define D3F2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
16445#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
16446#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
16447#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
16448#define D3F2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
16449#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
16450#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
16451#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
16452#define D3F2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
16453#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
16454#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
16455#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
16456#define D3F2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
16457#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
16458#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
16459#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
16460#define D3F2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
16461#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
16462#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
16463#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
16464#define D3F2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
16465#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
16466#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
16467#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
16468#define D3F2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
16469#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
16470#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
16471#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
16472#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
16473#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
16474#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
16475#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
16476#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
16477#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
16478#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
16479#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
16480#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
16481#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
16482#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
16483#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
16484#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
16485#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
16486#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
16487#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
16488#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
16489#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
16490#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
16491#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
16492#define D3F2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
16493#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
16494#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
16495#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
16496#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
16497#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
16498#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
16499#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
16500#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
16501#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
16502#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
16503#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
16504#define D3F2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
16505#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
16506#define D3F2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
16507#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
16508#define D3F2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
16509#define D3F2_PCIE_FC_P__PD_CREDITS_MASK 0xff
16510#define D3F2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
16511#define D3F2_PCIE_FC_P__PH_CREDITS_MASK 0xff00
16512#define D3F2_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
16513#define D3F2_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
16514#define D3F2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
16515#define D3F2_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
16516#define D3F2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
16517#define D3F2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
16518#define D3F2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
16519#define D3F2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
16520#define D3F2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
16521#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
16522#define D3F2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
16523#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
16524#define D3F2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
16525#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
16526#define D3F2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
16527#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
16528#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
16529#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
16530#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
16531#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
16532#define D3F2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
16533#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
16534#define D3F2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
16535#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
16536#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
16537#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
16538#define D3F2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
16539#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
16540#define D3F2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
16541#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
16542#define D3F2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
16543#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
16544#define D3F2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
16545#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
16546#define D3F2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
16547#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
16548#define D3F2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
16549#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
16550#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
16551#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
16552#define D3F2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
16553#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
16554#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
16555#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
16556#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
16557#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
16558#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
16559#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
16560#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
16561#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
16562#define D3F2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
16563#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
16564#define D3F2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
16565#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
16566#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
16567#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
16568#define D3F2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
16569#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
16570#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
16571#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
16572#define D3F2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
16573#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
16574#define D3F2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
16575#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
16576#define D3F2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
16577#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
16578#define D3F2_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
16579#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
16580#define D3F2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
16581#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
16582#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
16583#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
16584#define D3F2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
16585#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
16586#define D3F2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
16587#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
16588#define D3F2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
16589#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
16590#define D3F2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
16591#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
16592#define D3F2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
16593#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
16594#define D3F2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
16595#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
16596#define D3F2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
16597#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
16598#define D3F2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
16599#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
16600#define D3F2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
16601#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
16602#define D3F2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
16603#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
16604#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
16605#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
16606#define D3F2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
16607#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
16608#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
16609#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
16610#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
16611#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
16612#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
16613#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
16614#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
16615#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
16616#define D3F2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
16617#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
16618#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
16619#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
16620#define D3F2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
16621#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
16622#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
16623#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
16624#define D3F2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
16625#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
16626#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
16627#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
16628#define D3F2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
16629#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
16630#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
16631#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
16632#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
16633#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
16634#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
16635#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
16636#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
16637#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
16638#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
16639#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
16640#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
16641#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
16642#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
16643#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
16644#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
16645#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
16646#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
16647#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
16648#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
16649#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
16650#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
16651#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
16652#define D3F2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
16653#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
16654#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
16655#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
16656#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
16657#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
16658#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
16659#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
16660#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
16661#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
16662#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
16663#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
16664#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
16665#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
16666#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
16667#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
16668#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
16669#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
16670#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
16671#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
16672#define D3F2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
16673#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
16674#define D3F2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
16675#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
16676#define D3F2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
16677#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
16678#define D3F2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
16679#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
16680#define D3F2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
16681#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
16682#define D3F2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
16683#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
16684#define D3F2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
16685#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
16686#define D3F2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
16687#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
16688#define D3F2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
16689#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
16690#define D3F2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
16691#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
16692#define D3F2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
16693#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
16694#define D3F2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
16695#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
16696#define D3F2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
16697#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
16698#define D3F2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
16699#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
16700#define D3F2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
16701#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
16702#define D3F2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
16703#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
16704#define D3F2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
16705#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
16706#define D3F2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
16707#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
16708#define D3F2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
16709#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
16710#define D3F2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
16711#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
16712#define D3F2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
16713#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
16714#define D3F2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
16715#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
16716#define D3F2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
16717#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
16718#define D3F2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
16719#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
16720#define D3F2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
16721#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
16722#define D3F2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
16723#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
16724#define D3F2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
16725#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
16726#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
16727#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
16728#define D3F2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
16729#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
16730#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
16731#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
16732#define D3F2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
16733#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
16734#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
16735#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
16736#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
16737#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
16738#define D3F2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
16739#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
16740#define D3F2_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
16741#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
16742#define D3F2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
16743#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
16744#define D3F2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
16745#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
16746#define D3F2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
16747#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
16748#define D3F2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
16749#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
16750#define D3F2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
16751#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
16752#define D3F2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
16753#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
16754#define D3F2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
16755#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
16756#define D3F2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
16757#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
16758#define D3F2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
16759#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
16760#define D3F2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
16761#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
16762#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
16763#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
16764#define D3F2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
16765#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
16766#define D3F2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
16767#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
16768#define D3F2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
16769#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
16770#define D3F2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
16771#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
16772#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
16773#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
16774#define D3F2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
16775#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
16776#define D3F2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
16777#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
16778#define D3F2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
16779#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
16780#define D3F2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
16781#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
16782#define D3F2_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
16783#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
16784#define D3F2_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
16785#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
16786#define D3F2_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
16787#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
16788#define D3F2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
16789#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
16790#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
16791#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
16792#define D3F2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
16793#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
16794#define D3F2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
16795#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
16796#define D3F2_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
16797#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
16798#define D3F2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
16799#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
16800#define D3F2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
16801#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
16802#define D3F2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
16803#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
16804#define D3F2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
16805#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
16806#define D3F2_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
16807#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
16808#define D3F2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
16809#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
16810#define D3F2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
16811#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
16812#define D3F2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
16813#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
16814#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
16815#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
16816#define D3F2_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
16817#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
16818#define D3F2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
16819#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
16820#define D3F2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
16821#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
16822#define D3F2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
16823#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
16824#define D3F2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
16825#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
16826#define D3F2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
16827#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
16828#define D3F2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
16829#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
16830#define D3F2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
16831#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
16832#define D3F2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
16833#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
16834#define D3F2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
16835#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
16836#define D3F2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
16837#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
16838#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
16839#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
16840#define D3F2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
16841#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
16842#define D3F2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
16843#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
16844#define D3F2_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
16845#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
16846#define D3F2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
16847#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
16848#define D3F2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
16849#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
16850#define D3F2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
16851#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
16852#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
16853#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
16854#define D3F2_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
16855#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
16856#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
16857#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
16858#define D3F2_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
16859#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
16860#define D3F2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
16861#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
16862#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
16863#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
16864#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
16865#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
16866#define D3F2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
16867#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
16868#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
16869#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
16870#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
16871#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
16872#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
16873#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
16874#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
16875#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
16876#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
16877#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
16878#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
16879#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
16880#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
16881#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
16882#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
16883#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
16884#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
16885#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
16886#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
16887#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
16888#define D3F2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
16889#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
16890#define D3F2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
16891#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
16892#define D3F2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
16893#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
16894#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
16895#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
16896#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
16897#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
16898#define D3F2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
16899#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
16900#define D3F2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
16901#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
16902#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
16903#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
16904#define D3F2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
16905#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
16906#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
16907#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
16908#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
16909#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
16910#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
16911#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
16912#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
16913#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
16914#define D3F2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
16915#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
16916#define D3F2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
16917#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
16918#define D3F2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
16919#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
16920#define D3F2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
16921#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
16922#define D3F2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
16923#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
16924#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
16925#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
16926#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
16927#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
16928#define D3F2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
16929#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
16930#define D3F2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
16931#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
16932#define D3F2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
16933#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
16934#define D3F2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
16935#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
16936#define D3F2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
16937#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
16938#define D3F2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
16939#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
16940#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
16941#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
16942#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
16943#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
16944#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
16945#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
16946#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
16947#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
16948#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
16949#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
16950#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
16951#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
16952#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
16953#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
16954#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
16955#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
16956#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
16957#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
16958#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
16959#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
16960#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
16961#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
16962#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
16963#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
16964#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
16965#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
16966#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
16967#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
16968#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
16969#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
16970#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
16971#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
16972#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
16973#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
16974#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
16975#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
16976#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
16977#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
16978#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
16979#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
16980#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
16981#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
16982#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
16983#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
16984#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
16985#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
16986#define D3F2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
16987#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
16988#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
16989#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
16990#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
16991#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
16992#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
16993#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
16994#define D3F2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
16995#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
16996#define D3F2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
16997#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
16998#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
16999#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
17000#define D3F2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
17001#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
17002#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
17003#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
17004#define D3F2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
17005#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
17006#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
17007#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
17008#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
17009#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
17010#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
17011#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
17012#define D3F2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
17013#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
17014#define D3F2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
17015#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
17016#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
17017#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
17018#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
17019#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
17020#define D3F2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
17021#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
17022#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
17023#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
17024#define D3F2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
17025#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
17026#define D3F2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
17027#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
17028#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
17029#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
17030#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
17031#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
17032#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
17033#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
17034#define D3F2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
17035#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
17036#define D3F2_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
17037#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
17038#define D3F2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
17039#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
17040#define D3F2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
17041#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
17042#define D3F2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
17043#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
17044#define D3F2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
17045#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
17046#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
17047#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
17048#define D3F2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
17049#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
17050#define D3F2_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
17051#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
17052#define D3F2_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
17053#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
17054#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
17055#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
17056#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
17057#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
17058#define D3F2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
17059#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
17060#define D3F2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
17061#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
17062#define D3F2_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
17063#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
17064#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
17065#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
17066#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
17067#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
17068#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
17069#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
17070#define D3F2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
17071#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
17072#define D3F2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
17073#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
17074#define D3F2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
17075#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
17076#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
17077#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
17078#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
17079#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
17080#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
17081#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
17082#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
17083#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
17084#define D3F2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
17085#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
17086#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
17087#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
17088#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
17089#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
17090#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
17091#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
17092#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
17093#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
17094#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
17095#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
17096#define D3F2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
17097#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
17098#define D3F2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
17099#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
17100#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
17101#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
17102#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
17103#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
17104#define D3F2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
17105#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
17106#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
17107#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
17108#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
17109#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
17110#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
17111#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
17112#define D3F2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
17113#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
17114#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
17115#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
17116#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
17117#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
17118#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
17119#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
17120#define D3F2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
17121#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
17122#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
17123#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
17124#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
17125#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
17126#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
17127#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
17128#define D3F2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
17129#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
17130#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
17131#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
17132#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
17133#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
17134#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
17135#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
17136#define D3F2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
17137#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
17138#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
17139#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
17140#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
17141#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
17142#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
17143#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
17144#define D3F2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
17145#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
17146#define D3F2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
17147#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
17148#define D3F2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
17149#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
17150#define D3F2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
17151#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
17152#define D3F2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
17153#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
17154#define D3F2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
17155#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
17156#define D3F2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
17157#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
17158#define D3F2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
17159#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
17160#define D3F2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
17161#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
17162#define D3F2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
17163#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
17164#define D3F2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
17165#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
17166#define D3F2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
17167#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
17168#define D3F2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
17169#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
17170#define D3F2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
17171#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
17172#define D3F2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
17173#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
17174#define D3F2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
17175#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
17176#define D3F2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
17177#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
17178#define D3F2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
17179#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
17180#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
17181#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
17182#define D3F2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
17183#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
17184#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
17185#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
17186#define D3F2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
17187#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
17188#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
17189#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
17190#define D3F2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
17191#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
17192#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
17193#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
17194#define D3F2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
17195#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
17196#define D3F2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
17197#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
17198#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
17199#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
17200#define D3F2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
17201#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
17202#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
17203#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
17204#define D3F2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
17205#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
17206#define D3F2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
17207#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
17208#define D3F2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
17209#define D3F2_VENDOR_ID__VENDOR_ID_MASK 0xffff
17210#define D3F2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
17211#define D3F2_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
17212#define D3F2_DEVICE_ID__DEVICE_ID__SHIFT 0x10
17213#define D3F2_COMMAND__IO_ACCESS_EN_MASK 0x1
17214#define D3F2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
17215#define D3F2_COMMAND__MEM_ACCESS_EN_MASK 0x2
17216#define D3F2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
17217#define D3F2_COMMAND__BUS_MASTER_EN_MASK 0x4
17218#define D3F2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
17219#define D3F2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
17220#define D3F2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
17221#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
17222#define D3F2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
17223#define D3F2_COMMAND__PAL_SNOOP_EN_MASK 0x20
17224#define D3F2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
17225#define D3F2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
17226#define D3F2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
17227#define D3F2_COMMAND__AD_STEPPING_MASK 0x80
17228#define D3F2_COMMAND__AD_STEPPING__SHIFT 0x7
17229#define D3F2_COMMAND__SERR_EN_MASK 0x100
17230#define D3F2_COMMAND__SERR_EN__SHIFT 0x8
17231#define D3F2_COMMAND__FAST_B2B_EN_MASK 0x200
17232#define D3F2_COMMAND__FAST_B2B_EN__SHIFT 0x9
17233#define D3F2_COMMAND__INT_DIS_MASK 0x400
17234#define D3F2_COMMAND__INT_DIS__SHIFT 0xa
17235#define D3F2_STATUS__INT_STATUS_MASK 0x80000
17236#define D3F2_STATUS__INT_STATUS__SHIFT 0x13
17237#define D3F2_STATUS__CAP_LIST_MASK 0x100000
17238#define D3F2_STATUS__CAP_LIST__SHIFT 0x14
17239#define D3F2_STATUS__PCI_66_EN_MASK 0x200000
17240#define D3F2_STATUS__PCI_66_EN__SHIFT 0x15
17241#define D3F2_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
17242#define D3F2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
17243#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
17244#define D3F2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
17245#define D3F2_STATUS__DEVSEL_TIMING_MASK 0x6000000
17246#define D3F2_STATUS__DEVSEL_TIMING__SHIFT 0x19
17247#define D3F2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
17248#define D3F2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
17249#define D3F2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
17250#define D3F2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
17251#define D3F2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
17252#define D3F2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
17253#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
17254#define D3F2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
17255#define D3F2_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
17256#define D3F2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
17257#define D3F2_REVISION_ID__MINOR_REV_ID_MASK 0xf
17258#define D3F2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
17259#define D3F2_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
17260#define D3F2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
17261#define D3F2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
17262#define D3F2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
17263#define D3F2_SUB_CLASS__SUB_CLASS_MASK 0xff0000
17264#define D3F2_SUB_CLASS__SUB_CLASS__SHIFT 0x10
17265#define D3F2_BASE_CLASS__BASE_CLASS_MASK 0xff000000
17266#define D3F2_BASE_CLASS__BASE_CLASS__SHIFT 0x18
17267#define D3F2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
17268#define D3F2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
17269#define D3F2_LATENCY__LATENCY_TIMER_MASK 0xff00
17270#define D3F2_LATENCY__LATENCY_TIMER__SHIFT 0x8
17271#define D3F2_HEADER__HEADER_TYPE_MASK 0x7f0000
17272#define D3F2_HEADER__HEADER_TYPE__SHIFT 0x10
17273#define D3F2_HEADER__DEVICE_TYPE_MASK 0x800000
17274#define D3F2_HEADER__DEVICE_TYPE__SHIFT 0x17
17275#define D3F2_BIST__BIST_COMP_MASK 0xf000000
17276#define D3F2_BIST__BIST_COMP__SHIFT 0x18
17277#define D3F2_BIST__BIST_STRT_MASK 0x40000000
17278#define D3F2_BIST__BIST_STRT__SHIFT 0x1e
17279#define D3F2_BIST__BIST_CAP_MASK 0x80000000
17280#define D3F2_BIST__BIST_CAP__SHIFT 0x1f
17281#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
17282#define D3F2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
17283#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
17284#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
17285#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
17286#define D3F2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
17287#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
17288#define D3F2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
17289#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
17290#define D3F2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
17291#define D3F2_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
17292#define D3F2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
17293#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
17294#define D3F2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
17295#define D3F2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
17296#define D3F2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
17297#define D3F2_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
17298#define D3F2_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
17299#define D3F2_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
17300#define D3F2_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
17301#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
17302#define D3F2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
17303#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
17304#define D3F2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
17305#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
17306#define D3F2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
17307#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
17308#define D3F2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
17309#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
17310#define D3F2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
17311#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
17312#define D3F2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
17313#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
17314#define D3F2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
17315#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
17316#define D3F2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
17317#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
17318#define D3F2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
17319#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
17320#define D3F2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
17321#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
17322#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
17323#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
17324#define D3F2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
17325#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
17326#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
17327#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
17328#define D3F2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
17329#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
17330#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
17331#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
17332#define D3F2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
17333#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
17334#define D3F2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
17335#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
17336#define D3F2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
17337#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
17338#define D3F2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
17339#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
17340#define D3F2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
17341#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
17342#define D3F2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
17343#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
17344#define D3F2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
17345#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
17346#define D3F2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
17347#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
17348#define D3F2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
17349#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
17350#define D3F2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
17351#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
17352#define D3F2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
17353#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
17354#define D3F2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
17355#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
17356#define D3F2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
17357#define D3F2_CAP_PTR__CAP_PTR_MASK 0xff
17358#define D3F2_CAP_PTR__CAP_PTR__SHIFT 0x0
17359#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
17360#define D3F2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
17361#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
17362#define D3F2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
17363#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
17364#define D3F2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
17365#define D3F2_PMI_CAP_LIST__CAP_ID_MASK 0xff
17366#define D3F2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
17367#define D3F2_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
17368#define D3F2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
17369#define D3F2_PMI_CAP__VERSION_MASK 0x70000
17370#define D3F2_PMI_CAP__VERSION__SHIFT 0x10
17371#define D3F2_PMI_CAP__PME_CLOCK_MASK 0x80000
17372#define D3F2_PMI_CAP__PME_CLOCK__SHIFT 0x13
17373#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
17374#define D3F2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
17375#define D3F2_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
17376#define D3F2_PMI_CAP__AUX_CURRENT__SHIFT 0x16
17377#define D3F2_PMI_CAP__D1_SUPPORT_MASK 0x2000000
17378#define D3F2_PMI_CAP__D1_SUPPORT__SHIFT 0x19
17379#define D3F2_PMI_CAP__D2_SUPPORT_MASK 0x4000000
17380#define D3F2_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
17381#define D3F2_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
17382#define D3F2_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
17383#define D3F2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
17384#define D3F2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
17385#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
17386#define D3F2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
17387#define D3F2_PMI_STATUS_CNTL__PME_EN_MASK 0x100
17388#define D3F2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
17389#define D3F2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
17390#define D3F2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
17391#define D3F2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
17392#define D3F2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
17393#define D3F2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
17394#define D3F2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
17395#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
17396#define D3F2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
17397#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
17398#define D3F2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
17399#define D3F2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
17400#define D3F2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
17401#define D3F2_PCIE_CAP_LIST__CAP_ID_MASK 0xff
17402#define D3F2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
17403#define D3F2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
17404#define D3F2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
17405#define D3F2_PCIE_CAP__VERSION_MASK 0xf0000
17406#define D3F2_PCIE_CAP__VERSION__SHIFT 0x10
17407#define D3F2_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
17408#define D3F2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
17409#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
17410#define D3F2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
17411#define D3F2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
17412#define D3F2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
17413#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
17414#define D3F2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
17415#define D3F2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
17416#define D3F2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
17417#define D3F2_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
17418#define D3F2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
17419#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
17420#define D3F2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
17421#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
17422#define D3F2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
17423#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
17424#define D3F2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
17425#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
17426#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
17427#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
17428#define D3F2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
17429#define D3F2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
17430#define D3F2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
17431#define D3F2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
17432#define D3F2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
17433#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
17434#define D3F2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
17435#define D3F2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
17436#define D3F2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
17437#define D3F2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
17438#define D3F2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
17439#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
17440#define D3F2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
17441#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
17442#define D3F2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
17443#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
17444#define D3F2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
17445#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
17446#define D3F2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
17447#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
17448#define D3F2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
17449#define D3F2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
17450#define D3F2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
17451#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
17452#define D3F2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
17453#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
17454#define D3F2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
17455#define D3F2_DEVICE_STATUS__CORR_ERR_MASK 0x10000
17456#define D3F2_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
17457#define D3F2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
17458#define D3F2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
17459#define D3F2_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
17460#define D3F2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
17461#define D3F2_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
17462#define D3F2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
17463#define D3F2_DEVICE_STATUS__AUX_PWR_MASK 0x100000
17464#define D3F2_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
17465#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
17466#define D3F2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
17467#define D3F2_LINK_CAP__LINK_SPEED_MASK 0xf
17468#define D3F2_LINK_CAP__LINK_SPEED__SHIFT 0x0
17469#define D3F2_LINK_CAP__LINK_WIDTH_MASK 0x3f0
17470#define D3F2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
17471#define D3F2_LINK_CAP__PM_SUPPORT_MASK 0xc00
17472#define D3F2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
17473#define D3F2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
17474#define D3F2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
17475#define D3F2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
17476#define D3F2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
17477#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
17478#define D3F2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
17479#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
17480#define D3F2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
17481#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
17482#define D3F2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
17483#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
17484#define D3F2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
17485#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
17486#define D3F2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
17487#define D3F2_LINK_CAP__PORT_NUMBER_MASK 0xff000000
17488#define D3F2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
17489#define D3F2_LINK_CNTL__PM_CONTROL_MASK 0x3
17490#define D3F2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
17491#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
17492#define D3F2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
17493#define D3F2_LINK_CNTL__LINK_DIS_MASK 0x10
17494#define D3F2_LINK_CNTL__LINK_DIS__SHIFT 0x4
17495#define D3F2_LINK_CNTL__RETRAIN_LINK_MASK 0x20
17496#define D3F2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
17497#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
17498#define D3F2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
17499#define D3F2_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
17500#define D3F2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
17501#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
17502#define D3F2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
17503#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
17504#define D3F2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
17505#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
17506#define D3F2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
17507#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
17508#define D3F2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
17509#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
17510#define D3F2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
17511#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
17512#define D3F2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
17513#define D3F2_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
17514#define D3F2_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
17515#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
17516#define D3F2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
17517#define D3F2_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
17518#define D3F2_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
17519#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
17520#define D3F2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
17521#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
17522#define D3F2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
17523#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
17524#define D3F2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
17525#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
17526#define D3F2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
17527#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
17528#define D3F2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
17529#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
17530#define D3F2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
17531#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
17532#define D3F2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
17533#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
17534#define D3F2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
17535#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
17536#define D3F2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
17537#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
17538#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
17539#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
17540#define D3F2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
17541#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
17542#define D3F2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
17543#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
17544#define D3F2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
17545#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
17546#define D3F2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
17547#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
17548#define D3F2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
17549#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
17550#define D3F2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
17551#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
17552#define D3F2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
17553#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
17554#define D3F2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
17555#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
17556#define D3F2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
17557#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
17558#define D3F2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
17559#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
17560#define D3F2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
17561#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
17562#define D3F2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
17563#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
17564#define D3F2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
17565#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
17566#define D3F2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
17567#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
17568#define D3F2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
17569#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
17570#define D3F2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
17571#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
17572#define D3F2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
17573#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
17574#define D3F2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
17575#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
17576#define D3F2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
17577#define D3F2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
17578#define D3F2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
17579#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
17580#define D3F2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
17581#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
17582#define D3F2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
17583#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
17584#define D3F2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
17585#define D3F2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
17586#define D3F2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
17587#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
17588#define D3F2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
17589#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
17590#define D3F2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
17591#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
17592#define D3F2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
17593#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
17594#define D3F2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
17595#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
17596#define D3F2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
17597#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
17598#define D3F2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
17599#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
17600#define D3F2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
17601#define D3F2_ROOT_STATUS__PME_STATUS_MASK 0x10000
17602#define D3F2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
17603#define D3F2_ROOT_STATUS__PME_PENDING_MASK 0x20000
17604#define D3F2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
17605#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
17606#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
17607#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
17608#define D3F2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
17609#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
17610#define D3F2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
17611#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
17612#define D3F2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
17613#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
17614#define D3F2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
17615#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
17616#define D3F2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
17617#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
17618#define D3F2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
17619#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
17620#define D3F2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
17621#define D3F2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
17622#define D3F2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
17623#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
17624#define D3F2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
17625#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
17626#define D3F2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
17627#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
17628#define D3F2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
17629#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
17630#define D3F2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
17631#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
17632#define D3F2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
17633#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
17634#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
17635#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
17636#define D3F2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
17637#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
17638#define D3F2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
17639#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
17640#define D3F2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
17641#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
17642#define D3F2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
17643#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
17644#define D3F2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
17645#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
17646#define D3F2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
17647#define D3F2_DEVICE_CNTL2__LTR_EN_MASK 0x400
17648#define D3F2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
17649#define D3F2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
17650#define D3F2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
17651#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
17652#define D3F2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
17653#define D3F2_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
17654#define D3F2_DEVICE_STATUS2__RESERVED__SHIFT 0x10
17655#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
17656#define D3F2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
17657#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
17658#define D3F2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
17659#define D3F2_LINK_CAP2__RESERVED_MASK 0xfffffe00
17660#define D3F2_LINK_CAP2__RESERVED__SHIFT 0x9
17661#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
17662#define D3F2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
17663#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
17664#define D3F2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
17665#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
17666#define D3F2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
17667#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
17668#define D3F2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
17669#define D3F2_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
17670#define D3F2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
17671#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
17672#define D3F2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
17673#define D3F2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
17674#define D3F2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
17675#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
17676#define D3F2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
17677#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
17678#define D3F2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
17679#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
17680#define D3F2_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
17681#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
17682#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
17683#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
17684#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
17685#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
17686#define D3F2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
17687#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
17688#define D3F2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
17689#define D3F2_SLOT_CAP2__RESERVED_MASK 0xffffffff
17690#define D3F2_SLOT_CAP2__RESERVED__SHIFT 0x0
17691#define D3F2_SLOT_CNTL2__RESERVED_MASK 0xffff
17692#define D3F2_SLOT_CNTL2__RESERVED__SHIFT 0x0
17693#define D3F2_SLOT_STATUS2__RESERVED_MASK 0xffff0000
17694#define D3F2_SLOT_STATUS2__RESERVED__SHIFT 0x10
17695#define D3F2_MSI_CAP_LIST__CAP_ID_MASK 0xff
17696#define D3F2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
17697#define D3F2_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
17698#define D3F2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
17699#define D3F2_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
17700#define D3F2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
17701#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
17702#define D3F2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
17703#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
17704#define D3F2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
17705#define D3F2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
17706#define D3F2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
17707#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
17708#define D3F2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
17709#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
17710#define D3F2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
17711#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
17712#define D3F2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
17713#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
17714#define D3F2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
17715#define D3F2_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
17716#define D3F2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
17717#define D3F2_SSID_CAP_LIST__CAP_ID_MASK 0xff
17718#define D3F2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
17719#define D3F2_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
17720#define D3F2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
17721#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
17722#define D3F2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
17723#define D3F2_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
17724#define D3F2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
17725#define D3F2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
17726#define D3F2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
17727#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
17728#define D3F2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
17729#define D3F2_MSI_MAP_CAP__EN_MASK 0x10000
17730#define D3F2_MSI_MAP_CAP__EN__SHIFT 0x10
17731#define D3F2_MSI_MAP_CAP__FIXD_MASK 0x20000
17732#define D3F2_MSI_MAP_CAP__FIXD__SHIFT 0x11
17733#define D3F2_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
17734#define D3F2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
17735#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
17736#define D3F2_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
17737#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
17738#define D3F2_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
17739#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
17740#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
17741#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
17742#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
17743#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
17744#define D3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
17745#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
17746#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
17747#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
17748#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
17749#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
17750#define D3F2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
17751#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
17752#define D3F2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
17753#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
17754#define D3F2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
17755#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
17756#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
17757#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
17758#define D3F2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
17759#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
17760#define D3F2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
17761#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
17762#define D3F2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
17763#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
17764#define D3F2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
17765#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
17766#define D3F2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
17767#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
17768#define D3F2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
17769#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
17770#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
17771#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
17772#define D3F2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
17773#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
17774#define D3F2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
17775#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
17776#define D3F2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
17777#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
17778#define D3F2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
17779#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
17780#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
17781#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
17782#define D3F2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
17783#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
17784#define D3F2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
17785#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
17786#define D3F2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
17787#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
17788#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
17789#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
17790#define D3F2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
17791#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
17792#define D3F2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
17793#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
17794#define D3F2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
17795#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
17796#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
17797#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
17798#define D3F2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
17799#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
17800#define D3F2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
17801#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
17802#define D3F2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
17803#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
17804#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
17805#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
17806#define D3F2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
17807#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
17808#define D3F2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
17809#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
17810#define D3F2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
17811#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
17812#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
17813#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
17814#define D3F2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
17815#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
17816#define D3F2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
17817#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
17818#define D3F2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
17819#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
17820#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
17821#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
17822#define D3F2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
17823#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
17824#define D3F2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
17825#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
17826#define D3F2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
17827#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
17828#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
17829#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
17830#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
17831#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
17832#define D3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
17833#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
17834#define D3F2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
17835#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
17836#define D3F2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
17837#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
17838#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
17839#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
17840#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
17841#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
17842#define D3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
17843#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
17844#define D3F2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
17845#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
17846#define D3F2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
17847#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
17848#define D3F2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
17849#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
17850#define D3F2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
17851#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
17852#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
17853#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
17854#define D3F2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
17855#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
17856#define D3F2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
17857#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
17858#define D3F2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
17859#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
17860#define D3F2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
17861#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
17862#define D3F2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
17863#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
17864#define D3F2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
17865#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
17866#define D3F2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
17867#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
17868#define D3F2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
17869#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
17870#define D3F2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
17871#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
17872#define D3F2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
17873#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
17874#define D3F2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
17875#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
17876#define D3F2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
17877#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
17878#define D3F2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
17879#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
17880#define D3F2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
17881#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
17882#define D3F2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
17883#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
17884#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
17885#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
17886#define D3F2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
17887#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
17888#define D3F2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
17889#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
17890#define D3F2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
17891#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
17892#define D3F2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
17893#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
17894#define D3F2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
17895#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
17896#define D3F2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
17897#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
17898#define D3F2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
17899#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
17900#define D3F2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
17901#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
17902#define D3F2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
17903#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
17904#define D3F2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
17905#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
17906#define D3F2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
17907#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
17908#define D3F2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
17909#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
17910#define D3F2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
17911#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
17912#define D3F2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
17913#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
17914#define D3F2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
17915#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
17916#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
17917#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
17918#define D3F2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
17919#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
17920#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
17921#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
17922#define D3F2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
17923#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
17924#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
17925#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
17926#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
17927#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
17928#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
17929#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
17930#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
17931#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
17932#define D3F2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
17933#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
17934#define D3F2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
17935#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
17936#define D3F2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
17937#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
17938#define D3F2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
17939#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
17940#define D3F2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
17941#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
17942#define D3F2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
17943#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
17944#define D3F2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
17945#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
17946#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
17947#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
17948#define D3F2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
17949#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
17950#define D3F2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
17951#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
17952#define D3F2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
17953#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
17954#define D3F2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
17955#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
17956#define D3F2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
17957#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
17958#define D3F2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
17959#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
17960#define D3F2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
17961#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
17962#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
17963#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
17964#define D3F2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
17965#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
17966#define D3F2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
17967#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
17968#define D3F2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
17969#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
17970#define D3F2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
17971#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
17972#define D3F2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
17973#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
17974#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
17975#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
17976#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
17977#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
17978#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
17979#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
17980#define D3F2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
17981#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
17982#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
17983#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
17984#define D3F2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
17985#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
17986#define D3F2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
17987#define D3F2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
17988#define D3F2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
17989#define D3F2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
17990#define D3F2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
17991#define D3F2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
17992#define D3F2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
17993#define D3F2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
17994#define D3F2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
17995#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
17996#define D3F2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
17997#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
17998#define D3F2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
17999#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
18000#define D3F2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
18001#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
18002#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
18003#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
18004#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
18005#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
18006#define D3F2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
18007#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
18008#define D3F2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
18009#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
18010#define D3F2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
18011#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
18012#define D3F2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
18013#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
18014#define D3F2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
18015#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
18016#define D3F2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
18017#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
18018#define D3F2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
18019#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
18020#define D3F2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
18021#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
18022#define D3F2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
18023#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
18024#define D3F2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
18025#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
18026#define D3F2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
18027#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
18028#define D3F2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
18029#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
18030#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
18031#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
18032#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
18033#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
18034#define D3F2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
18035#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
18036#define D3F2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
18037#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
18038#define D3F2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
18039#define D3F2_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
18040#define D3F2_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
18041#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
18042#define D3F2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
18043#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
18044#define D3F2_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
18045#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18046#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18047#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18048#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18049#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18050#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18051#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18052#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18053#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18054#define D3F2_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18055#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18056#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18057#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18058#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18059#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18060#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18061#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18062#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18063#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18064#define D3F2_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18065#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18066#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18067#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18068#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18069#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18070#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18071#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18072#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18073#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18074#define D3F2_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18075#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18076#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18077#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18078#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18079#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18080#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18081#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18082#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18083#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18084#define D3F2_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18085#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18086#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18087#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18088#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18089#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18090#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18091#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18092#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18093#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18094#define D3F2_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18095#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18096#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18097#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18098#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18099#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18100#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18101#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18102#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18103#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18104#define D3F2_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18105#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18106#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18107#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18108#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18109#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18110#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18111#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18112#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18113#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18114#define D3F2_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18115#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18116#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18117#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18118#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18119#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18120#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18121#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18122#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18123#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18124#define D3F2_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18125#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18126#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18127#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18128#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18129#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18130#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18131#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18132#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18133#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18134#define D3F2_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18135#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18136#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18137#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18138#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18139#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18140#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18141#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18142#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18143#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18144#define D3F2_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18145#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18146#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18147#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18148#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18149#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18150#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18151#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18152#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18153#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18154#define D3F2_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18155#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18156#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18157#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18158#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18159#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18160#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18161#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18162#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18163#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18164#define D3F2_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18165#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18166#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18167#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18168#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18169#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18170#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18171#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18172#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18173#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18174#define D3F2_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18175#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18176#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18177#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18178#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18179#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18180#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18181#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18182#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18183#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18184#define D3F2_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18185#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
18186#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
18187#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
18188#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
18189#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
18190#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
18191#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
18192#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
18193#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
18194#define D3F2_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
18195#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
18196#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
18197#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
18198#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
18199#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
18200#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
18201#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
18202#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
18203#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
18204#define D3F2_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
18205#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
18206#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
18207#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
18208#define D3F2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
18209#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
18210#define D3F2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
18211#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
18212#define D3F2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
18213#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
18214#define D3F2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
18215#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
18216#define D3F2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
18217#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
18218#define D3F2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
18219#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
18220#define D3F2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
18221#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
18222#define D3F2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
18223#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
18224#define D3F2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
18225#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
18226#define D3F2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
18227#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
18228#define D3F2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
18229#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
18230#define D3F2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
18231#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
18232#define D3F2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
18233#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
18234#define D3F2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
18235#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
18236#define D3F2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
18237#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
18238#define D3F2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
18239#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
18240#define D3F2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
18241#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
18242#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
18243#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
18244#define D3F2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
18245#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
18246#define D3F2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
18247#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
18248#define D3F2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
18249#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
18250#define D3F2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
18251#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
18252#define D3F2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
18253#define D3F2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
18254#define D3F2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
18255#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
18256#define D3F2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
18257#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
18258#define D3F2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
18259#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
18260#define D3F2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
18261#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
18262#define D3F2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
18263#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
18264#define D3F2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
18265#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
18266#define D3F2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
18267#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
18268#define D3F2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
18269#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
18270#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
18271#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
18272#define D3F2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
18273#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
18274#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
18275#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
18276#define D3F2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
18277#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
18278#define D3F2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
18279#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
18280#define D3F3_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
18281#define D3F3_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
18282#define D3F3_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
18283#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
18284#define D3F3_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
18285#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
18286#define D3F3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
18287#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
18288#define D3F3_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
18289#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
18290#define D3F3_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
18291#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
18292#define D3F3_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
18293#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
18294#define D3F3_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
18295#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
18296#define D3F3_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
18297#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
18298#define D3F3_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
18299#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
18300#define D3F3_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
18301#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
18302#define D3F3_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
18303#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
18304#define D3F3_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
18305#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
18306#define D3F3_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
18307#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
18308#define D3F3_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
18309#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
18310#define D3F3_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
18311#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
18312#define D3F3_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
18313#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
18314#define D3F3_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
18315#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
18316#define D3F3_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
18317#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
18318#define D3F3_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
18319#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
18320#define D3F3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
18321#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
18322#define D3F3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
18323#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
18324#define D3F3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
18325#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
18326#define D3F3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
18327#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
18328#define D3F3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
18329#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
18330#define D3F3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
18331#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
18332#define D3F3_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
18333#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
18334#define D3F3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
18335#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
18336#define D3F3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
18337#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
18338#define D3F3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
18339#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
18340#define D3F3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
18341#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
18342#define D3F3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
18343#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
18344#define D3F3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
18345#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
18346#define D3F3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
18347#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
18348#define D3F3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
18349#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
18350#define D3F3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
18351#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
18352#define D3F3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
18353#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
18354#define D3F3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
18355#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
18356#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
18357#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
18358#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
18359#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
18360#define D3F3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
18361#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
18362#define D3F3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
18363#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
18364#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
18365#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
18366#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
18367#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
18368#define D3F3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
18369#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
18370#define D3F3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
18371#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
18372#define D3F3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
18373#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
18374#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
18375#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
18376#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
18377#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
18378#define D3F3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
18379#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
18380#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
18381#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
18382#define D3F3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
18383#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
18384#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
18385#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
18386#define D3F3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
18387#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
18388#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
18389#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
18390#define D3F3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
18391#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
18392#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
18393#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
18394#define D3F3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
18395#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
18396#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
18397#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
18398#define D3F3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
18399#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
18400#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
18401#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
18402#define D3F3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
18403#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
18404#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
18405#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
18406#define D3F3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
18407#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
18408#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
18409#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
18410#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
18411#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
18412#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
18413#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
18414#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
18415#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
18416#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
18417#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
18418#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
18419#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
18420#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
18421#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
18422#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
18423#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
18424#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
18425#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
18426#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
18427#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
18428#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
18429#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
18430#define D3F3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
18431#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
18432#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
18433#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
18434#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
18435#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
18436#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
18437#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
18438#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
18439#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
18440#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
18441#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
18442#define D3F3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
18443#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
18444#define D3F3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
18445#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
18446#define D3F3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
18447#define D3F3_PCIE_FC_P__PD_CREDITS_MASK 0xff
18448#define D3F3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
18449#define D3F3_PCIE_FC_P__PH_CREDITS_MASK 0xff00
18450#define D3F3_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
18451#define D3F3_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
18452#define D3F3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
18453#define D3F3_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
18454#define D3F3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
18455#define D3F3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
18456#define D3F3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
18457#define D3F3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
18458#define D3F3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
18459#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
18460#define D3F3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
18461#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
18462#define D3F3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
18463#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
18464#define D3F3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
18465#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
18466#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
18467#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
18468#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
18469#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
18470#define D3F3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
18471#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
18472#define D3F3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
18473#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
18474#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
18475#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
18476#define D3F3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
18477#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
18478#define D3F3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
18479#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
18480#define D3F3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
18481#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
18482#define D3F3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
18483#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
18484#define D3F3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
18485#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
18486#define D3F3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
18487#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
18488#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
18489#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
18490#define D3F3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
18491#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
18492#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
18493#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
18494#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
18495#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
18496#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
18497#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
18498#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
18499#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
18500#define D3F3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
18501#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
18502#define D3F3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
18503#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
18504#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
18505#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
18506#define D3F3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
18507#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
18508#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
18509#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
18510#define D3F3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
18511#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
18512#define D3F3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
18513#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
18514#define D3F3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
18515#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
18516#define D3F3_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
18517#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
18518#define D3F3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
18519#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
18520#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
18521#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
18522#define D3F3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
18523#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
18524#define D3F3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
18525#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
18526#define D3F3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
18527#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
18528#define D3F3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
18529#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
18530#define D3F3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
18531#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
18532#define D3F3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
18533#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
18534#define D3F3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
18535#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
18536#define D3F3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
18537#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
18538#define D3F3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
18539#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
18540#define D3F3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
18541#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
18542#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
18543#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
18544#define D3F3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
18545#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
18546#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
18547#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
18548#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
18549#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
18550#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
18551#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
18552#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
18553#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
18554#define D3F3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
18555#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
18556#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
18557#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
18558#define D3F3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
18559#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
18560#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
18561#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
18562#define D3F3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
18563#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
18564#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
18565#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
18566#define D3F3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
18567#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
18568#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
18569#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
18570#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
18571#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
18572#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
18573#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
18574#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
18575#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
18576#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
18577#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
18578#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
18579#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
18580#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
18581#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
18582#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
18583#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
18584#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
18585#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
18586#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
18587#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
18588#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
18589#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
18590#define D3F3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
18591#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
18592#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
18593#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
18594#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
18595#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
18596#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
18597#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
18598#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
18599#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
18600#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
18601#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
18602#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
18603#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
18604#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
18605#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
18606#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
18607#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
18608#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
18609#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
18610#define D3F3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
18611#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
18612#define D3F3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
18613#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
18614#define D3F3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
18615#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
18616#define D3F3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
18617#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
18618#define D3F3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
18619#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
18620#define D3F3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
18621#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
18622#define D3F3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
18623#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
18624#define D3F3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
18625#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
18626#define D3F3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
18627#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
18628#define D3F3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
18629#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
18630#define D3F3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
18631#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
18632#define D3F3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
18633#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
18634#define D3F3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
18635#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
18636#define D3F3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
18637#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
18638#define D3F3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
18639#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
18640#define D3F3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
18641#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
18642#define D3F3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
18643#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
18644#define D3F3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
18645#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
18646#define D3F3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
18647#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
18648#define D3F3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
18649#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
18650#define D3F3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
18651#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
18652#define D3F3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
18653#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
18654#define D3F3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
18655#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
18656#define D3F3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
18657#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
18658#define D3F3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
18659#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
18660#define D3F3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
18661#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
18662#define D3F3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
18663#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
18664#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
18665#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
18666#define D3F3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
18667#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
18668#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
18669#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
18670#define D3F3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
18671#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
18672#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
18673#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
18674#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
18675#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
18676#define D3F3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
18677#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
18678#define D3F3_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
18679#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
18680#define D3F3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
18681#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
18682#define D3F3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
18683#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
18684#define D3F3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
18685#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
18686#define D3F3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
18687#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
18688#define D3F3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
18689#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
18690#define D3F3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
18691#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
18692#define D3F3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
18693#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
18694#define D3F3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
18695#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
18696#define D3F3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
18697#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
18698#define D3F3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
18699#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
18700#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
18701#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
18702#define D3F3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
18703#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
18704#define D3F3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
18705#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
18706#define D3F3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
18707#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
18708#define D3F3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
18709#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
18710#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
18711#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
18712#define D3F3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
18713#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
18714#define D3F3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
18715#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
18716#define D3F3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
18717#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
18718#define D3F3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
18719#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
18720#define D3F3_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
18721#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
18722#define D3F3_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
18723#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
18724#define D3F3_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
18725#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
18726#define D3F3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
18727#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
18728#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
18729#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
18730#define D3F3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
18731#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
18732#define D3F3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
18733#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
18734#define D3F3_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
18735#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
18736#define D3F3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
18737#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
18738#define D3F3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
18739#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
18740#define D3F3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
18741#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
18742#define D3F3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
18743#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
18744#define D3F3_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
18745#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
18746#define D3F3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
18747#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
18748#define D3F3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
18749#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
18750#define D3F3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
18751#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
18752#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
18753#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
18754#define D3F3_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
18755#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
18756#define D3F3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
18757#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
18758#define D3F3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
18759#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
18760#define D3F3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
18761#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
18762#define D3F3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
18763#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
18764#define D3F3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
18765#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
18766#define D3F3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
18767#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
18768#define D3F3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
18769#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
18770#define D3F3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
18771#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
18772#define D3F3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
18773#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
18774#define D3F3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
18775#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
18776#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
18777#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
18778#define D3F3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
18779#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
18780#define D3F3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
18781#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
18782#define D3F3_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
18783#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
18784#define D3F3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
18785#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
18786#define D3F3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
18787#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
18788#define D3F3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
18789#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
18790#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
18791#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
18792#define D3F3_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
18793#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
18794#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
18795#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
18796#define D3F3_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
18797#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
18798#define D3F3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
18799#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
18800#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
18801#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
18802#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
18803#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
18804#define D3F3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
18805#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
18806#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
18807#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
18808#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
18809#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
18810#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
18811#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
18812#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
18813#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
18814#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
18815#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
18816#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
18817#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
18818#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
18819#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
18820#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
18821#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
18822#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
18823#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
18824#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
18825#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
18826#define D3F3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
18827#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
18828#define D3F3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
18829#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
18830#define D3F3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
18831#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
18832#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
18833#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
18834#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
18835#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
18836#define D3F3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
18837#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
18838#define D3F3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
18839#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
18840#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
18841#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
18842#define D3F3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
18843#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
18844#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
18845#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
18846#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
18847#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
18848#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
18849#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
18850#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
18851#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
18852#define D3F3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
18853#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
18854#define D3F3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
18855#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
18856#define D3F3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
18857#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
18858#define D3F3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
18859#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
18860#define D3F3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
18861#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
18862#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
18863#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
18864#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
18865#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
18866#define D3F3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
18867#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
18868#define D3F3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
18869#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
18870#define D3F3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
18871#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
18872#define D3F3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
18873#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
18874#define D3F3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
18875#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
18876#define D3F3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
18877#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
18878#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
18879#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
18880#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
18881#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
18882#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
18883#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
18884#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
18885#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
18886#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
18887#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
18888#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
18889#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
18890#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
18891#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
18892#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
18893#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
18894#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
18895#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
18896#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
18897#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
18898#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
18899#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
18900#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
18901#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
18902#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
18903#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
18904#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
18905#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
18906#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
18907#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
18908#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
18909#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
18910#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
18911#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
18912#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
18913#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
18914#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
18915#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
18916#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
18917#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
18918#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
18919#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
18920#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
18921#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
18922#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
18923#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
18924#define D3F3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
18925#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
18926#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
18927#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
18928#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
18929#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
18930#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
18931#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
18932#define D3F3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
18933#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
18934#define D3F3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
18935#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
18936#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
18937#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
18938#define D3F3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
18939#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
18940#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
18941#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
18942#define D3F3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
18943#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
18944#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
18945#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
18946#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
18947#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
18948#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
18949#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
18950#define D3F3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
18951#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
18952#define D3F3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
18953#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
18954#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
18955#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
18956#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
18957#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
18958#define D3F3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
18959#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
18960#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
18961#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
18962#define D3F3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
18963#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
18964#define D3F3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
18965#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
18966#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
18967#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
18968#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
18969#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
18970#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
18971#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
18972#define D3F3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
18973#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
18974#define D3F3_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
18975#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
18976#define D3F3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
18977#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
18978#define D3F3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
18979#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
18980#define D3F3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
18981#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
18982#define D3F3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
18983#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
18984#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
18985#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
18986#define D3F3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
18987#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
18988#define D3F3_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
18989#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
18990#define D3F3_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
18991#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
18992#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
18993#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
18994#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
18995#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
18996#define D3F3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
18997#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
18998#define D3F3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
18999#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
19000#define D3F3_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
19001#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
19002#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
19003#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
19004#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
19005#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
19006#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
19007#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
19008#define D3F3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
19009#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
19010#define D3F3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
19011#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
19012#define D3F3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
19013#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
19014#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
19015#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
19016#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
19017#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
19018#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
19019#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
19020#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
19021#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
19022#define D3F3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
19023#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
19024#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
19025#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
19026#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
19027#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
19028#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
19029#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
19030#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
19031#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
19032#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
19033#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
19034#define D3F3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
19035#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
19036#define D3F3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
19037#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
19038#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
19039#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
19040#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
19041#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
19042#define D3F3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
19043#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
19044#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
19045#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
19046#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
19047#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
19048#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
19049#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
19050#define D3F3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
19051#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
19052#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
19053#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
19054#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
19055#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
19056#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
19057#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
19058#define D3F3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
19059#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
19060#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
19061#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
19062#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
19063#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
19064#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
19065#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
19066#define D3F3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
19067#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
19068#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
19069#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
19070#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
19071#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
19072#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
19073#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
19074#define D3F3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
19075#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
19076#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
19077#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
19078#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
19079#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
19080#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
19081#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
19082#define D3F3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
19083#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
19084#define D3F3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
19085#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
19086#define D3F3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
19087#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
19088#define D3F3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
19089#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
19090#define D3F3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
19091#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
19092#define D3F3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
19093#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
19094#define D3F3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
19095#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
19096#define D3F3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
19097#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
19098#define D3F3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
19099#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
19100#define D3F3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
19101#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
19102#define D3F3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
19103#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
19104#define D3F3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
19105#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
19106#define D3F3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
19107#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
19108#define D3F3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
19109#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
19110#define D3F3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
19111#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
19112#define D3F3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
19113#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
19114#define D3F3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
19115#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
19116#define D3F3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
19117#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
19118#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
19119#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
19120#define D3F3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
19121#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
19122#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
19123#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
19124#define D3F3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
19125#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
19126#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
19127#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
19128#define D3F3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
19129#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
19130#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
19131#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
19132#define D3F3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
19133#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
19134#define D3F3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
19135#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
19136#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
19137#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
19138#define D3F3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
19139#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
19140#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
19141#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
19142#define D3F3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
19143#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
19144#define D3F3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
19145#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
19146#define D3F3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
19147#define D3F3_VENDOR_ID__VENDOR_ID_MASK 0xffff
19148#define D3F3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
19149#define D3F3_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
19150#define D3F3_DEVICE_ID__DEVICE_ID__SHIFT 0x10
19151#define D3F3_COMMAND__IO_ACCESS_EN_MASK 0x1
19152#define D3F3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
19153#define D3F3_COMMAND__MEM_ACCESS_EN_MASK 0x2
19154#define D3F3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
19155#define D3F3_COMMAND__BUS_MASTER_EN_MASK 0x4
19156#define D3F3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
19157#define D3F3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
19158#define D3F3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
19159#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
19160#define D3F3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
19161#define D3F3_COMMAND__PAL_SNOOP_EN_MASK 0x20
19162#define D3F3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
19163#define D3F3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
19164#define D3F3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
19165#define D3F3_COMMAND__AD_STEPPING_MASK 0x80
19166#define D3F3_COMMAND__AD_STEPPING__SHIFT 0x7
19167#define D3F3_COMMAND__SERR_EN_MASK 0x100
19168#define D3F3_COMMAND__SERR_EN__SHIFT 0x8
19169#define D3F3_COMMAND__FAST_B2B_EN_MASK 0x200
19170#define D3F3_COMMAND__FAST_B2B_EN__SHIFT 0x9
19171#define D3F3_COMMAND__INT_DIS_MASK 0x400
19172#define D3F3_COMMAND__INT_DIS__SHIFT 0xa
19173#define D3F3_STATUS__INT_STATUS_MASK 0x80000
19174#define D3F3_STATUS__INT_STATUS__SHIFT 0x13
19175#define D3F3_STATUS__CAP_LIST_MASK 0x100000
19176#define D3F3_STATUS__CAP_LIST__SHIFT 0x14
19177#define D3F3_STATUS__PCI_66_EN_MASK 0x200000
19178#define D3F3_STATUS__PCI_66_EN__SHIFT 0x15
19179#define D3F3_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
19180#define D3F3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
19181#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
19182#define D3F3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
19183#define D3F3_STATUS__DEVSEL_TIMING_MASK 0x6000000
19184#define D3F3_STATUS__DEVSEL_TIMING__SHIFT 0x19
19185#define D3F3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
19186#define D3F3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
19187#define D3F3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
19188#define D3F3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
19189#define D3F3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
19190#define D3F3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
19191#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
19192#define D3F3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
19193#define D3F3_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
19194#define D3F3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
19195#define D3F3_REVISION_ID__MINOR_REV_ID_MASK 0xf
19196#define D3F3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
19197#define D3F3_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
19198#define D3F3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
19199#define D3F3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
19200#define D3F3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
19201#define D3F3_SUB_CLASS__SUB_CLASS_MASK 0xff0000
19202#define D3F3_SUB_CLASS__SUB_CLASS__SHIFT 0x10
19203#define D3F3_BASE_CLASS__BASE_CLASS_MASK 0xff000000
19204#define D3F3_BASE_CLASS__BASE_CLASS__SHIFT 0x18
19205#define D3F3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
19206#define D3F3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
19207#define D3F3_LATENCY__LATENCY_TIMER_MASK 0xff00
19208#define D3F3_LATENCY__LATENCY_TIMER__SHIFT 0x8
19209#define D3F3_HEADER__HEADER_TYPE_MASK 0x7f0000
19210#define D3F3_HEADER__HEADER_TYPE__SHIFT 0x10
19211#define D3F3_HEADER__DEVICE_TYPE_MASK 0x800000
19212#define D3F3_HEADER__DEVICE_TYPE__SHIFT 0x17
19213#define D3F3_BIST__BIST_COMP_MASK 0xf000000
19214#define D3F3_BIST__BIST_COMP__SHIFT 0x18
19215#define D3F3_BIST__BIST_STRT_MASK 0x40000000
19216#define D3F3_BIST__BIST_STRT__SHIFT 0x1e
19217#define D3F3_BIST__BIST_CAP_MASK 0x80000000
19218#define D3F3_BIST__BIST_CAP__SHIFT 0x1f
19219#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
19220#define D3F3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
19221#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
19222#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
19223#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
19224#define D3F3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
19225#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
19226#define D3F3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
19227#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
19228#define D3F3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
19229#define D3F3_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
19230#define D3F3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
19231#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
19232#define D3F3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
19233#define D3F3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
19234#define D3F3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
19235#define D3F3_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
19236#define D3F3_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
19237#define D3F3_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
19238#define D3F3_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
19239#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
19240#define D3F3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
19241#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
19242#define D3F3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
19243#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
19244#define D3F3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
19245#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
19246#define D3F3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
19247#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
19248#define D3F3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
19249#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
19250#define D3F3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
19251#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
19252#define D3F3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
19253#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
19254#define D3F3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
19255#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
19256#define D3F3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
19257#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
19258#define D3F3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
19259#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
19260#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
19261#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
19262#define D3F3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
19263#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
19264#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
19265#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
19266#define D3F3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
19267#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
19268#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
19269#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
19270#define D3F3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
19271#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
19272#define D3F3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
19273#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
19274#define D3F3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
19275#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
19276#define D3F3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
19277#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
19278#define D3F3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
19279#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
19280#define D3F3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
19281#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
19282#define D3F3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
19283#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
19284#define D3F3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
19285#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
19286#define D3F3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
19287#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
19288#define D3F3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
19289#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
19290#define D3F3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
19291#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
19292#define D3F3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
19293#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
19294#define D3F3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
19295#define D3F3_CAP_PTR__CAP_PTR_MASK 0xff
19296#define D3F3_CAP_PTR__CAP_PTR__SHIFT 0x0
19297#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
19298#define D3F3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
19299#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
19300#define D3F3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
19301#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
19302#define D3F3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
19303#define D3F3_PMI_CAP_LIST__CAP_ID_MASK 0xff
19304#define D3F3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
19305#define D3F3_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
19306#define D3F3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
19307#define D3F3_PMI_CAP__VERSION_MASK 0x70000
19308#define D3F3_PMI_CAP__VERSION__SHIFT 0x10
19309#define D3F3_PMI_CAP__PME_CLOCK_MASK 0x80000
19310#define D3F3_PMI_CAP__PME_CLOCK__SHIFT 0x13
19311#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
19312#define D3F3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
19313#define D3F3_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
19314#define D3F3_PMI_CAP__AUX_CURRENT__SHIFT 0x16
19315#define D3F3_PMI_CAP__D1_SUPPORT_MASK 0x2000000
19316#define D3F3_PMI_CAP__D1_SUPPORT__SHIFT 0x19
19317#define D3F3_PMI_CAP__D2_SUPPORT_MASK 0x4000000
19318#define D3F3_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
19319#define D3F3_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
19320#define D3F3_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
19321#define D3F3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
19322#define D3F3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
19323#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
19324#define D3F3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
19325#define D3F3_PMI_STATUS_CNTL__PME_EN_MASK 0x100
19326#define D3F3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
19327#define D3F3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
19328#define D3F3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
19329#define D3F3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
19330#define D3F3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
19331#define D3F3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
19332#define D3F3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
19333#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
19334#define D3F3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
19335#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
19336#define D3F3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
19337#define D3F3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
19338#define D3F3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
19339#define D3F3_PCIE_CAP_LIST__CAP_ID_MASK 0xff
19340#define D3F3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
19341#define D3F3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
19342#define D3F3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
19343#define D3F3_PCIE_CAP__VERSION_MASK 0xf0000
19344#define D3F3_PCIE_CAP__VERSION__SHIFT 0x10
19345#define D3F3_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
19346#define D3F3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
19347#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
19348#define D3F3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
19349#define D3F3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
19350#define D3F3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
19351#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
19352#define D3F3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
19353#define D3F3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
19354#define D3F3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
19355#define D3F3_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
19356#define D3F3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
19357#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
19358#define D3F3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
19359#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
19360#define D3F3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
19361#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
19362#define D3F3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
19363#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
19364#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
19365#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
19366#define D3F3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
19367#define D3F3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
19368#define D3F3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
19369#define D3F3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
19370#define D3F3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
19371#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
19372#define D3F3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
19373#define D3F3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
19374#define D3F3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
19375#define D3F3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
19376#define D3F3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
19377#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
19378#define D3F3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
19379#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
19380#define D3F3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
19381#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
19382#define D3F3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
19383#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
19384#define D3F3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
19385#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
19386#define D3F3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
19387#define D3F3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
19388#define D3F3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
19389#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
19390#define D3F3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
19391#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
19392#define D3F3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
19393#define D3F3_DEVICE_STATUS__CORR_ERR_MASK 0x10000
19394#define D3F3_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
19395#define D3F3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
19396#define D3F3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
19397#define D3F3_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
19398#define D3F3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
19399#define D3F3_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
19400#define D3F3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
19401#define D3F3_DEVICE_STATUS__AUX_PWR_MASK 0x100000
19402#define D3F3_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
19403#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
19404#define D3F3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
19405#define D3F3_LINK_CAP__LINK_SPEED_MASK 0xf
19406#define D3F3_LINK_CAP__LINK_SPEED__SHIFT 0x0
19407#define D3F3_LINK_CAP__LINK_WIDTH_MASK 0x3f0
19408#define D3F3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
19409#define D3F3_LINK_CAP__PM_SUPPORT_MASK 0xc00
19410#define D3F3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
19411#define D3F3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
19412#define D3F3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
19413#define D3F3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
19414#define D3F3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
19415#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
19416#define D3F3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
19417#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
19418#define D3F3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
19419#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
19420#define D3F3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
19421#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
19422#define D3F3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
19423#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
19424#define D3F3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
19425#define D3F3_LINK_CAP__PORT_NUMBER_MASK 0xff000000
19426#define D3F3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
19427#define D3F3_LINK_CNTL__PM_CONTROL_MASK 0x3
19428#define D3F3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
19429#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
19430#define D3F3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
19431#define D3F3_LINK_CNTL__LINK_DIS_MASK 0x10
19432#define D3F3_LINK_CNTL__LINK_DIS__SHIFT 0x4
19433#define D3F3_LINK_CNTL__RETRAIN_LINK_MASK 0x20
19434#define D3F3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
19435#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
19436#define D3F3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
19437#define D3F3_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
19438#define D3F3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
19439#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
19440#define D3F3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
19441#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
19442#define D3F3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
19443#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
19444#define D3F3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
19445#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
19446#define D3F3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
19447#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
19448#define D3F3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
19449#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
19450#define D3F3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
19451#define D3F3_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
19452#define D3F3_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
19453#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
19454#define D3F3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
19455#define D3F3_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
19456#define D3F3_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
19457#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
19458#define D3F3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
19459#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
19460#define D3F3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
19461#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
19462#define D3F3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
19463#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
19464#define D3F3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
19465#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
19466#define D3F3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
19467#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
19468#define D3F3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
19469#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
19470#define D3F3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
19471#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
19472#define D3F3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
19473#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
19474#define D3F3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
19475#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
19476#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
19477#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
19478#define D3F3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
19479#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
19480#define D3F3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
19481#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
19482#define D3F3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
19483#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
19484#define D3F3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
19485#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
19486#define D3F3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
19487#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
19488#define D3F3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
19489#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
19490#define D3F3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
19491#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
19492#define D3F3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
19493#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
19494#define D3F3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
19495#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
19496#define D3F3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
19497#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
19498#define D3F3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
19499#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
19500#define D3F3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
19501#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
19502#define D3F3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
19503#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
19504#define D3F3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
19505#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
19506#define D3F3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
19507#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
19508#define D3F3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
19509#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
19510#define D3F3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
19511#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
19512#define D3F3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
19513#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
19514#define D3F3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
19515#define D3F3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
19516#define D3F3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
19517#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
19518#define D3F3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
19519#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
19520#define D3F3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
19521#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
19522#define D3F3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
19523#define D3F3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
19524#define D3F3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
19525#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
19526#define D3F3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
19527#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
19528#define D3F3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
19529#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
19530#define D3F3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
19531#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
19532#define D3F3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
19533#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
19534#define D3F3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
19535#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
19536#define D3F3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
19537#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
19538#define D3F3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
19539#define D3F3_ROOT_STATUS__PME_STATUS_MASK 0x10000
19540#define D3F3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
19541#define D3F3_ROOT_STATUS__PME_PENDING_MASK 0x20000
19542#define D3F3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
19543#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
19544#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
19545#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
19546#define D3F3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
19547#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
19548#define D3F3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
19549#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
19550#define D3F3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
19551#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
19552#define D3F3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
19553#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
19554#define D3F3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
19555#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
19556#define D3F3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
19557#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
19558#define D3F3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
19559#define D3F3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
19560#define D3F3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
19561#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
19562#define D3F3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
19563#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
19564#define D3F3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
19565#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
19566#define D3F3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
19567#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
19568#define D3F3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
19569#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
19570#define D3F3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
19571#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
19572#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
19573#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
19574#define D3F3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
19575#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
19576#define D3F3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
19577#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
19578#define D3F3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
19579#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
19580#define D3F3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
19581#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
19582#define D3F3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
19583#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
19584#define D3F3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
19585#define D3F3_DEVICE_CNTL2__LTR_EN_MASK 0x400
19586#define D3F3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
19587#define D3F3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
19588#define D3F3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
19589#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
19590#define D3F3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
19591#define D3F3_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
19592#define D3F3_DEVICE_STATUS2__RESERVED__SHIFT 0x10
19593#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
19594#define D3F3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
19595#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
19596#define D3F3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
19597#define D3F3_LINK_CAP2__RESERVED_MASK 0xfffffe00
19598#define D3F3_LINK_CAP2__RESERVED__SHIFT 0x9
19599#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
19600#define D3F3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
19601#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
19602#define D3F3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
19603#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
19604#define D3F3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
19605#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
19606#define D3F3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
19607#define D3F3_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
19608#define D3F3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
19609#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
19610#define D3F3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
19611#define D3F3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
19612#define D3F3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
19613#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
19614#define D3F3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
19615#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
19616#define D3F3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
19617#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
19618#define D3F3_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
19619#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
19620#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
19621#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
19622#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
19623#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
19624#define D3F3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
19625#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
19626#define D3F3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
19627#define D3F3_SLOT_CAP2__RESERVED_MASK 0xffffffff
19628#define D3F3_SLOT_CAP2__RESERVED__SHIFT 0x0
19629#define D3F3_SLOT_CNTL2__RESERVED_MASK 0xffff
19630#define D3F3_SLOT_CNTL2__RESERVED__SHIFT 0x0
19631#define D3F3_SLOT_STATUS2__RESERVED_MASK 0xffff0000
19632#define D3F3_SLOT_STATUS2__RESERVED__SHIFT 0x10
19633#define D3F3_MSI_CAP_LIST__CAP_ID_MASK 0xff
19634#define D3F3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
19635#define D3F3_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
19636#define D3F3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
19637#define D3F3_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
19638#define D3F3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
19639#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
19640#define D3F3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
19641#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
19642#define D3F3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
19643#define D3F3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
19644#define D3F3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
19645#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
19646#define D3F3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
19647#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
19648#define D3F3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
19649#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
19650#define D3F3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
19651#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
19652#define D3F3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
19653#define D3F3_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
19654#define D3F3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
19655#define D3F3_SSID_CAP_LIST__CAP_ID_MASK 0xff
19656#define D3F3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
19657#define D3F3_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
19658#define D3F3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
19659#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
19660#define D3F3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
19661#define D3F3_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
19662#define D3F3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
19663#define D3F3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
19664#define D3F3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
19665#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
19666#define D3F3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
19667#define D3F3_MSI_MAP_CAP__EN_MASK 0x10000
19668#define D3F3_MSI_MAP_CAP__EN__SHIFT 0x10
19669#define D3F3_MSI_MAP_CAP__FIXD_MASK 0x20000
19670#define D3F3_MSI_MAP_CAP__FIXD__SHIFT 0x11
19671#define D3F3_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
19672#define D3F3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
19673#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
19674#define D3F3_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
19675#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
19676#define D3F3_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
19677#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
19678#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
19679#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
19680#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
19681#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
19682#define D3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
19683#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
19684#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
19685#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
19686#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
19687#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
19688#define D3F3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
19689#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
19690#define D3F3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
19691#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
19692#define D3F3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
19693#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
19694#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
19695#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
19696#define D3F3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
19697#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
19698#define D3F3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
19699#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
19700#define D3F3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
19701#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
19702#define D3F3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
19703#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
19704#define D3F3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
19705#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
19706#define D3F3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
19707#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
19708#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
19709#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
19710#define D3F3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
19711#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
19712#define D3F3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
19713#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
19714#define D3F3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
19715#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
19716#define D3F3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
19717#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
19718#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
19719#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
19720#define D3F3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
19721#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
19722#define D3F3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
19723#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
19724#define D3F3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
19725#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
19726#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
19727#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
19728#define D3F3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
19729#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
19730#define D3F3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
19731#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
19732#define D3F3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
19733#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
19734#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
19735#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
19736#define D3F3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
19737#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
19738#define D3F3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
19739#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
19740#define D3F3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
19741#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
19742#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
19743#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
19744#define D3F3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
19745#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
19746#define D3F3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
19747#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
19748#define D3F3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
19749#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
19750#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
19751#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
19752#define D3F3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
19753#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
19754#define D3F3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
19755#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
19756#define D3F3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
19757#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
19758#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
19759#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
19760#define D3F3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
19761#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
19762#define D3F3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
19763#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
19764#define D3F3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
19765#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
19766#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
19767#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
19768#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
19769#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
19770#define D3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
19771#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
19772#define D3F3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
19773#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
19774#define D3F3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
19775#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
19776#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
19777#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
19778#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
19779#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
19780#define D3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
19781#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
19782#define D3F3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
19783#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
19784#define D3F3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
19785#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
19786#define D3F3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
19787#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
19788#define D3F3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
19789#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
19790#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
19791#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
19792#define D3F3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
19793#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
19794#define D3F3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
19795#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
19796#define D3F3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
19797#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
19798#define D3F3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
19799#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
19800#define D3F3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
19801#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
19802#define D3F3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
19803#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
19804#define D3F3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
19805#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
19806#define D3F3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
19807#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
19808#define D3F3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
19809#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
19810#define D3F3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
19811#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
19812#define D3F3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
19813#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
19814#define D3F3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
19815#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
19816#define D3F3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
19817#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
19818#define D3F3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
19819#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
19820#define D3F3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
19821#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
19822#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
19823#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
19824#define D3F3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
19825#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
19826#define D3F3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
19827#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
19828#define D3F3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
19829#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
19830#define D3F3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
19831#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
19832#define D3F3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
19833#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
19834#define D3F3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
19835#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
19836#define D3F3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
19837#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
19838#define D3F3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
19839#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
19840#define D3F3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
19841#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
19842#define D3F3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
19843#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
19844#define D3F3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
19845#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
19846#define D3F3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
19847#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
19848#define D3F3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
19849#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
19850#define D3F3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
19851#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
19852#define D3F3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
19853#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
19854#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
19855#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
19856#define D3F3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
19857#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
19858#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
19859#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
19860#define D3F3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
19861#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
19862#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
19863#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
19864#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
19865#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
19866#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
19867#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
19868#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
19869#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
19870#define D3F3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
19871#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
19872#define D3F3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
19873#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
19874#define D3F3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
19875#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
19876#define D3F3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
19877#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
19878#define D3F3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
19879#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
19880#define D3F3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
19881#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
19882#define D3F3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
19883#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
19884#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
19885#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
19886#define D3F3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
19887#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
19888#define D3F3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
19889#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
19890#define D3F3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
19891#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
19892#define D3F3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
19893#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
19894#define D3F3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
19895#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
19896#define D3F3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
19897#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
19898#define D3F3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
19899#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
19900#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
19901#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
19902#define D3F3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
19903#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
19904#define D3F3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
19905#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
19906#define D3F3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
19907#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
19908#define D3F3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
19909#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
19910#define D3F3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
19911#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
19912#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
19913#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
19914#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
19915#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
19916#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
19917#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
19918#define D3F3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
19919#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
19920#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
19921#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
19922#define D3F3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
19923#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
19924#define D3F3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
19925#define D3F3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
19926#define D3F3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
19927#define D3F3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
19928#define D3F3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
19929#define D3F3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
19930#define D3F3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
19931#define D3F3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
19932#define D3F3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
19933#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
19934#define D3F3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
19935#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
19936#define D3F3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
19937#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
19938#define D3F3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
19939#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
19940#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
19941#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
19942#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
19943#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
19944#define D3F3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
19945#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
19946#define D3F3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
19947#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
19948#define D3F3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
19949#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
19950#define D3F3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
19951#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
19952#define D3F3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
19953#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
19954#define D3F3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
19955#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
19956#define D3F3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
19957#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
19958#define D3F3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
19959#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
19960#define D3F3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
19961#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
19962#define D3F3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
19963#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
19964#define D3F3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
19965#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
19966#define D3F3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
19967#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
19968#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
19969#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
19970#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
19971#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
19972#define D3F3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
19973#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
19974#define D3F3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
19975#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
19976#define D3F3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
19977#define D3F3_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
19978#define D3F3_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
19979#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
19980#define D3F3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
19981#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
19982#define D3F3_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
19983#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
19984#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
19985#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
19986#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
19987#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
19988#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
19989#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
19990#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
19991#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
19992#define D3F3_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
19993#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
19994#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
19995#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
19996#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
19997#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
19998#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
19999#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20000#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20001#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20002#define D3F3_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20003#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20004#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20005#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20006#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20007#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20008#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20009#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20010#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20011#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20012#define D3F3_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20013#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20014#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20015#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20016#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20017#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20018#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20019#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20020#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20021#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20022#define D3F3_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20023#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20024#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20025#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20026#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20027#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20028#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20029#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20030#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20031#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20032#define D3F3_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20033#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20034#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20035#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20036#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20037#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20038#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20039#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20040#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20041#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20042#define D3F3_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20043#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20044#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20045#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20046#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20047#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20048#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20049#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20050#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20051#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20052#define D3F3_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20053#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20054#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20055#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20056#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20057#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20058#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20059#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20060#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20061#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20062#define D3F3_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20063#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20064#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20065#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20066#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20067#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20068#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20069#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20070#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20071#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20072#define D3F3_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20073#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20074#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20075#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20076#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20077#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20078#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20079#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20080#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20081#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20082#define D3F3_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20083#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20084#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20085#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20086#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20087#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20088#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20089#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20090#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20091#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20092#define D3F3_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20093#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20094#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20095#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20096#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20097#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20098#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20099#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20100#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20101#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20102#define D3F3_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20103#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20104#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20105#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20106#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20107#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20108#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20109#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20110#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20111#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20112#define D3F3_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20113#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20114#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20115#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20116#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20117#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20118#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20119#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20120#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20121#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20122#define D3F3_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20123#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
20124#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
20125#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
20126#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
20127#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
20128#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
20129#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
20130#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
20131#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
20132#define D3F3_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
20133#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
20134#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
20135#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
20136#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
20137#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
20138#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
20139#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
20140#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
20141#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
20142#define D3F3_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
20143#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
20144#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
20145#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
20146#define D3F3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
20147#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
20148#define D3F3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
20149#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
20150#define D3F3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
20151#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
20152#define D3F3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
20153#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
20154#define D3F3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
20155#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
20156#define D3F3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
20157#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
20158#define D3F3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
20159#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
20160#define D3F3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
20161#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
20162#define D3F3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
20163#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
20164#define D3F3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
20165#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
20166#define D3F3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
20167#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
20168#define D3F3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
20169#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
20170#define D3F3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
20171#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
20172#define D3F3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
20173#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
20174#define D3F3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
20175#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
20176#define D3F3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
20177#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
20178#define D3F3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
20179#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
20180#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
20181#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
20182#define D3F3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
20183#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
20184#define D3F3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
20185#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
20186#define D3F3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
20187#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
20188#define D3F3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
20189#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
20190#define D3F3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
20191#define D3F3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
20192#define D3F3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
20193#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
20194#define D3F3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
20195#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
20196#define D3F3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
20197#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
20198#define D3F3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
20199#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
20200#define D3F3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
20201#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
20202#define D3F3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
20203#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
20204#define D3F3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
20205#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
20206#define D3F3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
20207#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
20208#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
20209#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
20210#define D3F3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
20211#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
20212#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
20213#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
20214#define D3F3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
20215#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
20216#define D3F3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
20217#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
20218#define D3F4_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
20219#define D3F4_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
20220#define D3F4_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
20221#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
20222#define D3F4_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
20223#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
20224#define D3F4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
20225#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
20226#define D3F4_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
20227#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
20228#define D3F4_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
20229#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
20230#define D3F4_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
20231#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
20232#define D3F4_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
20233#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
20234#define D3F4_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
20235#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
20236#define D3F4_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
20237#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
20238#define D3F4_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
20239#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
20240#define D3F4_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
20241#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
20242#define D3F4_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
20243#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
20244#define D3F4_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
20245#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
20246#define D3F4_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
20247#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
20248#define D3F4_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
20249#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
20250#define D3F4_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
20251#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
20252#define D3F4_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
20253#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
20254#define D3F4_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
20255#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
20256#define D3F4_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
20257#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
20258#define D3F4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
20259#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
20260#define D3F4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
20261#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
20262#define D3F4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
20263#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
20264#define D3F4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
20265#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
20266#define D3F4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
20267#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
20268#define D3F4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
20269#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
20270#define D3F4_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
20271#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
20272#define D3F4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
20273#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
20274#define D3F4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
20275#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
20276#define D3F4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
20277#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
20278#define D3F4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
20279#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
20280#define D3F4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
20281#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
20282#define D3F4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
20283#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
20284#define D3F4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
20285#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
20286#define D3F4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
20287#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
20288#define D3F4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
20289#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
20290#define D3F4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
20291#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
20292#define D3F4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
20293#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
20294#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
20295#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
20296#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
20297#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
20298#define D3F4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
20299#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
20300#define D3F4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
20301#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
20302#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
20303#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
20304#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
20305#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
20306#define D3F4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
20307#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
20308#define D3F4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
20309#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
20310#define D3F4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
20311#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
20312#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
20313#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
20314#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
20315#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
20316#define D3F4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
20317#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
20318#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
20319#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
20320#define D3F4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
20321#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
20322#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
20323#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
20324#define D3F4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
20325#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
20326#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
20327#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
20328#define D3F4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
20329#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
20330#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
20331#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
20332#define D3F4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
20333#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
20334#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
20335#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
20336#define D3F4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
20337#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
20338#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
20339#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
20340#define D3F4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
20341#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
20342#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
20343#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
20344#define D3F4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
20345#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
20346#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
20347#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
20348#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
20349#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
20350#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
20351#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
20352#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
20353#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
20354#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
20355#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
20356#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
20357#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
20358#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
20359#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
20360#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
20361#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
20362#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
20363#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
20364#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
20365#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
20366#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
20367#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
20368#define D3F4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
20369#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
20370#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
20371#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
20372#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
20373#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
20374#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
20375#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
20376#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
20377#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
20378#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
20379#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
20380#define D3F4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
20381#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
20382#define D3F4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
20383#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
20384#define D3F4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
20385#define D3F4_PCIE_FC_P__PD_CREDITS_MASK 0xff
20386#define D3F4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
20387#define D3F4_PCIE_FC_P__PH_CREDITS_MASK 0xff00
20388#define D3F4_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
20389#define D3F4_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
20390#define D3F4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
20391#define D3F4_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
20392#define D3F4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
20393#define D3F4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
20394#define D3F4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
20395#define D3F4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
20396#define D3F4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
20397#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
20398#define D3F4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
20399#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
20400#define D3F4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
20401#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
20402#define D3F4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
20403#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
20404#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
20405#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
20406#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
20407#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
20408#define D3F4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
20409#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
20410#define D3F4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
20411#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
20412#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
20413#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
20414#define D3F4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
20415#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
20416#define D3F4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
20417#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
20418#define D3F4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
20419#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
20420#define D3F4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
20421#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
20422#define D3F4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
20423#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
20424#define D3F4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
20425#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
20426#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
20427#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
20428#define D3F4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
20429#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
20430#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
20431#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
20432#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
20433#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
20434#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
20435#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
20436#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
20437#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
20438#define D3F4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
20439#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
20440#define D3F4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
20441#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
20442#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
20443#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
20444#define D3F4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
20445#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
20446#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
20447#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
20448#define D3F4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
20449#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
20450#define D3F4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
20451#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
20452#define D3F4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
20453#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
20454#define D3F4_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
20455#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
20456#define D3F4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
20457#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
20458#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
20459#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
20460#define D3F4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
20461#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
20462#define D3F4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
20463#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
20464#define D3F4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
20465#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
20466#define D3F4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
20467#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
20468#define D3F4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
20469#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
20470#define D3F4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
20471#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
20472#define D3F4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
20473#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
20474#define D3F4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
20475#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
20476#define D3F4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
20477#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
20478#define D3F4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
20479#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
20480#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
20481#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
20482#define D3F4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
20483#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
20484#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
20485#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
20486#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
20487#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
20488#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
20489#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
20490#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
20491#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
20492#define D3F4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
20493#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
20494#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
20495#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
20496#define D3F4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
20497#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
20498#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
20499#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
20500#define D3F4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
20501#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
20502#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
20503#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
20504#define D3F4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
20505#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
20506#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
20507#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
20508#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
20509#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
20510#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
20511#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
20512#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
20513#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
20514#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
20515#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
20516#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
20517#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
20518#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
20519#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
20520#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
20521#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
20522#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
20523#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
20524#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
20525#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
20526#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
20527#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
20528#define D3F4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
20529#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
20530#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
20531#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
20532#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
20533#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
20534#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
20535#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
20536#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
20537#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
20538#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
20539#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
20540#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
20541#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
20542#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
20543#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
20544#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
20545#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
20546#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
20547#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
20548#define D3F4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
20549#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
20550#define D3F4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
20551#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
20552#define D3F4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
20553#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
20554#define D3F4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
20555#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
20556#define D3F4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
20557#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
20558#define D3F4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
20559#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
20560#define D3F4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
20561#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
20562#define D3F4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
20563#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
20564#define D3F4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
20565#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
20566#define D3F4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
20567#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
20568#define D3F4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
20569#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
20570#define D3F4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
20571#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
20572#define D3F4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
20573#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
20574#define D3F4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
20575#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
20576#define D3F4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
20577#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
20578#define D3F4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
20579#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
20580#define D3F4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
20581#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
20582#define D3F4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
20583#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
20584#define D3F4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
20585#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
20586#define D3F4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
20587#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
20588#define D3F4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
20589#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
20590#define D3F4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
20591#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
20592#define D3F4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
20593#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
20594#define D3F4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
20595#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
20596#define D3F4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
20597#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
20598#define D3F4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
20599#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
20600#define D3F4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
20601#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
20602#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
20603#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
20604#define D3F4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
20605#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
20606#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
20607#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
20608#define D3F4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
20609#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
20610#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
20611#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
20612#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
20613#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
20614#define D3F4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
20615#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
20616#define D3F4_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
20617#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
20618#define D3F4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
20619#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
20620#define D3F4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
20621#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
20622#define D3F4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
20623#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
20624#define D3F4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
20625#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
20626#define D3F4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
20627#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
20628#define D3F4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
20629#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
20630#define D3F4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
20631#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
20632#define D3F4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
20633#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
20634#define D3F4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
20635#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
20636#define D3F4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
20637#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
20638#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
20639#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
20640#define D3F4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
20641#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
20642#define D3F4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
20643#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
20644#define D3F4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
20645#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
20646#define D3F4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
20647#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
20648#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
20649#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
20650#define D3F4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
20651#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
20652#define D3F4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
20653#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
20654#define D3F4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
20655#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
20656#define D3F4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
20657#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
20658#define D3F4_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
20659#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
20660#define D3F4_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
20661#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
20662#define D3F4_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
20663#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
20664#define D3F4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
20665#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
20666#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
20667#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
20668#define D3F4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
20669#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
20670#define D3F4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
20671#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
20672#define D3F4_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
20673#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
20674#define D3F4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
20675#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
20676#define D3F4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
20677#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
20678#define D3F4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
20679#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
20680#define D3F4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
20681#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
20682#define D3F4_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
20683#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
20684#define D3F4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
20685#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
20686#define D3F4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
20687#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
20688#define D3F4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
20689#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
20690#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
20691#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
20692#define D3F4_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
20693#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
20694#define D3F4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
20695#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
20696#define D3F4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
20697#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
20698#define D3F4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
20699#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
20700#define D3F4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
20701#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
20702#define D3F4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
20703#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
20704#define D3F4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
20705#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
20706#define D3F4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
20707#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
20708#define D3F4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
20709#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
20710#define D3F4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
20711#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
20712#define D3F4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
20713#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
20714#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
20715#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
20716#define D3F4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
20717#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
20718#define D3F4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
20719#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
20720#define D3F4_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
20721#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
20722#define D3F4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
20723#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
20724#define D3F4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
20725#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
20726#define D3F4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
20727#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
20728#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
20729#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
20730#define D3F4_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
20731#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
20732#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
20733#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
20734#define D3F4_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
20735#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
20736#define D3F4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
20737#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
20738#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
20739#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
20740#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
20741#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
20742#define D3F4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
20743#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
20744#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
20745#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
20746#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
20747#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
20748#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
20749#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
20750#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
20751#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
20752#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
20753#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
20754#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
20755#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
20756#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
20757#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
20758#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
20759#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
20760#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
20761#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
20762#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
20763#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
20764#define D3F4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
20765#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
20766#define D3F4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
20767#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
20768#define D3F4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
20769#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
20770#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
20771#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
20772#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
20773#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
20774#define D3F4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
20775#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
20776#define D3F4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
20777#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
20778#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
20779#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
20780#define D3F4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
20781#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
20782#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
20783#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
20784#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
20785#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
20786#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
20787#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
20788#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
20789#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
20790#define D3F4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
20791#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
20792#define D3F4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
20793#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
20794#define D3F4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
20795#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
20796#define D3F4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
20797#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
20798#define D3F4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
20799#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
20800#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
20801#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
20802#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
20803#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
20804#define D3F4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
20805#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
20806#define D3F4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
20807#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
20808#define D3F4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
20809#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
20810#define D3F4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
20811#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
20812#define D3F4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
20813#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
20814#define D3F4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
20815#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
20816#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
20817#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
20818#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
20819#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
20820#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
20821#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
20822#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
20823#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
20824#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
20825#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
20826#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
20827#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
20828#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
20829#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
20830#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
20831#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
20832#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
20833#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
20834#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
20835#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
20836#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
20837#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
20838#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
20839#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
20840#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
20841#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
20842#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
20843#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
20844#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
20845#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
20846#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
20847#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
20848#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
20849#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
20850#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
20851#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
20852#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
20853#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
20854#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
20855#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
20856#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
20857#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
20858#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
20859#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
20860#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
20861#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
20862#define D3F4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
20863#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
20864#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
20865#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
20866#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
20867#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
20868#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
20869#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
20870#define D3F4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
20871#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
20872#define D3F4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
20873#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
20874#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
20875#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
20876#define D3F4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
20877#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
20878#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
20879#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
20880#define D3F4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
20881#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
20882#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
20883#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
20884#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
20885#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
20886#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
20887#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
20888#define D3F4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
20889#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
20890#define D3F4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
20891#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
20892#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
20893#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
20894#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
20895#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
20896#define D3F4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
20897#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
20898#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
20899#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
20900#define D3F4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
20901#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
20902#define D3F4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
20903#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
20904#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
20905#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
20906#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
20907#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
20908#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
20909#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
20910#define D3F4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
20911#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
20912#define D3F4_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
20913#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
20914#define D3F4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
20915#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
20916#define D3F4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
20917#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
20918#define D3F4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
20919#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
20920#define D3F4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
20921#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
20922#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
20923#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
20924#define D3F4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
20925#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
20926#define D3F4_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
20927#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
20928#define D3F4_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
20929#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
20930#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
20931#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
20932#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
20933#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
20934#define D3F4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
20935#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
20936#define D3F4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
20937#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
20938#define D3F4_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
20939#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
20940#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
20941#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
20942#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
20943#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
20944#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
20945#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
20946#define D3F4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
20947#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
20948#define D3F4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
20949#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
20950#define D3F4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
20951#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
20952#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
20953#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
20954#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
20955#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
20956#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
20957#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
20958#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
20959#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
20960#define D3F4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
20961#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
20962#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
20963#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
20964#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
20965#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
20966#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
20967#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
20968#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
20969#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
20970#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
20971#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
20972#define D3F4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
20973#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
20974#define D3F4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
20975#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
20976#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
20977#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
20978#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
20979#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
20980#define D3F4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
20981#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
20982#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
20983#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
20984#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
20985#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
20986#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
20987#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
20988#define D3F4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
20989#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
20990#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
20991#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
20992#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
20993#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
20994#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
20995#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
20996#define D3F4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
20997#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
20998#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
20999#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
21000#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
21001#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
21002#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
21003#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
21004#define D3F4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
21005#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
21006#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
21007#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
21008#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
21009#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
21010#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
21011#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
21012#define D3F4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
21013#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
21014#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
21015#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
21016#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
21017#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
21018#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
21019#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
21020#define D3F4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
21021#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
21022#define D3F4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
21023#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
21024#define D3F4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
21025#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
21026#define D3F4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
21027#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
21028#define D3F4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
21029#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
21030#define D3F4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
21031#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
21032#define D3F4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
21033#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
21034#define D3F4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
21035#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
21036#define D3F4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
21037#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
21038#define D3F4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
21039#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
21040#define D3F4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
21041#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
21042#define D3F4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
21043#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
21044#define D3F4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
21045#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
21046#define D3F4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
21047#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
21048#define D3F4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
21049#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
21050#define D3F4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
21051#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
21052#define D3F4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
21053#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
21054#define D3F4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
21055#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
21056#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
21057#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
21058#define D3F4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
21059#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
21060#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
21061#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
21062#define D3F4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
21063#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
21064#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
21065#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
21066#define D3F4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
21067#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
21068#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
21069#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
21070#define D3F4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
21071#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
21072#define D3F4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
21073#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
21074#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
21075#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
21076#define D3F4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
21077#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
21078#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
21079#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
21080#define D3F4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
21081#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
21082#define D3F4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
21083#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
21084#define D3F4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
21085#define D3F4_VENDOR_ID__VENDOR_ID_MASK 0xffff
21086#define D3F4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
21087#define D3F4_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
21088#define D3F4_DEVICE_ID__DEVICE_ID__SHIFT 0x10
21089#define D3F4_COMMAND__IO_ACCESS_EN_MASK 0x1
21090#define D3F4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
21091#define D3F4_COMMAND__MEM_ACCESS_EN_MASK 0x2
21092#define D3F4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
21093#define D3F4_COMMAND__BUS_MASTER_EN_MASK 0x4
21094#define D3F4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
21095#define D3F4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
21096#define D3F4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
21097#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
21098#define D3F4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
21099#define D3F4_COMMAND__PAL_SNOOP_EN_MASK 0x20
21100#define D3F4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
21101#define D3F4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
21102#define D3F4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
21103#define D3F4_COMMAND__AD_STEPPING_MASK 0x80
21104#define D3F4_COMMAND__AD_STEPPING__SHIFT 0x7
21105#define D3F4_COMMAND__SERR_EN_MASK 0x100
21106#define D3F4_COMMAND__SERR_EN__SHIFT 0x8
21107#define D3F4_COMMAND__FAST_B2B_EN_MASK 0x200
21108#define D3F4_COMMAND__FAST_B2B_EN__SHIFT 0x9
21109#define D3F4_COMMAND__INT_DIS_MASK 0x400
21110#define D3F4_COMMAND__INT_DIS__SHIFT 0xa
21111#define D3F4_STATUS__INT_STATUS_MASK 0x80000
21112#define D3F4_STATUS__INT_STATUS__SHIFT 0x13
21113#define D3F4_STATUS__CAP_LIST_MASK 0x100000
21114#define D3F4_STATUS__CAP_LIST__SHIFT 0x14
21115#define D3F4_STATUS__PCI_66_EN_MASK 0x200000
21116#define D3F4_STATUS__PCI_66_EN__SHIFT 0x15
21117#define D3F4_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
21118#define D3F4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
21119#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
21120#define D3F4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
21121#define D3F4_STATUS__DEVSEL_TIMING_MASK 0x6000000
21122#define D3F4_STATUS__DEVSEL_TIMING__SHIFT 0x19
21123#define D3F4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
21124#define D3F4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
21125#define D3F4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
21126#define D3F4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
21127#define D3F4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
21128#define D3F4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
21129#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
21130#define D3F4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
21131#define D3F4_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
21132#define D3F4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
21133#define D3F4_REVISION_ID__MINOR_REV_ID_MASK 0xf
21134#define D3F4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
21135#define D3F4_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
21136#define D3F4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
21137#define D3F4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
21138#define D3F4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
21139#define D3F4_SUB_CLASS__SUB_CLASS_MASK 0xff0000
21140#define D3F4_SUB_CLASS__SUB_CLASS__SHIFT 0x10
21141#define D3F4_BASE_CLASS__BASE_CLASS_MASK 0xff000000
21142#define D3F4_BASE_CLASS__BASE_CLASS__SHIFT 0x18
21143#define D3F4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
21144#define D3F4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
21145#define D3F4_LATENCY__LATENCY_TIMER_MASK 0xff00
21146#define D3F4_LATENCY__LATENCY_TIMER__SHIFT 0x8
21147#define D3F4_HEADER__HEADER_TYPE_MASK 0x7f0000
21148#define D3F4_HEADER__HEADER_TYPE__SHIFT 0x10
21149#define D3F4_HEADER__DEVICE_TYPE_MASK 0x800000
21150#define D3F4_HEADER__DEVICE_TYPE__SHIFT 0x17
21151#define D3F4_BIST__BIST_COMP_MASK 0xf000000
21152#define D3F4_BIST__BIST_COMP__SHIFT 0x18
21153#define D3F4_BIST__BIST_STRT_MASK 0x40000000
21154#define D3F4_BIST__BIST_STRT__SHIFT 0x1e
21155#define D3F4_BIST__BIST_CAP_MASK 0x80000000
21156#define D3F4_BIST__BIST_CAP__SHIFT 0x1f
21157#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
21158#define D3F4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
21159#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
21160#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
21161#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
21162#define D3F4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
21163#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
21164#define D3F4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
21165#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
21166#define D3F4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
21167#define D3F4_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
21168#define D3F4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
21169#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
21170#define D3F4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
21171#define D3F4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
21172#define D3F4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
21173#define D3F4_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
21174#define D3F4_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
21175#define D3F4_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
21176#define D3F4_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
21177#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
21178#define D3F4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
21179#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
21180#define D3F4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
21181#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
21182#define D3F4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
21183#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
21184#define D3F4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
21185#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
21186#define D3F4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
21187#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
21188#define D3F4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
21189#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
21190#define D3F4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
21191#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
21192#define D3F4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
21193#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
21194#define D3F4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
21195#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
21196#define D3F4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
21197#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
21198#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
21199#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
21200#define D3F4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
21201#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
21202#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
21203#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
21204#define D3F4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
21205#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
21206#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
21207#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
21208#define D3F4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
21209#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
21210#define D3F4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
21211#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
21212#define D3F4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
21213#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
21214#define D3F4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
21215#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
21216#define D3F4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
21217#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
21218#define D3F4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
21219#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
21220#define D3F4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
21221#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
21222#define D3F4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
21223#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
21224#define D3F4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
21225#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
21226#define D3F4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
21227#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
21228#define D3F4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
21229#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
21230#define D3F4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
21231#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
21232#define D3F4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
21233#define D3F4_CAP_PTR__CAP_PTR_MASK 0xff
21234#define D3F4_CAP_PTR__CAP_PTR__SHIFT 0x0
21235#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
21236#define D3F4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
21237#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
21238#define D3F4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
21239#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
21240#define D3F4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
21241#define D3F4_PMI_CAP_LIST__CAP_ID_MASK 0xff
21242#define D3F4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
21243#define D3F4_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
21244#define D3F4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
21245#define D3F4_PMI_CAP__VERSION_MASK 0x70000
21246#define D3F4_PMI_CAP__VERSION__SHIFT 0x10
21247#define D3F4_PMI_CAP__PME_CLOCK_MASK 0x80000
21248#define D3F4_PMI_CAP__PME_CLOCK__SHIFT 0x13
21249#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
21250#define D3F4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
21251#define D3F4_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
21252#define D3F4_PMI_CAP__AUX_CURRENT__SHIFT 0x16
21253#define D3F4_PMI_CAP__D1_SUPPORT_MASK 0x2000000
21254#define D3F4_PMI_CAP__D1_SUPPORT__SHIFT 0x19
21255#define D3F4_PMI_CAP__D2_SUPPORT_MASK 0x4000000
21256#define D3F4_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
21257#define D3F4_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
21258#define D3F4_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
21259#define D3F4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
21260#define D3F4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
21261#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
21262#define D3F4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
21263#define D3F4_PMI_STATUS_CNTL__PME_EN_MASK 0x100
21264#define D3F4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
21265#define D3F4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
21266#define D3F4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
21267#define D3F4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
21268#define D3F4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
21269#define D3F4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
21270#define D3F4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
21271#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
21272#define D3F4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
21273#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
21274#define D3F4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
21275#define D3F4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
21276#define D3F4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
21277#define D3F4_PCIE_CAP_LIST__CAP_ID_MASK 0xff
21278#define D3F4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
21279#define D3F4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
21280#define D3F4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
21281#define D3F4_PCIE_CAP__VERSION_MASK 0xf0000
21282#define D3F4_PCIE_CAP__VERSION__SHIFT 0x10
21283#define D3F4_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
21284#define D3F4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
21285#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
21286#define D3F4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
21287#define D3F4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
21288#define D3F4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
21289#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
21290#define D3F4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
21291#define D3F4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
21292#define D3F4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
21293#define D3F4_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
21294#define D3F4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
21295#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
21296#define D3F4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
21297#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
21298#define D3F4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
21299#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
21300#define D3F4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
21301#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
21302#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
21303#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
21304#define D3F4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
21305#define D3F4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
21306#define D3F4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
21307#define D3F4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
21308#define D3F4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
21309#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
21310#define D3F4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
21311#define D3F4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
21312#define D3F4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
21313#define D3F4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
21314#define D3F4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
21315#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
21316#define D3F4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
21317#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
21318#define D3F4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
21319#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
21320#define D3F4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
21321#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
21322#define D3F4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
21323#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
21324#define D3F4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
21325#define D3F4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
21326#define D3F4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
21327#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
21328#define D3F4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
21329#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
21330#define D3F4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
21331#define D3F4_DEVICE_STATUS__CORR_ERR_MASK 0x10000
21332#define D3F4_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
21333#define D3F4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
21334#define D3F4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
21335#define D3F4_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
21336#define D3F4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
21337#define D3F4_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
21338#define D3F4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
21339#define D3F4_DEVICE_STATUS__AUX_PWR_MASK 0x100000
21340#define D3F4_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
21341#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
21342#define D3F4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
21343#define D3F4_LINK_CAP__LINK_SPEED_MASK 0xf
21344#define D3F4_LINK_CAP__LINK_SPEED__SHIFT 0x0
21345#define D3F4_LINK_CAP__LINK_WIDTH_MASK 0x3f0
21346#define D3F4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
21347#define D3F4_LINK_CAP__PM_SUPPORT_MASK 0xc00
21348#define D3F4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
21349#define D3F4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
21350#define D3F4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
21351#define D3F4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
21352#define D3F4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
21353#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
21354#define D3F4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
21355#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
21356#define D3F4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
21357#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
21358#define D3F4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
21359#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
21360#define D3F4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
21361#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
21362#define D3F4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
21363#define D3F4_LINK_CAP__PORT_NUMBER_MASK 0xff000000
21364#define D3F4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
21365#define D3F4_LINK_CNTL__PM_CONTROL_MASK 0x3
21366#define D3F4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
21367#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
21368#define D3F4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
21369#define D3F4_LINK_CNTL__LINK_DIS_MASK 0x10
21370#define D3F4_LINK_CNTL__LINK_DIS__SHIFT 0x4
21371#define D3F4_LINK_CNTL__RETRAIN_LINK_MASK 0x20
21372#define D3F4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
21373#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
21374#define D3F4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
21375#define D3F4_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
21376#define D3F4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
21377#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
21378#define D3F4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
21379#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
21380#define D3F4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
21381#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
21382#define D3F4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
21383#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
21384#define D3F4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
21385#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
21386#define D3F4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
21387#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
21388#define D3F4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
21389#define D3F4_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
21390#define D3F4_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
21391#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
21392#define D3F4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
21393#define D3F4_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
21394#define D3F4_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
21395#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
21396#define D3F4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
21397#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
21398#define D3F4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
21399#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
21400#define D3F4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
21401#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
21402#define D3F4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
21403#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
21404#define D3F4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
21405#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
21406#define D3F4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
21407#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
21408#define D3F4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
21409#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
21410#define D3F4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
21411#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
21412#define D3F4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
21413#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
21414#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
21415#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
21416#define D3F4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
21417#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
21418#define D3F4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
21419#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
21420#define D3F4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
21421#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
21422#define D3F4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
21423#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
21424#define D3F4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
21425#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
21426#define D3F4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
21427#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
21428#define D3F4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
21429#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
21430#define D3F4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
21431#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
21432#define D3F4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
21433#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
21434#define D3F4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
21435#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
21436#define D3F4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
21437#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
21438#define D3F4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
21439#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
21440#define D3F4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
21441#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
21442#define D3F4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
21443#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
21444#define D3F4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
21445#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
21446#define D3F4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
21447#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
21448#define D3F4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
21449#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
21450#define D3F4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
21451#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
21452#define D3F4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
21453#define D3F4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
21454#define D3F4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
21455#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
21456#define D3F4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
21457#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
21458#define D3F4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
21459#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
21460#define D3F4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
21461#define D3F4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
21462#define D3F4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
21463#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
21464#define D3F4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
21465#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
21466#define D3F4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
21467#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
21468#define D3F4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
21469#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
21470#define D3F4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
21471#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
21472#define D3F4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
21473#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
21474#define D3F4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
21475#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
21476#define D3F4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
21477#define D3F4_ROOT_STATUS__PME_STATUS_MASK 0x10000
21478#define D3F4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
21479#define D3F4_ROOT_STATUS__PME_PENDING_MASK 0x20000
21480#define D3F4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
21481#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
21482#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
21483#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
21484#define D3F4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
21485#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
21486#define D3F4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
21487#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
21488#define D3F4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
21489#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
21490#define D3F4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
21491#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
21492#define D3F4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
21493#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
21494#define D3F4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
21495#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
21496#define D3F4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
21497#define D3F4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
21498#define D3F4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
21499#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
21500#define D3F4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
21501#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
21502#define D3F4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
21503#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
21504#define D3F4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
21505#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
21506#define D3F4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
21507#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
21508#define D3F4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
21509#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
21510#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
21511#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
21512#define D3F4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
21513#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
21514#define D3F4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
21515#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
21516#define D3F4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
21517#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
21518#define D3F4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
21519#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
21520#define D3F4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
21521#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
21522#define D3F4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
21523#define D3F4_DEVICE_CNTL2__LTR_EN_MASK 0x400
21524#define D3F4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
21525#define D3F4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
21526#define D3F4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
21527#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
21528#define D3F4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
21529#define D3F4_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
21530#define D3F4_DEVICE_STATUS2__RESERVED__SHIFT 0x10
21531#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
21532#define D3F4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
21533#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
21534#define D3F4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
21535#define D3F4_LINK_CAP2__RESERVED_MASK 0xfffffe00
21536#define D3F4_LINK_CAP2__RESERVED__SHIFT 0x9
21537#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
21538#define D3F4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
21539#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
21540#define D3F4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
21541#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
21542#define D3F4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
21543#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
21544#define D3F4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
21545#define D3F4_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
21546#define D3F4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
21547#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
21548#define D3F4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
21549#define D3F4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
21550#define D3F4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
21551#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
21552#define D3F4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
21553#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
21554#define D3F4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
21555#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
21556#define D3F4_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
21557#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
21558#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
21559#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
21560#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
21561#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
21562#define D3F4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
21563#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
21564#define D3F4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
21565#define D3F4_SLOT_CAP2__RESERVED_MASK 0xffffffff
21566#define D3F4_SLOT_CAP2__RESERVED__SHIFT 0x0
21567#define D3F4_SLOT_CNTL2__RESERVED_MASK 0xffff
21568#define D3F4_SLOT_CNTL2__RESERVED__SHIFT 0x0
21569#define D3F4_SLOT_STATUS2__RESERVED_MASK 0xffff0000
21570#define D3F4_SLOT_STATUS2__RESERVED__SHIFT 0x10
21571#define D3F4_MSI_CAP_LIST__CAP_ID_MASK 0xff
21572#define D3F4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
21573#define D3F4_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
21574#define D3F4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
21575#define D3F4_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
21576#define D3F4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
21577#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
21578#define D3F4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
21579#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
21580#define D3F4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
21581#define D3F4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
21582#define D3F4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
21583#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
21584#define D3F4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
21585#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
21586#define D3F4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
21587#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
21588#define D3F4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
21589#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
21590#define D3F4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
21591#define D3F4_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
21592#define D3F4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
21593#define D3F4_SSID_CAP_LIST__CAP_ID_MASK 0xff
21594#define D3F4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
21595#define D3F4_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
21596#define D3F4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
21597#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
21598#define D3F4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
21599#define D3F4_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
21600#define D3F4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
21601#define D3F4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
21602#define D3F4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
21603#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
21604#define D3F4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
21605#define D3F4_MSI_MAP_CAP__EN_MASK 0x10000
21606#define D3F4_MSI_MAP_CAP__EN__SHIFT 0x10
21607#define D3F4_MSI_MAP_CAP__FIXD_MASK 0x20000
21608#define D3F4_MSI_MAP_CAP__FIXD__SHIFT 0x11
21609#define D3F4_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
21610#define D3F4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
21611#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
21612#define D3F4_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
21613#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
21614#define D3F4_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
21615#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
21616#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
21617#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
21618#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
21619#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
21620#define D3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
21621#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
21622#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
21623#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
21624#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
21625#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
21626#define D3F4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
21627#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
21628#define D3F4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
21629#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
21630#define D3F4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
21631#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
21632#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
21633#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
21634#define D3F4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
21635#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
21636#define D3F4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
21637#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
21638#define D3F4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
21639#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
21640#define D3F4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
21641#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
21642#define D3F4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
21643#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
21644#define D3F4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
21645#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
21646#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
21647#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
21648#define D3F4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
21649#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
21650#define D3F4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
21651#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
21652#define D3F4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
21653#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
21654#define D3F4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
21655#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
21656#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
21657#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
21658#define D3F4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
21659#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
21660#define D3F4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
21661#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
21662#define D3F4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
21663#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
21664#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
21665#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
21666#define D3F4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
21667#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
21668#define D3F4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
21669#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
21670#define D3F4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
21671#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
21672#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
21673#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
21674#define D3F4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
21675#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
21676#define D3F4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
21677#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
21678#define D3F4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
21679#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
21680#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
21681#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
21682#define D3F4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
21683#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
21684#define D3F4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
21685#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
21686#define D3F4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
21687#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
21688#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
21689#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
21690#define D3F4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
21691#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
21692#define D3F4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
21693#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
21694#define D3F4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
21695#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
21696#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
21697#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
21698#define D3F4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
21699#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
21700#define D3F4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
21701#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
21702#define D3F4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
21703#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
21704#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
21705#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
21706#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
21707#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
21708#define D3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
21709#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
21710#define D3F4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
21711#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
21712#define D3F4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
21713#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
21714#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
21715#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
21716#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
21717#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
21718#define D3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
21719#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
21720#define D3F4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
21721#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
21722#define D3F4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
21723#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
21724#define D3F4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
21725#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
21726#define D3F4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
21727#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
21728#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
21729#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
21730#define D3F4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
21731#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
21732#define D3F4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
21733#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
21734#define D3F4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
21735#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
21736#define D3F4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
21737#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
21738#define D3F4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
21739#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
21740#define D3F4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
21741#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
21742#define D3F4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
21743#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
21744#define D3F4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
21745#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
21746#define D3F4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
21747#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
21748#define D3F4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
21749#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
21750#define D3F4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
21751#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
21752#define D3F4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
21753#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
21754#define D3F4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
21755#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
21756#define D3F4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
21757#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
21758#define D3F4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
21759#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
21760#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
21761#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
21762#define D3F4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
21763#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
21764#define D3F4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
21765#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
21766#define D3F4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
21767#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
21768#define D3F4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
21769#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
21770#define D3F4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
21771#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
21772#define D3F4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
21773#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
21774#define D3F4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
21775#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
21776#define D3F4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
21777#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
21778#define D3F4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
21779#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
21780#define D3F4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
21781#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
21782#define D3F4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
21783#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
21784#define D3F4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
21785#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
21786#define D3F4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
21787#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
21788#define D3F4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
21789#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
21790#define D3F4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
21791#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
21792#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
21793#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
21794#define D3F4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
21795#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
21796#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
21797#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
21798#define D3F4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
21799#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
21800#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
21801#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
21802#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
21803#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
21804#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
21805#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
21806#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
21807#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
21808#define D3F4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
21809#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
21810#define D3F4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
21811#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
21812#define D3F4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
21813#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
21814#define D3F4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
21815#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
21816#define D3F4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
21817#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
21818#define D3F4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
21819#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
21820#define D3F4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
21821#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
21822#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
21823#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
21824#define D3F4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
21825#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
21826#define D3F4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
21827#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
21828#define D3F4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
21829#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
21830#define D3F4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
21831#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
21832#define D3F4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
21833#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
21834#define D3F4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
21835#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
21836#define D3F4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
21837#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
21838#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
21839#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
21840#define D3F4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
21841#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
21842#define D3F4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
21843#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
21844#define D3F4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
21845#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
21846#define D3F4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
21847#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
21848#define D3F4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
21849#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
21850#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
21851#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
21852#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
21853#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
21854#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
21855#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
21856#define D3F4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
21857#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
21858#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
21859#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
21860#define D3F4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
21861#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
21862#define D3F4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
21863#define D3F4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
21864#define D3F4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
21865#define D3F4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
21866#define D3F4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
21867#define D3F4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
21868#define D3F4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
21869#define D3F4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
21870#define D3F4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
21871#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
21872#define D3F4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
21873#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
21874#define D3F4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
21875#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
21876#define D3F4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
21877#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
21878#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
21879#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
21880#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
21881#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
21882#define D3F4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
21883#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
21884#define D3F4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
21885#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
21886#define D3F4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
21887#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
21888#define D3F4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
21889#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
21890#define D3F4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
21891#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
21892#define D3F4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
21893#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
21894#define D3F4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
21895#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
21896#define D3F4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
21897#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
21898#define D3F4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
21899#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
21900#define D3F4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
21901#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
21902#define D3F4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
21903#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
21904#define D3F4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
21905#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
21906#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
21907#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
21908#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
21909#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
21910#define D3F4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
21911#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
21912#define D3F4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
21913#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
21914#define D3F4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
21915#define D3F4_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
21916#define D3F4_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
21917#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
21918#define D3F4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
21919#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
21920#define D3F4_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
21921#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
21922#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
21923#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
21924#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
21925#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
21926#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
21927#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
21928#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
21929#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
21930#define D3F4_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
21931#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
21932#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
21933#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
21934#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
21935#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
21936#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
21937#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
21938#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
21939#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
21940#define D3F4_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
21941#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
21942#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
21943#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
21944#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
21945#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
21946#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
21947#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
21948#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
21949#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
21950#define D3F4_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
21951#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
21952#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
21953#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
21954#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
21955#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
21956#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
21957#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
21958#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
21959#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
21960#define D3F4_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
21961#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
21962#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
21963#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
21964#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
21965#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
21966#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
21967#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
21968#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
21969#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
21970#define D3F4_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
21971#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
21972#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
21973#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
21974#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
21975#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
21976#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
21977#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
21978#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
21979#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
21980#define D3F4_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
21981#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
21982#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
21983#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
21984#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
21985#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
21986#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
21987#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
21988#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
21989#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
21990#define D3F4_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
21991#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
21992#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
21993#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
21994#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
21995#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
21996#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
21997#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
21998#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
21999#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
22000#define D3F4_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
22001#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
22002#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
22003#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
22004#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
22005#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
22006#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
22007#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
22008#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
22009#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
22010#define D3F4_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
22011#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
22012#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
22013#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
22014#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
22015#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
22016#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
22017#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
22018#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
22019#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
22020#define D3F4_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
22021#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
22022#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
22023#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
22024#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
22025#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
22026#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
22027#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
22028#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
22029#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
22030#define D3F4_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
22031#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
22032#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
22033#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
22034#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
22035#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
22036#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
22037#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
22038#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
22039#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
22040#define D3F4_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
22041#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
22042#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
22043#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
22044#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
22045#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
22046#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
22047#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
22048#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
22049#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
22050#define D3F4_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
22051#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
22052#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
22053#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
22054#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
22055#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
22056#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
22057#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
22058#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
22059#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
22060#define D3F4_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
22061#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
22062#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
22063#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
22064#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
22065#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
22066#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
22067#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
22068#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
22069#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
22070#define D3F4_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
22071#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
22072#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
22073#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
22074#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
22075#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
22076#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
22077#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
22078#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
22079#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
22080#define D3F4_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
22081#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
22082#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
22083#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
22084#define D3F4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
22085#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
22086#define D3F4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
22087#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
22088#define D3F4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
22089#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
22090#define D3F4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
22091#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
22092#define D3F4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
22093#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
22094#define D3F4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
22095#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
22096#define D3F4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
22097#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
22098#define D3F4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
22099#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
22100#define D3F4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
22101#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
22102#define D3F4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
22103#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
22104#define D3F4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
22105#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
22106#define D3F4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
22107#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
22108#define D3F4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
22109#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
22110#define D3F4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
22111#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
22112#define D3F4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
22113#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
22114#define D3F4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
22115#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
22116#define D3F4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
22117#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
22118#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
22119#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
22120#define D3F4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
22121#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
22122#define D3F4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
22123#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
22124#define D3F4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
22125#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
22126#define D3F4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
22127#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
22128#define D3F4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
22129#define D3F4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
22130#define D3F4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
22131#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
22132#define D3F4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
22133#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
22134#define D3F4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
22135#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
22136#define D3F4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
22137#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
22138#define D3F4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
22139#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
22140#define D3F4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
22141#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
22142#define D3F4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
22143#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
22144#define D3F4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
22145#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
22146#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
22147#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
22148#define D3F4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
22149#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
22150#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
22151#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
22152#define D3F4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
22153#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
22154#define D3F4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
22155#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX_MASK 0xff
22156#define D3F5_PCIE_PORT_INDEX__PCIE_INDEX__SHIFT 0x0
22157#define D3F5_PCIE_PORT_DATA__PCIE_DATA_MASK 0xffffffff
22158#define D3F5_PCIE_PORT_DATA__PCIE_DATA__SHIFT 0x0
22159#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xffffffff
22160#define D3F5_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
22161#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xffffffff
22162#define D3F5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
22163#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG_MASK 0x1
22164#define D3F5_PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
22165#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG_MASK 0x2
22166#define D3F5_PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
22167#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG_MASK 0x4
22168#define D3F5_PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
22169#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG_MASK 0x8
22170#define D3F5_PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
22171#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG_MASK 0x10
22172#define D3F5_PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
22173#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG_MASK 0x20
22174#define D3F5_PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
22175#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG_MASK 0x40
22176#define D3F5_PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
22177#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG_MASK 0x80
22178#define D3F5_PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
22179#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG_MASK 0x100
22180#define D3F5_PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
22181#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG_MASK 0x200
22182#define D3F5_PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
22183#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG_MASK 0x400
22184#define D3F5_PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
22185#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG_MASK 0x800
22186#define D3F5_PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
22187#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
22188#define D3F5_PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
22189#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
22190#define D3F5_PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
22191#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
22192#define D3F5_PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
22193#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
22194#define D3F5_PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
22195#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x1
22196#define D3F5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
22197#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x2
22198#define D3F5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
22199#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x4
22200#define D3F5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
22201#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x8
22202#define D3F5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
22203#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x10
22204#define D3F5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
22205#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x20
22206#define D3F5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
22207#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK 0x40
22208#define D3F5_PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT 0x6
22209#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x7f00
22210#define D3F5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
22211#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x30000
22212#define D3F5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x10
22213#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x1c0000
22214#define D3F5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
22215#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0xc00
22216#define D3F5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
22217#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x3000
22218#define D3F5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
22219#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x4000
22220#define D3F5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
22221#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x8000
22222#define D3F5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
22223#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x100000
22224#define D3F5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
22225#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x200000
22226#define D3F5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
22227#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x400000
22228#define D3F5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
22229#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x800000
22230#define D3F5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
22231#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x7
22232#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
22233#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0xf8
22234#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
22235#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0xff00
22236#define D3F5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
22237#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0xffffff
22238#define D3F5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
22239#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3f000000
22240#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
22241#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000
22242#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
22243#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000
22244#define D3F5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
22245#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0xfff
22246#define D3F5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
22247#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0xfff0000
22248#define D3F5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
22249#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x7
22250#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
22251#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x8000
22252#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
22253#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xffff0000
22254#define D3F5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
22255#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0xfff
22256#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
22257#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x1000
22258#define D3F5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
22259#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0xfff
22260#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
22261#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0xff0000
22262#define D3F5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
22263#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0xfff
22264#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
22265#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0xff0000
22266#define D3F5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
22267#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0xfff
22268#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
22269#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0xff0000
22270#define D3F5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
22271#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0xfff
22272#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
22273#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0xff0000
22274#define D3F5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
22275#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0xfff
22276#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
22277#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0xff0000
22278#define D3F5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
22279#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0xfff
22280#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
22281#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0xff0000
22282#define D3F5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
22283#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x1
22284#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
22285#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x2
22286#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
22287#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x4
22288#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
22289#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x8
22290#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
22291#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x10
22292#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
22293#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x20
22294#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
22295#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x10000
22296#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
22297#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x20000
22298#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
22299#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x40000
22300#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
22301#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x80000
22302#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
22303#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x100000
22304#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
22305#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x200000
22306#define D3F5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
22307#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x7
22308#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
22309#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x70
22310#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
22311#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x700
22312#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
22313#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x70000
22314#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
22315#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x700000
22316#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
22317#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x7000000
22318#define D3F5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
22319#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x1
22320#define D3F5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
22321#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x7e
22322#define D3F5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
22323#define D3F5_PCIE_FC_P__PD_CREDITS_MASK 0xff
22324#define D3F5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
22325#define D3F5_PCIE_FC_P__PH_CREDITS_MASK 0xff00
22326#define D3F5_PCIE_FC_P__PH_CREDITS__SHIFT 0x8
22327#define D3F5_PCIE_FC_NP__NPD_CREDITS_MASK 0xff
22328#define D3F5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
22329#define D3F5_PCIE_FC_NP__NPH_CREDITS_MASK 0xff00
22330#define D3F5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x8
22331#define D3F5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0xff
22332#define D3F5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
22333#define D3F5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0xff00
22334#define D3F5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x8
22335#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x1
22336#define D3F5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
22337#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x2
22338#define D3F5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
22339#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x4
22340#define D3F5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
22341#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x10
22342#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
22343#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x20
22344#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
22345#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x40
22346#define D3F5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
22347#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x80
22348#define D3F5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
22349#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x700
22350#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
22351#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x800
22352#define D3F5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
22353#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x4000
22354#define D3F5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
22355#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x8000
22356#define D3F5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
22357#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x10000
22358#define D3F5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
22359#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x20000
22360#define D3F5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
22361#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x40000
22362#define D3F5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
22363#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x1
22364#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
22365#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x2
22366#define D3F5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
22367#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x4
22368#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
22369#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x8
22370#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
22371#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x10
22372#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
22373#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x20
22374#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
22375#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x40
22376#define D3F5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
22377#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
22378#define D3F5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
22379#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
22380#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
22381#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x200
22382#define D3F5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
22383#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x400
22384#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
22385#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x800
22386#define D3F5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
22387#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x1000
22388#define D3F5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
22389#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x2000
22390#define D3F5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
22391#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK 0x4000
22392#define D3F5_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT 0xe
22393#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x8000
22394#define D3F5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
22395#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x70000
22396#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
22397#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x80000
22398#define D3F5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
22399#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x100000
22400#define D3F5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
22401#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x200000
22402#define D3F5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
22403#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x400000
22404#define D3F5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
22405#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x800000
22406#define D3F5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
22407#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x1000000
22408#define D3F5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
22409#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x2000000
22410#define D3F5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
22411#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x4000000
22412#define D3F5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
22413#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x8000000
22414#define D3F5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
22415#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0xfff
22416#define D3F5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
22417#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0xffffff
22418#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
22419#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x1000000
22420#define D3F5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
22421#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x1
22422#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
22423#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x2
22424#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
22425#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x4
22426#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
22427#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x8
22428#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
22429#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x10
22430#define D3F5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
22431#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0xfff
22432#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
22433#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0xff0000
22434#define D3F5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
22435#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0xfff
22436#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
22437#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0xff0000
22438#define D3F5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
22439#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0xfff
22440#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
22441#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0xff0000
22442#define D3F5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
22443#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x3
22444#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
22445#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0xc
22446#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
22447#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x30
22448#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
22449#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0xc0
22450#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
22451#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x300
22452#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
22453#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0xc00
22454#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
22455#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x3000
22456#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
22457#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0xc000
22458#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
22459#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x30000
22460#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
22461#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0xc0000
22462#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
22463#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x300000
22464#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
22465#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0xc00000
22466#define D3F5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
22467#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x3
22468#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
22469#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0xc
22470#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
22471#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x30
22472#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
22473#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0xc0
22474#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
22475#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x300
22476#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
22477#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0xc00
22478#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
22479#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x3000
22480#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
22481#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0xc000
22482#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
22483#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x30000
22484#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
22485#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0xc0000
22486#define D3F5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
22487#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x2
22488#define D3F5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
22489#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x4
22490#define D3F5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
22491#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x8
22492#define D3F5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
22493#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0xf0
22494#define D3F5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
22495#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0xf00
22496#define D3F5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
22497#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0xf000
22498#define D3F5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
22499#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x10000
22500#define D3F5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
22501#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x20000
22502#define D3F5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
22503#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0xc0000
22504#define D3F5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
22505#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x100000
22506#define D3F5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
22507#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x200000
22508#define D3F5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
22509#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x400000
22510#define D3F5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
22511#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x800000
22512#define D3F5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
22513#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x1000000
22514#define D3F5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
22515#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x6000000
22516#define D3F5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
22517#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x8000000
22518#define D3F5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
22519#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000
22520#define D3F5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
22521#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000
22522#define D3F5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
22523#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000
22524#define D3F5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
22525#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000
22526#define D3F5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
22527#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x3f
22528#define D3F5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
22529#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x40
22530#define D3F5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
22531#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x80
22532#define D3F5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
22533#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x100
22534#define D3F5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
22535#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x200
22536#define D3F5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
22537#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x400
22538#define D3F5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
22539#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x800
22540#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
22541#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x1000
22542#define D3F5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
22543#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x2000
22544#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
22545#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0xc000
22546#define D3F5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
22547#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x10000
22548#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
22549#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x20000
22550#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
22551#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x40000
22552#define D3F5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
22553#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK 0x80000
22554#define D3F5_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT 0x13
22555#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x100000
22556#define D3F5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
22557#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x200000
22558#define D3F5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
22559#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x400000
22560#define D3F5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
22561#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x1800000
22562#define D3F5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
22563#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x2000000
22564#define D3F5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
22565#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x4000000
22566#define D3F5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
22567#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x8000000
22568#define D3F5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
22569#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000
22570#define D3F5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
22571#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000
22572#define D3F5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
22573#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000
22574#define D3F5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
22575#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x1
22576#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
22577#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x6
22578#define D3F5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
22579#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x8
22580#define D3F5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
22581#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x10
22582#define D3F5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
22583#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x20
22584#define D3F5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
22585#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc0
22586#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
22587#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x100
22588#define D3F5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
22589#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x200
22590#define D3F5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
22591#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x400
22592#define D3F5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
22593#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x800
22594#define D3F5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
22595#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK 0x3000
22596#define D3F5_PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT 0xc
22597#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK 0xc000
22598#define D3F5_PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT 0xe
22599#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK 0x10000
22600#define D3F5_PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT 0x10
22601#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x20000
22602#define D3F5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
22603#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x40000
22604#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
22605#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x180000
22606#define D3F5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
22607#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x200000
22608#define D3F5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
22609#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK 0x400000
22610#define D3F5_PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT 0x16
22611#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x800000
22612#define D3F5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
22613#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x3000000
22614#define D3F5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
22615#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3c000000
22616#define D3F5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
22617#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000
22618#define D3F5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
22619#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK 0x80000000
22620#define D3F5_PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT 0x1f
22621#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x3
22622#define D3F5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
22623#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x4
22624#define D3F5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
22625#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x8
22626#define D3F5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
22627#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK 0x10
22628#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT 0x4
22629#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ_MASK 0x20
22630#define D3F5_PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT 0x5
22631#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x40
22632#define D3F5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
22633#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x80
22634#define D3F5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
22635#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK 0x300
22636#define D3F5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT 0x8
22637#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x400
22638#define D3F5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
22639#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK 0x800
22640#define D3F5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT 0xb
22641#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK 0x1000
22642#define D3F5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT 0xc
22643#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x2000
22644#define D3F5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
22645#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x4000
22646#define D3F5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
22647#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK 0x8000
22648#define D3F5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT 0xf
22649#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK 0x10000
22650#define D3F5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x10
22651#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK 0x20000
22652#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT 0x11
22653#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK 0x3c0000
22654#define D3F5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT 0x12
22655#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x400000
22656#define D3F5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
22657#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK 0x800000
22658#define D3F5_PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT 0x17
22659#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x1000000
22660#define D3F5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
22661#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x2000000
22662#define D3F5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
22663#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xfc000000
22664#define D3F5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
22665#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0_MASK 0x3f
22666#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT 0x0
22667#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8_MASK 0xfc0
22668#define D3F5_PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT 0x6
22669#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0_MASK 0x3f000
22670#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT 0xc
22671#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8_MASK 0xfc0000
22672#define D3F5_PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT 0x12
22673#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x1000000
22674#define D3F5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
22675#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x1
22676#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
22677#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x4
22678#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
22679#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x10
22680#define D3F5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
22681#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x1
22682#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
22683#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x2
22684#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
22685#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x4
22686#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
22687#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x8
22688#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
22689#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x10
22690#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
22691#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x20
22692#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
22693#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x40
22694#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
22695#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x80
22696#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
22697#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x100
22698#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
22699#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x200
22700#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
22701#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x400
22702#define D3F5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
22703#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0xf
22704#define D3F5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
22705#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x10
22706#define D3F5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
22707#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x20
22708#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
22709#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x40
22710#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
22711#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x80
22712#define D3F5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
22713#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x700
22714#define D3F5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
22715#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x800
22716#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
22717#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x1000
22718#define D3F5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
22719#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x2000
22720#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
22721#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x4000
22722#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
22723#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x8000
22724#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
22725#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x10000
22726#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
22727#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x20000
22728#define D3F5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
22729#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x40000
22730#define D3F5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
22731#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x80000
22732#define D3F5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
22733#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x100000
22734#define D3F5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
22735#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x200000
22736#define D3F5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
22737#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0xc00000
22738#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
22739#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x1000000
22740#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
22741#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x2000000
22742#define D3F5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
22743#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x4000000
22744#define D3F5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
22745#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x8000000
22746#define D3F5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
22747#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000
22748#define D3F5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
22749#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000
22750#define D3F5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
22751#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xc0000000
22752#define D3F5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
22753#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x7
22754#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
22755#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70
22756#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
22757#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x80
22758#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
22759#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x100
22760#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
22761#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x200
22762#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
22763#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x400
22764#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
22765#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x800
22766#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
22767#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000
22768#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
22769#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x2000
22770#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
22771#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x4000
22772#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
22773#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x8000
22774#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
22775#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK 0x10000
22776#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT 0x10
22777#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x20000
22778#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
22779#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x40000
22780#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
22781#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x80000
22782#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
22783#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x100000
22784#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
22785#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x600000
22786#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
22787#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x800000
22788#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
22789#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x1000000
22790#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
22791#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x2000000
22792#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
22793#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x4000000
22794#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
22795#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x8000000
22796#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
22797#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000
22798#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
22799#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000
22800#define D3F5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
22801#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0xff
22802#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
22803#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x100
22804#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
22805#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x200
22806#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
22807#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0xff0000
22808#define D3F5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
22809#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xff000000
22810#define D3F5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
22811#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x1
22812#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
22813#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x2
22814#define D3F5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
22815#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x4
22816#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x2
22817#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x18
22818#define D3F5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x3
22819#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x20
22820#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x5
22821#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x40
22822#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x6
22823#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x80
22824#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x7
22825#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x100
22826#define D3F5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x8
22827#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x200
22828#define D3F5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0x9
22829#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0xc00
22830#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xa
22831#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x1000
22832#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xc
22833#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x6000
22834#define D3F5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xd
22835#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x8000
22836#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0xf
22837#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x10000
22838#define D3F5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x10
22839#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x20000
22840#define D3F5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x11
22841#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x40000
22842#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x12
22843#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x80000
22844#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x13
22845#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x100000
22846#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x14
22847#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x200000
22848#define D3F5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x15
22849#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK 0x400000
22850#define D3F5_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT 0x16
22851#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x800000
22852#define D3F5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x17
22853#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x3000000
22854#define D3F5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x18
22855#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x4000000
22856#define D3F5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1a
22857#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x8000000
22858#define D3F5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1b
22859#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x10000000
22860#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1c
22861#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x20000000
22862#define D3F5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1d
22863#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x40000000
22864#define D3F5_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1e
22865#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x80000000
22866#define D3F5_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1f
22867#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0xfff
22868#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
22869#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0xfff000
22870#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
22871#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x3000000
22872#define D3F5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
22873#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0xffff
22874#define D3F5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
22875#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK 0xffff0000
22876#define D3F5_PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT 0x10
22877#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK 0x1
22878#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT 0x0
22879#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK 0x7e
22880#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT 0x1
22881#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK 0x1f80
22882#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT 0x7
22883#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK 0x7e000
22884#define D3F5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT 0xd
22885#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK 0x80000
22886#define D3F5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT 0x13
22887#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x100000
22888#define D3F5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
22889#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0xf
22890#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
22891#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x3f0
22892#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
22893#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0xfc00
22894#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
22895#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x3f0000
22896#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
22897#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3fc00000
22898#define D3F5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
22899#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK 0x1
22900#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT 0x0
22901#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK 0x7e
22902#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT 0x1
22903#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK 0x1f80
22904#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT 0x7
22905#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK 0x7e000
22906#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT 0xd
22907#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK 0x1f80000
22908#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT 0x13
22909#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK 0x7e000000
22910#define D3F5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT 0x19
22911#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x3f
22912#define D3F5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
22913#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x3f00
22914#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
22915#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x3f0000
22916#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
22917#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3f000000
22918#define D3F5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
22919#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x3f
22920#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
22921#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x3f00
22922#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
22923#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x3f0000
22924#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
22925#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3f000000
22926#define D3F5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
22927#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x3f
22928#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
22929#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x3f00
22930#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
22931#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x3f0000
22932#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
22933#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3f000000
22934#define D3F5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
22935#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x3f
22936#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
22937#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x3f00
22938#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
22939#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x3f0000
22940#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
22941#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3f000000
22942#define D3F5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
22943#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x3f
22944#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
22945#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x3f00
22946#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
22947#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x3f0000
22948#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
22949#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3f000000
22950#define D3F5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
22951#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x3f
22952#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
22953#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x3f00
22954#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
22955#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x3f0000
22956#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
22957#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3f000000
22958#define D3F5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
22959#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x3
22960#define D3F5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
22961#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0xc
22962#define D3F5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
22963#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x30
22964#define D3F5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
22965#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0xc0
22966#define D3F5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
22967#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x700
22968#define D3F5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
22969#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x800
22970#define D3F5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
22971#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x1000
22972#define D3F5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
22973#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x2000
22974#define D3F5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
22975#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x4000
22976#define D3F5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
22977#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x8000
22978#define D3F5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
22979#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x70000
22980#define D3F5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
22981#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x1
22982#define D3F5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
22983#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x2
22984#define D3F5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
22985#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x4
22986#define D3F5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
22987#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x18
22988#define D3F5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
22989#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x20
22990#define D3F5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
22991#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x1
22992#define D3F5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
22993#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0xff00
22994#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
22995#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xffff0000
22996#define D3F5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
22997#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x8
22998#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
22999#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x40
23000#define D3F5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
23001#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x1
23002#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
23003#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x2
23004#define D3F5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
23005#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x4
23006#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
23007#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x8
23008#define D3F5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
23009#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x80
23010#define D3F5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
23011#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x100
23012#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
23013#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x200
23014#define D3F5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
23015#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x400
23016#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
23017#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x800
23018#define D3F5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
23019#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x8000
23020#define D3F5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
23021#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x10000
23022#define D3F5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
23023#define D3F5_VENDOR_ID__VENDOR_ID_MASK 0xffff
23024#define D3F5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
23025#define D3F5_DEVICE_ID__DEVICE_ID_MASK 0xffff0000
23026#define D3F5_DEVICE_ID__DEVICE_ID__SHIFT 0x10
23027#define D3F5_COMMAND__IO_ACCESS_EN_MASK 0x1
23028#define D3F5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
23029#define D3F5_COMMAND__MEM_ACCESS_EN_MASK 0x2
23030#define D3F5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
23031#define D3F5_COMMAND__BUS_MASTER_EN_MASK 0x4
23032#define D3F5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
23033#define D3F5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x8
23034#define D3F5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
23035#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x10
23036#define D3F5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
23037#define D3F5_COMMAND__PAL_SNOOP_EN_MASK 0x20
23038#define D3F5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
23039#define D3F5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x40
23040#define D3F5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
23041#define D3F5_COMMAND__AD_STEPPING_MASK 0x80
23042#define D3F5_COMMAND__AD_STEPPING__SHIFT 0x7
23043#define D3F5_COMMAND__SERR_EN_MASK 0x100
23044#define D3F5_COMMAND__SERR_EN__SHIFT 0x8
23045#define D3F5_COMMAND__FAST_B2B_EN_MASK 0x200
23046#define D3F5_COMMAND__FAST_B2B_EN__SHIFT 0x9
23047#define D3F5_COMMAND__INT_DIS_MASK 0x400
23048#define D3F5_COMMAND__INT_DIS__SHIFT 0xa
23049#define D3F5_STATUS__INT_STATUS_MASK 0x80000
23050#define D3F5_STATUS__INT_STATUS__SHIFT 0x13
23051#define D3F5_STATUS__CAP_LIST_MASK 0x100000
23052#define D3F5_STATUS__CAP_LIST__SHIFT 0x14
23053#define D3F5_STATUS__PCI_66_EN_MASK 0x200000
23054#define D3F5_STATUS__PCI_66_EN__SHIFT 0x15
23055#define D3F5_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
23056#define D3F5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
23057#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
23058#define D3F5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
23059#define D3F5_STATUS__DEVSEL_TIMING_MASK 0x6000000
23060#define D3F5_STATUS__DEVSEL_TIMING__SHIFT 0x19
23061#define D3F5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
23062#define D3F5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
23063#define D3F5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
23064#define D3F5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
23065#define D3F5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
23066#define D3F5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
23067#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x40000000
23068#define D3F5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0x1e
23069#define D3F5_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
23070#define D3F5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
23071#define D3F5_REVISION_ID__MINOR_REV_ID_MASK 0xf
23072#define D3F5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
23073#define D3F5_REVISION_ID__MAJOR_REV_ID_MASK 0xf0
23074#define D3F5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
23075#define D3F5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xff00
23076#define D3F5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x8
23077#define D3F5_SUB_CLASS__SUB_CLASS_MASK 0xff0000
23078#define D3F5_SUB_CLASS__SUB_CLASS__SHIFT 0x10
23079#define D3F5_BASE_CLASS__BASE_CLASS_MASK 0xff000000
23080#define D3F5_BASE_CLASS__BASE_CLASS__SHIFT 0x18
23081#define D3F5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xff
23082#define D3F5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
23083#define D3F5_LATENCY__LATENCY_TIMER_MASK 0xff00
23084#define D3F5_LATENCY__LATENCY_TIMER__SHIFT 0x8
23085#define D3F5_HEADER__HEADER_TYPE_MASK 0x7f0000
23086#define D3F5_HEADER__HEADER_TYPE__SHIFT 0x10
23087#define D3F5_HEADER__DEVICE_TYPE_MASK 0x800000
23088#define D3F5_HEADER__DEVICE_TYPE__SHIFT 0x17
23089#define D3F5_BIST__BIST_COMP_MASK 0xf000000
23090#define D3F5_BIST__BIST_COMP__SHIFT 0x18
23091#define D3F5_BIST__BIST_STRT_MASK 0x40000000
23092#define D3F5_BIST__BIST_STRT__SHIFT 0x1e
23093#define D3F5_BIST__BIST_CAP_MASK 0x80000000
23094#define D3F5_BIST__BIST_CAP__SHIFT 0x1f
23095#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0xff
23096#define D3F5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
23097#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0xff00
23098#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
23099#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0xff0000
23100#define D3F5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
23101#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xff000000
23102#define D3F5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
23103#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0xf
23104#define D3F5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
23105#define D3F5_IO_BASE_LIMIT__IO_BASE_MASK 0xf0
23106#define D3F5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
23107#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0xf00
23108#define D3F5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
23109#define D3F5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xf000
23110#define D3F5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
23111#define D3F5_SECONDARY_STATUS__CAP_LIST_MASK 0x100000
23112#define D3F5_SECONDARY_STATUS__CAP_LIST__SHIFT 0x14
23113#define D3F5_SECONDARY_STATUS__PCI_66_EN_MASK 0x200000
23114#define D3F5_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x15
23115#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x800000
23116#define D3F5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x17
23117#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x1000000
23118#define D3F5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x18
23119#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x6000000
23120#define D3F5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x19
23121#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x8000000
23122#define D3F5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0x1b
23123#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x10000000
23124#define D3F5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0x1c
23125#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x20000000
23126#define D3F5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0x1d
23127#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x40000000
23128#define D3F5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0x1e
23129#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x80000000
23130#define D3F5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0x1f
23131#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0xf
23132#define D3F5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
23133#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0xfff0
23134#define D3F5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
23135#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0xf0000
23136#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
23137#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xfff00000
23138#define D3F5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
23139#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0xf
23140#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
23141#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0xfff0
23142#define D3F5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
23143#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0xf0000
23144#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
23145#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xfff00000
23146#define D3F5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
23147#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xffffffff
23148#define D3F5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
23149#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xffffffff
23150#define D3F5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
23151#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0xffff
23152#define D3F5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
23153#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xffff0000
23154#define D3F5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
23155#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x10000
23156#define D3F5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x10
23157#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x20000
23158#define D3F5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x11
23159#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x40000
23160#define D3F5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x12
23161#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x80000
23162#define D3F5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x13
23163#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x100000
23164#define D3F5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x14
23165#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x200000
23166#define D3F5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x15
23167#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x400000
23168#define D3F5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x16
23169#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x800000
23170#define D3F5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x17
23171#define D3F5_CAP_PTR__CAP_PTR_MASK 0xff
23172#define D3F5_CAP_PTR__CAP_PTR__SHIFT 0x0
23173#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xff
23174#define D3F5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
23175#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xff00
23176#define D3F5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x8
23177#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x1
23178#define D3F5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
23179#define D3F5_PMI_CAP_LIST__CAP_ID_MASK 0xff
23180#define D3F5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
23181#define D3F5_PMI_CAP_LIST__NEXT_PTR_MASK 0xff00
23182#define D3F5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
23183#define D3F5_PMI_CAP__VERSION_MASK 0x70000
23184#define D3F5_PMI_CAP__VERSION__SHIFT 0x10
23185#define D3F5_PMI_CAP__PME_CLOCK_MASK 0x80000
23186#define D3F5_PMI_CAP__PME_CLOCK__SHIFT 0x13
23187#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x200000
23188#define D3F5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x15
23189#define D3F5_PMI_CAP__AUX_CURRENT_MASK 0x1c00000
23190#define D3F5_PMI_CAP__AUX_CURRENT__SHIFT 0x16
23191#define D3F5_PMI_CAP__D1_SUPPORT_MASK 0x2000000
23192#define D3F5_PMI_CAP__D1_SUPPORT__SHIFT 0x19
23193#define D3F5_PMI_CAP__D2_SUPPORT_MASK 0x4000000
23194#define D3F5_PMI_CAP__D2_SUPPORT__SHIFT 0x1a
23195#define D3F5_PMI_CAP__PME_SUPPORT_MASK 0xf8000000
23196#define D3F5_PMI_CAP__PME_SUPPORT__SHIFT 0x1b
23197#define D3F5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x3
23198#define D3F5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
23199#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x8
23200#define D3F5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
23201#define D3F5_PMI_STATUS_CNTL__PME_EN_MASK 0x100
23202#define D3F5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
23203#define D3F5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x1e00
23204#define D3F5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
23205#define D3F5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x6000
23206#define D3F5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
23207#define D3F5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x8000
23208#define D3F5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
23209#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x400000
23210#define D3F5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
23211#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x800000
23212#define D3F5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
23213#define D3F5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xff000000
23214#define D3F5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
23215#define D3F5_PCIE_CAP_LIST__CAP_ID_MASK 0xff
23216#define D3F5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
23217#define D3F5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xff00
23218#define D3F5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
23219#define D3F5_PCIE_CAP__VERSION_MASK 0xf0000
23220#define D3F5_PCIE_CAP__VERSION__SHIFT 0x10
23221#define D3F5_PCIE_CAP__DEVICE_TYPE_MASK 0xf00000
23222#define D3F5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x14
23223#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x1000000
23224#define D3F5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x18
23225#define D3F5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3e000000
23226#define D3F5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x19
23227#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x7
23228#define D3F5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
23229#define D3F5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x18
23230#define D3F5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
23231#define D3F5_DEVICE_CAP__EXTENDED_TAG_MASK 0x20
23232#define D3F5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
23233#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x1c0
23234#define D3F5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
23235#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0xe00
23236#define D3F5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
23237#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x8000
23238#define D3F5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
23239#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x3fc0000
23240#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
23241#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0xc000000
23242#define D3F5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
23243#define D3F5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000
23244#define D3F5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
23245#define D3F5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x1
23246#define D3F5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
23247#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x2
23248#define D3F5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
23249#define D3F5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x4
23250#define D3F5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
23251#define D3F5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x8
23252#define D3F5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
23253#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x10
23254#define D3F5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
23255#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0xe0
23256#define D3F5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
23257#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x100
23258#define D3F5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
23259#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x200
23260#define D3F5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
23261#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x400
23262#define D3F5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
23263#define D3F5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x800
23264#define D3F5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
23265#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000
23266#define D3F5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
23267#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000
23268#define D3F5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
23269#define D3F5_DEVICE_STATUS__CORR_ERR_MASK 0x10000
23270#define D3F5_DEVICE_STATUS__CORR_ERR__SHIFT 0x10
23271#define D3F5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x20000
23272#define D3F5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x11
23273#define D3F5_DEVICE_STATUS__FATAL_ERR_MASK 0x40000
23274#define D3F5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x12
23275#define D3F5_DEVICE_STATUS__USR_DETECTED_MASK 0x80000
23276#define D3F5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x13
23277#define D3F5_DEVICE_STATUS__AUX_PWR_MASK 0x100000
23278#define D3F5_DEVICE_STATUS__AUX_PWR__SHIFT 0x14
23279#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x200000
23280#define D3F5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x15
23281#define D3F5_LINK_CAP__LINK_SPEED_MASK 0xf
23282#define D3F5_LINK_CAP__LINK_SPEED__SHIFT 0x0
23283#define D3F5_LINK_CAP__LINK_WIDTH_MASK 0x3f0
23284#define D3F5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
23285#define D3F5_LINK_CAP__PM_SUPPORT_MASK 0xc00
23286#define D3F5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
23287#define D3F5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x7000
23288#define D3F5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
23289#define D3F5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x38000
23290#define D3F5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
23291#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x40000
23292#define D3F5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
23293#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x80000
23294#define D3F5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
23295#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x100000
23296#define D3F5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
23297#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x200000
23298#define D3F5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
23299#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x400000
23300#define D3F5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
23301#define D3F5_LINK_CAP__PORT_NUMBER_MASK 0xff000000
23302#define D3F5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
23303#define D3F5_LINK_CNTL__PM_CONTROL_MASK 0x3
23304#define D3F5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
23305#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x8
23306#define D3F5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
23307#define D3F5_LINK_CNTL__LINK_DIS_MASK 0x10
23308#define D3F5_LINK_CNTL__LINK_DIS__SHIFT 0x4
23309#define D3F5_LINK_CNTL__RETRAIN_LINK_MASK 0x20
23310#define D3F5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
23311#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x40
23312#define D3F5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
23313#define D3F5_LINK_CNTL__EXTENDED_SYNC_MASK 0x80
23314#define D3F5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
23315#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x100
23316#define D3F5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
23317#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x200
23318#define D3F5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
23319#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x400
23320#define D3F5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
23321#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x800
23322#define D3F5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
23323#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0xf0000
23324#define D3F5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x10
23325#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x3f00000
23326#define D3F5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x14
23327#define D3F5_LINK_STATUS__LINK_TRAINING_MASK 0x8000000
23328#define D3F5_LINK_STATUS__LINK_TRAINING__SHIFT 0x1b
23329#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x10000000
23330#define D3F5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0x1c
23331#define D3F5_LINK_STATUS__DL_ACTIVE_MASK 0x20000000
23332#define D3F5_LINK_STATUS__DL_ACTIVE__SHIFT 0x1d
23333#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x40000000
23334#define D3F5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0x1e
23335#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x80000000
23336#define D3F5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0x1f
23337#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x1
23338#define D3F5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
23339#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x2
23340#define D3F5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
23341#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x4
23342#define D3F5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
23343#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x8
23344#define D3F5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
23345#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x10
23346#define D3F5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
23347#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x20
23348#define D3F5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
23349#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x40
23350#define D3F5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
23351#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x7f80
23352#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
23353#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x18000
23354#define D3F5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
23355#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x20000
23356#define D3F5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
23357#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x40000
23358#define D3F5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
23359#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xfff80000
23360#define D3F5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
23361#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x1
23362#define D3F5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
23363#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x2
23364#define D3F5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
23365#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x4
23366#define D3F5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
23367#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x8
23368#define D3F5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
23369#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x10
23370#define D3F5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
23371#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x20
23372#define D3F5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
23373#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0xc0
23374#define D3F5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
23375#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x300
23376#define D3F5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
23377#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x400
23378#define D3F5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
23379#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x800
23380#define D3F5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
23381#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000
23382#define D3F5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
23383#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x10000
23384#define D3F5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x10
23385#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x20000
23386#define D3F5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x11
23387#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x40000
23388#define D3F5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x12
23389#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x80000
23390#define D3F5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x13
23391#define D3F5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x100000
23392#define D3F5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x14
23393#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x200000
23394#define D3F5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x15
23395#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x400000
23396#define D3F5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x16
23397#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x800000
23398#define D3F5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x17
23399#define D3F5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x1000000
23400#define D3F5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x18
23401#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x1
23402#define D3F5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
23403#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x2
23404#define D3F5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
23405#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x4
23406#define D3F5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
23407#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x8
23408#define D3F5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
23409#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x10
23410#define D3F5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
23411#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x10000
23412#define D3F5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x10
23413#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0xffff
23414#define D3F5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
23415#define D3F5_ROOT_STATUS__PME_STATUS_MASK 0x10000
23416#define D3F5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
23417#define D3F5_ROOT_STATUS__PME_PENDING_MASK 0x20000
23418#define D3F5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
23419#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0xf
23420#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
23421#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x10
23422#define D3F5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
23423#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x20
23424#define D3F5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
23425#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x40
23426#define D3F5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
23427#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x80
23428#define D3F5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
23429#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x100
23430#define D3F5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
23431#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x200
23432#define D3F5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
23433#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x400
23434#define D3F5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
23435#define D3F5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x800
23436#define D3F5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
23437#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x3000
23438#define D3F5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
23439#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0xc0000
23440#define D3F5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
23441#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x100000
23442#define D3F5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
23443#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x200000
23444#define D3F5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
23445#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0xc00000
23446#define D3F5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
23447#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0xf
23448#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
23449#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x10
23450#define D3F5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
23451#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x20
23452#define D3F5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
23453#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x40
23454#define D3F5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
23455#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x80
23456#define D3F5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
23457#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x100
23458#define D3F5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
23459#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x200
23460#define D3F5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
23461#define D3F5_DEVICE_CNTL2__LTR_EN_MASK 0x400
23462#define D3F5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
23463#define D3F5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000
23464#define D3F5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
23465#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000
23466#define D3F5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
23467#define D3F5_DEVICE_STATUS2__RESERVED_MASK 0xffff0000
23468#define D3F5_DEVICE_STATUS2__RESERVED__SHIFT 0x10
23469#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0xfe
23470#define D3F5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
23471#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x100
23472#define D3F5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
23473#define D3F5_LINK_CAP2__RESERVED_MASK 0xfffffe00
23474#define D3F5_LINK_CAP2__RESERVED__SHIFT 0x9
23475#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0xf
23476#define D3F5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
23477#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x10
23478#define D3F5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
23479#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x20
23480#define D3F5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
23481#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x40
23482#define D3F5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
23483#define D3F5_LINK_CNTL2__XMIT_MARGIN_MASK 0x380
23484#define D3F5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
23485#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x400
23486#define D3F5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
23487#define D3F5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x800
23488#define D3F5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
23489#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xf000
23490#define D3F5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
23491#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x10000
23492#define D3F5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x10
23493#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x20000
23494#define D3F5_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x11
23495#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x40000
23496#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x12
23497#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x80000
23498#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x13
23499#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x100000
23500#define D3F5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x14
23501#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x200000
23502#define D3F5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x15
23503#define D3F5_SLOT_CAP2__RESERVED_MASK 0xffffffff
23504#define D3F5_SLOT_CAP2__RESERVED__SHIFT 0x0
23505#define D3F5_SLOT_CNTL2__RESERVED_MASK 0xffff
23506#define D3F5_SLOT_CNTL2__RESERVED__SHIFT 0x0
23507#define D3F5_SLOT_STATUS2__RESERVED_MASK 0xffff0000
23508#define D3F5_SLOT_STATUS2__RESERVED__SHIFT 0x10
23509#define D3F5_MSI_CAP_LIST__CAP_ID_MASK 0xff
23510#define D3F5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
23511#define D3F5_MSI_CAP_LIST__NEXT_PTR_MASK 0xff00
23512#define D3F5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
23513#define D3F5_MSI_MSG_CNTL__MSI_EN_MASK 0x10000
23514#define D3F5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x10
23515#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0xe0000
23516#define D3F5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x11
23517#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x700000
23518#define D3F5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x14
23519#define D3F5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x800000
23520#define D3F5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x17
23521#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x1000000
23522#define D3F5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x18
23523#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xfffffffc
23524#define D3F5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
23525#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xffffffff
23526#define D3F5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
23527#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xffff
23528#define D3F5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
23529#define D3F5_MSI_MSG_DATA__MSI_DATA_MASK 0xffff
23530#define D3F5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
23531#define D3F5_SSID_CAP_LIST__CAP_ID_MASK 0xff
23532#define D3F5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
23533#define D3F5_SSID_CAP_LIST__NEXT_PTR_MASK 0xff00
23534#define D3F5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
23535#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0xffff
23536#define D3F5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
23537#define D3F5_SSID_CAP__SUBSYSTEM_ID_MASK 0xffff0000
23538#define D3F5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
23539#define D3F5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0xff
23540#define D3F5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
23541#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xff00
23542#define D3F5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
23543#define D3F5_MSI_MAP_CAP__EN_MASK 0x10000
23544#define D3F5_MSI_MAP_CAP__EN__SHIFT 0x10
23545#define D3F5_MSI_MAP_CAP__FIXD_MASK 0x20000
23546#define D3F5_MSI_MAP_CAP__FIXD__SHIFT 0x11
23547#define D3F5_MSI_MAP_CAP__CAP_TYPE_MASK 0xf8000000
23548#define D3F5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0x1b
23549#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xfff00000
23550#define D3F5_MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14
23551#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xffffffff
23552#define D3F5_MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0
23553#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
23554#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
23555#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
23556#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
23557#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
23558#define D3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
23559#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0xffff
23560#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
23561#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0xf0000
23562#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
23563#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xfff00000
23564#define D3F5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
23565#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xffffffff
23566#define D3F5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
23567#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xffffffff
23568#define D3F5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
23569#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
23570#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
23571#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
23572#define D3F5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
23573#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
23574#define D3F5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
23575#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x7
23576#define D3F5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
23577#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x70
23578#define D3F5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
23579#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x300
23580#define D3F5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
23581#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0xc00
23582#define D3F5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
23583#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0xff
23584#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
23585#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xff000000
23586#define D3F5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
23587#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x1
23588#define D3F5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
23589#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0xe
23590#define D3F5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
23591#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x10000
23592#define D3F5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x10
23593#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
23594#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
23595#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
23596#define D3F5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
23597#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
23598#define D3F5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
23599#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
23600#define D3F5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
23601#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
23602#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
23603#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
23604#define D3F5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
23605#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
23606#define D3F5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
23607#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
23608#define D3F5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
23609#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x7000000
23610#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
23611#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
23612#define D3F5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
23613#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
23614#define D3F5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
23615#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
23616#define D3F5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
23617#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0xff
23618#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
23619#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x8000
23620#define D3F5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
23621#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x3f0000
23622#define D3F5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
23623#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xff000000
23624#define D3F5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
23625#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x1
23626#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
23627#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0xfe
23628#define D3F5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
23629#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x10000
23630#define D3F5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
23631#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0xe0000
23632#define D3F5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
23633#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x7000000
23634#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
23635#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000
23636#define D3F5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
23637#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x10000
23638#define D3F5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x10
23639#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x20000
23640#define D3F5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x11
23641#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0xffff
23642#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
23643#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
23644#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
23645#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
23646#define D3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
23647#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xffffffff
23648#define D3F5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
23649#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xffffffff
23650#define D3F5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
23651#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0xffff
23652#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
23653#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
23654#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
23655#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
23656#define D3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
23657#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x10
23658#define D3F5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
23659#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x20
23660#define D3F5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
23661#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x1000
23662#define D3F5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
23663#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x2000
23664#define D3F5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
23665#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x4000
23666#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
23667#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x8000
23668#define D3F5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
23669#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x10000
23670#define D3F5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
23671#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x20000
23672#define D3F5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
23673#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x40000
23674#define D3F5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
23675#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x80000
23676#define D3F5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
23677#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x100000
23678#define D3F5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
23679#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x200000
23680#define D3F5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
23681#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x400000
23682#define D3F5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
23683#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x800000
23684#define D3F5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
23685#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x1000000
23686#define D3F5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
23687#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x2000000
23688#define D3F5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
23689#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x10
23690#define D3F5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
23691#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x20
23692#define D3F5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
23693#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x1000
23694#define D3F5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
23695#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x2000
23696#define D3F5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
23697#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x4000
23698#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
23699#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x8000
23700#define D3F5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
23701#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x10000
23702#define D3F5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
23703#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x20000
23704#define D3F5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
23705#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x40000
23706#define D3F5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
23707#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x80000
23708#define D3F5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
23709#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x100000
23710#define D3F5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
23711#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x200000
23712#define D3F5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
23713#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x400000
23714#define D3F5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
23715#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x800000
23716#define D3F5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
23717#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x1000000
23718#define D3F5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
23719#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x2000000
23720#define D3F5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
23721#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x10
23722#define D3F5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
23723#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x20
23724#define D3F5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
23725#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x1000
23726#define D3F5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
23727#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x2000
23728#define D3F5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
23729#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x4000
23730#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
23731#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x8000
23732#define D3F5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
23733#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x10000
23734#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
23735#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x20000
23736#define D3F5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
23737#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x40000
23738#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
23739#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x80000
23740#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
23741#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x100000
23742#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
23743#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x200000
23744#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
23745#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x400000
23746#define D3F5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
23747#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x800000
23748#define D3F5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
23749#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x1000000
23750#define D3F5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
23751#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x2000000
23752#define D3F5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
23753#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x1
23754#define D3F5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
23755#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x40
23756#define D3F5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
23757#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x80
23758#define D3F5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
23759#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x100
23760#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
23761#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x1000
23762#define D3F5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
23763#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x2000
23764#define D3F5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
23765#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x4000
23766#define D3F5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
23767#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x8000
23768#define D3F5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
23769#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x1
23770#define D3F5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
23771#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x40
23772#define D3F5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
23773#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x80
23774#define D3F5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
23775#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x100
23776#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
23777#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x1000
23778#define D3F5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
23779#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x2000
23780#define D3F5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
23781#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x4000
23782#define D3F5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
23783#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x8000
23784#define D3F5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
23785#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x1f
23786#define D3F5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
23787#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x20
23788#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5
23789#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x40
23790#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6
23791#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x80
23792#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
23793#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x100
23794#define D3F5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
23795#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x200
23796#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
23797#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x400
23798#define D3F5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
23799#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x800
23800#define D3F5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
23801#define D3F5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xffffffff
23802#define D3F5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
23803#define D3F5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xffffffff
23804#define D3F5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
23805#define D3F5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xffffffff
23806#define D3F5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
23807#define D3F5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xffffffff
23808#define D3F5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
23809#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x1
23810#define D3F5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
23811#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x2
23812#define D3F5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
23813#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x4
23814#define D3F5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
23815#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x1
23816#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
23817#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x2
23818#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
23819#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x4
23820#define D3F5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
23821#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x8
23822#define D3F5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
23823#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x10
23824#define D3F5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
23825#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x20
23826#define D3F5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
23827#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x40
23828#define D3F5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
23829#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xf8000000
23830#define D3F5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
23831#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0xffff
23832#define D3F5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
23833#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xffff0000
23834#define D3F5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
23835#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xffffffff
23836#define D3F5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
23837#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xffffffff
23838#define D3F5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
23839#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xffffffff
23840#define D3F5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
23841#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xffffffff
23842#define D3F5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
23843#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0xffff
23844#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
23845#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
23846#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
23847#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
23848#define D3F5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
23849#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x1
23850#define D3F5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
23851#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x2
23852#define D3F5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
23853#define D3F5_PCIE_LINK_CNTL3__RESERVED_MASK 0xfffffffc
23854#define D3F5_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2
23855#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0xffff
23856#define D3F5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
23857#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xffff0000
23858#define D3F5_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10
23859#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23860#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23861#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23862#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23863#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23864#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23865#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23866#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23867#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23868#define D3F5_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23869#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23870#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23871#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23872#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23873#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23874#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23875#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23876#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23877#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23878#define D3F5_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23879#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23880#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23881#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23882#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23883#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23884#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23885#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23886#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23887#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23888#define D3F5_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23889#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23890#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23891#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23892#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23893#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23894#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23895#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23896#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23897#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23898#define D3F5_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23899#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23900#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23901#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23902#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23903#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23904#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23905#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23906#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23907#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23908#define D3F5_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23909#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23910#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23911#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23912#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23913#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23914#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23915#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23916#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23917#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23918#define D3F5_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23919#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23920#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23921#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23922#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23923#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23924#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23925#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23926#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23927#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23928#define D3F5_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23929#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23930#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23931#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23932#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23933#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23934#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23935#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23936#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23937#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23938#define D3F5_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23939#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23940#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23941#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23942#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23943#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23944#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23945#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23946#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23947#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23948#define D3F5_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23949#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23950#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23951#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23952#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23953#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23954#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23955#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23956#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23957#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23958#define D3F5_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23959#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23960#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23961#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23962#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23963#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23964#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23965#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23966#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23967#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23968#define D3F5_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23969#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23970#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23971#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23972#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23973#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23974#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23975#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23976#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23977#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23978#define D3F5_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23979#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
23980#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
23981#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
23982#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
23983#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
23984#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
23985#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
23986#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
23987#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
23988#define D3F5_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
23989#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
23990#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
23991#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
23992#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
23993#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
23994#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
23995#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
23996#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
23997#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
23998#define D3F5_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
23999#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf
24000#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
24001#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x70
24002#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
24003#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf00
24004#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
24005#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000
24006#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
24007#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000
24008#define D3F5_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf
24009#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0xf0000
24010#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x10
24011#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x700000
24012#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x14
24013#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0xf000000
24014#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x18
24015#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x70000000
24016#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x1c
24017#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x80000000
24018#define D3F5_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0x1f
24019#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0xffff
24020#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
24021#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
24022#define D3F5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
24023#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
24024#define D3F5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
24025#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x1
24026#define D3F5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
24027#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x2
24028#define D3F5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
24029#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x4
24030#define D3F5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
24031#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x8
24032#define D3F5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
24033#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x10
24034#define D3F5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
24035#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x20
24036#define D3F5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
24037#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x40
24038#define D3F5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
24039#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xff00
24040#define D3F5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
24041#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x10000
24042#define D3F5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x10
24043#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x20000
24044#define D3F5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x11
24045#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x40000
24046#define D3F5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x12
24047#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x80000
24048#define D3F5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x13
24049#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x100000
24050#define D3F5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x14
24051#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x200000
24052#define D3F5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x15
24053#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x400000
24054#define D3F5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x16
24055#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0xffff
24056#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
24057#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0xf0000
24058#define D3F5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
24059#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xfff00000
24060#define D3F5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
24061#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x3f
24062#define D3F5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
24063#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000
24064#define D3F5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
24065#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x3f0000
24066#define D3F5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x10
24067#define D3F5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x80000000
24068#define D3F5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0x1f
24069#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x3f
24070#define D3F5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
24071#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xfffff000
24072#define D3F5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
24073#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xffffffff
24074#define D3F5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
24075#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xffffffff
24076#define D3F5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
24077#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xffffffff
24078#define D3F5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
24079#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xffffffff
24080#define D3F5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
24081#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xffffffff
24082#define D3F5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
24083#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xffffffff
24084#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
24085#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xffffffff
24086#define D3F5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
24087#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x3f
24088#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
24089#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xffffffc0
24090#define D3F5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
24091#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xffffffff
24092#define D3F5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
24093#define C_PCIE_INDEX__PCIE_INDEX_MASK 0xffffffff
24094#define C_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
24095#define C_PCIE_DATA__PCIE_DATA_MASK 0xffffffff
24096#define C_PCIE_DATA__PCIE_DATA__SHIFT 0x0
24097#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
24098#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
24099#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
24100#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
24101#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
24102#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
24103#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
24104#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
24105#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
24106#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
24107#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
24108#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
24109#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
24110#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
24111#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
24112#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
24113#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
24114#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
24115#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
24116#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
24117#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
24118#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
24119#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
24120#define PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
24121#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
24122#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
24123#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
24124#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
24125#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
24126#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
24127#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
24128#define PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
24129#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
24130#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
24131#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
24132#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
24133#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
24134#define PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
24135#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
24136#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
24137#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
24138#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
24139#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
24140#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
24141#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
24142#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
24143#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
24144#define PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
24145#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
24146#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
24147#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
24148#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
24149#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
24150#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
24151#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
24152#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
24153#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
24154#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
24155#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
24156#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
24157#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
24158#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
24159#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
24160#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
24161#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
24162#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
24163#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
24164#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
24165#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
24166#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
24167#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
24168#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
24169#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
24170#define PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
24171#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
24172#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
24173#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
24174#define PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
24175#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
24176#define PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
24177#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
24178#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
24179#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
24180#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
24181#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
24182#define PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
24183#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
24184#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
24185#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
24186#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
24187#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
24188#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
24189#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
24190#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
24191#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
24192#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
24193#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
24194#define PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
24195#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
24196#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
24197#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
24198#define PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
24199#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
24200#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
24201#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
24202#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
24203#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
24204#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
24205#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
24206#define PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
24207#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
24208#define PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
24209#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
24210#define PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
24211#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24212#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24213#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24214#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24215#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24216#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24217#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24218#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24219#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24220#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24221#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24222#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24223#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24224#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24225#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24226#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24227#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24228#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24229#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24230#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24231#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24232#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24233#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24234#define PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24235#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24236#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24237#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24238#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24239#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24240#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24241#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24242#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24243#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24244#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24245#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24246#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24247#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24248#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24249#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24250#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24251#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24252#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24253#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24254#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24255#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24256#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24257#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24258#define PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24259#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24260#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24261#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24262#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24263#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
24264#define PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
24265#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
24266#define PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
24267#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24268#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24269#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24270#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24271#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24272#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24273#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24274#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24275#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24276#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24277#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24278#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24279#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24280#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24281#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24282#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24283#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24284#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24285#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24286#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24287#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24288#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24289#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24290#define PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24291#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24292#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24293#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24294#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24295#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24296#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24297#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24298#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24299#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24300#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24301#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24302#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24303#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24304#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24305#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24306#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24307#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24308#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24309#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24310#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24311#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24312#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24313#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24314#define PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24315#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24316#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24317#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24318#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24319#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
24320#define PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
24321#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
24322#define PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
24323#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24324#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24325#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24326#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24327#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24328#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24329#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24330#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24331#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24332#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24333#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24334#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24335#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24336#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24337#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24338#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24339#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24340#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24341#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24342#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24343#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24344#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24345#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24346#define PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24347#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24348#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24349#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24350#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24351#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24352#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24353#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24354#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24355#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24356#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24357#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24358#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24359#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24360#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24361#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24362#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24363#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24364#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24365#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24366#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24367#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24368#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24369#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24370#define PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24371#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24372#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24373#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24374#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24375#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
24376#define PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
24377#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
24378#define PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
24379#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24380#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24381#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24382#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24383#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24384#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24385#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24386#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24387#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24388#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24389#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24390#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24391#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24392#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24393#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24394#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24395#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24396#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24397#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24398#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24399#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24400#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24401#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24402#define PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24403#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24404#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24405#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24406#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24407#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24408#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24409#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24410#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24411#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24412#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24413#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24414#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24415#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24416#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24417#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24418#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24419#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24420#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24421#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24422#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24423#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24424#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24425#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24426#define PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24427#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24428#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24429#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24430#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24431#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
24432#define PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
24433#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
24434#define PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
24435#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24436#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24437#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24438#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24439#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24440#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24441#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24442#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24443#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24444#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24445#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24446#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24447#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24448#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24449#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24450#define PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24451#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24452#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24453#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24454#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24455#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24456#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24457#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24458#define PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24459#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24460#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24461#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24462#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24463#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24464#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24465#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24466#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24467#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24468#define PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24469#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24470#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24471#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24472#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24473#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24474#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24475#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24476#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24477#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24478#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24479#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24480#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24481#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24482#define PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24483#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24484#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24485#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24486#define PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24487#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
24488#define PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
24489#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
24490#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
24491#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
24492#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
24493#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
24494#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
24495#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
24496#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
24497#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
24498#define PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
24499#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
24500#define PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
24501#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
24502#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
24503#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
24504#define PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
24505#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
24506#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
24507#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
24508#define PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
24509#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
24510#define PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
24511#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
24512#define PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
24513#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
24514#define PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
24515#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
24516#define PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
24517#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
24518#define PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
24519#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
24520#define PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
24521#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
24522#define PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
24523#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
24524#define PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
24525#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
24526#define PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
24527#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
24528#define PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
24529#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
24530#define PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
24531#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
24532#define PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
24533#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
24534#define PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
24535#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
24536#define PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
24537#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
24538#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
24539#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
24540#define PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
24541#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
24542#define PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
24543#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
24544#define PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
24545#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
24546#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
24547#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
24548#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
24549#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
24550#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
24551#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
24552#define PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
24553#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
24554#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
24555#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
24556#define PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
24557#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
24558#define PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
24559#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
24560#define PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
24561#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
24562#define PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
24563#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
24564#define PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
24565#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
24566#define PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
24567#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
24568#define PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
24569#define PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
24570#define PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
24571#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
24572#define PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
24573#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
24574#define PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
24575#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
24576#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
24577#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
24578#define PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
24579#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
24580#define PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
24581#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
24582#define PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
24583#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
24584#define PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
24585#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
24586#define PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
24587#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
24588#define PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
24589#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
24590#define PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
24591#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
24592#define PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
24593#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
24594#define PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
24595#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
24596#define PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
24597#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
24598#define PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
24599#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
24600#define PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
24601#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
24602#define PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
24603#define PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
24604#define PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
24605#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
24606#define PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
24607#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
24608#define PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
24609#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
24610#define PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
24611#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
24612#define PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
24613#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
24614#define PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
24615#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
24616#define PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
24617#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
24618#define PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
24619#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
24620#define PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
24621#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
24622#define PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
24623#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
24624#define PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
24625#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
24626#define PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
24627#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
24628#define PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
24629#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
24630#define PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
24631#define PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
24632#define PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
24633#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
24634#define PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
24635#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
24636#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
24637#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
24638#define PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
24639#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
24640#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
24641#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
24642#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
24643#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
24644#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
24645#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
24646#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
24647#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
24648#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
24649#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
24650#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
24651#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
24652#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
24653#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
24654#define PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
24655#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
24656#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
24657#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
24658#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
24659#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
24660#define PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
24661#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
24662#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
24663#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
24664#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
24665#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
24666#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
24667#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
24668#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
24669#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
24670#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
24671#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
24672#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
24673#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
24674#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
24675#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
24676#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
24677#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
24678#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
24679#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
24680#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
24681#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
24682#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
24683#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
24684#define PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
24685#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
24686#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
24687#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
24688#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
24689#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
24690#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
24691#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
24692#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
24693#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
24694#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
24695#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
24696#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
24697#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
24698#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
24699#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
24700#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
24701#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
24702#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
24703#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
24704#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
24705#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
24706#define PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
24707#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
24708#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
24709#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
24710#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
24711#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
24712#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
24713#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
24714#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
24715#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
24716#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
24717#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
24718#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
24719#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
24720#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
24721#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
24722#define PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
24723#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK 0x2
24724#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT 0x1
24725#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK 0x4
24726#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT 0x2
24727#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK 0x8
24728#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT 0x3
24729#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK 0x20
24730#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT 0x5
24731#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK 0x200
24732#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT 0x9
24733#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK 0x800
24734#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT 0xb
24735#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK 0x2000
24736#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT 0xd
24737#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK 0x200000
24738#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT 0x15
24739#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK 0x800000
24740#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT 0x17
24741#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK 0x10000000
24742#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT 0x1c
24743#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK 0x20000000
24744#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT 0x1d
24745#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK 0xc0000000
24746#define PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT 0x1e
24747#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK 0x1ff8
24748#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT 0x3
24749#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK 0x6000
24750#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT 0xd
24751#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK 0x1f8000
24752#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT 0xf
24753#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK 0x200000
24754#define PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT 0x15
24755#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK 0x2
24756#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT 0x1
24757#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK 0xc
24758#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT 0x2
24759#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK 0x10
24760#define PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT 0x4
24761#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK 0x400
24762#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT 0xa
24763#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK 0x800
24764#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT 0xb
24765#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK 0x2000
24766#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT 0xd
24767#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK 0x4000
24768#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT 0xe
24769#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x18000
24770#define PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0xf
24771#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK 0x1
24772#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT 0x0
24773#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK 0x2
24774#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT 0x1
24775#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK 0x4
24776#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT 0x2
24777#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK 0x10
24778#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT 0x4
24779#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK 0x20
24780#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT 0x5
24781#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK 0x40
24782#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT 0x6
24783#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x80
24784#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
24785#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x100
24786#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
24787#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK 0x200
24788#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT 0x9
24789#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK 0x1000
24790#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT 0xc
24791#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK 0x10000
24792#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT 0x10
24793#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK 0x20000
24794#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT 0x11
24795#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK 0x40000
24796#define PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT 0x12
24797#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK 0x4000000
24798#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT 0x1a
24799#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK 0xc0000000
24800#define PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT 0x1e
24801#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK 0x1
24802#define PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT 0x0
24803#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK 0x1
24804#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT 0x0
24805#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK 0x2
24806#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT 0x1
24807#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK 0x4
24808#define PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT 0x2
24809#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK 0x1
24810#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT 0x0
24811#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK 0x4
24812#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT 0x2
24813#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x8
24814#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x3
24815#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK 0x70
24816#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT 0x4
24817#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x80
24818#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x7
24819#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK 0x100
24820#define PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT 0x8
24821#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK 0xffff
24822#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT 0x0
24823#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK 0xffff0000
24824#define PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT 0x10
24825#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x7
24826#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x0
24827#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x38
24828#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x3
24829#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK 0x3c0
24830#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x6
24831#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK 0x3c00
24832#define PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT 0xa
24833#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK 0xf
24834#define PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT 0x0
24835#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK 0x1
24836#define PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT 0x0
24837#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24838#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24839#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24840#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24841#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24842#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24843#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24844#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24845#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24846#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24847#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24848#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24849#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24850#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24851#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24852#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24853#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24854#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24855#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24856#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24857#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24858#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24859#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24860#define PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24861#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24862#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24863#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24864#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24865#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24866#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24867#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24868#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24869#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24870#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24871#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24872#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24873#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24874#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24875#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24876#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24877#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24878#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24879#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24880#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24881#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24882#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24883#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24884#define PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24885#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24886#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24887#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24888#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24889#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK 0x1
24890#define PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT 0x0
24891#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK 0x1
24892#define PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT 0x0
24893#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24894#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24895#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24896#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24897#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24898#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24899#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24900#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24901#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24902#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24903#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24904#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24905#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24906#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24907#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24908#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24909#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24910#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24911#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24912#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24913#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24914#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24915#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24916#define PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24917#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24918#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24919#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24920#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24921#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24922#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24923#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24924#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24925#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24926#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24927#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24928#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24929#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24930#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24931#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24932#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24933#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24934#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24935#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24936#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24937#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24938#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24939#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24940#define PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24941#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24942#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24943#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
24944#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
24945#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK 0x1
24946#define PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT 0x0
24947#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK 0x1
24948#define PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT 0x0
24949#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
24950#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
24951#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
24952#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
24953#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
24954#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
24955#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
24956#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
24957#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
24958#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
24959#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
24960#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
24961#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
24962#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
24963#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
24964#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
24965#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK 0xc000
24966#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
24967#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
24968#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
24969#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
24970#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
24971#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
24972#define PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
24973#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
24974#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
24975#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
24976#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
24977#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
24978#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
24979#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
24980#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
24981#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
24982#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
24983#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
24984#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
24985#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
24986#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
24987#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
24988#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
24989#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
24990#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
24991#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
24992#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
24993#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK 0x80
24994#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
24995#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
24996#define PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
24997#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
24998#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
24999#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
25000#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
25001#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK 0x1
25002#define PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT 0x0
25003#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK 0x1
25004#define PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT 0x0
25005#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
25006#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
25007#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
25008#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
25009#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
25010#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
25011#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
25012#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
25013#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
25014#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
25015#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
25016#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
25017#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
25018#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
25019#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
25020#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
25021#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK 0xc000
25022#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
25023#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
25024#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
25025#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
25026#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
25027#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
25028#define PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
25029#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
25030#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
25031#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
25032#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
25033#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
25034#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
25035#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
25036#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
25037#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
25038#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
25039#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
25040#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
25041#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
25042#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
25043#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
25044#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
25045#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
25046#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
25047#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
25048#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
25049#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK 0x80
25050#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
25051#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
25052#define PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
25053#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
25054#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
25055#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
25056#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
25057#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK 0x1
25058#define PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT 0x0
25059#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK 0x1
25060#define PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT 0x0
25061#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x4
25062#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0x2
25063#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x40
25064#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x6
25065#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK 0x80
25066#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT 0x7
25067#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK 0x100
25068#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT 0x8
25069#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK 0x600
25070#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT 0x9
25071#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK 0x3000
25072#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT 0xc
25073#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK 0x3f0000
25074#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT 0x10
25075#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK 0x3f000000
25076#define PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT 0x18
25077#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK 0xc000
25078#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT 0xe
25079#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK 0x70000
25080#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT 0x10
25081#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK 0x380000
25082#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT 0x13
25083#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK 0x400000
25084#define PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT 0x16
25085#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK 0x20
25086#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT 0x5
25087#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x800
25088#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0xb
25089#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK 0x1000
25090#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT 0xc
25091#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK 0x2000
25092#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT 0xd
25093#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK 0x4000
25094#define PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT 0xe
25095#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK 0x1
25096#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT 0x0
25097#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK 0xe
25098#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT 0x1
25099#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK 0x10
25100#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT 0x4
25101#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK 0x20
25102#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT 0x5
25103#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK 0x40
25104#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT 0x6
25105#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK 0x80
25106#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT 0x7
25107#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK 0x100
25108#define PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT 0x8
25109#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK 0x200
25110#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT 0x9
25111#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK 0xff000000
25112#define PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT 0x18
25113#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK 0x1
25114#define PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT 0x0
25115#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK 0x1
25116#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT 0x0
25117#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK 0x2
25118#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT 0x1
25119#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK 0x4
25120#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT 0x2
25121#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK 0x8
25122#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT 0x3
25123#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK 0x10
25124#define PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT 0x4
25125#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK 0xffffff
25126#define PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT 0x0
25127#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK 0x7
25128#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT 0x0
25129#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK 0x70
25130#define PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT 0x4
25131#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK 0xffff
25132#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT 0x0
25133#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK 0xffff0000
25134#define PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT 0x10
25135#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK 0xffffffff
25136#define PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT 0x0
25137#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK 0xffffffff
25138#define PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT 0x0
25139#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK 0xffffffff
25140#define PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT 0x0
25141#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK 0xffffffff
25142#define PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT 0x0
25143#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK 0xffffffff
25144#define PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT 0x0
25145#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK 0xffffffff
25146#define PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT 0x0
25147#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK 0xffffffff
25148#define PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT 0x0
25149#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK 0xffffffff
25150#define PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT 0x0
25151#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK 0xffffffff
25152#define PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT 0x0
25153#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK 0xffffffff
25154#define PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT 0x0
25155#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK 0xffffffff
25156#define PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT 0x0
25157#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK 0xffffffff
25158#define PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT 0x0
25159#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK 0x1
25160#define PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT 0x0
25161#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK 0x1
25162#define PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT 0x0
25163#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK 0x1
25164#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT 0x0
25165#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK 0x2
25166#define PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT 0x1
25167#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK 0x2
25168#define PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT 0x1
25169#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK 0x4
25170#define PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT 0x2
25171#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK 0x7
25172#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT 0x0
25173#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK 0x70
25174#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT 0x4
25175#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK 0x80
25176#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT 0x7
25177#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK 0x100
25178#define PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT 0x8
25179#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK 0xff
25180#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT 0x0
25181#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK 0x10000
25182#define PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT 0x10
25183#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK 0x1
25184#define PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT 0x0
25185#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK 0x800
25186#define PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT 0xb
25187#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK 0x1
25188#define PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT 0x0
25189#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK 0x1
25190#define PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT 0x0
25191#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK 0x1
25192#define PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT 0x0
25193#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK 0x1
25194#define PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT 0x0
25195#define PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK 0xffffffff
25196#define PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT 0x0
25197#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK 0xff
25198#define PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT 0x0
25199#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK 0xffffffff
25200#define PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT 0x0
25201#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK 0xff
25202#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT 0x0
25203#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK 0xf0000
25204#define PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT 0x10
25205#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK 0xf00000
25206#define PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT 0x14
25207#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK 0x1f000000
25208#define PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT 0x18
25209#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK 0x1
25210#define PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT 0x0
25211#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK 0x2
25212#define PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT 0x1
25213#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK 0x4
25214#define PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT 0x2
25215#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK 0x8
25216#define PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT 0x3
25217#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK 0x10
25218#define PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT 0x4
25219#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK 0x20
25220#define PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT 0x5
25221#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK 0x40
25222#define PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT 0x6
25223#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK 0x80
25224#define PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT 0x7
25225#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK 0x300
25226#define PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT 0x8
25227#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK 0xc00
25228#define PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT 0xa
25229#define PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK 0x3000
25230#define PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT 0xc
25231#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK 0xc000
25232#define PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT 0xe
25233#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK 0x10000
25234#define PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT 0x10
25235#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK 0x20000
25236#define PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT 0x11
25237#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK 0x40000
25238#define PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT 0x12
25239#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK 0x80000
25240#define PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT 0x13
25241#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK 0x100000
25242#define PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT 0x14
25243#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK 0x200000
25244#define PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT 0x15
25245#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK 0xc00000
25246#define PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT 0x16
25247#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK 0x1000000
25248#define PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT 0x18
25249#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK 0x2000000
25250#define PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT 0x19
25251#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK 0x4000000
25252#define PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT 0x1a
25253#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK 0x8000000
25254#define PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT 0x1b
25255#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK 0x10000000
25256#define PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT 0x1c
25257#define PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK 0x60000000
25258#define PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT 0x1d
25259#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK 0x80000000
25260#define PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT 0x1f
25261#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK 0x1
25262#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT 0x0
25263#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK 0x2
25264#define PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT 0x1
25265#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK 0x4
25266#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT 0x2
25267#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK 0x8
25268#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT 0x3
25269#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK 0x30
25270#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT 0x4
25271#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK 0xc0
25272#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT 0x6
25273#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK 0x300
25274#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT 0x8
25275#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK 0xf000
25276#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT 0xc
25277#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK 0xf0000
25278#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT 0x10
25279#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK 0xf00000
25280#define PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT 0x14
25281#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK 0x1ff
25282#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT 0x0
25283#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK 0x3fe00
25284#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT 0x9
25285#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK 0x7fc0000
25286#define PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT 0x12
25287#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK 0xff
25288#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT 0x0
25289#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK 0xff00
25290#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT 0x8
25291#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK 0xff0000
25292#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT 0x10
25293#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK 0xff
25294#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT 0x0
25295#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK 0xff00
25296#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT 0x8
25297#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK 0xff0000
25298#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT 0x10
25299#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK 0xff
25300#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT 0x0
25301#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK 0xff00
25302#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT 0x8
25303#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK 0xff0000
25304#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT 0x10
25305#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK 0xff
25306#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT 0x0
25307#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK 0xff00
25308#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT 0x8
25309#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK 0xff0000
25310#define PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT 0x10
25311#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK 0x1
25312#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT 0x0
25313#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK 0x2
25314#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT 0x1
25315#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK 0x4
25316#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT 0x2
25317#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK 0x8
25318#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT 0x3
25319#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK 0xff00
25320#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT 0x8
25321#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK 0x10000
25322#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT 0x10
25323#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK 0x20000
25324#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT 0x11
25325#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK 0x40000
25326#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT 0x12
25327#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK 0x100000
25328#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT 0x14
25329#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK 0x200000
25330#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT 0x15
25331#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK 0xf0000000
25332#define PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT 0x1c
25333#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK 0x1
25334#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT 0x0
25335#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK 0x2
25336#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT 0x1
25337#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK 0x4
25338#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT 0x2
25339#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK 0x8
25340#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT 0x3
25341#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK 0x10
25342#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT 0x4
25343#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK 0xff00
25344#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT 0x8
25345#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK 0xff0000
25346#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT 0x10
25347#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK 0x1f000000
25348#define PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT 0x18
25349#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK 0x1
25350#define RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT 0x0
25351#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK 0x2
25352#define RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT 0x1
25353#define RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK 0xffff
25354#define RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT 0x0
25355#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK 0x40000000
25356#define RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT 0x1e
25357#define RFE_SOFTRST_CNTL__SoftRstReg_MASK 0x80000000
25358#define RFE_SOFTRST_CNTL__SoftRstReg__SHIFT 0x1f
25359#define RFE_IMPRST_CNTL__REG_RST_impEn_MASK 0x1
25360#define RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT 0x0
25361#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK 0x1
25362#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT 0x0
25363#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK 0x2
25364#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT 0x1
25365#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK 0x4
25366#define RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT 0x2
25367#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK 0x1
25368#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT 0x0
25369#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK 0x2
25370#define RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT 0x1
25371#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK 0x4
25372#define RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT 0x2
25373#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK 0x1
25374#define RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT 0x0
25375#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK 0x2
25376#define RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT 0x1
25377#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK 0x4
25378#define RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT 0x2
25379#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK 0x1
25380#define RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT 0x0
25381#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK 0x2
25382#define RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT 0x1
25383#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK 0x4
25384#define RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT 0x2
25385#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK 0xff
25386#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT 0x0
25387#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK 0xf00
25388#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT 0x8
25389#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK 0xff0000
25390#define RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT 0x10
25391#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK 0x1000000
25392#define RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT 0x18
25393#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK 0xff
25394#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT 0x0
25395#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK 0xf00
25396#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT 0x8
25397#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK 0xff0000
25398#define RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT 0x10
25399#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK 0x1000000
25400#define RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT 0x18
25401#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK 0xff
25402#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT 0x0
25403#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK 0xf00
25404#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT 0x8
25405#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK 0xff0000
25406#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT 0x10
25407#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK 0x1000000
25408#define RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT 0x18
25409#define RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK 0x1
25410#define RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT 0x0
25411#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK 0x1
25412#define RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT 0x0
25413#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK 0x3ff
25414#define RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT 0x0
25415#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
25416#define PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
25417#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
25418#define PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
25419#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
25420#define PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
25421#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
25422#define PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
25423#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
25424#define PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
25425#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
25426#define PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
25427#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
25428#define PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
25429#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
25430#define PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
25431#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
25432#define PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
25433#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
25434#define PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
25435#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
25436#define PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
25437#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
25438#define PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
25439#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
25440#define PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
25441#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
25442#define PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
25443#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
25444#define PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
25445#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
25446#define PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
25447#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
25448#define PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
25449#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
25450#define PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
25451#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
25452#define PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
25453#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
25454#define PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
25455#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
25456#define PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
25457#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
25458#define PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
25459#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
25460#define PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
25461#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
25462#define PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
25463#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
25464#define PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
25465#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
25466#define PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
25467#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
25468#define PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
25469#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
25470#define PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
25471#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
25472#define PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
25473#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
25474#define PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
25475#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
25476#define PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
25477#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
25478#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
25479#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
25480#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
25481#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
25482#define PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
25483#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
25484#define PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
25485#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
25486#define PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
25487#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
25488#define PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
25489#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
25490#define PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
25491#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
25492#define PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
25493#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
25494#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
25495#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
25496#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
25497#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
25498#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
25499#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
25500#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
25501#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
25502#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
25503#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
25504#define PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
25505#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
25506#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
25507#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
25508#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
25509#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
25510#define PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
25511#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
25512#define PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
25513#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
25514#define PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
25515#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
25516#define PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
25517#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
25518#define PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
25519#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
25520#define PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
25521#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
25522#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
25523#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
25524#define PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
25525#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
25526#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
25527#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
25528#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
25529#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
25530#define PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
25531#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
25532#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
25533#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
25534#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
25535#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
25536#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
25537#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
25538#define PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
25539#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
25540#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
25541#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
25542#define PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
25543#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
25544#define PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
25545#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
25546#define PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
25547#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
25548#define PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
25549#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
25550#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
25551#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
25552#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
25553#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
25554#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
25555#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
25556#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
25557#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
25558#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
25559#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
25560#define PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
25561#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
25562#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
25563#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
25564#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
25565#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
25566#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
25567#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
25568#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
25569#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
25570#define PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
25571#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
25572#define PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
25573#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
25574#define PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
25575#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
25576#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
25577#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
25578#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
25579#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
25580#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
25581#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
25582#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
25583#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
25584#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
25585#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
25586#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
25587#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
25588#define PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
25589#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
25590#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
25591#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
25592#define PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
25593#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
25594#define PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
25595#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
25596#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
25597#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
25598#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
25599#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
25600#define PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
25601#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
25602#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
25603#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
25604#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
25605#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
25606#define PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
25607#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
25608#define PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
25609#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
25610#define PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
25611#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
25612#define PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
25613#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
25614#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
25615#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
25616#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
25617#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
25618#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
25619#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
25620#define PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
25621#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
25622#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
25623#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
25624#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
25625#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
25626#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
25627#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
25628#define PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
25629#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
25630#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
25631#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
25632#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
25633#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
25634#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
25635#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
25636#define PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
25637#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
25638#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
25639#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
25640#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
25641#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
25642#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
25643#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
25644#define PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
25645#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
25646#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
25647#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
25648#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
25649#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
25650#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
25651#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
25652#define PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
25653#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
25654#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
25655#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
25656#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
25657#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
25658#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
25659#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
25660#define PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
25661#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
25662#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
25663#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
25664#define PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
25665#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
25666#define PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
25667#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
25668#define PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
25669#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
25670#define PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
25671#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
25672#define PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
25673#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
25674#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
25675#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
25676#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
25677#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
25678#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
25679#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
25680#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
25681#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
25682#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
25683#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
25684#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
25685#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
25686#define PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
25687#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
25688#define PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
25689#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
25690#define PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
25691#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
25692#define PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
25693#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
25694#define PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
25695#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
25696#define PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
25697#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
25698#define PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
25699#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
25700#define PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
25701#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
25702#define PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
25703#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
25704#define PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
25705#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
25706#define PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
25707#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
25708#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
25709#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
25710#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
25711#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
25712#define PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
25713#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
25714#define PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
25715#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
25716#define PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
25717#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
25718#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
25719#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
25720#define PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
25721#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
25722#define PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
25723#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
25724#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
25725#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
25726#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
25727#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
25728#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
25729#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
25730#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
25731#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
25732#define PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
25733#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
25734#define PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
25735#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
25736#define PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
25737#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
25738#define PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
25739#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
25740#define PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
25741#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
25742#define PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
25743#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
25744#define PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
25745#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
25746#define PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
25747#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
25748#define PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
25749#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
25750#define PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
25751#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
25752#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
25753#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
25754#define PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
25755#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
25756#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
25757#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
25758#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
25759#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
25760#define PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
25761#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
25762#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
25763#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
25764#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
25765#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
25766#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
25767#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
25768#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
25769#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
25770#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
25771#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
25772#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
25773#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
25774#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
25775#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
25776#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
25777#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
25778#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
25779#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
25780#define PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
25781#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
25782#define PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
25783#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
25784#define PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
25785#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
25786#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
25787#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
25788#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
25789#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
25790#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
25791#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
25792#define PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
25793#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
25794#define PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
25795#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
25796#define PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
25797#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
25798#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
25799#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
25800#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
25801#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
25802#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
25803#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
25804#define PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
25805#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
25806#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
25807#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
25808#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
25809#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
25810#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
25811#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
25812#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
25813#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
25814#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
25815#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
25816#define PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
25817#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
25818#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
25819#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
25820#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
25821#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
25822#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
25823#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
25824#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
25825#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
25826#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
25827#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
25828#define PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
25829#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
25830#define PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
25831#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
25832#define PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
25833#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
25834#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
25835#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
25836#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
25837#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
25838#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
25839#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
25840#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
25841#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
25842#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
25843#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
25844#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
25845#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
25846#define PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
25847#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
25848#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
25849#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
25850#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
25851#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
25852#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
25853#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
25854#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
25855#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
25856#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
25857#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
25858#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
25859#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
25860#define PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
25861#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
25862#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
25863#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
25864#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
25865#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
25866#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
25867#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
25868#define PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
25869#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
25870#define PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
25871#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
25872#define PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
25873#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
25874#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
25875#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
25876#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
25877#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
25878#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
25879#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
25880#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
25881#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
25882#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
25883#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
25884#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
25885#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
25886#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
25887#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
25888#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
25889#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
25890#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
25891#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
25892#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
25893#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
25894#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
25895#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
25896#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
25897#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
25898#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
25899#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
25900#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
25901#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
25902#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
25903#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
25904#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
25905#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
25906#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
25907#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
25908#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
25909#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
25910#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
25911#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
25912#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
25913#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
25914#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
25915#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
25916#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
25917#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
25918#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
25919#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
25920#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
25921#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
25922#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
25923#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
25924#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
25925#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
25926#define PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
25927#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
25928#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
25929#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
25930#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
25931#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
25932#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
25933#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
25934#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
25935#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
25936#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
25937#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
25938#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
25939#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
25940#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
25941#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
25942#define PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
25943#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
25944#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
25945#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
25946#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
25947#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
25948#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
25949#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
25950#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
25951#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
25952#define PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
25953#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
25954#define PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
25955#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
25956#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
25957#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
25958#define PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
25959#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
25960#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
25961#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
25962#define PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
25963#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
25964#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
25965#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
25966#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
25967#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
25968#define PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
25969#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
25970#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
25971#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
25972#define PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
25973#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
25974#define PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
25975#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
25976#define PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
25977#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
25978#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
25979#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
25980#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
25981#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
25982#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
25983#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
25984#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
25985#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
25986#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
25987#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
25988#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
25989#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
25990#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
25991#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
25992#define PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
25993#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
25994#define PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
25995#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
25996#define PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
25997#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
25998#define PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
25999#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
26000#define PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
26001#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
26002#define PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
26003#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
26004#define PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
26005#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
26006#define PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
26007#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
26008#define PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
26009#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
26010#define PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
26011#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
26012#define PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
26013#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
26014#define PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
26015#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
26016#define PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
26017#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
26018#define PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
26019#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
26020#define PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
26021#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
26022#define PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
26023#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
26024#define PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
26025#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
26026#define PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
26027#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
26028#define PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
26029#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
26030#define PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
26031#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
26032#define PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
26033#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
26034#define PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
26035#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
26036#define PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
26037#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
26038#define PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
26039#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
26040#define PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
26041#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
26042#define PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
26043#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
26044#define PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
26045#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
26046#define PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
26047#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
26048#define PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
26049#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
26050#define PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
26051#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
26052#define PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
26053#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
26054#define PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
26055#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
26056#define PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
26057#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
26058#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
26059#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
26060#define PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
26061#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
26062#define PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
26063#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
26064#define PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
26065#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
26066#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
26067#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
26068#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
26069#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
26070#define PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
26071#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
26072#define PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
26073#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
26074#define PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
26075#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
26076#define PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
26077#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
26078#define PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
26079#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
26080#define PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
26081#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
26082#define PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
26083#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
26084#define PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
26085#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
26086#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
26087#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
26088#define PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
26089#define PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
26090#define PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
26091#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
26092#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
26093#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
26094#define PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
26095#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
26096#define PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
26097#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
26098#define PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
26099#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
26100#define PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
26101#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
26102#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
26103#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
26104#define PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
26105#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
26106#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
26107#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
26108#define PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
26109#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
26110#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
26111#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
26112#define PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
26113#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
26114#define PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
26115#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
26116#define PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
26117#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
26118#define PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
26119#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
26120#define PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
26121#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
26122#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
26123#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
26124#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
26125#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
26126#define PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
26127#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
26128#define PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
26129#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
26130#define PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
26131#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
26132#define PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
26133#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
26134#define PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
26135#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
26136#define PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
26137#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
26138#define PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
26139#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
26140#define PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
26141#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
26142#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
26143#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
26144#define PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
26145#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
26146#define PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
26147#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
26148#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
26149#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
26150#define PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
26151#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
26152#define PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
26153#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
26154#define PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
26155#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
26156#define PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
26157#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
26158#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
26159#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
26160#define PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
26161#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
26162#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
26163#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
26164#define PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
26165#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
26166#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
26167#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
26168#define PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
26169#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
26170#define PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
26171#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
26172#define PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
26173#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
26174#define PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
26175#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
26176#define PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
26177#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
26178#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
26179#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
26180#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
26181#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
26182#define PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
26183#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
26184#define PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
26185#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
26186#define PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
26187#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
26188#define PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
26189#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
26190#define PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
26191#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
26192#define PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
26193#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
26194#define PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
26195#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
26196#define PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
26197#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
26198#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
26199#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
26200#define PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
26201#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
26202#define PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
26203#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
26204#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
26205#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
26206#define PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
26207#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
26208#define PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
26209#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
26210#define PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
26211#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
26212#define PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
26213#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
26214#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
26215#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
26216#define PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
26217#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
26218#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
26219#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
26220#define PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
26221#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
26222#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
26223#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
26224#define PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
26225#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
26226#define PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
26227#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
26228#define PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
26229#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
26230#define PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
26231#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
26232#define PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
26233#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
26234#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
26235#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
26236#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
26237#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
26238#define PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
26239#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
26240#define PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
26241#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
26242#define PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
26243#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
26244#define PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
26245#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
26246#define PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
26247#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
26248#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
26249#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
26250#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
26251#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
26252#define PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
26253#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
26254#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
26255#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
26256#define PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
26257#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
26258#define PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
26259#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
26260#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
26261#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
26262#define PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
26263#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
26264#define PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
26265#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
26266#define PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
26267#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
26268#define PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
26269#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
26270#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
26271#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
26272#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
26273#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
26274#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
26275#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
26276#define PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
26277#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
26278#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
26279#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
26280#define PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
26281#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
26282#define PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
26283#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
26284#define PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
26285#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
26286#define PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
26287#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
26288#define PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
26289#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
26290#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
26291#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
26292#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
26293#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
26294#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
26295#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
26296#define PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
26297#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
26298#define PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
26299#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
26300#define PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
26301#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
26302#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
26303#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
26304#define PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
26305#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
26306#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
26307#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
26308#define PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
26309#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
26310#define PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
26311#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
26312#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
26313#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
26314#define PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
26315#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
26316#define PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
26317#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
26318#define PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
26319#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
26320#define PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
26321#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
26322#define PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
26323#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
26324#define PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
26325#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
26326#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
26327#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
26328#define PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
26329#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
26330#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
26331#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
26332#define PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
26333#define PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
26334#define PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
26335#define PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
26336#define PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
26337#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
26338#define PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
26339#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
26340#define PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
26341#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
26342#define PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
26343#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
26344#define PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
26345#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
26346#define PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
26347#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
26348#define PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
26349#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
26350#define PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
26351#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
26352#define PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
26353#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
26354#define PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
26355#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
26356#define PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
26357#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
26358#define PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
26359#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
26360#define PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
26361#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
26362#define PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
26363#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
26364#define PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
26365#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
26366#define PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
26367#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
26368#define PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
26369#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
26370#define PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
26371#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
26372#define PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
26373#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
26374#define PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
26375#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
26376#define PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
26377#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
26378#define PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
26379#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
26380#define PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
26381#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
26382#define PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
26383#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
26384#define PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
26385#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
26386#define PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
26387#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
26388#define PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
26389#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
26390#define PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
26391#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
26392#define PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
26393#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
26394#define PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
26395#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
26396#define PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
26397#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
26398#define PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
26399#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
26400#define PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
26401#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
26402#define PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
26403#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
26404#define PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
26405#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
26406#define PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
26407#define PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
26408#define PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
26409#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
26410#define PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
26411#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
26412#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
26413#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
26414#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
26415#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
26416#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
26417#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
26418#define PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
26419#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
26420#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
26421#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
26422#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
26423#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
26424#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
26425#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
26426#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
26427#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
26428#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
26429#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
26430#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
26431#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
26432#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
26433#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
26434#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
26435#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
26436#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
26437#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
26438#define PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
26439#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
26440#define PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
26441#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
26442#define PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
26443#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
26444#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
26445#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
26446#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
26447#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
26448#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
26449#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
26450#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
26451#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
26452#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
26453#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
26454#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
26455#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
26456#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
26457#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
26458#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
26459#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
26460#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
26461#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
26462#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
26463#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
26464#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
26465#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
26466#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
26467#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
26468#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
26469#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
26470#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
26471#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
26472#define PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
26473#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
26474#define PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
26475#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
26476#define PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
26477#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
26478#define PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
26479#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
26480#define PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
26481#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
26482#define PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
26483#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
26484#define PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
26485#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
26486#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
26487#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
26488#define PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
26489#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
26490#define PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
26491#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
26492#define PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
26493#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
26494#define PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
26495#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
26496#define PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
26497#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
26498#define PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
26499#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
26500#define PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
26501#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
26502#define PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
26503#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
26504#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
26505#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
26506#define PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
26507#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
26508#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
26509#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
26510#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
26511#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
26512#define PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
26513#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
26514#define PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
26515#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
26516#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
26517#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
26518#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
26519#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
26520#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
26521#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
26522#define PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
26523#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
26524#define PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
26525#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
26526#define PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
26527#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
26528#define PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
26529#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
26530#define PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
26531#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
26532#define PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
26533#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
26534#define PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
26535#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
26536#define PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
26537#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
26538#define PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
26539#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
26540#define PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
26541#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
26542#define PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
26543#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
26544#define PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
26545#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
26546#define PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
26547#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK 0xffffffff
26548#define PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
26549#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xffffffff
26550#define PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
26551#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK 0x1
26552#define PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
26553#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK 0x2
26554#define PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
26555#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK 0x4
26556#define PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
26557#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK 0x8
26558#define PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
26559#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK 0x10
26560#define PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
26561#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK 0x20
26562#define PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
26563#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK 0x40
26564#define PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
26565#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK 0x80
26566#define PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
26567#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK 0x100
26568#define PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
26569#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK 0x200
26570#define PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
26571#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK 0x400
26572#define PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
26573#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK 0x800
26574#define PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
26575#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
26576#define PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
26577#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
26578#define PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
26579#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
26580#define PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
26581#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
26582#define PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
26583#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xffffffff
26584#define PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
26585#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xffffffff
26586#define PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
26587#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x1
26588#define PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
26589#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0xe
26590#define PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
26591#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x80
26592#define PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
26593#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x100
26594#define PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
26595#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x200
26596#define PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
26597#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x1c00
26598#define PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
26599#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x8000
26600#define PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
26601#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x10000
26602#define PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
26603#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x20000
26604#define PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
26605#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x40000
26606#define PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
26607#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x80000
26608#define PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
26609#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x100000
26610#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
26611#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x200000
26612#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
26613#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x400000
26614#define PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
26615#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x800000
26616#define PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
26617#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK 0x3f000000
26618#define PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT 0x18
26619#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000
26620#define PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
26621#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000
26622#define PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
26623#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0xf
26624#define PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
26625#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x10000
26626#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
26627#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0xe0000
26628#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
26629#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x100000
26630#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
26631#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0xe00000
26632#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
26633#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x1000000
26634#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
26635#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x6000000
26636#define PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
26637#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK 0xff
26638#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT 0x0
26639#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK 0x100
26640#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT 0x8
26641#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK 0xffff0000
26642#define PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT 0x10
26643#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x1
26644#define PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
26645#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x3e
26646#define PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
26647#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x7c0
26648#define PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
26649#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x800
26650#define PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
26651#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x1000
26652#define PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
26653#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x2000
26654#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
26655#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x4000
26656#define PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
26657#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000
26658#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
26659#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x20000
26660#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
26661#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x40000
26662#define PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
26663#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x80000
26664#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
26665#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x100000
26666#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
26667#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x200000
26668#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
26669#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x400000
26670#define PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
26671#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x800000
26672#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
26673#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1f000000
26674#define PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
26675#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000
26676#define PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
26677#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000
26678#define PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
26679#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000
26680#define PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
26681#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x1
26682#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
26683#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x2
26684#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
26685#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x4
26686#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
26687#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x8
26688#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
26689#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x10
26690#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
26691#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x20
26692#define PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
26693#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x100
26694#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
26695#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0xe00
26696#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
26697#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x1000
26698#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
26699#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x2000
26700#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
26701#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x4000
26702#define PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
26703#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x3ff0000
26704#define PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
26705#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000
26706#define PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
26707#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x3
26708#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
26709#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0xc
26710#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
26711#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x30
26712#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
26713#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0xc0
26714#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
26715#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x300
26716#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
26717#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0xc00
26718#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
26719#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x3000
26720#define PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
26721#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x4
26722#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
26723#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK 0x8
26724#define PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT 0x3
26725#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x10
26726#define PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
26727#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0xc0
26728#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
26729#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x100
26730#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
26731#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x200
26732#define PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
26733#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x400
26734#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
26735#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x800
26736#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
26737#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x1000
26738#define PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
26739#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x40
26740#define PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
26741#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x80
26742#define PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
26743#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x1000
26744#define PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
26745#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x3f
26746#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
26747#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x3f00
26748#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
26749#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x3f0000
26750#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
26751#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3f000000
26752#define PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
26753#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x3f
26754#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
26755#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x3f00
26756#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
26757#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x3f0000
26758#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
26759#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3f000000
26760#define PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
26761#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x3f
26762#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
26763#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x3f00
26764#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
26765#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x3f0000
26766#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
26767#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3f000000
26768#define PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
26769#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x3f
26770#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
26771#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x3f00
26772#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
26773#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x3f0000
26774#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
26775#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3f000000
26776#define PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
26777#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x3f
26778#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
26779#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x3f00
26780#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
26781#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x3f0000
26782#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
26783#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3f000000
26784#define PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
26785#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x3f
26786#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
26787#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x3f00
26788#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
26789#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x3f0000
26790#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
26791#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3f000000
26792#define PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
26793#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x1
26794#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
26795#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x2
26796#define PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
26797#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x1c
26798#define PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
26799#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
26800#define PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
26801#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0xffff
26802#define PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
26803#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xffff0000
26804#define PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
26805#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x1
26806#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
26807#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x2
26808#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
26809#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x4
26810#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
26811#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x8
26812#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
26813#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x10
26814#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
26815#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x20
26816#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
26817#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x40
26818#define PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
26819#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xffffffff
26820#define PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
26821#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xffffffff
26822#define PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
26823#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xffffffff
26824#define PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
26825#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xffffffff
26826#define PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
26827#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xffffffff
26828#define PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
26829#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xffffffff
26830#define PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
26831#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xffffffff
26832#define PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
26833#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xffffffff
26834#define PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
26835#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x1ffff
26836#define PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
26837#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xffffffff
26838#define PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
26839#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x1
26840#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
26841#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x2
26842#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
26843#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x4
26844#define PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
26845#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK 0x1
26846#define PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT 0x0
26847#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK 0x1
26848#define PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
26849#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x2
26850#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
26851#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK 0x4
26852#define PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT 0x2
26853#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK 0x8
26854#define PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT 0x3
26855#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x10
26856#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
26857#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x20
26858#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
26859#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x40
26860#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
26861#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x80
26862#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
26863#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x100
26864#define PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
26865#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x1000
26866#define PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
26867#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x2000
26868#define PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
26869#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0xc000
26870#define PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
26871#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x10000
26872#define PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
26873#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0xffff
26874#define PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
26875#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xffff0000
26876#define PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
26877#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0xffff
26878#define PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
26879#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0xff
26880#define PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
26881#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xffff0000
26882#define PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
26883#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0xff
26884#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
26885#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0xff00
26886#define PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
26887#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x1
26888#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
26889#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x2
26890#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
26891#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x4
26892#define PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
26893#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK 0xff
26894#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT 0x0
26895#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK 0xff00
26896#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT 0x8
26897#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK 0xff0000
26898#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT 0x10
26899#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK 0xff000000
26900#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT 0x18
26901#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK 0xffffffff
26902#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT 0x0
26903#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK 0xffffffff
26904#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT 0x0
26905#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK 0xff
26906#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT 0x0
26907#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK 0xff00
26908#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT 0x8
26909#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK 0xff0000
26910#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT 0x10
26911#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK 0xff000000
26912#define PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT 0x18
26913#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK 0xffffffff
26914#define PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT 0x0
26915#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK 0xffffffff
26916#define PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT 0x0
26917#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK 0xff
26918#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT 0x0
26919#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK 0xff00
26920#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT 0x8
26921#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK 0xff0000
26922#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT 0x10
26923#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK 0xff000000
26924#define PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT 0x18
26925#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK 0xffffffff
26926#define PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT 0x0
26927#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK 0xffffffff
26928#define PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT 0x0
26929#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK 0xff
26930#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT 0x0
26931#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK 0xff00
26932#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT 0x8
26933#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK 0xff0000
26934#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT 0x10
26935#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK 0xff000000
26936#define PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT 0x18
26937#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK 0xffffffff
26938#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT 0x0
26939#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK 0xffffffff
26940#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT 0x0
26941#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK 0xff
26942#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT 0x0
26943#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK 0xff00
26944#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT 0x8
26945#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK 0xff0000
26946#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT 0x10
26947#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK 0xff000000
26948#define PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT 0x18
26949#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK 0xffffffff
26950#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT 0x0
26951#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK 0xffffffff
26952#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT 0x0
26953#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK 0xff
26954#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT 0x0
26955#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK 0xff00
26956#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT 0x8
26957#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK 0xff0000
26958#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT 0x10
26959#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK 0xff000000
26960#define PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT 0x18
26961#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK 0xffffffff
26962#define PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT 0x0
26963#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK 0xffffffff
26964#define PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT 0x0
26965#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK 0xf
26966#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT 0x0
26967#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK 0xf0
26968#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT 0x4
26969#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK 0xf00
26970#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT 0x8
26971#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK 0xf000
26972#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT 0xc
26973#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
26974#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
26975#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
26976#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
26977#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0xf000000
26978#define PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x18
26979#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK 0xf
26980#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT 0x0
26981#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK 0xf0
26982#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT 0x4
26983#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK 0xf00
26984#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT 0x8
26985#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK 0xf000
26986#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT 0xc
26987#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK 0xf0000
26988#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT 0x10
26989#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK 0xf00000
26990#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT 0x14
26991#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0xf000000
26992#define PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0x18
26993#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0xff
26994#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
26995#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0xff00
26996#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
26997#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0xff0000
26998#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
26999#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xff000000
27000#define PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
27001#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xffffffff
27002#define PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
27003#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xffffffff
27004#define PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
27005#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x1
27006#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
27007#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x2
27008#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
27009#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x4
27010#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
27011#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x8
27012#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
27013#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x10
27014#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
27015#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x20
27016#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
27017#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x40
27018#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
27019#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x80
27020#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
27021#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x100
27022#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
27023#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x200
27024#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
27025#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x400
27026#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
27027#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x800
27028#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
27029#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x1000
27030#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
27031#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x2000
27032#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
27033#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK 0x4000
27034#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT 0xe
27035#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x8000
27036#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
27037#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x10000
27038#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
27039#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x20000
27040#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
27041#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x40000
27042#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
27043#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x80000
27044#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
27045#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x100000
27046#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
27047#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0xe00000
27048#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
27049#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x7000000
27050#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
27051#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x8000000
27052#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
27053#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000
27054#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
27055#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK 0x20000000
27056#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT 0x1d
27057#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000
27058#define PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
27059#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x10
27060#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
27061#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x1000000
27062#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
27063#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK 0x2000000
27064#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT 0x19
27065#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x4000000
27066#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
27067#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000
27068#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
27069#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000
27070#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
27071#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK 0x40000000
27072#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT 0x1e
27073#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK 0x80000000
27074#define PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT 0x1f
27075#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x1
27076#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
27077#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x2
27078#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
27079#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x4
27080#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
27081#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x8
27082#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
27083#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x10
27084#define PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
27085#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x1
27086#define PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
27087#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000
27088#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
27089#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000
27090#define PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
27091#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x7f
27092#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
27093#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK 0x80
27094#define PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT 0x7
27095#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK 0xffff
27096#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
27097#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK 0xf0000
27098#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT 0x10
27099#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x1000000
27100#define PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
27101#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0xffff
27102#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
27103#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xffff0000
27104#define PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
27105#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0xffff
27106#define PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
27107#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0xffff
27108#define PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
27109#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK 0x1
27110#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
27111#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0xe
27112#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
27113#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x10
27114#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
27115#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x20
27116#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
27117#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0xc0
27118#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
27119#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x1f00
27120#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
27121#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0xc000
27122#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
27123#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xffff0000
27124#define PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
27125#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3fffffff
27126#define PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
27127#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xffffffff
27128#define PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
27129#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0xff
27130#define PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
27131#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xffffffff
27132#define PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
27133#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xffffffff
27134#define PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
27135#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xffffffff
27136#define PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
27137#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xffffffff
27138#define PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
27139#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xffffffff
27140#define PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
27141#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xffffffff
27142#define PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
27143#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xffffffff
27144#define PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
27145#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xffffffff
27146#define PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
27147#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xffffffff
27148#define PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
27149#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xffffffff
27150#define PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
27151#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xffffffff
27152#define PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
27153#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xffffffff
27154#define PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
27155#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xffffffff
27156#define PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
27157#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xffffffff
27158#define PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
27159#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xffffffff
27160#define PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
27161#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xffffffff
27162#define PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
27163#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x1
27164#define PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
27165#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x2
27166#define PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
27167#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x10000
27168#define PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
27169#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x20000
27170#define PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
27171#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x1
27172#define PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
27173#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x2
27174#define PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
27175#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x1c
27176#define PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
27177#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x100
27178#define PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
27179#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x200
27180#define PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
27181#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x400
27182#define PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
27183#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x1000
27184#define PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
27185#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK 0x2000
27186#define PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT 0xd
27187#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK 0x4000
27188#define PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT 0xe
27189#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK 0x10000
27190#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT 0x10
27191#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK 0x20000
27192#define PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT 0x11
27193#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK 0x8000
27194#define PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT 0xf
27195#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x10000
27196#define PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x10
27197#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x20000
27198#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x11
27199#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x40000
27200#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x12
27201#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x80000
27202#define PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x13
27203#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x100000
27204#define PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x14
27205#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x200000
27206#define PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x15
27207#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x400000
27208#define PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x16
27209#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK 0x1
27210#define PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x0
27211#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK 0x2
27212#define PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT 0x1
27213#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK 0x4
27214#define PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT 0x2
27215#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK 0x8
27216#define PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT 0x3
27217#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK 0x10
27218#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT 0x4
27219#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK 0x20
27220#define PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT 0x5
27221#define PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK 0x40
27222#define PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT 0x6
27223#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK 0x100
27224#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT 0x8
27225#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK 0x200
27226#define PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT 0x9
27227#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK 0x2000
27228#define PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT 0xd
27229#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK 0x4000
27230#define PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT 0xe
27231#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK 0x8000
27232#define PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT 0xf
27233#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK 0x10000
27234#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT 0x10
27235#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK 0x20000
27236#define PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT 0x11
27237#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK 0x100000
27238#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT 0x14
27239#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK 0x200000
27240#define PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT 0x15
27241#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK 0x1000000
27242#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT 0x18
27243#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK 0x2000000
27244#define PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT 0x19
27245#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x10000000
27246#define PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1c
27247#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK 0x20000000
27248#define PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT 0x1d
27249#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK 0x8000
27250#define PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT 0xf
27251#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x10000
27252#define PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x10
27253#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x20000
27254#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x11
27255#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x40000
27256#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x12
27257#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x80000
27258#define PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x13
27259#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x100000
27260#define PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x14
27261#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x200000
27262#define PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x15
27263#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x400000
27264#define PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x16
27265#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x1
27266#define PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x0
27267#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x2
27268#define PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x1
27269#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK 0x4
27270#define PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT 0x2
27271#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK 0x8
27272#define PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT 0x3
27273#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK 0x10
27274#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT 0x4
27275#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK 0x20
27276#define PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT 0x5
27277#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK 0x40
27278#define PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT 0x6
27279#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK 0x100
27280#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT 0x8
27281#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK 0x200
27282#define PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT 0x9
27283#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x2000
27284#define PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0xd
27285#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x4000
27286#define PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0xe
27287#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x8000
27288#define PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0xf
27289#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK 0x10000
27290#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT 0x10
27291#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK 0x20000
27292#define PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT 0x11
27293#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK 0x100000
27294#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT 0x14
27295#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK 0x200000
27296#define PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT 0x15
27297#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x1000000
27298#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x18
27299#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK 0x2000000
27300#define PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT 0x19
27301#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x10000000
27302#define PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1c
27303#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK 0x20000000
27304#define PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT 0x1d
27305#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK 0x8000
27306#define PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT 0xf
27307#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x10000
27308#define PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x10
27309#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x20000
27310#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x11
27311#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x40000
27312#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x12
27313#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x80000
27314#define PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x13
27315#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x100000
27316#define PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x14
27317#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x200000
27318#define PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x15
27319#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x400000
27320#define PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x16
27321#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x1
27322#define PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x0
27323#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x2
27324#define PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x1
27325#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK 0x4
27326#define PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT 0x2
27327#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK 0x8
27328#define PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT 0x3
27329#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK 0x10
27330#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT 0x4
27331#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK 0x20
27332#define PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT 0x5
27333#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK 0x40
27334#define PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT 0x6
27335#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK 0x100
27336#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT 0x8
27337#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK 0x200
27338#define PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT 0x9
27339#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x2000
27340#define PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0xd
27341#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x4000
27342#define PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0xe
27343#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x8000
27344#define PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0xf
27345#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK 0x10000
27346#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT 0x10
27347#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK 0x20000
27348#define PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT 0x11
27349#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK 0x100000
27350#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT 0x14
27351#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK 0x200000
27352#define PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT 0x15
27353#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x1000000
27354#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x18
27355#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK 0x2000000
27356#define PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT 0x19
27357#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x10000000
27358#define PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1c
27359#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK 0x20000000
27360#define PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT 0x1d
27361#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK 0x4000
27362#define PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT 0xe
27363#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x10000
27364#define PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x10
27365#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x20000
27366#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x11
27367#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x40000
27368#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x12
27369#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x80000
27370#define PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x13
27371#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x100000
27372#define PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x14
27373#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x200000
27374#define PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x15
27375#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x400000
27376#define PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x16
27377#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x1
27378#define PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x0
27379#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x2
27380#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x1
27381#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK 0x4
27382#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT 0x2
27383#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK 0x8
27384#define PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT 0x3
27385#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK 0x10
27386#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT 0x4
27387#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK 0x20
27388#define PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT 0x5
27389#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK 0x40
27390#define PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT 0x6
27391#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK 0x100
27392#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT 0x8
27393#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK 0x200
27394#define PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT 0x9
27395#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x2000
27396#define PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0xd
27397#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x4000
27398#define PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0xe
27399#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x8000
27400#define PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0xf
27401#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK 0x10000
27402#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT 0x10
27403#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK 0x20000
27404#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT 0x11
27405#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK 0x100000
27406#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT 0x14
27407#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK 0x200000
27408#define PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT 0x15
27409#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x1000000
27410#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x18
27411#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK 0x2000000
27412#define PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT 0x19
27413#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x10000000
27414#define PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1c
27415#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK 0x20000000
27416#define PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT 0x1d
27417#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK 0x1
27418#define PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT 0x0
27419#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK 0x100
27420#define PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT 0x8
27421#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x1
27422#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
27423#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x2
27424#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
27425#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK 0x4
27426#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT 0x2
27427#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK 0x8
27428#define PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT 0x3
27429#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK 0x10
27430#define PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT 0x4
27431#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x20
27432#define PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
27433#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x40
27434#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
27435#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x80
27436#define PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
27437#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x100
27438#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
27439#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x200
27440#define PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
27441#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x400
27442#define PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xa
27443#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK 0x800
27444#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT 0xb
27445#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x1000
27446#define PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xc
27447#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x2000
27448#define PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xd
27449#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x4000
27450#define PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0xe
27451#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x8000
27452#define PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0xf
27453#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK 0x10000
27454#define PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT 0x10
27455#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0xe0000
27456#define PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x11
27457#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK 0x100000
27458#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT 0x14
27459#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK 0x200000
27460#define PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT 0x15
27461#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x400000
27462#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
27463#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x800000
27464#define PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
27465#define PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK 0xff000000
27466#define PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT 0x18
27467#define PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK 0x1e
27468#define PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT 0x1
27469#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK 0x20
27470#define PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT 0x5
27471#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK 0xc0
27472#define PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT 0x6
27473#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK 0x700
27474#define PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT 0x8
27475#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK 0xff
27476#define PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT 0x0
27477#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK 0xff00
27478#define PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT 0x8
27479#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK 0xff0000
27480#define PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT 0x10
27481#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK 0xff000000
27482#define PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT 0x18
27483#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK 0xff
27484#define PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT 0x0
27485#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK 0xff00
27486#define PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT 0x8
27487#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK 0xff0000
27488#define PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT 0x10
27489#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK 0xff000000
27490#define PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT 0x18
27491#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK 0xff
27492#define PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT 0x0
27493#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK 0xff00
27494#define PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT 0x8
27495#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK 0xff0000
27496#define PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT 0x10
27497#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK 0xff000000
27498#define PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT 0x18
27499#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK 0xff
27500#define PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT 0x0
27501#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK 0xff00
27502#define PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT 0x8
27503#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK 0xff0000
27504#define PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT 0x10
27505#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK 0xff000000
27506#define PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT 0x18
27507#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK 0xff
27508#define PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT 0x0
27509#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK 0xff00
27510#define PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT 0x8
27511#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK 0xff0000
27512#define PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT 0x10
27513#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK 0xff000000
27514#define PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT 0x18
27515#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK 0xff
27516#define PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT 0x0
27517#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK 0xff00
27518#define PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT 0x8
27519#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK 0xff0000
27520#define PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT 0x10
27521#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK 0xff000000
27522#define PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT 0x18
27523#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK 0xff
27524#define PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT 0x0
27525#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK 0xff00
27526#define PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT 0x8
27527#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK 0xff0000
27528#define PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT 0x10
27529#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK 0xff000000
27530#define PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT 0x18
27531#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK 0xff
27532#define PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT 0x0
27533#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK 0xff00
27534#define PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT 0x8
27535#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK 0xff0000
27536#define PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT 0x10
27537#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK 0xff000000
27538#define PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT 0x18
27539#define PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK 0xffff
27540#define PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT 0x0
27541#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK 0xffff
27542#define PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT 0x0
27543#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK 0x10000000
27544#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT 0x1c
27545#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK 0x20000000
27546#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT 0x1d
27547#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK 0x40000000
27548#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT 0x1e
27549#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK 0x80000000
27550#define PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT 0x1f
27551#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK 0x7
27552#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT 0x0
27553#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK 0x38
27554#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT 0x3
27555#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK 0xc0
27556#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT 0x6
27557#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK 0x700
27558#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT 0x8
27559#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK 0x3800
27560#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT 0xb
27561#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK 0xc000
27562#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT 0xe
27563#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK 0x70000
27564#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT 0x10
27565#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK 0x380000
27566#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT 0x13
27567#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK 0xc00000
27568#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT 0x16
27569#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK 0x7000000
27570#define PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT 0x18
27571#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK 0x38000000
27572#define PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT 0x1b
27573#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK 0xc0000000
27574#define PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT 0x1e
27575#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK 0x1
27576#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT 0x0
27577#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK 0x2
27578#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT 0x1
27579#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK 0x1c
27580#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT 0x2
27581#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK 0x20
27582#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT 0x5
27583#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK 0x40
27584#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT 0x6
27585#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK 0x80
27586#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT 0x7
27587#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK 0x100
27588#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT 0x8
27589#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK 0x200
27590#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT 0x9
27591#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK 0x400
27592#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT 0xa
27593#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK 0x3800
27594#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT 0xb
27595#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK 0x4000
27596#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT 0xe
27597#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK 0x8000
27598#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT 0xf
27599#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK 0x10000
27600#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT 0x10
27601#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK 0x20000
27602#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT 0x11
27603#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK 0x40000
27604#define PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT 0x12
27605#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK 0x80000
27606#define PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT 0x13
27607#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK 0x700000
27608#define PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT 0x14
27609#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK 0x800000
27610#define PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT 0x17
27611#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK 0x1000000
27612#define PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT 0x18
27613#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK 0x2000000
27614#define PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT 0x19
27615#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK 0x4000000
27616#define PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT 0x1a
27617#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK 0x18000000
27618#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT 0x1b
27619#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK 0x60000000
27620#define PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT 0x1d
27621#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK 0x1
27622#define PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT 0x0
27623#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK 0x2
27624#define PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT 0x1
27625#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK 0x1c
27626#define PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT 0x2
27627#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK 0x20
27628#define PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT 0x5
27629#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK 0x40
27630#define PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT 0x6
27631#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK 0x80
27632#define PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT 0x7
27633#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK 0x100
27634#define PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT 0x8
27635#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK 0x600
27636#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT 0x9
27637#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK 0x1800
27638#define PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT 0xb
27639#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK 0x7e000
27640#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT 0xd
27641#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK 0x1f80000
27642#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT 0x13
27643#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK 0x7e000000
27644#define PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT 0x19
27645#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK 0x3f
27646#define PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT 0x0
27647#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK 0xfc0
27648#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT 0x6
27649#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK 0x3f000
27650#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT 0xc
27651#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK 0xfc0000
27652#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT 0x12
27653#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK 0x3f000000
27654#define PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT 0x18
27655#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK 0x7
27656#define PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT 0x0
27657#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK 0x38
27658#define PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT 0x3
27659#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK 0x1c0
27660#define PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT 0x6
27661#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK 0xe00
27662#define PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT 0x9
27663#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK 0xf000
27664#define PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT 0xc
27665#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK 0xf0000
27666#define PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT 0x10
27667#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK 0xf00000
27668#define PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT 0x14
27669#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK 0xf000000
27670#define PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT 0x18
27671#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK 0x10000000
27672#define PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT 0x1c
27673#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK 0x20000000
27674#define PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT 0x1d
27675#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK 0x40000000
27676#define PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT 0x1e
27677#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK 0x80000000
27678#define PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT 0x1f
27679#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
27680#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
27681#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
27682#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
27683#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
27684#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
27685#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
27686#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
27687#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
27688#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
27689#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
27690#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
27691#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
27692#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
27693#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
27694#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
27695#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
27696#define PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
27697#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
27698#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
27699#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
27700#define PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
27701#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
27702#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
27703#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
27704#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
27705#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
27706#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
27707#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
27708#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
27709#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
27710#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
27711#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
27712#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
27713#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
27714#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
27715#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
27716#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
27717#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
27718#define PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
27719#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
27720#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
27721#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
27722#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
27723#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
27724#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
27725#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
27726#define PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
27727#define PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
27728#define PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
27729#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
27730#define PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
27731#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
27732#define PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
27733#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
27734#define PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
27735#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
27736#define PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
27737#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
27738#define PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
27739#define PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
27740#define PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
27741#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
27742#define PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
27743#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
27744#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
27745#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
27746#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
27747#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
27748#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
27749#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
27750#define PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
27751#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
27752#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
27753#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
27754#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
27755#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
27756#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
27757#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
27758#define PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
27759#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
27760#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
27761#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
27762#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
27763#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
27764#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
27765#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
27766#define PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
27767#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
27768#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
27769#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
27770#define PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
27771#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
27772#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
27773#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
27774#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
27775#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
27776#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
27777#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
27778#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
27779#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
27780#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
27781#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
27782#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
27783#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
27784#define PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
27785#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
27786#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
27787#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
27788#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
27789#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
27790#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
27791#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
27792#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
27793#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
27794#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
27795#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
27796#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
27797#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
27798#define PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
27799#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
27800#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
27801#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
27802#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
27803#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
27804#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
27805#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
27806#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
27807#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
27808#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
27809#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
27810#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
27811#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
27812#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
27813#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
27814#define PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
27815#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
27816#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
27817#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
27818#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
27819#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
27820#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
27821#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
27822#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
27823#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
27824#define PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
27825#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
27826#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
27827#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
27828#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
27829#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
27830#define PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
27831#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
27832#define PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
27833#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
27834#define PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
27835#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
27836#define PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
27837#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
27838#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
27839#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
27840#define PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
27841#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
27842#define PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
27843#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
27844#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
27845#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
27846#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
27847#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
27848#define PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
27849#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
27850#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
27851#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
27852#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
27853#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
27854#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
27855#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
27856#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
27857#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
27858#define PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
27859#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
27860#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
27861#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
27862#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
27863#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
27864#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
27865#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
27866#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
27867#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
27868#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
27869#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
27870#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
27871#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
27872#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
27873#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
27874#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
27875#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
27876#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
27877#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
27878#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
27879#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
27880#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
27881#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
27882#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
27883#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
27884#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
27885#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
27886#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
27887#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
27888#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
27889#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
27890#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
27891#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
27892#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
27893#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
27894#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
27895#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
27896#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
27897#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
27898#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
27899#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
27900#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
27901#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
27902#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
27903#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
27904#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
27905#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
27906#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
27907#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
27908#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
27909#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
27910#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
27911#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
27912#define PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
27913#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
27914#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
27915#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
27916#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
27917#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
27918#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
27919#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
27920#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
27921#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
27922#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
27923#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
27924#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
27925#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
27926#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
27927#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
27928#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
27929#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
27930#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
27931#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
27932#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
27933#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
27934#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
27935#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
27936#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
27937#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
27938#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
27939#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
27940#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
27941#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
27942#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
27943#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
27944#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
27945#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
27946#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
27947#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
27948#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
27949#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
27950#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
27951#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
27952#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
27953#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
27954#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
27955#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
27956#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
27957#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
27958#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
27959#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
27960#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
27961#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
27962#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
27963#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
27964#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
27965#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
27966#define PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
27967#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
27968#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
27969#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
27970#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
27971#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
27972#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
27973#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
27974#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
27975#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
27976#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
27977#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
27978#define PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
27979#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
27980#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
27981#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
27982#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
27983#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
27984#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
27985#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
27986#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
27987#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
27988#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
27989#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
27990#define PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
27991#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
27992#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
27993#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
27994#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
27995#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
27996#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
27997#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
27998#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
27999#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
28000#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28001#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
28002#define PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
28003#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
28004#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
28005#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
28006#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
28007#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
28008#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
28009#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
28010#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
28011#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
28012#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28013#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
28014#define PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
28015#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
28016#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
28017#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
28018#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
28019#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
28020#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
28021#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
28022#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
28023#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
28024#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28025#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
28026#define PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
28027#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
28028#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
28029#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
28030#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
28031#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
28032#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
28033#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
28034#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
28035#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
28036#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28037#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
28038#define PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
28039#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
28040#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
28041#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
28042#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
28043#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
28044#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
28045#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
28046#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
28047#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
28048#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28049#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
28050#define PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
28051#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
28052#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
28053#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
28054#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
28055#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
28056#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
28057#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
28058#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
28059#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
28060#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28061#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
28062#define PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
28063#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
28064#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
28065#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
28066#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
28067#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
28068#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
28069#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
28070#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
28071#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
28072#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
28073#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
28074#define PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
28075#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
28076#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
28077#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
28078#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
28079#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
28080#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
28081#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
28082#define PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
28083#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
28084#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
28085#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
28086#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
28087#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
28088#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
28089#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
28090#define PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
28091#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
28092#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
28093#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
28094#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
28095#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
28096#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
28097#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
28098#define PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
28099#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
28100#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
28101#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
28102#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
28103#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
28104#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
28105#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
28106#define PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
28107#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
28108#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
28109#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
28110#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
28111#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
28112#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
28113#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
28114#define PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
28115#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
28116#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
28117#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
28118#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
28119#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
28120#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
28121#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
28122#define PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
28123#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
28124#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
28125#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
28126#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
28127#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
28128#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
28129#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
28130#define PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
28131#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
28132#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
28133#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
28134#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
28135#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
28136#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
28137#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
28138#define PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
28139#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
28140#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
28141#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
28142#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
28143#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
28144#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
28145#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
28146#define PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
28147#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
28148#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
28149#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
28150#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
28151#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
28152#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
28153#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
28154#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
28155#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
28156#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
28157#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
28158#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
28159#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
28160#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
28161#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
28162#define PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
28163#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
28164#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
28165#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
28166#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
28167#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
28168#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
28169#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
28170#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
28171#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
28172#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
28173#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
28174#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
28175#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
28176#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
28177#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
28178#define PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
28179#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
28180#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
28181#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
28182#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
28183#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
28184#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
28185#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
28186#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
28187#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
28188#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
28189#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
28190#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
28191#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
28192#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
28193#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
28194#define PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
28195#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
28196#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
28197#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
28198#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
28199#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
28200#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
28201#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
28202#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
28203#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
28204#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
28205#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
28206#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
28207#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
28208#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
28209#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
28210#define PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
28211#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
28212#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
28213#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
28214#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
28215#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
28216#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
28217#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
28218#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
28219#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
28220#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
28221#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
28222#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
28223#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
28224#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
28225#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
28226#define PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
28227#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
28228#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
28229#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
28230#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
28231#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
28232#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
28233#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
28234#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
28235#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
28236#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
28237#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
28238#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
28239#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
28240#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
28241#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
28242#define PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
28243#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
28244#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
28245#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
28246#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
28247#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
28248#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
28249#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
28250#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
28251#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
28252#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
28253#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
28254#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
28255#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
28256#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
28257#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
28258#define PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
28259#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
28260#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
28261#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
28262#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
28263#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
28264#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
28265#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
28266#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
28267#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
28268#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
28269#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
28270#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
28271#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
28272#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
28273#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
28274#define PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
28275#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
28276#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
28277#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
28278#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
28279#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
28280#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
28281#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
28282#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
28283#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
28284#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
28285#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
28286#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
28287#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
28288#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
28289#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
28290#define PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
28291#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
28292#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
28293#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
28294#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
28295#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
28296#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
28297#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
28298#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
28299#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
28300#define PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
28301#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
28302#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
28303#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
28304#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
28305#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
28306#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
28307#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
28308#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
28309#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
28310#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
28311#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
28312#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
28313#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
28314#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
28315#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
28316#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
28317#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
28318#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
28319#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
28320#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
28321#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
28322#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
28323#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
28324#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
28325#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
28326#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
28327#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
28328#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
28329#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
28330#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
28331#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
28332#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
28333#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
28334#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
28335#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
28336#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
28337#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
28338#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
28339#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
28340#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
28341#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
28342#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
28343#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
28344#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
28345#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
28346#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
28347#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
28348#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
28349#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
28350#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
28351#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
28352#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
28353#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
28354#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
28355#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
28356#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
28357#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
28358#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
28359#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
28360#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
28361#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
28362#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
28363#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
28364#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
28365#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
28366#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
28367#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
28368#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
28369#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
28370#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
28371#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
28372#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
28373#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
28374#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
28375#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
28376#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
28377#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
28378#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
28379#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
28380#define PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
28381#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
28382#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
28383#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
28384#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
28385#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
28386#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
28387#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28388#define PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28389#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
28390#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
28391#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
28392#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
28393#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
28394#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
28395#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28396#define PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28397#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
28398#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
28399#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
28400#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
28401#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
28402#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
28403#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28404#define PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28405#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
28406#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
28407#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
28408#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
28409#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
28410#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
28411#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28412#define PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28413#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
28414#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
28415#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
28416#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
28417#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
28418#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
28419#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28420#define PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28421#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
28422#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
28423#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
28424#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
28425#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
28426#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
28427#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28428#define PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28429#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
28430#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
28431#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
28432#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
28433#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
28434#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
28435#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28436#define PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28437#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
28438#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
28439#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
28440#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
28441#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
28442#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
28443#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28444#define PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28445#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
28446#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
28447#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
28448#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
28449#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
28450#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
28451#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
28452#define PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
28453#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
28454#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
28455#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
28456#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
28457#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
28458#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
28459#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
28460#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
28461#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
28462#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
28463#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
28464#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
28465#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
28466#define PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
28467#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
28468#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
28469#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
28470#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
28471#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
28472#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
28473#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
28474#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
28475#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
28476#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
28477#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
28478#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
28479#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
28480#define PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
28481#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
28482#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
28483#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
28484#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
28485#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
28486#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
28487#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
28488#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
28489#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
28490#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
28491#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
28492#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
28493#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
28494#define PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
28495#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
28496#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
28497#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
28498#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
28499#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
28500#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
28501#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
28502#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
28503#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
28504#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
28505#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
28506#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
28507#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
28508#define PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
28509#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
28510#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
28511#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
28512#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
28513#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
28514#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
28515#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
28516#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
28517#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
28518#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
28519#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
28520#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
28521#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
28522#define PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
28523#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
28524#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
28525#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
28526#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
28527#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
28528#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
28529#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
28530#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
28531#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
28532#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
28533#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
28534#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
28535#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
28536#define PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
28537#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
28538#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
28539#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
28540#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
28541#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
28542#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
28543#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
28544#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
28545#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
28546#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
28547#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
28548#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
28549#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
28550#define PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
28551#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
28552#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
28553#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
28554#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
28555#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
28556#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
28557#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
28558#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
28559#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
28560#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
28561#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
28562#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
28563#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
28564#define PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
28565#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
28566#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
28567#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
28568#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
28569#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
28570#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
28571#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
28572#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
28573#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
28574#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
28575#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
28576#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
28577#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
28578#define PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
28579#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28580#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28581#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28582#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28583#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28584#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28585#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28586#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28587#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28588#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28589#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28590#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28591#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28592#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28593#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28594#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28595#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28596#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28597#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28598#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28599#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28600#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28601#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28602#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28603#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28604#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28605#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28606#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28607#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28608#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28609#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28610#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28611#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28612#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28613#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28614#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28615#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28616#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28617#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28618#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28619#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28620#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28621#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28622#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28623#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28624#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28625#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28626#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28627#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28628#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28629#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28630#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28631#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28632#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28633#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28634#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28635#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28636#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28637#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28638#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28639#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28640#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28641#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28642#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28643#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28644#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28645#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28646#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28647#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28648#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28649#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28650#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28651#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28652#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28653#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28654#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28655#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28656#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28657#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28658#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28659#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28660#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28661#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28662#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28663#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28664#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28665#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28666#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28667#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28668#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28669#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28670#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28671#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28672#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28673#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28674#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28675#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28676#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28677#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28678#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28679#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28680#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28681#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28682#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28683#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28684#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28685#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28686#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28687#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28688#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28689#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28690#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28691#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28692#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28693#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28694#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28695#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28696#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28697#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28698#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28699#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28700#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28701#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28702#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28703#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28704#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28705#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28706#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28707#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
28708#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
28709#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
28710#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
28711#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
28712#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
28713#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
28714#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
28715#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
28716#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
28717#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
28718#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
28719#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
28720#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
28721#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
28722#define PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
28723#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
28724#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
28725#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
28726#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
28727#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
28728#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
28729#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28730#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28731#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28732#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28733#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28734#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28735#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
28736#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
28737#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
28738#define PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
28739#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
28740#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
28741#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
28742#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
28743#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
28744#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
28745#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28746#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28747#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28748#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28749#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28750#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28751#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
28752#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
28753#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
28754#define PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
28755#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
28756#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
28757#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
28758#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
28759#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
28760#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
28761#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28762#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28763#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28764#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28765#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28766#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28767#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
28768#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
28769#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
28770#define PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
28771#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
28772#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
28773#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
28774#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
28775#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
28776#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
28777#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28778#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28779#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28780#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28781#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28782#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28783#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
28784#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
28785#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
28786#define PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
28787#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
28788#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
28789#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
28790#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
28791#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
28792#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
28793#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28794#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28795#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28796#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28797#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28798#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28799#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
28800#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
28801#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
28802#define PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
28803#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
28804#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
28805#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
28806#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
28807#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
28808#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
28809#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28810#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28811#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28812#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28813#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28814#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28815#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
28816#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
28817#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
28818#define PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
28819#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
28820#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
28821#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
28822#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
28823#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
28824#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
28825#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28826#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28827#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28828#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28829#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28830#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28831#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
28832#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
28833#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
28834#define PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
28835#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
28836#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
28837#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
28838#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
28839#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
28840#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
28841#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28842#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28843#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28844#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28845#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28846#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28847#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
28848#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
28849#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
28850#define PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
28851#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
28852#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
28853#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
28854#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
28855#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
28856#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
28857#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
28858#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
28859#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
28860#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
28861#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
28862#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
28863#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
28864#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
28865#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
28866#define PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
28867#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
28868#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
28869#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
28870#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
28871#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
28872#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
28873#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
28874#define PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
28875#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
28876#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
28877#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
28878#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
28879#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
28880#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
28881#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
28882#define PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
28883#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
28884#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
28885#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
28886#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
28887#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
28888#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
28889#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
28890#define PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
28891#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
28892#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
28893#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
28894#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
28895#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
28896#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
28897#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
28898#define PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
28899#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
28900#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
28901#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
28902#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
28903#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
28904#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
28905#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
28906#define PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
28907#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
28908#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
28909#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
28910#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
28911#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
28912#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
28913#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
28914#define PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
28915#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
28916#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
28917#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
28918#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
28919#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
28920#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
28921#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
28922#define PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
28923#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
28924#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
28925#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
28926#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
28927#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
28928#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
28929#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
28930#define PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
28931#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
28932#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
28933#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
28934#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
28935#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
28936#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
28937#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
28938#define PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
28939#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
28940#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
28941#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
28942#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
28943#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
28944#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
28945#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
28946#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
28947#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
28948#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
28949#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
28950#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
28951#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
28952#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
28953#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
28954#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
28955#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
28956#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
28957#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
28958#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
28959#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
28960#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
28961#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
28962#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
28963#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
28964#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
28965#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
28966#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
28967#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
28968#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
28969#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
28970#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
28971#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
28972#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
28973#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
28974#define PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
28975#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
28976#define PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
28977#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
28978#define PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
28979#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
28980#define PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
28981#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
28982#define PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
28983#define PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
28984#define PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
28985#define PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
28986#define PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
28987#define PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
28988#define PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
28989#define PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
28990#define PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
28991#define PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
28992#define PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
28993#define PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
28994#define PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
28995#define PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
28996#define PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
28997#define PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
28998#define PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
28999#define PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
29000#define PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
29001#define PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
29002#define PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
29003#define PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
29004#define PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
29005#define PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
29006#define PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
29007#define PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
29008#define PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
29009#define PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
29010#define PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
29011#define PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
29012#define PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
29013#define PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
29014#define PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
29015#define PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
29016#define PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
29017#define PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
29018#define PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
29019#define PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
29020#define PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
29021#define PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
29022#define PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
29023#define PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
29024#define PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
29025#define PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
29026#define PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
29027#define PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
29028#define PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
29029#define PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
29030#define PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
29031#define PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
29032#define PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
29033#define PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
29034#define PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
29035#define PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
29036#define PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
29037#define PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
29038#define PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
29039#define PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
29040#define PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
29041#define PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
29042#define PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
29043#define PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
29044#define PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
29045#define PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
29046#define PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
29047#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
29048#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
29049#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
29050#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
29051#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
29052#define PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
29053#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
29054#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
29055#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
29056#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
29057#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
29058#define PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
29059#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
29060#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
29061#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
29062#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
29063#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
29064#define PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
29065#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
29066#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
29067#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
29068#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
29069#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
29070#define PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
29071#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
29072#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
29073#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
29074#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
29075#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
29076#define PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
29077#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
29078#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
29079#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
29080#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
29081#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
29082#define PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
29083#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
29084#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
29085#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
29086#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
29087#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
29088#define PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
29089#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
29090#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
29091#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
29092#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
29093#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
29094#define PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
29095#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
29096#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
29097#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
29098#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
29099#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
29100#define PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
29101#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
29102#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
29103#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
29104#define PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
29105#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
29106#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
29107#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
29108#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
29109#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
29110#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
29111#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
29112#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
29113#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
29114#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
29115#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
29116#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
29117#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
29118#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
29119#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
29120#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
29121#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
29122#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
29123#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
29124#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
29125#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
29126#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
29127#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
29128#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
29129#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
29130#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
29131#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
29132#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
29133#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
29134#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
29135#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
29136#define PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
29137#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
29138#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
29139#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
29140#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
29141#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
29142#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
29143#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
29144#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
29145#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
29146#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
29147#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
29148#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
29149#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
29150#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
29151#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
29152#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
29153#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
29154#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
29155#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
29156#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
29157#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
29158#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
29159#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
29160#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
29161#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
29162#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
29163#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
29164#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
29165#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
29166#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
29167#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
29168#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
29169#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
29170#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
29171#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
29172#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
29173#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
29174#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
29175#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
29176#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
29177#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
29178#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
29179#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
29180#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
29181#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
29182#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
29183#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
29184#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
29185#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
29186#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
29187#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
29188#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
29189#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
29190#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
29191#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
29192#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
29193#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
29194#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
29195#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
29196#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
29197#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
29198#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
29199#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
29200#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
29201#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
29202#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
29203#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
29204#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
29205#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
29206#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
29207#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
29208#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
29209#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
29210#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
29211#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
29212#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
29213#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
29214#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
29215#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
29216#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
29217#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
29218#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
29219#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
29220#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
29221#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
29222#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
29223#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
29224#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
29225#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
29226#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
29227#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
29228#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
29229#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
29230#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
29231#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
29232#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
29233#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
29234#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
29235#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
29236#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
29237#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
29238#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
29239#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
29240#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
29241#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
29242#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
29243#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
29244#define PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
29245#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
29246#define PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
29247#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
29248#define PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
29249#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
29250#define PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
29251#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
29252#define PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
29253#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
29254#define PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
29255#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
29256#define PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
29257#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
29258#define PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
29259#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
29260#define PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
29261#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
29262#define PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
29263#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
29264#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
29265#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
29266#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
29267#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
29268#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
29269#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
29270#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
29271#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
29272#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
29273#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
29274#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
29275#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
29276#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
29277#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
29278#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
29279#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
29280#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
29281#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
29282#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
29283#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
29284#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
29285#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
29286#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
29287#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
29288#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
29289#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
29290#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
29291#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
29292#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
29293#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
29294#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
29295#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
29296#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
29297#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
29298#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
29299#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
29300#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
29301#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
29302#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
29303#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
29304#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
29305#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
29306#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
29307#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
29308#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
29309#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
29310#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
29311#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
29312#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
29313#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
29314#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
29315#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
29316#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
29317#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
29318#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
29319#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
29320#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
29321#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
29322#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
29323#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
29324#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
29325#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
29326#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
29327#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
29328#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
29329#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
29330#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
29331#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
29332#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
29333#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
29334#define PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
29335#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
29336#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
29337#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
29338#define PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
29339#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
29340#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
29341#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
29342#define PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
29343#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
29344#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
29345#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
29346#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
29347#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
29348#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
29349#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
29350#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
29351#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
29352#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
29353#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
29354#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
29355#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
29356#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
29357#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
29358#define PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
29359#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
29360#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
29361#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
29362#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
29363#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
29364#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
29365#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
29366#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
29367#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
29368#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
29369#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
29370#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
29371#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
29372#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
29373#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
29374#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
29375#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
29376#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
29377#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
29378#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
29379#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
29380#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
29381#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
29382#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
29383#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
29384#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
29385#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
29386#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
29387#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
29388#define PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
29389#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
29390#define PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
29391#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
29392#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
29393#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
29394#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
29395#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
29396#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
29397#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
29398#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
29399#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
29400#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
29401#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
29402#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
29403#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
29404#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
29405#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
29406#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
29407#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
29408#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
29409#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
29410#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
29411#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
29412#define PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
29413#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
29414#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
29415#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
29416#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
29417#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
29418#define PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
29419#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
29420#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
29421#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
29422#define PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
29423#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
29424#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
29425#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
29426#define PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
29427#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
29428#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
29429#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
29430#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
29431#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
29432#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
29433#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
29434#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
29435#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
29436#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
29437#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
29438#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
29439#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
29440#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
29441#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
29442#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
29443#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
29444#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
29445#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
29446#define PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
29447#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
29448#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
29449#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
29450#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
29451#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
29452#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
29453#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
29454#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
29455#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
29456#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
29457#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
29458#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
29459#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
29460#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
29461#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
29462#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
29463#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
29464#define PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
29465#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
29466#define PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
29467#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
29468#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
29469#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
29470#define PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
29471#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
29472#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
29473#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
29474#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
29475#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
29476#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
29477#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
29478#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
29479#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
29480#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
29481#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
29482#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
29483#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
29484#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
29485#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
29486#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
29487#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
29488#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
29489#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
29490#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
29491#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
29492#define PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
29493#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK 0x1
29494#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT 0x0
29495#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK 0x6
29496#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT 0x1
29497#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK 0x8
29498#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT 0x3
29499#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK 0xf0
29500#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT 0x4
29501#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK 0x100
29502#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT 0x8
29503#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK 0x600
29504#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT 0x9
29505#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK 0x1800
29506#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT 0xb
29507#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK 0xc0000
29508#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT 0x12
29509#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK 0xfff00000
29510#define PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT 0x14
29511#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK 0x1
29512#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT 0x0
29513#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK 0xfffffffe
29514#define PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT 0x1
29515#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK 0x1
29516#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT 0x0
29517#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK 0xe
29518#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT 0x1
29519#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK 0x3f0
29520#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT 0x4
29521#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK 0xfc00
29522#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT 0xa
29523#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK 0xf0000
29524#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT 0x10
29525#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK 0xf00000
29526#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT 0x14
29527#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK 0xf000000
29528#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT 0x18
29529#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK 0x10000000
29530#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT 0x1c
29531#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK 0xe0000000
29532#define PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT 0x1d
29533#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK 0x1
29534#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT 0x0
29535#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK 0x2
29536#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT 0x1
29537#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK 0x4
29538#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT 0x2
29539#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK 0x3f0
29540#define PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT 0x4
29541#define PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK 0x1
29542#define PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT 0x0
29543#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK 0x7fe
29544#define PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT 0x1
29545#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK 0x800
29546#define PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT 0xb
29547#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK 0x2000
29548#define PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT 0xd
29549#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK 0x8000
29550#define PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT 0xf
29551#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK 0x7e0000
29552#define PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT 0x11
29553#define PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK 0xf000000
29554#define PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT 0x18
29555#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK 0x20000000
29556#define PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT 0x1d
29557#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK 0xff
29558#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT 0x0
29559#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK 0xff00
29560#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT 0x8
29561#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK 0xff0000
29562#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT 0x10
29563#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK 0xff000000
29564#define PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT 0x18
29565#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK 0xff
29566#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT 0x0
29567#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK 0xff00
29568#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT 0x8
29569#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK 0xff0000
29570#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT 0x10
29571#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK 0xff000000
29572#define PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT 0x18
29573#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK 0xff
29574#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT 0x0
29575#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK 0xff00
29576#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT 0x8
29577#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK 0xff0000
29578#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT 0x10
29579#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK 0xff000000
29580#define PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT 0x18
29581#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK 0xf
29582#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT 0x0
29583#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK 0x3f0
29584#define PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT 0x4
29585#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK 0x7
29586#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT 0x0
29587#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK 0xf0
29588#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT 0x4
29589#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK 0x1e00
29590#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT 0x9
29591#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK 0x3c000
29592#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT 0xe
29593#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK 0x780000
29594#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT 0x13
29595#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK 0x1e000000
29596#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT 0x19
29597#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK 0xe0000000
29598#define PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT 0x1d
29599#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK 0x3
29600#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT 0x0
29601#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK 0x78
29602#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT 0x3
29603#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK 0xf00
29604#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT 0x8
29605#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK 0x1e000
29606#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT 0xd
29607#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK 0x3c0000
29608#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT 0x12
29609#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK 0x3800000
29610#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT 0x17
29611#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK 0x38000000
29612#define PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT 0x1b
29613#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK 0x1f
29614#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT 0x0
29615#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK 0x7c0
29616#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT 0x6
29617#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK 0xe000
29618#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT 0xd
29619#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK 0xe0000
29620#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT 0x11
29621#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK 0xfc00000
29622#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT 0x16
29623#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK 0x3f
29624#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT 0x0
29625#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK 0xf00
29626#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT 0x8
29627#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK 0x1e000
29628#define PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT 0xd
29629#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK 0x1ff
29630#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT 0x0
29631#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK 0xff800
29632#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT 0xb
29633#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK 0x7fc00000
29634#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT 0x16
29635#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK 0x3f
29636#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT 0x0
29637#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK 0x1f80
29638#define PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT 0x7
29639#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK 0x7
29640#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT 0x0
29641#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK 0x1c0
29642#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT 0x6
29643#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK 0x3fffc00
29644#define PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT 0xa
29645#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK 0x20
29646#define PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT 0x5
29647#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK 0xc0
29648#define PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT 0x6
29649#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK 0x300
29650#define PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT 0x8
29651#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK 0x1f
29652#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT 0x0
29653#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK 0x40
29654#define PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT 0x6
29655#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK 0x70
29656#define PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT 0x4
29657#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK 0x1
29658#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT 0x0
29659#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK 0x780
29660#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT 0x7
29661#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK 0x7e000
29662#define PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT 0xd
29663#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK 0x1
29664#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT 0x0
29665#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK 0x3c
29666#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT 0x2
29667#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK 0x780
29668#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT 0x7
29669#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK 0x1ff000
29670#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT 0xc
29671#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK 0xc00000
29672#define PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT 0x16
29673#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK 0x7
29674#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT 0x0
29675#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK 0x18
29676#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT 0x3
29677#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK 0x20
29678#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT 0x5
29679#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK 0x7
29680#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT 0x0
29681#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK 0x18
29682#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT 0x3
29683#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK 0x20
29684#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT 0x5
29685#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK 0x7
29686#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT 0x0
29687#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK 0x18
29688#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT 0x3
29689#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK 0x20
29690#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT 0x5
29691#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK 0x7
29692#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT 0x0
29693#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK 0x18
29694#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT 0x3
29695#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK 0x20
29696#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT 0x5
29697#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK 0x7
29698#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT 0x0
29699#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK 0x18
29700#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT 0x3
29701#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK 0x20
29702#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT 0x5
29703#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK 0x7
29704#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT 0x0
29705#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK 0x18
29706#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT 0x3
29707#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK 0x20
29708#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT 0x5
29709#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK 0x7
29710#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT 0x0
29711#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK 0x18
29712#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT 0x3
29713#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK 0x20
29714#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT 0x5
29715#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK 0x7
29716#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT 0x0
29717#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK 0x18
29718#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT 0x3
29719#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK 0x20
29720#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT 0x5
29721#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK 0x7
29722#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT 0x0
29723#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK 0x18
29724#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT 0x3
29725#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK 0x20
29726#define PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT 0x5
29727#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK 0x1
29728#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT 0x0
29729#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK 0x6
29730#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT 0x1
29731#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK 0x8
29732#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT 0x3
29733#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK 0x1
29734#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT 0x0
29735#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK 0x6
29736#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT 0x1
29737#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK 0x8
29738#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT 0x3
29739#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK 0x1
29740#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT 0x0
29741#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK 0x6
29742#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT 0x1
29743#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK 0x8
29744#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT 0x3
29745#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK 0x1
29746#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT 0x0
29747#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK 0x6
29748#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT 0x1
29749#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK 0x8
29750#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT 0x3
29751#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK 0x1
29752#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT 0x0
29753#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK 0x6
29754#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT 0x1
29755#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK 0x8
29756#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT 0x3
29757#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK 0x1
29758#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT 0x0
29759#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK 0x6
29760#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT 0x1
29761#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK 0x8
29762#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT 0x3
29763#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK 0x1
29764#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT 0x0
29765#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK 0x6
29766#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT 0x1
29767#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK 0x8
29768#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT 0x3
29769#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK 0x1
29770#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT 0x0
29771#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK 0x6
29772#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT 0x1
29773#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK 0x8
29774#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT 0x3
29775#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK 0x1
29776#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT 0x0
29777#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK 0x6
29778#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT 0x1
29779#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK 0x8
29780#define PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT 0x3
29781#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK 0x1
29782#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT 0x0
29783#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK 0x1fe
29784#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT 0x1
29785#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK 0x1800
29786#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT 0xb
29787#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK 0x2000
29788#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT 0xd
29789#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK 0x4000
29790#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29791#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK 0x8000
29792#define PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT 0xf
29793#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK 0x1
29794#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT 0x0
29795#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK 0x1fe
29796#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT 0x1
29797#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK 0x1800
29798#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT 0xb
29799#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK 0x2000
29800#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT 0xd
29801#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK 0x4000
29802#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29803#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK 0x8000
29804#define PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT 0xf
29805#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK 0x1
29806#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT 0x0
29807#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK 0x1fe
29808#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT 0x1
29809#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK 0x1800
29810#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT 0xb
29811#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK 0x2000
29812#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT 0xd
29813#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK 0x4000
29814#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29815#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK 0x8000
29816#define PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT 0xf
29817#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK 0x1
29818#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT 0x0
29819#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK 0x1fe
29820#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT 0x1
29821#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK 0x1800
29822#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT 0xb
29823#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK 0x2000
29824#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT 0xd
29825#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK 0x4000
29826#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29827#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK 0x8000
29828#define PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT 0xf
29829#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK 0x1
29830#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT 0x0
29831#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK 0x1fe
29832#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT 0x1
29833#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK 0x1800
29834#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT 0xb
29835#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK 0x2000
29836#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT 0xd
29837#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK 0x4000
29838#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29839#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK 0x8000
29840#define PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT 0xf
29841#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK 0x1
29842#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT 0x0
29843#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK 0x1fe
29844#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT 0x1
29845#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK 0x1800
29846#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT 0xb
29847#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK 0x2000
29848#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT 0xd
29849#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK 0x4000
29850#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29851#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK 0x8000
29852#define PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT 0xf
29853#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK 0x1
29854#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT 0x0
29855#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK 0x1fe
29856#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT 0x1
29857#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK 0x1800
29858#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT 0xb
29859#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK 0x2000
29860#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT 0xd
29861#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK 0x4000
29862#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29863#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK 0x8000
29864#define PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT 0xf
29865#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK 0x1
29866#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT 0x0
29867#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK 0x1fe
29868#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT 0x1
29869#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK 0x1800
29870#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT 0xb
29871#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK 0x2000
29872#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT 0xd
29873#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK 0x4000
29874#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29875#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK 0x8000
29876#define PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT 0xf
29877#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK 0x1
29878#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT 0x0
29879#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK 0x1fe
29880#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT 0x1
29881#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK 0x1800
29882#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT 0xb
29883#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK 0x2000
29884#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT 0xd
29885#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK 0x4000
29886#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT 0xe
29887#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK 0x8000
29888#define PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT 0xf
29889#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK 0x7
29890#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT 0x0
29891#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK 0x10
29892#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT 0x4
29893#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK 0x20
29894#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT 0x5
29895#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK 0x80
29896#define PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT 0x7
29897#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK 0x7
29898#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT 0x0
29899#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK 0x10
29900#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT 0x4
29901#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK 0x20
29902#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT 0x5
29903#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK 0x80
29904#define PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT 0x7
29905#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK 0x7
29906#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT 0x0
29907#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK 0x10
29908#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT 0x4
29909#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK 0x20
29910#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT 0x5
29911#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK 0x80
29912#define PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT 0x7
29913#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK 0x7
29914#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT 0x0
29915#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK 0x10
29916#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT 0x4
29917#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK 0x20
29918#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT 0x5
29919#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK 0x80
29920#define PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT 0x7
29921#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK 0x7
29922#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT 0x0
29923#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK 0x10
29924#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT 0x4
29925#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK 0x20
29926#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT 0x5
29927#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK 0x80
29928#define PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT 0x7
29929#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK 0x7
29930#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT 0x0
29931#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK 0x10
29932#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT 0x4
29933#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK 0x20
29934#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT 0x5
29935#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK 0x80
29936#define PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT 0x7
29937#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK 0x7
29938#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT 0x0
29939#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK 0x10
29940#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT 0x4
29941#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK 0x20
29942#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT 0x5
29943#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK 0x80
29944#define PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT 0x7
29945#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK 0x7
29946#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT 0x0
29947#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK 0x10
29948#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT 0x4
29949#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK 0x20
29950#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT 0x5
29951#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK 0x80
29952#define PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT 0x7
29953#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK 0x7
29954#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT 0x0
29955#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK 0x10
29956#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT 0x4
29957#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK 0x20
29958#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT 0x5
29959#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK 0x80
29960#define PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT 0x7
29961#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK 0x1
29962#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT 0x0
29963#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK 0x2
29964#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT 0x1
29965#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK 0x10
29966#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT 0x4
29967#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK 0x20
29968#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT 0x5
29969#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK 0x40
29970#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT 0x6
29971#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK 0x80
29972#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT 0x7
29973#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK 0x100
29974#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT 0x8
29975#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK 0x400
29976#define PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT 0xa
29977#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK 0x1
29978#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT 0x0
29979#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK 0x2
29980#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT 0x1
29981#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK 0x10
29982#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT 0x4
29983#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK 0x20
29984#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT 0x5
29985#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK 0x40
29986#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT 0x6
29987#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK 0x80
29988#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT 0x7
29989#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK 0x100
29990#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT 0x8
29991#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK 0x400
29992#define PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT 0xa
29993#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK 0x1
29994#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT 0x0
29995#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK 0x2
29996#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT 0x1
29997#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK 0x10
29998#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT 0x4
29999#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK 0x20
30000#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT 0x5
30001#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK 0x40
30002#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT 0x6
30003#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK 0x80
30004#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT 0x7
30005#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK 0x100
30006#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT 0x8
30007#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK 0x400
30008#define PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT 0xa
30009#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK 0x1
30010#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT 0x0
30011#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK 0x2
30012#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT 0x1
30013#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK 0x10
30014#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT 0x4
30015#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK 0x20
30016#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT 0x5
30017#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK 0x40
30018#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT 0x6
30019#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK 0x80
30020#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT 0x7
30021#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK 0x100
30022#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT 0x8
30023#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK 0x400
30024#define PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT 0xa
30025#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK 0x1
30026#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT 0x0
30027#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK 0x2
30028#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT 0x1
30029#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK 0x10
30030#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT 0x4
30031#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK 0x20
30032#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT 0x5
30033#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK 0x40
30034#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT 0x6
30035#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK 0x80
30036#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT 0x7
30037#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK 0x100
30038#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT 0x8
30039#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK 0x400
30040#define PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT 0xa
30041#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK 0x1
30042#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT 0x0
30043#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK 0x2
30044#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT 0x1
30045#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK 0x10
30046#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT 0x4
30047#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK 0x20
30048#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT 0x5
30049#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK 0x40
30050#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT 0x6
30051#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK 0x80
30052#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT 0x7
30053#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK 0x100
30054#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT 0x8
30055#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK 0x400
30056#define PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT 0xa
30057#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK 0x1
30058#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT 0x0
30059#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK 0x2
30060#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT 0x1
30061#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK 0x10
30062#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT 0x4
30063#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK 0x20
30064#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT 0x5
30065#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK 0x40
30066#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT 0x6
30067#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK 0x80
30068#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT 0x7
30069#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK 0x100
30070#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT 0x8
30071#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK 0x400
30072#define PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT 0xa
30073#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK 0x1
30074#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT 0x0
30075#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK 0x2
30076#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT 0x1
30077#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK 0x10
30078#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT 0x4
30079#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK 0x20
30080#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT 0x5
30081#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK 0x40
30082#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT 0x6
30083#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK 0x80
30084#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT 0x7
30085#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK 0x100
30086#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT 0x8
30087#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK 0x400
30088#define PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT 0xa
30089#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK 0x1
30090#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT 0x0
30091#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK 0x2
30092#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT 0x1
30093#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK 0x10
30094#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT 0x4
30095#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK 0x20
30096#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT 0x5
30097#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK 0x40
30098#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT 0x6
30099#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK 0x80
30100#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT 0x7
30101#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK 0x100
30102#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT 0x8
30103#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK 0x400
30104#define PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT 0xa
30105#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK 0x1
30106#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT 0x0
30107#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK 0x2
30108#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT 0x1
30109#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK 0x4
30110#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT 0x2
30111#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK 0x1f8
30112#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT 0x3
30113#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK 0x400
30114#define PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT 0xa
30115#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK 0x1
30116#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT 0x0
30117#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK 0x2
30118#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT 0x1
30119#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK 0x4
30120#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT 0x2
30121#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK 0x1f8
30122#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT 0x3
30123#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK 0x400
30124#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT 0xa
30125#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK 0x1
30126#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT 0x0
30127#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK 0x2
30128#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT 0x1
30129#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK 0x4
30130#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT 0x2
30131#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK 0x1f8
30132#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT 0x3
30133#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK 0x400
30134#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT 0xa
30135#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK 0x1
30136#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT 0x0
30137#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK 0x2
30138#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT 0x1
30139#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK 0x4
30140#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT 0x2
30141#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK 0x1f8
30142#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT 0x3
30143#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK 0x400
30144#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT 0xa
30145#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK 0x1
30146#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT 0x0
30147#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK 0x2
30148#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT 0x1
30149#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK 0x4
30150#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT 0x2
30151#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK 0x1f8
30152#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT 0x3
30153#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK 0x400
30154#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT 0xa
30155#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK 0x1
30156#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT 0x0
30157#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK 0x2
30158#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT 0x1
30159#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK 0x4
30160#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT 0x2
30161#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK 0x1f8
30162#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT 0x3
30163#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK 0x400
30164#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT 0xa
30165#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK 0x1
30166#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT 0x0
30167#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK 0x2
30168#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT 0x1
30169#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK 0x4
30170#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT 0x2
30171#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK 0x1f8
30172#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT 0x3
30173#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK 0x400
30174#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT 0xa
30175#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK 0x1
30176#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT 0x0
30177#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK 0x2
30178#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT 0x1
30179#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK 0x4
30180#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT 0x2
30181#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK 0x1f8
30182#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT 0x3
30183#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK 0x400
30184#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT 0xa
30185#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK 0x1
30186#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT 0x0
30187#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK 0x2
30188#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT 0x1
30189#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK 0x4
30190#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT 0x2
30191#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK 0x1f8
30192#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT 0x3
30193#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK 0x400
30194#define PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT 0xa
30195#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK 0x3ff
30196#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT 0x0
30197#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK 0xe000
30198#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT 0xd
30199#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK 0x20000
30200#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT 0x11
30201#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30202#define PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30203#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK 0x3ff
30204#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT 0x0
30205#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK 0xe000
30206#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT 0xd
30207#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK 0x20000
30208#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT 0x11
30209#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30210#define PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30211#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK 0x3ff
30212#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT 0x0
30213#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK 0xe000
30214#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT 0xd
30215#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK 0x20000
30216#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT 0x11
30217#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30218#define PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30219#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK 0x3ff
30220#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT 0x0
30221#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK 0xe000
30222#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT 0xd
30223#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK 0x20000
30224#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT 0x11
30225#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30226#define PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30227#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK 0x3ff
30228#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT 0x0
30229#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK 0xe000
30230#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT 0xd
30231#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK 0x20000
30232#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT 0x11
30233#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30234#define PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30235#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK 0x3ff
30236#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT 0x0
30237#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK 0xe000
30238#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT 0xd
30239#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK 0x20000
30240#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT 0x11
30241#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30242#define PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30243#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK 0x3ff
30244#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT 0x0
30245#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK 0xe000
30246#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT 0xd
30247#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK 0x20000
30248#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT 0x11
30249#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30250#define PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30251#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK 0x3ff
30252#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT 0x0
30253#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK 0xe000
30254#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT 0xd
30255#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK 0x20000
30256#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT 0x11
30257#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30258#define PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30259#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK 0x3ff
30260#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT 0x0
30261#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK 0xe000
30262#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT 0xd
30263#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK 0x20000
30264#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT 0x11
30265#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK 0x180000
30266#define PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT 0x13
30267#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK 0x1
30268#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT 0x0
30269#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK 0x1fe
30270#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT 0x1
30271#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK 0x800
30272#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT 0xb
30273#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK 0x1000
30274#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT 0xc
30275#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK 0x2000
30276#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT 0xd
30277#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK 0x4000
30278#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT 0xe
30279#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK 0x10000
30280#define PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT 0x10
30281#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK 0x1
30282#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT 0x0
30283#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK 0x1fe
30284#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT 0x1
30285#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK 0x800
30286#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT 0xb
30287#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK 0x1000
30288#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT 0xc
30289#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK 0x2000
30290#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT 0xd
30291#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK 0x4000
30292#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT 0xe
30293#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK 0x10000
30294#define PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT 0x10
30295#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK 0x1
30296#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT 0x0
30297#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK 0x1fe
30298#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT 0x1
30299#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK 0x800
30300#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT 0xb
30301#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK 0x1000
30302#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT 0xc
30303#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK 0x2000
30304#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT 0xd
30305#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK 0x4000
30306#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT 0xe
30307#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK 0x10000
30308#define PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT 0x10
30309#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK 0x1
30310#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT 0x0
30311#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK 0x1fe
30312#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT 0x1
30313#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK 0x800
30314#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT 0xb
30315#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK 0x1000
30316#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT 0xc
30317#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK 0x2000
30318#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT 0xd
30319#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK 0x4000
30320#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT 0xe
30321#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK 0x10000
30322#define PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT 0x10
30323#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK 0x1
30324#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT 0x0
30325#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK 0x1fe
30326#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT 0x1
30327#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK 0x800
30328#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT 0xb
30329#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK 0x1000
30330#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT 0xc
30331#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK 0x2000
30332#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT 0xd
30333#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK 0x4000
30334#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT 0xe
30335#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK 0x10000
30336#define PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT 0x10
30337#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK 0x1
30338#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT 0x0
30339#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK 0x1fe
30340#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT 0x1
30341#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK 0x800
30342#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT 0xb
30343#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK 0x1000
30344#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT 0xc
30345#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK 0x2000
30346#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT 0xd
30347#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK 0x4000
30348#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT 0xe
30349#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK 0x10000
30350#define PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT 0x10
30351#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK 0x1
30352#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT 0x0
30353#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK 0x1fe
30354#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT 0x1
30355#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK 0x800
30356#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT 0xb
30357#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK 0x1000
30358#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT 0xc
30359#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK 0x2000
30360#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT 0xd
30361#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK 0x4000
30362#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT 0xe
30363#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK 0x10000
30364#define PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT 0x10
30365#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK 0x1
30366#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT 0x0
30367#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK 0x1fe
30368#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT 0x1
30369#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK 0x800
30370#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT 0xb
30371#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK 0x1000
30372#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT 0xc
30373#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK 0x2000
30374#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT 0xd
30375#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK 0x4000
30376#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT 0xe
30377#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK 0x10000
30378#define PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT 0x10
30379#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK 0x1
30380#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT 0x0
30381#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK 0x1fe
30382#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT 0x1
30383#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK 0x800
30384#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT 0xb
30385#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK 0x1000
30386#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT 0xc
30387#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK 0x2000
30388#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT 0xd
30389#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK 0x4000
30390#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT 0xe
30391#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK 0x10000
30392#define PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT 0x10
30393#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30394#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30395#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30396#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30397#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30398#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30399#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30400#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30401#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30402#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30403#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30404#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30405#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30406#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30407#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30408#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30409#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30410#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30411#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30412#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30413#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30414#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30415#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30416#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30417#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30418#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30419#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30420#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30421#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30422#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30423#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30424#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30425#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30426#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30427#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30428#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30429#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30430#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30431#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30432#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30433#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30434#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30435#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30436#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30437#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30438#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30439#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30440#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30441#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30442#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30443#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30444#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30445#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30446#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30447#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30448#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30449#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30450#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30451#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30452#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30453#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30454#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30455#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30456#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30457#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30458#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30459#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30460#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30461#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30462#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30463#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30464#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30465#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30466#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30467#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30468#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30469#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30470#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30471#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30472#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30473#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30474#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30475#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30476#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30477#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30478#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30479#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30480#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30481#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30482#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30483#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30484#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30485#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30486#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30487#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30488#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30489#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30490#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30491#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30492#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30493#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30494#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30495#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30496#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30497#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30498#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30499#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30500#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30501#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30502#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30503#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30504#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30505#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30506#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30507#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30508#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30509#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30510#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30511#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30512#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30513#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30514#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30515#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30516#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30517#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30518#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30519#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30520#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30521#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK 0x1
30522#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT 0x0
30523#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK 0x2
30524#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT 0x1
30525#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK 0x4
30526#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT 0x2
30527#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK 0x8
30528#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT 0x3
30529#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK 0x10
30530#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT 0x4
30531#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK 0x20
30532#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT 0x5
30533#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK 0x40
30534#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT 0x6
30535#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK 0x80
30536#define PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT 0x7
30537#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK 0x1
30538#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT 0x0
30539#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK 0x2
30540#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT 0x1
30541#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK 0x4
30542#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT 0x2
30543#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30544#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30545#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30546#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30547#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30548#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30549#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK 0x40
30550#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT 0x6
30551#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK 0x80
30552#define PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT 0x7
30553#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK 0x1
30554#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT 0x0
30555#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK 0x2
30556#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT 0x1
30557#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK 0x4
30558#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT 0x2
30559#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30560#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30561#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30562#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30563#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30564#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30565#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK 0x40
30566#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT 0x6
30567#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK 0x80
30568#define PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT 0x7
30569#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK 0x1
30570#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT 0x0
30571#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK 0x2
30572#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT 0x1
30573#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK 0x4
30574#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT 0x2
30575#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30576#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30577#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30578#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30579#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30580#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30581#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK 0x40
30582#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT 0x6
30583#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK 0x80
30584#define PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT 0x7
30585#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK 0x1
30586#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT 0x0
30587#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK 0x2
30588#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT 0x1
30589#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK 0x4
30590#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT 0x2
30591#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30592#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30593#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30594#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30595#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30596#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30597#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK 0x40
30598#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT 0x6
30599#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK 0x80
30600#define PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT 0x7
30601#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK 0x1
30602#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT 0x0
30603#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK 0x2
30604#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT 0x1
30605#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK 0x4
30606#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT 0x2
30607#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30608#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30609#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30610#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30611#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30612#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30613#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK 0x40
30614#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT 0x6
30615#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK 0x80
30616#define PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT 0x7
30617#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK 0x1
30618#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT 0x0
30619#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK 0x2
30620#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT 0x1
30621#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK 0x4
30622#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT 0x2
30623#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30624#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30625#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30626#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30627#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30628#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30629#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK 0x40
30630#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT 0x6
30631#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK 0x80
30632#define PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT 0x7
30633#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK 0x1
30634#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT 0x0
30635#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK 0x2
30636#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT 0x1
30637#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK 0x4
30638#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT 0x2
30639#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30640#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30641#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30642#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30643#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30644#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30645#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK 0x40
30646#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT 0x6
30647#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK 0x80
30648#define PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT 0x7
30649#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK 0x1
30650#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT 0x0
30651#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK 0x2
30652#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT 0x1
30653#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK 0x4
30654#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT 0x2
30655#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30656#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30657#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30658#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30659#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30660#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30661#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK 0x40
30662#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT 0x6
30663#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK 0x80
30664#define PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT 0x7
30665#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK 0x1
30666#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT 0x0
30667#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK 0x2
30668#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT 0x1
30669#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK 0x4
30670#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT 0x2
30671#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK 0x8
30672#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT 0x3
30673#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK 0x10
30674#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT 0x4
30675#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK 0x20
30676#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT 0x5
30677#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK 0x40
30678#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT 0x6
30679#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK 0x80
30680#define PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT 0x7
30681#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK 0xf
30682#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT 0x0
30683#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK 0x1ffc0
30684#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT 0x6
30685#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK 0x80000
30686#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT 0x13
30687#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK 0x100000
30688#define PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT 0x14
30689#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK 0xf
30690#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT 0x0
30691#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK 0x1ffc0
30692#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT 0x6
30693#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK 0x80000
30694#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT 0x13
30695#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK 0x100000
30696#define PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT 0x14
30697#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK 0xf
30698#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT 0x0
30699#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK 0x1ffc0
30700#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT 0x6
30701#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK 0x80000
30702#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT 0x13
30703#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK 0x100000
30704#define PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT 0x14
30705#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK 0xf
30706#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT 0x0
30707#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK 0x1ffc0
30708#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT 0x6
30709#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK 0x80000
30710#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT 0x13
30711#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK 0x100000
30712#define PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT 0x14
30713#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK 0xf
30714#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT 0x0
30715#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK 0x1ffc0
30716#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT 0x6
30717#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK 0x80000
30718#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT 0x13
30719#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK 0x100000
30720#define PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT 0x14
30721#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK 0xf
30722#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT 0x0
30723#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK 0x1ffc0
30724#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT 0x6
30725#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK 0x80000
30726#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT 0x13
30727#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK 0x100000
30728#define PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT 0x14
30729#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK 0xf
30730#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT 0x0
30731#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK 0x1ffc0
30732#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT 0x6
30733#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK 0x80000
30734#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT 0x13
30735#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK 0x100000
30736#define PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT 0x14
30737#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK 0xf
30738#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT 0x0
30739#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK 0x1ffc0
30740#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT 0x6
30741#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK 0x80000
30742#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT 0x13
30743#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK 0x100000
30744#define PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT 0x14
30745#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK 0xf
30746#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT 0x0
30747#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK 0x1ffc0
30748#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT 0x6
30749#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK 0x80000
30750#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT 0x13
30751#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK 0x100000
30752#define PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT 0x14
30753#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK 0x7
30754#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT 0x0
30755#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK 0x18
30756#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT 0x3
30757#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK 0x7
30758#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT 0x0
30759#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK 0x18
30760#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT 0x3
30761#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK 0x7
30762#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT 0x0
30763#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK 0x18
30764#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT 0x3
30765#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK 0x7
30766#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT 0x0
30767#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK 0x18
30768#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT 0x3
30769#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK 0x7
30770#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT 0x0
30771#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK 0x18
30772#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT 0x3
30773#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK 0x7
30774#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT 0x0
30775#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK 0x18
30776#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT 0x3
30777#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK 0x7
30778#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT 0x0
30779#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK 0x18
30780#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT 0x3
30781#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK 0x7
30782#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT 0x0
30783#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK 0x18
30784#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT 0x3
30785#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK 0x7
30786#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT 0x0
30787#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK 0x18
30788#define PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT 0x3
30789#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK 0x1
30790#define PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT 0x0
30791#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK 0x4
30792#define PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT 0x2
30793#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK 0x10
30794#define PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT 0x4
30795#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK 0x100
30796#define PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT 0x8
30797#define PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK 0x1
30798#define PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT 0x0
30799#define PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK 0x4
30800#define PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT 0x2
30801#define PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK 0x10
30802#define PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT 0x4
30803#define PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK 0x100
30804#define PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT 0x8
30805#define PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK 0x1
30806#define PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT 0x0
30807#define PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK 0x4
30808#define PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT 0x2
30809#define PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK 0x10
30810#define PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT 0x4
30811#define PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK 0x100
30812#define PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT 0x8
30813#define PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK 0x1
30814#define PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT 0x0
30815#define PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK 0x4
30816#define PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT 0x2
30817#define PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK 0x10
30818#define PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT 0x4
30819#define PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK 0x100
30820#define PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT 0x8
30821#define PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK 0x1
30822#define PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT 0x0
30823#define PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK 0x4
30824#define PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT 0x2
30825#define PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK 0x10
30826#define PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT 0x4
30827#define PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK 0x100
30828#define PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT 0x8
30829#define PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK 0x1
30830#define PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT 0x0
30831#define PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK 0x4
30832#define PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT 0x2
30833#define PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK 0x10
30834#define PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT 0x4
30835#define PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK 0x100
30836#define PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT 0x8
30837#define PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK 0x1
30838#define PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT 0x0
30839#define PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK 0x4
30840#define PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT 0x2
30841#define PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK 0x10
30842#define PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT 0x4
30843#define PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK 0x100
30844#define PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT 0x8
30845#define PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK 0x1
30846#define PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT 0x0
30847#define PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK 0x4
30848#define PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT 0x2
30849#define PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK 0x10
30850#define PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT 0x4
30851#define PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK 0x100
30852#define PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT 0x8
30853#define PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK 0x1
30854#define PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT 0x0
30855#define PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK 0x4
30856#define PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT 0x2
30857#define PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK 0x10
30858#define PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT 0x4
30859#define PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK 0x100
30860#define PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT 0x8
30861#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK 0xff
30862#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT 0x0
30863#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK 0x3f00
30864#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT 0x8
30865#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK 0xff0000
30866#define PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT 0x10
30867#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK 0xff
30868#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT 0x0
30869#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK 0x3f00
30870#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT 0x8
30871#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK 0xff0000
30872#define PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT 0x10
30873#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK 0xff
30874#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT 0x0
30875#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK 0x3f00
30876#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT 0x8
30877#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK 0xff0000
30878#define PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT 0x10
30879#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK 0xff
30880#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT 0x0
30881#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK 0x3f00
30882#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT 0x8
30883#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK 0xff0000
30884#define PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT 0x10
30885#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK 0xff
30886#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT 0x0
30887#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK 0x3f00
30888#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT 0x8
30889#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK 0xff0000
30890#define PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT 0x10
30891#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK 0xff
30892#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT 0x0
30893#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK 0x3f00
30894#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT 0x8
30895#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK 0xff0000
30896#define PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT 0x10
30897#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK 0xff
30898#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT 0x0
30899#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK 0x3f00
30900#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT 0x8
30901#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK 0xff0000
30902#define PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT 0x10
30903#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK 0xff
30904#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT 0x0
30905#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK 0x3f00
30906#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT 0x8
30907#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK 0xff0000
30908#define PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT 0x10
30909#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK 0xff
30910#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT 0x0
30911#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK 0x3f00
30912#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT 0x8
30913#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK 0xff0000
30914#define PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT 0x10
30915#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK 0x7
30916#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT 0x0
30917#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK 0x8
30918#define PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT 0x3
30919#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK 0x7
30920#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT 0x0
30921#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK 0x8
30922#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT 0x3
30923#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK 0x7
30924#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT 0x0
30925#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK 0x8
30926#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT 0x3
30927#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK 0x7
30928#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT 0x0
30929#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK 0x8
30930#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT 0x3
30931#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK 0x7
30932#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT 0x0
30933#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK 0x8
30934#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT 0x3
30935#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK 0x7
30936#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT 0x0
30937#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK 0x8
30938#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT 0x3
30939#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK 0x7
30940#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT 0x0
30941#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK 0x8
30942#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT 0x3
30943#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK 0x7
30944#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT 0x0
30945#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK 0x8
30946#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT 0x3
30947#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK 0x7
30948#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT 0x0
30949#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK 0x8
30950#define PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT 0x3
30951#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK 0x1f
30952#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT 0x0
30953#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK 0x40
30954#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT 0x6
30955#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK 0x100
30956#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT 0x8
30957#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK 0x400
30958#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT 0xa
30959#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK 0x1000
30960#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT 0xc
30961#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK 0x7f0000
30962#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT 0x10
30963#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK 0x1f
30964#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT 0x0
30965#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK 0x40
30966#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT 0x6
30967#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK 0x100
30968#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT 0x8
30969#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK 0x400
30970#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT 0xa
30971#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK 0x1000
30972#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT 0xc
30973#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK 0x7f0000
30974#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT 0x10
30975#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK 0x1f
30976#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT 0x0
30977#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK 0x40
30978#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT 0x6
30979#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK 0x100
30980#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT 0x8
30981#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK 0x400
30982#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT 0xa
30983#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK 0x1000
30984#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT 0xc
30985#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK 0x7f0000
30986#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT 0x10
30987#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK 0x1f
30988#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT 0x0
30989#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK 0x40
30990#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT 0x6
30991#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK 0x100
30992#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT 0x8
30993#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK 0x400
30994#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT 0xa
30995#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK 0x1000
30996#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT 0xc
30997#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK 0x7f0000
30998#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT 0x10
30999#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK 0x1f
31000#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT 0x0
31001#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK 0x40
31002#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT 0x6
31003#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK 0x100
31004#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT 0x8
31005#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK 0x400
31006#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT 0xa
31007#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK 0x1000
31008#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT 0xc
31009#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK 0x7f0000
31010#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT 0x10
31011#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK 0x1f
31012#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT 0x0
31013#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK 0x40
31014#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT 0x6
31015#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK 0x100
31016#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT 0x8
31017#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK 0x400
31018#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT 0xa
31019#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK 0x1000
31020#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT 0xc
31021#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK 0x7f0000
31022#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT 0x10
31023#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK 0x1f
31024#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT 0x0
31025#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK 0x40
31026#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT 0x6
31027#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK 0x100
31028#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT 0x8
31029#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK 0x400
31030#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT 0xa
31031#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK 0x1000
31032#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT 0xc
31033#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK 0x7f0000
31034#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT 0x10
31035#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK 0x1f
31036#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT 0x0
31037#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK 0x40
31038#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT 0x6
31039#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK 0x100
31040#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT 0x8
31041#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK 0x400
31042#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT 0xa
31043#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK 0x1000
31044#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT 0xc
31045#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK 0x7f0000
31046#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT 0x10
31047#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK 0x1f
31048#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT 0x0
31049#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK 0x40
31050#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT 0x6
31051#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK 0x100
31052#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT 0x8
31053#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK 0x400
31054#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT 0xa
31055#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK 0x1000
31056#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT 0xc
31057#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK 0x7f0000
31058#define PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT 0x10
31059#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK 0x800
31060#define PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT 0xb
31061#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK 0x800
31062#define PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT 0xb
31063#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK 0x800
31064#define PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT 0xb
31065#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK 0x800
31066#define PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT 0xb
31067#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK 0x800
31068#define PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT 0xb
31069#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK 0x800
31070#define PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT 0xb
31071#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK 0x800
31072#define PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT 0xb
31073#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK 0x800
31074#define PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT 0xb
31075#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK 0x800
31076#define PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT 0xb
31077#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK 0x1
31078#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT 0x0
31079#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK 0x6
31080#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT 0x1
31081#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK 0x8
31082#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT 0x3
31083#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK 0xe0
31084#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT 0x5
31085#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK 0x1
31086#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT 0x0
31087#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK 0x6
31088#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT 0x1
31089#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK 0x8
31090#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT 0x3
31091#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK 0xe0
31092#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT 0x5
31093#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK 0x1
31094#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT 0x0
31095#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK 0x6
31096#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT 0x1
31097#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK 0x8
31098#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT 0x3
31099#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK 0xe0
31100#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT 0x5
31101#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK 0x1
31102#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT 0x0
31103#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK 0x6
31104#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT 0x1
31105#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK 0x8
31106#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT 0x3
31107#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK 0xe0
31108#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT 0x5
31109#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK 0x1
31110#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT 0x0
31111#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK 0x6
31112#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT 0x1
31113#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK 0x8
31114#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT 0x3
31115#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK 0xe0
31116#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT 0x5
31117#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK 0x1
31118#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT 0x0
31119#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK 0x6
31120#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT 0x1
31121#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK 0x8
31122#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT 0x3
31123#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK 0xe0
31124#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT 0x5
31125#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK 0x1
31126#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT 0x0
31127#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK 0x6
31128#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT 0x1
31129#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK 0x8
31130#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT 0x3
31131#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK 0xe0
31132#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT 0x5
31133#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK 0x1
31134#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT 0x0
31135#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK 0x6
31136#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT 0x1
31137#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK 0x8
31138#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT 0x3
31139#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK 0xe0
31140#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT 0x5
31141#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK 0x1
31142#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT 0x0
31143#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK 0x6
31144#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT 0x1
31145#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK 0x8
31146#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT 0x3
31147#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK 0xe0
31148#define PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT 0x5
31149#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
31150#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
31151#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
31152#define PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
31153#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
31154#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
31155#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
31156#define PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
31157#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK 0xff
31158#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT 0x0
31159#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK 0x3c00
31160#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT 0xa
31161#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK 0x3fc000
31162#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT 0xe
31163#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
31164#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT 0x16
31165#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK 0x4000000
31166#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT 0x1a
31167#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
31168#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
31169#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK 0x20000000
31170#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT 0x1d
31171#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
31172#define PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
31173#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
31174#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
31175#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
31176#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
31177#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK 0x3ffff
31178#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT 0x0
31179#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK 0x40000
31180#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT 0x12
31181#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
31182#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
31183#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK 0x7f
31184#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT 0x0
31185#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK 0x80
31186#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT 0x7
31187#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK 0x100
31188#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT 0x8
31189#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK 0x200
31190#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT 0x9
31191#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK 0x400
31192#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT 0xa
31193#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK 0x800
31194#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT 0xb
31195#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
31196#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
31197#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
31198#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
31199#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
31200#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
31201#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
31202#define PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
31203#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
31204#define PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
31205#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK 0x1
31206#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT 0x0
31207#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK 0x2
31208#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT 0x1
31209#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK 0x4
31210#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x2
31211#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK 0x8
31212#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT 0x3
31213#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10
31214#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x4
31215#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK 0x60
31216#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT 0x5
31217#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
31218#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
31219#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK 0x4000000
31220#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT 0x1a
31221#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK 0x1
31222#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT 0x0
31223#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK 0x1e
31224#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT 0x1
31225#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK 0xf00
31226#define PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT 0x8
31227#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
31228#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
31229#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
31230#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
31231#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
31232#define PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
31233#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK 0x7
31234#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT 0x0
31235#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK 0x10
31236#define PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT 0x4
31237#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK 0x7
31238#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT 0x0
31239#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK 0x8
31240#define PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT 0x3
31241#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK 0xff
31242#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT 0x0
31243#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK 0x700
31244#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT 0x8
31245#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK 0x3000
31246#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT 0xc
31247#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK 0x3c000
31248#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT 0xe
31249#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK 0x3c0000
31250#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT 0x12
31251#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK 0x3c00000
31252#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT 0x16
31253#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK 0x4000000
31254#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT 0x1a
31255#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK 0x10000000
31256#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT 0x1c
31257#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK 0x20000000
31258#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT 0x1d
31259#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK 0xc0000000
31260#define PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT 0x1e
31261#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK 0x7ff
31262#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT 0x0
31263#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK 0xfffff800
31264#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT 0xb
31265#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK 0x3ffff
31266#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT 0x0
31267#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK 0x40000
31268#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT 0x12
31269#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK 0xe00000
31270#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT 0x15
31271#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK 0x1000
31272#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT 0xc
31273#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK 0x2000
31274#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT 0xd
31275#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK 0x10000
31276#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT 0x10
31277#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK 0x20000
31278#define PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT 0x11
31279#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK 0xff
31280#define PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT 0x0
31281#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK 0x1
31282#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT 0x0
31283#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK 0x3800000
31284#define PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT 0x17
31285#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK 0x3fff
31286#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT 0x0
31287#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK 0x8000
31288#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT 0xf
31289#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK 0x10000
31290#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT 0x10
31291#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK 0xe0000
31292#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT 0x11
31293#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK 0x3f00000
31294#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT 0x14
31295#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK 0x4000000
31296#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT 0x1a
31297#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK 0x8000000
31298#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT 0x1b
31299#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK 0x20000000
31300#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT 0x1d
31301#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK 0xffff
31302#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT 0x0
31303#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK 0xff
31304#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT 0x0
31305#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK 0xf00
31306#define PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT 0x8
31307#define PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
31308#define PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
31309#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
31310#define PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
31311#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
31312#define PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
31313#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
31314#define PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
31315#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
31316#define PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
31317#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
31318#define PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
31319#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
31320#define PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
31321#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
31322#define PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
31323#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
31324#define PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
31325#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
31326#define PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
31327#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
31328#define PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
31329#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
31330#define PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
31331#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
31332#define PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
31333#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
31334#define PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
31335#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
31336#define PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
31337#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
31338#define PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
31339#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
31340#define PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
31341#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
31342#define PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
31343#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
31344#define PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
31345#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
31346#define PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
31347#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
31348#define PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
31349#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
31350#define PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
31351#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
31352#define PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
31353#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
31354#define PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
31355#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
31356#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
31357#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
31358#define PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
31359#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
31360#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
31361#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
31362#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
31363#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
31364#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
31365#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
31366#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
31367#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
31368#define PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
31369#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
31370#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
31371#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
31372#define PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
31373#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
31374#define PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
31375#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
31376#define PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
31377#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
31378#define PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
31379#define PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
31380#define PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
31381#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
31382#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
31383#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
31384#define PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
31385#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
31386#define PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
31387#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
31388#define PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
31389#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
31390#define PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
31391#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
31392#define PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
31393#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
31394#define PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
31395#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
31396#define PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
31397#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
31398#define PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
31399#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
31400#define PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
31401#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
31402#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
31403#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
31404#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
31405#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
31406#define PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
31407#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
31408#define PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
31409#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
31410#define PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
31411#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
31412#define PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
31413#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
31414#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
31415#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
31416#define PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
31417#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
31418#define PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
31419#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
31420#define PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
31421#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
31422#define PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
31423#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
31424#define PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
31425#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
31426#define PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
31427#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
31428#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
31429#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
31430#define PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
31431#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
31432#define PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
31433#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
31434#define PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
31435#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
31436#define PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
31437#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
31438#define PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
31439#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
31440#define PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
31441#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
31442#define PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
31443#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
31444#define PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
31445#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
31446#define PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
31447#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
31448#define PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
31449#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
31450#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
31451#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
31452#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
31453#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
31454#define PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
31455#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
31456#define PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
31457#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
31458#define PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
31459#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
31460#define PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
31461#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
31462#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
31463#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
31464#define PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
31465#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
31466#define PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
31467#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
31468#define PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
31469#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
31470#define PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
31471#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
31472#define PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
31473#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
31474#define PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
31475#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
31476#define PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
31477#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
31478#define PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
31479#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
31480#define PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
31481#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
31482#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
31483#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
31484#define PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
31485#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
31486#define PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
31487#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
31488#define PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
31489#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
31490#define PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
31491#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
31492#define PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
31493#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
31494#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
31495#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
31496#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
31497#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
31498#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
31499#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
31500#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
31501#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
31502#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
31503#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
31504#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
31505#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
31506#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
31507#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
31508#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
31509#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
31510#define PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
31511#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
31512#define PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
31513#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
31514#define PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
31515#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
31516#define PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
31517#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
31518#define PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
31519#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
31520#define PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
31521#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
31522#define PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
31523#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
31524#define PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
31525#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
31526#define PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
31527#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
31528#define PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
31529#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
31530#define PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
31531#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
31532#define PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
31533#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
31534#define PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
31535#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
31536#define PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
31537#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
31538#define PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
31539#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
31540#define PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
31541#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
31542#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
31543#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
31544#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
31545#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
31546#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
31547#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
31548#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
31549#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
31550#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
31551#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
31552#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
31553#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
31554#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
31555#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
31556#define PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
31557#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
31558#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
31559#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
31560#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
31561#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
31562#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
31563#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
31564#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
31565#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
31566#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
31567#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
31568#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
31569#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
31570#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
31571#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
31572#define PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
31573#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
31574#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
31575#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
31576#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
31577#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
31578#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
31579#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
31580#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
31581#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
31582#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
31583#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
31584#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
31585#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
31586#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
31587#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
31588#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
31589#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
31590#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
31591#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
31592#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
31593#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
31594#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
31595#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
31596#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
31597#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
31598#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
31599#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
31600#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
31601#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
31602#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
31603#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
31604#define PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
31605#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
31606#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
31607#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
31608#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
31609#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
31610#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
31611#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
31612#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
31613#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
31614#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
31615#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
31616#define PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
31617#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
31618#define PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
31619#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
31620#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
31621#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
31622#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
31623#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
31624#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
31625#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
31626#define PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
31627#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
31628#define PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
31629#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
31630#define PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
31631#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
31632#define PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
31633#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
31634#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
31635#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
31636#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
31637#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
31638#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
31639#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
31640#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
31641#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
31642#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
31643#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
31644#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
31645#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
31646#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
31647#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
31648#define PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
31649#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
31650#define PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
31651#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
31652#define PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
31653#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
31654#define PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
31655#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
31656#define PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
31657#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
31658#define PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
31659#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
31660#define PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
31661#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
31662#define PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
31663#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
31664#define PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
31665#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
31666#define PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
31667#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
31668#define PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
31669#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
31670#define PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
31671#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
31672#define PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
31673#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
31674#define PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
31675#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
31676#define PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
31677#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
31678#define PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
31679#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
31680#define PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
31681#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
31682#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
31683#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
31684#define PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
31685#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
31686#define PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
31687#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
31688#define PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
31689#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
31690#define PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
31691#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
31692#define PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
31693#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
31694#define PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
31695#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
31696#define PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
31697#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
31698#define PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
31699#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
31700#define PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
31701#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
31702#define PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
31703#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
31704#define PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
31705#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
31706#define PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
31707#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
31708#define PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
31709#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
31710#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
31711#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
31712#define PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
31713#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
31714#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
31715#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
31716#define PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
31717#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
31718#define PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
31719#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
31720#define PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
31721#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
31722#define PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
31723#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
31724#define PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
31725#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
31726#define PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
31727#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
31728#define PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
31729#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
31730#define PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
31731#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
31732#define PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
31733#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
31734#define PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
31735#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
31736#define PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
31737#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
31738#define PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
31739#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
31740#define PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
31741#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
31742#define PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
31743#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
31744#define PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
31745#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
31746#define PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
31747#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
31748#define PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
31749#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
31750#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
31751#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
31752#define PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
31753#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
31754#define PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
31755#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
31756#define PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
31757#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
31758#define PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
31759#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
31760#define PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
31761#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
31762#define PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
31763#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
31764#define PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
31765#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
31766#define PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
31767#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
31768#define PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
31769#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
31770#define PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
31771#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
31772#define PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
31773#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
31774#define PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
31775#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
31776#define PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
31777#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
31778#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
31779#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
31780#define PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
31781#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
31782#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
31783#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
31784#define PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
31785#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
31786#define PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
31787#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
31788#define PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
31789#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
31790#define PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
31791#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
31792#define PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
31793#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
31794#define PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
31795#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
31796#define PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
31797#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
31798#define PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
31799#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
31800#define PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
31801#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
31802#define PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
31803#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
31804#define PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
31805#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
31806#define PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
31807#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
31808#define PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
31809#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
31810#define PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
31811#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
31812#define PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
31813#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
31814#define PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
31815#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
31816#define PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
31817#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
31818#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
31819#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
31820#define PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
31821#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
31822#define PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
31823#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
31824#define PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
31825#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
31826#define PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
31827#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
31828#define PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
31829#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
31830#define PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
31831#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
31832#define PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
31833#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
31834#define PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
31835#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
31836#define PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
31837#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
31838#define PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
31839#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
31840#define PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
31841#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
31842#define PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
31843#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
31844#define PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
31845#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
31846#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
31847#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
31848#define PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
31849#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
31850#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
31851#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
31852#define PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
31853#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
31854#define PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
31855#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
31856#define PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
31857#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
31858#define PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
31859#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
31860#define PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
31861#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
31862#define PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
31863#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
31864#define PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
31865#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
31866#define PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
31867#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
31868#define PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
31869#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
31870#define PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
31871#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
31872#define PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
31873#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
31874#define PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
31875#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
31876#define PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
31877#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
31878#define PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
31879#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
31880#define PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
31881#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
31882#define PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
31883#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
31884#define PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
31885#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
31886#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
31887#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
31888#define PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
31889#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
31890#define PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
31891#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
31892#define PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
31893#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
31894#define PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
31895#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
31896#define PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
31897#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
31898#define PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
31899#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
31900#define PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
31901#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
31902#define PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
31903#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
31904#define PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
31905#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
31906#define PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
31907#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
31908#define PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
31909#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
31910#define PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
31911#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
31912#define PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
31913#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
31914#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
31915#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
31916#define PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
31917#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
31918#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
31919#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
31920#define PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
31921#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
31922#define PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
31923#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
31924#define PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
31925#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
31926#define PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
31927#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
31928#define PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
31929#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
31930#define PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
31931#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
31932#define PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
31933#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
31934#define PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
31935#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
31936#define PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
31937#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
31938#define PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
31939#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
31940#define PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
31941#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
31942#define PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
31943#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
31944#define PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
31945#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
31946#define PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
31947#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
31948#define PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
31949#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
31950#define PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
31951#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
31952#define PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
31953#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
31954#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
31955#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
31956#define PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
31957#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
31958#define PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
31959#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
31960#define PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
31961#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
31962#define PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
31963#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
31964#define PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
31965#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
31966#define PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
31967#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
31968#define PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
31969#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
31970#define PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
31971#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
31972#define PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
31973#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
31974#define PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
31975#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
31976#define PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
31977#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
31978#define PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
31979#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
31980#define PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
31981#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
31982#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
31983#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
31984#define PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
31985#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
31986#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
31987#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
31988#define PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
31989#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
31990#define PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
31991#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
31992#define PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
31993#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
31994#define PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
31995#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
31996#define PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
31997#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
31998#define PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
31999#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
32000#define PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
32001#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
32002#define PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
32003#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
32004#define PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
32005#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
32006#define PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
32007#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
32008#define PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
32009#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
32010#define PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
32011#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
32012#define PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
32013#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
32014#define PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
32015#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
32016#define PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
32017#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
32018#define PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
32019#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
32020#define PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
32021#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
32022#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
32023#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
32024#define PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
32025#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
32026#define PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
32027#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
32028#define PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
32029#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
32030#define PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
32031#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
32032#define PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
32033#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
32034#define PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
32035#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
32036#define PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
32037#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
32038#define PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
32039#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
32040#define PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
32041#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
32042#define PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
32043#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
32044#define PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
32045#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
32046#define PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
32047#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
32048#define PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
32049#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
32050#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
32051#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
32052#define PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
32053#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
32054#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
32055#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
32056#define PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
32057#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
32058#define PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
32059#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
32060#define PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
32061#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
32062#define PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
32063#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
32064#define PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
32065#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
32066#define PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
32067#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
32068#define PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
32069#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
32070#define PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
32071#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
32072#define PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
32073#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
32074#define PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
32075#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
32076#define PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
32077#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
32078#define PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
32079#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
32080#define PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
32081#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
32082#define PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
32083#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
32084#define PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
32085#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
32086#define PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
32087#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
32088#define PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
32089#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
32090#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
32091#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
32092#define PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
32093#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
32094#define PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
32095#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
32096#define PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
32097#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
32098#define PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
32099#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
32100#define PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
32101#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
32102#define PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
32103#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
32104#define PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
32105#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
32106#define PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
32107#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
32108#define PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
32109#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
32110#define PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
32111#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
32112#define PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
32113#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
32114#define PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
32115#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
32116#define PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
32117#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
32118#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
32119#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
32120#define PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
32121#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
32122#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
32123#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
32124#define PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
32125#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
32126#define PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
32127#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
32128#define PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
32129#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
32130#define PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
32131#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
32132#define PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
32133#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
32134#define PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
32135#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
32136#define PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
32137#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
32138#define PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
32139#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
32140#define PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
32141#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
32142#define PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
32143#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
32144#define PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
32145#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
32146#define PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
32147#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
32148#define PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
32149#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
32150#define PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
32151#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
32152#define PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
32153#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
32154#define PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
32155#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
32156#define PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
32157#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
32158#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
32159#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
32160#define PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
32161#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
32162#define PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
32163#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
32164#define PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
32165#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
32166#define PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
32167#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
32168#define PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
32169#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
32170#define PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
32171#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
32172#define PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
32173#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
32174#define PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
32175#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
32176#define PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
32177#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
32178#define PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
32179#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
32180#define PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
32181#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
32182#define PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
32183#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
32184#define PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
32185#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
32186#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
32187#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
32188#define PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
32189#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
32190#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
32191#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
32192#define PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
32193#define PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK 0xffffffff
32194#define PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT 0x0
32195#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK 0x1
32196#define PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
32197#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK 0x2
32198#define PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
32199#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK 0x4
32200#define PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
32201#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK 0x8
32202#define PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
32203#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK 0x10
32204#define PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
32205#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK 0x20
32206#define PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
32207#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK 0x40
32208#define PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
32209#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK 0x80
32210#define PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
32211#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK 0x100
32212#define PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
32213#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK 0x200
32214#define PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT 0x9
32215#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK 0x400
32216#define PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
32217#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK 0x800
32218#define PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT 0xb
32219#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK 0x1000
32220#define PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT 0xc
32221#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK 0x2000
32222#define PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
32223#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK 0x4000
32224#define PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT 0xe
32225#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK 0x8000
32226#define PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT 0xf
32227#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK 0x2
32228#define PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT 0x1
32229#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK 0x4
32230#define PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT 0x2
32231#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK 0x8
32232#define PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT 0x3
32233#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK 0x10
32234#define PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT 0x4
32235#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK 0x20
32236#define PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT 0x5
32237#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK 0xc0
32238#define PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT 0x6
32239#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK 0x300
32240#define PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT 0x8
32241#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK 0x400
32242#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT 0xa
32243#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK 0x800
32244#define PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT 0xb
32245#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK 0x1000
32246#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT 0xc
32247#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK 0x2000
32248#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT 0xd
32249#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK 0x4000
32250#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT 0xe
32251#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK 0x8000
32252#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT 0xf
32253#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK 0x10000
32254#define PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT 0x10
32255#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK 0x1
32256#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT 0x0
32257#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK 0x2
32258#define PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT 0x1
32259#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK 0x4
32260#define PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT 0x2
32261#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK 0x8
32262#define PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT 0x3
32263#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK 0x10
32264#define PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT 0x4
32265#define PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK 0xc0
32266#define PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT 0x6
32267#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK 0x100
32268#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT 0x8
32269#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK 0x200
32270#define PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT 0x9
32271#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK 0x400
32272#define PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT 0xa
32273#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK 0x800
32274#define PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT 0xb
32275#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK 0x1000
32276#define PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT 0xc
32277#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK 0x2000
32278#define PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT 0xd
32279#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK 0x4000
32280#define PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT 0xe
32281#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK 0x7
32282#define PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT 0x0
32283#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK 0x38
32284#define PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT 0x3
32285#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK 0x1c0
32286#define PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT 0x6
32287#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK 0xe00
32288#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT 0x9
32289#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK 0x7000
32290#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT 0xc
32291#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK 0x38000
32292#define PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT 0xf
32293#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK 0x1c0000
32294#define PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT 0x12
32295#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK 0x200000
32296#define PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT 0x15
32297#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK 0x400000
32298#define PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT 0x16
32299#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK 0x800000
32300#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT 0x17
32301#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK 0x1000000
32302#define PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT 0x18
32303#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK 0x7
32304#define PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT 0x0
32305#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK 0x38
32306#define PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT 0x3
32307#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK 0x1c0
32308#define PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT 0x6
32309#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK 0x200
32310#define PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
32311#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
32312#define PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
32313#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK 0x10000
32314#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT 0x10
32315#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK 0x60000
32316#define PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT 0x11
32317#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK 0x200000
32318#define PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT 0x15
32319#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK 0x1c00000
32320#define PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT 0x16
32321#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK 0x2000000
32322#define PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT 0x19
32323#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK 0x1c000000
32324#define PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT 0x1a
32325#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK 0x20000000
32326#define PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT 0x1d
32327#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK 0x40000000
32328#define PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT 0x1e
32329#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK 0x7
32330#define PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT 0x0
32331#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK 0x38
32332#define PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT 0x3
32333#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK 0x1c0
32334#define PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT 0x6
32335#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK 0xe00
32336#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT 0x9
32337#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK 0x7000
32338#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT 0xc
32339#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK 0x38000
32340#define PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT 0xf
32341#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK 0x1c0000
32342#define PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT 0x12
32343#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK 0x200000
32344#define PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT 0x15
32345#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK 0x400000
32346#define PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT 0x16
32347#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK 0x800000
32348#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT 0x17
32349#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK 0x1000000
32350#define PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT 0x18
32351#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK 0x2000000
32352#define PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT 0x19
32353#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK 0x4000000
32354#define PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT 0x1a
32355#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK 0x7
32356#define PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT 0x0
32357#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK 0x38
32358#define PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT 0x3
32359#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK 0x1c0
32360#define PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT 0x6
32361#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK 0x200
32362#define PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT 0x9
32363#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK 0x400
32364#define PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT 0xa
32365#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK 0x10000
32366#define PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT 0x10
32367#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK 0x60000
32368#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT 0x11
32369#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK 0x180000
32370#define PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT 0x13
32371#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK 0xe00000
32372#define PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT 0x15
32373#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK 0x1000000
32374#define PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT 0x18
32375#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK 0x6000000
32376#define PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT 0x19
32377#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK 0x8000000
32378#define PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT 0x1b
32379#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK 0x1
32380#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT 0x0
32381#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK 0x2
32382#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT 0x1
32383#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK 0x4
32384#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT 0x2
32385#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK 0x8
32386#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT 0x3
32387#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK 0x10
32388#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT 0x4
32389#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK 0x20
32390#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT 0x5
32391#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK 0x40
32392#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT 0x6
32393#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK 0x80
32394#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT 0x7
32395#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK 0x10000
32396#define PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT 0x10
32397#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK 0x1
32398#define PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT 0x0
32399#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK 0x2
32400#define PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT 0x1
32401#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK 0x4
32402#define PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT 0x2
32403#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK 0x8
32404#define PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT 0x3
32405#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK 0x10
32406#define PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT 0x4
32407#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK 0x20
32408#define PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT 0x5
32409#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK 0x40
32410#define PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT 0x6
32411#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK 0x80
32412#define PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT 0x7
32413#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK 0x100
32414#define PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT 0x8
32415#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK 0x200
32416#define PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT 0x9
32417#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK 0x400
32418#define PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT 0xa
32419#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK 0x800
32420#define PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT 0xb
32421#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK 0x10000
32422#define PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT 0x10
32423#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK 0x20000
32424#define PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT 0x11
32425#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK 0x100000
32426#define PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT 0x14
32427#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK 0x1
32428#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT 0x0
32429#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK 0x2
32430#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT 0x1
32431#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK 0x4
32432#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT 0x2
32433#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK 0x8
32434#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT 0x3
32435#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK 0x10
32436#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT 0x4
32437#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK 0x20
32438#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT 0x5
32439#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK 0x40
32440#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT 0x6
32441#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK 0x80
32442#define PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT 0x7
32443#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK 0x100
32444#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT 0x8
32445#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK 0x200
32446#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT 0x9
32447#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK 0x400
32448#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT 0xa
32449#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK 0x800
32450#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT 0xb
32451#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK 0x1000
32452#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT 0xc
32453#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK 0x2000
32454#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT 0xd
32455#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK 0x4000
32456#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT 0xe
32457#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK 0x8000
32458#define PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT 0xf
32459#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK 0x10000
32460#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT 0x10
32461#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK 0x20000
32462#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT 0x11
32463#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK 0x40000
32464#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT 0x12
32465#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK 0x80000
32466#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT 0x13
32467#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK 0x100000
32468#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT 0x14
32469#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK 0x200000
32470#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT 0x15
32471#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK 0x400000
32472#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT 0x16
32473#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK 0x800000
32474#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT 0x17
32475#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK 0x1000000
32476#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT 0x18
32477#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK 0x2000000
32478#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT 0x19
32479#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK 0x4000000
32480#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT 0x1a
32481#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK 0x8000000
32482#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT 0x1b
32483#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK 0x10000000
32484#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT 0x1c
32485#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK 0x20000000
32486#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT 0x1d
32487#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK 0x40000000
32488#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT 0x1e
32489#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK 0x80000000
32490#define PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT 0x1f
32491#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK 0x3
32492#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT 0x0
32493#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK 0xc
32494#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT 0x2
32495#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK 0x10
32496#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT 0x4
32497#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK 0x60
32498#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT 0x5
32499#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK 0x80
32500#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT 0x7
32501#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK 0x100
32502#define PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT 0x8
32503#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK 0x200
32504#define PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT 0x9
32505#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK 0x1
32506#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT 0x0
32507#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK 0x2
32508#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT 0x1
32509#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK 0x4
32510#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT 0x2
32511#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK 0x38
32512#define PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT 0x3
32513#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK 0x40
32514#define PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT 0x6
32515#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK 0x180
32516#define PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT 0x7
32517#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK 0x200
32518#define PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT 0x9
32519#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK 0x10000
32520#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT 0x10
32521#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK 0x20000
32522#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT 0x11
32523#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK 0x40000
32524#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT 0x12
32525#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK 0x80000
32526#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT 0x13
32527#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK 0x100000
32528#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT 0x14
32529#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK 0x200000
32530#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT 0x15
32531#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK 0x400000
32532#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT 0x16
32533#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK 0x800000
32534#define PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT 0x17
32535#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK 0x1
32536#define PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT 0x0
32537#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK 0x2
32538#define PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT 0x1
32539#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK 0x4
32540#define PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT 0x2
32541#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK 0x8
32542#define PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT 0x3
32543#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK 0x10
32544#define PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT 0x4
32545#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK 0x20
32546#define PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT 0x5
32547#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK 0x40
32548#define PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT 0x6
32549#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK 0x80
32550#define PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT 0x7
32551#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK 0x100
32552#define PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT 0x8
32553#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK 0x200
32554#define PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT 0x9
32555#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK 0x400
32556#define PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT 0xa
32557#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK 0x800
32558#define PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT 0xb
32559#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK 0x1000
32560#define PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT 0xc
32561#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK 0x2000
32562#define PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT 0xd
32563#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK 0x4000
32564#define PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT 0xe
32565#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK 0x8000
32566#define PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT 0xf
32567#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK 0x10000
32568#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT 0x10
32569#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK 0x20000
32570#define PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT 0x11
32571#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK 0x7
32572#define PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT 0x0
32573#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK 0x18
32574#define PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT 0x3
32575#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK 0x60
32576#define PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT 0x5
32577#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK 0x80
32578#define PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT 0x7
32579#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK 0x700
32580#define PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT 0x8
32581#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK 0x1800
32582#define PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT 0xb
32583#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK 0xe000
32584#define PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT 0xd
32585#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK 0x30000
32586#define PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT 0x10
32587#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK 0x40000
32588#define PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT 0x12
32589#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK 0x80000
32590#define PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT 0x13
32591#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK 0x100000
32592#define PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT 0x14
32593#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK 0x200000
32594#define PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT 0x15
32595#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK 0x400000
32596#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT 0x16
32597#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK 0x800000
32598#define PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT 0x17
32599#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK 0x3000000
32600#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT 0x18
32601#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK 0xfc000000
32602#define PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT 0x1a
32603#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK 0x1
32604#define PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT 0x0
32605#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK 0x2
32606#define PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT 0x1
32607#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK 0x4
32608#define PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT 0x2
32609#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK 0x8
32610#define PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT 0x3
32611#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK 0x10
32612#define PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT 0x4
32613#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK 0x20
32614#define PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT 0x5
32615#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK 0x40
32616#define PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT 0x6
32617#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK 0x80
32618#define PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT 0x7
32619#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK 0x100
32620#define PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT 0x8
32621#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK 0x200
32622#define PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT 0x9
32623#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK 0x400
32624#define PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT 0xa
32625#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK 0x800
32626#define PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT 0xb
32627#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK 0x1000
32628#define PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT 0xc
32629#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK 0x2000
32630#define PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT 0xd
32631#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK 0x4000
32632#define PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT 0xe
32633#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK 0x8000
32634#define PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT 0xf
32635#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK 0x10000
32636#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT 0x10
32637#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK 0x20000
32638#define PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT 0x11
32639#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK 0x7
32640#define PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT 0x0
32641#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK 0x18
32642#define PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT 0x3
32643#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK 0x60
32644#define PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT 0x5
32645#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK 0x80
32646#define PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT 0x7
32647#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK 0x700
32648#define PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT 0x8
32649#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK 0x1800
32650#define PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT 0xb
32651#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK 0xe000
32652#define PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT 0xd
32653#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK 0x30000
32654#define PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT 0x10
32655#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK 0x40000
32656#define PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT 0x12
32657#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK 0x80000
32658#define PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT 0x13
32659#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK 0x100000
32660#define PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT 0x14
32661#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK 0x200000
32662#define PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT 0x15
32663#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK 0x400000
32664#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT 0x16
32665#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK 0x800000
32666#define PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT 0x17
32667#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK 0x3000000
32668#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT 0x18
32669#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK 0xfc000000
32670#define PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT 0x1a
32671#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK 0x1
32672#define PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT 0x0
32673#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK 0x2
32674#define PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT 0x1
32675#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK 0x4
32676#define PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT 0x2
32677#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK 0x8
32678#define PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT 0x3
32679#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK 0x10
32680#define PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT 0x4
32681#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK 0x20
32682#define PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT 0x5
32683#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK 0x40
32684#define PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT 0x6
32685#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK 0x80
32686#define PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT 0x7
32687#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK 0x100
32688#define PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT 0x8
32689#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK 0x200
32690#define PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT 0x9
32691#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK 0x400
32692#define PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT 0xa
32693#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK 0x800
32694#define PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT 0xb
32695#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK 0x1000
32696#define PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT 0xc
32697#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK 0x2000
32698#define PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT 0xd
32699#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK 0x4000
32700#define PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT 0xe
32701#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK 0x8000
32702#define PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT 0xf
32703#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK 0x10000
32704#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT 0x10
32705#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK 0x20000
32706#define PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT 0x11
32707#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK 0x7
32708#define PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT 0x0
32709#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK 0x18
32710#define PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT 0x3
32711#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK 0x60
32712#define PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT 0x5
32713#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK 0x80
32714#define PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT 0x7
32715#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK 0x700
32716#define PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT 0x8
32717#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK 0x1800
32718#define PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT 0xb
32719#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK 0xe000
32720#define PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT 0xd
32721#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK 0x30000
32722#define PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT 0x10
32723#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK 0x40000
32724#define PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT 0x12
32725#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK 0x80000
32726#define PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT 0x13
32727#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK 0x100000
32728#define PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT 0x14
32729#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK 0x200000
32730#define PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT 0x15
32731#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK 0x400000
32732#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT 0x16
32733#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK 0x800000
32734#define PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT 0x17
32735#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK 0x3000000
32736#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT 0x18
32737#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK 0xfc000000
32738#define PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT 0x1a
32739#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK 0x1
32740#define PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT 0x0
32741#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK 0x2
32742#define PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT 0x1
32743#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK 0x4
32744#define PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT 0x2
32745#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK 0x8
32746#define PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT 0x3
32747#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK 0x10
32748#define PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT 0x4
32749#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK 0x20
32750#define PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT 0x5
32751#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK 0x40
32752#define PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT 0x6
32753#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK 0x80
32754#define PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT 0x7
32755#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK 0x100
32756#define PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT 0x8
32757#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK 0x200
32758#define PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT 0x9
32759#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK 0x400
32760#define PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT 0xa
32761#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK 0x800
32762#define PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT 0xb
32763#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK 0x1000
32764#define PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT 0xc
32765#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK 0x2000
32766#define PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT 0xd
32767#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK 0x4000
32768#define PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT 0xe
32769#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK 0x8000
32770#define PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT 0xf
32771#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK 0x10000
32772#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT 0x10
32773#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK 0x20000
32774#define PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT 0x11
32775#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK 0x7
32776#define PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT 0x0
32777#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK 0x18
32778#define PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT 0x3
32779#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK 0x60
32780#define PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT 0x5
32781#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK 0x80
32782#define PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT 0x7
32783#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK 0x700
32784#define PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT 0x8
32785#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK 0x1800
32786#define PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT 0xb
32787#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK 0xe000
32788#define PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT 0xd
32789#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK 0x30000
32790#define PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT 0x10
32791#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK 0x40000
32792#define PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT 0x12
32793#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK 0x80000
32794#define PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT 0x13
32795#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK 0x100000
32796#define PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT 0x14
32797#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK 0x200000
32798#define PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT 0x15
32799#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK 0x400000
32800#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT 0x16
32801#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK 0x800000
32802#define PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT 0x17
32803#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK 0x3000000
32804#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT 0x18
32805#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK 0xfc000000
32806#define PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT 0x1a
32807#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK 0x1
32808#define PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT 0x0
32809#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK 0x2
32810#define PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT 0x1
32811#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK 0x4
32812#define PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT 0x2
32813#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK 0x8
32814#define PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT 0x3
32815#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK 0x10
32816#define PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT 0x4
32817#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK 0x20
32818#define PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT 0x5
32819#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK 0x40
32820#define PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT 0x6
32821#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK 0x80
32822#define PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT 0x7
32823#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK 0x100
32824#define PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT 0x8
32825#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK 0x200
32826#define PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT 0x9
32827#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK 0x400
32828#define PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT 0xa
32829#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK 0x800
32830#define PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT 0xb
32831#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK 0x1000
32832#define PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT 0xc
32833#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK 0x2000
32834#define PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT 0xd
32835#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK 0x4000
32836#define PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT 0xe
32837#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK 0x8000
32838#define PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT 0xf
32839#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK 0x10000
32840#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT 0x10
32841#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK 0x20000
32842#define PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT 0x11
32843#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK 0x7
32844#define PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT 0x0
32845#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK 0x18
32846#define PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT 0x3
32847#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK 0x60
32848#define PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT 0x5
32849#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK 0x80
32850#define PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT 0x7
32851#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK 0x700
32852#define PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT 0x8
32853#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK 0x1800
32854#define PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT 0xb
32855#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK 0xe000
32856#define PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT 0xd
32857#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK 0x30000
32858#define PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT 0x10
32859#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK 0x40000
32860#define PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT 0x12
32861#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK 0x80000
32862#define PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT 0x13
32863#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK 0x100000
32864#define PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT 0x14
32865#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK 0x200000
32866#define PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT 0x15
32867#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK 0x400000
32868#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT 0x16
32869#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK 0x800000
32870#define PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT 0x17
32871#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK 0x3000000
32872#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT 0x18
32873#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK 0xfc000000
32874#define PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT 0x1a
32875#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK 0x1
32876#define PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT 0x0
32877#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK 0x2
32878#define PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT 0x1
32879#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK 0x4
32880#define PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT 0x2
32881#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK 0x8
32882#define PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT 0x3
32883#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK 0x10
32884#define PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT 0x4
32885#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK 0x20
32886#define PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT 0x5
32887#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK 0x40
32888#define PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT 0x6
32889#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK 0x80
32890#define PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT 0x7
32891#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK 0x100
32892#define PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT 0x8
32893#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK 0x200
32894#define PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT 0x9
32895#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK 0x400
32896#define PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT 0xa
32897#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK 0x800
32898#define PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT 0xb
32899#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK 0x1000
32900#define PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT 0xc
32901#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK 0x2000
32902#define PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT 0xd
32903#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK 0x4000
32904#define PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT 0xe
32905#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK 0x8000
32906#define PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT 0xf
32907#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK 0x10000
32908#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT 0x10
32909#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK 0x20000
32910#define PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT 0x11
32911#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK 0x7
32912#define PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT 0x0
32913#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK 0x18
32914#define PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT 0x3
32915#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK 0x60
32916#define PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT 0x5
32917#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK 0x80
32918#define PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT 0x7
32919#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK 0x700
32920#define PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT 0x8
32921#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK 0x1800
32922#define PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT 0xb
32923#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK 0xe000
32924#define PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT 0xd
32925#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK 0x30000
32926#define PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT 0x10
32927#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK 0x40000
32928#define PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT 0x12
32929#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK 0x80000
32930#define PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT 0x13
32931#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK 0x100000
32932#define PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT 0x14
32933#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK 0x200000
32934#define PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT 0x15
32935#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK 0x400000
32936#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT 0x16
32937#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK 0x800000
32938#define PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT 0x17
32939#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK 0x3000000
32940#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT 0x18
32941#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK 0xfc000000
32942#define PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT 0x1a
32943#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK 0x1
32944#define PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT 0x0
32945#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK 0x2
32946#define PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT 0x1
32947#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK 0x4
32948#define PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT 0x2
32949#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK 0x8
32950#define PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT 0x3
32951#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK 0x10
32952#define PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT 0x4
32953#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK 0x20
32954#define PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT 0x5
32955#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK 0x40
32956#define PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT 0x6
32957#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK 0x80
32958#define PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT 0x7
32959#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK 0x100
32960#define PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT 0x8
32961#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK 0x200
32962#define PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT 0x9
32963#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK 0x400
32964#define PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT 0xa
32965#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK 0x800
32966#define PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT 0xb
32967#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK 0x1000
32968#define PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT 0xc
32969#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK 0x2000
32970#define PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT 0xd
32971#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK 0x4000
32972#define PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT 0xe
32973#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK 0x8000
32974#define PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT 0xf
32975#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK 0x10000
32976#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT 0x10
32977#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK 0x20000
32978#define PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT 0x11
32979#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK 0x7
32980#define PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT 0x0
32981#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK 0x18
32982#define PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT 0x3
32983#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK 0x60
32984#define PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT 0x5
32985#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK 0x80
32986#define PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT 0x7
32987#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK 0x700
32988#define PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT 0x8
32989#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK 0x1800
32990#define PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT 0xb
32991#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK 0xe000
32992#define PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT 0xd
32993#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK 0x30000
32994#define PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT 0x10
32995#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK 0x40000
32996#define PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT 0x12
32997#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK 0x80000
32998#define PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT 0x13
32999#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK 0x100000
33000#define PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT 0x14
33001#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK 0x200000
33002#define PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT 0x15
33003#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK 0x400000
33004#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT 0x16
33005#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK 0x800000
33006#define PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT 0x17
33007#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK 0x3000000
33008#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT 0x18
33009#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK 0xfc000000
33010#define PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT 0x1a
33011#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK 0x1
33012#define PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT 0x0
33013#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK 0x2
33014#define PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT 0x1
33015#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK 0x4
33016#define PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT 0x2
33017#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK 0x8
33018#define PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT 0x3
33019#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK 0x10
33020#define PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT 0x4
33021#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK 0x20
33022#define PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT 0x5
33023#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK 0x40
33024#define PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT 0x6
33025#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK 0x80
33026#define PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT 0x7
33027#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK 0x100
33028#define PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT 0x8
33029#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK 0x200
33030#define PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT 0x9
33031#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK 0x400
33032#define PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT 0xa
33033#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK 0x800
33034#define PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT 0xb
33035#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK 0x1000
33036#define PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT 0xc
33037#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK 0x2000
33038#define PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT 0xd
33039#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK 0x4000
33040#define PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT 0xe
33041#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK 0x8000
33042#define PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT 0xf
33043#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK 0x10000
33044#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT 0x10
33045#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK 0x20000
33046#define PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT 0x11
33047#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK 0x7
33048#define PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT 0x0
33049#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK 0x18
33050#define PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT 0x3
33051#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK 0x60
33052#define PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT 0x5
33053#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK 0x80
33054#define PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT 0x7
33055#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK 0x700
33056#define PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT 0x8
33057#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK 0x1800
33058#define PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT 0xb
33059#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK 0xe000
33060#define PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT 0xd
33061#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK 0x30000
33062#define PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT 0x10
33063#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK 0x40000
33064#define PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT 0x12
33065#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK 0x80000
33066#define PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT 0x13
33067#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK 0x100000
33068#define PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT 0x14
33069#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK 0x200000
33070#define PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT 0x15
33071#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK 0x400000
33072#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT 0x16
33073#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK 0x800000
33074#define PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT 0x17
33075#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK 0x3000000
33076#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT 0x18
33077#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK 0xfc000000
33078#define PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT 0x1a
33079
33080#endif /* BIF_5_1_SH_MASK_H */
33081

source code of linux/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h