linux/linux/drivers/gpu/drm/amd/include/asic

../
dce_10_0_d.h
dce_10_0_enum.h ArrayMode BUF_DATA_FORMAT BUF_NUM_FORMAT BankHeight BankInterleaveSize BankSwapBytes BankTiling BankWidth BankWidthHeight COL_MAN_DENORM_CLAMP_CONTROL COL_MAN_DISABLE_MULTIPLE_UPDATE COL_MAN_GAMMA_CORR_CONTROL COL_MAN_INPUTCSC_CONVERT COL_MAN_INPUTCSC_MODE COL_MAN_INPUTCSC_TYPE COL_MAN_OUTPUT_CSC_MODE COL_MAN_PRESCALE_MODE COL_MAN_UPDATE_LOCK CmaskMode ColorArray ColorFormat ColorTransform CompareRef DCIOCHIP_AUXSLAVE_PAD_MODE DCIOCHIP_DVO_VREFPON DCIOCHIP_DVO_VREFSEL DCIOCHIP_ENABLE_2BIT DCIOCHIP_ENABLE_4BIT DCIOCHIP_ENABLE_5BIT DCIOCHIP_GPIO_I2C_DRIVE DCIOCHIP_GPIO_I2C_EN DCIOCHIP_GPIO_I2C_MASK DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_MASK_2BIT DCIOCHIP_MASK_4BIT DCIOCHIP_MASK_5BIT DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT DCIO_BL_PWM_CNTL_BL_PWM_EN DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN DCIO_BL_PWM_GRP1_REG_LOCK DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS DCIO_DACA_SOFT_RESET DCIO_DBG_OUT_12BIT_SEL DCIO_DBG_OUT_PIN_SEL DCIO_DCO_DCFE_EXT_VSYNC_MUX DCIO_DCO_EXT_VSYNC_MASK DCIO_DCRXPHY_SOFT_RESET DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPIO_MACRO_DEBUG DCIO_DC_GPIO_VIP_DEBUG DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS DCIO_DC_PAD_EXTERN_SIG_SEL DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DPHY_LANE_SEL DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL0_GLOBAL_UNLOCK_SEL DCIO_GSL0_TIMING_SYNC_SEL DCIO_GSL1_GLOBAL_UNLOCK_SEL DCIO_GSL1_TIMING_SYNC_SEL DCIO_GSL2_GLOBAL_UNLOCK_SEL DCIO_GSL2_TIMING_SYNC_SEL DCIO_GSL_SEL DCIO_GSL_VSYNC_SEL DCIO_IMPCAL_STEP_DELAY DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION DebugBlockId DebugBlockId_BY16 DebugBlockId_BY2 DebugBlockId_BY4 DebugBlockId_BY8 DebugBlockId_OLD DepthArray DepthFormat ENUM_NUM_SIMD_PER_CU GATCL1RequestType GroupInterleave IMG_DATA_FORMAT IMG_NUM_FORMAT MEM_PWR_DIS_CTRL MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 MTYPE MacroTileAspect MicroTileMode MultiGPUTileSize NonDispTilingOrder NumBanks NumGPUs NumLowerPipes NumPipes NumShaderEngines PERFMON_COUNTER_MODE PERFMON_SPM_MODE PipeConfig PipeInterleaveSize PipeTiling QuadExportFormat QuadExportFormatOld ReadSize RowSize RowTiling SampleSplit SampleSplitBytes ShaderEngineTileSize StencilFormat SurfaceArray SurfaceEndian SurfaceFormat SurfaceTiling TCC_CACHE_POLICIES TileSplit TileType ZFormat
dce_10_0_sh_mask.h
dce_11_0_d.h
dce_11_0_enum.h ABM_SOFT_RESET AFMT_AUDIO_CRC_CONTROL_CH_SEL AFMT_AUDIO_CRC_CONTROL_CONT AFMT_AUDIO_CRC_CONTROL_SOURCE AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS AFMT_AUDIO_SRC_CONTROL_SELECT AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE AFMT_INTERRUPT_STATUS_CHG_MASK AFMT_RAMP_CONTROL0_SIGN AUDIO_LAYOUT_SELECT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE AZ_CORB_SIZE AZ_GLOBAL_CAPABILITIES AZ_LATENCY_COUNTER_CONTROL AZ_RIRB_SIZE AZ_RIRB_WRITE_POINTER_RESET AZ_STATE_CHANGE_STATUS ArrayMode BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN BLNDV_CONTROL2_PTI_ENABLE BLNDV_CONTROL_BLND_ALPHA_MODE BLNDV_CONTROL_BLND_FEEDTHROUGH_EN BLNDV_CONTROL_BLND_MODE BLNDV_CONTROL_BLND_MULTIPLIED_MODE BLNDV_CONTROL_BLND_STEREO_POLARITY BLNDV_CONTROL_BLND_STEREO_TYPE BLNDV_DEBUG_BLND_CNV_MUX_SELECT BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE BLNDV_SM_CONTROL2_SM_MODE BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN BLND_CONTROL2_PTI_ENABLE BLND_CONTROL_BLND_ALPHA_MODE BLND_CONTROL_BLND_FEEDTHROUGH_EN BLND_CONTROL_BLND_MODE BLND_CONTROL_BLND_MULTIPLIED_MODE BLND_CONTROL_BLND_STEREO_POLARITY BLND_CONTROL_BLND_STEREO_TYPE BLND_DEBUG_BLND_CNV_MUX_SELECT BLND_SM_CONTROL2_SM_FIELD_ALTERNATE BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL BLND_SM_CONTROL2_SM_FRAME_ALTERNATE BLND_SM_CONTROL2_SM_MODE BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE BUF_DATA_FORMAT BUF_NUM_FORMAT BankHeight BankInterleaveSize BankSwapBytes BankTiling BankWidth BankWidthHeight CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY COL_MAN_DENORM_CLAMP_CONTROL COL_MAN_DISABLE_MULTIPLE_UPDATE COL_MAN_GAMMA_CORR_CONTROL COL_MAN_GLOBAL_PASSTHROUGH_ENABLE COL_MAN_INPUTCSC_CONVERT COL_MAN_INPUTCSC_MODE COL_MAN_INPUTCSC_TYPE COL_MAN_INPUT_GAMMA_MODE COL_MAN_OUTPUT_CSC_MODE COL_MAN_PRESCALE_MODE COL_MAN_UPDATE_LOCK CORB_READ_POINTER_RESET CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY CRTC_CONTROL_CRTC_MASTER_EN CRTC_CONTROL_CRTC_SOF_PULL_EN CRTC_CONTROL_CRTC_START_POINT_CNTL CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN CRTC_CRC_CNTL_CRTC_CRC_CONT_EN CRTC_CRC_CNTL_CRTC_CRC_EN CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL CRTC_HORZ_REPETITION_COUNT CRTC_H_SYNC_A_POL CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE CRTC_STEREO_CONTROL_CRTC_STEREO_EN CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR CRTC_V_SYNC_A_POL CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR CmaskMode ColorArray ColorFormat ColorTransform CompareRef DACA_SOFT_RESET DAC_MUX_SELECT DB_CLK_SOFT_RESET DCIOCHIP_AUXSLAVE_PAD_MODE DCIOCHIP_DVO_VREFPON DCIOCHIP_DVO_VREFSEL DCIOCHIP_ENABLE_2BIT DCIOCHIP_ENABLE_4BIT DCIOCHIP_ENABLE_5BIT DCIOCHIP_GPIO_I2C_DRIVE DCIOCHIP_GPIO_I2C_EN DCIOCHIP_GPIO_I2C_MASK DCIOCHIP_GPIO_MASK_EN DCIOCHIP_HPD_SEL DCIOCHIP_INVERT DCIOCHIP_MASK DCIOCHIP_MASK_2BIT DCIOCHIP_MASK_4BIT DCIOCHIP_MASK_5BIT DCIOCHIP_PAD_MODE DCIOCHIP_PD_EN DCIOCHIP_REF_27_SRC_SEL DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT DCIO_BL_PWM_CNTL_BL_PWM_EN DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN DCIO_BL_PWM_GRP1_REG_LOCK DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS DCIO_DACA_SOFT_RESET DCIO_DBG_OUT_12BIT_SEL DCIO_DBG_OUT_PIN_SEL DCIO_DCO_DCFE_EXT_VSYNC_MUX DCIO_DCO_EXT_VSYNC_MASK DCIO_DCRXPHY_SOFT_RESET DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN DCIO_DC_GENERICA_SEL DCIO_DC_GENERICB_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE DCIO_DC_GPIO_MACRO_DEBUG DCIO_DC_GPIO_VIP_DEBUG DCIO_DC_GPU_TIMER_READ_SELECT DCIO_DC_GPU_TIMER_START_POSITION DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS DCIO_DC_PAD_EXTERN_SIG_SEL DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL DCIO_DPHY_LANE_SEL DCIO_DSYNC_SOFT_RESET DCIO_GENLK_CLK_GSL_MASK DCIO_GENLK_VSYNC_GSL_MASK DCIO_GSL0_GLOBAL_UNLOCK_SEL DCIO_GSL0_TIMING_SYNC_SEL DCIO_GSL1_GLOBAL_UNLOCK_SEL DCIO_GSL1_TIMING_SYNC_SEL DCIO_GSL2_GLOBAL_UNLOCK_SEL DCIO_GSL2_TIMING_SYNC_SEL DCIO_GSL_SEL DCIO_GSL_VSYNC_SEL DCIO_IMPCAL_STEP_DELAY DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN DCIO_SWAPLOCK_A_GSL_MASK DCIO_SWAPLOCK_B_GSL_MASK DCIO_UNIPHY_CHANNEL_XBAR_SOURCE DCIO_UNIPHY_IMPCAL_SEL DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION DCO_DBG_BLOCK_SEL DCO_DBG_CLOCK_SEL DCP_ALPHA_ROUND_TRUNC_MODE DCP_CRC_ENABLE DCP_CRC_LINE_SEL DCP_CRC_SOURCE_SEL DCP_CUR2_INV_TRANS_CLAMP DCP_CURSOR2_2X_MAGNIFY DCP_CURSOR2_DEGAMMA_MODE DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE DCP_CURSOR2_EN DCP_CURSOR2_FORCE_MC_ON DCP_CURSOR2_MODE DCP_CURSOR2_STEREO_EN DCP_CURSOR2_STEREO_OFFSET_YNX DCP_CURSOR2_UPDATE_LOCK DCP_CURSOR2_UPDATE_PENDING DCP_CURSOR2_UPDATE_STEREO_MODE DCP_CURSOR2_UPDATE_TAKEN DCP_CURSOR2_URGENT_CONTROL DCP_CURSOR_2X_MAGNIFY DCP_CURSOR_ALPHA_BLND_ENA DCP_CURSOR_DEGAMMA_MODE DCP_CURSOR_DISABLE_MULTIPLE_UPDATE DCP_CURSOR_EN DCP_CURSOR_FORCE_MC_ON DCP_CURSOR_MODE DCP_CURSOR_STEREO_EN DCP_CURSOR_STEREO_OFFSET_YNX DCP_CURSOR_UPDATE_LOCK DCP_CURSOR_UPDATE_PENDING DCP_CURSOR_UPDATE_STEREO_MODE DCP_CURSOR_UPDATE_TAKEN DCP_CURSOR_URGENT_CONTROL DCP_CUR_INV_TRANS_CLAMP DCP_CUR_REQUEST_FILTER_DIS DCP_DC_LUT_AUTOFILL DCP_DC_LUT_AUTOFILL_DONE DCP_DC_LUT_DATA_B_FLOAT_POINT_EN DCP_DC_LUT_DATA_B_FORMAT DCP_DC_LUT_DATA_B_SIGNED_EN DCP_DC_LUT_DATA_G_FLOAT_POINT_EN DCP_DC_LUT_DATA_G_FORMAT DCP_DC_LUT_DATA_G_SIGNED_EN DCP_DC_LUT_DATA_R_FLOAT_POINT_EN DCP_DC_LUT_DATA_R_FORMAT DCP_DC_LUT_DATA_R_SIGNED_EN DCP_DC_LUT_INC_B DCP_DC_LUT_INC_G DCP_DC_LUT_INC_R DCP_DC_LUT_RW_MODE DCP_DC_LUT_VGA_ACCESS_ENABLE DCP_DENORM_14BIT_OUT DCP_DENORM_MODE DCP_FRAME_RANDOM_ENABLE DCP_GRPH_ADDRESS_TRANSLATION_ENABLE DCP_GRPH_ALPHA_CROSSBAR DCP_GRPH_ARRAY_MODE DCP_GRPH_BANK_HEIGHT DCP_GRPH_BANK_WIDTH DCP_GRPH_BLUE_CROSSBAR DCP_GRPH_COLOR_EXPANSION_MODE DCP_GRPH_DEGAMMA_MODE DCP_GRPH_DEPTH DCP_GRPH_DFQ_MIN_FREE_ENTRIES DCP_GRPH_DFQ_RESET DCP_GRPH_DFQ_RESET_ACK DCP_GRPH_DFQ_SIZE DCP_GRPH_ENABLE DCP_GRPH_ENDIAN_SWAP DCP_GRPH_FLIP_RATE DCP_GRPH_FLIP_RATE_ENABLE DCP_GRPH_FORMAT DCP_GRPH_GAMUT_REMAP_MODE DCP_GRPH_GREEN_CROSSBAR DCP_GRPH_INPUT_GAMMA_MODE DCP_GRPH_KEYER_ALPHA_SEL DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN DCP_GRPH_LUT_10BIT_BYPASS_EN DCP_GRPH_MACRO_TILE_ASPECT DCP_GRPH_MICRO_TILE_MODE DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_MODE_UPDATE_PENDING DCP_GRPH_MODE_UPDATE_TAKEN DCP_GRPH_NUM_BANKS DCP_GRPH_PFLIP_INT_CLEAR DCP_GRPH_PFLIP_INT_MASK DCP_GRPH_PFLIP_INT_TYPE DCP_GRPH_PRESCALE_BYPASS DCP_GRPH_PRESCALE_B_SIGN DCP_GRPH_PRESCALE_G_SIGN DCP_GRPH_PRESCALE_R_SIGN DCP_GRPH_PRESCALE_SELECT DCP_GRPH_PRIMARY_DFQ_ENABLE DCP_GRPH_PRIVILEGED_ACCESS_ENABLE DCP_GRPH_RED_CROSSBAR DCP_GRPH_REGAMMA_MODE DCP_GRPH_ROTATION_ANGLE DCP_GRPH_SECONDARY_DFQ_ENABLE DCP_GRPH_STEREOSYNC_FLIP_EN DCP_GRPH_STEREOSYNC_FLIP_MODE DCP_GRPH_STEREOSYNC_SELECT_DISABLE DCP_GRPH_SURFACE_COUNTER_EN DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN DCP_GRPH_SURFACE_UPDATE_PENDING DCP_GRPH_SURFACE_UPDATE_TAKEN DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE DCP_GRPH_TILE_SPLIT DCP_GRPH_UPDATE_LOCK DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK DCP_GRPH_XDMA_SUPER_AA_EN DCP_GSL0_EN DCP_GSL1_EN DCP_GSL2_EN DCP_GSL_DELAY_SURFACE_UPDATE_PENDING DCP_GSL_MASTER_EN DCP_GSL_SYNC_SOURCE DCP_GSL_XDMA_GROUP DCP_GSL_XDMA_GROUP_UNDERFLOW_EN DCP_HIGHPASS_RANDOM_ENABLE DCP_INPUT_CSC_GRPH_MODE DCP_KEY_MODE DCP_OUTPUT_CSC_GRPH_MODE DCP_OUT_ROUND_TRUNC_MODE DCP_RGB_RANDOM_ENABLE DCP_SPATIAL_DITHER_DEPTH DCP_SPATIAL_DITHER_EN DCP_SPATIAL_DITHER_MODE DCP_TEST_DEBUG_WRITE_EN DIGA_BE_SOFT_RESET DIGA_FE_SOFT_RESET DIGB_BE_SOFT_RESET DIGB_FE_SOFT_RESET DIGC_BE_SOFT_RESET DIGC_FE_SOFT_RESET DIGD_BE_SOFT_RESET DIGD_FE_SOFT_RESET DIGE_BE_SOFT_RESET DIGE_FE_SOFT_RESET DIGF_BE_SOFT_RESET DIGF_FE_SOFT_RESET DIGG_BE_SOFT_RESET DIGG_FE_SOFT_RESET DIGLPA_BE_SOFT_RESET DIGLPA_FE_SOFT_RESET DIGLPB_BE_SOFT_RESET DIGLPB_FE_SOFT_RESET DIG_BE_CNTL_HPD_SELECT DIG_BE_CNTL_MODE DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT DIG_FE_CNTL_SOURCE_SELECT DIG_FE_CNTL_STEREOSYNC_SELECT DIG_FIFO_ERROR_ACK DIG_FIFO_READ_CLOCK_SRC DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL DIG_OUTPUT_CRC_CNTL_LINK_SEL DIG_OUTPUT_CRC_DATA_SEL DIG_RANDOM_PATTERN_SEED_RAN_PAT DIG_TEST_PATTERN_EXTERNAL_RESET_EN DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN DIG_TEST_PATTERN_RANDOM_PATTERN_RESET DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE DOUT_I2C_ACK DOUT_I2C_ARBITRATION_ABORT_XFER DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO DOUT_I2C_ARBITRATION_SW_PRIORITY DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ DOUT_I2C_CONTROL_DBG_REF_SEL DOUT_I2C_CONTROL_DDC_SELECT DOUT_I2C_CONTROL_GO DOUT_I2C_CONTROL_SEND_RESET DOUT_I2C_CONTROL_SOFT_RESET DOUT_I2C_CONTROL_SW_STATUS_RESET DOUT_I2C_CONTROL_TRANSACTION_COUNT DOUT_I2C_DATA_INDEX_WRITE DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE DOUT_I2C_DDC_SPEED_THRESHOLD DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE DOUT_I2C_TRANSACTION_STOP_ON_NACK DPDBG_EN DPDBG_ERROR_DETECTION_MODE DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE DPDBG_INPUT_EN DPDBG_SOFT_RESET DPHY_8B10B_CUR_DISP DPHY_8B10B_RESET DPHY_ATEST_SEL_LANE0 DPHY_ATEST_SEL_LANE1 DPHY_ATEST_SEL_LANE2 DPHY_ATEST_SEL_LANE3 DPHY_BYPASS DPHY_CRC_CONT_EN DPHY_CRC_EN DPHY_CRC_FIELD DPHY_CRC_MST_PHASE_ERROR_ACK DPHY_CRC_SEL DPHY_LOAD_BS_COUNT_START DPHY_PRBS_EN DPHY_PRBS_SEL DPHY_RX_FAST_TRAINING_CAPABLE DPHY_SKEW_BYPASS DPHY_SW_FAST_TRAINING_START DPHY_TRAINING_PATTERN_SEL DP_AUX_ARB_CONTROL_ARB_PRIORITY DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ DP_AUX_CONTROL_HPD_SEL DP_AUX_CONTROL_TEST_MODE DP_AUX_DEFINITE_ERR_REACHED_ACK DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW DP_AUX_DPHY_RX_CONTROL_START_WINDOW DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN DP_AUX_DPHY_RX_DETECTION_THRESHOLD DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL DP_AUX_ERR_OCCURRED_ACK DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN DP_AUX_INT_ACK DP_AUX_LS_UPDATE_ACK DP_AUX_POTENTIAL_ERR_REACHED_ACK DP_AUX_RESET DP_AUX_RESET_DONE DP_AUX_SW_CONTROL_LS_READ_TRIG DP_AUX_SW_CONTROL_SW_GO DP_COMPONENT_DEPTH DP_DPHY_8B10B_EXT_DISP DP_DPHY_FAST_TRAINING_COMPLETE_ACK DP_DPHY_FAST_TRAINING_COMPLETE_MASK DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN DP_DPHY_HBR2_PATTERN_CONTROL_MODE DP_DYN_RANGE DP_EMBEDDED_PANEL_MODE DP_LINK_TRAINING_COMPLETE DP_MSA_MISC0_OVERRIDE_ENABLE DP_MSA_V_TIMING_OVERRIDE_EN DP_MSE_BLANK_CODE DP_MSE_LINK_LINE DP_MSE_OUTPUT_DPDBG_DATA DP_MSE_SAT_UPDATE_ACT DP_MSE_TIMESTAMP_MODE DP_MSE_ZERO_ENCODER DP_PIXEL_ENCODING DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE DP_SEC_ASP_PRIORITY DP_SEC_AUDIO_MUTE DP_SEC_COLLISION_ACK DP_SEC_GSP0_PRIORITY DP_SEC_GSP0_SEND DP_SEC_TIMESTAMP_MODE DP_STEER_OVERFLOW_ACK DP_STEER_OVERFLOW_MASK DP_TU_OVERFLOW_ACK DP_UDI_LANES DP_VID_ENHANCED_FRAME_MODE DP_VID_MSA_TOP_FIELD_MODE DP_VID_M_N_DOUBLE_BUFFER_MODE DP_VID_M_N_GEN_EN DP_VID_STREAM_DISABLE_ACK DP_VID_STREAM_DISABLE_MASK DP_VID_STREAM_DIS_DEFER DP_VID_TIMING_MODE DP_VID_VBID_FIELD_POL DP_YCBCR_RANGE DVO_SOFT_RESET DebugBlockId DebugBlockId_BY16 DebugBlockId_BY2 DebugBlockId_BY4 DebugBlockId_BY8 DepthArray DepthFormat ENUM_NUM_SIMD_PER_CU FMT0_SOFT_RESET FMT1_SOFT_RESET FMT2_SOFT_RESET FMT3_SOFT_RESET FMT4_SOFT_RESET FMT5_SOFT_RESET FMT_BIT_DEPTH_CONTROL_25FRC_SEL FMT_BIT_DEPTH_CONTROL_50FRC_SEL FMT_BIT_DEPTH_CONTROL_75FRC_SEL FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE FMT_CLAMP_CNTL_COLOR_FORMAT FMT_CONTROL_PIXEL_ENCODING FMT_CONTROL_SUBSAMPLING_MODE FMT_CONTROL_SUBSAMPLING_ORDER FMT_CRC_CNTL_CONT_EN FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT FMT_CRC_CNTL_INCLUDE_OVERSCAN FMT_CRC_CNTL_INTERLACE_MODE FMT_CRC_CNTL_ONLY_BLANKB FMT_CRC_CNTL_PSR_MODE_ENABLE FMT_DEBUG_CNTL_COLOR_SELECT FMT_DYNAMIC_EXP_MODE FMT_SPATIAL_DITHER_MODE FMT_STEREOSYNC_OVR_POL FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT GATCL1RequestType GENERICA_STEREOSYNC_SEL GENERICB_STEREOSYNC_SEL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED GENERIC_AZ_CONTROLLER_REGISTER_STATUS GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE GLOBAL_CONTROL_CONTROLLER_RESET GLOBAL_CONTROL_FLUSH_CONTROL GLOBAL_STATUS_FLUSH_STATUS GroupInterleave HDMI_ACR_AUDIO_PRIORITY HDMI_ACR_CONT HDMI_ACR_N_MULTIPLE HDMI_ACR_SELECT HDMI_ACR_SEND HDMI_ACR_SOURCE HDMI_AUDIO_DELAY_EN HDMI_AUDIO_INFO_CONT HDMI_AUDIO_INFO_SEND HDMI_AUDIO_SEND_MAX_PACKETS HDMI_AVI_INFO_CONT HDMI_AVI_INFO_SEND HDMI_CLOCK_CHANNEL_RATE HDMI_DEEP_COLOR_DEPTH HDMI_DEFAULT_PAHSE HDMI_ERROR_ACK HDMI_ERROR_MASK HDMI_GC_AVMUTE HDMI_GC_AVMUTE_CONT HDMI_GC_CONT HDMI_GC_SEND HDMI_GENERIC0_CONT HDMI_GENERIC0_SEND HDMI_GENERIC1_CONT HDMI_GENERIC1_SEND HDMI_GENERIC2_CONT HDMI_GENERIC2_SEND HDMI_GENERIC3_CONT HDMI_GENERIC3_SEND HDMI_ISRC_CONT HDMI_ISRC_SEND HDMI_KEEPOUT_MODE HDMI_MPEG_INFO_CONT HDMI_MPEG_INFO_SEND HDMI_NO_EXTRA_NULL_PACKET_FILLED HDMI_NULL_SEND HDMI_PACKET_GEN_VERSION HDMI_PACKING_PHASE_OVERRIDE HPD_INT_CONTROL_ACK HPD_INT_CONTROL_POLARITY HPD_INT_CONTROL_RX_INT_ACK I2S0_SPDIF0_SOFT_RESET I2S1_SOFT_RESET IMG_DATA_FORMAT IMG_NUM_FORMAT IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID LBV_DITHER_EN LBV_DOWNSCALE_PREFETCH_EN LBV_DYNAMIC_PIXEL_DEPTH LBV_INTERLEAVE_EN LBV_MEMORY_CONFIG LBV_PIXEL_DEPTH LBV_PIXEL_EXPAN_MODE LBV_PIXEL_REDUCE_MODE LBV_SYNC_DURATION LBV_SYNC_RESET_SEL2 LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK LB_DATA_FORMAT_ALPHA_EN LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH LB_DATA_FORMAT_INTERLEAVE_EN LB_DATA_FORMAT_PIXEL_DEPTH LB_DATA_FORMAT_PIXEL_EXPAN_MODE LB_DATA_FORMAT_PIXEL_REDUCE_MODE LB_DATA_FORMAT_REQUEST_MODE LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE LB_SYNC_RESET_SEL_LB_SYNC_DURATION LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN LB_VBLANK_STATUS_VBLANK_ACK LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE LB_VLINE2_START_END_VLINE2_INV LB_VLINE2_STATUS_VLINE2_ACK LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE LB_VLINE_START_END_VLINE_INV LB_VLINE_STATUS_VLINE_ACK LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE LVTMA_RANDOM_PATTERN_SEED_RAN_PAT LptNumBanks MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE MASTER_UPDATE_MODE_MASTER_UPDATE_MODE MEM_PWR_DIS_CTRL MEM_PWR_FORCE_CTRL MEM_PWR_FORCE_CTRL2 MEM_PWR_SEL_CTRL MEM_PWR_SEL_CTRL2 MTYPE MVP_SOFT_RESET MacroTileAspect MicroTileMode MultiGPUTileSize NonDispTilingOrder NumBanks NumGPUs NumLowerPipes NumPipes NumShaderEngines OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE PERFCOUNTER_ACTIVE PERFCOUNTER_CNT0_STATE PERFCOUNTER_CNT1_STATE PERFCOUNTER_CNT2_STATE PERFCOUNTER_CNT3_STATE PERFCOUNTER_CNT4_STATE PERFCOUNTER_CNT5_STATE PERFCOUNTER_CNT6_STATE PERFCOUNTER_CNT7_STATE PERFCOUNTER_CNTL_SEL PERFCOUNTER_CNTOFF_START_DIS PERFCOUNTER_COUNTED_VALUE_TYPE PERFCOUNTER_CVALUE_SEL PERFCOUNTER_HW_CNTL_SEL PERFCOUNTER_INC_MODE PERFCOUNTER_INT_EN PERFCOUNTER_INT_TYPE PERFCOUNTER_OFF_MASK PERFCOUNTER_RESTART_EN PERFCOUNTER_RUNEN_MODE PERFCOUNTER_STATE_SEL0 PERFCOUNTER_STATE_SEL1 PERFCOUNTER_STATE_SEL2 PERFCOUNTER_STATE_SEL3 PERFCOUNTER_STATE_SEL4 PERFCOUNTER_STATE_SEL5 PERFCOUNTER_STATE_SEL6 PERFCOUNTER_STATE_SEL7 PERFMON_CNTOFF_AND_OR PERFMON_CNTOFF_INT_EN PERFMON_CNTOFF_INT_TYPE PERFMON_COUNTER_MODE PERFMON_SPM_MODE PERFMON_STATE PM_ASSERT_RESET PipeConfig PipeInterleaveSize PipeTiling QuadExportFormat QuadExportFormatOld RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL ReadSize RowSize RowTiling SCLV_COEF_UPDATE_COMPLETE SCLV_INTERLACE_SOURCE SCLV_UPDATE_LOCK SCL_ALU_DISABLE SCL_BOUNDARY_MODE SCL_BYPASS_MODE SCL_COEF_UPDATE_COMPLETE SCL_C_RAM_FILTER_TYPE SCL_C_RAM_PHASE SCL_C_RAM_TAP_PAIR_IDX SCL_EARLY_EOL_MOD SCL_HF_SHARP_EN SCL_HF_SHARP_SCALE_FACTOR SCL_HOST_CONFLICT_MASK SCL_H_2TAP_HARDCODE_COEF_EN SCL_H_CALC_AUTO_RATIO_EN SCL_H_FILTER_PICK_NEAREST SCL_H_MANUAL_REPLICATE_FACTOR SCL_H_NUM_OF_TAPS SCL_MODE_SEL SCL_PSCL_EN SCL_SCL_MODE_CHANGE_MASK SCL_UPDATE_LOCK SCL_UPDATE_TAKEN SCL_VF_SHARP_EN SCL_VF_SHARP_SCALE_FACTOR SCL_V_2TAP_HARDCODE_COEF_EN SCL_V_CALC_AUTO_RATIO_EN SCL_V_FILTER_PICK_NEAREST SCL_V_MANUAL_REPLICATE_FACTOR SCL_V_NUM_OF_TAPS SPDIF1_SOFT_RESET STREAM_0_SYNCHRONIZATION STREAM_10_SYNCHRONIZATION STREAM_11_SYNCHRONIZATION STREAM_12_SYNCHRONIZATION STREAM_13_SYNCHRONIZATION STREAM_14_SYNCHRONIZATION STREAM_15_SYNCHRONIZATION STREAM_1_SYNCHRONIZATION STREAM_2_SYNCHRONIZATION STREAM_3_SYNCHRONIZATION STREAM_4_SYNCHRONIZATION STREAM_5_SYNCHRONIZATION STREAM_6_SYNCHRONIZATION STREAM_7_SYNCHRONIZATION STREAM_8_SYNCHRONIZATION STREAM_9_SYNCHRONIZATION SampleSplit SampleSplitBytes ShaderEngineTileSize StencilFormat SurfaceArray SurfaceEndian SurfaceFormat SurfaceTiling TCC_CACHE_POLICIES TMDS_COLOR_FORMAT TMDS_CTL0_DATA_DELAY TMDS_CTL0_DATA_INVERT TMDS_CTL0_DATA_MODULATION TMDS_CTL0_DATA_SEL TMDS_CTL0_PATTERN_OUT_EN TMDS_CTL1_DATA_DELAY TMDS_CTL1_DATA_INVERT TMDS_CTL1_DATA_MODULATION TMDS_CTL1_DATA_SEL TMDS_CTL1_PATTERN_OUT_EN TMDS_CTL2_DATA_DELAY TMDS_CTL2_DATA_INVERT TMDS_CTL2_DATA_MODULATION TMDS_CTL2_DATA_SEL TMDS_CTL2_PATTERN_OUT_EN TMDS_CTL3_DATA_DELAY TMDS_CTL3_DATA_INVERT TMDS_CTL3_DATA_MODULATION TMDS_CTL3_DATA_SEL TMDS_CTL3_PATTERN_OUT_EN TMDS_DATA_SYNCHRONIZATION_DSINTSEL TMDS_DVO_MUX_SELECT TMDS_PIXEL_ENCODING TMDS_REG_TEST_OUTPUTA_CNTLA TMDS_REG_TEST_OUTPUTB_CNTLB TMDS_STEREOSYNC_CTL_SEL_REG TMDS_SYNC_PHASE TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB TMDS_TRANSMITTER_CONTROL_IDSCKSELA TMDS_TRANSMITTER_CONTROL_IDSCKSELB TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS TMDS_TRANSMITTER_ENABLE_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK TileSplit TileType UNP_BUFFER_MODE UNP_CRC_LINE_SEL UNP_CRC_SOURCE_SEL UNP_GRPH_ADDRESS_TRANSLATION_ENABLE UNP_GRPH_BANK_HEIGHT UNP_GRPH_BANK_WIDTH UNP_GRPH_BLUE_CROSSBAR UNP_GRPH_COLOR_EXPANSION_MODE UNP_GRPH_DEPTH UNP_GRPH_EN UNP_GRPH_ENDIAN_SWAP UNP_GRPH_GREEN_CROSSBAR UNP_GRPH_MACRO_TILE_ASPECT UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_MODE_UPDATE_LOCKG UNP_GRPH_NUM_BANKS UNP_GRPH_PRIVILEGED_ACCESS_ENABLE UNP_GRPH_RED_CROSSBAR UNP_GRPH_STACK_INTERLACE_FLIP_EN UNP_GRPH_STACK_INTERLACE_FLIP_MODE UNP_GRPH_STEREOSYNC_FLIP_EN UNP_GRPH_STEREOSYNC_FLIP_MODE UNP_GRPH_STEREOSYNC_SELECT_DISABLE UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK UNP_GRPH_TILE_SPLIT UNP_PIXEL_DROP UNP_ROTATION_ANGLE UNP_VIDEO_FORMAT ZFormat
dce_11_0_sh_mask.h
dce_11_2_d.h
dce_11_2_sh_mask.h
dce_12_0_offset.h
dce_12_0_sh_mask.h
dce_6_0_d.h
dce_6_0_sh_mask.h
dce_8_0_d.h
dce_8_0_sh_mask.h