1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _gc_9_0_OFFSET_HEADER
22#define _gc_9_0_OFFSET_HEADER
23
24
25
26// addressBlock: gc_grbmdec
27// base address: 0x8000
28#define mmGRBM_CNTL 0x0000
29#define mmGRBM_CNTL_BASE_IDX 0
30#define mmGRBM_SKEW_CNTL 0x0001
31#define mmGRBM_SKEW_CNTL_BASE_IDX 0
32#define mmGRBM_STATUS2 0x0002
33#define mmGRBM_STATUS2_BASE_IDX 0
34#define mmGRBM_PWR_CNTL 0x0003
35#define mmGRBM_PWR_CNTL_BASE_IDX 0
36#define mmGRBM_STATUS 0x0004
37#define mmGRBM_STATUS_BASE_IDX 0
38#define mmGRBM_STATUS_SE0 0x0005
39#define mmGRBM_STATUS_SE0_BASE_IDX 0
40#define mmGRBM_STATUS_SE1 0x0006
41#define mmGRBM_STATUS_SE1_BASE_IDX 0
42#define mmGRBM_SOFT_RESET 0x0008
43#define mmGRBM_SOFT_RESET_BASE_IDX 0
44#define mmGRBM_CGTT_CLK_CNTL 0x000b
45#define mmGRBM_CGTT_CLK_CNTL_BASE_IDX 0
46#define mmGRBM_GFX_CLKEN_CNTL 0x000c
47#define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
48#define mmGRBM_WAIT_IDLE_CLOCKS 0x000d
49#define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
50#define mmGRBM_STATUS_SE2 0x000e
51#define mmGRBM_STATUS_SE2_BASE_IDX 0
52#define mmGRBM_STATUS_SE3 0x000f
53#define mmGRBM_STATUS_SE3_BASE_IDX 0
54#define mmGRBM_READ_ERROR 0x0016
55#define mmGRBM_READ_ERROR_BASE_IDX 0
56#define mmGRBM_READ_ERROR2 0x0017
57#define mmGRBM_READ_ERROR2_BASE_IDX 0
58#define mmGRBM_INT_CNTL 0x0018
59#define mmGRBM_INT_CNTL_BASE_IDX 0
60#define mmGRBM_TRAP_OP 0x0019
61#define mmGRBM_TRAP_OP_BASE_IDX 0
62#define mmGRBM_TRAP_ADDR 0x001a
63#define mmGRBM_TRAP_ADDR_BASE_IDX 0
64#define mmGRBM_TRAP_ADDR_MSK 0x001b
65#define mmGRBM_TRAP_ADDR_MSK_BASE_IDX 0
66#define mmGRBM_TRAP_WD 0x001c
67#define mmGRBM_TRAP_WD_BASE_IDX 0
68#define mmGRBM_TRAP_WD_MSK 0x001d
69#define mmGRBM_TRAP_WD_MSK_BASE_IDX 0
70#define mmGRBM_DSM_BYPASS 0x001e
71#define mmGRBM_DSM_BYPASS_BASE_IDX 0
72#define mmGRBM_WRITE_ERROR 0x001f
73#define mmGRBM_WRITE_ERROR_BASE_IDX 0
74#define mmGRBM_IOV_ERROR 0x0020
75#define mmGRBM_IOV_ERROR_BASE_IDX 0
76#define mmGRBM_CHIP_REVISION 0x0021
77#define mmGRBM_CHIP_REVISION_BASE_IDX 0
78#define mmGRBM_GFX_CNTL 0x0022
79#define mmGRBM_GFX_CNTL_BASE_IDX 0
80#define mmGRBM_RSMU_CFG 0x0023
81#define mmGRBM_RSMU_CFG_BASE_IDX 0
82#define mmGRBM_IH_CREDIT 0x0024
83#define mmGRBM_IH_CREDIT_BASE_IDX 0
84#define mmGRBM_PWR_CNTL2 0x0025
85#define mmGRBM_PWR_CNTL2_BASE_IDX 0
86#define mmGRBM_UTCL2_INVAL_RANGE_START 0x0026
87#define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
88#define mmGRBM_UTCL2_INVAL_RANGE_END 0x0027
89#define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
90#define mmGRBM_RSMU_READ_ERROR 0x0028
91#define mmGRBM_RSMU_READ_ERROR_BASE_IDX 0
92#define mmGRBM_CHICKEN_BITS 0x0029
93#define mmGRBM_CHICKEN_BITS_BASE_IDX 0
94#define mmGRBM_NOWHERE 0x003f
95#define mmGRBM_NOWHERE_BASE_IDX 0
96#define mmGRBM_SCRATCH_REG0 0x0040
97#define mmGRBM_SCRATCH_REG0_BASE_IDX 0
98#define mmGRBM_SCRATCH_REG1 0x0041
99#define mmGRBM_SCRATCH_REG1_BASE_IDX 0
100#define mmGRBM_SCRATCH_REG2 0x0042
101#define mmGRBM_SCRATCH_REG2_BASE_IDX 0
102#define mmGRBM_SCRATCH_REG3 0x0043
103#define mmGRBM_SCRATCH_REG3_BASE_IDX 0
104#define mmGRBM_SCRATCH_REG4 0x0044
105#define mmGRBM_SCRATCH_REG4_BASE_IDX 0
106#define mmGRBM_SCRATCH_REG5 0x0045
107#define mmGRBM_SCRATCH_REG5_BASE_IDX 0
108#define mmGRBM_SCRATCH_REG6 0x0046
109#define mmGRBM_SCRATCH_REG6_BASE_IDX 0
110#define mmGRBM_SCRATCH_REG7 0x0047
111#define mmGRBM_SCRATCH_REG7_BASE_IDX 0
112
113
114// addressBlock: gc_cpdec
115// base address: 0x8200
116#define mmCP_CPC_STATUS 0x0084
117#define mmCP_CPC_STATUS_BASE_IDX 0
118#define mmCP_CPC_BUSY_STAT 0x0085
119#define mmCP_CPC_BUSY_STAT_BASE_IDX 0
120#define mmCP_CPC_STALLED_STAT1 0x0086
121#define mmCP_CPC_STALLED_STAT1_BASE_IDX 0
122#define mmCP_CPF_STATUS 0x0087
123#define mmCP_CPF_STATUS_BASE_IDX 0
124#define mmCP_CPF_BUSY_STAT 0x0088
125#define mmCP_CPF_BUSY_STAT_BASE_IDX 0
126#define mmCP_CPF_STALLED_STAT1 0x0089
127#define mmCP_CPF_STALLED_STAT1_BASE_IDX 0
128#define mmCP_CPC_GRBM_FREE_COUNT 0x008b
129#define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0
130#define mmCP_MEC_CNTL 0x008d
131#define mmCP_MEC_CNTL_BASE_IDX 0
132#define mmCP_MEC_ME1_HEADER_DUMP 0x008e
133#define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0
134#define mmCP_MEC_ME2_HEADER_DUMP 0x008f
135#define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX 0
136#define mmCP_CPC_SCRATCH_INDEX 0x0090
137#define mmCP_CPC_SCRATCH_INDEX_BASE_IDX 0
138#define mmCP_CPC_SCRATCH_DATA 0x0091
139#define mmCP_CPC_SCRATCH_DATA_BASE_IDX 0
140#define mmCP_CPF_GRBM_FREE_COUNT 0x0092
141#define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0
142#define mmCP_CPC_HALT_HYST_COUNT 0x00a7
143#define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX 0
144#define mmCP_PRT_LOD_STATS_CNTL0 0x00ad
145#define mmCP_PRT_LOD_STATS_CNTL0_BASE_IDX 0
146#define mmCP_PRT_LOD_STATS_CNTL1 0x00ae
147#define mmCP_PRT_LOD_STATS_CNTL1_BASE_IDX 0
148#define mmCP_PRT_LOD_STATS_CNTL2 0x00af
149#define mmCP_PRT_LOD_STATS_CNTL2_BASE_IDX 0
150#define mmCP_PRT_LOD_STATS_CNTL3 0x00b0
151#define mmCP_PRT_LOD_STATS_CNTL3_BASE_IDX 0
152#define mmCP_CE_COMPARE_COUNT 0x00c0
153#define mmCP_CE_COMPARE_COUNT_BASE_IDX 0
154#define mmCP_CE_DE_COUNT 0x00c1
155#define mmCP_CE_DE_COUNT_BASE_IDX 0
156#define mmCP_DE_CE_COUNT 0x00c2
157#define mmCP_DE_CE_COUNT_BASE_IDX 0
158#define mmCP_DE_LAST_INVAL_COUNT 0x00c3
159#define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX 0
160#define mmCP_DE_DE_COUNT 0x00c4
161#define mmCP_DE_DE_COUNT_BASE_IDX 0
162#define mmCP_STALLED_STAT3 0x019c
163#define mmCP_STALLED_STAT3_BASE_IDX 0
164#define mmCP_STALLED_STAT1 0x019d
165#define mmCP_STALLED_STAT1_BASE_IDX 0
166#define mmCP_STALLED_STAT2 0x019e
167#define mmCP_STALLED_STAT2_BASE_IDX 0
168#define mmCP_BUSY_STAT 0x019f
169#define mmCP_BUSY_STAT_BASE_IDX 0
170#define mmCP_STAT 0x01a0
171#define mmCP_STAT_BASE_IDX 0
172#define mmCP_ME_HEADER_DUMP 0x01a1
173#define mmCP_ME_HEADER_DUMP_BASE_IDX 0
174#define mmCP_PFP_HEADER_DUMP 0x01a2
175#define mmCP_PFP_HEADER_DUMP_BASE_IDX 0
176#define mmCP_GRBM_FREE_COUNT 0x01a3
177#define mmCP_GRBM_FREE_COUNT_BASE_IDX 0
178#define mmCP_CE_HEADER_DUMP 0x01a4
179#define mmCP_CE_HEADER_DUMP_BASE_IDX 0
180#define mmCP_PFP_INSTR_PNTR 0x01a5
181#define mmCP_PFP_INSTR_PNTR_BASE_IDX 0
182#define mmCP_ME_INSTR_PNTR 0x01a6
183#define mmCP_ME_INSTR_PNTR_BASE_IDX 0
184#define mmCP_CE_INSTR_PNTR 0x01a7
185#define mmCP_CE_INSTR_PNTR_BASE_IDX 0
186#define mmCP_MEC1_INSTR_PNTR 0x01a8
187#define mmCP_MEC1_INSTR_PNTR_BASE_IDX 0
188#define mmCP_MEC2_INSTR_PNTR 0x01a9
189#define mmCP_MEC2_INSTR_PNTR_BASE_IDX 0
190#define mmCP_CSF_STAT 0x01b4
191#define mmCP_CSF_STAT_BASE_IDX 0
192#define mmCP_ME_CNTL 0x01b6
193#define mmCP_ME_CNTL_BASE_IDX 0
194#define mmCP_CNTX_STAT 0x01b8
195#define mmCP_CNTX_STAT_BASE_IDX 0
196#define mmCP_ME_PREEMPTION 0x01b9
197#define mmCP_ME_PREEMPTION_BASE_IDX 0
198#define mmCP_ROQ_THRESHOLDS 0x01bc
199#define mmCP_ROQ_THRESHOLDS_BASE_IDX 0
200#define mmCP_MEQ_STQ_THRESHOLD 0x01bd
201#define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX 0
202#define mmCP_RB2_RPTR 0x01be
203#define mmCP_RB2_RPTR_BASE_IDX 0
204#define mmCP_RB1_RPTR 0x01bf
205#define mmCP_RB1_RPTR_BASE_IDX 0
206#define mmCP_RB0_RPTR 0x01c0
207#define mmCP_RB0_RPTR_BASE_IDX 0
208#define mmCP_RB_RPTR 0x01c0
209#define mmCP_RB_RPTR_BASE_IDX 0
210#define mmCP_RB_WPTR_DELAY 0x01c1
211#define mmCP_RB_WPTR_DELAY_BASE_IDX 0
212#define mmCP_RB_WPTR_POLL_CNTL 0x01c2
213#define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX 0
214#define mmCP_ROQ1_THRESHOLDS 0x01d5
215#define mmCP_ROQ1_THRESHOLDS_BASE_IDX 0
216#define mmCP_ROQ2_THRESHOLDS 0x01d6
217#define mmCP_ROQ2_THRESHOLDS_BASE_IDX 0
218#define mmCP_STQ_THRESHOLDS 0x01d7
219#define mmCP_STQ_THRESHOLDS_BASE_IDX 0
220#define mmCP_QUEUE_THRESHOLDS 0x01d8
221#define mmCP_QUEUE_THRESHOLDS_BASE_IDX 0
222#define mmCP_MEQ_THRESHOLDS 0x01d9
223#define mmCP_MEQ_THRESHOLDS_BASE_IDX 0
224#define mmCP_ROQ_AVAIL 0x01da
225#define mmCP_ROQ_AVAIL_BASE_IDX 0
226#define mmCP_STQ_AVAIL 0x01db
227#define mmCP_STQ_AVAIL_BASE_IDX 0
228#define mmCP_ROQ2_AVAIL 0x01dc
229#define mmCP_ROQ2_AVAIL_BASE_IDX 0
230#define mmCP_MEQ_AVAIL 0x01dd
231#define mmCP_MEQ_AVAIL_BASE_IDX 0
232#define mmCP_CMD_INDEX 0x01de
233#define mmCP_CMD_INDEX_BASE_IDX 0
234#define mmCP_CMD_DATA 0x01df
235#define mmCP_CMD_DATA_BASE_IDX 0
236#define mmCP_ROQ_RB_STAT 0x01e0
237#define mmCP_ROQ_RB_STAT_BASE_IDX 0
238#define mmCP_ROQ_IB1_STAT 0x01e1
239#define mmCP_ROQ_IB1_STAT_BASE_IDX 0
240#define mmCP_ROQ_IB2_STAT 0x01e2
241#define mmCP_ROQ_IB2_STAT_BASE_IDX 0
242#define mmCP_STQ_STAT 0x01e3
243#define mmCP_STQ_STAT_BASE_IDX 0
244#define mmCP_STQ_WR_STAT 0x01e4
245#define mmCP_STQ_WR_STAT_BASE_IDX 0
246#define mmCP_MEQ_STAT 0x01e5
247#define mmCP_MEQ_STAT_BASE_IDX 0
248#define mmCP_CEQ1_AVAIL 0x01e6
249#define mmCP_CEQ1_AVAIL_BASE_IDX 0
250#define mmCP_CEQ2_AVAIL 0x01e7
251#define mmCP_CEQ2_AVAIL_BASE_IDX 0
252#define mmCP_CE_ROQ_RB_STAT 0x01e8
253#define mmCP_CE_ROQ_RB_STAT_BASE_IDX 0
254#define mmCP_CE_ROQ_IB1_STAT 0x01e9
255#define mmCP_CE_ROQ_IB1_STAT_BASE_IDX 0
256#define mmCP_CE_ROQ_IB2_STAT 0x01ea
257#define mmCP_CE_ROQ_IB2_STAT_BASE_IDX 0
258#define mmCP_INT_STAT_DEBUG 0x01f7
259#define mmCP_INT_STAT_DEBUG_BASE_IDX 0
260
261
262// addressBlock: gc_padec
263// base address: 0x8800
264#define mmVGT_VTX_VECT_EJECT_REG 0x022c
265#define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX 0
266#define mmVGT_DMA_DATA_FIFO_DEPTH 0x022d
267#define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0
268#define mmVGT_DMA_REQ_FIFO_DEPTH 0x022e
269#define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0
270#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x022f
271#define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0
272#define mmVGT_LAST_COPY_STATE 0x0230
273#define mmVGT_LAST_COPY_STATE_BASE_IDX 0
274#define mmVGT_CACHE_INVALIDATION 0x0231
275#define mmVGT_CACHE_INVALIDATION_BASE_IDX 0
276#define mmVGT_RESET_DEBUG 0x0232
277#define mmVGT_RESET_DEBUG_BASE_IDX 0
278#define mmVGT_STRMOUT_DELAY 0x0233
279#define mmVGT_STRMOUT_DELAY_BASE_IDX 0
280#define mmVGT_FIFO_DEPTHS 0x0234
281#define mmVGT_FIFO_DEPTHS_BASE_IDX 0
282#define mmVGT_GS_VERTEX_REUSE 0x0235
283#define mmVGT_GS_VERTEX_REUSE_BASE_IDX 0
284#define mmVGT_MC_LAT_CNTL 0x0236
285#define mmVGT_MC_LAT_CNTL_BASE_IDX 0
286#define mmIA_CNTL_STATUS 0x0237
287#define mmIA_CNTL_STATUS_BASE_IDX 0
288#define mmVGT_CNTL_STATUS 0x023c
289#define mmVGT_CNTL_STATUS_BASE_IDX 0
290#define mmWD_CNTL_STATUS 0x023f
291#define mmWD_CNTL_STATUS_BASE_IDX 0
292#define mmCC_GC_PRIM_CONFIG 0x0240
293#define mmCC_GC_PRIM_CONFIG_BASE_IDX 0
294#define mmGC_USER_PRIM_CONFIG 0x0241
295#define mmGC_USER_PRIM_CONFIG_BASE_IDX 0
296#define mmWD_QOS 0x0242
297#define mmWD_QOS_BASE_IDX 0
298#define mmWD_UTCL1_CNTL 0x0243
299#define mmWD_UTCL1_CNTL_BASE_IDX 0
300#define mmWD_UTCL1_STATUS 0x0244
301#define mmWD_UTCL1_STATUS_BASE_IDX 0
302#define mmIA_UTCL1_CNTL 0x0246
303#define mmIA_UTCL1_CNTL_BASE_IDX 0
304#define mmIA_UTCL1_STATUS 0x0247
305#define mmIA_UTCL1_STATUS_BASE_IDX 0
306#define mmVGT_SYS_CONFIG 0x0263
307#define mmVGT_SYS_CONFIG_BASE_IDX 0
308#define mmVGT_VS_MAX_WAVE_ID 0x0268
309#define mmVGT_VS_MAX_WAVE_ID_BASE_IDX 0
310#define mmVGT_GS_MAX_WAVE_ID 0x0269
311#define mmVGT_GS_MAX_WAVE_ID_BASE_IDX 0
312#define mmGFX_PIPE_CONTROL 0x026d
313#define mmGFX_PIPE_CONTROL_BASE_IDX 0
314#define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f
315#define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0
316#define mmGC_USER_SHADER_ARRAY_CONFIG 0x0270
317#define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 0
318#define mmVGT_DMA_PRIMITIVE_TYPE 0x0271
319#define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX 0
320#define mmVGT_DMA_CONTROL 0x0272
321#define mmVGT_DMA_CONTROL_BASE_IDX 0
322#define mmVGT_DMA_LS_HS_CONFIG 0x0273
323#define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX 0
324#define mmWD_BUF_RESOURCE_1 0x0276
325#define mmWD_BUF_RESOURCE_1_BASE_IDX 0
326#define mmWD_BUF_RESOURCE_2 0x0277
327#define mmWD_BUF_RESOURCE_2_BASE_IDX 0
328#define mmPA_CL_CNTL_STATUS 0x0284
329#define mmPA_CL_CNTL_STATUS_BASE_IDX 0
330#define mmPA_CL_ENHANCE 0x0285
331#define mmPA_CL_ENHANCE_BASE_IDX 0
332#define mmPA_CL_RESET_DEBUG 0x0286
333#define mmPA_CL_RESET_DEBUG_BASE_IDX 0
334#define mmPA_SU_CNTL_STATUS 0x0294
335#define mmPA_SU_CNTL_STATUS_BASE_IDX 0
336#define mmPA_SC_FIFO_DEPTH_CNTL 0x0295
337#define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0
338#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x02c0
339#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
340#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x02c1
341#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
342#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x02c2
343#define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 0
344#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x02c9
345#define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 0
346#define mmPA_SC_BINNER_EVENT_CNTL_0 0x02cc
347#define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 0
348#define mmPA_SC_BINNER_EVENT_CNTL_1 0x02cd
349#define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 0
350#define mmPA_SC_BINNER_EVENT_CNTL_2 0x02ce
351#define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 0
352#define mmPA_SC_BINNER_EVENT_CNTL_3 0x02cf
353#define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 0
354#define mmPA_SC_BINNER_TIMEOUT_COUNTER 0x02d0
355#define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 0
356#define mmPA_SC_BINNER_PERF_CNTL_0 0x02d1
357#define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 0
358#define mmPA_SC_BINNER_PERF_CNTL_1 0x02d2
359#define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 0
360#define mmPA_SC_BINNER_PERF_CNTL_2 0x02d3
361#define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 0
362#define mmPA_SC_BINNER_PERF_CNTL_3 0x02d4
363#define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 0
364#define mmPA_SC_FIFO_SIZE 0x02f3
365#define mmPA_SC_FIFO_SIZE_BASE_IDX 0
366#define mmPA_SC_IF_FIFO_SIZE 0x02f5
367#define mmPA_SC_IF_FIFO_SIZE_BASE_IDX 0
368#define mmPA_SC_PKR_WAVE_TABLE_CNTL 0x02f8
369#define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 0
370#define mmPA_UTCL1_CNTL1 0x02f9
371#define mmPA_UTCL1_CNTL1_BASE_IDX 0
372#define mmPA_UTCL1_CNTL2 0x02fa
373#define mmPA_UTCL1_CNTL2_BASE_IDX 0
374#define mmPA_SIDEBAND_REQUEST_DELAYS 0x02fb
375#define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX 0
376#define mmPA_SC_ENHANCE 0x02fc
377#define mmPA_SC_ENHANCE_BASE_IDX 0
378#define mmPA_SC_ENHANCE_1 0x02fd
379#define mmPA_SC_ENHANCE_1_BASE_IDX 0
380#define mmPA_SC_DSM_CNTL 0x02fe
381#define mmPA_SC_DSM_CNTL_BASE_IDX 0
382#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0x02ff
383#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 0
384
385
386// addressBlock: gc_sqdec
387// base address: 0x8c00
388#define mmSQ_CONFIG 0x0300
389#define mmSQ_CONFIG_BASE_IDX 0
390#define mmSQC_CONFIG 0x0301
391#define mmSQC_CONFIG_BASE_IDX 0
392#define mmLDS_CONFIG 0x0302
393#define mmLDS_CONFIG_BASE_IDX 0
394#define mmSQ_RANDOM_WAVE_PRI 0x0303
395#define mmSQ_RANDOM_WAVE_PRI_BASE_IDX 0
396#define mmSQ_REG_CREDITS 0x0304
397#define mmSQ_REG_CREDITS_BASE_IDX 0
398#define mmSQ_FIFO_SIZES 0x0305
399#define mmSQ_FIFO_SIZES_BASE_IDX 0
400#define mmSQ_DSM_CNTL 0x0306
401#define mmSQ_DSM_CNTL_BASE_IDX 0
402#define mmSQ_DSM_CNTL2 0x0307
403#define mmSQ_DSM_CNTL2_BASE_IDX 0
404#define mmSQ_RUNTIME_CONFIG 0x0308
405#define mmSQ_RUNTIME_CONFIG_BASE_IDX 0
406#define mmSH_MEM_BASES 0x030a
407#define mmSH_MEM_BASES_BASE_IDX 0
408#define mmSH_MEM_CONFIG 0x030d
409#define mmSH_MEM_CONFIG_BASE_IDX 0
410#define mmCC_GC_SHADER_RATE_CONFIG 0x0312
411#define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX 0
412#define mmGC_USER_SHADER_RATE_CONFIG 0x0313
413#define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX 0
414#define mmSQ_INTERRUPT_AUTO_MASK 0x0314
415#define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0
416#define mmSQ_INTERRUPT_MSG_CTRL 0x0315
417#define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0
418#define mmSQ_UTCL1_CNTL1 0x0317
419#define mmSQ_UTCL1_CNTL1_BASE_IDX 0
420#define mmSQ_UTCL1_CNTL2 0x0318
421#define mmSQ_UTCL1_CNTL2_BASE_IDX 0
422#define mmSQ_UTCL1_STATUS 0x0319
423#define mmSQ_UTCL1_STATUS_BASE_IDX 0
424#define mmSQ_SHADER_TBA_LO 0x031c
425#define mmSQ_SHADER_TBA_LO_BASE_IDX 0
426#define mmSQ_SHADER_TBA_HI 0x031d
427#define mmSQ_SHADER_TBA_HI_BASE_IDX 0
428#define mmSQ_SHADER_TMA_LO 0x031e
429#define mmSQ_SHADER_TMA_LO_BASE_IDX 0
430#define mmSQ_SHADER_TMA_HI 0x031f
431#define mmSQ_SHADER_TMA_HI_BASE_IDX 0
432#define mmSQC_DSM_CNTL 0x0320
433#define mmSQC_DSM_CNTL_BASE_IDX 0
434#define mmSQC_DSM_CNTLA 0x0321
435#define mmSQC_DSM_CNTLA_BASE_IDX 0
436#define mmSQC_DSM_CNTLB 0x0322
437#define mmSQC_DSM_CNTLB_BASE_IDX 0
438#define mmSQC_DSM_CNTL2 0x0325
439#define mmSQC_DSM_CNTL2_BASE_IDX 0
440#define mmSQC_DSM_CNTL2A 0x0326
441#define mmSQC_DSM_CNTL2A_BASE_IDX 0
442#define mmSQC_DSM_CNTL2B 0x0327
443#define mmSQC_DSM_CNTL2B_BASE_IDX 0
444#define mmSQC_EDC_FUE_CNTL 0x032b
445#define mmSQC_EDC_FUE_CNTL_BASE_IDX 0
446#define mmSQC_EDC_CNT2 0x032c
447#define mmSQC_EDC_CNT2_BASE_IDX 0
448#define mmSQC_EDC_CNT3 0x032d
449#define mmSQC_EDC_CNT3_BASE_IDX 0
450#define mmSQ_REG_TIMESTAMP 0x0374
451#define mmSQ_REG_TIMESTAMP_BASE_IDX 0
452#define mmSQ_CMD_TIMESTAMP 0x0375
453#define mmSQ_CMD_TIMESTAMP_BASE_IDX 0
454#define mmSQ_IND_INDEX 0x0378
455#define mmSQ_IND_INDEX_BASE_IDX 0
456#define mmSQ_IND_DATA 0x0379
457#define mmSQ_IND_DATA_BASE_IDX 0
458#define mmSQ_CMD 0x037b
459#define mmSQ_CMD_BASE_IDX 0
460#define mmSQ_TIME_HI 0x037c
461#define mmSQ_TIME_HI_BASE_IDX 0
462#define mmSQ_TIME_LO 0x037d
463#define mmSQ_TIME_LO_BASE_IDX 0
464#define mmSQ_DS_0 0x037f
465#define mmSQ_DS_0_BASE_IDX 0
466#define mmSQ_DS_1 0x037f
467#define mmSQ_DS_1_BASE_IDX 0
468#define mmSQ_EXP_0 0x037f
469#define mmSQ_EXP_0_BASE_IDX 0
470#define mmSQ_EXP_1 0x037f
471#define mmSQ_EXP_1_BASE_IDX 0
472#define mmSQ_FLAT_0 0x037f
473#define mmSQ_FLAT_0_BASE_IDX 0
474#define mmSQ_FLAT_1 0x037f
475#define mmSQ_FLAT_1_BASE_IDX 0
476#define mmSQ_GLBL_0 0x037f
477#define mmSQ_GLBL_0_BASE_IDX 0
478#define mmSQ_GLBL_1 0x037f
479#define mmSQ_GLBL_1_BASE_IDX 0
480#define mmSQ_INST 0x037f
481#define mmSQ_INST_BASE_IDX 0
482#define mmSQ_MIMG_0 0x037f
483#define mmSQ_MIMG_0_BASE_IDX 0
484#define mmSQ_MIMG_1 0x037f
485#define mmSQ_MIMG_1_BASE_IDX 0
486#define mmSQ_MTBUF_0 0x037f
487#define mmSQ_MTBUF_0_BASE_IDX 0
488#define mmSQ_MTBUF_1 0x037f
489#define mmSQ_MTBUF_1_BASE_IDX 0
490#define mmSQ_MUBUF_0 0x037f
491#define mmSQ_MUBUF_0_BASE_IDX 0
492#define mmSQ_MUBUF_1 0x037f
493#define mmSQ_MUBUF_1_BASE_IDX 0
494#define mmSQ_SCRATCH_0 0x037f
495#define mmSQ_SCRATCH_0_BASE_IDX 0
496#define mmSQ_SCRATCH_1 0x037f
497#define mmSQ_SCRATCH_1_BASE_IDX 0
498#define mmSQ_SMEM_0 0x037f
499#define mmSQ_SMEM_0_BASE_IDX 0
500#define mmSQ_SMEM_1 0x037f
501#define mmSQ_SMEM_1_BASE_IDX 0
502#define mmSQ_SOP1 0x037f
503#define mmSQ_SOP1_BASE_IDX 0
504#define mmSQ_SOP2 0x037f
505#define mmSQ_SOP2_BASE_IDX 0
506#define mmSQ_SOPC 0x037f
507#define mmSQ_SOPC_BASE_IDX 0
508#define mmSQ_SOPK 0x037f
509#define mmSQ_SOPK_BASE_IDX 0
510#define mmSQ_SOPP 0x037f
511#define mmSQ_SOPP_BASE_IDX 0
512#define mmSQ_VINTRP 0x037f
513#define mmSQ_VINTRP_BASE_IDX 0
514#define mmSQ_VOP1 0x037f
515#define mmSQ_VOP1_BASE_IDX 0
516#define mmSQ_VOP2 0x037f
517#define mmSQ_VOP2_BASE_IDX 0
518#define mmSQ_VOP3P_0 0x037f
519#define mmSQ_VOP3P_0_BASE_IDX 0
520#define mmSQ_VOP3P_1 0x037f
521#define mmSQ_VOP3P_1_BASE_IDX 0
522#define mmSQ_VOP3_0 0x037f
523#define mmSQ_VOP3_0_BASE_IDX 0
524#define mmSQ_VOP3_0_SDST_ENC 0x037f
525#define mmSQ_VOP3_0_SDST_ENC_BASE_IDX 0
526#define mmSQ_VOP3_1 0x037f
527#define mmSQ_VOP3_1_BASE_IDX 0
528#define mmSQ_VOPC 0x037f
529#define mmSQ_VOPC_BASE_IDX 0
530#define mmSQ_VOP_DPP 0x037f
531#define mmSQ_VOP_DPP_BASE_IDX 0
532#define mmSQ_VOP_SDWA 0x037f
533#define mmSQ_VOP_SDWA_BASE_IDX 0
534#define mmSQ_VOP_SDWA_SDST_ENC 0x037f
535#define mmSQ_VOP_SDWA_SDST_ENC_BASE_IDX 0
536#define mmSQ_LB_CTR_CTRL 0x0398
537#define mmSQ_LB_CTR_CTRL_BASE_IDX 0
538#define mmSQ_LB_DATA0 0x0399
539#define mmSQ_LB_DATA0_BASE_IDX 0
540#define mmSQ_LB_DATA1 0x039a
541#define mmSQ_LB_DATA1_BASE_IDX 0
542#define mmSQ_LB_DATA2 0x039b
543#define mmSQ_LB_DATA2_BASE_IDX 0
544#define mmSQ_LB_DATA3 0x039c
545#define mmSQ_LB_DATA3_BASE_IDX 0
546#define mmSQ_LB_CTR_SEL 0x039d
547#define mmSQ_LB_CTR_SEL_BASE_IDX 0
548#define mmSQ_LB_CTR0_CU 0x039e
549#define mmSQ_LB_CTR0_CU_BASE_IDX 0
550#define mmSQ_LB_CTR1_CU 0x039f
551#define mmSQ_LB_CTR1_CU_BASE_IDX 0
552#define mmSQ_LB_CTR2_CU 0x03a0
553#define mmSQ_LB_CTR2_CU_BASE_IDX 0
554#define mmSQ_LB_CTR3_CU 0x03a1
555#define mmSQ_LB_CTR3_CU_BASE_IDX 0
556#define mmSQC_EDC_CNT 0x03a2
557#define mmSQC_EDC_CNT_BASE_IDX 0
558#define mmSQ_EDC_SEC_CNT 0x03a3
559#define mmSQ_EDC_SEC_CNT_BASE_IDX 0
560#define mmSQ_EDC_DED_CNT 0x03a4
561#define mmSQ_EDC_DED_CNT_BASE_IDX 0
562#define mmSQ_EDC_INFO 0x03a5
563#define mmSQ_EDC_INFO_BASE_IDX 0
564#define mmSQ_EDC_CNT 0x03a6
565#define mmSQ_EDC_CNT_BASE_IDX 0
566#define mmSQ_EDC_FUE_CNTL 0x03a7
567#define mmSQ_EDC_FUE_CNTL_BASE_IDX 0
568#define mmSQ_THREAD_TRACE_WORD_CMN 0x03b0
569#define mmSQ_THREAD_TRACE_WORD_CMN_BASE_IDX 0
570#define mmSQ_THREAD_TRACE_WORD_EVENT 0x03b0
571#define mmSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX 0
572#define mmSQ_THREAD_TRACE_WORD_INST 0x03b0
573#define mmSQ_THREAD_TRACE_WORD_INST_BASE_IDX 0
574#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x03b0
575#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX 0
576#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x03b0
577#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX 0
578#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x03b0
579#define mmSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX 0
580#define mmSQ_THREAD_TRACE_WORD_MISC 0x03b0
581#define mmSQ_THREAD_TRACE_WORD_MISC_BASE_IDX 0
582#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x03b0
583#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX 0
584#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x03b0
585#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX 0
586#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x03b0
587#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX 0
588#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x03b0
589#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX 0
590#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x03b0
591#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX 0
592#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x03b0
593#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX 0
594#define mmSQ_THREAD_TRACE_WORD_WAVE 0x03b0
595#define mmSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX 0
596#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x03b0
597#define mmSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX 0
598#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x03b1
599#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX 0
600#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x03b1
601#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX 0
602#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x03b1
603#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX 0
604#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x03b1
605#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX 0
606#define mmSQ_WREXEC_EXEC_HI 0x03b1
607#define mmSQ_WREXEC_EXEC_HI_BASE_IDX 0
608#define mmSQ_WREXEC_EXEC_LO 0x03b1
609#define mmSQ_WREXEC_EXEC_LO_BASE_IDX 0
610#define mmSQ_BUF_RSRC_WORD0 0x03c0
611#define mmSQ_BUF_RSRC_WORD0_BASE_IDX 0
612#define mmSQ_BUF_RSRC_WORD1 0x03c1
613#define mmSQ_BUF_RSRC_WORD1_BASE_IDX 0
614#define mmSQ_BUF_RSRC_WORD2 0x03c2
615#define mmSQ_BUF_RSRC_WORD2_BASE_IDX 0
616#define mmSQ_BUF_RSRC_WORD3 0x03c3
617#define mmSQ_BUF_RSRC_WORD3_BASE_IDX 0
618#define mmSQ_IMG_RSRC_WORD0 0x03c4
619#define mmSQ_IMG_RSRC_WORD0_BASE_IDX 0
620#define mmSQ_IMG_RSRC_WORD1 0x03c5
621#define mmSQ_IMG_RSRC_WORD1_BASE_IDX 0
622#define mmSQ_IMG_RSRC_WORD2 0x03c6
623#define mmSQ_IMG_RSRC_WORD2_BASE_IDX 0
624#define mmSQ_IMG_RSRC_WORD3 0x03c7
625#define mmSQ_IMG_RSRC_WORD3_BASE_IDX 0
626#define mmSQ_IMG_RSRC_WORD4 0x03c8
627#define mmSQ_IMG_RSRC_WORD4_BASE_IDX 0
628#define mmSQ_IMG_RSRC_WORD5 0x03c9
629#define mmSQ_IMG_RSRC_WORD5_BASE_IDX 0
630#define mmSQ_IMG_RSRC_WORD6 0x03ca
631#define mmSQ_IMG_RSRC_WORD6_BASE_IDX 0
632#define mmSQ_IMG_RSRC_WORD7 0x03cb
633#define mmSQ_IMG_RSRC_WORD7_BASE_IDX 0
634#define mmSQ_IMG_SAMP_WORD0 0x03cc
635#define mmSQ_IMG_SAMP_WORD0_BASE_IDX 0
636#define mmSQ_IMG_SAMP_WORD1 0x03cd
637#define mmSQ_IMG_SAMP_WORD1_BASE_IDX 0
638#define mmSQ_IMG_SAMP_WORD2 0x03ce
639#define mmSQ_IMG_SAMP_WORD2_BASE_IDX 0
640#define mmSQ_IMG_SAMP_WORD3 0x03cf
641#define mmSQ_IMG_SAMP_WORD3_BASE_IDX 0
642#define mmSQ_FLAT_SCRATCH_WORD0 0x03d0
643#define mmSQ_FLAT_SCRATCH_WORD0_BASE_IDX 0
644#define mmSQ_FLAT_SCRATCH_WORD1 0x03d1
645#define mmSQ_FLAT_SCRATCH_WORD1_BASE_IDX 0
646#define mmSQ_M0_GPR_IDX_WORD 0x03d2
647#define mmSQ_M0_GPR_IDX_WORD_BASE_IDX 0
648#define mmSQC_ICACHE_UTCL1_CNTL1 0x03d3
649#define mmSQC_ICACHE_UTCL1_CNTL1_BASE_IDX 0
650#define mmSQC_ICACHE_UTCL1_CNTL2 0x03d4
651#define mmSQC_ICACHE_UTCL1_CNTL2_BASE_IDX 0
652#define mmSQC_DCACHE_UTCL1_CNTL1 0x03d5
653#define mmSQC_DCACHE_UTCL1_CNTL1_BASE_IDX 0
654#define mmSQC_DCACHE_UTCL1_CNTL2 0x03d6
655#define mmSQC_DCACHE_UTCL1_CNTL2_BASE_IDX 0
656#define mmSQC_ICACHE_UTCL1_STATUS 0x03d7
657#define mmSQC_ICACHE_UTCL1_STATUS_BASE_IDX 0
658#define mmSQC_DCACHE_UTCL1_STATUS 0x03d8
659#define mmSQC_DCACHE_UTCL1_STATUS_BASE_IDX 0
660
661
662// addressBlock: gc_shsdec
663// base address: 0x9000
664#define mmSX_DEBUG_BUSY 0x0414
665#define mmSX_DEBUG_BUSY_BASE_IDX 0
666#define mmSX_DEBUG_BUSY_2 0x0415
667#define mmSX_DEBUG_BUSY_2_BASE_IDX 0
668#define mmSX_DEBUG_BUSY_3 0x0416
669#define mmSX_DEBUG_BUSY_3_BASE_IDX 0
670#define mmSX_DEBUG_BUSY_4 0x0417
671#define mmSX_DEBUG_BUSY_4_BASE_IDX 0
672#define mmSX_DEBUG_BUSY_5 0x0418
673#define mmSX_DEBUG_BUSY_5_BASE_IDX 0
674#define mmSX_DEBUG_1 0x0419
675#define mmSX_DEBUG_1_BASE_IDX 0
676#define mmSPI_PS_MAX_WAVE_ID 0x043a
677#define mmSPI_PS_MAX_WAVE_ID_BASE_IDX 0
678#define mmSPI_START_PHASE 0x043b
679#define mmSPI_START_PHASE_BASE_IDX 0
680#define mmSPI_GFX_CNTL 0x043c
681#define mmSPI_GFX_CNTL_BASE_IDX 0
682#define mmSPI_DEBUG_READ 0x0442
683#define mmSPI_DEBUG_READ_BASE_IDX 0
684#define mmSPI_DSM_CNTL 0x0443
685#define mmSPI_DSM_CNTL_BASE_IDX 0
686#define mmSPI_DSM_CNTL2 0x0444
687#define mmSPI_DSM_CNTL2_BASE_IDX 0
688#define mmSPI_EDC_CNT 0x0445
689#define mmSPI_EDC_CNT_BASE_IDX 0
690#define mmSPI_DEBUG_BUSY 0x0450
691#define mmSPI_DEBUG_BUSY_BASE_IDX 0
692#define mmSPI_CONFIG_PS_CU_EN 0x0452
693#define mmSPI_CONFIG_PS_CU_EN_BASE_IDX 0
694#define mmSPI_WF_LIFETIME_CNTL 0x04aa
695#define mmSPI_WF_LIFETIME_CNTL_BASE_IDX 0
696#define mmSPI_WF_LIFETIME_LIMIT_0 0x04ab
697#define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0
698#define mmSPI_WF_LIFETIME_LIMIT_1 0x04ac
699#define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX 0
700#define mmSPI_WF_LIFETIME_LIMIT_2 0x04ad
701#define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0
702#define mmSPI_WF_LIFETIME_LIMIT_3 0x04ae
703#define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0
704#define mmSPI_WF_LIFETIME_LIMIT_4 0x04af
705#define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0
706#define mmSPI_WF_LIFETIME_LIMIT_5 0x04b0
707#define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0
708#define mmSPI_WF_LIFETIME_LIMIT_6 0x04b1
709#define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX 0
710#define mmSPI_WF_LIFETIME_LIMIT_7 0x04b2
711#define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX 0
712#define mmSPI_WF_LIFETIME_LIMIT_8 0x04b3
713#define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX 0
714#define mmSPI_WF_LIFETIME_LIMIT_9 0x04b4
715#define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX 0
716#define mmSPI_WF_LIFETIME_STATUS_0 0x04b5
717#define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0
718#define mmSPI_WF_LIFETIME_STATUS_1 0x04b6
719#define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX 0
720#define mmSPI_WF_LIFETIME_STATUS_2 0x04b7
721#define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0
722#define mmSPI_WF_LIFETIME_STATUS_3 0x04b8
723#define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX 0
724#define mmSPI_WF_LIFETIME_STATUS_4 0x04b9
725#define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0
726#define mmSPI_WF_LIFETIME_STATUS_5 0x04ba
727#define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX 0
728#define mmSPI_WF_LIFETIME_STATUS_6 0x04bb
729#define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0
730#define mmSPI_WF_LIFETIME_STATUS_7 0x04bc
731#define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0
732#define mmSPI_WF_LIFETIME_STATUS_8 0x04bd
733#define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX 0
734#define mmSPI_WF_LIFETIME_STATUS_9 0x04be
735#define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0
736#define mmSPI_WF_LIFETIME_STATUS_10 0x04bf
737#define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX 0
738#define mmSPI_WF_LIFETIME_STATUS_11 0x04c0
739#define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0
740#define mmSPI_WF_LIFETIME_STATUS_12 0x04c1
741#define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX 0
742#define mmSPI_WF_LIFETIME_STATUS_13 0x04c2
743#define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0
744#define mmSPI_WF_LIFETIME_STATUS_14 0x04c3
745#define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0
746#define mmSPI_WF_LIFETIME_STATUS_15 0x04c4
747#define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0
748#define mmSPI_WF_LIFETIME_STATUS_16 0x04c5
749#define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0
750#define mmSPI_WF_LIFETIME_STATUS_17 0x04c6
751#define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0
752#define mmSPI_WF_LIFETIME_STATUS_18 0x04c7
753#define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0
754#define mmSPI_WF_LIFETIME_STATUS_19 0x04c8
755#define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0
756#define mmSPI_WF_LIFETIME_STATUS_20 0x04c9
757#define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0
758#define mmSPI_WF_LIFETIME_DEBUG 0x04ca
759#define mmSPI_WF_LIFETIME_DEBUG_BASE_IDX 0
760#define mmSPI_LB_CTR_CTRL 0x04d4
761#define mmSPI_LB_CTR_CTRL_BASE_IDX 0
762#define mmSPI_LB_CU_MASK 0x04d5
763#define mmSPI_LB_CU_MASK_BASE_IDX 0
764#define mmSPI_LB_DATA_REG 0x04d6
765#define mmSPI_LB_DATA_REG_BASE_IDX 0
766#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x04d7
767#define mmSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX 0
768#define mmSPI_GDS_CREDITS 0x04d8
769#define mmSPI_GDS_CREDITS_BASE_IDX 0
770#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x04d9
771#define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0
772#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x04da
773#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0
774#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x04db
775#define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0
776#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x04dc
777#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0
778#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x04dd
779#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0
780#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x04de
781#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0
782#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x04df
783#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0
784#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x04e0
785#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0
786#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x04e1
787#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0
788#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x04e2
789#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0
790#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x04e3
791#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0
792#define mmSPI_LB_DATA_WAVES 0x04e4
793#define mmSPI_LB_DATA_WAVES_BASE_IDX 0
794#define mmSPI_LB_DATA_PERCU_WAVE_HSGS 0x04e5
795#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX 0
796#define mmSPI_LB_DATA_PERCU_WAVE_VSPS 0x04e6
797#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX 0
798#define mmSPI_LB_DATA_PERCU_WAVE_CS 0x04e7
799#define mmSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX 0
800#define mmSPIS_DEBUG_READ 0x04ea
801#define mmSPIS_DEBUG_READ_BASE_IDX 0
802#define mmBCI_DEBUG_READ 0x04eb
803#define mmBCI_DEBUG_READ_BASE_IDX 0
804#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x04ec
805#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
806#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x04ed
807#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
808#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x04ee
809#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
810#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x04ef
811#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
812#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x04f0
813#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
814#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x04f1
815#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0
816#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x04f2
817#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0
818#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x04f3
819#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0
820#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x04f4
821#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0
822#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x04f5
823#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0
824
825
826// addressBlock: gc_tpdec
827// base address: 0x9400
828#define mmTD_CNTL 0x0525
829#define mmTD_CNTL_BASE_IDX 0
830#define mmTD_STATUS 0x0526
831#define mmTD_STATUS_BASE_IDX 0
832#define mmTD_DSM_CNTL 0x052f
833#define mmTD_DSM_CNTL_BASE_IDX 0
834#define mmTD_DSM_CNTL2 0x0530
835#define mmTD_DSM_CNTL2_BASE_IDX 0
836#define mmTD_SCRATCH 0x0533
837#define mmTD_SCRATCH_BASE_IDX 0
838#define mmTA_CNTL 0x0541
839#define mmTA_CNTL_BASE_IDX 0
840#define mmTA_CNTL_AUX 0x0542
841#define mmTA_CNTL_AUX_BASE_IDX 0
842#define mmTA_RESERVED_010C 0x0543
843#define mmTA_RESERVED_010C_BASE_IDX 0
844#define mmTA_STATUS 0x0548
845#define mmTA_STATUS_BASE_IDX 0
846#define mmTA_SCRATCH 0x0564
847#define mmTA_SCRATCH_BASE_IDX 0
848
849
850// addressBlock: gc_gdsdec
851// base address: 0x9700
852#define mmGDS_CONFIG 0x05c0
853#define mmGDS_CONFIG_BASE_IDX 0
854#define mmGDS_CNTL_STATUS 0x05c1
855#define mmGDS_CNTL_STATUS_BASE_IDX 0
856#define mmGDS_ENHANCE2 0x05c2
857#define mmGDS_ENHANCE2_BASE_IDX 0
858#define mmGDS_PROTECTION_FAULT 0x05c3
859#define mmGDS_PROTECTION_FAULT_BASE_IDX 0
860#define mmGDS_VM_PROTECTION_FAULT 0x05c4
861#define mmGDS_VM_PROTECTION_FAULT_BASE_IDX 0
862#define mmGDS_EDC_CNT 0x05c5
863#define mmGDS_EDC_CNT_BASE_IDX 0
864#define mmGDS_EDC_GRBM_CNT 0x05c6
865#define mmGDS_EDC_GRBM_CNT_BASE_IDX 0
866#define mmGDS_EDC_OA_DED 0x05c7
867#define mmGDS_EDC_OA_DED_BASE_IDX 0
868#define mmGDS_DSM_CNTL 0x05ca
869#define mmGDS_DSM_CNTL_BASE_IDX 0
870#define mmGDS_EDC_OA_PHY_CNT 0x05cb
871#define mmGDS_EDC_OA_PHY_CNT_BASE_IDX 0
872#define mmGDS_EDC_OA_PIPE_CNT 0x05cc
873#define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX 0
874#define mmGDS_DSM_CNTL2 0x05cd
875#define mmGDS_DSM_CNTL2_BASE_IDX 0
876#define mmGDS_WD_GDS_CSB 0x05ce
877#define mmGDS_WD_GDS_CSB_BASE_IDX 0
878
879
880// addressBlock: gc_rbdec
881// base address: 0x9800
882#define mmDB_DEBUG 0x060c
883#define mmDB_DEBUG_BASE_IDX 0
884#define mmDB_DEBUG2 0x060d
885#define mmDB_DEBUG2_BASE_IDX 0
886#define mmDB_DEBUG3 0x060e
887#define mmDB_DEBUG3_BASE_IDX 0
888#define mmDB_DEBUG4 0x060f
889#define mmDB_DEBUG4_BASE_IDX 0
890#define mmDB_CREDIT_LIMIT 0x0614
891#define mmDB_CREDIT_LIMIT_BASE_IDX 0
892#define mmDB_WATERMARKS 0x0615
893#define mmDB_WATERMARKS_BASE_IDX 0
894#define mmDB_SUBTILE_CONTROL 0x0616
895#define mmDB_SUBTILE_CONTROL_BASE_IDX 0
896#define mmDB_FREE_CACHELINES 0x0617
897#define mmDB_FREE_CACHELINES_BASE_IDX 0
898#define mmDB_FIFO_DEPTH1 0x0618
899#define mmDB_FIFO_DEPTH1_BASE_IDX 0
900#define mmDB_FIFO_DEPTH2 0x0619
901#define mmDB_FIFO_DEPTH2_BASE_IDX 0
902#define mmDB_EXCEPTION_CONTROL 0x061a
903#define mmDB_EXCEPTION_CONTROL_BASE_IDX 0
904#define mmDB_RING_CONTROL 0x061b
905#define mmDB_RING_CONTROL_BASE_IDX 0
906#define mmDB_MEM_ARB_WATERMARKS 0x061c
907#define mmDB_MEM_ARB_WATERMARKS_BASE_IDX 0
908#define mmDB_RMI_CACHE_POLICY 0x061e
909#define mmDB_RMI_CACHE_POLICY_BASE_IDX 0
910#define mmDB_DFSM_CONFIG 0x0630
911#define mmDB_DFSM_CONFIG_BASE_IDX 0
912#define mmDB_DFSM_WATERMARK 0x0631
913#define mmDB_DFSM_WATERMARK_BASE_IDX 0
914#define mmDB_DFSM_TILES_IN_FLIGHT 0x0632
915#define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX 0
916#define mmDB_DFSM_PRIMS_IN_FLIGHT 0x0633
917#define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX 0
918#define mmDB_DFSM_WATCHDOG 0x0634
919#define mmDB_DFSM_WATCHDOG_BASE_IDX 0
920#define mmDB_DFSM_FLUSH_ENABLE 0x0635
921#define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX 0
922#define mmDB_DFSM_FLUSH_AUX_EVENT 0x0636
923#define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX 0
924#define mmCC_RB_REDUNDANCY 0x063c
925#define mmCC_RB_REDUNDANCY_BASE_IDX 0
926#define mmCC_RB_BACKEND_DISABLE 0x063d
927#define mmCC_RB_BACKEND_DISABLE_BASE_IDX 0
928#define mmGB_ADDR_CONFIG 0x063e
929#define mmGB_ADDR_CONFIG_BASE_IDX 0
930#define mmGB_BACKEND_MAP 0x063f
931#define mmGB_BACKEND_MAP_BASE_IDX 0
932#define mmGB_GPU_ID 0x0640
933#define mmGB_GPU_ID_BASE_IDX 0
934#define mmCC_RB_DAISY_CHAIN 0x0641
935#define mmCC_RB_DAISY_CHAIN_BASE_IDX 0
936#define mmGB_ADDR_CONFIG_READ 0x0642
937#define mmGB_ADDR_CONFIG_READ_BASE_IDX 0
938#define mmGB_TILE_MODE0 0x0644
939#define mmGB_TILE_MODE0_BASE_IDX 0
940#define mmGB_TILE_MODE1 0x0645
941#define mmGB_TILE_MODE1_BASE_IDX 0
942#define mmGB_TILE_MODE2 0x0646
943#define mmGB_TILE_MODE2_BASE_IDX 0
944#define mmGB_TILE_MODE3 0x0647
945#define mmGB_TILE_MODE3_BASE_IDX 0
946#define mmGB_TILE_MODE4 0x0648
947#define mmGB_TILE_MODE4_BASE_IDX 0
948#define mmGB_TILE_MODE5 0x0649
949#define mmGB_TILE_MODE5_BASE_IDX 0
950#define mmGB_TILE_MODE6 0x064a
951#define mmGB_TILE_MODE6_BASE_IDX 0
952#define mmGB_TILE_MODE7 0x064b
953#define mmGB_TILE_MODE7_BASE_IDX 0
954#define mmGB_TILE_MODE8 0x064c
955#define mmGB_TILE_MODE8_BASE_IDX 0
956#define mmGB_TILE_MODE9 0x064d
957#define mmGB_TILE_MODE9_BASE_IDX 0
958#define mmGB_TILE_MODE10 0x064e
959#define mmGB_TILE_MODE10_BASE_IDX 0
960#define mmGB_TILE_MODE11 0x064f
961#define mmGB_TILE_MODE11_BASE_IDX 0
962#define mmGB_TILE_MODE12 0x0650
963#define mmGB_TILE_MODE12_BASE_IDX 0
964#define mmGB_TILE_MODE13 0x0651
965#define mmGB_TILE_MODE13_BASE_IDX 0
966#define mmGB_TILE_MODE14 0x0652
967#define mmGB_TILE_MODE14_BASE_IDX 0
968#define mmGB_TILE_MODE15 0x0653
969#define mmGB_TILE_MODE15_BASE_IDX 0
970#define mmGB_TILE_MODE16 0x0654
971#define mmGB_TILE_MODE16_BASE_IDX 0
972#define mmGB_TILE_MODE17 0x0655
973#define mmGB_TILE_MODE17_BASE_IDX 0
974#define mmGB_TILE_MODE18 0x0656
975#define mmGB_TILE_MODE18_BASE_IDX 0
976#define mmGB_TILE_MODE19 0x0657
977#define mmGB_TILE_MODE19_BASE_IDX 0
978#define mmGB_TILE_MODE20 0x0658
979#define mmGB_TILE_MODE20_BASE_IDX 0
980#define mmGB_TILE_MODE21 0x0659
981#define mmGB_TILE_MODE21_BASE_IDX 0
982#define mmGB_TILE_MODE22 0x065a
983#define mmGB_TILE_MODE22_BASE_IDX 0
984#define mmGB_TILE_MODE23 0x065b
985#define mmGB_TILE_MODE23_BASE_IDX 0
986#define mmGB_TILE_MODE24 0x065c
987#define mmGB_TILE_MODE24_BASE_IDX 0
988#define mmGB_TILE_MODE25 0x065d
989#define mmGB_TILE_MODE25_BASE_IDX 0
990#define mmGB_TILE_MODE26 0x065e
991#define mmGB_TILE_MODE26_BASE_IDX 0
992#define mmGB_TILE_MODE27 0x065f
993#define mmGB_TILE_MODE27_BASE_IDX 0
994#define mmGB_TILE_MODE28 0x0660
995#define mmGB_TILE_MODE28_BASE_IDX 0
996#define mmGB_TILE_MODE29 0x0661
997#define mmGB_TILE_MODE29_BASE_IDX 0
998#define mmGB_TILE_MODE30 0x0662
999#define mmGB_TILE_MODE30_BASE_IDX 0
1000#define mmGB_TILE_MODE31 0x0663
1001#define mmGB_TILE_MODE31_BASE_IDX 0
1002#define mmGB_MACROTILE_MODE0 0x0664
1003#define mmGB_MACROTILE_MODE0_BASE_IDX 0
1004#define mmGB_MACROTILE_MODE1 0x0665
1005#define mmGB_MACROTILE_MODE1_BASE_IDX 0
1006#define mmGB_MACROTILE_MODE2 0x0666
1007#define mmGB_MACROTILE_MODE2_BASE_IDX 0
1008#define mmGB_MACROTILE_MODE3 0x0667
1009#define mmGB_MACROTILE_MODE3_BASE_IDX 0
1010#define mmGB_MACROTILE_MODE4 0x0668
1011#define mmGB_MACROTILE_MODE4_BASE_IDX 0
1012#define mmGB_MACROTILE_MODE5 0x0669
1013#define mmGB_MACROTILE_MODE5_BASE_IDX 0
1014#define mmGB_MACROTILE_MODE6 0x066a
1015#define mmGB_MACROTILE_MODE6_BASE_IDX 0
1016#define mmGB_MACROTILE_MODE7 0x066b
1017#define mmGB_MACROTILE_MODE7_BASE_IDX 0
1018#define mmGB_MACROTILE_MODE8 0x066c
1019#define mmGB_MACROTILE_MODE8_BASE_IDX 0
1020#define mmGB_MACROTILE_MODE9 0x066d
1021#define mmGB_MACROTILE_MODE9_BASE_IDX 0
1022#define mmGB_MACROTILE_MODE10 0x066e
1023#define mmGB_MACROTILE_MODE10_BASE_IDX 0
1024#define mmGB_MACROTILE_MODE11 0x066f
1025#define mmGB_MACROTILE_MODE11_BASE_IDX 0
1026#define mmGB_MACROTILE_MODE12 0x0670
1027#define mmGB_MACROTILE_MODE12_BASE_IDX 0
1028#define mmGB_MACROTILE_MODE13 0x0671
1029#define mmGB_MACROTILE_MODE13_BASE_IDX 0
1030#define mmGB_MACROTILE_MODE14 0x0672
1031#define mmGB_MACROTILE_MODE14_BASE_IDX 0
1032#define mmGB_MACROTILE_MODE15 0x0673
1033#define mmGB_MACROTILE_MODE15_BASE_IDX 0
1034#define mmCB_HW_CONTROL 0x0680
1035#define mmCB_HW_CONTROL_BASE_IDX 0
1036#define mmCB_HW_CONTROL_1 0x0681
1037#define mmCB_HW_CONTROL_1_BASE_IDX 0
1038#define mmCB_HW_CONTROL_2 0x0682
1039#define mmCB_HW_CONTROL_2_BASE_IDX 0
1040#define mmCB_HW_CONTROL_3 0x0683
1041#define mmCB_HW_CONTROL_3_BASE_IDX 0
1042#define mmCB_HW_MEM_ARBITER_RD 0x0686
1043#define mmCB_HW_MEM_ARBITER_RD_BASE_IDX 0
1044#define mmCB_HW_MEM_ARBITER_WR 0x0687
1045#define mmCB_HW_MEM_ARBITER_WR_BASE_IDX 0
1046#define mmCB_DCC_CONFIG 0x0688
1047#define mmCB_DCC_CONFIG_BASE_IDX 0
1048#define mmGC_USER_RB_REDUNDANCY 0x06de
1049#define mmGC_USER_RB_REDUNDANCY_BASE_IDX 0
1050#define mmGC_USER_RB_BACKEND_DISABLE 0x06df
1051#define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX 0
1052
1053
1054// addressBlock: gc_rmi_rmidec
1055// base address: 0x9e00
1056#define mmRMI_GENERAL_CNTL 0x0780
1057#define mmRMI_GENERAL_CNTL_BASE_IDX 0
1058#define mmRMI_GENERAL_CNTL1 0x0781
1059#define mmRMI_GENERAL_CNTL1_BASE_IDX 0
1060#define mmRMI_GENERAL_STATUS 0x0782
1061#define mmRMI_GENERAL_STATUS_BASE_IDX 0
1062#define mmRMI_SUBBLOCK_STATUS0 0x0783
1063#define mmRMI_SUBBLOCK_STATUS0_BASE_IDX 0
1064#define mmRMI_SUBBLOCK_STATUS1 0x0784
1065#define mmRMI_SUBBLOCK_STATUS1_BASE_IDX 0
1066#define mmRMI_SUBBLOCK_STATUS2 0x0785
1067#define mmRMI_SUBBLOCK_STATUS2_BASE_IDX 0
1068#define mmRMI_SUBBLOCK_STATUS3 0x0786
1069#define mmRMI_SUBBLOCK_STATUS3_BASE_IDX 0
1070#define mmRMI_XBAR_CONFIG 0x0787
1071#define mmRMI_XBAR_CONFIG_BASE_IDX 0
1072#define mmRMI_PROBE_POP_LOGIC_CNTL 0x0788
1073#define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 0
1074#define mmRMI_UTC_XNACK_N_MISC_CNTL 0x0789
1075#define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 0
1076#define mmRMI_DEMUX_CNTL 0x078a
1077#define mmRMI_DEMUX_CNTL_BASE_IDX 0
1078#define mmRMI_UTCL1_CNTL1 0x078b
1079#define mmRMI_UTCL1_CNTL1_BASE_IDX 0
1080#define mmRMI_UTCL1_CNTL2 0x078c
1081#define mmRMI_UTCL1_CNTL2_BASE_IDX 0
1082#define mmRMI_UTC_UNIT_CONFIG 0x078d
1083#define mmRMI_UTC_UNIT_CONFIG_BASE_IDX 0
1084#define mmRMI_TCIW_FORMATTER0_CNTL 0x078e
1085#define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 0
1086#define mmRMI_TCIW_FORMATTER1_CNTL 0x078f
1087#define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 0
1088#define mmRMI_SCOREBOARD_CNTL 0x0790
1089#define mmRMI_SCOREBOARD_CNTL_BASE_IDX 0
1090#define mmRMI_SCOREBOARD_STATUS0 0x0791
1091#define mmRMI_SCOREBOARD_STATUS0_BASE_IDX 0
1092#define mmRMI_SCOREBOARD_STATUS1 0x0792
1093#define mmRMI_SCOREBOARD_STATUS1_BASE_IDX 0
1094#define mmRMI_SCOREBOARD_STATUS2 0x0793
1095#define mmRMI_SCOREBOARD_STATUS2_BASE_IDX 0
1096#define mmRMI_XBAR_ARBITER_CONFIG 0x0794
1097#define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX 0
1098#define mmRMI_XBAR_ARBITER_CONFIG_1 0x0795
1099#define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 0
1100#define mmRMI_CLOCK_CNTRL 0x0796
1101#define mmRMI_CLOCK_CNTRL_BASE_IDX 0
1102#define mmRMI_UTCL1_STATUS 0x0797
1103#define mmRMI_UTCL1_STATUS_BASE_IDX 0
1104#define mmRMI_XNACK_DEBUG 0x079d
1105#define mmRMI_XNACK_DEBUG_BASE_IDX 0
1106#define mmRMI_SPARE 0x079e
1107#define mmRMI_SPARE_BASE_IDX 0
1108#define mmRMI_SPARE_1 0x079f
1109#define mmRMI_SPARE_1_BASE_IDX 0
1110#define mmRMI_SPARE_2 0x07a0
1111#define mmRMI_SPARE_2_BASE_IDX 0
1112
1113
1114// addressBlock: gc_utcl2_atcl2dec
1115// base address: 0xa000
1116#define mmATC_L2_CNTL 0x0800
1117#define mmATC_L2_CNTL_BASE_IDX 0
1118#define mmATC_L2_CNTL2 0x0801
1119#define mmATC_L2_CNTL2_BASE_IDX 0
1120#define mmATC_L2_CACHE_DATA0 0x0804
1121#define mmATC_L2_CACHE_DATA0_BASE_IDX 0
1122#define mmATC_L2_CACHE_DATA1 0x0805
1123#define mmATC_L2_CACHE_DATA1_BASE_IDX 0
1124#define mmATC_L2_CACHE_DATA2 0x0806
1125#define mmATC_L2_CACHE_DATA2_BASE_IDX 0
1126#define mmATC_L2_CNTL3 0x0807
1127#define mmATC_L2_CNTL3_BASE_IDX 0
1128#define mmATC_L2_STATUS 0x0808
1129#define mmATC_L2_STATUS_BASE_IDX 0
1130#define mmATC_L2_STATUS2 0x0809
1131#define mmATC_L2_STATUS2_BASE_IDX 0
1132#define mmATC_L2_MISC_CG 0x080a
1133#define mmATC_L2_MISC_CG_BASE_IDX 0
1134#define mmATC_L2_MEM_POWER_LS 0x080b
1135#define mmATC_L2_MEM_POWER_LS_BASE_IDX 0
1136#define mmATC_L2_CGTT_CLK_CTRL 0x080c
1137#define mmATC_L2_CGTT_CLK_CTRL_BASE_IDX 0
1138
1139
1140// addressBlock: gc_utcl2_vml2pfdec
1141// base address: 0xa100
1142#define mmVM_L2_CNTL 0x0840
1143#define mmVM_L2_CNTL_BASE_IDX 0
1144#define mmVM_L2_CNTL2 0x0841
1145#define mmVM_L2_CNTL2_BASE_IDX 0
1146#define mmVM_L2_CNTL3 0x0842
1147#define mmVM_L2_CNTL3_BASE_IDX 0
1148#define mmVM_L2_STATUS 0x0843
1149#define mmVM_L2_STATUS_BASE_IDX 0
1150#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0844
1151#define mmVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0
1152#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0845
1153#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0
1154#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0846
1155#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0
1156#define mmVM_L2_PROTECTION_FAULT_CNTL 0x0847
1157#define mmVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0
1158#define mmVM_L2_PROTECTION_FAULT_CNTL2 0x0848
1159#define mmVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0
1160#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0x0849
1161#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0
1162#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0x084a
1163#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0
1164#define mmVM_L2_PROTECTION_FAULT_STATUS 0x084b
1165#define mmVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0
1166#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0x084c
1167#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0
1168#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0x084d
1169#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0
1170#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x084e
1171#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
1172#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x084f
1173#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
1174#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0851
1175#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
1176#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0852
1177#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0
1178#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0853
1179#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0
1180#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0854
1181#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0
1182#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0855
1183#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0
1184#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0856
1185#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0
1186#define mmVM_L2_CNTL4 0x0857
1187#define mmVM_L2_CNTL4_BASE_IDX 0
1188#define mmVM_L2_MM_GROUP_RT_CLASSES 0x0858
1189#define mmVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0
1190#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x0859
1191#define mmVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0
1192#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x085a
1193#define mmVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
1194#define mmVM_L2_CACHE_PARITY_CNTL 0x085b
1195#define mmVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
1196#define mmVM_L2_CGTT_CLK_CTRL 0x085e
1197#define mmVM_L2_CGTT_CLK_CTRL_BASE_IDX 0
1198
1199
1200// addressBlock: gc_utcl2_vml2vcdec
1201// base address: 0xa200
1202#define mmVM_CONTEXT0_CNTL 0x0880
1203#define mmVM_CONTEXT0_CNTL_BASE_IDX 0
1204#define mmVM_CONTEXT1_CNTL 0x0881
1205#define mmVM_CONTEXT1_CNTL_BASE_IDX 0
1206#define mmVM_CONTEXT2_CNTL 0x0882
1207#define mmVM_CONTEXT2_CNTL_BASE_IDX 0
1208#define mmVM_CONTEXT3_CNTL 0x0883
1209#define mmVM_CONTEXT3_CNTL_BASE_IDX 0
1210#define mmVM_CONTEXT4_CNTL 0x0884
1211#define mmVM_CONTEXT4_CNTL_BASE_IDX 0
1212#define mmVM_CONTEXT5_CNTL 0x0885
1213#define mmVM_CONTEXT5_CNTL_BASE_IDX 0
1214#define mmVM_CONTEXT6_CNTL 0x0886
1215#define mmVM_CONTEXT6_CNTL_BASE_IDX 0
1216#define mmVM_CONTEXT7_CNTL 0x0887
1217#define mmVM_CONTEXT7_CNTL_BASE_IDX 0
1218#define mmVM_CONTEXT8_CNTL 0x0888
1219#define mmVM_CONTEXT8_CNTL_BASE_IDX 0
1220#define mmVM_CONTEXT9_CNTL 0x0889
1221#define mmVM_CONTEXT9_CNTL_BASE_IDX 0
1222#define mmVM_CONTEXT10_CNTL 0x088a
1223#define mmVM_CONTEXT10_CNTL_BASE_IDX 0
1224#define mmVM_CONTEXT11_CNTL 0x088b
1225#define mmVM_CONTEXT11_CNTL_BASE_IDX 0
1226#define mmVM_CONTEXT12_CNTL 0x088c
1227#define mmVM_CONTEXT12_CNTL_BASE_IDX 0
1228#define mmVM_CONTEXT13_CNTL 0x088d
1229#define mmVM_CONTEXT13_CNTL_BASE_IDX 0
1230#define mmVM_CONTEXT14_CNTL 0x088e
1231#define mmVM_CONTEXT14_CNTL_BASE_IDX 0
1232#define mmVM_CONTEXT15_CNTL 0x088f
1233#define mmVM_CONTEXT15_CNTL_BASE_IDX 0
1234#define mmVM_CONTEXTS_DISABLE 0x0890
1235#define mmVM_CONTEXTS_DISABLE_BASE_IDX 0
1236#define mmVM_INVALIDATE_ENG0_SEM 0x0891
1237#define mmVM_INVALIDATE_ENG0_SEM_BASE_IDX 0
1238#define mmVM_INVALIDATE_ENG1_SEM 0x0892
1239#define mmVM_INVALIDATE_ENG1_SEM_BASE_IDX 0
1240#define mmVM_INVALIDATE_ENG2_SEM 0x0893
1241#define mmVM_INVALIDATE_ENG2_SEM_BASE_IDX 0
1242#define mmVM_INVALIDATE_ENG3_SEM 0x0894
1243#define mmVM_INVALIDATE_ENG3_SEM_BASE_IDX 0
1244#define mmVM_INVALIDATE_ENG4_SEM 0x0895
1245#define mmVM_INVALIDATE_ENG4_SEM_BASE_IDX 0
1246#define mmVM_INVALIDATE_ENG5_SEM 0x0896
1247#define mmVM_INVALIDATE_ENG5_SEM_BASE_IDX 0
1248#define mmVM_INVALIDATE_ENG6_SEM 0x0897
1249#define mmVM_INVALIDATE_ENG6_SEM_BASE_IDX 0
1250#define mmVM_INVALIDATE_ENG7_SEM 0x0898
1251#define mmVM_INVALIDATE_ENG7_SEM_BASE_IDX 0
1252#define mmVM_INVALIDATE_ENG8_SEM 0x0899
1253#define mmVM_INVALIDATE_ENG8_SEM_BASE_IDX 0
1254#define mmVM_INVALIDATE_ENG9_SEM 0x089a
1255#define mmVM_INVALIDATE_ENG9_SEM_BASE_IDX 0
1256#define mmVM_INVALIDATE_ENG10_SEM 0x089b
1257#define mmVM_INVALIDATE_ENG10_SEM_BASE_IDX 0
1258#define mmVM_INVALIDATE_ENG11_SEM 0x089c
1259#define mmVM_INVALIDATE_ENG11_SEM_BASE_IDX 0
1260#define mmVM_INVALIDATE_ENG12_SEM 0x089d
1261#define mmVM_INVALIDATE_ENG12_SEM_BASE_IDX 0
1262#define mmVM_INVALIDATE_ENG13_SEM 0x089e
1263#define mmVM_INVALIDATE_ENG13_SEM_BASE_IDX 0
1264#define mmVM_INVALIDATE_ENG14_SEM 0x089f
1265#define mmVM_INVALIDATE_ENG14_SEM_BASE_IDX 0
1266#define mmVM_INVALIDATE_ENG15_SEM 0x08a0
1267#define mmVM_INVALIDATE_ENG15_SEM_BASE_IDX 0
1268#define mmVM_INVALIDATE_ENG16_SEM 0x08a1
1269#define mmVM_INVALIDATE_ENG16_SEM_BASE_IDX 0
1270#define mmVM_INVALIDATE_ENG17_SEM 0x08a2
1271#define mmVM_INVALIDATE_ENG17_SEM_BASE_IDX 0
1272#define mmVM_INVALIDATE_ENG0_REQ 0x08a3
1273#define mmVM_INVALIDATE_ENG0_REQ_BASE_IDX 0
1274#define mmVM_INVALIDATE_ENG1_REQ 0x08a4
1275#define mmVM_INVALIDATE_ENG1_REQ_BASE_IDX 0
1276#define mmVM_INVALIDATE_ENG2_REQ 0x08a5
1277#define mmVM_INVALIDATE_ENG2_REQ_BASE_IDX 0
1278#define mmVM_INVALIDATE_ENG3_REQ 0x08a6
1279#define mmVM_INVALIDATE_ENG3_REQ_BASE_IDX 0
1280#define mmVM_INVALIDATE_ENG4_REQ 0x08a7
1281#define mmVM_INVALIDATE_ENG4_REQ_BASE_IDX 0
1282#define mmVM_INVALIDATE_ENG5_REQ 0x08a8
1283#define mmVM_INVALIDATE_ENG5_REQ_BASE_IDX 0
1284#define mmVM_INVALIDATE_ENG6_REQ 0x08a9
1285#define mmVM_INVALIDATE_ENG6_REQ_BASE_IDX 0
1286#define mmVM_INVALIDATE_ENG7_REQ 0x08aa
1287#define mmVM_INVALIDATE_ENG7_REQ_BASE_IDX 0
1288#define mmVM_INVALIDATE_ENG8_REQ 0x08ab
1289#define mmVM_INVALIDATE_ENG8_REQ_BASE_IDX 0
1290#define mmVM_INVALIDATE_ENG9_REQ 0x08ac
1291#define mmVM_INVALIDATE_ENG9_REQ_BASE_IDX 0
1292#define mmVM_INVALIDATE_ENG10_REQ 0x08ad
1293#define mmVM_INVALIDATE_ENG10_REQ_BASE_IDX 0
1294#define mmVM_INVALIDATE_ENG11_REQ 0x08ae
1295#define mmVM_INVALIDATE_ENG11_REQ_BASE_IDX 0
1296#define mmVM_INVALIDATE_ENG12_REQ 0x08af
1297#define mmVM_INVALIDATE_ENG12_REQ_BASE_IDX 0
1298#define mmVM_INVALIDATE_ENG13_REQ 0x08b0
1299#define mmVM_INVALIDATE_ENG13_REQ_BASE_IDX 0
1300#define mmVM_INVALIDATE_ENG14_REQ 0x08b1
1301#define mmVM_INVALIDATE_ENG14_REQ_BASE_IDX 0
1302#define mmVM_INVALIDATE_ENG15_REQ 0x08b2
1303#define mmVM_INVALIDATE_ENG15_REQ_BASE_IDX 0
1304#define mmVM_INVALIDATE_ENG16_REQ 0x08b3
1305#define mmVM_INVALIDATE_ENG16_REQ_BASE_IDX 0
1306#define mmVM_INVALIDATE_ENG17_REQ 0x08b4
1307#define mmVM_INVALIDATE_ENG17_REQ_BASE_IDX 0
1308#define mmVM_INVALIDATE_ENG0_ACK 0x08b5
1309#define mmVM_INVALIDATE_ENG0_ACK_BASE_IDX 0
1310#define mmVM_INVALIDATE_ENG1_ACK 0x08b6
1311#define mmVM_INVALIDATE_ENG1_ACK_BASE_IDX 0
1312#define mmVM_INVALIDATE_ENG2_ACK 0x08b7
1313#define mmVM_INVALIDATE_ENG2_ACK_BASE_IDX 0
1314#define mmVM_INVALIDATE_ENG3_ACK 0x08b8
1315#define mmVM_INVALIDATE_ENG3_ACK_BASE_IDX 0
1316#define mmVM_INVALIDATE_ENG4_ACK 0x08b9
1317#define mmVM_INVALIDATE_ENG4_ACK_BASE_IDX 0
1318#define mmVM_INVALIDATE_ENG5_ACK 0x08ba
1319#define mmVM_INVALIDATE_ENG5_ACK_BASE_IDX 0
1320#define mmVM_INVALIDATE_ENG6_ACK 0x08bb
1321#define mmVM_INVALIDATE_ENG6_ACK_BASE_IDX 0
1322#define mmVM_INVALIDATE_ENG7_ACK 0x08bc
1323#define mmVM_INVALIDATE_ENG7_ACK_BASE_IDX 0
1324#define mmVM_INVALIDATE_ENG8_ACK 0x08bd
1325#define mmVM_INVALIDATE_ENG8_ACK_BASE_IDX 0
1326#define mmVM_INVALIDATE_ENG9_ACK 0x08be
1327#define mmVM_INVALIDATE_ENG9_ACK_BASE_IDX 0
1328#define mmVM_INVALIDATE_ENG10_ACK 0x08bf
1329#define mmVM_INVALIDATE_ENG10_ACK_BASE_IDX 0
1330#define mmVM_INVALIDATE_ENG11_ACK 0x08c0
1331#define mmVM_INVALIDATE_ENG11_ACK_BASE_IDX 0
1332#define mmVM_INVALIDATE_ENG12_ACK 0x08c1
1333#define mmVM_INVALIDATE_ENG12_ACK_BASE_IDX 0
1334#define mmVM_INVALIDATE_ENG13_ACK 0x08c2
1335#define mmVM_INVALIDATE_ENG13_ACK_BASE_IDX 0
1336#define mmVM_INVALIDATE_ENG14_ACK 0x08c3
1337#define mmVM_INVALIDATE_ENG14_ACK_BASE_IDX 0
1338#define mmVM_INVALIDATE_ENG15_ACK 0x08c4
1339#define mmVM_INVALIDATE_ENG15_ACK_BASE_IDX 0
1340#define mmVM_INVALIDATE_ENG16_ACK 0x08c5
1341#define mmVM_INVALIDATE_ENG16_ACK_BASE_IDX 0
1342#define mmVM_INVALIDATE_ENG17_ACK 0x08c6
1343#define mmVM_INVALIDATE_ENG17_ACK_BASE_IDX 0
1344#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x08c7
1345#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0
1346#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x08c8
1347#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0
1348#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x08c9
1349#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0
1350#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x08ca
1351#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0
1352#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x08cb
1353#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0
1354#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x08cc
1355#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0
1356#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x08cd
1357#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0
1358#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x08ce
1359#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0
1360#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x08cf
1361#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0
1362#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x08d0
1363#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0
1364#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x08d1
1365#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0
1366#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x08d2
1367#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0
1368#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x08d3
1369#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0
1370#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x08d4
1371#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0
1372#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x08d5
1373#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0
1374#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x08d6
1375#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0
1376#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x08d7
1377#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0
1378#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x08d8
1379#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0
1380#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x08d9
1381#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0
1382#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x08da
1383#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0
1384#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x08db
1385#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0
1386#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x08dc
1387#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0
1388#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x08dd
1389#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0
1390#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x08de
1391#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0
1392#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x08df
1393#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0
1394#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08e0
1395#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0
1396#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08e1
1397#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0
1398#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08e2
1399#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0
1400#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08e3
1401#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0
1402#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08e4
1403#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0
1404#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08e5
1405#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0
1406#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08e6
1407#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0
1408#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08e7
1409#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0
1410#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08e8
1411#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0
1412#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08e9
1413#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0
1414#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08ea
1415#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0
1416#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08eb
1417#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1418#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ec
1419#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1420#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ed
1421#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1422#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ee
1423#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1424#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08ef
1425#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1426#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08f0
1427#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1428#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08f1
1429#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1430#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08f2
1431#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1432#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08f3
1433#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1434#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08f4
1435#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1436#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08f5
1437#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1438#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08f6
1439#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1440#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08f7
1441#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1442#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08f8
1443#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1444#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08f9
1445#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1446#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08fa
1447#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1448#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08fb
1449#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1450#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08fc
1451#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1452#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08fd
1453#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1454#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08fe
1455#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1456#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08ff
1457#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1458#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0900
1459#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1460#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0901
1461#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1462#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0902
1463#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1464#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0903
1465#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1466#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0904
1467#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1468#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0905
1469#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1470#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0906
1471#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1472#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0907
1473#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1474#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0908
1475#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1476#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0909
1477#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0
1478#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x090a
1479#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0
1480#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x090b
1481#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1482#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x090c
1483#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1484#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x090d
1485#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1486#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x090e
1487#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1488#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x090f
1489#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1490#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0910
1491#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1492#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0911
1493#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1494#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0912
1495#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1496#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0913
1497#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1498#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0914
1499#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1500#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0915
1501#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1502#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0916
1503#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1504#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0917
1505#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1506#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0918
1507#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1508#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0919
1509#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1510#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x091a
1511#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1512#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x091b
1513#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1514#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x091c
1515#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1516#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x091d
1517#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1518#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x091e
1519#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1520#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x091f
1521#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1522#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0920
1523#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1524#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0921
1525#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1526#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0922
1527#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1528#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0923
1529#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1530#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0924
1531#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1532#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0925
1533#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1534#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0926
1535#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1536#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0927
1537#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1538#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0928
1539#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1540#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0929
1541#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0
1542#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x092a
1543#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0
1544#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x092b
1545#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1546#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x092c
1547#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1548#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x092d
1549#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1550#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x092e
1551#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1552#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x092f
1553#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1554#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0930
1555#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1556#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0931
1557#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1558#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0932
1559#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1560#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0933
1561#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1562#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0934
1563#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1564#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0935
1565#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1566#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0936
1567#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1568#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0937
1569#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1570#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0938
1571#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1572#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0939
1573#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1574#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x093a
1575#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1576#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x093b
1577#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1578#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x093c
1579#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1580#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x093d
1581#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1582#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x093e
1583#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1584#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x093f
1585#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1586#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0940
1587#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1588#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0941
1589#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1590#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0942
1591#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1592#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0943
1593#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1594#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0944
1595#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1596#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0945
1597#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1598#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0946
1599#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1600#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0947
1601#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1602#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0948
1603#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1604#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0949
1605#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0
1606#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x094a
1607#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0
1608
1609
1610// addressBlock: gc_utcl2_vmsharedpfdec
1611// base address: 0xa590
1612#define mmMC_VM_NB_MMIOBASE 0x0964
1613#define mmMC_VM_NB_MMIOBASE_BASE_IDX 0
1614#define mmMC_VM_NB_MMIOLIMIT 0x0965
1615#define mmMC_VM_NB_MMIOLIMIT_BASE_IDX 0
1616#define mmMC_VM_NB_PCI_CTRL 0x0966
1617#define mmMC_VM_NB_PCI_CTRL_BASE_IDX 0
1618#define mmMC_VM_NB_PCI_ARB 0x0967
1619#define mmMC_VM_NB_PCI_ARB_BASE_IDX 0
1620#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0968
1621#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0
1622#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0969
1623#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0
1624#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0x096a
1625#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0
1626#define mmMC_VM_FB_OFFSET 0x096b
1627#define mmMC_VM_FB_OFFSET_BASE_IDX 0
1628#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x096c
1629#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0
1630#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x096d
1631#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0
1632#define mmMC_VM_STEERING 0x096e
1633#define mmMC_VM_STEERING_BASE_IDX 0
1634#define mmMC_SHARED_VIRT_RESET_REQ 0x096f
1635#define mmMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0
1636#define mmMC_MEM_POWER_LS 0x0970
1637#define mmMC_MEM_POWER_LS_BASE_IDX 0
1638#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0971
1639#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0
1640#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0972
1641#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0
1642#define mmMC_VM_APT_CNTL 0x0973
1643#define mmMC_VM_APT_CNTL_BASE_IDX 0
1644#define mmMC_VM_LOCAL_HBM_ADDRESS_START 0x0974
1645#define mmMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0
1646#define mmMC_VM_LOCAL_HBM_ADDRESS_END 0x0975
1647#define mmMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0
1648#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0976
1649#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0
1650
1651
1652// addressBlock: gc_utcl2_vmsharedvcdec
1653// base address: 0xa600
1654#define mmMC_VM_FB_LOCATION_BASE 0x0980
1655#define mmMC_VM_FB_LOCATION_BASE_BASE_IDX 0
1656#define mmMC_VM_FB_LOCATION_TOP 0x0981
1657#define mmMC_VM_FB_LOCATION_TOP_BASE_IDX 0
1658#define mmMC_VM_AGP_TOP 0x0982
1659#define mmMC_VM_AGP_TOP_BASE_IDX 0
1660#define mmMC_VM_AGP_BOT 0x0983
1661#define mmMC_VM_AGP_BOT_BASE_IDX 0
1662#define mmMC_VM_AGP_BASE 0x0984
1663#define mmMC_VM_AGP_BASE_BASE_IDX 0
1664#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0985
1665#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0
1666#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0986
1667#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0
1668#define mmMC_VM_MX_L1_TLB_CNTL 0x0987
1669#define mmMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0
1670
1671
1672// addressBlock: gc_tcdec
1673// base address: 0xac00
1674#define mmTCP_INVALIDATE 0x0b00
1675#define mmTCP_INVALIDATE_BASE_IDX 0
1676#define mmTCP_STATUS 0x0b01
1677#define mmTCP_STATUS_BASE_IDX 0
1678#define mmTCP_CNTL 0x0b02
1679#define mmTCP_CNTL_BASE_IDX 0
1680#define mmTCP_CHAN_STEER_LO 0x0b03
1681#define mmTCP_CHAN_STEER_LO_BASE_IDX 0
1682#define mmTCP_CHAN_STEER_HI 0x0b04
1683#define mmTCP_CHAN_STEER_HI_BASE_IDX 0
1684#define mmTCP_ADDR_CONFIG 0x0b05
1685#define mmTCP_ADDR_CONFIG_BASE_IDX 0
1686#define mmTCP_CREDIT 0x0b06
1687#define mmTCP_CREDIT_BASE_IDX 0
1688#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x0b16
1689#define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0
1690#define mmTCP_EDC_CNT 0x0b17
1691#define mmTCP_EDC_CNT_BASE_IDX 0
1692#define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a
1693#define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0
1694#define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b
1695#define mmTC_CFG_L1_LOAD_POLICY1_BASE_IDX 0
1696#define mmTC_CFG_L1_STORE_POLICY 0x0b1c
1697#define mmTC_CFG_L1_STORE_POLICY_BASE_IDX 0
1698#define mmTC_CFG_L2_LOAD_POLICY0 0x0b1d
1699#define mmTC_CFG_L2_LOAD_POLICY0_BASE_IDX 0
1700#define mmTC_CFG_L2_LOAD_POLICY1 0x0b1e
1701#define mmTC_CFG_L2_LOAD_POLICY1_BASE_IDX 0
1702#define mmTC_CFG_L2_STORE_POLICY0 0x0b1f
1703#define mmTC_CFG_L2_STORE_POLICY0_BASE_IDX 0
1704#define mmTC_CFG_L2_STORE_POLICY1 0x0b20
1705#define mmTC_CFG_L2_STORE_POLICY1_BASE_IDX 0
1706#define mmTC_CFG_L2_ATOMIC_POLICY 0x0b21
1707#define mmTC_CFG_L2_ATOMIC_POLICY_BASE_IDX 0
1708#define mmTC_CFG_L1_VOLATILE 0x0b22
1709#define mmTC_CFG_L1_VOLATILE_BASE_IDX 0
1710#define mmTC_CFG_L2_VOLATILE 0x0b23
1711#define mmTC_CFG_L2_VOLATILE_BASE_IDX 0
1712#define mmTCI_STATUS 0x0b61
1713#define mmTCI_STATUS_BASE_IDX 0
1714#define mmTCI_CNTL_1 0x0b62
1715#define mmTCI_CNTL_1_BASE_IDX 0
1716#define mmTCI_CNTL_2 0x0b63
1717#define mmTCI_CNTL_2_BASE_IDX 0
1718#define mmTCC_CTRL 0x0b80
1719#define mmTCC_CTRL_BASE_IDX 0
1720#define mmTCC_CTRL2 0x0b81
1721#define mmTCC_CTRL2_BASE_IDX 0
1722#define mmTCC_EDC_CNT 0x0b82
1723#define mmTCC_EDC_CNT_BASE_IDX 0
1724#define mmTCC_EDC_CNT2 0x0b83
1725#define mmTCC_EDC_CNT2_BASE_IDX 0
1726#define mmTCC_REDUNDANCY 0x0b84
1727#define mmTCC_REDUNDANCY_BASE_IDX 0
1728#define mmTCC_EXE_DISABLE 0x0b85
1729#define mmTCC_EXE_DISABLE_BASE_IDX 0
1730#define mmTCC_DSM_CNTL 0x0b86
1731#define mmTCC_DSM_CNTL_BASE_IDX 0
1732#define mmTCC_DSM_CNTLA 0x0b87
1733#define mmTCC_DSM_CNTLA_BASE_IDX 0
1734#define mmTCC_DSM_CNTL2 0x0b88
1735#define mmTCC_DSM_CNTL2_BASE_IDX 0
1736#define mmTCC_DSM_CNTL2A 0x0b89
1737#define mmTCC_DSM_CNTL2A_BASE_IDX 0
1738#define mmTCC_DSM_CNTL2B 0x0b8a
1739#define mmTCC_DSM_CNTL2B_BASE_IDX 0
1740#define mmTCC_WBINVL2 0x0b8b
1741#define mmTCC_WBINVL2_BASE_IDX 0
1742#define mmTCC_SOFT_RESET 0x0b8c
1743#define mmTCC_SOFT_RESET_BASE_IDX 0
1744#define mmTCA_CTRL 0x0bc0
1745#define mmTCA_CTRL_BASE_IDX 0
1746#define mmTCA_BURST_MASK 0x0bc1
1747#define mmTCA_BURST_MASK_BASE_IDX 0
1748#define mmTCA_BURST_CTRL 0x0bc2
1749#define mmTCA_BURST_CTRL_BASE_IDX 0
1750#define mmTCA_DSM_CNTL 0x0bc3
1751#define mmTCA_DSM_CNTL_BASE_IDX 0
1752#define mmTCA_DSM_CNTL2 0x0bc4
1753#define mmTCA_DSM_CNTL2_BASE_IDX 0
1754#define mmTCA_EDC_CNT 0x0bc5
1755#define mmTCA_EDC_CNT_BASE_IDX 0
1756
1757
1758// addressBlock: gc_shdec
1759// base address: 0xb000
1760#define mmSPI_SHADER_PGM_RSRC3_PS 0x0c07
1761#define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0
1762#define mmSPI_SHADER_PGM_LO_PS 0x0c08
1763#define mmSPI_SHADER_PGM_LO_PS_BASE_IDX 0
1764#define mmSPI_SHADER_PGM_HI_PS 0x0c09
1765#define mmSPI_SHADER_PGM_HI_PS_BASE_IDX 0
1766#define mmSPI_SHADER_PGM_RSRC1_PS 0x0c0a
1767#define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0
1768#define mmSPI_SHADER_PGM_RSRC2_PS 0x0c0b
1769#define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0
1770#define mmSPI_SHADER_USER_DATA_PS_0 0x0c0c
1771#define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0
1772#define mmSPI_SHADER_USER_DATA_PS_1 0x0c0d
1773#define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0
1774#define mmSPI_SHADER_USER_DATA_PS_2 0x0c0e
1775#define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0
1776#define mmSPI_SHADER_USER_DATA_PS_3 0x0c0f
1777#define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0
1778#define mmSPI_SHADER_USER_DATA_PS_4 0x0c10
1779#define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0
1780#define mmSPI_SHADER_USER_DATA_PS_5 0x0c11
1781#define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0
1782#define mmSPI_SHADER_USER_DATA_PS_6 0x0c12
1783#define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0
1784#define mmSPI_SHADER_USER_DATA_PS_7 0x0c13
1785#define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0
1786#define mmSPI_SHADER_USER_DATA_PS_8 0x0c14
1787#define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0
1788#define mmSPI_SHADER_USER_DATA_PS_9 0x0c15
1789#define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0
1790#define mmSPI_SHADER_USER_DATA_PS_10 0x0c16
1791#define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0
1792#define mmSPI_SHADER_USER_DATA_PS_11 0x0c17
1793#define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0
1794#define mmSPI_SHADER_USER_DATA_PS_12 0x0c18
1795#define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0
1796#define mmSPI_SHADER_USER_DATA_PS_13 0x0c19
1797#define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0
1798#define mmSPI_SHADER_USER_DATA_PS_14 0x0c1a
1799#define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0
1800#define mmSPI_SHADER_USER_DATA_PS_15 0x0c1b
1801#define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0
1802#define mmSPI_SHADER_USER_DATA_PS_16 0x0c1c
1803#define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0
1804#define mmSPI_SHADER_USER_DATA_PS_17 0x0c1d
1805#define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0
1806#define mmSPI_SHADER_USER_DATA_PS_18 0x0c1e
1807#define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0
1808#define mmSPI_SHADER_USER_DATA_PS_19 0x0c1f
1809#define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0
1810#define mmSPI_SHADER_USER_DATA_PS_20 0x0c20
1811#define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0
1812#define mmSPI_SHADER_USER_DATA_PS_21 0x0c21
1813#define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0
1814#define mmSPI_SHADER_USER_DATA_PS_22 0x0c22
1815#define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0
1816#define mmSPI_SHADER_USER_DATA_PS_23 0x0c23
1817#define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0
1818#define mmSPI_SHADER_USER_DATA_PS_24 0x0c24
1819#define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0
1820#define mmSPI_SHADER_USER_DATA_PS_25 0x0c25
1821#define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0
1822#define mmSPI_SHADER_USER_DATA_PS_26 0x0c26
1823#define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0
1824#define mmSPI_SHADER_USER_DATA_PS_27 0x0c27
1825#define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0
1826#define mmSPI_SHADER_USER_DATA_PS_28 0x0c28
1827#define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0
1828#define mmSPI_SHADER_USER_DATA_PS_29 0x0c29
1829#define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0
1830#define mmSPI_SHADER_USER_DATA_PS_30 0x0c2a
1831#define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0
1832#define mmSPI_SHADER_USER_DATA_PS_31 0x0c2b
1833#define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0
1834#define mmSPI_SHADER_PGM_RSRC3_VS 0x0c46
1835#define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX 0
1836#define mmSPI_SHADER_LATE_ALLOC_VS 0x0c47
1837#define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX 0
1838#define mmSPI_SHADER_PGM_LO_VS 0x0c48
1839#define mmSPI_SHADER_PGM_LO_VS_BASE_IDX 0
1840#define mmSPI_SHADER_PGM_HI_VS 0x0c49
1841#define mmSPI_SHADER_PGM_HI_VS_BASE_IDX 0
1842#define mmSPI_SHADER_PGM_RSRC1_VS 0x0c4a
1843#define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX 0
1844#define mmSPI_SHADER_PGM_RSRC2_VS 0x0c4b
1845#define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX 0
1846#define mmSPI_SHADER_USER_DATA_VS_0 0x0c4c
1847#define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX 0
1848#define mmSPI_SHADER_USER_DATA_VS_1 0x0c4d
1849#define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX 0
1850#define mmSPI_SHADER_USER_DATA_VS_2 0x0c4e
1851#define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX 0
1852#define mmSPI_SHADER_USER_DATA_VS_3 0x0c4f
1853#define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX 0
1854#define mmSPI_SHADER_USER_DATA_VS_4 0x0c50
1855#define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX 0
1856#define mmSPI_SHADER_USER_DATA_VS_5 0x0c51
1857#define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX 0
1858#define mmSPI_SHADER_USER_DATA_VS_6 0x0c52
1859#define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX 0
1860#define mmSPI_SHADER_USER_DATA_VS_7 0x0c53
1861#define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX 0
1862#define mmSPI_SHADER_USER_DATA_VS_8 0x0c54
1863#define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX 0
1864#define mmSPI_SHADER_USER_DATA_VS_9 0x0c55
1865#define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX 0
1866#define mmSPI_SHADER_USER_DATA_VS_10 0x0c56
1867#define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX 0
1868#define mmSPI_SHADER_USER_DATA_VS_11 0x0c57
1869#define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX 0
1870#define mmSPI_SHADER_USER_DATA_VS_12 0x0c58
1871#define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX 0
1872#define mmSPI_SHADER_USER_DATA_VS_13 0x0c59
1873#define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX 0
1874#define mmSPI_SHADER_USER_DATA_VS_14 0x0c5a
1875#define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX 0
1876#define mmSPI_SHADER_USER_DATA_VS_15 0x0c5b
1877#define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX 0
1878#define mmSPI_SHADER_USER_DATA_VS_16 0x0c5c
1879#define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX 0
1880#define mmSPI_SHADER_USER_DATA_VS_17 0x0c5d
1881#define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX 0
1882#define mmSPI_SHADER_USER_DATA_VS_18 0x0c5e
1883#define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX 0
1884#define mmSPI_SHADER_USER_DATA_VS_19 0x0c5f
1885#define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX 0
1886#define mmSPI_SHADER_USER_DATA_VS_20 0x0c60
1887#define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX 0
1888#define mmSPI_SHADER_USER_DATA_VS_21 0x0c61
1889#define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX 0
1890#define mmSPI_SHADER_USER_DATA_VS_22 0x0c62
1891#define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX 0
1892#define mmSPI_SHADER_USER_DATA_VS_23 0x0c63
1893#define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX 0
1894#define mmSPI_SHADER_USER_DATA_VS_24 0x0c64
1895#define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX 0
1896#define mmSPI_SHADER_USER_DATA_VS_25 0x0c65
1897#define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX 0
1898#define mmSPI_SHADER_USER_DATA_VS_26 0x0c66
1899#define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX 0
1900#define mmSPI_SHADER_USER_DATA_VS_27 0x0c67
1901#define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX 0
1902#define mmSPI_SHADER_USER_DATA_VS_28 0x0c68
1903#define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX 0
1904#define mmSPI_SHADER_USER_DATA_VS_29 0x0c69
1905#define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX 0
1906#define mmSPI_SHADER_USER_DATA_VS_30 0x0c6a
1907#define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX 0
1908#define mmSPI_SHADER_USER_DATA_VS_31 0x0c6b
1909#define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX 0
1910#define mmSPI_SHADER_PGM_RSRC2_GS_VS 0x0c7c
1911#define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX 0
1912#define mmSPI_SHADER_PGM_RSRC4_GS 0x0c81
1913#define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0
1914#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0x0c82
1915#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0
1916#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0x0c83
1917#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0
1918#define mmSPI_SHADER_PGM_LO_ES 0x0c84
1919#define mmSPI_SHADER_PGM_LO_ES_BASE_IDX 0
1920#define mmSPI_SHADER_PGM_HI_ES 0x0c85
1921#define mmSPI_SHADER_PGM_HI_ES_BASE_IDX 0
1922#define mmSPI_SHADER_PGM_RSRC3_GS 0x0c87
1923#define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0
1924#define mmSPI_SHADER_PGM_LO_GS 0x0c88
1925#define mmSPI_SHADER_PGM_LO_GS_BASE_IDX 0
1926#define mmSPI_SHADER_PGM_HI_GS 0x0c89
1927#define mmSPI_SHADER_PGM_HI_GS_BASE_IDX 0
1928#define mmSPI_SHADER_PGM_RSRC1_GS 0x0c8a
1929#define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0
1930#define mmSPI_SHADER_PGM_RSRC2_GS 0x0c8b
1931#define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0
1932#define mmSPI_SHADER_USER_DATA_ES_0 0x0ccc
1933#define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX 0
1934#define mmSPI_SHADER_USER_DATA_ES_1 0x0ccd
1935#define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX 0
1936#define mmSPI_SHADER_USER_DATA_ES_2 0x0cce
1937#define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX 0
1938#define mmSPI_SHADER_USER_DATA_ES_3 0x0ccf
1939#define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX 0
1940#define mmSPI_SHADER_USER_DATA_ES_4 0x0cd0
1941#define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX 0
1942#define mmSPI_SHADER_USER_DATA_ES_5 0x0cd1
1943#define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX 0
1944#define mmSPI_SHADER_USER_DATA_ES_6 0x0cd2
1945#define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX 0
1946#define mmSPI_SHADER_USER_DATA_ES_7 0x0cd3
1947#define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX 0
1948#define mmSPI_SHADER_USER_DATA_ES_8 0x0cd4
1949#define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX 0
1950#define mmSPI_SHADER_USER_DATA_ES_9 0x0cd5
1951#define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX 0
1952#define mmSPI_SHADER_USER_DATA_ES_10 0x0cd6
1953#define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX 0
1954#define mmSPI_SHADER_USER_DATA_ES_11 0x0cd7
1955#define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX 0
1956#define mmSPI_SHADER_USER_DATA_ES_12 0x0cd8
1957#define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX 0
1958#define mmSPI_SHADER_USER_DATA_ES_13 0x0cd9
1959#define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX 0
1960#define mmSPI_SHADER_USER_DATA_ES_14 0x0cda
1961#define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX 0
1962#define mmSPI_SHADER_USER_DATA_ES_15 0x0cdb
1963#define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX 0
1964#define mmSPI_SHADER_USER_DATA_ES_16 0x0cdc
1965#define mmSPI_SHADER_USER_DATA_ES_16_BASE_IDX 0
1966#define mmSPI_SHADER_USER_DATA_ES_17 0x0cdd
1967#define mmSPI_SHADER_USER_DATA_ES_17_BASE_IDX 0
1968#define mmSPI_SHADER_USER_DATA_ES_18 0x0cde
1969#define mmSPI_SHADER_USER_DATA_ES_18_BASE_IDX 0
1970#define mmSPI_SHADER_USER_DATA_ES_19 0x0cdf
1971#define mmSPI_SHADER_USER_DATA_ES_19_BASE_IDX 0
1972#define mmSPI_SHADER_USER_DATA_ES_20 0x0ce0
1973#define mmSPI_SHADER_USER_DATA_ES_20_BASE_IDX 0
1974#define mmSPI_SHADER_USER_DATA_ES_21 0x0ce1
1975#define mmSPI_SHADER_USER_DATA_ES_21_BASE_IDX 0
1976#define mmSPI_SHADER_USER_DATA_ES_22 0x0ce2
1977#define mmSPI_SHADER_USER_DATA_ES_22_BASE_IDX 0
1978#define mmSPI_SHADER_USER_DATA_ES_23 0x0ce3
1979#define mmSPI_SHADER_USER_DATA_ES_23_BASE_IDX 0
1980#define mmSPI_SHADER_USER_DATA_ES_24 0x0ce4
1981#define mmSPI_SHADER_USER_DATA_ES_24_BASE_IDX 0
1982#define mmSPI_SHADER_USER_DATA_ES_25 0x0ce5
1983#define mmSPI_SHADER_USER_DATA_ES_25_BASE_IDX 0
1984#define mmSPI_SHADER_USER_DATA_ES_26 0x0ce6
1985#define mmSPI_SHADER_USER_DATA_ES_26_BASE_IDX 0
1986#define mmSPI_SHADER_USER_DATA_ES_27 0x0ce7
1987#define mmSPI_SHADER_USER_DATA_ES_27_BASE_IDX 0
1988#define mmSPI_SHADER_USER_DATA_ES_28 0x0ce8
1989#define mmSPI_SHADER_USER_DATA_ES_28_BASE_IDX 0
1990#define mmSPI_SHADER_USER_DATA_ES_29 0x0ce9
1991#define mmSPI_SHADER_USER_DATA_ES_29_BASE_IDX 0
1992#define mmSPI_SHADER_USER_DATA_ES_30 0x0cea
1993#define mmSPI_SHADER_USER_DATA_ES_30_BASE_IDX 0
1994#define mmSPI_SHADER_USER_DATA_ES_31 0x0ceb
1995#define mmSPI_SHADER_USER_DATA_ES_31_BASE_IDX 0
1996#define mmSPI_SHADER_PGM_RSRC4_HS 0x0d01
1997#define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0
1998#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0x0d02
1999#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0
2000#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0x0d03
2001#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0
2002#define mmSPI_SHADER_PGM_LO_LS 0x0d04
2003#define mmSPI_SHADER_PGM_LO_LS_BASE_IDX 0
2004#define mmSPI_SHADER_PGM_HI_LS 0x0d05
2005#define mmSPI_SHADER_PGM_HI_LS_BASE_IDX 0
2006#define mmSPI_SHADER_PGM_RSRC3_HS 0x0d07
2007#define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0
2008#define mmSPI_SHADER_PGM_LO_HS 0x0d08
2009#define mmSPI_SHADER_PGM_LO_HS_BASE_IDX 0
2010#define mmSPI_SHADER_PGM_HI_HS 0x0d09
2011#define mmSPI_SHADER_PGM_HI_HS_BASE_IDX 0
2012#define mmSPI_SHADER_PGM_RSRC1_HS 0x0d0a
2013#define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0
2014#define mmSPI_SHADER_PGM_RSRC2_HS 0x0d0b
2015#define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0
2016#define mmSPI_SHADER_USER_DATA_LS_0 0x0d0c
2017#define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX 0
2018#define mmSPI_SHADER_USER_DATA_LS_1 0x0d0d
2019#define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX 0
2020#define mmSPI_SHADER_USER_DATA_LS_2 0x0d0e
2021#define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX 0
2022#define mmSPI_SHADER_USER_DATA_LS_3 0x0d0f
2023#define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX 0
2024#define mmSPI_SHADER_USER_DATA_LS_4 0x0d10
2025#define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX 0
2026#define mmSPI_SHADER_USER_DATA_LS_5 0x0d11
2027#define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX 0
2028#define mmSPI_SHADER_USER_DATA_LS_6 0x0d12
2029#define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX 0
2030#define mmSPI_SHADER_USER_DATA_LS_7 0x0d13
2031#define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX 0
2032#define mmSPI_SHADER_USER_DATA_LS_8 0x0d14
2033#define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX 0
2034#define mmSPI_SHADER_USER_DATA_LS_9 0x0d15
2035#define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX 0
2036#define mmSPI_SHADER_USER_DATA_LS_10 0x0d16
2037#define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX 0
2038#define mmSPI_SHADER_USER_DATA_LS_11 0x0d17
2039#define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX 0
2040#define mmSPI_SHADER_USER_DATA_LS_12 0x0d18
2041#define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX 0
2042#define mmSPI_SHADER_USER_DATA_LS_13 0x0d19
2043#define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX 0
2044#define mmSPI_SHADER_USER_DATA_LS_14 0x0d1a
2045#define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX 0
2046#define mmSPI_SHADER_USER_DATA_LS_15 0x0d1b
2047#define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX 0
2048#define mmSPI_SHADER_USER_DATA_LS_16 0x0d1c
2049#define mmSPI_SHADER_USER_DATA_LS_16_BASE_IDX 0
2050#define mmSPI_SHADER_USER_DATA_LS_17 0x0d1d
2051#define mmSPI_SHADER_USER_DATA_LS_17_BASE_IDX 0
2052#define mmSPI_SHADER_USER_DATA_LS_18 0x0d1e
2053#define mmSPI_SHADER_USER_DATA_LS_18_BASE_IDX 0
2054#define mmSPI_SHADER_USER_DATA_LS_19 0x0d1f
2055#define mmSPI_SHADER_USER_DATA_LS_19_BASE_IDX 0
2056#define mmSPI_SHADER_USER_DATA_LS_20 0x0d20
2057#define mmSPI_SHADER_USER_DATA_LS_20_BASE_IDX 0
2058#define mmSPI_SHADER_USER_DATA_LS_21 0x0d21
2059#define mmSPI_SHADER_USER_DATA_LS_21_BASE_IDX 0
2060#define mmSPI_SHADER_USER_DATA_LS_22 0x0d22
2061#define mmSPI_SHADER_USER_DATA_LS_22_BASE_IDX 0
2062#define mmSPI_SHADER_USER_DATA_LS_23 0x0d23
2063#define mmSPI_SHADER_USER_DATA_LS_23_BASE_IDX 0
2064#define mmSPI_SHADER_USER_DATA_LS_24 0x0d24
2065#define mmSPI_SHADER_USER_DATA_LS_24_BASE_IDX 0
2066#define mmSPI_SHADER_USER_DATA_LS_25 0x0d25
2067#define mmSPI_SHADER_USER_DATA_LS_25_BASE_IDX 0
2068#define mmSPI_SHADER_USER_DATA_LS_26 0x0d26
2069#define mmSPI_SHADER_USER_DATA_LS_26_BASE_IDX 0
2070#define mmSPI_SHADER_USER_DATA_LS_27 0x0d27
2071#define mmSPI_SHADER_USER_DATA_LS_27_BASE_IDX 0
2072#define mmSPI_SHADER_USER_DATA_LS_28 0x0d28
2073#define mmSPI_SHADER_USER_DATA_LS_28_BASE_IDX 0
2074#define mmSPI_SHADER_USER_DATA_LS_29 0x0d29
2075#define mmSPI_SHADER_USER_DATA_LS_29_BASE_IDX 0
2076#define mmSPI_SHADER_USER_DATA_LS_30 0x0d2a
2077#define mmSPI_SHADER_USER_DATA_LS_30_BASE_IDX 0
2078#define mmSPI_SHADER_USER_DATA_LS_31 0x0d2b
2079#define mmSPI_SHADER_USER_DATA_LS_31_BASE_IDX 0
2080#define mmSPI_SHADER_USER_DATA_COMMON_0 0x0d4c
2081#define mmSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX 0
2082#define mmSPI_SHADER_USER_DATA_COMMON_1 0x0d4d
2083#define mmSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX 0
2084#define mmSPI_SHADER_USER_DATA_COMMON_2 0x0d4e
2085#define mmSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX 0
2086#define mmSPI_SHADER_USER_DATA_COMMON_3 0x0d4f
2087#define mmSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX 0
2088#define mmSPI_SHADER_USER_DATA_COMMON_4 0x0d50
2089#define mmSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX 0
2090#define mmSPI_SHADER_USER_DATA_COMMON_5 0x0d51
2091#define mmSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX 0
2092#define mmSPI_SHADER_USER_DATA_COMMON_6 0x0d52
2093#define mmSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX 0
2094#define mmSPI_SHADER_USER_DATA_COMMON_7 0x0d53
2095#define mmSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX 0
2096#define mmSPI_SHADER_USER_DATA_COMMON_8 0x0d54
2097#define mmSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX 0
2098#define mmSPI_SHADER_USER_DATA_COMMON_9 0x0d55
2099#define mmSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX 0
2100#define mmSPI_SHADER_USER_DATA_COMMON_10 0x0d56
2101#define mmSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX 0
2102#define mmSPI_SHADER_USER_DATA_COMMON_11 0x0d57
2103#define mmSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX 0
2104#define mmSPI_SHADER_USER_DATA_COMMON_12 0x0d58
2105#define mmSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX 0
2106#define mmSPI_SHADER_USER_DATA_COMMON_13 0x0d59
2107#define mmSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX 0
2108#define mmSPI_SHADER_USER_DATA_COMMON_14 0x0d5a
2109#define mmSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX 0
2110#define mmSPI_SHADER_USER_DATA_COMMON_15 0x0d5b
2111#define mmSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX 0
2112#define mmSPI_SHADER_USER_DATA_COMMON_16 0x0d5c
2113#define mmSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX 0
2114#define mmSPI_SHADER_USER_DATA_COMMON_17 0x0d5d
2115#define mmSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX 0
2116#define mmSPI_SHADER_USER_DATA_COMMON_18 0x0d5e
2117#define mmSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX 0
2118#define mmSPI_SHADER_USER_DATA_COMMON_19 0x0d5f
2119#define mmSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX 0
2120#define mmSPI_SHADER_USER_DATA_COMMON_20 0x0d60
2121#define mmSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX 0
2122#define mmSPI_SHADER_USER_DATA_COMMON_21 0x0d61
2123#define mmSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX 0
2124#define mmSPI_SHADER_USER_DATA_COMMON_22 0x0d62
2125#define mmSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX 0
2126#define mmSPI_SHADER_USER_DATA_COMMON_23 0x0d63
2127#define mmSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX 0
2128#define mmSPI_SHADER_USER_DATA_COMMON_24 0x0d64
2129#define mmSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX 0
2130#define mmSPI_SHADER_USER_DATA_COMMON_25 0x0d65
2131#define mmSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX 0
2132#define mmSPI_SHADER_USER_DATA_COMMON_26 0x0d66
2133#define mmSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX 0
2134#define mmSPI_SHADER_USER_DATA_COMMON_27 0x0d67
2135#define mmSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX 0
2136#define mmSPI_SHADER_USER_DATA_COMMON_28 0x0d68
2137#define mmSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX 0
2138#define mmSPI_SHADER_USER_DATA_COMMON_29 0x0d69
2139#define mmSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX 0
2140#define mmSPI_SHADER_USER_DATA_COMMON_30 0x0d6a
2141#define mmSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX 0
2142#define mmSPI_SHADER_USER_DATA_COMMON_31 0x0d6b
2143#define mmSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX 0
2144#define mmCOMPUTE_DISPATCH_INITIATOR 0x0e00
2145#define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0
2146#define mmCOMPUTE_DIM_X 0x0e01
2147#define mmCOMPUTE_DIM_X_BASE_IDX 0
2148#define mmCOMPUTE_DIM_Y 0x0e02
2149#define mmCOMPUTE_DIM_Y_BASE_IDX 0
2150#define mmCOMPUTE_DIM_Z 0x0e03
2151#define mmCOMPUTE_DIM_Z_BASE_IDX 0
2152#define mmCOMPUTE_START_X 0x0e04
2153#define mmCOMPUTE_START_X_BASE_IDX 0
2154#define mmCOMPUTE_START_Y 0x0e05
2155#define mmCOMPUTE_START_Y_BASE_IDX 0
2156#define mmCOMPUTE_START_Z 0x0e06
2157#define mmCOMPUTE_START_Z_BASE_IDX 0
2158#define mmCOMPUTE_NUM_THREAD_X 0x0e07
2159#define mmCOMPUTE_NUM_THREAD_X_BASE_IDX 0
2160#define mmCOMPUTE_NUM_THREAD_Y 0x0e08
2161#define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX 0
2162#define mmCOMPUTE_NUM_THREAD_Z 0x0e09
2163#define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX 0
2164#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x0e0a
2165#define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0
2166#define mmCOMPUTE_PERFCOUNT_ENABLE 0x0e0b
2167#define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0
2168#define mmCOMPUTE_PGM_LO 0x0e0c
2169#define mmCOMPUTE_PGM_LO_BASE_IDX 0
2170#define mmCOMPUTE_PGM_HI 0x0e0d
2171#define mmCOMPUTE_PGM_HI_BASE_IDX 0
2172#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0x0e0e
2173#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0
2174#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0x0e0f
2175#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0
2176#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x0e10
2177#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0
2178#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x0e11
2179#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0
2180#define mmCOMPUTE_PGM_RSRC1 0x0e12
2181#define mmCOMPUTE_PGM_RSRC1_BASE_IDX 0
2182#define mmCOMPUTE_PGM_RSRC2 0x0e13
2183#define mmCOMPUTE_PGM_RSRC2_BASE_IDX 0
2184#define mmCOMPUTE_VMID 0x0e14
2185#define mmCOMPUTE_VMID_BASE_IDX 0
2186#define mmCOMPUTE_RESOURCE_LIMITS 0x0e15
2187#define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0
2188#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x0e16
2189#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0
2190#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x0e17
2191#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0
2192#define mmCOMPUTE_TMPRING_SIZE 0x0e18
2193#define mmCOMPUTE_TMPRING_SIZE_BASE_IDX 0
2194#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x0e19
2195#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0
2196#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x0e1a
2197#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0
2198#define mmCOMPUTE_RESTART_X 0x0e1b
2199#define mmCOMPUTE_RESTART_X_BASE_IDX 0
2200#define mmCOMPUTE_RESTART_Y 0x0e1c
2201#define mmCOMPUTE_RESTART_Y_BASE_IDX 0
2202#define mmCOMPUTE_RESTART_Z 0x0e1d
2203#define mmCOMPUTE_RESTART_Z_BASE_IDX 0
2204#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x0e1e
2205#define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0
2206#define mmCOMPUTE_MISC_RESERVED 0x0e1f
2207#define mmCOMPUTE_MISC_RESERVED_BASE_IDX 0
2208#define mmCOMPUTE_DISPATCH_ID 0x0e20
2209#define mmCOMPUTE_DISPATCH_ID_BASE_IDX 0
2210#define mmCOMPUTE_THREADGROUP_ID 0x0e21
2211#define mmCOMPUTE_THREADGROUP_ID_BASE_IDX 0
2212#define mmCOMPUTE_RELAUNCH 0x0e22
2213#define mmCOMPUTE_RELAUNCH_BASE_IDX 0
2214#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x0e23
2215#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0
2216#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x0e24
2217#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0
2218#define mmCOMPUTE_USER_DATA_0 0x0e40
2219#define mmCOMPUTE_USER_DATA_0_BASE_IDX 0
2220#define mmCOMPUTE_USER_DATA_1 0x0e41
2221#define mmCOMPUTE_USER_DATA_1_BASE_IDX 0
2222#define mmCOMPUTE_USER_DATA_2 0x0e42
2223#define mmCOMPUTE_USER_DATA_2_BASE_IDX 0
2224#define mmCOMPUTE_USER_DATA_3 0x0e43
2225#define mmCOMPUTE_USER_DATA_3_BASE_IDX 0
2226#define mmCOMPUTE_USER_DATA_4 0x0e44
2227#define mmCOMPUTE_USER_DATA_4_BASE_IDX 0
2228#define mmCOMPUTE_USER_DATA_5 0x0e45
2229#define mmCOMPUTE_USER_DATA_5_BASE_IDX 0
2230#define mmCOMPUTE_USER_DATA_6 0x0e46
2231#define mmCOMPUTE_USER_DATA_6_BASE_IDX 0
2232#define mmCOMPUTE_USER_DATA_7 0x0e47
2233#define mmCOMPUTE_USER_DATA_7_BASE_IDX 0
2234#define mmCOMPUTE_USER_DATA_8 0x0e48
2235#define mmCOMPUTE_USER_DATA_8_BASE_IDX 0
2236#define mmCOMPUTE_USER_DATA_9 0x0e49
2237#define mmCOMPUTE_USER_DATA_9_BASE_IDX 0
2238#define mmCOMPUTE_USER_DATA_10 0x0e4a
2239#define mmCOMPUTE_USER_DATA_10_BASE_IDX 0
2240#define mmCOMPUTE_USER_DATA_11 0x0e4b
2241#define mmCOMPUTE_USER_DATA_11_BASE_IDX 0
2242#define mmCOMPUTE_USER_DATA_12 0x0e4c
2243#define mmCOMPUTE_USER_DATA_12_BASE_IDX 0
2244#define mmCOMPUTE_USER_DATA_13 0x0e4d
2245#define mmCOMPUTE_USER_DATA_13_BASE_IDX 0
2246#define mmCOMPUTE_USER_DATA_14 0x0e4e
2247#define mmCOMPUTE_USER_DATA_14_BASE_IDX 0
2248#define mmCOMPUTE_USER_DATA_15 0x0e4f
2249#define mmCOMPUTE_USER_DATA_15_BASE_IDX 0
2250#define mmCOMPUTE_NOWHERE 0x0e7f
2251#define mmCOMPUTE_NOWHERE_BASE_IDX 0
2252
2253
2254// addressBlock: gc_cppdec
2255// base address: 0xc080
2256#define mmCP_DFY_CNTL 0x1020
2257#define mmCP_DFY_CNTL_BASE_IDX 0
2258#define mmCP_DFY_STAT 0x1021
2259#define mmCP_DFY_STAT_BASE_IDX 0
2260#define mmCP_DFY_ADDR_HI 0x1022
2261#define mmCP_DFY_ADDR_HI_BASE_IDX 0
2262#define mmCP_DFY_ADDR_LO 0x1023
2263#define mmCP_DFY_ADDR_LO_BASE_IDX 0
2264#define mmCP_DFY_DATA_0 0x1024
2265#define mmCP_DFY_DATA_0_BASE_IDX 0
2266#define mmCP_DFY_DATA_1 0x1025
2267#define mmCP_DFY_DATA_1_BASE_IDX 0
2268#define mmCP_DFY_DATA_2 0x1026
2269#define mmCP_DFY_DATA_2_BASE_IDX 0
2270#define mmCP_DFY_DATA_3 0x1027
2271#define mmCP_DFY_DATA_3_BASE_IDX 0
2272#define mmCP_DFY_DATA_4 0x1028
2273#define mmCP_DFY_DATA_4_BASE_IDX 0
2274#define mmCP_DFY_DATA_5 0x1029
2275#define mmCP_DFY_DATA_5_BASE_IDX 0
2276#define mmCP_DFY_DATA_6 0x102a
2277#define mmCP_DFY_DATA_6_BASE_IDX 0
2278#define mmCP_DFY_DATA_7 0x102b
2279#define mmCP_DFY_DATA_7_BASE_IDX 0
2280#define mmCP_DFY_DATA_8 0x102c
2281#define mmCP_DFY_DATA_8_BASE_IDX 0
2282#define mmCP_DFY_DATA_9 0x102d
2283#define mmCP_DFY_DATA_9_BASE_IDX 0
2284#define mmCP_DFY_DATA_10 0x102e
2285#define mmCP_DFY_DATA_10_BASE_IDX 0
2286#define mmCP_DFY_DATA_11 0x102f
2287#define mmCP_DFY_DATA_11_BASE_IDX 0
2288#define mmCP_DFY_DATA_12 0x1030
2289#define mmCP_DFY_DATA_12_BASE_IDX 0
2290#define mmCP_DFY_DATA_13 0x1031
2291#define mmCP_DFY_DATA_13_BASE_IDX 0
2292#define mmCP_DFY_DATA_14 0x1032
2293#define mmCP_DFY_DATA_14_BASE_IDX 0
2294#define mmCP_DFY_DATA_15 0x1033
2295#define mmCP_DFY_DATA_15_BASE_IDX 0
2296#define mmCP_DFY_CMD 0x1034
2297#define mmCP_DFY_CMD_BASE_IDX 0
2298#define mmCP_EOPQ_WAIT_TIME 0x1035
2299#define mmCP_EOPQ_WAIT_TIME_BASE_IDX 0
2300#define mmCP_CPC_MGCG_SYNC_CNTL 0x1036
2301#define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0
2302#define mmCPC_INT_INFO 0x1037
2303#define mmCPC_INT_INFO_BASE_IDX 0
2304#define mmCP_VIRT_STATUS 0x1038
2305#define mmCP_VIRT_STATUS_BASE_IDX 0
2306#define mmCPC_INT_ADDR 0x1039
2307#define mmCPC_INT_ADDR_BASE_IDX 0
2308#define mmCPC_INT_PASID 0x103a
2309#define mmCPC_INT_PASID_BASE_IDX 0
2310#define mmCP_GFX_ERROR 0x103b
2311#define mmCP_GFX_ERROR_BASE_IDX 0
2312#define mmCPG_UTCL1_CNTL 0x103c
2313#define mmCPG_UTCL1_CNTL_BASE_IDX 0
2314#define mmCPC_UTCL1_CNTL 0x103d
2315#define mmCPC_UTCL1_CNTL_BASE_IDX 0
2316#define mmCPF_UTCL1_CNTL 0x103e
2317#define mmCPF_UTCL1_CNTL_BASE_IDX 0
2318#define mmCP_AQL_SMM_STATUS 0x103f
2319#define mmCP_AQL_SMM_STATUS_BASE_IDX 0
2320#define mmCP_RB0_BASE 0x1040
2321#define mmCP_RB0_BASE_BASE_IDX 0
2322#define mmCP_RB_BASE 0x1040
2323#define mmCP_RB_BASE_BASE_IDX 0
2324#define mmCP_RB0_CNTL 0x1041
2325#define mmCP_RB0_CNTL_BASE_IDX 0
2326#define mmCP_RB_CNTL 0x1041
2327#define mmCP_RB_CNTL_BASE_IDX 0
2328#define mmCP_RB_RPTR_WR 0x1042
2329#define mmCP_RB_RPTR_WR_BASE_IDX 0
2330#define mmCP_RB0_RPTR_ADDR 0x1043
2331#define mmCP_RB0_RPTR_ADDR_BASE_IDX 0
2332#define mmCP_RB_RPTR_ADDR 0x1043
2333#define mmCP_RB_RPTR_ADDR_BASE_IDX 0
2334#define mmCP_RB0_RPTR_ADDR_HI 0x1044
2335#define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX 0
2336#define mmCP_RB_RPTR_ADDR_HI 0x1044
2337#define mmCP_RB_RPTR_ADDR_HI_BASE_IDX 0
2338#define mmCP_RB0_BUFSZ_MASK 0x1045
2339#define mmCP_RB0_BUFSZ_MASK_BASE_IDX 0
2340#define mmCP_RB_BUFSZ_MASK 0x1045
2341#define mmCP_RB_BUFSZ_MASK_BASE_IDX 0
2342#define mmCP_RB_WPTR_POLL_ADDR_LO 0x1046
2343#define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
2344#define mmCP_RB_WPTR_POLL_ADDR_HI 0x1047
2345#define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
2346#define mmGC_PRIV_MODE 0x1048
2347#define mmGC_PRIV_MODE_BASE_IDX 0
2348#define mmCP_INT_CNTL 0x1049
2349#define mmCP_INT_CNTL_BASE_IDX 0
2350#define mmCP_INT_STATUS 0x104a
2351#define mmCP_INT_STATUS_BASE_IDX 0
2352#define mmCP_DEVICE_ID 0x104b
2353#define mmCP_DEVICE_ID_BASE_IDX 0
2354#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x104c
2355#define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0
2356#define mmCP_RING_PRIORITY_CNTS 0x104c
2357#define mmCP_RING_PRIORITY_CNTS_BASE_IDX 0
2358#define mmCP_ME0_PIPE0_PRIORITY 0x104d
2359#define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX 0
2360#define mmCP_RING0_PRIORITY 0x104d
2361#define mmCP_RING0_PRIORITY_BASE_IDX 0
2362#define mmCP_ME0_PIPE1_PRIORITY 0x104e
2363#define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX 0
2364#define mmCP_RING1_PRIORITY 0x104e
2365#define mmCP_RING1_PRIORITY_BASE_IDX 0
2366#define mmCP_ME0_PIPE2_PRIORITY 0x104f
2367#define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX 0
2368#define mmCP_RING2_PRIORITY 0x104f
2369#define mmCP_RING2_PRIORITY_BASE_IDX 0
2370#define mmCP_FATAL_ERROR 0x1050
2371#define mmCP_FATAL_ERROR_BASE_IDX 0
2372#define mmCP_RB_VMID 0x1051
2373#define mmCP_RB_VMID_BASE_IDX 0
2374#define mmCP_ME0_PIPE0_VMID 0x1052
2375#define mmCP_ME0_PIPE0_VMID_BASE_IDX 0
2376#define mmCP_ME0_PIPE1_VMID 0x1053
2377#define mmCP_ME0_PIPE1_VMID_BASE_IDX 0
2378#define mmCP_RB0_WPTR 0x1054
2379#define mmCP_RB0_WPTR_BASE_IDX 0
2380#define mmCP_RB_WPTR 0x1054
2381#define mmCP_RB_WPTR_BASE_IDX 0
2382#define mmCP_RB0_WPTR_HI 0x1055
2383#define mmCP_RB0_WPTR_HI_BASE_IDX 0
2384#define mmCP_RB_WPTR_HI 0x1055
2385#define mmCP_RB_WPTR_HI_BASE_IDX 0
2386#define mmCP_RB1_WPTR 0x1056
2387#define mmCP_RB1_WPTR_BASE_IDX 0
2388#define mmCP_RB1_WPTR_HI 0x1057
2389#define mmCP_RB1_WPTR_HI_BASE_IDX 0
2390#define mmCP_RB2_WPTR 0x1058
2391#define mmCP_RB2_WPTR_BASE_IDX 0
2392#define mmCP_RB_DOORBELL_CONTROL 0x1059
2393#define mmCP_RB_DOORBELL_CONTROL_BASE_IDX 0
2394#define mmCP_RB_DOORBELL_RANGE_LOWER 0x105a
2395#define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0
2396#define mmCP_RB_DOORBELL_RANGE_UPPER 0x105b
2397#define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0
2398#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x105c
2399#define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0
2400#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x105d
2401#define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0
2402#define mmCPG_UTCL1_ERROR 0x105e
2403#define mmCPG_UTCL1_ERROR_BASE_IDX 0
2404#define mmCPC_UTCL1_ERROR 0x105f
2405#define mmCPC_UTCL1_ERROR_BASE_IDX 0
2406#define mmCP_RB1_BASE 0x1060
2407#define mmCP_RB1_BASE_BASE_IDX 0
2408#define mmCP_RB1_CNTL 0x1061
2409#define mmCP_RB1_CNTL_BASE_IDX 0
2410#define mmCP_RB1_RPTR_ADDR 0x1062
2411#define mmCP_RB1_RPTR_ADDR_BASE_IDX 0
2412#define mmCP_RB1_RPTR_ADDR_HI 0x1063
2413#define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX 0
2414#define mmCP_RB2_BASE 0x1065
2415#define mmCP_RB2_BASE_BASE_IDX 0
2416#define mmCP_RB2_CNTL 0x1066
2417#define mmCP_RB2_CNTL_BASE_IDX 0
2418#define mmCP_RB2_RPTR_ADDR 0x1067
2419#define mmCP_RB2_RPTR_ADDR_BASE_IDX 0
2420#define mmCP_RB2_RPTR_ADDR_HI 0x1068
2421#define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX 0
2422#define mmCP_RB0_ACTIVE 0x1069
2423#define mmCP_RB0_ACTIVE_BASE_IDX 0
2424#define mmCP_RB_ACTIVE 0x1069
2425#define mmCP_RB_ACTIVE_BASE_IDX 0
2426#define mmCP_INT_CNTL_RING0 0x106a
2427#define mmCP_INT_CNTL_RING0_BASE_IDX 0
2428#define mmCP_INT_CNTL_RING1 0x106b
2429#define mmCP_INT_CNTL_RING1_BASE_IDX 0
2430#define mmCP_INT_CNTL_RING2 0x106c
2431#define mmCP_INT_CNTL_RING2_BASE_IDX 0
2432#define mmCP_INT_STATUS_RING0 0x106d
2433#define mmCP_INT_STATUS_RING0_BASE_IDX 0
2434#define mmCP_INT_STATUS_RING1 0x106e
2435#define mmCP_INT_STATUS_RING1_BASE_IDX 0
2436#define mmCP_INT_STATUS_RING2 0x106f
2437#define mmCP_INT_STATUS_RING2_BASE_IDX 0
2438#define mmCP_PWR_CNTL 0x1078
2439#define mmCP_PWR_CNTL_BASE_IDX 0
2440#define mmCP_MEM_SLP_CNTL 0x1079
2441#define mmCP_MEM_SLP_CNTL_BASE_IDX 0
2442#define mmCP_ECC_FIRSTOCCURRENCE 0x107a
2443#define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0
2444#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x107b
2445#define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0
2446#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x107c
2447#define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX 0
2448#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x107d
2449#define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0
2450#define mmGB_EDC_MODE 0x107e
2451#define mmGB_EDC_MODE_BASE_IDX 0
2452#define mmCP_DEBUG 0x107f
2453#define mmCP_DEBUG_BASE_IDX 0
2454#define mmCP_CPF_DEBUG 0x1080
2455#define mmCP_PQ_WPTR_POLL_CNTL 0x1083
2456#define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0
2457#define mmCP_PQ_WPTR_POLL_CNTL1 0x1084
2458#define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0
2459#define mmCP_ME1_PIPE0_INT_CNTL 0x1085
2460#define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0
2461#define mmCP_ME1_PIPE1_INT_CNTL 0x1086
2462#define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0
2463#define mmCP_ME1_PIPE2_INT_CNTL 0x1087
2464#define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0
2465#define mmCP_ME1_PIPE3_INT_CNTL 0x1088
2466#define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0
2467#define mmCP_ME2_PIPE0_INT_CNTL 0x1089
2468#define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX 0
2469#define mmCP_ME2_PIPE1_INT_CNTL 0x108a
2470#define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX 0
2471#define mmCP_ME2_PIPE2_INT_CNTL 0x108b
2472#define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX 0
2473#define mmCP_ME2_PIPE3_INT_CNTL 0x108c
2474#define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX 0
2475#define mmCP_ME1_PIPE0_INT_STATUS 0x108d
2476#define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0
2477#define mmCP_ME1_PIPE1_INT_STATUS 0x108e
2478#define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0
2479#define mmCP_ME1_PIPE2_INT_STATUS 0x108f
2480#define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0
2481#define mmCP_ME1_PIPE3_INT_STATUS 0x1090
2482#define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0
2483#define mmCP_ME2_PIPE0_INT_STATUS 0x1091
2484#define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX 0
2485#define mmCP_ME2_PIPE1_INT_STATUS 0x1092
2486#define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX 0
2487#define mmCP_ME2_PIPE2_INT_STATUS 0x1093
2488#define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX 0
2489#define mmCP_ME2_PIPE3_INT_STATUS 0x1094
2490#define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX 0
2491#define mmCP_ME1_INT_STAT_DEBUG 0x1095
2492#define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX 0
2493#define mmCP_ME2_INT_STAT_DEBUG 0x1096
2494#define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX 0
2495#define mmCC_GC_EDC_CONFIG 0x1098
2496#define mmCC_GC_EDC_CONFIG_BASE_IDX 0
2497#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x1099
2498#define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0
2499#define mmCP_ME1_PIPE0_PRIORITY 0x109a
2500#define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX 0
2501#define mmCP_ME1_PIPE1_PRIORITY 0x109b
2502#define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX 0
2503#define mmCP_ME1_PIPE2_PRIORITY 0x109c
2504#define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX 0
2505#define mmCP_ME1_PIPE3_PRIORITY 0x109d
2506#define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX 0
2507#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x109e
2508#define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX 0
2509#define mmCP_ME2_PIPE0_PRIORITY 0x109f
2510#define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX 0
2511#define mmCP_ME2_PIPE1_PRIORITY 0x10a0
2512#define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX 0
2513#define mmCP_ME2_PIPE2_PRIORITY 0x10a1
2514#define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX 0
2515#define mmCP_ME2_PIPE3_PRIORITY 0x10a2
2516#define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX 0
2517#define mmCP_CE_PRGRM_CNTR_START 0x10a3
2518#define mmCP_CE_PRGRM_CNTR_START_BASE_IDX 0
2519#define mmCP_PFP_PRGRM_CNTR_START 0x10a4
2520#define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX 0
2521#define mmCP_ME_PRGRM_CNTR_START 0x10a5
2522#define mmCP_ME_PRGRM_CNTR_START_BASE_IDX 0
2523#define mmCP_MEC1_PRGRM_CNTR_START 0x10a6
2524#define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0
2525#define mmCP_MEC2_PRGRM_CNTR_START 0x10a7
2526#define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX 0
2527#define mmCP_CE_INTR_ROUTINE_START 0x10a8
2528#define mmCP_CE_INTR_ROUTINE_START_BASE_IDX 0
2529#define mmCP_PFP_INTR_ROUTINE_START 0x10a9
2530#define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX 0
2531#define mmCP_ME_INTR_ROUTINE_START 0x10aa
2532#define mmCP_ME_INTR_ROUTINE_START_BASE_IDX 0
2533#define mmCP_MEC1_INTR_ROUTINE_START 0x10ab
2534#define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0
2535#define mmCP_MEC2_INTR_ROUTINE_START 0x10ac
2536#define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX 0
2537#define mmCP_CONTEXT_CNTL 0x10ad
2538#define mmCP_CONTEXT_CNTL_BASE_IDX 0
2539#define mmCP_MAX_CONTEXT 0x10ae
2540#define mmCP_MAX_CONTEXT_BASE_IDX 0
2541#define mmCP_IQ_WAIT_TIME1 0x10af
2542#define mmCP_IQ_WAIT_TIME1_BASE_IDX 0
2543#define mmCP_IQ_WAIT_TIME2 0x10b0
2544#define mmCP_IQ_WAIT_TIME2_BASE_IDX 0
2545#define mmCP_RB0_BASE_HI 0x10b1
2546#define mmCP_RB0_BASE_HI_BASE_IDX 0
2547#define mmCP_RB1_BASE_HI 0x10b2
2548#define mmCP_RB1_BASE_HI_BASE_IDX 0
2549#define mmCP_VMID_RESET 0x10b3
2550#define mmCP_VMID_RESET_BASE_IDX 0
2551#define mmCPC_INT_CNTL 0x10b4
2552#define mmCPC_INT_CNTL_BASE_IDX 0
2553#define mmCPC_INT_STATUS 0x10b5
2554#define mmCPC_INT_STATUS_BASE_IDX 0
2555#define mmCP_VMID_PREEMPT 0x10b6
2556#define mmCP_VMID_PREEMPT_BASE_IDX 0
2557#define mmCPC_INT_CNTX_ID 0x10b7
2558#define mmCPC_INT_CNTX_ID_BASE_IDX 0
2559#define mmCP_PQ_STATUS 0x10b8
2560#define mmCP_PQ_STATUS_BASE_IDX 0
2561#define mmCP_CPC_IC_BASE_LO 0x10b9
2562#define mmCP_CPC_IC_BASE_LO_BASE_IDX 0
2563#define mmCP_CPC_IC_BASE_HI 0x10ba
2564#define mmCP_CPC_IC_BASE_HI_BASE_IDX 0
2565#define mmCP_CPC_IC_BASE_CNTL 0x10bb
2566#define mmCP_CPC_IC_BASE_CNTL_BASE_IDX 0
2567#define mmCP_CPC_IC_OP_CNTL 0x10bc
2568#define mmCP_CPC_IC_OP_CNTL_BASE_IDX 0
2569#define mmCP_MEC1_F32_INT_DIS 0x10bd
2570#define mmCP_MEC1_F32_INT_DIS_BASE_IDX 0
2571#define mmCP_MEC2_F32_INT_DIS 0x10be
2572#define mmCP_MEC2_F32_INT_DIS_BASE_IDX 0
2573#define mmCP_VMID_STATUS 0x10bf
2574#define mmCP_VMID_STATUS_BASE_IDX 0
2575
2576
2577// addressBlock: gc_cppdec2
2578// base address: 0xc600
2579#define mmCP_RB_DOORBELL_CONTROL_SCH_0 0x1180
2580#define mmCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX 0
2581#define mmCP_RB_DOORBELL_CONTROL_SCH_1 0x1181
2582#define mmCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX 0
2583#define mmCP_RB_DOORBELL_CONTROL_SCH_2 0x1182
2584#define mmCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX 0
2585#define mmCP_RB_DOORBELL_CONTROL_SCH_3 0x1183
2586#define mmCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX 0
2587#define mmCP_RB_DOORBELL_CONTROL_SCH_4 0x1184
2588#define mmCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX 0
2589#define mmCP_RB_DOORBELL_CONTROL_SCH_5 0x1185
2590#define mmCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX 0
2591#define mmCP_RB_DOORBELL_CONTROL_SCH_6 0x1186
2592#define mmCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX 0
2593#define mmCP_RB_DOORBELL_CONTROL_SCH_7 0x1187
2594#define mmCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX 0
2595#define mmCP_RB_DOORBELL_CLEAR 0x1188
2596#define mmCP_RB_DOORBELL_CLEAR_BASE_IDX 0
2597#define mmCP_GFX_MQD_CONTROL 0x11a0
2598#define mmCP_GFX_MQD_CONTROL_BASE_IDX 0
2599#define mmCP_GFX_MQD_BASE_ADDR 0x11a1
2600#define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX 0
2601#define mmCP_GFX_MQD_BASE_ADDR_HI 0x11a2
2602#define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0
2603#define mmCP_RB_STATUS 0x11a3
2604#define mmCP_RB_STATUS_BASE_IDX 0
2605#define mmCPG_UTCL1_STATUS 0x11b4
2606#define mmCPG_UTCL1_STATUS_BASE_IDX 0
2607#define mmCPC_UTCL1_STATUS 0x11b5
2608#define mmCPC_UTCL1_STATUS_BASE_IDX 0
2609#define mmCPF_UTCL1_STATUS 0x11b6
2610#define mmCPF_UTCL1_STATUS_BASE_IDX 0
2611#define mmCP_SD_CNTL 0x11b7
2612#define mmCP_SD_CNTL_BASE_IDX 0
2613#define mmCP_SOFT_RESET_CNTL 0x11b9
2614#define mmCP_SOFT_RESET_CNTL_BASE_IDX 0
2615#define mmCP_CPC_GFX_CNTL 0x11ba
2616#define mmCP_CPC_GFX_CNTL_BASE_IDX 0
2617
2618
2619// addressBlock: gc_spipdec
2620// base address: 0xc700
2621#define mmSPI_ARB_PRIORITY 0x11c0
2622#define mmSPI_ARB_PRIORITY_BASE_IDX 0
2623#define mmSPI_ARB_CYCLES_0 0x11c1
2624#define mmSPI_ARB_CYCLES_0_BASE_IDX 0
2625#define mmSPI_ARB_CYCLES_1 0x11c2
2626#define mmSPI_ARB_CYCLES_1_BASE_IDX 0
2627#define mmSPI_CDBG_SYS_GFX 0x11c3
2628#define mmSPI_CDBG_SYS_GFX_BASE_IDX 0
2629#define mmSPI_CDBG_SYS_HP3D 0x11c4
2630#define mmSPI_CDBG_SYS_HP3D_BASE_IDX 0
2631#define mmSPI_CDBG_SYS_CS0 0x11c5
2632#define mmSPI_CDBG_SYS_CS0_BASE_IDX 0
2633#define mmSPI_CDBG_SYS_CS1 0x11c6
2634#define mmSPI_CDBG_SYS_CS1_BASE_IDX 0
2635#define mmSPI_WCL_PIPE_PERCENT_GFX 0x11c7
2636#define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0
2637#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x11c8
2638#define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0
2639#define mmSPI_WCL_PIPE_PERCENT_CS0 0x11c9
2640#define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0
2641#define mmSPI_WCL_PIPE_PERCENT_CS1 0x11ca
2642#define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0
2643#define mmSPI_WCL_PIPE_PERCENT_CS2 0x11cb
2644#define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0
2645#define mmSPI_WCL_PIPE_PERCENT_CS3 0x11cc
2646#define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0
2647#define mmSPI_WCL_PIPE_PERCENT_CS4 0x11cd
2648#define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0
2649#define mmSPI_WCL_PIPE_PERCENT_CS5 0x11ce
2650#define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0
2651#define mmSPI_WCL_PIPE_PERCENT_CS6 0x11cf
2652#define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0
2653#define mmSPI_WCL_PIPE_PERCENT_CS7 0x11d0
2654#define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0
2655#define mmSPI_GDBG_WAVE_CNTL 0x11d1
2656#define mmSPI_GDBG_WAVE_CNTL_BASE_IDX 0
2657#define mmSPI_GDBG_TRAP_CONFIG 0x11d2
2658#define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX 0
2659#define mmSPI_GDBG_TRAP_MASK 0x11d3
2660#define mmSPI_GDBG_TRAP_MASK_BASE_IDX 0
2661#define mmSPI_GDBG_WAVE_CNTL2 0x11d4
2662#define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX 0
2663#define mmSPI_GDBG_WAVE_CNTL3 0x11d5
2664#define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX 0
2665#define mmSPI_GDBG_TRAP_DATA0 0x11d8
2666#define mmSPI_GDBG_TRAP_DATA0_BASE_IDX 0
2667#define mmSPI_GDBG_TRAP_DATA1 0x11d9
2668#define mmSPI_GDBG_TRAP_DATA1_BASE_IDX 0
2669#define mmSPI_RESET_DEBUG 0x11da
2670#define mmSPI_RESET_DEBUG_BASE_IDX 0
2671#define mmSPI_COMPUTE_QUEUE_RESET 0x11db
2672#define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0
2673#define mmSPI_RESOURCE_RESERVE_CU_0 0x11dc
2674#define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 0
2675#define mmSPI_RESOURCE_RESERVE_CU_1 0x11dd
2676#define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 0
2677#define mmSPI_RESOURCE_RESERVE_CU_2 0x11de
2678#define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 0
2679#define mmSPI_RESOURCE_RESERVE_CU_3 0x11df
2680#define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 0
2681#define mmSPI_RESOURCE_RESERVE_CU_4 0x11e0
2682#define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 0
2683#define mmSPI_RESOURCE_RESERVE_CU_5 0x11e1
2684#define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 0
2685#define mmSPI_RESOURCE_RESERVE_CU_6 0x11e2
2686#define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 0
2687#define mmSPI_RESOURCE_RESERVE_CU_7 0x11e3
2688#define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 0
2689#define mmSPI_RESOURCE_RESERVE_CU_8 0x11e4
2690#define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 0
2691#define mmSPI_RESOURCE_RESERVE_CU_9 0x11e5
2692#define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 0
2693#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x11e6
2694#define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 0
2695#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x11e7
2696#define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 0
2697#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x11e8
2698#define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 0
2699#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x11e9
2700#define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 0
2701#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x11ea
2702#define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 0
2703#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x11eb
2704#define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 0
2705#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x11ec
2706#define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 0
2707#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x11ed
2708#define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 0
2709#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x11ee
2710#define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 0
2711#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x11ef
2712#define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 0
2713#define mmSPI_RESOURCE_RESERVE_CU_10 0x11f0
2714#define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 0
2715#define mmSPI_RESOURCE_RESERVE_CU_11 0x11f1
2716#define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 0
2717#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x11f2
2718#define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 0
2719#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x11f3
2720#define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 0
2721#define mmSPI_RESOURCE_RESERVE_CU_12 0x11f4
2722#define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 0
2723#define mmSPI_RESOURCE_RESERVE_CU_13 0x11f5
2724#define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 0
2725#define mmSPI_RESOURCE_RESERVE_CU_14 0x11f6
2726#define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 0
2727#define mmSPI_RESOURCE_RESERVE_CU_15 0x11f7
2728#define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 0
2729#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x11f8
2730#define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 0
2731#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x11f9
2732#define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 0
2733#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x11fa
2734#define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 0
2735#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x11fb
2736#define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 0
2737#define mmSPI_COMPUTE_WF_CTX_SAVE 0x11fc
2738#define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0
2739#define mmSPI_ARB_CNTL_0 0x11fd
2740#define mmSPI_ARB_CNTL_0_BASE_IDX 0
2741
2742
2743// addressBlock: gc_cpphqddec
2744// base address: 0xc800
2745#define mmCP_HQD_GFX_CONTROL 0x123e
2746#define mmCP_HQD_GFX_CONTROL_BASE_IDX 0
2747#define mmCP_HQD_GFX_STATUS 0x123f
2748#define mmCP_HQD_GFX_STATUS_BASE_IDX 0
2749#define mmCP_HPD_ROQ_OFFSETS 0x1240
2750#define mmCP_HPD_ROQ_OFFSETS_BASE_IDX 0
2751#define mmCP_HPD_STATUS0 0x1241
2752#define mmCP_HPD_STATUS0_BASE_IDX 0
2753#define mmCP_HPD_UTCL1_CNTL 0x1242
2754#define mmCP_HPD_UTCL1_CNTL_BASE_IDX 0
2755#define mmCP_HPD_UTCL1_ERROR 0x1243
2756#define mmCP_HPD_UTCL1_ERROR_BASE_IDX 0
2757#define mmCP_HPD_UTCL1_ERROR_ADDR 0x1244
2758#define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0
2759#define mmCP_MQD_BASE_ADDR 0x1245
2760#define mmCP_MQD_BASE_ADDR_BASE_IDX 0
2761#define mmCP_MQD_BASE_ADDR_HI 0x1246
2762#define mmCP_MQD_BASE_ADDR_HI_BASE_IDX 0
2763#define mmCP_HQD_ACTIVE 0x1247
2764#define mmCP_HQD_ACTIVE_BASE_IDX 0
2765#define mmCP_HQD_VMID 0x1248
2766#define mmCP_HQD_VMID_BASE_IDX 0
2767#define mmCP_HQD_PERSISTENT_STATE 0x1249
2768#define mmCP_HQD_PERSISTENT_STATE_BASE_IDX 0
2769#define mmCP_HQD_PIPE_PRIORITY 0x124a
2770#define mmCP_HQD_PIPE_PRIORITY_BASE_IDX 0
2771#define mmCP_HQD_QUEUE_PRIORITY 0x124b
2772#define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX 0
2773#define mmCP_HQD_QUANTUM 0x124c
2774#define mmCP_HQD_QUANTUM_BASE_IDX 0
2775#define mmCP_HQD_PQ_BASE 0x124d
2776#define mmCP_HQD_PQ_BASE_BASE_IDX 0
2777#define mmCP_HQD_PQ_BASE_HI 0x124e
2778#define mmCP_HQD_PQ_BASE_HI_BASE_IDX 0
2779#define mmCP_HQD_PQ_RPTR 0x124f
2780#define mmCP_HQD_PQ_RPTR_BASE_IDX 0
2781#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x1250
2782#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0
2783#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
2784#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0
2785#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
2786#define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0
2787#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
2788#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0
2789#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x1254
2790#define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0
2791#define mmCP_HQD_PQ_CONTROL 0x1256
2792#define mmCP_HQD_PQ_CONTROL_BASE_IDX 0
2793#define mmCP_HQD_IB_BASE_ADDR 0x1257
2794#define mmCP_HQD_IB_BASE_ADDR_BASE_IDX 0
2795#define mmCP_HQD_IB_BASE_ADDR_HI 0x1258
2796#define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0
2797#define mmCP_HQD_IB_RPTR 0x1259
2798#define mmCP_HQD_IB_RPTR_BASE_IDX 0
2799#define mmCP_HQD_IB_CONTROL 0x125a
2800#define mmCP_HQD_IB_CONTROL_BASE_IDX 0
2801#define mmCP_HQD_IQ_TIMER 0x125b
2802#define mmCP_HQD_IQ_TIMER_BASE_IDX 0
2803#define mmCP_HQD_IQ_RPTR 0x125c
2804#define mmCP_HQD_IQ_RPTR_BASE_IDX 0
2805#define mmCP_HQD_DEQUEUE_REQUEST 0x125d
2806#define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0
2807#define mmCP_HQD_DMA_OFFLOAD 0x125e
2808#define mmCP_HQD_DMA_OFFLOAD_BASE_IDX 0
2809#define mmCP_HQD_OFFLOAD 0x125e
2810#define mmCP_HQD_OFFLOAD_BASE_IDX 0
2811#define mmCP_HQD_SEMA_CMD 0x125f
2812#define mmCP_HQD_SEMA_CMD_BASE_IDX 0
2813#define mmCP_HQD_MSG_TYPE 0x1260
2814#define mmCP_HQD_MSG_TYPE_BASE_IDX 0
2815#define mmCP_HQD_ATOMIC0_PREOP_LO 0x1261
2816#define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0
2817#define mmCP_HQD_ATOMIC0_PREOP_HI 0x1262
2818#define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0
2819#define mmCP_HQD_ATOMIC1_PREOP_LO 0x1263
2820#define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0
2821#define mmCP_HQD_ATOMIC1_PREOP_HI 0x1264
2822#define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0
2823#define mmCP_HQD_HQ_SCHEDULER0 0x1265
2824#define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX 0
2825#define mmCP_HQD_HQ_STATUS0 0x1265
2826#define mmCP_HQD_HQ_STATUS0_BASE_IDX 0
2827#define mmCP_HQD_HQ_CONTROL0 0x1266
2828#define mmCP_HQD_HQ_CONTROL0_BASE_IDX 0
2829#define mmCP_HQD_HQ_SCHEDULER1 0x1266
2830#define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX 0
2831#define mmCP_MQD_CONTROL 0x1267
2832#define mmCP_MQD_CONTROL_BASE_IDX 0
2833#define mmCP_HQD_HQ_STATUS1 0x1268
2834#define mmCP_HQD_HQ_STATUS1_BASE_IDX 0
2835#define mmCP_HQD_HQ_CONTROL1 0x1269
2836#define mmCP_HQD_HQ_CONTROL1_BASE_IDX 0
2837#define mmCP_HQD_EOP_BASE_ADDR 0x126a
2838#define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX 0
2839#define mmCP_HQD_EOP_BASE_ADDR_HI 0x126b
2840#define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0
2841#define mmCP_HQD_EOP_CONTROL 0x126c
2842#define mmCP_HQD_EOP_CONTROL_BASE_IDX 0
2843#define mmCP_HQD_EOP_RPTR 0x126d
2844#define mmCP_HQD_EOP_RPTR_BASE_IDX 0
2845#define mmCP_HQD_EOP_WPTR 0x126e
2846#define mmCP_HQD_EOP_WPTR_BASE_IDX 0
2847#define mmCP_HQD_EOP_EVENTS 0x126f
2848#define mmCP_HQD_EOP_EVENTS_BASE_IDX 0
2849#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1270
2850#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0
2851#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1271
2852#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0
2853#define mmCP_HQD_CTX_SAVE_CONTROL 0x1272
2854#define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0
2855#define mmCP_HQD_CNTL_STACK_OFFSET 0x1273
2856#define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0
2857#define mmCP_HQD_CNTL_STACK_SIZE 0x1274
2858#define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0
2859#define mmCP_HQD_WG_STATE_OFFSET 0x1275
2860#define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX 0
2861#define mmCP_HQD_CTX_SAVE_SIZE 0x1276
2862#define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0
2863#define mmCP_HQD_GDS_RESOURCE_STATE 0x1277
2864#define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0
2865#define mmCP_HQD_ERROR 0x1278
2866#define mmCP_HQD_ERROR_BASE_IDX 0
2867#define mmCP_HQD_EOP_WPTR_MEM 0x1279
2868#define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX 0
2869#define mmCP_HQD_AQL_CONTROL 0x127a
2870#define mmCP_HQD_AQL_CONTROL_BASE_IDX 0
2871#define mmCP_HQD_PQ_WPTR_LO 0x127b
2872#define mmCP_HQD_PQ_WPTR_LO_BASE_IDX 0
2873#define mmCP_HQD_PQ_WPTR_HI 0x127c
2874#define mmCP_HQD_PQ_WPTR_HI_BASE_IDX 0
2875
2876
2877// addressBlock: gc_didtdec
2878// base address: 0xca00
2879#define mmDIDT_IND_INDEX 0x1280
2880#define mmDIDT_IND_INDEX_BASE_IDX 0
2881#define mmDIDT_IND_DATA 0x1281
2882#define mmDIDT_IND_DATA_BASE_IDX 0
2883
2884
2885// addressBlock: gc_gccacdec
2886// base address: 0xca10
2887#define mmGC_CAC_CTRL_1 0x1284
2888#define mmGC_CAC_CTRL_1_BASE_IDX 0
2889#define mmGC_CAC_CTRL_2 0x1285
2890#define mmGC_CAC_CTRL_2_BASE_IDX 0
2891#define mmGC_CAC_CGTT_CLK_CTRL 0x1286
2892#define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX 0
2893#define mmGC_CAC_AGGR_LOWER 0x1287
2894#define mmGC_CAC_AGGR_LOWER_BASE_IDX 0
2895#define mmGC_CAC_AGGR_UPPER 0x1288
2896#define mmGC_CAC_AGGR_UPPER_BASE_IDX 0
2897#define mmGC_CAC_SOFT_CTRL 0x128d
2898#define mmGC_CAC_SOFT_CTRL_BASE_IDX 0
2899#define mmGC_DIDT_CTRL0 0x128e
2900#define mmGC_DIDT_CTRL0_BASE_IDX 0
2901#define mmGC_DIDT_CTRL1 0x128f
2902#define mmGC_DIDT_CTRL1_BASE_IDX 0
2903#define mmGC_DIDT_CTRL2 0x1290
2904#define mmGC_DIDT_CTRL2_BASE_IDX 0
2905#define mmGC_DIDT_WEIGHT 0x1291
2906#define mmGC_DIDT_WEIGHT_BASE_IDX 0
2907#define mmGC_DIDT_WEIGHT_1 0x1292
2908#define mmGC_DIDT_WEIGHT_1_BASE_IDX 0
2909#define mmGC_EDC_CTRL 0x1293
2910#define mmGC_EDC_CTRL_BASE_IDX 0
2911#define mmGC_EDC_THRESHOLD 0x1294
2912#define mmGC_EDC_THRESHOLD_BASE_IDX 0
2913#define mmGC_EDC_STATUS 0x1295
2914#define mmGC_EDC_STATUS_BASE_IDX 0
2915#define mmGC_EDC_OVERFLOW 0x1296
2916#define mmGC_EDC_OVERFLOW_BASE_IDX 0
2917#define mmGC_EDC_ROLLING_POWER_DELTA 0x1297
2918#define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX 0
2919#define mmGC_DIDT_DROOP_CTRL 0x1298
2920#define mmGC_DIDT_DROOP_CTRL_BASE_IDX 0
2921#define mmGC_EDC_DROOP_CTRL 0x1299
2922#define mmGC_EDC_DROOP_CTRL_BASE_IDX 0
2923#define mmGC_CAC_IND_INDEX 0x129a
2924#define mmGC_CAC_IND_INDEX_BASE_IDX 0
2925#define mmGC_CAC_IND_DATA 0x129b
2926#define mmGC_CAC_IND_DATA_BASE_IDX 0
2927#define mmSE_CAC_CGTT_CLK_CTRL 0x129c
2928#define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX 0
2929#define mmSE_CAC_IND_INDEX 0x129d
2930#define mmSE_CAC_IND_INDEX_BASE_IDX 0
2931#define mmSE_CAC_IND_DATA 0x129e
2932#define mmSE_CAC_IND_DATA_BASE_IDX 0
2933
2934
2935// addressBlock: gc_tcpdec
2936// base address: 0xca80
2937#define mmTCP_WATCH0_ADDR_H 0x12a0
2938#define mmTCP_WATCH0_ADDR_H_BASE_IDX 0
2939#define mmTCP_WATCH0_ADDR_L 0x12a1
2940#define mmTCP_WATCH0_ADDR_L_BASE_IDX 0
2941#define mmTCP_WATCH0_CNTL 0x12a2
2942#define mmTCP_WATCH0_CNTL_BASE_IDX 0
2943#define mmTCP_WATCH1_ADDR_H 0x12a3
2944#define mmTCP_WATCH1_ADDR_H_BASE_IDX 0
2945#define mmTCP_WATCH1_ADDR_L 0x12a4
2946#define mmTCP_WATCH1_ADDR_L_BASE_IDX 0
2947#define mmTCP_WATCH1_CNTL 0x12a5
2948#define mmTCP_WATCH1_CNTL_BASE_IDX 0
2949#define mmTCP_WATCH2_ADDR_H 0x12a6
2950#define mmTCP_WATCH2_ADDR_H_BASE_IDX 0
2951#define mmTCP_WATCH2_ADDR_L 0x12a7
2952#define mmTCP_WATCH2_ADDR_L_BASE_IDX 0
2953#define mmTCP_WATCH2_CNTL 0x12a8
2954#define mmTCP_WATCH2_CNTL_BASE_IDX 0
2955#define mmTCP_WATCH3_ADDR_H 0x12a9
2956#define mmTCP_WATCH3_ADDR_H_BASE_IDX 0
2957#define mmTCP_WATCH3_ADDR_L 0x12aa
2958#define mmTCP_WATCH3_ADDR_L_BASE_IDX 0
2959#define mmTCP_WATCH3_CNTL 0x12ab
2960#define mmTCP_WATCH3_CNTL_BASE_IDX 0
2961#define mmTCP_GATCL1_CNTL 0x12b0
2962#define mmTCP_GATCL1_CNTL_BASE_IDX 0
2963#define mmTCP_ATC_EDC_GATCL1_CNT 0x12b1
2964#define mmTCP_ATC_EDC_GATCL1_CNT_BASE_IDX 0
2965#define mmTCP_GATCL1_DSM_CNTL 0x12b2
2966#define mmTCP_GATCL1_DSM_CNTL_BASE_IDX 0
2967#define mmTCP_CNTL2 0x12b4
2968#define mmTCP_CNTL2_BASE_IDX 0
2969#define mmTCP_UTCL1_CNTL1 0x12b5
2970#define mmTCP_UTCL1_CNTL1_BASE_IDX 0
2971#define mmTCP_UTCL1_CNTL2 0x12b6
2972#define mmTCP_UTCL1_CNTL2_BASE_IDX 0
2973#define mmTCP_UTCL1_STATUS 0x12b7
2974#define mmTCP_UTCL1_STATUS_BASE_IDX 0
2975#define mmTCP_PERFCOUNTER_FILTER 0x12b9
2976#define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0
2977#define mmTCP_PERFCOUNTER_FILTER_EN 0x12ba
2978#define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 0
2979
2980
2981// addressBlock: gc_gdspdec
2982// base address: 0xcc00
2983#define mmGDS_VMID0_BASE 0x1300
2984#define mmGDS_VMID0_BASE_BASE_IDX 0
2985#define mmGDS_VMID0_SIZE 0x1301
2986#define mmGDS_VMID0_SIZE_BASE_IDX 0
2987#define mmGDS_VMID1_BASE 0x1302
2988#define mmGDS_VMID1_BASE_BASE_IDX 0
2989#define mmGDS_VMID1_SIZE 0x1303
2990#define mmGDS_VMID1_SIZE_BASE_IDX 0
2991#define mmGDS_VMID2_BASE 0x1304
2992#define mmGDS_VMID2_BASE_BASE_IDX 0
2993#define mmGDS_VMID2_SIZE 0x1305
2994#define mmGDS_VMID2_SIZE_BASE_IDX 0
2995#define mmGDS_VMID3_BASE 0x1306
2996#define mmGDS_VMID3_BASE_BASE_IDX 0
2997#define mmGDS_VMID3_SIZE 0x1307
2998#define mmGDS_VMID3_SIZE_BASE_IDX 0
2999#define mmGDS_VMID4_BASE 0x1308
3000#define mmGDS_VMID4_BASE_BASE_IDX 0
3001#define mmGDS_VMID4_SIZE 0x1309
3002#define mmGDS_VMID4_SIZE_BASE_IDX 0
3003#define mmGDS_VMID5_BASE 0x130a
3004#define mmGDS_VMID5_BASE_BASE_IDX 0
3005#define mmGDS_VMID5_SIZE 0x130b
3006#define mmGDS_VMID5_SIZE_BASE_IDX 0
3007#define mmGDS_VMID6_BASE 0x130c
3008#define mmGDS_VMID6_BASE_BASE_IDX 0
3009#define mmGDS_VMID6_SIZE 0x130d
3010#define mmGDS_VMID6_SIZE_BASE_IDX 0
3011#define mmGDS_VMID7_BASE 0x130e
3012#define mmGDS_VMID7_BASE_BASE_IDX 0
3013#define mmGDS_VMID7_SIZE 0x130f
3014#define mmGDS_VMID7_SIZE_BASE_IDX 0
3015#define mmGDS_VMID8_BASE 0x1310
3016#define mmGDS_VMID8_BASE_BASE_IDX 0
3017#define mmGDS_VMID8_SIZE 0x1311
3018#define mmGDS_VMID8_SIZE_BASE_IDX 0
3019#define mmGDS_VMID9_BASE 0x1312
3020#define mmGDS_VMID9_BASE_BASE_IDX 0
3021#define mmGDS_VMID9_SIZE 0x1313
3022#define mmGDS_VMID9_SIZE_BASE_IDX 0
3023#define mmGDS_VMID10_BASE 0x1314
3024#define mmGDS_VMID10_BASE_BASE_IDX 0
3025#define mmGDS_VMID10_SIZE 0x1315
3026#define mmGDS_VMID10_SIZE_BASE_IDX 0
3027#define mmGDS_VMID11_BASE 0x1316
3028#define mmGDS_VMID11_BASE_BASE_IDX 0
3029#define mmGDS_VMID11_SIZE 0x1317
3030#define mmGDS_VMID11_SIZE_BASE_IDX 0
3031#define mmGDS_VMID12_BASE 0x1318
3032#define mmGDS_VMID12_BASE_BASE_IDX 0
3033#define mmGDS_VMID12_SIZE 0x1319
3034#define mmGDS_VMID12_SIZE_BASE_IDX 0
3035#define mmGDS_VMID13_BASE 0x131a
3036#define mmGDS_VMID13_BASE_BASE_IDX 0
3037#define mmGDS_VMID13_SIZE 0x131b
3038#define mmGDS_VMID13_SIZE_BASE_IDX 0
3039#define mmGDS_VMID14_BASE 0x131c
3040#define mmGDS_VMID14_BASE_BASE_IDX 0
3041#define mmGDS_VMID14_SIZE 0x131d
3042#define mmGDS_VMID14_SIZE_BASE_IDX 0
3043#define mmGDS_VMID15_BASE 0x131e
3044#define mmGDS_VMID15_BASE_BASE_IDX 0
3045#define mmGDS_VMID15_SIZE 0x131f
3046#define mmGDS_VMID15_SIZE_BASE_IDX 0
3047#define mmGDS_GWS_VMID0 0x1320
3048#define mmGDS_GWS_VMID0_BASE_IDX 0
3049#define mmGDS_GWS_VMID1 0x1321
3050#define mmGDS_GWS_VMID1_BASE_IDX 0
3051#define mmGDS_GWS_VMID2 0x1322
3052#define mmGDS_GWS_VMID2_BASE_IDX 0
3053#define mmGDS_GWS_VMID3 0x1323
3054#define mmGDS_GWS_VMID3_BASE_IDX 0
3055#define mmGDS_GWS_VMID4 0x1324
3056#define mmGDS_GWS_VMID4_BASE_IDX 0
3057#define mmGDS_GWS_VMID5 0x1325
3058#define mmGDS_GWS_VMID5_BASE_IDX 0
3059#define mmGDS_GWS_VMID6 0x1326
3060#define mmGDS_GWS_VMID6_BASE_IDX 0
3061#define mmGDS_GWS_VMID7 0x1327
3062#define mmGDS_GWS_VMID7_BASE_IDX 0
3063#define mmGDS_GWS_VMID8 0x1328
3064#define mmGDS_GWS_VMID8_BASE_IDX 0
3065#define mmGDS_GWS_VMID9 0x1329
3066#define mmGDS_GWS_VMID9_BASE_IDX 0
3067#define mmGDS_GWS_VMID10 0x132a
3068#define mmGDS_GWS_VMID10_BASE_IDX 0
3069#define mmGDS_GWS_VMID11 0x132b
3070#define mmGDS_GWS_VMID11_BASE_IDX 0
3071#define mmGDS_GWS_VMID12 0x132c
3072#define mmGDS_GWS_VMID12_BASE_IDX 0
3073#define mmGDS_GWS_VMID13 0x132d
3074#define mmGDS_GWS_VMID13_BASE_IDX 0
3075#define mmGDS_GWS_VMID14 0x132e
3076#define mmGDS_GWS_VMID14_BASE_IDX 0
3077#define mmGDS_GWS_VMID15 0x132f
3078#define mmGDS_GWS_VMID15_BASE_IDX 0
3079#define mmGDS_OA_VMID0 0x1330
3080#define mmGDS_OA_VMID0_BASE_IDX 0
3081#define mmGDS_OA_VMID1 0x1331
3082#define mmGDS_OA_VMID1_BASE_IDX 0
3083#define mmGDS_OA_VMID2 0x1332
3084#define mmGDS_OA_VMID2_BASE_IDX 0
3085#define mmGDS_OA_VMID3 0x1333
3086#define mmGDS_OA_VMID3_BASE_IDX 0
3087#define mmGDS_OA_VMID4 0x1334
3088#define mmGDS_OA_VMID4_BASE_IDX 0
3089#define mmGDS_OA_VMID5 0x1335
3090#define mmGDS_OA_VMID5_BASE_IDX 0
3091#define mmGDS_OA_VMID6 0x1336
3092#define mmGDS_OA_VMID6_BASE_IDX 0
3093#define mmGDS_OA_VMID7 0x1337
3094#define mmGDS_OA_VMID7_BASE_IDX 0
3095#define mmGDS_OA_VMID8 0x1338
3096#define mmGDS_OA_VMID8_BASE_IDX 0
3097#define mmGDS_OA_VMID9 0x1339
3098#define mmGDS_OA_VMID9_BASE_IDX 0
3099#define mmGDS_OA_VMID10 0x133a
3100#define mmGDS_OA_VMID10_BASE_IDX 0
3101#define mmGDS_OA_VMID11 0x133b
3102#define mmGDS_OA_VMID11_BASE_IDX 0
3103#define mmGDS_OA_VMID12 0x133c
3104#define mmGDS_OA_VMID12_BASE_IDX 0
3105#define mmGDS_OA_VMID13 0x133d
3106#define mmGDS_OA_VMID13_BASE_IDX 0
3107#define mmGDS_OA_VMID14 0x133e
3108#define mmGDS_OA_VMID14_BASE_IDX 0
3109#define mmGDS_OA_VMID15 0x133f
3110#define mmGDS_OA_VMID15_BASE_IDX 0
3111#define mmGDS_GWS_RESET0 0x1344
3112#define mmGDS_GWS_RESET0_BASE_IDX 0
3113#define mmGDS_GWS_RESET1 0x1345
3114#define mmGDS_GWS_RESET1_BASE_IDX 0
3115#define mmGDS_GWS_RESOURCE_RESET 0x1346
3116#define mmGDS_GWS_RESOURCE_RESET_BASE_IDX 0
3117#define mmGDS_COMPUTE_MAX_WAVE_ID 0x1348
3118#define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 0
3119#define mmGDS_OA_RESET_MASK 0x1349
3120#define mmGDS_OA_RESET_MASK_BASE_IDX 0
3121#define mmGDS_OA_RESET 0x134a
3122#define mmGDS_OA_RESET_BASE_IDX 0
3123#define mmGDS_ENHANCE 0x134b
3124#define mmGDS_ENHANCE_BASE_IDX 0
3125#define mmGDS_OA_CGPG_RESTORE 0x134c
3126#define mmGDS_OA_CGPG_RESTORE_BASE_IDX 0
3127#define mmGDS_CS_CTXSW_STATUS 0x134d
3128#define mmGDS_CS_CTXSW_STATUS_BASE_IDX 0
3129#define mmGDS_CS_CTXSW_CNT0 0x134e
3130#define mmGDS_CS_CTXSW_CNT0_BASE_IDX 0
3131#define mmGDS_CS_CTXSW_CNT1 0x134f
3132#define mmGDS_CS_CTXSW_CNT1_BASE_IDX 0
3133#define mmGDS_CS_CTXSW_CNT2 0x1350
3134#define mmGDS_CS_CTXSW_CNT2_BASE_IDX 0
3135#define mmGDS_CS_CTXSW_CNT3 0x1351
3136#define mmGDS_CS_CTXSW_CNT3_BASE_IDX 0
3137#define mmGDS_GFX_CTXSW_STATUS 0x1352
3138#define mmGDS_GFX_CTXSW_STATUS_BASE_IDX 0
3139#define mmGDS_VS_CTXSW_CNT0 0x1353
3140#define mmGDS_VS_CTXSW_CNT0_BASE_IDX 0
3141#define mmGDS_VS_CTXSW_CNT1 0x1354
3142#define mmGDS_VS_CTXSW_CNT1_BASE_IDX 0
3143#define mmGDS_VS_CTXSW_CNT2 0x1355
3144#define mmGDS_VS_CTXSW_CNT2_BASE_IDX 0
3145#define mmGDS_VS_CTXSW_CNT3 0x1356
3146#define mmGDS_VS_CTXSW_CNT3_BASE_IDX 0
3147#define mmGDS_PS0_CTXSW_CNT0 0x1357
3148#define mmGDS_PS0_CTXSW_CNT0_BASE_IDX 0
3149#define mmGDS_PS0_CTXSW_CNT1 0x1358
3150#define mmGDS_PS0_CTXSW_CNT1_BASE_IDX 0
3151#define mmGDS_PS0_CTXSW_CNT2 0x1359
3152#define mmGDS_PS0_CTXSW_CNT2_BASE_IDX 0
3153#define mmGDS_PS0_CTXSW_CNT3 0x135a
3154#define mmGDS_PS0_CTXSW_CNT3_BASE_IDX 0
3155#define mmGDS_PS1_CTXSW_CNT0 0x135b
3156#define mmGDS_PS1_CTXSW_CNT0_BASE_IDX 0
3157#define mmGDS_PS1_CTXSW_CNT1 0x135c
3158#define mmGDS_PS1_CTXSW_CNT1_BASE_IDX 0
3159#define mmGDS_PS1_CTXSW_CNT2 0x135d
3160#define mmGDS_PS1_CTXSW_CNT2_BASE_IDX 0
3161#define mmGDS_PS1_CTXSW_CNT3 0x135e
3162#define mmGDS_PS1_CTXSW_CNT3_BASE_IDX 0
3163#define mmGDS_PS2_CTXSW_CNT0 0x135f
3164#define mmGDS_PS2_CTXSW_CNT0_BASE_IDX 0
3165#define mmGDS_PS2_CTXSW_CNT1 0x1360
3166#define mmGDS_PS2_CTXSW_CNT1_BASE_IDX 0
3167#define mmGDS_PS2_CTXSW_CNT2 0x1361
3168#define mmGDS_PS2_CTXSW_CNT2_BASE_IDX 0
3169#define mmGDS_PS2_CTXSW_CNT3 0x1362
3170#define mmGDS_PS2_CTXSW_CNT3_BASE_IDX 0
3171#define mmGDS_PS3_CTXSW_CNT0 0x1363
3172#define mmGDS_PS3_CTXSW_CNT0_BASE_IDX 0
3173#define mmGDS_PS3_CTXSW_CNT1 0x1364
3174#define mmGDS_PS3_CTXSW_CNT1_BASE_IDX 0
3175#define mmGDS_PS3_CTXSW_CNT2 0x1365
3176#define mmGDS_PS3_CTXSW_CNT2_BASE_IDX 0
3177#define mmGDS_PS3_CTXSW_CNT3 0x1366
3178#define mmGDS_PS3_CTXSW_CNT3_BASE_IDX 0
3179#define mmGDS_PS4_CTXSW_CNT0 0x1367
3180#define mmGDS_PS4_CTXSW_CNT0_BASE_IDX 0
3181#define mmGDS_PS4_CTXSW_CNT1 0x1368
3182#define mmGDS_PS4_CTXSW_CNT1_BASE_IDX 0
3183#define mmGDS_PS4_CTXSW_CNT2 0x1369
3184#define mmGDS_PS4_CTXSW_CNT2_BASE_IDX 0
3185#define mmGDS_PS4_CTXSW_CNT3 0x136a
3186#define mmGDS_PS4_CTXSW_CNT3_BASE_IDX 0
3187#define mmGDS_PS5_CTXSW_CNT0 0x136b
3188#define mmGDS_PS5_CTXSW_CNT0_BASE_IDX 0
3189#define mmGDS_PS5_CTXSW_CNT1 0x136c
3190#define mmGDS_PS5_CTXSW_CNT1_BASE_IDX 0
3191#define mmGDS_PS5_CTXSW_CNT2 0x136d
3192#define mmGDS_PS5_CTXSW_CNT2_BASE_IDX 0
3193#define mmGDS_PS5_CTXSW_CNT3 0x136e
3194#define mmGDS_PS5_CTXSW_CNT3_BASE_IDX 0
3195#define mmGDS_PS6_CTXSW_CNT0 0x136f
3196#define mmGDS_PS6_CTXSW_CNT0_BASE_IDX 0
3197#define mmGDS_PS6_CTXSW_CNT1 0x1370
3198#define mmGDS_PS6_CTXSW_CNT1_BASE_IDX 0
3199#define mmGDS_PS6_CTXSW_CNT2 0x1371
3200#define mmGDS_PS6_CTXSW_CNT2_BASE_IDX 0
3201#define mmGDS_PS6_CTXSW_CNT3 0x1372
3202#define mmGDS_PS6_CTXSW_CNT3_BASE_IDX 0
3203#define mmGDS_PS7_CTXSW_CNT0 0x1373
3204#define mmGDS_PS7_CTXSW_CNT0_BASE_IDX 0
3205#define mmGDS_PS7_CTXSW_CNT1 0x1374
3206#define mmGDS_PS7_CTXSW_CNT1_BASE_IDX 0
3207#define mmGDS_PS7_CTXSW_CNT2 0x1375
3208#define mmGDS_PS7_CTXSW_CNT2_BASE_IDX 0
3209#define mmGDS_PS7_CTXSW_CNT3 0x1376
3210#define mmGDS_PS7_CTXSW_CNT3_BASE_IDX 0
3211#define mmGDS_GS_CTXSW_CNT0 0x1377
3212#define mmGDS_GS_CTXSW_CNT0_BASE_IDX 0
3213#define mmGDS_GS_CTXSW_CNT1 0x1378
3214#define mmGDS_GS_CTXSW_CNT1_BASE_IDX 0
3215#define mmGDS_GS_CTXSW_CNT2 0x1379
3216#define mmGDS_GS_CTXSW_CNT2_BASE_IDX 0
3217#define mmGDS_GS_CTXSW_CNT3 0x137a
3218#define mmGDS_GS_CTXSW_CNT3_BASE_IDX 0
3219
3220
3221// addressBlock: gc_rasdec
3222// base address: 0xce00
3223#define mmRAS_SIGNATURE_CONTROL 0x1380
3224#define mmRAS_SIGNATURE_CONTROL_BASE_IDX 0
3225#define mmRAS_SIGNATURE_MASK 0x1381
3226#define mmRAS_SIGNATURE_MASK_BASE_IDX 0
3227#define mmRAS_SX_SIGNATURE0 0x1382
3228#define mmRAS_SX_SIGNATURE0_BASE_IDX 0
3229#define mmRAS_SX_SIGNATURE1 0x1383
3230#define mmRAS_SX_SIGNATURE1_BASE_IDX 0
3231#define mmRAS_SX_SIGNATURE2 0x1384
3232#define mmRAS_SX_SIGNATURE2_BASE_IDX 0
3233#define mmRAS_SX_SIGNATURE3 0x1385
3234#define mmRAS_SX_SIGNATURE3_BASE_IDX 0
3235#define mmRAS_DB_SIGNATURE0 0x138b
3236#define mmRAS_DB_SIGNATURE0_BASE_IDX 0
3237#define mmRAS_PA_SIGNATURE0 0x138c
3238#define mmRAS_PA_SIGNATURE0_BASE_IDX 0
3239#define mmRAS_VGT_SIGNATURE0 0x138d
3240#define mmRAS_VGT_SIGNATURE0_BASE_IDX 0
3241#define mmRAS_SQ_SIGNATURE0 0x138e
3242#define mmRAS_SQ_SIGNATURE0_BASE_IDX 0
3243#define mmRAS_SC_SIGNATURE0 0x138f
3244#define mmRAS_SC_SIGNATURE0_BASE_IDX 0
3245#define mmRAS_SC_SIGNATURE1 0x1390
3246#define mmRAS_SC_SIGNATURE1_BASE_IDX 0
3247#define mmRAS_SC_SIGNATURE2 0x1391
3248#define mmRAS_SC_SIGNATURE2_BASE_IDX 0
3249#define mmRAS_SC_SIGNATURE3 0x1392
3250#define mmRAS_SC_SIGNATURE3_BASE_IDX 0
3251#define mmRAS_SC_SIGNATURE4 0x1393
3252#define mmRAS_SC_SIGNATURE4_BASE_IDX 0
3253#define mmRAS_SC_SIGNATURE5 0x1394
3254#define mmRAS_SC_SIGNATURE5_BASE_IDX 0
3255#define mmRAS_SC_SIGNATURE6 0x1395
3256#define mmRAS_SC_SIGNATURE6_BASE_IDX 0
3257#define mmRAS_SC_SIGNATURE7 0x1396
3258#define mmRAS_SC_SIGNATURE7_BASE_IDX 0
3259#define mmRAS_IA_SIGNATURE0 0x1397
3260#define mmRAS_IA_SIGNATURE0_BASE_IDX 0
3261#define mmRAS_IA_SIGNATURE1 0x1398
3262#define mmRAS_IA_SIGNATURE1_BASE_IDX 0
3263#define mmRAS_SPI_SIGNATURE0 0x1399
3264#define mmRAS_SPI_SIGNATURE0_BASE_IDX 0
3265#define mmRAS_SPI_SIGNATURE1 0x139a
3266#define mmRAS_SPI_SIGNATURE1_BASE_IDX 0
3267#define mmRAS_TA_SIGNATURE0 0x139b
3268#define mmRAS_TA_SIGNATURE0_BASE_IDX 0
3269#define mmRAS_TD_SIGNATURE0 0x139c
3270#define mmRAS_TD_SIGNATURE0_BASE_IDX 0
3271#define mmRAS_CB_SIGNATURE0 0x139d
3272#define mmRAS_CB_SIGNATURE0_BASE_IDX 0
3273#define mmRAS_BCI_SIGNATURE0 0x139e
3274#define mmRAS_BCI_SIGNATURE0_BASE_IDX 0
3275#define mmRAS_BCI_SIGNATURE1 0x139f
3276#define mmRAS_BCI_SIGNATURE1_BASE_IDX 0
3277#define mmRAS_TA_SIGNATURE1 0x13a0
3278#define mmRAS_TA_SIGNATURE1_BASE_IDX 0
3279
3280
3281// addressBlock: gc_gfxdec0
3282// base address: 0x28000
3283#define mmDB_RENDER_CONTROL 0x0000
3284#define mmDB_RENDER_CONTROL_BASE_IDX 1
3285#define mmDB_COUNT_CONTROL 0x0001
3286#define mmDB_COUNT_CONTROL_BASE_IDX 1
3287#define mmDB_DEPTH_VIEW 0x0002
3288#define mmDB_DEPTH_VIEW_BASE_IDX 1
3289#define mmDB_RENDER_OVERRIDE 0x0003
3290#define mmDB_RENDER_OVERRIDE_BASE_IDX 1
3291#define mmDB_RENDER_OVERRIDE2 0x0004
3292#define mmDB_RENDER_OVERRIDE2_BASE_IDX 1
3293#define mmDB_HTILE_DATA_BASE 0x0005
3294#define mmDB_HTILE_DATA_BASE_BASE_IDX 1
3295#define mmDB_HTILE_DATA_BASE_HI 0x0006
3296#define mmDB_HTILE_DATA_BASE_HI_BASE_IDX 1
3297#define mmDB_DEPTH_SIZE 0x0007
3298#define mmDB_DEPTH_SIZE_BASE_IDX 1
3299#define mmDB_DEPTH_BOUNDS_MIN 0x0008
3300#define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX 1
3301#define mmDB_DEPTH_BOUNDS_MAX 0x0009
3302#define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX 1
3303#define mmDB_STENCIL_CLEAR 0x000a
3304#define mmDB_STENCIL_CLEAR_BASE_IDX 1
3305#define mmDB_DEPTH_CLEAR 0x000b
3306#define mmDB_DEPTH_CLEAR_BASE_IDX 1
3307#define mmPA_SC_SCREEN_SCISSOR_TL 0x000c
3308#define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1
3309#define mmPA_SC_SCREEN_SCISSOR_BR 0x000d
3310#define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1
3311#define mmDB_Z_INFO 0x000e
3312#define mmDB_Z_INFO_BASE_IDX 1
3313#define mmDB_STENCIL_INFO 0x000f
3314#define mmDB_STENCIL_INFO_BASE_IDX 1
3315#define mmDB_Z_READ_BASE 0x0010
3316#define mmDB_Z_READ_BASE_BASE_IDX 1
3317#define mmDB_Z_READ_BASE_HI 0x0011
3318#define mmDB_Z_READ_BASE_HI_BASE_IDX 1
3319#define mmDB_STENCIL_READ_BASE 0x0012
3320#define mmDB_STENCIL_READ_BASE_BASE_IDX 1
3321#define mmDB_STENCIL_READ_BASE_HI 0x0013
3322#define mmDB_STENCIL_READ_BASE_HI_BASE_IDX 1
3323#define mmDB_Z_WRITE_BASE 0x0014
3324#define mmDB_Z_WRITE_BASE_BASE_IDX 1
3325#define mmDB_Z_WRITE_BASE_HI 0x0015
3326#define mmDB_Z_WRITE_BASE_HI_BASE_IDX 1
3327#define mmDB_STENCIL_WRITE_BASE 0x0016
3328#define mmDB_STENCIL_WRITE_BASE_BASE_IDX 1
3329#define mmDB_STENCIL_WRITE_BASE_HI 0x0017
3330#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
3331#define mmDB_DFSM_CONTROL 0x0018
3332#define mmDB_DFSM_CONTROL_BASE_IDX 1
3333#define mmDB_Z_INFO2 0x001a
3334#define mmDB_Z_INFO2_BASE_IDX 1
3335#define mmDB_STENCIL_INFO2 0x001b
3336#define mmDB_STENCIL_INFO2_BASE_IDX 1
3337#define mmTA_BC_BASE_ADDR 0x0020
3338#define mmTA_BC_BASE_ADDR_BASE_IDX 1
3339#define mmTA_BC_BASE_ADDR_HI 0x0021
3340#define mmTA_BC_BASE_ADDR_HI_BASE_IDX 1
3341#define mmCOHER_DEST_BASE_HI_0 0x007a
3342#define mmCOHER_DEST_BASE_HI_0_BASE_IDX 1
3343#define mmCOHER_DEST_BASE_HI_1 0x007b
3344#define mmCOHER_DEST_BASE_HI_1_BASE_IDX 1
3345#define mmCOHER_DEST_BASE_HI_2 0x007c
3346#define mmCOHER_DEST_BASE_HI_2_BASE_IDX 1
3347#define mmCOHER_DEST_BASE_HI_3 0x007d
3348#define mmCOHER_DEST_BASE_HI_3_BASE_IDX 1
3349#define mmCOHER_DEST_BASE_2 0x007e
3350#define mmCOHER_DEST_BASE_2_BASE_IDX 1
3351#define mmCOHER_DEST_BASE_3 0x007f
3352#define mmCOHER_DEST_BASE_3_BASE_IDX 1
3353#define mmPA_SC_WINDOW_OFFSET 0x0080
3354#define mmPA_SC_WINDOW_OFFSET_BASE_IDX 1
3355#define mmPA_SC_WINDOW_SCISSOR_TL 0x0081
3356#define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1
3357#define mmPA_SC_WINDOW_SCISSOR_BR 0x0082
3358#define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1
3359#define mmPA_SC_CLIPRECT_RULE 0x0083
3360#define mmPA_SC_CLIPRECT_RULE_BASE_IDX 1
3361#define mmPA_SC_CLIPRECT_0_TL 0x0084
3362#define mmPA_SC_CLIPRECT_0_TL_BASE_IDX 1
3363#define mmPA_SC_CLIPRECT_0_BR 0x0085
3364#define mmPA_SC_CLIPRECT_0_BR_BASE_IDX 1
3365#define mmPA_SC_CLIPRECT_1_TL 0x0086
3366#define mmPA_SC_CLIPRECT_1_TL_BASE_IDX 1
3367#define mmPA_SC_CLIPRECT_1_BR 0x0087
3368#define mmPA_SC_CLIPRECT_1_BR_BASE_IDX 1
3369#define mmPA_SC_CLIPRECT_2_TL 0x0088
3370#define mmPA_SC_CLIPRECT_2_TL_BASE_IDX 1
3371#define mmPA_SC_CLIPRECT_2_BR 0x0089
3372#define mmPA_SC_CLIPRECT_2_BR_BASE_IDX 1
3373#define mmPA_SC_CLIPRECT_3_TL 0x008a
3374#define mmPA_SC_CLIPRECT_3_TL_BASE_IDX 1
3375#define mmPA_SC_CLIPRECT_3_BR 0x008b
3376#define mmPA_SC_CLIPRECT_3_BR_BASE_IDX 1
3377#define mmPA_SC_EDGERULE 0x008c
3378#define mmPA_SC_EDGERULE_BASE_IDX 1
3379#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0x008d
3380#define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1
3381#define mmCB_TARGET_MASK 0x008e
3382#define mmCB_TARGET_MASK_BASE_IDX 1
3383#define mmCB_SHADER_MASK 0x008f
3384#define mmCB_SHADER_MASK_BASE_IDX 1
3385#define mmPA_SC_GENERIC_SCISSOR_TL 0x0090
3386#define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1
3387#define mmPA_SC_GENERIC_SCISSOR_BR 0x0091
3388#define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1
3389#define mmCOHER_DEST_BASE_0 0x0092
3390#define mmCOHER_DEST_BASE_0_BASE_IDX 1
3391#define mmCOHER_DEST_BASE_1 0x0093
3392#define mmCOHER_DEST_BASE_1_BASE_IDX 1
3393#define mmPA_SC_VPORT_SCISSOR_0_TL 0x0094
3394#define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1
3395#define mmPA_SC_VPORT_SCISSOR_0_BR 0x0095
3396#define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1
3397#define mmPA_SC_VPORT_SCISSOR_1_TL 0x0096
3398#define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1
3399#define mmPA_SC_VPORT_SCISSOR_1_BR 0x0097
3400#define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1
3401#define mmPA_SC_VPORT_SCISSOR_2_TL 0x0098
3402#define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1
3403#define mmPA_SC_VPORT_SCISSOR_2_BR 0x0099
3404#define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1
3405#define mmPA_SC_VPORT_SCISSOR_3_TL 0x009a
3406#define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1
3407#define mmPA_SC_VPORT_SCISSOR_3_BR 0x009b
3408#define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1
3409#define mmPA_SC_VPORT_SCISSOR_4_TL 0x009c
3410#define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1
3411#define mmPA_SC_VPORT_SCISSOR_4_BR 0x009d
3412#define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1
3413#define mmPA_SC_VPORT_SCISSOR_5_TL 0x009e
3414#define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1
3415#define mmPA_SC_VPORT_SCISSOR_5_BR 0x009f
3416#define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1
3417#define mmPA_SC_VPORT_SCISSOR_6_TL 0x00a0
3418#define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1
3419#define mmPA_SC_VPORT_SCISSOR_6_BR 0x00a1
3420#define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1
3421#define mmPA_SC_VPORT_SCISSOR_7_TL 0x00a2
3422#define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1
3423#define mmPA_SC_VPORT_SCISSOR_7_BR 0x00a3
3424#define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1
3425#define mmPA_SC_VPORT_SCISSOR_8_TL 0x00a4
3426#define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1
3427#define mmPA_SC_VPORT_SCISSOR_8_BR 0x00a5
3428#define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1
3429#define mmPA_SC_VPORT_SCISSOR_9_TL 0x00a6
3430#define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1
3431#define mmPA_SC_VPORT_SCISSOR_9_BR 0x00a7
3432#define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1
3433#define mmPA_SC_VPORT_SCISSOR_10_TL 0x00a8
3434#define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1
3435#define mmPA_SC_VPORT_SCISSOR_10_BR 0x00a9
3436#define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1
3437#define mmPA_SC_VPORT_SCISSOR_11_TL 0x00aa
3438#define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1
3439#define mmPA_SC_VPORT_SCISSOR_11_BR 0x00ab
3440#define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1
3441#define mmPA_SC_VPORT_SCISSOR_12_TL 0x00ac
3442#define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1
3443#define mmPA_SC_VPORT_SCISSOR_12_BR 0x00ad
3444#define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1
3445#define mmPA_SC_VPORT_SCISSOR_13_TL 0x00ae
3446#define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1
3447#define mmPA_SC_VPORT_SCISSOR_13_BR 0x00af
3448#define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1
3449#define mmPA_SC_VPORT_SCISSOR_14_TL 0x00b0
3450#define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1
3451#define mmPA_SC_VPORT_SCISSOR_14_BR 0x00b1
3452#define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1
3453#define mmPA_SC_VPORT_SCISSOR_15_TL 0x00b2
3454#define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1
3455#define mmPA_SC_VPORT_SCISSOR_15_BR 0x00b3
3456#define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1
3457#define mmPA_SC_VPORT_ZMIN_0 0x00b4
3458#define mmPA_SC_VPORT_ZMIN_0_BASE_IDX 1
3459#define mmPA_SC_VPORT_ZMAX_0 0x00b5
3460#define mmPA_SC_VPORT_ZMAX_0_BASE_IDX 1
3461#define mmPA_SC_VPORT_ZMIN_1 0x00b6
3462#define mmPA_SC_VPORT_ZMIN_1_BASE_IDX 1
3463#define mmPA_SC_VPORT_ZMAX_1 0x00b7
3464#define mmPA_SC_VPORT_ZMAX_1_BASE_IDX 1
3465#define mmPA_SC_VPORT_ZMIN_2 0x00b8
3466#define mmPA_SC_VPORT_ZMIN_2_BASE_IDX 1
3467#define mmPA_SC_VPORT_ZMAX_2 0x00b9
3468#define mmPA_SC_VPORT_ZMAX_2_BASE_IDX 1
3469#define mmPA_SC_VPORT_ZMIN_3 0x00ba
3470#define mmPA_SC_VPORT_ZMIN_3_BASE_IDX 1
3471#define mmPA_SC_VPORT_ZMAX_3 0x00bb
3472#define mmPA_SC_VPORT_ZMAX_3_BASE_IDX 1
3473#define mmPA_SC_VPORT_ZMIN_4 0x00bc
3474#define mmPA_SC_VPORT_ZMIN_4_BASE_IDX 1
3475#define mmPA_SC_VPORT_ZMAX_4 0x00bd
3476#define mmPA_SC_VPORT_ZMAX_4_BASE_IDX 1
3477#define mmPA_SC_VPORT_ZMIN_5 0x00be
3478#define mmPA_SC_VPORT_ZMIN_5_BASE_IDX 1
3479#define mmPA_SC_VPORT_ZMAX_5 0x00bf
3480#define mmPA_SC_VPORT_ZMAX_5_BASE_IDX 1
3481#define mmPA_SC_VPORT_ZMIN_6 0x00c0
3482#define mmPA_SC_VPORT_ZMIN_6_BASE_IDX 1
3483#define mmPA_SC_VPORT_ZMAX_6 0x00c1
3484#define mmPA_SC_VPORT_ZMAX_6_BASE_IDX 1
3485#define mmPA_SC_VPORT_ZMIN_7 0x00c2
3486#define mmPA_SC_VPORT_ZMIN_7_BASE_IDX 1
3487#define mmPA_SC_VPORT_ZMAX_7 0x00c3
3488#define mmPA_SC_VPORT_ZMAX_7_BASE_IDX 1
3489#define mmPA_SC_VPORT_ZMIN_8 0x00c4
3490#define mmPA_SC_VPORT_ZMIN_8_BASE_IDX 1
3491#define mmPA_SC_VPORT_ZMAX_8 0x00c5
3492#define mmPA_SC_VPORT_ZMAX_8_BASE_IDX 1
3493#define mmPA_SC_VPORT_ZMIN_9 0x00c6
3494#define mmPA_SC_VPORT_ZMIN_9_BASE_IDX 1
3495#define mmPA_SC_VPORT_ZMAX_9 0x00c7
3496#define mmPA_SC_VPORT_ZMAX_9_BASE_IDX 1
3497#define mmPA_SC_VPORT_ZMIN_10 0x00c8
3498#define mmPA_SC_VPORT_ZMIN_10_BASE_IDX 1
3499#define mmPA_SC_VPORT_ZMAX_10 0x00c9
3500#define mmPA_SC_VPORT_ZMAX_10_BASE_IDX 1
3501#define mmPA_SC_VPORT_ZMIN_11 0x00ca
3502#define mmPA_SC_VPORT_ZMIN_11_BASE_IDX 1
3503#define mmPA_SC_VPORT_ZMAX_11 0x00cb
3504#define mmPA_SC_VPORT_ZMAX_11_BASE_IDX 1
3505#define mmPA_SC_VPORT_ZMIN_12 0x00cc
3506#define mmPA_SC_VPORT_ZMIN_12_BASE_IDX 1
3507#define mmPA_SC_VPORT_ZMAX_12 0x00cd
3508#define mmPA_SC_VPORT_ZMAX_12_BASE_IDX 1
3509#define mmPA_SC_VPORT_ZMIN_13 0x00ce
3510#define mmPA_SC_VPORT_ZMIN_13_BASE_IDX 1
3511#define mmPA_SC_VPORT_ZMAX_13 0x00cf
3512#define mmPA_SC_VPORT_ZMAX_13_BASE_IDX 1
3513#define mmPA_SC_VPORT_ZMIN_14 0x00d0
3514#define mmPA_SC_VPORT_ZMIN_14_BASE_IDX 1
3515#define mmPA_SC_VPORT_ZMAX_14 0x00d1
3516#define mmPA_SC_VPORT_ZMAX_14_BASE_IDX 1
3517#define mmPA_SC_VPORT_ZMIN_15 0x00d2
3518#define mmPA_SC_VPORT_ZMIN_15_BASE_IDX 1
3519#define mmPA_SC_VPORT_ZMAX_15 0x00d3
3520#define mmPA_SC_VPORT_ZMAX_15_BASE_IDX 1
3521#define mmPA_SC_RASTER_CONFIG 0x00d4
3522#define mmPA_SC_RASTER_CONFIG_BASE_IDX 1
3523#define mmPA_SC_RASTER_CONFIG_1 0x00d5
3524#define mmPA_SC_RASTER_CONFIG_1_BASE_IDX 1
3525#define mmPA_SC_SCREEN_EXTENT_CONTROL 0x00d6
3526#define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1
3527#define mmPA_SC_TILE_STEERING_OVERRIDE 0x00d7
3528#define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1
3529#define mmCP_PERFMON_CNTX_CNTL 0x00d8
3530#define mmCP_PERFMON_CNTX_CNTL_BASE_IDX 1
3531#define mmCP_PIPEID 0x00d9
3532#define mmCP_PIPEID_BASE_IDX 1
3533#define mmCP_RINGID 0x00d9
3534#define mmCP_RINGID_BASE_IDX 1
3535#define mmCP_VMID 0x00da
3536#define mmCP_VMID_BASE_IDX 1
3537#define mmPA_SC_RIGHT_VERT_GRID 0x00e8
3538#define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX 1
3539#define mmPA_SC_LEFT_VERT_GRID 0x00e9
3540#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
3541#define mmPA_SC_HORIZ_GRID 0x00ea
3542#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
3543#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
3544#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
3545#define mmCB_BLEND_RED 0x0105
3546#define mmCB_BLEND_RED_BASE_IDX 1
3547#define mmCB_BLEND_GREEN 0x0106
3548#define mmCB_BLEND_GREEN_BASE_IDX 1
3549#define mmCB_BLEND_BLUE 0x0107
3550#define mmCB_BLEND_BLUE_BASE_IDX 1
3551#define mmCB_BLEND_ALPHA 0x0108
3552#define mmCB_BLEND_ALPHA_BASE_IDX 1
3553#define mmCB_DCC_CONTROL 0x0109
3554#define mmCB_DCC_CONTROL_BASE_IDX 1
3555#define mmDB_STENCIL_CONTROL 0x010b
3556#define mmDB_STENCIL_CONTROL_BASE_IDX 1
3557#define mmDB_STENCILREFMASK 0x010c
3558#define mmDB_STENCILREFMASK_BASE_IDX 1
3559#define mmDB_STENCILREFMASK_BF 0x010d
3560#define mmDB_STENCILREFMASK_BF_BASE_IDX 1
3561#define mmPA_CL_VPORT_XSCALE 0x010f
3562#define mmPA_CL_VPORT_XSCALE_BASE_IDX 1
3563#define mmPA_CL_VPORT_XOFFSET 0x0110
3564#define mmPA_CL_VPORT_XOFFSET_BASE_IDX 1
3565#define mmPA_CL_VPORT_YSCALE 0x0111
3566#define mmPA_CL_VPORT_YSCALE_BASE_IDX 1
3567#define mmPA_CL_VPORT_YOFFSET 0x0112
3568#define mmPA_CL_VPORT_YOFFSET_BASE_IDX 1
3569#define mmPA_CL_VPORT_ZSCALE 0x0113
3570#define mmPA_CL_VPORT_ZSCALE_BASE_IDX 1
3571#define mmPA_CL_VPORT_ZOFFSET 0x0114
3572#define mmPA_CL_VPORT_ZOFFSET_BASE_IDX 1
3573#define mmPA_CL_VPORT_XSCALE_1 0x0115
3574#define mmPA_CL_VPORT_XSCALE_1_BASE_IDX 1
3575#define mmPA_CL_VPORT_XOFFSET_1 0x0116
3576#define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX 1
3577#define mmPA_CL_VPORT_YSCALE_1 0x0117
3578#define mmPA_CL_VPORT_YSCALE_1_BASE_IDX 1
3579#define mmPA_CL_VPORT_YOFFSET_1 0x0118
3580#define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX 1
3581#define mmPA_CL_VPORT_ZSCALE_1 0x0119
3582#define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX 1
3583#define mmPA_CL_VPORT_ZOFFSET_1 0x011a
3584#define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1
3585#define mmPA_CL_VPORT_XSCALE_2 0x011b
3586#define mmPA_CL_VPORT_XSCALE_2_BASE_IDX 1
3587#define mmPA_CL_VPORT_XOFFSET_2 0x011c
3588#define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX 1
3589#define mmPA_CL_VPORT_YSCALE_2 0x011d
3590#define mmPA_CL_VPORT_YSCALE_2_BASE_IDX 1
3591#define mmPA_CL_VPORT_YOFFSET_2 0x011e
3592#define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX 1
3593#define mmPA_CL_VPORT_ZSCALE_2 0x011f
3594#define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX 1
3595#define mmPA_CL_VPORT_ZOFFSET_2 0x0120
3596#define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1
3597#define mmPA_CL_VPORT_XSCALE_3 0x0121
3598#define mmPA_CL_VPORT_XSCALE_3_BASE_IDX 1
3599#define mmPA_CL_VPORT_XOFFSET_3 0x0122
3600#define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX 1
3601#define mmPA_CL_VPORT_YSCALE_3 0x0123
3602#define mmPA_CL_VPORT_YSCALE_3_BASE_IDX 1
3603#define mmPA_CL_VPORT_YOFFSET_3 0x0124
3604#define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX 1
3605#define mmPA_CL_VPORT_ZSCALE_3 0x0125
3606#define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX 1
3607#define mmPA_CL_VPORT_ZOFFSET_3 0x0126
3608#define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1
3609#define mmPA_CL_VPORT_XSCALE_4 0x0127
3610#define mmPA_CL_VPORT_XSCALE_4_BASE_IDX 1
3611#define mmPA_CL_VPORT_XOFFSET_4 0x0128
3612#define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX 1
3613#define mmPA_CL_VPORT_YSCALE_4 0x0129
3614#define mmPA_CL_VPORT_YSCALE_4_BASE_IDX 1
3615#define mmPA_CL_VPORT_YOFFSET_4 0x012a
3616#define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX 1
3617#define mmPA_CL_VPORT_ZSCALE_4 0x012b
3618#define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX 1
3619#define mmPA_CL_VPORT_ZOFFSET_4 0x012c
3620#define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1
3621#define mmPA_CL_VPORT_XSCALE_5 0x012d
3622#define mmPA_CL_VPORT_XSCALE_5_BASE_IDX 1
3623#define mmPA_CL_VPORT_XOFFSET_5 0x012e
3624#define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX 1
3625#define mmPA_CL_VPORT_YSCALE_5 0x012f
3626#define mmPA_CL_VPORT_YSCALE_5_BASE_IDX 1
3627#define mmPA_CL_VPORT_YOFFSET_5 0x0130
3628#define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX 1
3629#define mmPA_CL_VPORT_ZSCALE_5 0x0131
3630#define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX 1
3631#define mmPA_CL_VPORT_ZOFFSET_5 0x0132
3632#define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1
3633#define mmPA_CL_VPORT_XSCALE_6 0x0133
3634#define mmPA_CL_VPORT_XSCALE_6_BASE_IDX 1
3635#define mmPA_CL_VPORT_XOFFSET_6 0x0134
3636#define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX 1
3637#define mmPA_CL_VPORT_YSCALE_6 0x0135
3638#define mmPA_CL_VPORT_YSCALE_6_BASE_IDX 1
3639#define mmPA_CL_VPORT_YOFFSET_6 0x0136
3640#define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX 1
3641#define mmPA_CL_VPORT_ZSCALE_6 0x0137
3642#define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX 1
3643#define mmPA_CL_VPORT_ZOFFSET_6 0x0138
3644#define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1
3645#define mmPA_CL_VPORT_XSCALE_7 0x0139
3646#define mmPA_CL_VPORT_XSCALE_7_BASE_IDX 1
3647#define mmPA_CL_VPORT_XOFFSET_7 0x013a
3648#define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX 1
3649#define mmPA_CL_VPORT_YSCALE_7 0x013b
3650#define mmPA_CL_VPORT_YSCALE_7_BASE_IDX 1
3651#define mmPA_CL_VPORT_YOFFSET_7 0x013c
3652#define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX 1
3653#define mmPA_CL_VPORT_ZSCALE_7 0x013d
3654#define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX 1
3655#define mmPA_CL_VPORT_ZOFFSET_7 0x013e
3656#define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1
3657#define mmPA_CL_VPORT_XSCALE_8 0x013f
3658#define mmPA_CL_VPORT_XSCALE_8_BASE_IDX 1
3659#define mmPA_CL_VPORT_XOFFSET_8 0x0140
3660#define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX 1
3661#define mmPA_CL_VPORT_YSCALE_8 0x0141
3662#define mmPA_CL_VPORT_YSCALE_8_BASE_IDX 1
3663#define mmPA_CL_VPORT_YOFFSET_8 0x0142
3664#define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX 1
3665#define mmPA_CL_VPORT_ZSCALE_8 0x0143
3666#define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX 1
3667#define mmPA_CL_VPORT_ZOFFSET_8 0x0144
3668#define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1
3669#define mmPA_CL_VPORT_XSCALE_9 0x0145
3670#define mmPA_CL_VPORT_XSCALE_9_BASE_IDX 1
3671#define mmPA_CL_VPORT_XOFFSET_9 0x0146
3672#define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX 1
3673#define mmPA_CL_VPORT_YSCALE_9 0x0147
3674#define mmPA_CL_VPORT_YSCALE_9_BASE_IDX 1
3675#define mmPA_CL_VPORT_YOFFSET_9 0x0148
3676#define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX 1
3677#define mmPA_CL_VPORT_ZSCALE_9 0x0149
3678#define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX 1
3679#define mmPA_CL_VPORT_ZOFFSET_9 0x014a
3680#define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1
3681#define mmPA_CL_VPORT_XSCALE_10 0x014b
3682#define mmPA_CL_VPORT_XSCALE_10_BASE_IDX 1
3683#define mmPA_CL_VPORT_XOFFSET_10 0x014c
3684#define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX 1
3685#define mmPA_CL_VPORT_YSCALE_10 0x014d
3686#define mmPA_CL_VPORT_YSCALE_10_BASE_IDX 1
3687#define mmPA_CL_VPORT_YOFFSET_10 0x014e
3688#define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX 1
3689#define mmPA_CL_VPORT_ZSCALE_10 0x014f
3690#define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX 1
3691#define mmPA_CL_VPORT_ZOFFSET_10 0x0150
3692#define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1
3693#define mmPA_CL_VPORT_XSCALE_11 0x0151
3694#define mmPA_CL_VPORT_XSCALE_11_BASE_IDX 1
3695#define mmPA_CL_VPORT_XOFFSET_11 0x0152
3696#define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX 1
3697#define mmPA_CL_VPORT_YSCALE_11 0x0153
3698#define mmPA_CL_VPORT_YSCALE_11_BASE_IDX 1
3699#define mmPA_CL_VPORT_YOFFSET_11 0x0154
3700#define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX 1
3701#define mmPA_CL_VPORT_ZSCALE_11 0x0155
3702#define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX 1
3703#define mmPA_CL_VPORT_ZOFFSET_11 0x0156
3704#define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1
3705#define mmPA_CL_VPORT_XSCALE_12 0x0157
3706#define mmPA_CL_VPORT_XSCALE_12_BASE_IDX 1
3707#define mmPA_CL_VPORT_XOFFSET_12 0x0158
3708#define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX 1
3709#define mmPA_CL_VPORT_YSCALE_12 0x0159
3710#define mmPA_CL_VPORT_YSCALE_12_BASE_IDX 1
3711#define mmPA_CL_VPORT_YOFFSET_12 0x015a
3712#define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX 1
3713#define mmPA_CL_VPORT_ZSCALE_12 0x015b
3714#define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX 1
3715#define mmPA_CL_VPORT_ZOFFSET_12 0x015c
3716#define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1
3717#define mmPA_CL_VPORT_XSCALE_13 0x015d
3718#define mmPA_CL_VPORT_XSCALE_13_BASE_IDX 1
3719#define mmPA_CL_VPORT_XOFFSET_13 0x015e
3720#define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX 1
3721#define mmPA_CL_VPORT_YSCALE_13 0x015f
3722#define mmPA_CL_VPORT_YSCALE_13_BASE_IDX 1
3723#define mmPA_CL_VPORT_YOFFSET_13 0x0160
3724#define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX 1
3725#define mmPA_CL_VPORT_ZSCALE_13 0x0161
3726#define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX 1
3727#define mmPA_CL_VPORT_ZOFFSET_13 0x0162
3728#define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1
3729#define mmPA_CL_VPORT_XSCALE_14 0x0163
3730#define mmPA_CL_VPORT_XSCALE_14_BASE_IDX 1
3731#define mmPA_CL_VPORT_XOFFSET_14 0x0164
3732#define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX 1
3733#define mmPA_CL_VPORT_YSCALE_14 0x0165
3734#define mmPA_CL_VPORT_YSCALE_14_BASE_IDX 1
3735#define mmPA_CL_VPORT_YOFFSET_14 0x0166
3736#define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX 1
3737#define mmPA_CL_VPORT_ZSCALE_14 0x0167
3738#define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX 1
3739#define mmPA_CL_VPORT_ZOFFSET_14 0x0168
3740#define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1
3741#define mmPA_CL_VPORT_XSCALE_15 0x0169
3742#define mmPA_CL_VPORT_XSCALE_15_BASE_IDX 1
3743#define mmPA_CL_VPORT_XOFFSET_15 0x016a
3744#define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX 1
3745#define mmPA_CL_VPORT_YSCALE_15 0x016b
3746#define mmPA_CL_VPORT_YSCALE_15_BASE_IDX 1
3747#define mmPA_CL_VPORT_YOFFSET_15 0x016c
3748#define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX 1
3749#define mmPA_CL_VPORT_ZSCALE_15 0x016d
3750#define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX 1
3751#define mmPA_CL_VPORT_ZOFFSET_15 0x016e
3752#define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1
3753#define mmPA_CL_UCP_0_X 0x016f
3754#define mmPA_CL_UCP_0_X_BASE_IDX 1
3755#define mmPA_CL_UCP_0_Y 0x0170
3756#define mmPA_CL_UCP_0_Y_BASE_IDX 1
3757#define mmPA_CL_UCP_0_Z 0x0171
3758#define mmPA_CL_UCP_0_Z_BASE_IDX 1
3759#define mmPA_CL_UCP_0_W 0x0172
3760#define mmPA_CL_UCP_0_W_BASE_IDX 1
3761#define mmPA_CL_UCP_1_X 0x0173
3762#define mmPA_CL_UCP_1_X_BASE_IDX 1
3763#define mmPA_CL_UCP_1_Y 0x0174
3764#define mmPA_CL_UCP_1_Y_BASE_IDX 1
3765#define mmPA_CL_UCP_1_Z 0x0175
3766#define mmPA_CL_UCP_1_Z_BASE_IDX 1
3767#define mmPA_CL_UCP_1_W 0x0176
3768#define mmPA_CL_UCP_1_W_BASE_IDX 1
3769#define mmPA_CL_UCP_2_X 0x0177
3770#define mmPA_CL_UCP_2_X_BASE_IDX 1
3771#define mmPA_CL_UCP_2_Y 0x0178
3772#define mmPA_CL_UCP_2_Y_BASE_IDX 1
3773#define mmPA_CL_UCP_2_Z 0x0179
3774#define mmPA_CL_UCP_2_Z_BASE_IDX 1
3775#define mmPA_CL_UCP_2_W 0x017a
3776#define mmPA_CL_UCP_2_W_BASE_IDX 1
3777#define mmPA_CL_UCP_3_X 0x017b
3778#define mmPA_CL_UCP_3_X_BASE_IDX 1
3779#define mmPA_CL_UCP_3_Y 0x017c
3780#define mmPA_CL_UCP_3_Y_BASE_IDX 1
3781#define mmPA_CL_UCP_3_Z 0x017d
3782#define mmPA_CL_UCP_3_Z_BASE_IDX 1
3783#define mmPA_CL_UCP_3_W 0x017e
3784#define mmPA_CL_UCP_3_W_BASE_IDX 1
3785#define mmPA_CL_UCP_4_X 0x017f
3786#define mmPA_CL_UCP_4_X_BASE_IDX 1
3787#define mmPA_CL_UCP_4_Y 0x0180
3788#define mmPA_CL_UCP_4_Y_BASE_IDX 1
3789#define mmPA_CL_UCP_4_Z 0x0181
3790#define mmPA_CL_UCP_4_Z_BASE_IDX 1
3791#define mmPA_CL_UCP_4_W 0x0182
3792#define mmPA_CL_UCP_4_W_BASE_IDX 1
3793#define mmPA_CL_UCP_5_X 0x0183
3794#define mmPA_CL_UCP_5_X_BASE_IDX 1
3795#define mmPA_CL_UCP_5_Y 0x0184
3796#define mmPA_CL_UCP_5_Y_BASE_IDX 1
3797#define mmPA_CL_UCP_5_Z 0x0185
3798#define mmPA_CL_UCP_5_Z_BASE_IDX 1
3799#define mmPA_CL_UCP_5_W 0x0186
3800#define mmPA_CL_UCP_5_W_BASE_IDX 1
3801#define mmSPI_PS_INPUT_CNTL_0 0x0191
3802#define mmSPI_PS_INPUT_CNTL_0_BASE_IDX 1
3803#define mmSPI_PS_INPUT_CNTL_1 0x0192
3804#define mmSPI_PS_INPUT_CNTL_1_BASE_IDX 1
3805#define mmSPI_PS_INPUT_CNTL_2 0x0193
3806#define mmSPI_PS_INPUT_CNTL_2_BASE_IDX 1
3807#define mmSPI_PS_INPUT_CNTL_3 0x0194
3808#define mmSPI_PS_INPUT_CNTL_3_BASE_IDX 1
3809#define mmSPI_PS_INPUT_CNTL_4 0x0195
3810#define mmSPI_PS_INPUT_CNTL_4_BASE_IDX 1
3811#define mmSPI_PS_INPUT_CNTL_5 0x0196
3812#define mmSPI_PS_INPUT_CNTL_5_BASE_IDX 1
3813#define mmSPI_PS_INPUT_CNTL_6 0x0197
3814#define mmSPI_PS_INPUT_CNTL_6_BASE_IDX 1
3815#define mmSPI_PS_INPUT_CNTL_7 0x0198
3816#define mmSPI_PS_INPUT_CNTL_7_BASE_IDX 1
3817#define mmSPI_PS_INPUT_CNTL_8 0x0199
3818#define mmSPI_PS_INPUT_CNTL_8_BASE_IDX 1
3819#define mmSPI_PS_INPUT_CNTL_9 0x019a
3820#define mmSPI_PS_INPUT_CNTL_9_BASE_IDX 1
3821#define mmSPI_PS_INPUT_CNTL_10 0x019b
3822#define mmSPI_PS_INPUT_CNTL_10_BASE_IDX 1
3823#define mmSPI_PS_INPUT_CNTL_11 0x019c
3824#define mmSPI_PS_INPUT_CNTL_11_BASE_IDX 1
3825#define mmSPI_PS_INPUT_CNTL_12 0x019d
3826#define mmSPI_PS_INPUT_CNTL_12_BASE_IDX 1
3827#define mmSPI_PS_INPUT_CNTL_13 0x019e
3828#define mmSPI_PS_INPUT_CNTL_13_BASE_IDX 1
3829#define mmSPI_PS_INPUT_CNTL_14 0x019f
3830#define mmSPI_PS_INPUT_CNTL_14_BASE_IDX 1
3831#define mmSPI_PS_INPUT_CNTL_15 0x01a0
3832#define mmSPI_PS_INPUT_CNTL_15_BASE_IDX 1
3833#define mmSPI_PS_INPUT_CNTL_16 0x01a1
3834#define mmSPI_PS_INPUT_CNTL_16_BASE_IDX 1
3835#define mmSPI_PS_INPUT_CNTL_17 0x01a2
3836#define mmSPI_PS_INPUT_CNTL_17_BASE_IDX 1
3837#define mmSPI_PS_INPUT_CNTL_18 0x01a3
3838#define mmSPI_PS_INPUT_CNTL_18_BASE_IDX 1
3839#define mmSPI_PS_INPUT_CNTL_19 0x01a4
3840#define mmSPI_PS_INPUT_CNTL_19_BASE_IDX 1
3841#define mmSPI_PS_INPUT_CNTL_20 0x01a5
3842#define mmSPI_PS_INPUT_CNTL_20_BASE_IDX 1
3843#define mmSPI_PS_INPUT_CNTL_21 0x01a6
3844#define mmSPI_PS_INPUT_CNTL_21_BASE_IDX 1
3845#define mmSPI_PS_INPUT_CNTL_22 0x01a7
3846#define mmSPI_PS_INPUT_CNTL_22_BASE_IDX 1
3847#define mmSPI_PS_INPUT_CNTL_23 0x01a8
3848#define mmSPI_PS_INPUT_CNTL_23_BASE_IDX 1
3849#define mmSPI_PS_INPUT_CNTL_24 0x01a9
3850#define mmSPI_PS_INPUT_CNTL_24_BASE_IDX 1
3851#define mmSPI_PS_INPUT_CNTL_25 0x01aa
3852#define mmSPI_PS_INPUT_CNTL_25_BASE_IDX 1
3853#define mmSPI_PS_INPUT_CNTL_26 0x01ab
3854#define mmSPI_PS_INPUT_CNTL_26_BASE_IDX 1
3855#define mmSPI_PS_INPUT_CNTL_27 0x01ac
3856#define mmSPI_PS_INPUT_CNTL_27_BASE_IDX 1
3857#define mmSPI_PS_INPUT_CNTL_28 0x01ad
3858#define mmSPI_PS_INPUT_CNTL_28_BASE_IDX 1
3859#define mmSPI_PS_INPUT_CNTL_29 0x01ae
3860#define mmSPI_PS_INPUT_CNTL_29_BASE_IDX 1
3861#define mmSPI_PS_INPUT_CNTL_30 0x01af
3862#define mmSPI_PS_INPUT_CNTL_30_BASE_IDX 1
3863#define mmSPI_PS_INPUT_CNTL_31 0x01b0
3864#define mmSPI_PS_INPUT_CNTL_31_BASE_IDX 1
3865#define mmSPI_VS_OUT_CONFIG 0x01b1
3866#define mmSPI_VS_OUT_CONFIG_BASE_IDX 1
3867#define mmSPI_PS_INPUT_ENA 0x01b3
3868#define mmSPI_PS_INPUT_ENA_BASE_IDX 1
3869#define mmSPI_PS_INPUT_ADDR 0x01b4
3870#define mmSPI_PS_INPUT_ADDR_BASE_IDX 1
3871#define mmSPI_INTERP_CONTROL_0 0x01b5
3872#define mmSPI_INTERP_CONTROL_0_BASE_IDX 1
3873#define mmSPI_PS_IN_CONTROL 0x01b6
3874#define mmSPI_PS_IN_CONTROL_BASE_IDX 1
3875#define mmSPI_BARYC_CNTL 0x01b8
3876#define mmSPI_BARYC_CNTL_BASE_IDX 1
3877#define mmSPI_TMPRING_SIZE 0x01ba
3878#define mmSPI_TMPRING_SIZE_BASE_IDX 1
3879#define mmSPI_SHADER_POS_FORMAT 0x01c3
3880#define mmSPI_SHADER_POS_FORMAT_BASE_IDX 1
3881#define mmSPI_SHADER_Z_FORMAT 0x01c4
3882#define mmSPI_SHADER_Z_FORMAT_BASE_IDX 1
3883#define mmSPI_SHADER_COL_FORMAT 0x01c5
3884#define mmSPI_SHADER_COL_FORMAT_BASE_IDX 1
3885#define mmSX_PS_DOWNCONVERT 0x01d5
3886#define mmSX_PS_DOWNCONVERT_BASE_IDX 1
3887#define mmSX_BLEND_OPT_EPSILON 0x01d6
3888#define mmSX_BLEND_OPT_EPSILON_BASE_IDX 1
3889#define mmSX_BLEND_OPT_CONTROL 0x01d7
3890#define mmSX_BLEND_OPT_CONTROL_BASE_IDX 1
3891#define mmSX_MRT0_BLEND_OPT 0x01d8
3892#define mmSX_MRT0_BLEND_OPT_BASE_IDX 1
3893#define mmSX_MRT1_BLEND_OPT 0x01d9
3894#define mmSX_MRT1_BLEND_OPT_BASE_IDX 1
3895#define mmSX_MRT2_BLEND_OPT 0x01da
3896#define mmSX_MRT2_BLEND_OPT_BASE_IDX 1
3897#define mmSX_MRT3_BLEND_OPT 0x01db
3898#define mmSX_MRT3_BLEND_OPT_BASE_IDX 1
3899#define mmSX_MRT4_BLEND_OPT 0x01dc
3900#define mmSX_MRT4_BLEND_OPT_BASE_IDX 1
3901#define mmSX_MRT5_BLEND_OPT 0x01dd
3902#define mmSX_MRT5_BLEND_OPT_BASE_IDX 1
3903#define mmSX_MRT6_BLEND_OPT 0x01de
3904#define mmSX_MRT6_BLEND_OPT_BASE_IDX 1
3905#define mmSX_MRT7_BLEND_OPT 0x01df
3906#define mmSX_MRT7_BLEND_OPT_BASE_IDX 1
3907#define mmCB_BLEND0_CONTROL 0x01e0
3908#define mmCB_BLEND0_CONTROL_BASE_IDX 1
3909#define mmCB_BLEND1_CONTROL 0x01e1
3910#define mmCB_BLEND1_CONTROL_BASE_IDX 1
3911#define mmCB_BLEND2_CONTROL 0x01e2
3912#define mmCB_BLEND2_CONTROL_BASE_IDX 1
3913#define mmCB_BLEND3_CONTROL 0x01e3
3914#define mmCB_BLEND3_CONTROL_BASE_IDX 1
3915#define mmCB_BLEND4_CONTROL 0x01e4
3916#define mmCB_BLEND4_CONTROL_BASE_IDX 1
3917#define mmCB_BLEND5_CONTROL 0x01e5
3918#define mmCB_BLEND5_CONTROL_BASE_IDX 1
3919#define mmCB_BLEND6_CONTROL 0x01e6
3920#define mmCB_BLEND6_CONTROL_BASE_IDX 1
3921#define mmCB_BLEND7_CONTROL 0x01e7
3922#define mmCB_BLEND7_CONTROL_BASE_IDX 1
3923#define mmCB_MRT0_EPITCH 0x01e8
3924#define mmCB_MRT0_EPITCH_BASE_IDX 1
3925#define mmCB_MRT1_EPITCH 0x01e9
3926#define mmCB_MRT1_EPITCH_BASE_IDX 1
3927#define mmCB_MRT2_EPITCH 0x01ea
3928#define mmCB_MRT2_EPITCH_BASE_IDX 1
3929#define mmCB_MRT3_EPITCH 0x01eb
3930#define mmCB_MRT3_EPITCH_BASE_IDX 1
3931#define mmCB_MRT4_EPITCH 0x01ec
3932#define mmCB_MRT4_EPITCH_BASE_IDX 1
3933#define mmCB_MRT5_EPITCH 0x01ed
3934#define mmCB_MRT5_EPITCH_BASE_IDX 1
3935#define mmCB_MRT6_EPITCH 0x01ee
3936#define mmCB_MRT6_EPITCH_BASE_IDX 1
3937#define mmCB_MRT7_EPITCH 0x01ef
3938#define mmCB_MRT7_EPITCH_BASE_IDX 1
3939#define mmCS_COPY_STATE 0x01f3
3940#define mmCS_COPY_STATE_BASE_IDX 1
3941#define mmGFX_COPY_STATE 0x01f4
3942#define mmGFX_COPY_STATE_BASE_IDX 1
3943#define mmPA_CL_POINT_X_RAD 0x01f5
3944#define mmPA_CL_POINT_X_RAD_BASE_IDX 1
3945#define mmPA_CL_POINT_Y_RAD 0x01f6
3946#define mmPA_CL_POINT_Y_RAD_BASE_IDX 1
3947#define mmPA_CL_POINT_SIZE 0x01f7
3948#define mmPA_CL_POINT_SIZE_BASE_IDX 1
3949#define mmPA_CL_POINT_CULL_RAD 0x01f8
3950#define mmPA_CL_POINT_CULL_RAD_BASE_IDX 1
3951#define mmVGT_DMA_BASE_HI 0x01f9
3952#define mmVGT_DMA_BASE_HI_BASE_IDX 1
3953#define mmVGT_DMA_BASE 0x01fa
3954#define mmVGT_DMA_BASE_BASE_IDX 1
3955#define mmVGT_DRAW_INITIATOR 0x01fc
3956#define mmVGT_DRAW_INITIATOR_BASE_IDX 1
3957#define mmVGT_IMMED_DATA 0x01fd
3958#define mmVGT_IMMED_DATA_BASE_IDX 1
3959#define mmVGT_EVENT_ADDRESS_REG 0x01fe
3960#define mmVGT_EVENT_ADDRESS_REG_BASE_IDX 1
3961#define mmDB_DEPTH_CONTROL 0x0200
3962#define mmDB_DEPTH_CONTROL_BASE_IDX 1
3963#define mmDB_EQAA 0x0201
3964#define mmDB_EQAA_BASE_IDX 1
3965#define mmCB_COLOR_CONTROL 0x0202
3966#define mmCB_COLOR_CONTROL_BASE_IDX 1
3967#define mmDB_SHADER_CONTROL 0x0203
3968#define mmDB_SHADER_CONTROL_BASE_IDX 1
3969#define mmPA_CL_CLIP_CNTL 0x0204
3970#define mmPA_CL_CLIP_CNTL_BASE_IDX 1
3971#define mmPA_SU_SC_MODE_CNTL 0x0205
3972#define mmPA_SU_SC_MODE_CNTL_BASE_IDX 1
3973#define mmPA_CL_VTE_CNTL 0x0206
3974#define mmPA_CL_VTE_CNTL_BASE_IDX 1
3975#define mmPA_CL_VS_OUT_CNTL 0x0207
3976#define mmPA_CL_VS_OUT_CNTL_BASE_IDX 1
3977#define mmPA_CL_NANINF_CNTL 0x0208
3978#define mmPA_CL_NANINF_CNTL_BASE_IDX 1
3979#define mmPA_SU_LINE_STIPPLE_CNTL 0x0209
3980#define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1
3981#define mmPA_SU_LINE_STIPPLE_SCALE 0x020a
3982#define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1
3983#define mmPA_SU_PRIM_FILTER_CNTL 0x020b
3984#define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1
3985#define mmPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c
3986#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1
3987#define mmPA_CL_OBJPRIM_ID_CNTL 0x020d
3988#define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX 1
3989#define mmPA_CL_NGG_CNTL 0x020e
3990#define mmPA_CL_NGG_CNTL_BASE_IDX 1
3991#define mmPA_SU_OVER_RASTERIZATION_CNTL 0x020f
3992#define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1
3993#define mmPA_SU_POINT_SIZE 0x0280
3994#define mmPA_SU_POINT_SIZE_BASE_IDX 1
3995#define mmPA_SU_POINT_MINMAX 0x0281
3996#define mmPA_SU_POINT_MINMAX_BASE_IDX 1
3997#define mmPA_SU_LINE_CNTL 0x0282
3998#define mmPA_SU_LINE_CNTL_BASE_IDX 1
3999#define mmPA_SC_LINE_STIPPLE 0x0283
4000#define mmPA_SC_LINE_STIPPLE_BASE_IDX 1
4001#define mmVGT_OUTPUT_PATH_CNTL 0x0284
4002#define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX 1
4003#define mmVGT_HOS_CNTL 0x0285
4004#define mmVGT_HOS_CNTL_BASE_IDX 1
4005#define mmVGT_HOS_MAX_TESS_LEVEL 0x0286
4006#define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1
4007#define mmVGT_HOS_MIN_TESS_LEVEL 0x0287
4008#define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1
4009#define mmVGT_HOS_REUSE_DEPTH 0x0288
4010#define mmVGT_HOS_REUSE_DEPTH_BASE_IDX 1
4011#define mmVGT_GROUP_PRIM_TYPE 0x0289
4012#define mmVGT_GROUP_PRIM_TYPE_BASE_IDX 1
4013#define mmVGT_GROUP_FIRST_DECR 0x028a
4014#define mmVGT_GROUP_FIRST_DECR_BASE_IDX 1
4015#define mmVGT_GROUP_DECR 0x028b
4016#define mmVGT_GROUP_DECR_BASE_IDX 1
4017#define mmVGT_GROUP_VECT_0_CNTL 0x028c
4018#define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX 1
4019#define mmVGT_GROUP_VECT_1_CNTL 0x028d
4020#define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX 1
4021#define mmVGT_GROUP_VECT_0_FMT_CNTL 0x028e
4022#define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX 1
4023#define mmVGT_GROUP_VECT_1_FMT_CNTL 0x028f
4024#define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX 1
4025#define mmVGT_GS_MODE 0x0290
4026#define mmVGT_GS_MODE_BASE_IDX 1
4027#define mmVGT_GS_ONCHIP_CNTL 0x0291
4028#define mmVGT_GS_ONCHIP_CNTL_BASE_IDX 1
4029#define mmPA_SC_MODE_CNTL_0 0x0292
4030#define mmPA_SC_MODE_CNTL_0_BASE_IDX 1
4031#define mmPA_SC_MODE_CNTL_1 0x0293
4032#define mmPA_SC_MODE_CNTL_1_BASE_IDX 1
4033#define mmVGT_ENHANCE 0x0294
4034#define mmVGT_ENHANCE_BASE_IDX 1
4035#define mmVGT_GS_PER_ES 0x0295
4036#define mmVGT_GS_PER_ES_BASE_IDX 1
4037#define mmVGT_ES_PER_GS 0x0296
4038#define mmVGT_ES_PER_GS_BASE_IDX 1
4039#define mmVGT_GS_PER_VS 0x0297
4040#define mmVGT_GS_PER_VS_BASE_IDX 1
4041#define mmVGT_GSVS_RING_OFFSET_1 0x0298
4042#define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX 1
4043#define mmVGT_GSVS_RING_OFFSET_2 0x0299
4044#define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX 1
4045#define mmVGT_GSVS_RING_OFFSET_3 0x029a
4046#define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX 1
4047#define mmVGT_GS_OUT_PRIM_TYPE 0x029b
4048#define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1
4049#define mmIA_ENHANCE 0x029c
4050#define mmIA_ENHANCE_BASE_IDX 1
4051#define mmVGT_DMA_SIZE 0x029d
4052#define mmVGT_DMA_SIZE_BASE_IDX 1
4053#define mmVGT_DMA_MAX_SIZE 0x029e
4054#define mmVGT_DMA_MAX_SIZE_BASE_IDX 1
4055#define mmVGT_DMA_INDEX_TYPE 0x029f
4056#define mmVGT_DMA_INDEX_TYPE_BASE_IDX 1
4057#define mmWD_ENHANCE 0x02a0
4058#define mmWD_ENHANCE_BASE_IDX 1
4059#define mmVGT_PRIMITIVEID_EN 0x02a1
4060#define mmVGT_PRIMITIVEID_EN_BASE_IDX 1
4061#define mmVGT_DMA_NUM_INSTANCES 0x02a2
4062#define mmVGT_DMA_NUM_INSTANCES_BASE_IDX 1
4063#define mmVGT_PRIMITIVEID_RESET 0x02a3
4064#define mmVGT_PRIMITIVEID_RESET_BASE_IDX 1
4065#define mmVGT_EVENT_INITIATOR 0x02a4
4066#define mmVGT_EVENT_INITIATOR_BASE_IDX 1
4067#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP 0x02a5
4068#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
4069#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
4070#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
4071#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
4072#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
4073#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
4074#define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX 1
4075#define mmVGT_ESGS_RING_ITEMSIZE 0x02ab
4076#define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX 1
4077#define mmVGT_GSVS_RING_ITEMSIZE 0x02ac
4078#define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX 1
4079#define mmVGT_REUSE_OFF 0x02ad
4080#define mmVGT_REUSE_OFF_BASE_IDX 1
4081#define mmVGT_VTX_CNT_EN 0x02ae
4082#define mmVGT_VTX_CNT_EN_BASE_IDX 1
4083#define mmDB_HTILE_SURFACE 0x02af
4084#define mmDB_HTILE_SURFACE_BASE_IDX 1
4085#define mmDB_SRESULTS_COMPARE_STATE0 0x02b0
4086#define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1
4087#define mmDB_SRESULTS_COMPARE_STATE1 0x02b1
4088#define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1
4089#define mmDB_PRELOAD_CONTROL 0x02b2
4090#define mmDB_PRELOAD_CONTROL_BASE_IDX 1
4091#define mmVGT_STRMOUT_BUFFER_SIZE_0 0x02b4
4092#define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX 1
4093#define mmVGT_STRMOUT_VTX_STRIDE_0 0x02b5
4094#define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX 1
4095#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0x02b7
4096#define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX 1
4097#define mmVGT_STRMOUT_BUFFER_SIZE_1 0x02b8
4098#define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX 1
4099#define mmVGT_STRMOUT_VTX_STRIDE_1 0x02b9
4100#define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX 1
4101#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0x02bb
4102#define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX 1
4103#define mmVGT_STRMOUT_BUFFER_SIZE_2 0x02bc
4104#define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX 1
4105#define mmVGT_STRMOUT_VTX_STRIDE_2 0x02bd
4106#define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX 1
4107#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0x02bf
4108#define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX 1
4109#define mmVGT_STRMOUT_BUFFER_SIZE_3 0x02c0
4110#define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX 1
4111#define mmVGT_STRMOUT_VTX_STRIDE_3 0x02c1
4112#define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX 1
4113#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0x02c3
4114#define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX 1
4115#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca
4116#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1
4117#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb
4118#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1
4119#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc
4120#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1
4121#define mmVGT_GS_MAX_VERT_OUT 0x02ce
4122#define mmVGT_GS_MAX_VERT_OUT_BASE_IDX 1
4123#define mmVGT_TESS_DISTRIBUTION 0x02d4
4124#define mmVGT_TESS_DISTRIBUTION_BASE_IDX 1
4125#define mmVGT_SHADER_STAGES_EN 0x02d5
4126#define mmVGT_SHADER_STAGES_EN_BASE_IDX 1
4127#define mmVGT_LS_HS_CONFIG 0x02d6
4128#define mmVGT_LS_HS_CONFIG_BASE_IDX 1
4129#define mmVGT_GS_VERT_ITEMSIZE 0x02d7
4130#define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX 1
4131#define mmVGT_GS_VERT_ITEMSIZE_1 0x02d8
4132#define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX 1
4133#define mmVGT_GS_VERT_ITEMSIZE_2 0x02d9
4134#define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX 1
4135#define mmVGT_GS_VERT_ITEMSIZE_3 0x02da
4136#define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX 1
4137#define mmVGT_TF_PARAM 0x02db
4138#define mmVGT_TF_PARAM_BASE_IDX 1
4139#define mmDB_ALPHA_TO_MASK 0x02dc
4140#define mmDB_ALPHA_TO_MASK_BASE_IDX 1
4141#define mmVGT_DISPATCH_DRAW_INDEX 0x02dd
4142#define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX 1
4143#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de
4144#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1
4145#define mmPA_SU_POLY_OFFSET_CLAMP 0x02df
4146#define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1
4147#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0
4148#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1
4149#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1
4150#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1
4151#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2
4152#define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1
4153#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3
4154#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1
4155#define mmVGT_GS_INSTANCE_CNT 0x02e4
4156#define mmVGT_GS_INSTANCE_CNT_BASE_IDX 1
4157#define mmVGT_STRMOUT_CONFIG 0x02e5
4158#define mmVGT_STRMOUT_CONFIG_BASE_IDX