| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _gc_9_0_SH_MASK_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | // addressBlock: gc_grbmdec |
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| 26 | //GRBM_CNTL |
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| 27 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 |
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| 28 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f |
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| 29 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL |
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| 30 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L |
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| 31 | //GRBM_SKEW_CNTL |
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| 32 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 |
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| 33 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 |
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| 34 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL |
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| 35 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L |
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| 36 | //GRBM_STATUS2 |
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| 37 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 |
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| 38 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 |
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| 39 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 |
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| 40 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 |
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| 41 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 |
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| 42 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 |
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| 43 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 |
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| 44 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa |
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| 45 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb |
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| 46 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc |
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| 47 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd |
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| 48 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe |
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| 49 | #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf |
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| 50 | #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 |
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| 51 | #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 |
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| 52 | #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 |
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| 53 | #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 |
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| 54 | #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 |
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| 55 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 |
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| 56 | #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 |
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| 57 | #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a |
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| 58 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c |
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| 59 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d |
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| 60 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e |
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| 61 | #define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f |
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| 62 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL |
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| 63 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L |
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| 64 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L |
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| 65 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L |
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| 66 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L |
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| 67 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L |
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| 68 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L |
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| 69 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L |
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| 70 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L |
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| 71 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L |
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| 72 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L |
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| 73 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L |
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| 74 | #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L |
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| 75 | #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L |
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| 76 | #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L |
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| 77 | #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L |
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| 78 | #define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L |
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| 79 | #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L |
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| 80 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L |
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| 81 | #define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L |
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| 82 | #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L |
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| 83 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L |
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| 84 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L |
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| 85 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L |
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| 86 | #define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L |
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| 87 | //GRBM_PWR_CNTL |
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| 88 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 |
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| 89 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 |
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| 90 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 |
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| 91 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 |
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| 92 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe |
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| 93 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf |
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| 94 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L |
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| 95 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL |
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| 96 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L |
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| 97 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L |
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| 98 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L |
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| 99 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L |
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| 100 | //GRBM_STATUS |
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| 101 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 |
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| 102 | #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 |
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| 103 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 |
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| 104 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 |
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| 105 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 |
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| 106 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc |
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| 107 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd |
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| 108 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe |
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| 109 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf |
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| 110 | #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 |
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| 111 | #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 |
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| 112 | #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 |
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| 113 | #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 |
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| 114 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 |
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| 115 | #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 |
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| 116 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 |
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| 117 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 |
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| 118 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 |
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| 119 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 |
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| 120 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a |
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| 121 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c |
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| 122 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d |
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| 123 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e |
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| 124 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f |
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| 125 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL |
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| 126 | #define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L |
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| 127 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L |
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| 128 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L |
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| 129 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L |
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| 130 | #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L |
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| 131 | #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L |
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| 132 | #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L |
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| 133 | #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L |
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| 134 | #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L |
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| 135 | #define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L |
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| 136 | #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L |
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| 137 | #define GRBM_STATUS__IA_BUSY_MASK 0x00080000L |
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| 138 | #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L |
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| 139 | #define GRBM_STATUS__WD_BUSY_MASK 0x00200000L |
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| 140 | #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L |
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| 141 | #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L |
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| 142 | #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L |
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| 143 | #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L |
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| 144 | #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L |
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| 145 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L |
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| 146 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L |
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| 147 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L |
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| 148 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
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| 149 | //GRBM_STATUS_SE0 |
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| 150 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 |
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| 151 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 |
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| 152 | #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 |
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| 153 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 |
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| 154 | #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 |
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| 155 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 |
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| 156 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 |
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| 157 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a |
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| 158 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b |
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| 159 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d |
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| 160 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e |
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| 161 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f |
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| 162 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L |
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| 163 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L |
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| 164 | #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L |
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| 165 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L |
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| 166 | #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L |
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| 167 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L |
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| 168 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L |
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| 169 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L |
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| 170 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L |
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| 171 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L |
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| 172 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L |
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| 173 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L |
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| 174 | //GRBM_STATUS_SE1 |
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| 175 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 |
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| 176 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 |
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| 177 | #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 |
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| 178 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 |
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| 179 | #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 |
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| 180 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 |
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| 181 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 |
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| 182 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a |
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| 183 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b |
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| 184 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d |
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| 185 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e |
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| 186 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f |
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| 187 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L |
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| 188 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L |
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| 189 | #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L |
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| 190 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L |
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| 191 | #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L |
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| 192 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L |
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| 193 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L |
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| 194 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L |
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| 195 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L |
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| 196 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L |
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| 197 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L |
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| 198 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L |
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| 199 | //GRBM_SOFT_RESET |
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| 200 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 |
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| 201 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 |
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| 202 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 |
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| 203 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 |
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| 204 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 |
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| 205 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 |
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| 206 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 |
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| 207 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 |
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| 208 | #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 |
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| 209 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L |
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| 210 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L |
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| 211 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L |
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| 212 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L |
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| 213 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L |
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| 214 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L |
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| 215 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L |
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| 216 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L |
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| 217 | #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L |
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| 218 | //GRBM_CGTT_CLK_CNTL |
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| 219 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 |
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| 220 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 |
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| 221 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
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| 222 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
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| 223 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
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| 224 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
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| 225 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
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| 226 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
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| 227 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
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| 228 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
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| 229 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
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| 230 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL |
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| 231 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L |
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| 232 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
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| 233 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
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| 234 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
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| 235 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
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| 236 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
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| 237 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
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| 238 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
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| 239 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
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| 240 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
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| 241 | //GRBM_GFX_CLKEN_CNTL |
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| 242 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 |
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| 243 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 |
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| 244 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL |
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| 245 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L |
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| 246 | //GRBM_WAIT_IDLE_CLOCKS |
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| 247 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 |
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| 248 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL |
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| 249 | //GRBM_STATUS_SE2 |
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| 250 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 |
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| 251 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 |
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| 252 | #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 |
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| 253 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 |
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| 254 | #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 |
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| 255 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 |
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| 256 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 |
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| 257 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a |
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| 258 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b |
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| 259 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d |
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| 260 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e |
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| 261 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f |
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| 262 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L |
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| 263 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L |
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| 264 | #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L |
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| 265 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L |
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| 266 | #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L |
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| 267 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L |
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| 268 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L |
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| 269 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L |
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| 270 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L |
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| 271 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L |
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| 272 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L |
|---|
| 273 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L |
|---|
| 274 | //GRBM_STATUS_SE3 |
|---|
| 275 | #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 |
|---|
| 276 | #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 |
|---|
| 277 | #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 |
|---|
| 278 | #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 |
|---|
| 279 | #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 |
|---|
| 280 | #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 |
|---|
| 281 | #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 |
|---|
| 282 | #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a |
|---|
| 283 | #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b |
|---|
| 284 | #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d |
|---|
| 285 | #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e |
|---|
| 286 | #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f |
|---|
| 287 | #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L |
|---|
| 288 | #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L |
|---|
| 289 | #define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L |
|---|
| 290 | #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L |
|---|
| 291 | #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L |
|---|
| 292 | #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L |
|---|
| 293 | #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L |
|---|
| 294 | #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L |
|---|
| 295 | #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L |
|---|
| 296 | #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L |
|---|
| 297 | #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L |
|---|
| 298 | #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L |
|---|
| 299 | //GRBM_READ_ERROR |
|---|
| 300 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 |
|---|
| 301 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 |
|---|
| 302 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 |
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| 303 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f |
|---|
| 304 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL |
|---|
| 305 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L |
|---|
| 306 | #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L |
|---|
| 307 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
|---|
| 308 | //GRBM_READ_ERROR2 |
|---|
| 309 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 |
|---|
| 310 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 |
|---|
| 311 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 |
|---|
| 312 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 |
|---|
| 313 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 |
|---|
| 314 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 |
|---|
| 315 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 |
|---|
| 316 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 |
|---|
| 317 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 |
|---|
| 318 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 |
|---|
| 319 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a |
|---|
| 320 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b |
|---|
| 321 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c |
|---|
| 322 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d |
|---|
| 323 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e |
|---|
| 324 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f |
|---|
| 325 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L |
|---|
| 326 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L |
|---|
| 327 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L |
|---|
| 328 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L |
|---|
| 329 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L |
|---|
| 330 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L |
|---|
| 331 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L |
|---|
| 332 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L |
|---|
| 333 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L |
|---|
| 334 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L |
|---|
| 335 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L |
|---|
| 336 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L |
|---|
| 337 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L |
|---|
| 338 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L |
|---|
| 339 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L |
|---|
| 340 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L |
|---|
| 341 | //GRBM_INT_CNTL |
|---|
| 342 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 |
|---|
| 343 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 |
|---|
| 344 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L |
|---|
| 345 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L |
|---|
| 346 | //GRBM_TRAP_OP |
|---|
| 347 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 |
|---|
| 348 | #define GRBM_TRAP_OP__RW_MASK 0x00000001L |
|---|
| 349 | //GRBM_TRAP_ADDR |
|---|
| 350 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 |
|---|
| 351 | #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL |
|---|
| 352 | //GRBM_TRAP_ADDR_MSK |
|---|
| 353 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 |
|---|
| 354 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL |
|---|
| 355 | //GRBM_TRAP_WD |
|---|
| 356 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 |
|---|
| 357 | #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL |
|---|
| 358 | //GRBM_TRAP_WD_MSK |
|---|
| 359 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 |
|---|
| 360 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL |
|---|
| 361 | //GRBM_DSM_BYPASS |
|---|
| 362 | #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 |
|---|
| 363 | #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 |
|---|
| 364 | #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L |
|---|
| 365 | #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L |
|---|
| 366 | //GRBM_WRITE_ERROR |
|---|
| 367 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 |
|---|
| 368 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 |
|---|
| 369 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 |
|---|
| 370 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 |
|---|
| 371 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc |
|---|
| 372 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd |
|---|
| 373 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 |
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| 374 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 |
|---|
| 375 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f |
|---|
| 376 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L |
|---|
| 377 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L |
|---|
| 378 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL |
|---|
| 379 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L |
|---|
| 380 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L |
|---|
| 381 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L |
|---|
| 382 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L |
|---|
| 383 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L |
|---|
| 384 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L |
|---|
| 385 | //GRBM_IOV_ERROR |
|---|
| 386 | #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 |
|---|
| 387 | #define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 |
|---|
| 388 | #define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a |
|---|
| 389 | #define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b |
|---|
| 390 | #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f |
|---|
| 391 | #define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL |
|---|
| 392 | #define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L |
|---|
| 393 | #define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L |
|---|
| 394 | #define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L |
|---|
| 395 | #define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L |
|---|
| 396 | //GRBM_CHIP_REVISION |
|---|
| 397 | #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 |
|---|
| 398 | #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL |
|---|
| 399 | //GRBM_GFX_CNTL |
|---|
| 400 | #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 |
|---|
| 401 | #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 |
|---|
| 402 | #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 |
|---|
| 403 | #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 |
|---|
| 404 | #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L |
|---|
| 405 | #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL |
|---|
| 406 | #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L |
|---|
| 407 | #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L |
|---|
| 408 | //GRBM_RSMU_CFG |
|---|
| 409 | #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 |
|---|
| 410 | #define GRBM_RSMU_CFG__QOS__SHIFT 0xc |
|---|
| 411 | #define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 |
|---|
| 412 | #define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 |
|---|
| 413 | #define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL |
|---|
| 414 | #define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L |
|---|
| 415 | #define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L |
|---|
| 416 | #define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L |
|---|
| 417 | //GRBM_IH_CREDIT |
|---|
| 418 | #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
|---|
| 419 | #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 |
|---|
| 420 | #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
|---|
| 421 | #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L |
|---|
| 422 | //GRBM_PWR_CNTL2 |
|---|
| 423 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 |
|---|
| 424 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 |
|---|
| 425 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L |
|---|
| 426 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L |
|---|
| 427 | //GRBM_UTCL2_INVAL_RANGE_START |
|---|
| 428 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 |
|---|
| 429 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL |
|---|
| 430 | //GRBM_UTCL2_INVAL_RANGE_END |
|---|
| 431 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 |
|---|
| 432 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL |
|---|
| 433 | //GRBM_RSMU_READ_ERROR |
|---|
| 434 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 |
|---|
| 435 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 |
|---|
| 436 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 |
|---|
| 437 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b |
|---|
| 438 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f |
|---|
| 439 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL |
|---|
| 440 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L |
|---|
| 441 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L |
|---|
| 442 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L |
|---|
| 443 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L |
|---|
| 444 | //GRBM_CHICKEN_BITS |
|---|
| 445 | #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 |
|---|
| 446 | #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L |
|---|
| 447 | //GRBM_NOWHERE |
|---|
| 448 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 |
|---|
| 449 | #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL |
|---|
| 450 | //GRBM_SCRATCH_REG0 |
|---|
| 451 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
|---|
| 452 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
|---|
| 453 | //GRBM_SCRATCH_REG1 |
|---|
| 454 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
|---|
| 455 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
|---|
| 456 | //GRBM_SCRATCH_REG2 |
|---|
| 457 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
|---|
| 458 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
|---|
| 459 | //GRBM_SCRATCH_REG3 |
|---|
| 460 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
|---|
| 461 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
|---|
| 462 | //GRBM_SCRATCH_REG4 |
|---|
| 463 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
|---|
| 464 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
|---|
| 465 | //GRBM_SCRATCH_REG5 |
|---|
| 466 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
|---|
| 467 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
|---|
| 468 | //GRBM_SCRATCH_REG6 |
|---|
| 469 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
|---|
| 470 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
|---|
| 471 | //GRBM_SCRATCH_REG7 |
|---|
| 472 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
|---|
| 473 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
|---|
| 474 | |
|---|
| 475 | |
|---|
| 476 | // addressBlock: gc_cpdec |
|---|
| 477 | //CP_CPC_STATUS |
|---|
| 478 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 |
|---|
| 479 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 |
|---|
| 480 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 |
|---|
| 481 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 |
|---|
| 482 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 |
|---|
| 483 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 |
|---|
| 484 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 |
|---|
| 485 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 |
|---|
| 486 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa |
|---|
| 487 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb |
|---|
| 488 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc |
|---|
| 489 | #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd |
|---|
| 490 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe |
|---|
| 491 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d |
|---|
| 492 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e |
|---|
| 493 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f |
|---|
| 494 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L |
|---|
| 495 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L |
|---|
| 496 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L |
|---|
| 497 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L |
|---|
| 498 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L |
|---|
| 499 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L |
|---|
| 500 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L |
|---|
| 501 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L |
|---|
| 502 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L |
|---|
| 503 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L |
|---|
| 504 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L |
|---|
| 505 | #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L |
|---|
| 506 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L |
|---|
| 507 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L |
|---|
| 508 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L |
|---|
| 509 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L |
|---|
| 510 | //CP_CPC_BUSY_STAT |
|---|
| 511 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 |
|---|
| 512 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 |
|---|
| 513 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 |
|---|
| 514 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 |
|---|
| 515 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 |
|---|
| 516 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 |
|---|
| 517 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 |
|---|
| 518 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 |
|---|
| 519 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 |
|---|
| 520 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 |
|---|
| 521 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa |
|---|
| 522 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb |
|---|
| 523 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc |
|---|
| 524 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd |
|---|
| 525 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 |
|---|
| 526 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 |
|---|
| 527 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 |
|---|
| 528 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 |
|---|
| 529 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 |
|---|
| 530 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 |
|---|
| 531 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 |
|---|
| 532 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 |
|---|
| 533 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 |
|---|
| 534 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 |
|---|
| 535 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a |
|---|
| 536 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b |
|---|
| 537 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c |
|---|
| 538 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d |
|---|
| 539 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L |
|---|
| 540 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L |
|---|
| 541 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L |
|---|
| 542 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L |
|---|
| 543 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L |
|---|
| 544 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L |
|---|
| 545 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L |
|---|
| 546 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L |
|---|
| 547 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L |
|---|
| 548 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L |
|---|
| 549 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L |
|---|
| 550 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L |
|---|
| 551 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L |
|---|
| 552 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L |
|---|
| 553 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L |
|---|
| 554 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L |
|---|
| 555 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L |
|---|
| 556 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L |
|---|
| 557 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L |
|---|
| 558 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L |
|---|
| 559 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L |
|---|
| 560 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L |
|---|
| 561 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L |
|---|
| 562 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L |
|---|
| 563 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L |
|---|
| 564 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L |
|---|
| 565 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L |
|---|
| 566 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L |
|---|
| 567 | //CP_CPC_STALLED_STAT1 |
|---|
| 568 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 |
|---|
| 569 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 |
|---|
| 570 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 |
|---|
| 571 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 |
|---|
| 572 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 |
|---|
| 573 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa |
|---|
| 574 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd |
|---|
| 575 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 |
|---|
| 576 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 |
|---|
| 577 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 |
|---|
| 578 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 |
|---|
| 579 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 |
|---|
| 580 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 |
|---|
| 581 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 |
|---|
| 582 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L |
|---|
| 583 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L |
|---|
| 584 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L |
|---|
| 585 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L |
|---|
| 586 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L |
|---|
| 587 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L |
|---|
| 588 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L |
|---|
| 589 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L |
|---|
| 590 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L |
|---|
| 591 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L |
|---|
| 592 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L |
|---|
| 593 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L |
|---|
| 594 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L |
|---|
| 595 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L |
|---|
| 596 | //CP_CPF_STATUS |
|---|
| 597 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 |
|---|
| 598 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 |
|---|
| 599 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 |
|---|
| 600 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 |
|---|
| 601 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 |
|---|
| 602 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 |
|---|
| 603 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 |
|---|
| 604 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 |
|---|
| 605 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa |
|---|
| 606 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb |
|---|
| 607 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc |
|---|
| 608 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd |
|---|
| 609 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe |
|---|
| 610 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf |
|---|
| 611 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 |
|---|
| 612 | #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 |
|---|
| 613 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a |
|---|
| 614 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b |
|---|
| 615 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c |
|---|
| 616 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e |
|---|
| 617 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f |
|---|
| 618 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L |
|---|
| 619 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L |
|---|
| 620 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L |
|---|
| 621 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L |
|---|
| 622 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L |
|---|
| 623 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L |
|---|
| 624 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L |
|---|
| 625 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L |
|---|
| 626 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L |
|---|
| 627 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L |
|---|
| 628 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L |
|---|
| 629 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L |
|---|
| 630 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L |
|---|
| 631 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L |
|---|
| 632 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L |
|---|
| 633 | #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L |
|---|
| 634 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L |
|---|
| 635 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L |
|---|
| 636 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L |
|---|
| 637 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L |
|---|
| 638 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L |
|---|
| 639 | //CP_CPF_BUSY_STAT |
|---|
| 640 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
|---|
| 641 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 |
|---|
| 642 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 |
|---|
| 643 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 |
|---|
| 644 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 |
|---|
| 645 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 |
|---|
| 646 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 |
|---|
| 647 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 |
|---|
| 648 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 |
|---|
| 649 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 |
|---|
| 650 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb |
|---|
| 651 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc |
|---|
| 652 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd |
|---|
| 653 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
|---|
| 654 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf |
|---|
| 655 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 |
|---|
| 656 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 |
|---|
| 657 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
|---|
| 658 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 |
|---|
| 659 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 |
|---|
| 660 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 |
|---|
| 661 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
|---|
| 662 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
|---|
| 663 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
|---|
| 664 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 |
|---|
| 665 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a |
|---|
| 666 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
|---|
| 667 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c |
|---|
| 668 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d |
|---|
| 669 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e |
|---|
| 670 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f |
|---|
| 671 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
|---|
| 672 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L |
|---|
| 673 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L |
|---|
| 674 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L |
|---|
| 675 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L |
|---|
| 676 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L |
|---|
| 677 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L |
|---|
| 678 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L |
|---|
| 679 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L |
|---|
| 680 | #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L |
|---|
| 681 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L |
|---|
| 682 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L |
|---|
| 683 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L |
|---|
| 684 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
|---|
| 685 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L |
|---|
| 686 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L |
|---|
| 687 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L |
|---|
| 688 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
|---|
| 689 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L |
|---|
| 690 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L |
|---|
| 691 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L |
|---|
| 692 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
|---|
| 693 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
|---|
| 694 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
|---|
| 695 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L |
|---|
| 696 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L |
|---|
| 697 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
|---|
| 698 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L |
|---|
| 699 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L |
|---|
| 700 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L |
|---|
| 701 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L |
|---|
| 702 | //CP_CPF_STALLED_STAT1 |
|---|
| 703 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 |
|---|
| 704 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 |
|---|
| 705 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 |
|---|
| 706 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 |
|---|
| 707 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 |
|---|
| 708 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 |
|---|
| 709 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 |
|---|
| 710 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 |
|---|
| 711 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 |
|---|
| 712 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa |
|---|
| 713 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb |
|---|
| 714 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L |
|---|
| 715 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L |
|---|
| 716 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L |
|---|
| 717 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L |
|---|
| 718 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L |
|---|
| 719 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L |
|---|
| 720 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L |
|---|
| 721 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L |
|---|
| 722 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L |
|---|
| 723 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L |
|---|
| 724 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L |
|---|
| 725 | //CP_CPC_GRBM_FREE_COUNT |
|---|
| 726 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
|---|
| 727 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
|---|
| 728 | //CP_MEC_CNTL |
|---|
| 729 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 |
|---|
| 730 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 |
|---|
| 731 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 |
|---|
| 732 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 |
|---|
| 733 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 |
|---|
| 734 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 |
|---|
| 735 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 |
|---|
| 736 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c |
|---|
| 737 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d |
|---|
| 738 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e |
|---|
| 739 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f |
|---|
| 740 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L |
|---|
| 741 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L |
|---|
| 742 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L |
|---|
| 743 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L |
|---|
| 744 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L |
|---|
| 745 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L |
|---|
| 746 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L |
|---|
| 747 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L |
|---|
| 748 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L |
|---|
| 749 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L |
|---|
| 750 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L |
|---|
| 751 | //CP_MEC_ME1_HEADER_DUMP |
|---|
| 752 | #define 0x0 |
|---|
| 753 | #define 0xFFFFFFFFL |
|---|
| 754 | //CP_MEC_ME2_HEADER_DUMP |
|---|
| 755 | #define 0x0 |
|---|
| 756 | #define 0xFFFFFFFFL |
|---|
| 757 | //CP_CPC_SCRATCH_INDEX |
|---|
| 758 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
|---|
| 759 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
|---|
| 760 | //CP_CPC_SCRATCH_DATA |
|---|
| 761 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
|---|
| 762 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
|---|
| 763 | //CP_CPF_GRBM_FREE_COUNT |
|---|
| 764 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
|---|
| 765 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L |
|---|
| 766 | //CP_CPC_HALT_HYST_COUNT |
|---|
| 767 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 |
|---|
| 768 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL |
|---|
| 769 | //CP_PRT_LOD_STATS_CNTL0 |
|---|
| 770 | #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 |
|---|
| 771 | #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL |
|---|
| 772 | //CP_PRT_LOD_STATS_CNTL1 |
|---|
| 773 | #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 |
|---|
| 774 | #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL |
|---|
| 775 | //CP_PRT_LOD_STATS_CNTL2 |
|---|
| 776 | #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 |
|---|
| 777 | #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL |
|---|
| 778 | //CP_PRT_LOD_STATS_CNTL3 |
|---|
| 779 | #define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2 |
|---|
| 780 | #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa |
|---|
| 781 | #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12 |
|---|
| 782 | #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13 |
|---|
| 783 | #define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17 |
|---|
| 784 | #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c |
|---|
| 785 | #define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL |
|---|
| 786 | #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L |
|---|
| 787 | #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L |
|---|
| 788 | #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L |
|---|
| 789 | #define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L |
|---|
| 790 | #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L |
|---|
| 791 | //CP_CE_COMPARE_COUNT |
|---|
| 792 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 |
|---|
| 793 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL |
|---|
| 794 | //CP_CE_DE_COUNT |
|---|
| 795 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
|---|
| 796 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
|---|
| 797 | //CP_DE_CE_COUNT |
|---|
| 798 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 |
|---|
| 799 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
|---|
| 800 | //CP_DE_LAST_INVAL_COUNT |
|---|
| 801 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 |
|---|
| 802 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL |
|---|
| 803 | //CP_DE_DE_COUNT |
|---|
| 804 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
|---|
| 805 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
|---|
| 806 | //CP_STALLED_STAT3 |
|---|
| 807 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
|---|
| 808 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 |
|---|
| 809 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 |
|---|
| 810 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 |
|---|
| 811 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 |
|---|
| 812 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 |
|---|
| 813 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 |
|---|
| 814 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 |
|---|
| 815 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa |
|---|
| 816 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb |
|---|
| 817 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc |
|---|
| 818 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd |
|---|
| 819 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe |
|---|
| 820 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf |
|---|
| 821 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 |
|---|
| 822 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 |
|---|
| 823 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 |
|---|
| 824 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 |
|---|
| 825 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 |
|---|
| 826 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
|---|
| 827 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L |
|---|
| 828 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L |
|---|
| 829 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L |
|---|
| 830 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L |
|---|
| 831 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L |
|---|
| 832 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L |
|---|
| 833 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L |
|---|
| 834 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L |
|---|
| 835 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L |
|---|
| 836 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L |
|---|
| 837 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L |
|---|
| 838 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L |
|---|
| 839 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L |
|---|
| 840 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L |
|---|
| 841 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L |
|---|
| 842 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L |
|---|
| 843 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L |
|---|
| 844 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L |
|---|
| 845 | //CP_STALLED_STAT1 |
|---|
| 846 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 |
|---|
| 847 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 |
|---|
| 848 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 |
|---|
| 849 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa |
|---|
| 850 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb |
|---|
| 851 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc |
|---|
| 852 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd |
|---|
| 853 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe |
|---|
| 854 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf |
|---|
| 855 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 |
|---|
| 856 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 |
|---|
| 857 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 |
|---|
| 858 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a |
|---|
| 859 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b |
|---|
| 860 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c |
|---|
| 861 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d |
|---|
| 862 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L |
|---|
| 863 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L |
|---|
| 864 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L |
|---|
| 865 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L |
|---|
| 866 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L |
|---|
| 867 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L |
|---|
| 868 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L |
|---|
| 869 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L |
|---|
| 870 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L |
|---|
| 871 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L |
|---|
| 872 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L |
|---|
| 873 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L |
|---|
| 874 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L |
|---|
| 875 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L |
|---|
| 876 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L |
|---|
| 877 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L |
|---|
| 878 | //CP_STALLED_STAT2 |
|---|
| 879 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
|---|
| 880 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 |
|---|
| 881 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 |
|---|
| 882 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 |
|---|
| 883 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 |
|---|
| 884 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 |
|---|
| 885 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 |
|---|
| 886 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa |
|---|
| 887 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb |
|---|
| 888 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc |
|---|
| 889 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd |
|---|
| 890 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe |
|---|
| 891 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf |
|---|
| 892 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 |
|---|
| 893 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 |
|---|
| 894 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 |
|---|
| 895 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 |
|---|
| 896 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 |
|---|
| 897 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 |
|---|
| 898 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 |
|---|
| 899 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 |
|---|
| 900 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 |
|---|
| 901 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 |
|---|
| 902 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a |
|---|
| 903 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b |
|---|
| 904 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c |
|---|
| 905 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d |
|---|
| 906 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e |
|---|
| 907 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f |
|---|
| 908 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
|---|
| 909 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L |
|---|
| 910 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L |
|---|
| 911 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L |
|---|
| 912 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L |
|---|
| 913 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L |
|---|
| 914 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L |
|---|
| 915 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L |
|---|
| 916 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L |
|---|
| 917 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L |
|---|
| 918 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L |
|---|
| 919 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L |
|---|
| 920 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L |
|---|
| 921 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L |
|---|
| 922 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L |
|---|
| 923 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L |
|---|
| 924 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L |
|---|
| 925 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L |
|---|
| 926 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L |
|---|
| 927 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L |
|---|
| 928 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L |
|---|
| 929 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L |
|---|
| 930 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L |
|---|
| 931 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L |
|---|
| 932 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L |
|---|
| 933 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L |
|---|
| 934 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L |
|---|
| 935 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L |
|---|
| 936 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L |
|---|
| 937 | //CP_BUSY_STAT |
|---|
| 938 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
|---|
| 939 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 |
|---|
| 940 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 |
|---|
| 941 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 |
|---|
| 942 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 |
|---|
| 943 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa |
|---|
| 944 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc |
|---|
| 945 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd |
|---|
| 946 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe |
|---|
| 947 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf |
|---|
| 948 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 |
|---|
| 949 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 |
|---|
| 950 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 |
|---|
| 951 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 |
|---|
| 952 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 |
|---|
| 953 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 |
|---|
| 954 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
|---|
| 955 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L |
|---|
| 956 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L |
|---|
| 957 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L |
|---|
| 958 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L |
|---|
| 959 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L |
|---|
| 960 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L |
|---|
| 961 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L |
|---|
| 962 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L |
|---|
| 963 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L |
|---|
| 964 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L |
|---|
| 965 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L |
|---|
| 966 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L |
|---|
| 967 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L |
|---|
| 968 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L |
|---|
| 969 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L |
|---|
| 970 | //CP_STAT |
|---|
| 971 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 |
|---|
| 972 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa |
|---|
| 973 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb |
|---|
| 974 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc |
|---|
| 975 | #define CP_STAT__DC_BUSY__SHIFT 0xd |
|---|
| 976 | #define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe |
|---|
| 977 | #define CP_STAT__PFP_BUSY__SHIFT 0xf |
|---|
| 978 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 |
|---|
| 979 | #define CP_STAT__ME_BUSY__SHIFT 0x11 |
|---|
| 980 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 |
|---|
| 981 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 |
|---|
| 982 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 |
|---|
| 983 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 |
|---|
| 984 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 |
|---|
| 985 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 |
|---|
| 986 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 |
|---|
| 987 | #define CP_STAT__CE_BUSY__SHIFT 0x1a |
|---|
| 988 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b |
|---|
| 989 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c |
|---|
| 990 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d |
|---|
| 991 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e |
|---|
| 992 | #define CP_STAT__CP_BUSY__SHIFT 0x1f |
|---|
| 993 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L |
|---|
| 994 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L |
|---|
| 995 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L |
|---|
| 996 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L |
|---|
| 997 | #define CP_STAT__DC_BUSY_MASK 0x00002000L |
|---|
| 998 | #define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L |
|---|
| 999 | #define CP_STAT__PFP_BUSY_MASK 0x00008000L |
|---|
| 1000 | #define CP_STAT__MEQ_BUSY_MASK 0x00010000L |
|---|
| 1001 | #define CP_STAT__ME_BUSY_MASK 0x00020000L |
|---|
| 1002 | #define CP_STAT__QUERY_BUSY_MASK 0x00040000L |
|---|
| 1003 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L |
|---|
| 1004 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L |
|---|
| 1005 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L |
|---|
| 1006 | #define CP_STAT__DMA_BUSY_MASK 0x00400000L |
|---|
| 1007 | #define CP_STAT__RCIU_BUSY_MASK 0x00800000L |
|---|
| 1008 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L |
|---|
| 1009 | #define CP_STAT__CE_BUSY_MASK 0x04000000L |
|---|
| 1010 | #define CP_STAT__TCIU_BUSY_MASK 0x08000000L |
|---|
| 1011 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L |
|---|
| 1012 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L |
|---|
| 1013 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L |
|---|
| 1014 | #define CP_STAT__CP_BUSY_MASK 0x80000000L |
|---|
| 1015 | //CP_ME_HEADER_DUMP |
|---|
| 1016 | #define 0x0 |
|---|
| 1017 | #define 0xFFFFFFFFL |
|---|
| 1018 | //CP_PFP_HEADER_DUMP |
|---|
| 1019 | #define 0x0 |
|---|
| 1020 | #define 0xFFFFFFFFL |
|---|
| 1021 | //CP_GRBM_FREE_COUNT |
|---|
| 1022 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
|---|
| 1023 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 |
|---|
| 1024 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 |
|---|
| 1025 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
|---|
| 1026 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L |
|---|
| 1027 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L |
|---|
| 1028 | //CP_CE_HEADER_DUMP |
|---|
| 1029 | #define 0x0 |
|---|
| 1030 | #define 0xFFFFFFFFL |
|---|
| 1031 | //CP_PFP_INSTR_PNTR |
|---|
| 1032 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
|---|
| 1033 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
|---|
| 1034 | //CP_ME_INSTR_PNTR |
|---|
| 1035 | #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
|---|
| 1036 | #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
|---|
| 1037 | //CP_CE_INSTR_PNTR |
|---|
| 1038 | #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
|---|
| 1039 | #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
|---|
| 1040 | //CP_MEC1_INSTR_PNTR |
|---|
| 1041 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
|---|
| 1042 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
|---|
| 1043 | //CP_MEC2_INSTR_PNTR |
|---|
| 1044 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
|---|
| 1045 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
|---|
| 1046 | //CP_CSF_STAT |
|---|
| 1047 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 |
|---|
| 1048 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L |
|---|
| 1049 | //CP_ME_CNTL |
|---|
| 1050 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 |
|---|
| 1051 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 |
|---|
| 1052 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 |
|---|
| 1053 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 |
|---|
| 1054 | #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 |
|---|
| 1055 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 |
|---|
| 1056 | #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 |
|---|
| 1057 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 |
|---|
| 1058 | #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 |
|---|
| 1059 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 |
|---|
| 1060 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 |
|---|
| 1061 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a |
|---|
| 1062 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b |
|---|
| 1063 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c |
|---|
| 1064 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d |
|---|
| 1065 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L |
|---|
| 1066 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L |
|---|
| 1067 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L |
|---|
| 1068 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L |
|---|
| 1069 | #define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L |
|---|
| 1070 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L |
|---|
| 1071 | #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L |
|---|
| 1072 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L |
|---|
| 1073 | #define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L |
|---|
| 1074 | #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L |
|---|
| 1075 | #define CP_ME_CNTL__CE_STEP_MASK 0x02000000L |
|---|
| 1076 | #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L |
|---|
| 1077 | #define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L |
|---|
| 1078 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L |
|---|
| 1079 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000L |
|---|
| 1080 | //CP_CNTX_STAT |
|---|
| 1081 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 |
|---|
| 1082 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 |
|---|
| 1083 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 |
|---|
| 1084 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c |
|---|
| 1085 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL |
|---|
| 1086 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L |
|---|
| 1087 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L |
|---|
| 1088 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L |
|---|
| 1089 | //CP_ME_PREEMPTION |
|---|
| 1090 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 |
|---|
| 1091 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L |
|---|
| 1092 | //CP_ROQ_THRESHOLDS |
|---|
| 1093 | #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 |
|---|
| 1094 | #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 |
|---|
| 1095 | #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL |
|---|
| 1096 | #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L |
|---|
| 1097 | //CP_MEQ_STQ_THRESHOLD |
|---|
| 1098 | #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 |
|---|
| 1099 | #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL |
|---|
| 1100 | //CP_RB2_RPTR |
|---|
| 1101 | #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 |
|---|
| 1102 | #define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL |
|---|
| 1103 | //CP_RB1_RPTR |
|---|
| 1104 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 |
|---|
| 1105 | #define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL |
|---|
| 1106 | //CP_RB0_RPTR |
|---|
| 1107 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 |
|---|
| 1108 | #define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL |
|---|
| 1109 | //CP_RB_RPTR |
|---|
| 1110 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 |
|---|
| 1111 | #define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL |
|---|
| 1112 | //CP_RB_WPTR_DELAY |
|---|
| 1113 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 |
|---|
| 1114 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c |
|---|
| 1115 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL |
|---|
| 1116 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L |
|---|
| 1117 | //CP_RB_WPTR_POLL_CNTL |
|---|
| 1118 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 |
|---|
| 1119 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
|---|
| 1120 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL |
|---|
| 1121 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
|---|
| 1122 | //CP_ROQ1_THRESHOLDS |
|---|
| 1123 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 |
|---|
| 1124 | #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 |
|---|
| 1125 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 |
|---|
| 1126 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 |
|---|
| 1127 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL |
|---|
| 1128 | #define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L |
|---|
| 1129 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L |
|---|
| 1130 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L |
|---|
| 1131 | //CP_ROQ2_THRESHOLDS |
|---|
| 1132 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 |
|---|
| 1133 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 |
|---|
| 1134 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 |
|---|
| 1135 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 |
|---|
| 1136 | #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL |
|---|
| 1137 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L |
|---|
| 1138 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L |
|---|
| 1139 | #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L |
|---|
| 1140 | //CP_STQ_THRESHOLDS |
|---|
| 1141 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 |
|---|
| 1142 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 |
|---|
| 1143 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 |
|---|
| 1144 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL |
|---|
| 1145 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L |
|---|
| 1146 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L |
|---|
| 1147 | //CP_QUEUE_THRESHOLDS |
|---|
| 1148 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 |
|---|
| 1149 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 |
|---|
| 1150 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL |
|---|
| 1151 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L |
|---|
| 1152 | //CP_MEQ_THRESHOLDS |
|---|
| 1153 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 |
|---|
| 1154 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 |
|---|
| 1155 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL |
|---|
| 1156 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L |
|---|
| 1157 | //CP_ROQ_AVAIL |
|---|
| 1158 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 |
|---|
| 1159 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 |
|---|
| 1160 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL |
|---|
| 1161 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L |
|---|
| 1162 | //CP_STQ_AVAIL |
|---|
| 1163 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 |
|---|
| 1164 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL |
|---|
| 1165 | //CP_ROQ2_AVAIL |
|---|
| 1166 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 |
|---|
| 1167 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL |
|---|
| 1168 | //CP_MEQ_AVAIL |
|---|
| 1169 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 |
|---|
| 1170 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL |
|---|
| 1171 | //CP_CMD_INDEX |
|---|
| 1172 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 |
|---|
| 1173 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc |
|---|
| 1174 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 |
|---|
| 1175 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL |
|---|
| 1176 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L |
|---|
| 1177 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L |
|---|
| 1178 | //CP_CMD_DATA |
|---|
| 1179 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 |
|---|
| 1180 | #define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL |
|---|
| 1181 | //CP_ROQ_RB_STAT |
|---|
| 1182 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 |
|---|
| 1183 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 |
|---|
| 1184 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL |
|---|
| 1185 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L |
|---|
| 1186 | //CP_ROQ_IB1_STAT |
|---|
| 1187 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 |
|---|
| 1188 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 |
|---|
| 1189 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL |
|---|
| 1190 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L |
|---|
| 1191 | //CP_ROQ_IB2_STAT |
|---|
| 1192 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 |
|---|
| 1193 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 |
|---|
| 1194 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL |
|---|
| 1195 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L |
|---|
| 1196 | //CP_STQ_STAT |
|---|
| 1197 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 |
|---|
| 1198 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL |
|---|
| 1199 | //CP_STQ_WR_STAT |
|---|
| 1200 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 |
|---|
| 1201 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL |
|---|
| 1202 | //CP_MEQ_STAT |
|---|
| 1203 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 |
|---|
| 1204 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 |
|---|
| 1205 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL |
|---|
| 1206 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L |
|---|
| 1207 | //CP_CEQ1_AVAIL |
|---|
| 1208 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 |
|---|
| 1209 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 |
|---|
| 1210 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL |
|---|
| 1211 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L |
|---|
| 1212 | //CP_CEQ2_AVAIL |
|---|
| 1213 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 |
|---|
| 1214 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL |
|---|
| 1215 | //CP_CE_ROQ_RB_STAT |
|---|
| 1216 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 |
|---|
| 1217 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 |
|---|
| 1218 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL |
|---|
| 1219 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L |
|---|
| 1220 | //CP_CE_ROQ_IB1_STAT |
|---|
| 1221 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 |
|---|
| 1222 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 |
|---|
| 1223 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL |
|---|
| 1224 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L |
|---|
| 1225 | //CP_CE_ROQ_IB2_STAT |
|---|
| 1226 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 |
|---|
| 1227 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 |
|---|
| 1228 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL |
|---|
| 1229 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L |
|---|
| 1230 | //CP_INT_STAT_DEBUG |
|---|
| 1231 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb |
|---|
| 1232 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
|---|
| 1233 | #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
|---|
| 1234 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
|---|
| 1235 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 |
|---|
| 1236 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 |
|---|
| 1237 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 |
|---|
| 1238 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 |
|---|
| 1239 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 |
|---|
| 1240 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
|---|
| 1241 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
|---|
| 1242 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
|---|
| 1243 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
|---|
| 1244 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
|---|
| 1245 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
|---|
| 1246 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
|---|
| 1247 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L |
|---|
| 1248 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
|---|
| 1249 | #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
|---|
| 1250 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
|---|
| 1251 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L |
|---|
| 1252 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L |
|---|
| 1253 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L |
|---|
| 1254 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L |
|---|
| 1255 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L |
|---|
| 1256 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
|---|
| 1257 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
|---|
| 1258 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
|---|
| 1259 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
|---|
| 1260 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
|---|
| 1261 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
|---|
| 1262 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
|---|
| 1263 | |
|---|
| 1264 | |
|---|
| 1265 | // addressBlock: gc_padec |
|---|
| 1266 | //VGT_VTX_VECT_EJECT_REG |
|---|
| 1267 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 |
|---|
| 1268 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL |
|---|
| 1269 | //VGT_DMA_DATA_FIFO_DEPTH |
|---|
| 1270 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 |
|---|
| 1271 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 |
|---|
| 1272 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL |
|---|
| 1273 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L |
|---|
| 1274 | //VGT_DMA_REQ_FIFO_DEPTH |
|---|
| 1275 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 |
|---|
| 1276 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL |
|---|
| 1277 | //VGT_DRAW_INIT_FIFO_DEPTH |
|---|
| 1278 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 |
|---|
| 1279 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL |
|---|
| 1280 | //VGT_LAST_COPY_STATE |
|---|
| 1281 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
|---|
| 1282 | #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 |
|---|
| 1283 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
|---|
| 1284 | #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L |
|---|
| 1285 | //VGT_CACHE_INVALIDATION |
|---|
| 1286 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 |
|---|
| 1287 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 |
|---|
| 1288 | #define 0x5 |
|---|
| 1289 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 |
|---|
| 1290 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 |
|---|
| 1291 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb |
|---|
| 1292 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc |
|---|
| 1293 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd |
|---|
| 1294 | #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 |
|---|
| 1295 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 |
|---|
| 1296 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 |
|---|
| 1297 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 |
|---|
| 1298 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c |
|---|
| 1299 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d |
|---|
| 1300 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L |
|---|
| 1301 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L |
|---|
| 1302 | #define 0x00000020L |
|---|
| 1303 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L |
|---|
| 1304 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L |
|---|
| 1305 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L |
|---|
| 1306 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L |
|---|
| 1307 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L |
|---|
| 1308 | #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L |
|---|
| 1309 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L |
|---|
| 1310 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L |
|---|
| 1311 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L |
|---|
| 1312 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L |
|---|
| 1313 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L |
|---|
| 1314 | //VGT_RESET_DEBUG |
|---|
| 1315 | #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 |
|---|
| 1316 | #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 |
|---|
| 1317 | #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 |
|---|
| 1318 | #define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L |
|---|
| 1319 | #define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L |
|---|
| 1320 | #define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L |
|---|
| 1321 | //VGT_STRMOUT_DELAY |
|---|
| 1322 | #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 |
|---|
| 1323 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 |
|---|
| 1324 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb |
|---|
| 1325 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe |
|---|
| 1326 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 |
|---|
| 1327 | #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL |
|---|
| 1328 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L |
|---|
| 1329 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L |
|---|
| 1330 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L |
|---|
| 1331 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L |
|---|
| 1332 | //VGT_FIFO_DEPTHS |
|---|
| 1333 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 |
|---|
| 1334 | #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 |
|---|
| 1335 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 |
|---|
| 1336 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 |
|---|
| 1337 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL |
|---|
| 1338 | #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L |
|---|
| 1339 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L |
|---|
| 1340 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L |
|---|
| 1341 | //VGT_GS_VERTEX_REUSE |
|---|
| 1342 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 |
|---|
| 1343 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL |
|---|
| 1344 | //VGT_MC_LAT_CNTL |
|---|
| 1345 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 |
|---|
| 1346 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL |
|---|
| 1347 | //IA_CNTL_STATUS |
|---|
| 1348 | #define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 |
|---|
| 1349 | #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 |
|---|
| 1350 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 |
|---|
| 1351 | #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 |
|---|
| 1352 | #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 |
|---|
| 1353 | #define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L |
|---|
| 1354 | #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L |
|---|
| 1355 | #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L |
|---|
| 1356 | #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L |
|---|
| 1357 | #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L |
|---|
| 1358 | //VGT_CNTL_STATUS |
|---|
| 1359 | #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 |
|---|
| 1360 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 |
|---|
| 1361 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 |
|---|
| 1362 | #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 |
|---|
| 1363 | #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 |
|---|
| 1364 | #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 |
|---|
| 1365 | #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 |
|---|
| 1366 | #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 |
|---|
| 1367 | #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 |
|---|
| 1368 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 |
|---|
| 1369 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa |
|---|
| 1370 | #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L |
|---|
| 1371 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L |
|---|
| 1372 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L |
|---|
| 1373 | #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L |
|---|
| 1374 | #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L |
|---|
| 1375 | #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L |
|---|
| 1376 | #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L |
|---|
| 1377 | #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L |
|---|
| 1378 | #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L |
|---|
| 1379 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L |
|---|
| 1380 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L |
|---|
| 1381 | //WD_CNTL_STATUS |
|---|
| 1382 | #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 |
|---|
| 1383 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 |
|---|
| 1384 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 |
|---|
| 1385 | #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 |
|---|
| 1386 | #define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L |
|---|
| 1387 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L |
|---|
| 1388 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L |
|---|
| 1389 | #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L |
|---|
| 1390 | //CC_GC_PRIM_CONFIG |
|---|
| 1391 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
|---|
| 1392 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
|---|
| 1393 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
|---|
| 1394 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
|---|
| 1395 | //GC_USER_PRIM_CONFIG |
|---|
| 1396 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
|---|
| 1397 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
|---|
| 1398 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
|---|
| 1399 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
|---|
| 1400 | //WD_QOS |
|---|
| 1401 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 |
|---|
| 1402 | #define WD_QOS__DRAW_STALL_MASK 0x00000001L |
|---|
| 1403 | //WD_UTCL1_CNTL |
|---|
| 1404 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
|---|
| 1405 | #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
|---|
| 1406 | #define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
|---|
| 1407 | #define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
|---|
| 1408 | #define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
|---|
| 1409 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
|---|
| 1410 | #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
|---|
| 1411 | #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
|---|
| 1412 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
|---|
| 1413 | #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
|---|
| 1414 | #define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
|---|
| 1415 | #define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
|---|
| 1416 | #define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
|---|
| 1417 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
|---|
| 1418 | #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
|---|
| 1419 | #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
|---|
| 1420 | //WD_UTCL1_STATUS |
|---|
| 1421 | #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
|---|
| 1422 | #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
|---|
| 1423 | #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
|---|
| 1424 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
|---|
| 1425 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
|---|
| 1426 | #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
|---|
| 1427 | #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
|---|
| 1428 | #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
|---|
| 1429 | #define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
|---|
| 1430 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
|---|
| 1431 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
|---|
| 1432 | #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
|---|
| 1433 | //IA_UTCL1_CNTL |
|---|
| 1434 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
|---|
| 1435 | #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
|---|
| 1436 | #define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
|---|
| 1437 | #define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
|---|
| 1438 | #define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
|---|
| 1439 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
|---|
| 1440 | #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
|---|
| 1441 | #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d |
|---|
| 1442 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
|---|
| 1443 | #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
|---|
| 1444 | #define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
|---|
| 1445 | #define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
|---|
| 1446 | #define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
|---|
| 1447 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
|---|
| 1448 | #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
|---|
| 1449 | #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L |
|---|
| 1450 | //IA_UTCL1_STATUS |
|---|
| 1451 | #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
|---|
| 1452 | #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
|---|
| 1453 | #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
|---|
| 1454 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
|---|
| 1455 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
|---|
| 1456 | #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
|---|
| 1457 | #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
|---|
| 1458 | #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
|---|
| 1459 | #define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
|---|
| 1460 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
|---|
| 1461 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
|---|
| 1462 | #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
|---|
| 1463 | //VGT_SYS_CONFIG |
|---|
| 1464 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 |
|---|
| 1465 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 |
|---|
| 1466 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 |
|---|
| 1467 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L |
|---|
| 1468 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL |
|---|
| 1469 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L |
|---|
| 1470 | //VGT_VS_MAX_WAVE_ID |
|---|
| 1471 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
|---|
| 1472 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
|---|
| 1473 | //VGT_GS_MAX_WAVE_ID |
|---|
| 1474 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
|---|
| 1475 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
|---|
| 1476 | //GFX_PIPE_CONTROL |
|---|
| 1477 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 |
|---|
| 1478 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd |
|---|
| 1479 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 |
|---|
| 1480 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL |
|---|
| 1481 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L |
|---|
| 1482 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L |
|---|
| 1483 | //CC_GC_SHADER_ARRAY_CONFIG |
|---|
| 1484 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 |
|---|
| 1485 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L |
|---|
| 1486 | //GC_USER_SHADER_ARRAY_CONFIG |
|---|
| 1487 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 |
|---|
| 1488 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L |
|---|
| 1489 | //VGT_DMA_PRIMITIVE_TYPE |
|---|
| 1490 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
|---|
| 1491 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
|---|
| 1492 | //VGT_DMA_CONTROL |
|---|
| 1493 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 |
|---|
| 1494 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 |
|---|
| 1495 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 |
|---|
| 1496 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 |
|---|
| 1497 | #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 |
|---|
| 1498 | #define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 |
|---|
| 1499 | #define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 |
|---|
| 1500 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
|---|
| 1501 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L |
|---|
| 1502 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L |
|---|
| 1503 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L |
|---|
| 1504 | #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L |
|---|
| 1505 | #define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L |
|---|
| 1506 | #define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L |
|---|
| 1507 | //VGT_DMA_LS_HS_CONFIG |
|---|
| 1508 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
|---|
| 1509 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
|---|
| 1510 | //WD_BUF_RESOURCE_1 |
|---|
| 1511 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 |
|---|
| 1512 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 |
|---|
| 1513 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL |
|---|
| 1514 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L |
|---|
| 1515 | //WD_BUF_RESOURCE_2 |
|---|
| 1516 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 |
|---|
| 1517 | #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf |
|---|
| 1518 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 |
|---|
| 1519 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL |
|---|
| 1520 | #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L |
|---|
| 1521 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L |
|---|
| 1522 | //PA_CL_CNTL_STATUS |
|---|
| 1523 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 |
|---|
| 1524 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 |
|---|
| 1525 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 |
|---|
| 1526 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L |
|---|
| 1527 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L |
|---|
| 1528 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L |
|---|
| 1529 | //PA_CL_ENHANCE |
|---|
| 1530 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 |
|---|
| 1531 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 |
|---|
| 1532 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 |
|---|
| 1533 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 |
|---|
| 1534 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 |
|---|
| 1535 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 |
|---|
| 1536 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 |
|---|
| 1537 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 |
|---|
| 1538 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 |
|---|
| 1539 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb |
|---|
| 1540 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc |
|---|
| 1541 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe |
|---|
| 1542 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c |
|---|
| 1543 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d |
|---|
| 1544 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e |
|---|
| 1545 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f |
|---|
| 1546 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L |
|---|
| 1547 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L |
|---|
| 1548 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L |
|---|
| 1549 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L |
|---|
| 1550 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L |
|---|
| 1551 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L |
|---|
| 1552 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L |
|---|
| 1553 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L |
|---|
| 1554 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L |
|---|
| 1555 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L |
|---|
| 1556 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L |
|---|
| 1557 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L |
|---|
| 1558 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L |
|---|
| 1559 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L |
|---|
| 1560 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L |
|---|
| 1561 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L |
|---|
| 1562 | //PA_CL_RESET_DEBUG |
|---|
| 1563 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 |
|---|
| 1564 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L |
|---|
| 1565 | //PA_SU_CNTL_STATUS |
|---|
| 1566 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f |
|---|
| 1567 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L |
|---|
| 1568 | //PA_SC_FIFO_DEPTH_CNTL |
|---|
| 1569 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 |
|---|
| 1570 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL |
|---|
| 1571 | //PA_SC_P3D_TRAP_SCREEN_HV_LOCK |
|---|
| 1572 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
|---|
| 1573 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
|---|
| 1574 | //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK |
|---|
| 1575 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
|---|
| 1576 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
|---|
| 1577 | //PA_SC_TRAP_SCREEN_HV_LOCK |
|---|
| 1578 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
|---|
| 1579 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
|---|
| 1580 | //PA_SC_FORCE_EOV_MAX_CNTS |
|---|
| 1581 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 |
|---|
| 1582 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 |
|---|
| 1583 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL |
|---|
| 1584 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L |
|---|
| 1585 | //PA_SC_BINNER_EVENT_CNTL_0 |
|---|
| 1586 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 |
|---|
| 1587 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 |
|---|
| 1588 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 |
|---|
| 1589 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 |
|---|
| 1590 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 |
|---|
| 1591 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa |
|---|
| 1592 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc |
|---|
| 1593 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe |
|---|
| 1594 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 |
|---|
| 1595 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 |
|---|
| 1596 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 |
|---|
| 1597 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 |
|---|
| 1598 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 |
|---|
| 1599 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a |
|---|
| 1600 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c |
|---|
| 1601 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e |
|---|
| 1602 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L |
|---|
| 1603 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL |
|---|
| 1604 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L |
|---|
| 1605 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L |
|---|
| 1606 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L |
|---|
| 1607 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L |
|---|
| 1608 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L |
|---|
| 1609 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L |
|---|
| 1610 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L |
|---|
| 1611 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L |
|---|
| 1612 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L |
|---|
| 1613 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L |
|---|
| 1614 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L |
|---|
| 1615 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L |
|---|
| 1616 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L |
|---|
| 1617 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L |
|---|
| 1618 | //PA_SC_BINNER_EVENT_CNTL_1 |
|---|
| 1619 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 |
|---|
| 1620 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 |
|---|
| 1621 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 |
|---|
| 1622 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 |
|---|
| 1623 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 |
|---|
| 1624 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa |
|---|
| 1625 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc |
|---|
| 1626 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe |
|---|
| 1627 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 |
|---|
| 1628 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 |
|---|
| 1629 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 |
|---|
| 1630 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 |
|---|
| 1631 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 |
|---|
| 1632 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a |
|---|
| 1633 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c |
|---|
| 1634 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e |
|---|
| 1635 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L |
|---|
| 1636 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL |
|---|
| 1637 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L |
|---|
| 1638 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L |
|---|
| 1639 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L |
|---|
| 1640 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L |
|---|
| 1641 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L |
|---|
| 1642 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L |
|---|
| 1643 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L |
|---|
| 1644 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L |
|---|
| 1645 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L |
|---|
| 1646 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L |
|---|
| 1647 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L |
|---|
| 1648 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L |
|---|
| 1649 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L |
|---|
| 1650 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L |
|---|
| 1651 | //PA_SC_BINNER_EVENT_CNTL_2 |
|---|
| 1652 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 |
|---|
| 1653 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 |
|---|
| 1654 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 |
|---|
| 1655 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 |
|---|
| 1656 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 |
|---|
| 1657 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa |
|---|
| 1658 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc |
|---|
| 1659 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe |
|---|
| 1660 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 |
|---|
| 1661 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 |
|---|
| 1662 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 |
|---|
| 1663 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 |
|---|
| 1664 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 |
|---|
| 1665 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a |
|---|
| 1666 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c |
|---|
| 1667 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e |
|---|
| 1668 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L |
|---|
| 1669 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL |
|---|
| 1670 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L |
|---|
| 1671 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L |
|---|
| 1672 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L |
|---|
| 1673 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L |
|---|
| 1674 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L |
|---|
| 1675 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L |
|---|
| 1676 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L |
|---|
| 1677 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L |
|---|
| 1678 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L |
|---|
| 1679 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L |
|---|
| 1680 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L |
|---|
| 1681 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L |
|---|
| 1682 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L |
|---|
| 1683 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L |
|---|
| 1684 | //PA_SC_BINNER_EVENT_CNTL_3 |
|---|
| 1685 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 |
|---|
| 1686 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 |
|---|
| 1687 | #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 |
|---|
| 1688 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 |
|---|
| 1689 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 |
|---|
| 1690 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa |
|---|
| 1691 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc |
|---|
| 1692 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe |
|---|
| 1693 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 |
|---|
| 1694 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 |
|---|
| 1695 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 |
|---|
| 1696 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 |
|---|
| 1697 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 |
|---|
| 1698 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a |
|---|
| 1699 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c |
|---|
| 1700 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e |
|---|
| 1701 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L |
|---|
| 1702 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL |
|---|
| 1703 | #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L |
|---|
| 1704 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L |
|---|
| 1705 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L |
|---|
| 1706 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L |
|---|
| 1707 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L |
|---|
| 1708 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L |
|---|
| 1709 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L |
|---|
| 1710 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L |
|---|
| 1711 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L |
|---|
| 1712 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L |
|---|
| 1713 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L |
|---|
| 1714 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L |
|---|
| 1715 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L |
|---|
| 1716 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L |
|---|
| 1717 | //PA_SC_BINNER_TIMEOUT_COUNTER |
|---|
| 1718 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 |
|---|
| 1719 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL |
|---|
| 1720 | //PA_SC_BINNER_PERF_CNTL_0 |
|---|
| 1721 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 |
|---|
| 1722 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa |
|---|
| 1723 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 |
|---|
| 1724 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 |
|---|
| 1725 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL |
|---|
| 1726 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L |
|---|
| 1727 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L |
|---|
| 1728 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L |
|---|
| 1729 | //PA_SC_BINNER_PERF_CNTL_1 |
|---|
| 1730 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 |
|---|
| 1731 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 |
|---|
| 1732 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa |
|---|
| 1733 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL |
|---|
| 1734 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L |
|---|
| 1735 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L |
|---|
| 1736 | //PA_SC_BINNER_PERF_CNTL_2 |
|---|
| 1737 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 |
|---|
| 1738 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb |
|---|
| 1739 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL |
|---|
| 1740 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L |
|---|
| 1741 | //PA_SC_BINNER_PERF_CNTL_3 |
|---|
| 1742 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 |
|---|
| 1743 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL |
|---|
| 1744 | //PA_SC_FIFO_SIZE |
|---|
| 1745 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 |
|---|
| 1746 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 |
|---|
| 1747 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf |
|---|
| 1748 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 |
|---|
| 1749 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL |
|---|
| 1750 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L |
|---|
| 1751 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L |
|---|
| 1752 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L |
|---|
| 1753 | //PA_SC_IF_FIFO_SIZE |
|---|
| 1754 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 |
|---|
| 1755 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 |
|---|
| 1756 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc |
|---|
| 1757 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 |
|---|
| 1758 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL |
|---|
| 1759 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L |
|---|
| 1760 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L |
|---|
| 1761 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L |
|---|
| 1762 | //PA_SC_PKR_WAVE_TABLE_CNTL |
|---|
| 1763 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 |
|---|
| 1764 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL |
|---|
| 1765 | //PA_UTCL1_CNTL1 |
|---|
| 1766 | #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
|---|
| 1767 | #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 |
|---|
| 1768 | #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
|---|
| 1769 | #define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
|---|
| 1770 | #define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
|---|
| 1771 | #define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
|---|
| 1772 | #define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 |
|---|
| 1773 | #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
|---|
| 1774 | #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
|---|
| 1775 | #define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
|---|
| 1776 | #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
|---|
| 1777 | #define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
|---|
| 1778 | #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 |
|---|
| 1779 | #define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
|---|
| 1780 | #define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
|---|
| 1781 | #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
|---|
| 1782 | #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
|---|
| 1783 | #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
|---|
| 1784 | #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L |
|---|
| 1785 | #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
|---|
| 1786 | #define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
|---|
| 1787 | #define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
|---|
| 1788 | #define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
|---|
| 1789 | #define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L |
|---|
| 1790 | #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
|---|
| 1791 | #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
|---|
| 1792 | #define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
|---|
| 1793 | #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
|---|
| 1794 | #define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
|---|
| 1795 | #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L |
|---|
| 1796 | #define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
|---|
| 1797 | #define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
|---|
| 1798 | #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
|---|
| 1799 | #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
|---|
| 1800 | //PA_UTCL1_CNTL2 |
|---|
| 1801 | #define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 |
|---|
| 1802 | #define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 |
|---|
| 1803 | #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
|---|
| 1804 | #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
|---|
| 1805 | #define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb |
|---|
| 1806 | #define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
|---|
| 1807 | #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd |
|---|
| 1808 | #define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
|---|
| 1809 | #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
|---|
| 1810 | #define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 |
|---|
| 1811 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
|---|
| 1812 | #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
|---|
| 1813 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
|---|
| 1814 | #define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
|---|
| 1815 | #define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 |
|---|
| 1816 | #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
|---|
| 1817 | #define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b |
|---|
| 1818 | #define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL |
|---|
| 1819 | #define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L |
|---|
| 1820 | #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
|---|
| 1821 | #define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
|---|
| 1822 | #define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L |
|---|
| 1823 | #define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
|---|
| 1824 | #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L |
|---|
| 1825 | #define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
|---|
| 1826 | #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
|---|
| 1827 | #define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L |
|---|
| 1828 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
|---|
| 1829 | #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
|---|
| 1830 | #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
|---|
| 1831 | #define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
|---|
| 1832 | #define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L |
|---|
| 1833 | #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
|---|
| 1834 | #define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L |
|---|
| 1835 | //PA_SIDEBAND_REQUEST_DELAYS |
|---|
| 1836 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 |
|---|
| 1837 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 |
|---|
| 1838 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL |
|---|
| 1839 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L |
|---|
| 1840 | //PA_SC_ENHANCE |
|---|
| 1841 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 |
|---|
| 1842 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 |
|---|
| 1843 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 |
|---|
| 1844 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 |
|---|
| 1845 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 |
|---|
| 1846 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 |
|---|
| 1847 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 |
|---|
| 1848 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 |
|---|
| 1849 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 |
|---|
| 1850 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 |
|---|
| 1851 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa |
|---|
| 1852 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb |
|---|
| 1853 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc |
|---|
| 1854 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd |
|---|
| 1855 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe |
|---|
| 1856 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf |
|---|
| 1857 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 |
|---|
| 1858 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 |
|---|
| 1859 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 |
|---|
| 1860 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 |
|---|
| 1861 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 |
|---|
| 1862 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 |
|---|
| 1863 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 |
|---|
| 1864 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 |
|---|
| 1865 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
|---|
| 1866 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 |
|---|
| 1867 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a |
|---|
| 1868 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b |
|---|
| 1869 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c |
|---|
| 1870 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d |
|---|
| 1871 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L |
|---|
| 1872 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L |
|---|
| 1873 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L |
|---|
| 1874 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L |
|---|
| 1875 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L |
|---|
| 1876 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L |
|---|
| 1877 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L |
|---|
| 1878 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L |
|---|
| 1879 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L |
|---|
| 1880 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L |
|---|
| 1881 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L |
|---|
| 1882 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L |
|---|
| 1883 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L |
|---|
| 1884 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L |
|---|
| 1885 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L |
|---|
| 1886 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L |
|---|
| 1887 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L |
|---|
| 1888 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L |
|---|
| 1889 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L |
|---|
| 1890 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L |
|---|
| 1891 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L |
|---|
| 1892 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L |
|---|
| 1893 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L |
|---|
| 1894 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L |
|---|
| 1895 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
|---|
| 1896 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L |
|---|
| 1897 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L |
|---|
| 1898 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L |
|---|
| 1899 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L |
|---|
| 1900 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L |
|---|
| 1901 | //PA_SC_ENHANCE_1 |
|---|
| 1902 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 |
|---|
| 1903 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 |
|---|
| 1904 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 |
|---|
| 1905 | #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 |
|---|
| 1906 | #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 |
|---|
| 1907 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 |
|---|
| 1908 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 |
|---|
| 1909 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 |
|---|
| 1910 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 |
|---|
| 1911 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa |
|---|
| 1912 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb |
|---|
| 1913 | #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc |
|---|
| 1914 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd |
|---|
| 1915 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe |
|---|
| 1916 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf |
|---|
| 1917 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 |
|---|
| 1918 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 |
|---|
| 1919 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 |
|---|
| 1920 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 |
|---|
| 1921 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 |
|---|
| 1922 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 |
|---|
| 1923 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 |
|---|
| 1924 | #define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17 |
|---|
| 1925 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L |
|---|
| 1926 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L |
|---|
| 1927 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L |
|---|
| 1928 | #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L |
|---|
| 1929 | #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L |
|---|
| 1930 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L |
|---|
| 1931 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L |
|---|
| 1932 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L |
|---|
| 1933 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L |
|---|
| 1934 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L |
|---|
| 1935 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L |
|---|
| 1936 | #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L |
|---|
| 1937 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L |
|---|
| 1938 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L |
|---|
| 1939 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L |
|---|
| 1940 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L |
|---|
| 1941 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L |
|---|
| 1942 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L |
|---|
| 1943 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L |
|---|
| 1944 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L |
|---|
| 1945 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L |
|---|
| 1946 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L |
|---|
| 1947 | #define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L |
|---|
| 1948 | //PA_SC_DSM_CNTL |
|---|
| 1949 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 |
|---|
| 1950 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 |
|---|
| 1951 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L |
|---|
| 1952 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L |
|---|
| 1953 | //PA_SC_TILE_STEERING_CREST_OVERRIDE |
|---|
| 1954 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 |
|---|
| 1955 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 |
|---|
| 1956 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 |
|---|
| 1957 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L |
|---|
| 1958 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L |
|---|
| 1959 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L |
|---|
| 1960 | |
|---|
| 1961 | |
|---|
| 1962 | // addressBlock: gc_sqdec |
|---|
| 1963 | //SQ_CONFIG |
|---|
| 1964 | #define SQ_CONFIG__UNUSED__SHIFT 0x0 |
|---|
| 1965 | #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 |
|---|
| 1966 | #define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 |
|---|
| 1967 | #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 |
|---|
| 1968 | #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa |
|---|
| 1969 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb |
|---|
| 1970 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc |
|---|
| 1971 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd |
|---|
| 1972 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe |
|---|
| 1973 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf |
|---|
| 1974 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 |
|---|
| 1975 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 |
|---|
| 1976 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 |
|---|
| 1977 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 |
|---|
| 1978 | #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 |
|---|
| 1979 | #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c |
|---|
| 1980 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d |
|---|
| 1981 | #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e |
|---|
| 1982 | #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f |
|---|
| 1983 | #define SQ_CONFIG__UNUSED_MASK 0x0000007FL |
|---|
| 1984 | #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L |
|---|
| 1985 | #define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L |
|---|
| 1986 | #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L |
|---|
| 1987 | #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L |
|---|
| 1988 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L |
|---|
| 1989 | #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L |
|---|
| 1990 | #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L |
|---|
| 1991 | #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L |
|---|
| 1992 | #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L |
|---|
| 1993 | #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L |
|---|
| 1994 | #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L |
|---|
| 1995 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L |
|---|
| 1996 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L |
|---|
| 1997 | #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L |
|---|
| 1998 | #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L |
|---|
| 1999 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L |
|---|
| 2000 | #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L |
|---|
| 2001 | #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L |
|---|
| 2002 | //SQC_CONFIG |
|---|
| 2003 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 |
|---|
| 2004 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 |
|---|
| 2005 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 |
|---|
| 2006 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 |
|---|
| 2007 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 |
|---|
| 2008 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 |
|---|
| 2009 | #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 |
|---|
| 2010 | #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa |
|---|
| 2011 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb |
|---|
| 2012 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc |
|---|
| 2013 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe |
|---|
| 2014 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf |
|---|
| 2015 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 |
|---|
| 2016 | #define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 |
|---|
| 2017 | #define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a |
|---|
| 2018 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L |
|---|
| 2019 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL |
|---|
| 2020 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L |
|---|
| 2021 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L |
|---|
| 2022 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L |
|---|
| 2023 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L |
|---|
| 2024 | #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L |
|---|
| 2025 | #define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L |
|---|
| 2026 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L |
|---|
| 2027 | #define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L |
|---|
| 2028 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L |
|---|
| 2029 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L |
|---|
| 2030 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L |
|---|
| 2031 | #define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L |
|---|
| 2032 | #define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L |
|---|
| 2033 | //LDS_CONFIG |
|---|
| 2034 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 |
|---|
| 2035 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L |
|---|
| 2036 | //SQ_RANDOM_WAVE_PRI |
|---|
| 2037 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 |
|---|
| 2038 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 |
|---|
| 2039 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa |
|---|
| 2040 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL |
|---|
| 2041 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L |
|---|
| 2042 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L |
|---|
| 2043 | //SQ_REG_CREDITS |
|---|
| 2044 | #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 |
|---|
| 2045 | #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 |
|---|
| 2046 | #define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c |
|---|
| 2047 | #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d |
|---|
| 2048 | #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e |
|---|
| 2049 | #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f |
|---|
| 2050 | #define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL |
|---|
| 2051 | #define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L |
|---|
| 2052 | #define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L |
|---|
| 2053 | #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L |
|---|
| 2054 | #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L |
|---|
| 2055 | #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L |
|---|
| 2056 | //SQ_FIFO_SIZES |
|---|
| 2057 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 |
|---|
| 2058 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 |
|---|
| 2059 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 |
|---|
| 2060 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 |
|---|
| 2061 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL |
|---|
| 2062 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L |
|---|
| 2063 | #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L |
|---|
| 2064 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L |
|---|
| 2065 | //SQ_DSM_CNTL |
|---|
| 2066 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 |
|---|
| 2067 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 |
|---|
| 2068 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 |
|---|
| 2069 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 |
|---|
| 2070 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 |
|---|
| 2071 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 |
|---|
| 2072 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa |
|---|
| 2073 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 |
|---|
| 2074 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 |
|---|
| 2075 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 |
|---|
| 2076 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 |
|---|
| 2077 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 |
|---|
| 2078 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 |
|---|
| 2079 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 |
|---|
| 2080 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 |
|---|
| 2081 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
|---|
| 2082 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L |
|---|
| 2083 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L |
|---|
| 2084 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L |
|---|
| 2085 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L |
|---|
| 2086 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L |
|---|
| 2087 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L |
|---|
| 2088 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L |
|---|
| 2089 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L |
|---|
| 2090 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L |
|---|
| 2091 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L |
|---|
| 2092 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L |
|---|
| 2093 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L |
|---|
| 2094 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L |
|---|
| 2095 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L |
|---|
| 2096 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L |
|---|
| 2097 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
|---|
| 2098 | //SQ_DSM_CNTL2 |
|---|
| 2099 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 2100 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 2101 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 2102 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 2103 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 2104 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 2105 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 2106 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 2107 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe |
|---|
| 2108 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 |
|---|
| 2109 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a |
|---|
| 2110 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 2111 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 2112 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 2113 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 2114 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 2115 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 2116 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 2117 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 2118 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L |
|---|
| 2119 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L |
|---|
| 2120 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L |
|---|
| 2121 | //SQ_RUNTIME_CONFIG |
|---|
| 2122 | #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 |
|---|
| 2123 | #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L |
|---|
| 2124 | //SH_MEM_BASES |
|---|
| 2125 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 |
|---|
| 2126 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 |
|---|
| 2127 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL |
|---|
| 2128 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L |
|---|
| 2129 | //SH_MEM_CONFIG |
|---|
| 2130 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 |
|---|
| 2131 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 |
|---|
| 2132 | #define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc |
|---|
| 2133 | #define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd |
|---|
| 2134 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L |
|---|
| 2135 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L |
|---|
| 2136 | #define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L |
|---|
| 2137 | #define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L |
|---|
| 2138 | //CC_GC_SHADER_RATE_CONFIG |
|---|
| 2139 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
|---|
| 2140 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
|---|
| 2141 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 |
|---|
| 2142 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
|---|
| 2143 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
|---|
| 2144 | #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L |
|---|
| 2145 | //GC_USER_SHADER_RATE_CONFIG |
|---|
| 2146 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
|---|
| 2147 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
|---|
| 2148 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 |
|---|
| 2149 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
|---|
| 2150 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
|---|
| 2151 | #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L |
|---|
| 2152 | //SQ_INTERRUPT_AUTO_MASK |
|---|
| 2153 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 |
|---|
| 2154 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL |
|---|
| 2155 | //SQ_INTERRUPT_MSG_CTRL |
|---|
| 2156 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 |
|---|
| 2157 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L |
|---|
| 2158 | //SQ_UTCL1_CNTL1 |
|---|
| 2159 | #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
|---|
| 2160 | #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
|---|
| 2161 | #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
|---|
| 2162 | #define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
|---|
| 2163 | #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
|---|
| 2164 | #define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
|---|
| 2165 | #define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
|---|
| 2166 | #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
|---|
| 2167 | #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
|---|
| 2168 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
|---|
| 2169 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
|---|
| 2170 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
|---|
| 2171 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 |
|---|
| 2172 | #define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
|---|
| 2173 | #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
|---|
| 2174 | #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
|---|
| 2175 | #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
|---|
| 2176 | #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
|---|
| 2177 | #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
|---|
| 2178 | #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
|---|
| 2179 | #define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
|---|
| 2180 | #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
|---|
| 2181 | #define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
|---|
| 2182 | #define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
|---|
| 2183 | #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
|---|
| 2184 | #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
|---|
| 2185 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
|---|
| 2186 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
|---|
| 2187 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
|---|
| 2188 | #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L |
|---|
| 2189 | #define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
|---|
| 2190 | #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
|---|
| 2191 | #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
|---|
| 2192 | #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
|---|
| 2193 | //SQ_UTCL1_CNTL2 |
|---|
| 2194 | #define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
|---|
| 2195 | #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
|---|
| 2196 | #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
|---|
| 2197 | #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
|---|
| 2198 | #define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
|---|
| 2199 | #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
|---|
| 2200 | #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
|---|
| 2201 | #define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
|---|
| 2202 | #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
|---|
| 2203 | #define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 |
|---|
| 2204 | #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
|---|
| 2205 | #define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c |
|---|
| 2206 | #define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
|---|
| 2207 | #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
|---|
| 2208 | #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
|---|
| 2209 | #define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
|---|
| 2210 | #define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
|---|
| 2211 | #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
|---|
| 2212 | #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
|---|
| 2213 | #define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
|---|
| 2214 | #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
|---|
| 2215 | #define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L |
|---|
| 2216 | #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
|---|
| 2217 | #define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L |
|---|
| 2218 | //SQ_UTCL1_STATUS |
|---|
| 2219 | #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
|---|
| 2220 | #define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
|---|
| 2221 | #define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
|---|
| 2222 | #define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
|---|
| 2223 | #define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 |
|---|
| 2224 | #define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
|---|
| 2225 | #define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
|---|
| 2226 | #define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
|---|
| 2227 | #define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L |
|---|
| 2228 | #define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L |
|---|
| 2229 | //SQ_SHADER_TBA_LO |
|---|
| 2230 | #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 |
|---|
| 2231 | #define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
|---|
| 2232 | //SQ_SHADER_TBA_HI |
|---|
| 2233 | #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 |
|---|
| 2234 | #define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL |
|---|
| 2235 | //SQ_SHADER_TMA_LO |
|---|
| 2236 | #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 |
|---|
| 2237 | #define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
|---|
| 2238 | //SQ_SHADER_TMA_HI |
|---|
| 2239 | #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 |
|---|
| 2240 | #define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL |
|---|
| 2241 | //SQC_DSM_CNTL |
|---|
| 2242 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 2243 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 2244 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 2245 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 2246 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 2247 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 2248 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 2249 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 2250 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 2251 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 2252 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 2253 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 2254 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 2255 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 2256 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 2257 | #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 2258 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 2259 | #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 2260 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 2261 | #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 2262 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 2263 | #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 2264 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 2265 | #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 2266 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 2267 | #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 2268 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 2269 | #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 2270 | //SQC_DSM_CNTLA |
|---|
| 2271 | #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 2272 | #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 2273 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 2274 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 2275 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 2276 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 2277 | #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 2278 | #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 2279 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 2280 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 2281 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 2282 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 2283 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 2284 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 2285 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
|---|
| 2286 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
|---|
| 2287 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 |
|---|
| 2288 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
|---|
| 2289 | #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 2290 | #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 2291 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 2292 | #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 2293 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 2294 | #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 2295 | #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 2296 | #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 2297 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 2298 | #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 2299 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 2300 | #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 2301 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 2302 | #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 2303 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
|---|
| 2304 | #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
|---|
| 2305 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L |
|---|
| 2306 | #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
|---|
| 2307 | //SQC_DSM_CNTLB |
|---|
| 2308 | #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
|---|
| 2309 | #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
|---|
| 2310 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 |
|---|
| 2311 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
|---|
| 2312 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
|---|
| 2313 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
|---|
| 2314 | #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
|---|
| 2315 | #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
|---|
| 2316 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc |
|---|
| 2317 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
|---|
| 2318 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf |
|---|
| 2319 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
|---|
| 2320 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 |
|---|
| 2321 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
|---|
| 2322 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
|---|
| 2323 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
|---|
| 2324 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 |
|---|
| 2325 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
|---|
| 2326 | #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
|---|
| 2327 | #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
|---|
| 2328 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L |
|---|
| 2329 | #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
|---|
| 2330 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
|---|
| 2331 | #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
|---|
| 2332 | #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
|---|
| 2333 | #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
|---|
| 2334 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
|---|
| 2335 | #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
|---|
| 2336 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L |
|---|
| 2337 | #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
|---|
| 2338 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
|---|
| 2339 | #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
|---|
| 2340 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
|---|
| 2341 | #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
|---|
| 2342 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L |
|---|
| 2343 | #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
|---|
| 2344 | //SQC_DSM_CNTL2 |
|---|
| 2345 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 2346 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 2347 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 2348 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 2349 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 2350 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 2351 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 2352 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 2353 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 2354 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 2355 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 2356 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 2357 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 2358 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 2359 | #define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
|---|
| 2360 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 2361 | #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 2362 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 2363 | #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 2364 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 2365 | #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 2366 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 2367 | #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 2368 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 2369 | #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 2370 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 2371 | #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 2372 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 2373 | #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 2374 | #define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
|---|
| 2375 | //SQC_DSM_CNTL2A |
|---|
| 2376 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 2377 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 2378 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 2379 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 2380 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 2381 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 2382 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 2383 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 2384 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 2385 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 2386 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 2387 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 2388 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 2389 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 2390 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
|---|
| 2391 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
|---|
| 2392 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 |
|---|
| 2393 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a |
|---|
| 2394 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 2395 | #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 2396 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 2397 | #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 2398 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 2399 | #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 2400 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 2401 | #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 2402 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 2403 | #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 2404 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 2405 | #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 2406 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 2407 | #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 2408 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
|---|
| 2409 | #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
|---|
| 2410 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L |
|---|
| 2411 | #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L |
|---|
| 2412 | //SQC_DSM_CNTL2B |
|---|
| 2413 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
|---|
| 2414 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 |
|---|
| 2415 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 |
|---|
| 2416 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 |
|---|
| 2417 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
|---|
| 2418 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
|---|
| 2419 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
|---|
| 2420 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
|---|
| 2421 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc |
|---|
| 2422 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe |
|---|
| 2423 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf |
|---|
| 2424 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 |
|---|
| 2425 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 |
|---|
| 2426 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 |
|---|
| 2427 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
|---|
| 2428 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 |
|---|
| 2429 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 |
|---|
| 2430 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a |
|---|
| 2431 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
|---|
| 2432 | #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L |
|---|
| 2433 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L |
|---|
| 2434 | #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L |
|---|
| 2435 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
|---|
| 2436 | #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
|---|
| 2437 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
|---|
| 2438 | #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
|---|
| 2439 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
|---|
| 2440 | #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L |
|---|
| 2441 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L |
|---|
| 2442 | #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L |
|---|
| 2443 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
|---|
| 2444 | #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L |
|---|
| 2445 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
|---|
| 2446 | #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L |
|---|
| 2447 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L |
|---|
| 2448 | #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L |
|---|
| 2449 | //SQC_EDC_FUE_CNTL |
|---|
| 2450 | #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
|---|
| 2451 | #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
|---|
| 2452 | #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
|---|
| 2453 | #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
|---|
| 2454 | //SQC_EDC_CNT2 |
|---|
| 2455 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 |
|---|
| 2456 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 |
|---|
| 2457 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 |
|---|
| 2458 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 |
|---|
| 2459 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 |
|---|
| 2460 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa |
|---|
| 2461 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc |
|---|
| 2462 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe |
|---|
| 2463 | #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 |
|---|
| 2464 | #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12 |
|---|
| 2465 | #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14 |
|---|
| 2466 | #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16 |
|---|
| 2467 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 |
|---|
| 2468 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a |
|---|
| 2469 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c |
|---|
| 2470 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L |
|---|
| 2471 | #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL |
|---|
| 2472 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L |
|---|
| 2473 | #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L |
|---|
| 2474 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L |
|---|
| 2475 | #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L |
|---|
| 2476 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L |
|---|
| 2477 | #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L |
|---|
| 2478 | #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L |
|---|
| 2479 | #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L |
|---|
| 2480 | #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L |
|---|
| 2481 | #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L |
|---|
| 2482 | #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L |
|---|
| 2483 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L |
|---|
| 2484 | #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L |
|---|
| 2485 | //SQC_EDC_CNT3 |
|---|
| 2486 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 |
|---|
| 2487 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 |
|---|
| 2488 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 |
|---|
| 2489 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 |
|---|
| 2490 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 |
|---|
| 2491 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa |
|---|
| 2492 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc |
|---|
| 2493 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe |
|---|
| 2494 | #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 |
|---|
| 2495 | #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12 |
|---|
| 2496 | #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14 |
|---|
| 2497 | #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16 |
|---|
| 2498 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 |
|---|
| 2499 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L |
|---|
| 2500 | #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL |
|---|
| 2501 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L |
|---|
| 2502 | #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L |
|---|
| 2503 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L |
|---|
| 2504 | #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L |
|---|
| 2505 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L |
|---|
| 2506 | #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L |
|---|
| 2507 | #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L |
|---|
| 2508 | #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L |
|---|
| 2509 | #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L |
|---|
| 2510 | #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L |
|---|
| 2511 | #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L |
|---|
| 2512 | //SQ_REG_TIMESTAMP |
|---|
| 2513 | #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 |
|---|
| 2514 | #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL |
|---|
| 2515 | //SQ_CMD_TIMESTAMP |
|---|
| 2516 | #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 |
|---|
| 2517 | #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL |
|---|
| 2518 | //SQ_IND_INDEX |
|---|
| 2519 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 |
|---|
| 2520 | #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 |
|---|
| 2521 | #define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 |
|---|
| 2522 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc |
|---|
| 2523 | #define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd |
|---|
| 2524 | #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe |
|---|
| 2525 | #define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf |
|---|
| 2526 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 |
|---|
| 2527 | #define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL |
|---|
| 2528 | #define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L |
|---|
| 2529 | #define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L |
|---|
| 2530 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L |
|---|
| 2531 | #define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L |
|---|
| 2532 | #define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L |
|---|
| 2533 | #define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L |
|---|
| 2534 | #define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L |
|---|
| 2535 | //SQ_IND_DATA |
|---|
| 2536 | #define SQ_IND_DATA__DATA__SHIFT 0x0 |
|---|
| 2537 | #define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL |
|---|
| 2538 | //SQ_CMD |
|---|
| 2539 | #define SQ_CMD__CMD__SHIFT 0x0 |
|---|
| 2540 | #define SQ_CMD__MODE__SHIFT 0x4 |
|---|
| 2541 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 |
|---|
| 2542 | #define SQ_CMD__DATA__SHIFT 0x8 |
|---|
| 2543 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 |
|---|
| 2544 | #define SQ_CMD__SIMD_ID__SHIFT 0x14 |
|---|
| 2545 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 |
|---|
| 2546 | #define SQ_CMD__VM_ID__SHIFT 0x1c |
|---|
| 2547 | #define SQ_CMD__CMD_MASK 0x00000007L |
|---|
| 2548 | #define SQ_CMD__MODE_MASK 0x00000070L |
|---|
| 2549 | #define SQ_CMD__CHECK_VMID_MASK 0x00000080L |
|---|
| 2550 | #define SQ_CMD__DATA_MASK 0x00000F00L |
|---|
| 2551 | #define SQ_CMD__WAVE_ID_MASK 0x000F0000L |
|---|
| 2552 | #define SQ_CMD__SIMD_ID_MASK 0x00300000L |
|---|
| 2553 | #define SQ_CMD__QUEUE_ID_MASK 0x07000000L |
|---|
| 2554 | #define SQ_CMD__VM_ID_MASK 0xF0000000L |
|---|
| 2555 | //SQ_TIME_HI |
|---|
| 2556 | #define SQ_TIME_HI__TIME__SHIFT 0x0 |
|---|
| 2557 | #define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL |
|---|
| 2558 | //SQ_TIME_LO |
|---|
| 2559 | #define SQ_TIME_LO__TIME__SHIFT 0x0 |
|---|
| 2560 | #define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL |
|---|
| 2561 | //SQ_DS_0 |
|---|
| 2562 | #define SQ_DS_0__OFFSET0__SHIFT 0x0 |
|---|
| 2563 | #define SQ_DS_0__OFFSET1__SHIFT 0x8 |
|---|
| 2564 | #define SQ_DS_0__GDS__SHIFT 0x10 |
|---|
| 2565 | #define SQ_DS_0__OP__SHIFT 0x11 |
|---|
| 2566 | #define SQ_DS_0__ENCODING__SHIFT 0x1a |
|---|
| 2567 | #define SQ_DS_0__OFFSET0_MASK 0x000000FFL |
|---|
| 2568 | #define SQ_DS_0__OFFSET1_MASK 0x0000FF00L |
|---|
| 2569 | #define SQ_DS_0__GDS_MASK 0x00010000L |
|---|
| 2570 | #define SQ_DS_0__OP_MASK 0x01FE0000L |
|---|
| 2571 | #define SQ_DS_0__ENCODING_MASK 0xFC000000L |
|---|
| 2572 | //SQ_DS_1 |
|---|
| 2573 | #define SQ_DS_1__ADDR__SHIFT 0x0 |
|---|
| 2574 | #define SQ_DS_1__DATA0__SHIFT 0x8 |
|---|
| 2575 | #define SQ_DS_1__DATA1__SHIFT 0x10 |
|---|
| 2576 | #define SQ_DS_1__VDST__SHIFT 0x18 |
|---|
| 2577 | #define SQ_DS_1__ADDR_MASK 0x000000FFL |
|---|
| 2578 | #define SQ_DS_1__DATA0_MASK 0x0000FF00L |
|---|
| 2579 | #define SQ_DS_1__DATA1_MASK 0x00FF0000L |
|---|
| 2580 | #define SQ_DS_1__VDST_MASK 0xFF000000L |
|---|
| 2581 | //SQ_EXP_0 |
|---|
| 2582 | #define SQ_EXP_0__EN__SHIFT 0x0 |
|---|
| 2583 | #define SQ_EXP_0__TGT__SHIFT 0x4 |
|---|
| 2584 | #define SQ_EXP_0__COMPR__SHIFT 0xa |
|---|
| 2585 | #define SQ_EXP_0__DONE__SHIFT 0xb |
|---|
| 2586 | #define SQ_EXP_0__VM__SHIFT 0xc |
|---|
| 2587 | #define SQ_EXP_0__ENCODING__SHIFT 0x1a |
|---|
| 2588 | #define SQ_EXP_0__EN_MASK 0x0000000FL |
|---|
| 2589 | #define SQ_EXP_0__TGT_MASK 0x000003F0L |
|---|
| 2590 | #define SQ_EXP_0__COMPR_MASK 0x00000400L |
|---|
| 2591 | #define SQ_EXP_0__DONE_MASK 0x00000800L |
|---|
| 2592 | #define SQ_EXP_0__VM_MASK 0x00001000L |
|---|
| 2593 | #define SQ_EXP_0__ENCODING_MASK 0xFC000000L |
|---|
| 2594 | //SQ_EXP_1 |
|---|
| 2595 | #define SQ_EXP_1__VSRC0__SHIFT 0x0 |
|---|
| 2596 | #define SQ_EXP_1__VSRC1__SHIFT 0x8 |
|---|
| 2597 | #define SQ_EXP_1__VSRC2__SHIFT 0x10 |
|---|
| 2598 | #define SQ_EXP_1__VSRC3__SHIFT 0x18 |
|---|
| 2599 | #define SQ_EXP_1__VSRC0_MASK 0x000000FFL |
|---|
| 2600 | #define SQ_EXP_1__VSRC1_MASK 0x0000FF00L |
|---|
| 2601 | #define SQ_EXP_1__VSRC2_MASK 0x00FF0000L |
|---|
| 2602 | #define SQ_EXP_1__VSRC3_MASK 0xFF000000L |
|---|
| 2603 | //SQ_FLAT_0 |
|---|
| 2604 | #define SQ_FLAT_0__OFFSET__SHIFT 0x0 |
|---|
| 2605 | #define SQ_FLAT_0__LDS__SHIFT 0xd |
|---|
| 2606 | #define SQ_FLAT_0__SEG__SHIFT 0xe |
|---|
| 2607 | #define SQ_FLAT_0__GLC__SHIFT 0x10 |
|---|
| 2608 | #define SQ_FLAT_0__SLC__SHIFT 0x11 |
|---|
| 2609 | #define SQ_FLAT_0__OP__SHIFT 0x12 |
|---|
| 2610 | #define SQ_FLAT_0__ENCODING__SHIFT 0x1a |
|---|
| 2611 | #define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL |
|---|
| 2612 | #define SQ_FLAT_0__LDS_MASK 0x00002000L |
|---|
| 2613 | #define SQ_FLAT_0__SEG_MASK 0x0000C000L |
|---|
| 2614 | #define SQ_FLAT_0__GLC_MASK 0x00010000L |
|---|
| 2615 | #define SQ_FLAT_0__SLC_MASK 0x00020000L |
|---|
| 2616 | #define SQ_FLAT_0__OP_MASK 0x01FC0000L |
|---|
| 2617 | #define SQ_FLAT_0__ENCODING_MASK 0xFC000000L |
|---|
| 2618 | //SQ_FLAT_1 |
|---|
| 2619 | #define SQ_FLAT_1__ADDR__SHIFT 0x0 |
|---|
| 2620 | #define SQ_FLAT_1__DATA__SHIFT 0x8 |
|---|
| 2621 | #define SQ_FLAT_1__SADDR__SHIFT 0x10 |
|---|
| 2622 | #define SQ_FLAT_1__NV__SHIFT 0x17 |
|---|
| 2623 | #define SQ_FLAT_1__VDST__SHIFT 0x18 |
|---|
| 2624 | #define SQ_FLAT_1__ADDR_MASK 0x000000FFL |
|---|
| 2625 | #define SQ_FLAT_1__DATA_MASK 0x0000FF00L |
|---|
| 2626 | #define SQ_FLAT_1__SADDR_MASK 0x007F0000L |
|---|
| 2627 | #define SQ_FLAT_1__NV_MASK 0x00800000L |
|---|
| 2628 | #define SQ_FLAT_1__VDST_MASK 0xFF000000L |
|---|
| 2629 | //SQ_GLBL_0 |
|---|
| 2630 | #define SQ_GLBL_0__OFFSET__SHIFT 0x0 |
|---|
| 2631 | #define SQ_GLBL_0__LDS__SHIFT 0xd |
|---|
| 2632 | #define SQ_GLBL_0__SEG__SHIFT 0xe |
|---|
| 2633 | #define SQ_GLBL_0__GLC__SHIFT 0x10 |
|---|
| 2634 | #define SQ_GLBL_0__SLC__SHIFT 0x11 |
|---|
| 2635 | #define SQ_GLBL_0__OP__SHIFT 0x12 |
|---|
| 2636 | #define SQ_GLBL_0__ENCODING__SHIFT 0x1a |
|---|
| 2637 | #define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL |
|---|
| 2638 | #define SQ_GLBL_0__LDS_MASK 0x00002000L |
|---|
| 2639 | #define SQ_GLBL_0__SEG_MASK 0x0000C000L |
|---|
| 2640 | #define SQ_GLBL_0__GLC_MASK 0x00010000L |
|---|
| 2641 | #define SQ_GLBL_0__SLC_MASK 0x00020000L |
|---|
| 2642 | #define SQ_GLBL_0__OP_MASK 0x01FC0000L |
|---|
| 2643 | #define SQ_GLBL_0__ENCODING_MASK 0xFC000000L |
|---|
| 2644 | //SQ_GLBL_1 |
|---|
| 2645 | #define SQ_GLBL_1__ADDR__SHIFT 0x0 |
|---|
| 2646 | #define SQ_GLBL_1__DATA__SHIFT 0x8 |
|---|
| 2647 | #define SQ_GLBL_1__SADDR__SHIFT 0x10 |
|---|
| 2648 | #define SQ_GLBL_1__NV__SHIFT 0x17 |
|---|
| 2649 | #define SQ_GLBL_1__VDST__SHIFT 0x18 |
|---|
| 2650 | #define SQ_GLBL_1__ADDR_MASK 0x000000FFL |
|---|
| 2651 | #define SQ_GLBL_1__DATA_MASK 0x0000FF00L |
|---|
| 2652 | #define SQ_GLBL_1__SADDR_MASK 0x007F0000L |
|---|
| 2653 | #define SQ_GLBL_1__NV_MASK 0x00800000L |
|---|
| 2654 | #define SQ_GLBL_1__VDST_MASK 0xFF000000L |
|---|
| 2655 | //SQ_INST |
|---|
| 2656 | #define SQ_INST__ENCODING__SHIFT 0x0 |
|---|
| 2657 | #define SQ_INST__ENCODING_MASK 0xFFFFFFFFL |
|---|
| 2658 | //SQ_MIMG_0 |
|---|
| 2659 | #define SQ_MIMG_0__OPM__SHIFT 0x0 |
|---|
| 2660 | #define SQ_MIMG_0__DMASK__SHIFT 0x8 |
|---|
| 2661 | #define SQ_MIMG_0__UNORM__SHIFT 0xc |
|---|
| 2662 | #define SQ_MIMG_0__GLC__SHIFT 0xd |
|---|
| 2663 | #define SQ_MIMG_0__DA__SHIFT 0xe |
|---|
| 2664 | #define SQ_MIMG_0__A16__SHIFT 0xf |
|---|
| 2665 | #define SQ_MIMG_0__TFE__SHIFT 0x10 |
|---|
| 2666 | #define SQ_MIMG_0__LWE__SHIFT 0x11 |
|---|
| 2667 | #define SQ_MIMG_0__OP__SHIFT 0x12 |
|---|
| 2668 | #define SQ_MIMG_0__SLC__SHIFT 0x19 |
|---|
| 2669 | #define SQ_MIMG_0__ENCODING__SHIFT 0x1a |
|---|
| 2670 | #define SQ_MIMG_0__OPM_MASK 0x00000001L |
|---|
| 2671 | #define SQ_MIMG_0__DMASK_MASK 0x00000F00L |
|---|
| 2672 | #define SQ_MIMG_0__UNORM_MASK 0x00001000L |
|---|
| 2673 | #define SQ_MIMG_0__GLC_MASK 0x00002000L |
|---|
| 2674 | #define SQ_MIMG_0__DA_MASK 0x00004000L |
|---|
| 2675 | #define SQ_MIMG_0__A16_MASK 0x00008000L |
|---|
| 2676 | #define SQ_MIMG_0__TFE_MASK 0x00010000L |
|---|
| 2677 | #define SQ_MIMG_0__LWE_MASK 0x00020000L |
|---|
| 2678 | #define SQ_MIMG_0__OP_MASK 0x01FC0000L |
|---|
| 2679 | #define SQ_MIMG_0__SLC_MASK 0x02000000L |
|---|
| 2680 | #define SQ_MIMG_0__ENCODING_MASK 0xFC000000L |
|---|
| 2681 | //SQ_MIMG_1 |
|---|
| 2682 | #define SQ_MIMG_1__VADDR__SHIFT 0x0 |
|---|
| 2683 | #define SQ_MIMG_1__VDATA__SHIFT 0x8 |
|---|
| 2684 | #define SQ_MIMG_1__SRSRC__SHIFT 0x10 |
|---|
| 2685 | #define SQ_MIMG_1__SSAMP__SHIFT 0x15 |
|---|
| 2686 | #define SQ_MIMG_1__D16__SHIFT 0x1f |
|---|
| 2687 | #define SQ_MIMG_1__VADDR_MASK 0x000000FFL |
|---|
| 2688 | #define SQ_MIMG_1__VDATA_MASK 0x0000FF00L |
|---|
| 2689 | #define SQ_MIMG_1__SRSRC_MASK 0x001F0000L |
|---|
| 2690 | #define SQ_MIMG_1__SSAMP_MASK 0x03E00000L |
|---|
| 2691 | #define SQ_MIMG_1__D16_MASK 0x80000000L |
|---|
| 2692 | //SQ_MTBUF_0 |
|---|
| 2693 | #define SQ_MTBUF_0__OFFSET__SHIFT 0x0 |
|---|
| 2694 | #define SQ_MTBUF_0__OFFEN__SHIFT 0xc |
|---|
| 2695 | #define SQ_MTBUF_0__IDXEN__SHIFT 0xd |
|---|
| 2696 | #define SQ_MTBUF_0__GLC__SHIFT 0xe |
|---|
| 2697 | #define SQ_MTBUF_0__OP__SHIFT 0xf |
|---|
| 2698 | #define SQ_MTBUF_0__DFMT__SHIFT 0x13 |
|---|
| 2699 | #define SQ_MTBUF_0__NFMT__SHIFT 0x17 |
|---|
| 2700 | #define SQ_MTBUF_0__ENCODING__SHIFT 0x1a |
|---|
| 2701 | #define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL |
|---|
| 2702 | #define SQ_MTBUF_0__OFFEN_MASK 0x00001000L |
|---|
| 2703 | #define SQ_MTBUF_0__IDXEN_MASK 0x00002000L |
|---|
| 2704 | #define SQ_MTBUF_0__GLC_MASK 0x00004000L |
|---|
| 2705 | #define SQ_MTBUF_0__OP_MASK 0x00078000L |
|---|
| 2706 | #define SQ_MTBUF_0__DFMT_MASK 0x00780000L |
|---|
| 2707 | #define SQ_MTBUF_0__NFMT_MASK 0x03800000L |
|---|
| 2708 | #define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L |
|---|
| 2709 | //SQ_MTBUF_1 |
|---|
| 2710 | #define SQ_MTBUF_1__VADDR__SHIFT 0x0 |
|---|
| 2711 | #define SQ_MTBUF_1__VDATA__SHIFT 0x8 |
|---|
| 2712 | #define SQ_MTBUF_1__SRSRC__SHIFT 0x10 |
|---|
| 2713 | #define SQ_MTBUF_1__SLC__SHIFT 0x16 |
|---|
| 2714 | #define SQ_MTBUF_1__TFE__SHIFT 0x17 |
|---|
| 2715 | #define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 |
|---|
| 2716 | #define SQ_MTBUF_1__VADDR_MASK 0x000000FFL |
|---|
| 2717 | #define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L |
|---|
| 2718 | #define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L |
|---|
| 2719 | #define SQ_MTBUF_1__SLC_MASK 0x00400000L |
|---|
| 2720 | #define SQ_MTBUF_1__TFE_MASK 0x00800000L |
|---|
| 2721 | #define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L |
|---|
| 2722 | //SQ_MUBUF_0 |
|---|
| 2723 | #define SQ_MUBUF_0__OFFSET__SHIFT 0x0 |
|---|
| 2724 | #define SQ_MUBUF_0__OFFEN__SHIFT 0xc |
|---|
| 2725 | #define SQ_MUBUF_0__IDXEN__SHIFT 0xd |
|---|
| 2726 | #define SQ_MUBUF_0__GLC__SHIFT 0xe |
|---|
| 2727 | #define SQ_MUBUF_0__LDS__SHIFT 0x10 |
|---|
| 2728 | #define SQ_MUBUF_0__SLC__SHIFT 0x11 |
|---|
| 2729 | #define SQ_MUBUF_0__OP__SHIFT 0x12 |
|---|
| 2730 | #define SQ_MUBUF_0__ENCODING__SHIFT 0x1a |
|---|
| 2731 | #define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL |
|---|
| 2732 | #define SQ_MUBUF_0__OFFEN_MASK 0x00001000L |
|---|
| 2733 | #define SQ_MUBUF_0__IDXEN_MASK 0x00002000L |
|---|
| 2734 | #define SQ_MUBUF_0__GLC_MASK 0x00004000L |
|---|
| 2735 | #define SQ_MUBUF_0__LDS_MASK 0x00010000L |
|---|
| 2736 | #define SQ_MUBUF_0__SLC_MASK 0x00020000L |
|---|
| 2737 | #define SQ_MUBUF_0__OP_MASK 0x01FC0000L |
|---|
| 2738 | #define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L |
|---|
| 2739 | //SQ_MUBUF_1 |
|---|
| 2740 | #define SQ_MUBUF_1__VADDR__SHIFT 0x0 |
|---|
| 2741 | #define SQ_MUBUF_1__VDATA__SHIFT 0x8 |
|---|
| 2742 | #define SQ_MUBUF_1__SRSRC__SHIFT 0x10 |
|---|
| 2743 | #define SQ_MUBUF_1__TFE__SHIFT 0x17 |
|---|
| 2744 | #define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 |
|---|
| 2745 | #define SQ_MUBUF_1__VADDR_MASK 0x000000FFL |
|---|
| 2746 | #define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L |
|---|
| 2747 | #define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L |
|---|
| 2748 | #define SQ_MUBUF_1__TFE_MASK 0x00800000L |
|---|
| 2749 | #define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L |
|---|
| 2750 | //SQ_SCRATCH_0 |
|---|
| 2751 | #define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 |
|---|
| 2752 | #define SQ_SCRATCH_0__LDS__SHIFT 0xd |
|---|
| 2753 | #define SQ_SCRATCH_0__SEG__SHIFT 0xe |
|---|
| 2754 | #define SQ_SCRATCH_0__GLC__SHIFT 0x10 |
|---|
| 2755 | #define SQ_SCRATCH_0__SLC__SHIFT 0x11 |
|---|
| 2756 | #define SQ_SCRATCH_0__OP__SHIFT 0x12 |
|---|
| 2757 | #define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a |
|---|
| 2758 | #define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL |
|---|
| 2759 | #define SQ_SCRATCH_0__LDS_MASK 0x00002000L |
|---|
| 2760 | #define SQ_SCRATCH_0__SEG_MASK 0x0000C000L |
|---|
| 2761 | #define SQ_SCRATCH_0__GLC_MASK 0x00010000L |
|---|
| 2762 | #define SQ_SCRATCH_0__SLC_MASK 0x00020000L |
|---|
| 2763 | #define SQ_SCRATCH_0__OP_MASK 0x01FC0000L |
|---|
| 2764 | #define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L |
|---|
| 2765 | //SQ_SCRATCH_1 |
|---|
| 2766 | #define SQ_SCRATCH_1__ADDR__SHIFT 0x0 |
|---|
| 2767 | #define SQ_SCRATCH_1__DATA__SHIFT 0x8 |
|---|
| 2768 | #define SQ_SCRATCH_1__SADDR__SHIFT 0x10 |
|---|
| 2769 | #define SQ_SCRATCH_1__NV__SHIFT 0x17 |
|---|
| 2770 | #define SQ_SCRATCH_1__VDST__SHIFT 0x18 |
|---|
| 2771 | #define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL |
|---|
| 2772 | #define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L |
|---|
| 2773 | #define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L |
|---|
| 2774 | #define SQ_SCRATCH_1__NV_MASK 0x00800000L |
|---|
| 2775 | #define SQ_SCRATCH_1__VDST_MASK 0xFF000000L |
|---|
| 2776 | //SQ_SMEM_0 |
|---|
| 2777 | #define SQ_SMEM_0__SBASE__SHIFT 0x0 |
|---|
| 2778 | #define SQ_SMEM_0__SDATA__SHIFT 0x6 |
|---|
| 2779 | #define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe |
|---|
| 2780 | #define SQ_SMEM_0__NV__SHIFT 0xf |
|---|
| 2781 | #define SQ_SMEM_0__GLC__SHIFT 0x10 |
|---|
| 2782 | #define SQ_SMEM_0__IMM__SHIFT 0x11 |
|---|
| 2783 | #define SQ_SMEM_0__OP__SHIFT 0x12 |
|---|
| 2784 | #define SQ_SMEM_0__ENCODING__SHIFT 0x1a |
|---|
| 2785 | #define SQ_SMEM_0__SBASE_MASK 0x0000003FL |
|---|
| 2786 | #define SQ_SMEM_0__SDATA_MASK 0x00001FC0L |
|---|
| 2787 | #define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L |
|---|
| 2788 | #define SQ_SMEM_0__NV_MASK 0x00008000L |
|---|
| 2789 | #define SQ_SMEM_0__GLC_MASK 0x00010000L |
|---|
| 2790 | #define SQ_SMEM_0__IMM_MASK 0x00020000L |
|---|
| 2791 | #define SQ_SMEM_0__OP_MASK 0x03FC0000L |
|---|
| 2792 | #define SQ_SMEM_0__ENCODING_MASK 0xFC000000L |
|---|
| 2793 | //SQ_SMEM_1 |
|---|
| 2794 | #define SQ_SMEM_1__OFFSET__SHIFT 0x0 |
|---|
| 2795 | #define SQ_SMEM_1__SOFFSET__SHIFT 0x19 |
|---|
| 2796 | #define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL |
|---|
| 2797 | #define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L |
|---|
| 2798 | //SQ_SOP1 |
|---|
| 2799 | #define SQ_SOP1__SSRC0__SHIFT 0x0 |
|---|
| 2800 | #define SQ_SOP1__OP__SHIFT 0x8 |
|---|
| 2801 | #define SQ_SOP1__SDST__SHIFT 0x10 |
|---|
| 2802 | #define SQ_SOP1__ENCODING__SHIFT 0x17 |
|---|
| 2803 | #define SQ_SOP1__SSRC0_MASK 0x000000FFL |
|---|
| 2804 | #define SQ_SOP1__OP_MASK 0x0000FF00L |
|---|
| 2805 | #define SQ_SOP1__SDST_MASK 0x007F0000L |
|---|
| 2806 | #define SQ_SOP1__ENCODING_MASK 0xFF800000L |
|---|
| 2807 | //SQ_SOP2 |
|---|
| 2808 | #define SQ_SOP2__SSRC0__SHIFT 0x0 |
|---|
| 2809 | #define SQ_SOP2__SSRC1__SHIFT 0x8 |
|---|
| 2810 | #define SQ_SOP2__SDST__SHIFT 0x10 |
|---|
| 2811 | #define SQ_SOP2__OP__SHIFT 0x17 |
|---|
| 2812 | #define SQ_SOP2__ENCODING__SHIFT 0x1e |
|---|
| 2813 | #define SQ_SOP2__SSRC0_MASK 0x000000FFL |
|---|
| 2814 | #define SQ_SOP2__SSRC1_MASK 0x0000FF00L |
|---|
| 2815 | #define SQ_SOP2__SDST_MASK 0x007F0000L |
|---|
| 2816 | #define SQ_SOP2__OP_MASK 0x3F800000L |
|---|
| 2817 | #define SQ_SOP2__ENCODING_MASK 0xC0000000L |
|---|
| 2818 | //SQ_SOPC |
|---|
| 2819 | #define SQ_SOPC__SSRC0__SHIFT 0x0 |
|---|
| 2820 | #define SQ_SOPC__SSRC1__SHIFT 0x8 |
|---|
| 2821 | #define SQ_SOPC__OP__SHIFT 0x10 |
|---|
| 2822 | #define SQ_SOPC__ENCODING__SHIFT 0x17 |
|---|
| 2823 | #define SQ_SOPC__SSRC0_MASK 0x000000FFL |
|---|
| 2824 | #define SQ_SOPC__SSRC1_MASK 0x0000FF00L |
|---|
| 2825 | #define SQ_SOPC__OP_MASK 0x007F0000L |
|---|
| 2826 | #define SQ_SOPC__ENCODING_MASK 0xFF800000L |
|---|
| 2827 | //SQ_SOPK |
|---|
| 2828 | #define SQ_SOPK__SIMM16__SHIFT 0x0 |
|---|
| 2829 | #define SQ_SOPK__SDST__SHIFT 0x10 |
|---|
| 2830 | #define SQ_SOPK__OP__SHIFT 0x17 |
|---|
| 2831 | #define SQ_SOPK__ENCODING__SHIFT 0x1c |
|---|
| 2832 | #define SQ_SOPK__SIMM16_MASK 0x0000FFFFL |
|---|
| 2833 | #define SQ_SOPK__SDST_MASK 0x007F0000L |
|---|
| 2834 | #define SQ_SOPK__OP_MASK 0x0F800000L |
|---|
| 2835 | #define SQ_SOPK__ENCODING_MASK 0xF0000000L |
|---|
| 2836 | //SQ_SOPP |
|---|
| 2837 | #define SQ_SOPP__SIMM16__SHIFT 0x0 |
|---|
| 2838 | #define SQ_SOPP__OP__SHIFT 0x10 |
|---|
| 2839 | #define SQ_SOPP__ENCODING__SHIFT 0x17 |
|---|
| 2840 | #define SQ_SOPP__SIMM16_MASK 0x0000FFFFL |
|---|
| 2841 | #define SQ_SOPP__OP_MASK 0x007F0000L |
|---|
| 2842 | #define SQ_SOPP__ENCODING_MASK 0xFF800000L |
|---|
| 2843 | //SQ_VINTRP |
|---|
| 2844 | #define SQ_VINTRP__VSRC__SHIFT 0x0 |
|---|
| 2845 | #define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 |
|---|
| 2846 | #define SQ_VINTRP__ATTR__SHIFT 0xa |
|---|
| 2847 | #define SQ_VINTRP__OP__SHIFT 0x10 |
|---|
| 2848 | #define SQ_VINTRP__VDST__SHIFT 0x12 |
|---|
| 2849 | #define SQ_VINTRP__ENCODING__SHIFT 0x1a |
|---|
| 2850 | #define SQ_VINTRP__VSRC_MASK 0x000000FFL |
|---|
| 2851 | #define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L |
|---|
| 2852 | #define SQ_VINTRP__ATTR_MASK 0x0000FC00L |
|---|
| 2853 | #define SQ_VINTRP__OP_MASK 0x00030000L |
|---|
| 2854 | #define SQ_VINTRP__VDST_MASK 0x03FC0000L |
|---|
| 2855 | #define SQ_VINTRP__ENCODING_MASK 0xFC000000L |
|---|
| 2856 | //SQ_VOP1 |
|---|
| 2857 | #define SQ_VOP1__SRC0__SHIFT 0x0 |
|---|
| 2858 | #define SQ_VOP1__OP__SHIFT 0x9 |
|---|
| 2859 | #define SQ_VOP1__VDST__SHIFT 0x11 |
|---|
| 2860 | #define SQ_VOP1__ENCODING__SHIFT 0x19 |
|---|
| 2861 | #define SQ_VOP1__SRC0_MASK 0x000001FFL |
|---|
| 2862 | #define SQ_VOP1__OP_MASK 0x0001FE00L |
|---|
| 2863 | #define SQ_VOP1__VDST_MASK 0x01FE0000L |
|---|
| 2864 | #define SQ_VOP1__ENCODING_MASK 0xFE000000L |
|---|
| 2865 | //SQ_VOP2 |
|---|
| 2866 | #define SQ_VOP2__SRC0__SHIFT 0x0 |
|---|
| 2867 | #define SQ_VOP2__VSRC1__SHIFT 0x9 |
|---|
| 2868 | #define SQ_VOP2__VDST__SHIFT 0x11 |
|---|
| 2869 | #define SQ_VOP2__OP__SHIFT 0x19 |
|---|
| 2870 | #define SQ_VOP2__ENCODING__SHIFT 0x1f |
|---|
| 2871 | #define SQ_VOP2__SRC0_MASK 0x000001FFL |
|---|
| 2872 | #define SQ_VOP2__VSRC1_MASK 0x0001FE00L |
|---|
| 2873 | #define SQ_VOP2__VDST_MASK 0x01FE0000L |
|---|
| 2874 | #define SQ_VOP2__OP_MASK 0x7E000000L |
|---|
| 2875 | #define SQ_VOP2__ENCODING_MASK 0x80000000L |
|---|
| 2876 | //SQ_VOP3P_0 |
|---|
| 2877 | #define SQ_VOP3P_0__VDST__SHIFT 0x0 |
|---|
| 2878 | #define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 |
|---|
| 2879 | #define SQ_VOP3P_0__OP_SEL__SHIFT 0xb |
|---|
| 2880 | #define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe |
|---|
| 2881 | #define SQ_VOP3P_0__CLAMP__SHIFT 0xf |
|---|
| 2882 | #define SQ_VOP3P_0__OP__SHIFT 0x10 |
|---|
| 2883 | #define SQ_VOP3P_0__ENCODING__SHIFT 0x17 |
|---|
| 2884 | #define SQ_VOP3P_0__VDST_MASK 0x000000FFL |
|---|
| 2885 | #define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L |
|---|
| 2886 | #define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L |
|---|
| 2887 | #define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L |
|---|
| 2888 | #define SQ_VOP3P_0__CLAMP_MASK 0x00008000L |
|---|
| 2889 | #define SQ_VOP3P_0__OP_MASK 0x007F0000L |
|---|
| 2890 | #define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L |
|---|
| 2891 | //SQ_VOP3P_1 |
|---|
| 2892 | #define SQ_VOP3P_1__SRC0__SHIFT 0x0 |
|---|
| 2893 | #define SQ_VOP3P_1__SRC1__SHIFT 0x9 |
|---|
| 2894 | #define SQ_VOP3P_1__SRC2__SHIFT 0x12 |
|---|
| 2895 | #define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b |
|---|
| 2896 | #define SQ_VOP3P_1__NEG__SHIFT 0x1d |
|---|
| 2897 | #define SQ_VOP3P_1__SRC0_MASK 0x000001FFL |
|---|
| 2898 | #define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L |
|---|
| 2899 | #define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L |
|---|
| 2900 | #define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L |
|---|
| 2901 | #define SQ_VOP3P_1__NEG_MASK 0xE0000000L |
|---|
| 2902 | //SQ_VOP3_0 |
|---|
| 2903 | #define SQ_VOP3_0__VDST__SHIFT 0x0 |
|---|
| 2904 | #define SQ_VOP3_0__ABS__SHIFT 0x8 |
|---|
| 2905 | #define SQ_VOP3_0__OP_SEL__SHIFT 0xb |
|---|
| 2906 | #define SQ_VOP3_0__CLAMP__SHIFT 0xf |
|---|
| 2907 | #define SQ_VOP3_0__OP__SHIFT 0x10 |
|---|
| 2908 | #define SQ_VOP3_0__ENCODING__SHIFT 0x1a |
|---|
| 2909 | #define SQ_VOP3_0__VDST_MASK 0x000000FFL |
|---|
| 2910 | #define SQ_VOP3_0__ABS_MASK 0x00000700L |
|---|
| 2911 | #define SQ_VOP3_0__OP_SEL_MASK 0x00007800L |
|---|
| 2912 | #define SQ_VOP3_0__CLAMP_MASK 0x00008000L |
|---|
| 2913 | #define SQ_VOP3_0__OP_MASK 0x03FF0000L |
|---|
| 2914 | #define SQ_VOP3_0__ENCODING_MASK 0xFC000000L |
|---|
| 2915 | //SQ_VOP3_0_SDST_ENC |
|---|
| 2916 | #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 |
|---|
| 2917 | #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 |
|---|
| 2918 | #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf |
|---|
| 2919 | #define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 |
|---|
| 2920 | #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a |
|---|
| 2921 | #define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL |
|---|
| 2922 | #define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L |
|---|
| 2923 | #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L |
|---|
| 2924 | #define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L |
|---|
| 2925 | #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L |
|---|
| 2926 | //SQ_VOP3_1 |
|---|
| 2927 | #define SQ_VOP3_1__SRC0__SHIFT 0x0 |
|---|
| 2928 | #define SQ_VOP3_1__SRC1__SHIFT 0x9 |
|---|
| 2929 | #define SQ_VOP3_1__SRC2__SHIFT 0x12 |
|---|
| 2930 | #define SQ_VOP3_1__OMOD__SHIFT 0x1b |
|---|
| 2931 | #define SQ_VOP3_1__NEG__SHIFT 0x1d |
|---|
| 2932 | #define SQ_VOP3_1__SRC0_MASK 0x000001FFL |
|---|
| 2933 | #define SQ_VOP3_1__SRC1_MASK 0x0003FE00L |
|---|
| 2934 | #define SQ_VOP3_1__SRC2_MASK 0x07FC0000L |
|---|
| 2935 | #define SQ_VOP3_1__OMOD_MASK 0x18000000L |
|---|
| 2936 | #define SQ_VOP3_1__NEG_MASK 0xE0000000L |
|---|
| 2937 | //SQ_VOPC |
|---|
| 2938 | #define SQ_VOPC__SRC0__SHIFT 0x0 |
|---|
| 2939 | #define SQ_VOPC__VSRC1__SHIFT 0x9 |
|---|
| 2940 | #define SQ_VOPC__OP__SHIFT 0x11 |
|---|
| 2941 | #define SQ_VOPC__ENCODING__SHIFT 0x19 |
|---|
| 2942 | #define SQ_VOPC__SRC0_MASK 0x000001FFL |
|---|
| 2943 | #define SQ_VOPC__VSRC1_MASK 0x0001FE00L |
|---|
| 2944 | #define SQ_VOPC__OP_MASK 0x01FE0000L |
|---|
| 2945 | #define SQ_VOPC__ENCODING_MASK 0xFE000000L |
|---|
| 2946 | //SQ_VOP_DPP |
|---|
| 2947 | #define SQ_VOP_DPP__SRC0__SHIFT 0x0 |
|---|
| 2948 | #define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 |
|---|
| 2949 | #define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 |
|---|
| 2950 | #define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 |
|---|
| 2951 | #define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 |
|---|
| 2952 | #define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 |
|---|
| 2953 | #define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 |
|---|
| 2954 | #define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 |
|---|
| 2955 | #define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c |
|---|
| 2956 | #define SQ_VOP_DPP__SRC0_MASK 0x000000FFL |
|---|
| 2957 | #define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L |
|---|
| 2958 | #define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L |
|---|
| 2959 | #define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L |
|---|
| 2960 | #define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L |
|---|
| 2961 | #define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L |
|---|
| 2962 | #define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L |
|---|
| 2963 | #define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L |
|---|
| 2964 | #define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L |
|---|
| 2965 | //SQ_VOP_SDWA |
|---|
| 2966 | #define SQ_VOP_SDWA__SRC0__SHIFT 0x0 |
|---|
| 2967 | #define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 |
|---|
| 2968 | #define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb |
|---|
| 2969 | #define SQ_VOP_SDWA__CLAMP__SHIFT 0xd |
|---|
| 2970 | #define SQ_VOP_SDWA__OMOD__SHIFT 0xe |
|---|
| 2971 | #define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 |
|---|
| 2972 | #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 |
|---|
| 2973 | #define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 |
|---|
| 2974 | #define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 |
|---|
| 2975 | #define SQ_VOP_SDWA__S0__SHIFT 0x17 |
|---|
| 2976 | #define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 |
|---|
| 2977 | #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b |
|---|
| 2978 | #define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c |
|---|
| 2979 | #define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d |
|---|
| 2980 | #define SQ_VOP_SDWA__S1__SHIFT 0x1f |
|---|
| 2981 | #define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL |
|---|
| 2982 | #define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L |
|---|
| 2983 | #define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L |
|---|
| 2984 | #define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L |
|---|
| 2985 | #define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L |
|---|
| 2986 | #define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L |
|---|
| 2987 | #define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L |
|---|
| 2988 | #define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L |
|---|
| 2989 | #define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L |
|---|
| 2990 | #define SQ_VOP_SDWA__S0_MASK 0x00800000L |
|---|
| 2991 | #define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L |
|---|
| 2992 | #define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L |
|---|
| 2993 | #define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L |
|---|
| 2994 | #define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L |
|---|
| 2995 | #define SQ_VOP_SDWA__S1_MASK 0x80000000L |
|---|
| 2996 | //SQ_VOP_SDWA_SDST_ENC |
|---|
| 2997 | #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 |
|---|
| 2998 | #define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 |
|---|
| 2999 | #define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf |
|---|
| 3000 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 |
|---|
| 3001 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 |
|---|
| 3002 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 |
|---|
| 3003 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 |
|---|
| 3004 | #define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 |
|---|
| 3005 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 |
|---|
| 3006 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b |
|---|
| 3007 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c |
|---|
| 3008 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d |
|---|
| 3009 | #define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f |
|---|
| 3010 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL |
|---|
| 3011 | #define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L |
|---|
| 3012 | #define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L |
|---|
| 3013 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L |
|---|
| 3014 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L |
|---|
| 3015 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L |
|---|
| 3016 | #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L |
|---|
| 3017 | #define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L |
|---|
| 3018 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L |
|---|
| 3019 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L |
|---|
| 3020 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L |
|---|
| 3021 | #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L |
|---|
| 3022 | #define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L |
|---|
| 3023 | //SQ_LB_CTR_CTRL |
|---|
| 3024 | #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 |
|---|
| 3025 | #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
|---|
| 3026 | #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
|---|
| 3027 | #define SQ_LB_CTR_CTRL__START_MASK 0x00000001L |
|---|
| 3028 | #define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
|---|
| 3029 | #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
|---|
| 3030 | //SQ_LB_DATA0 |
|---|
| 3031 | #define SQ_LB_DATA0__DATA__SHIFT 0x0 |
|---|
| 3032 | #define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
|---|
| 3033 | //SQ_LB_DATA1 |
|---|
| 3034 | #define SQ_LB_DATA1__DATA__SHIFT 0x0 |
|---|
| 3035 | #define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
|---|
| 3036 | //SQ_LB_DATA2 |
|---|
| 3037 | #define SQ_LB_DATA2__DATA__SHIFT 0x0 |
|---|
| 3038 | #define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
|---|
| 3039 | //SQ_LB_DATA3 |
|---|
| 3040 | #define SQ_LB_DATA3__DATA__SHIFT 0x0 |
|---|
| 3041 | #define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
|---|
| 3042 | //SQ_LB_CTR_SEL |
|---|
| 3043 | #define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 |
|---|
| 3044 | #define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 |
|---|
| 3045 | #define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 |
|---|
| 3046 | #define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc |
|---|
| 3047 | #define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL |
|---|
| 3048 | #define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L |
|---|
| 3049 | #define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L |
|---|
| 3050 | #define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L |
|---|
| 3051 | //SQ_LB_CTR0_CU |
|---|
| 3052 | #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 |
|---|
| 3053 | #define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 |
|---|
| 3054 | #define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL |
|---|
| 3055 | #define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L |
|---|
| 3056 | //SQ_LB_CTR1_CU |
|---|
| 3057 | #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 |
|---|
| 3058 | #define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 |
|---|
| 3059 | #define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL |
|---|
| 3060 | #define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L |
|---|
| 3061 | //SQ_LB_CTR2_CU |
|---|
| 3062 | #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 |
|---|
| 3063 | #define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 |
|---|
| 3064 | #define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL |
|---|
| 3065 | #define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L |
|---|
| 3066 | //SQ_LB_CTR3_CU |
|---|
| 3067 | #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 |
|---|
| 3068 | #define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 |
|---|
| 3069 | #define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL |
|---|
| 3070 | #define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L |
|---|
| 3071 | //SQC_EDC_CNT |
|---|
| 3072 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 |
|---|
| 3073 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 |
|---|
| 3074 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 |
|---|
| 3075 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 |
|---|
| 3076 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 |
|---|
| 3077 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa |
|---|
| 3078 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc |
|---|
| 3079 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe |
|---|
| 3080 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 |
|---|
| 3081 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 |
|---|
| 3082 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 |
|---|
| 3083 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 |
|---|
| 3084 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 |
|---|
| 3085 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a |
|---|
| 3086 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c |
|---|
| 3087 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e |
|---|
| 3088 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L |
|---|
| 3089 | #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL |
|---|
| 3090 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L |
|---|
| 3091 | #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L |
|---|
| 3092 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L |
|---|
| 3093 | #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L |
|---|
| 3094 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L |
|---|
| 3095 | #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L |
|---|
| 3096 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L |
|---|
| 3097 | #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L |
|---|
| 3098 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L |
|---|
| 3099 | #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L |
|---|
| 3100 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L |
|---|
| 3101 | #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L |
|---|
| 3102 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L |
|---|
| 3103 | #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L |
|---|
| 3104 | //SQ_EDC_SEC_CNT |
|---|
| 3105 | #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 |
|---|
| 3106 | #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 |
|---|
| 3107 | #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 |
|---|
| 3108 | #define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL |
|---|
| 3109 | #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L |
|---|
| 3110 | #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L |
|---|
| 3111 | //SQ_EDC_DED_CNT |
|---|
| 3112 | #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 |
|---|
| 3113 | #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 |
|---|
| 3114 | #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 |
|---|
| 3115 | #define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL |
|---|
| 3116 | #define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L |
|---|
| 3117 | #define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L |
|---|
| 3118 | //SQ_EDC_INFO |
|---|
| 3119 | #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 |
|---|
| 3120 | #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 |
|---|
| 3121 | #define SQ_EDC_INFO__SOURCE__SHIFT 0x6 |
|---|
| 3122 | #define SQ_EDC_INFO__VM_ID__SHIFT 0x9 |
|---|
| 3123 | #define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL |
|---|
| 3124 | #define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L |
|---|
| 3125 | #define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L |
|---|
| 3126 | #define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L |
|---|
| 3127 | //SQ_EDC_CNT |
|---|
| 3128 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 |
|---|
| 3129 | #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 |
|---|
| 3130 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 |
|---|
| 3131 | #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 |
|---|
| 3132 | #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 |
|---|
| 3133 | #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa |
|---|
| 3134 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc |
|---|
| 3135 | #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe |
|---|
| 3136 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 |
|---|
| 3137 | #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 |
|---|
| 3138 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 |
|---|
| 3139 | #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 |
|---|
| 3140 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 |
|---|
| 3141 | #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a |
|---|
| 3142 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L |
|---|
| 3143 | #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL |
|---|
| 3144 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L |
|---|
| 3145 | #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L |
|---|
| 3146 | #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L |
|---|
| 3147 | #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L |
|---|
| 3148 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L |
|---|
| 3149 | #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L |
|---|
| 3150 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L |
|---|
| 3151 | #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L |
|---|
| 3152 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L |
|---|
| 3153 | #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L |
|---|
| 3154 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L |
|---|
| 3155 | #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L |
|---|
| 3156 | //SQ_EDC_FUE_CNTL |
|---|
| 3157 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
|---|
| 3158 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
|---|
| 3159 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
|---|
| 3160 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
|---|
| 3161 | //SQ_THREAD_TRACE_WORD_CMN |
|---|
| 3162 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3163 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 |
|---|
| 3164 | #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL |
|---|
| 3165 | #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L |
|---|
| 3166 | //SQ_THREAD_TRACE_WORD_EVENT |
|---|
| 3167 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3168 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 |
|---|
| 3169 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 |
|---|
| 3170 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 |
|---|
| 3171 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa |
|---|
| 3172 | #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL |
|---|
| 3173 | #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L |
|---|
| 3174 | #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L |
|---|
| 3175 | #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L |
|---|
| 3176 | #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L |
|---|
| 3177 | //SQ_THREAD_TRACE_WORD_INST |
|---|
| 3178 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3179 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 |
|---|
| 3180 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 |
|---|
| 3181 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 |
|---|
| 3182 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb |
|---|
| 3183 | #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL |
|---|
| 3184 | #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L |
|---|
| 3185 | #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L |
|---|
| 3186 | #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L |
|---|
| 3187 | #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L |
|---|
| 3188 | //SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 |
|---|
| 3189 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3190 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 |
|---|
| 3191 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 |
|---|
| 3192 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 |
|---|
| 3193 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf |
|---|
| 3194 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 |
|---|
| 3195 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3196 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L |
|---|
| 3197 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L |
|---|
| 3198 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L |
|---|
| 3199 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L |
|---|
| 3200 | #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L |
|---|
| 3201 | //SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 |
|---|
| 3202 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3203 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 |
|---|
| 3204 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 |
|---|
| 3205 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 |
|---|
| 3206 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa |
|---|
| 3207 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe |
|---|
| 3208 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 |
|---|
| 3209 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3210 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L |
|---|
| 3211 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L |
|---|
| 3212 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L |
|---|
| 3213 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L |
|---|
| 3214 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L |
|---|
| 3215 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L |
|---|
| 3216 | //SQ_THREAD_TRACE_WORD_ISSUE |
|---|
| 3217 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3218 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 |
|---|
| 3219 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 |
|---|
| 3220 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 |
|---|
| 3221 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa |
|---|
| 3222 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc |
|---|
| 3223 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe |
|---|
| 3224 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 |
|---|
| 3225 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 |
|---|
| 3226 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 |
|---|
| 3227 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 |
|---|
| 3228 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 |
|---|
| 3229 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a |
|---|
| 3230 | #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3231 | #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L |
|---|
| 3232 | #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L |
|---|
| 3233 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L |
|---|
| 3234 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L |
|---|
| 3235 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L |
|---|
| 3236 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L |
|---|
| 3237 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L |
|---|
| 3238 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L |
|---|
| 3239 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L |
|---|
| 3240 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L |
|---|
| 3241 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L |
|---|
| 3242 | #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L |
|---|
| 3243 | //SQ_THREAD_TRACE_WORD_MISC |
|---|
| 3244 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3245 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 |
|---|
| 3246 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc |
|---|
| 3247 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd |
|---|
| 3248 | #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL |
|---|
| 3249 | #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L |
|---|
| 3250 | #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L |
|---|
| 3251 | #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L |
|---|
| 3252 | //SQ_THREAD_TRACE_WORD_PERF_1_OF_2 |
|---|
| 3253 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3254 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 |
|---|
| 3255 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 |
|---|
| 3256 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 |
|---|
| 3257 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa |
|---|
| 3258 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc |
|---|
| 3259 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 |
|---|
| 3260 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3261 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L |
|---|
| 3262 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L |
|---|
| 3263 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L |
|---|
| 3264 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L |
|---|
| 3265 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L |
|---|
| 3266 | #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L |
|---|
| 3267 | //SQ_THREAD_TRACE_WORD_REG_1_OF_2 |
|---|
| 3268 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3269 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 |
|---|
| 3270 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 |
|---|
| 3271 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 |
|---|
| 3272 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 |
|---|
| 3273 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa |
|---|
| 3274 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe |
|---|
| 3275 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf |
|---|
| 3276 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 |
|---|
| 3277 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3278 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L |
|---|
| 3279 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L |
|---|
| 3280 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L |
|---|
| 3281 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L |
|---|
| 3282 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L |
|---|
| 3283 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L |
|---|
| 3284 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L |
|---|
| 3285 | #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L |
|---|
| 3286 | //SQ_THREAD_TRACE_WORD_REG_2_OF_2 |
|---|
| 3287 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 |
|---|
| 3288 | #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL |
|---|
| 3289 | //SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 |
|---|
| 3290 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3291 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 |
|---|
| 3292 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 |
|---|
| 3293 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 |
|---|
| 3294 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 |
|---|
| 3295 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 |
|---|
| 3296 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3297 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L |
|---|
| 3298 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L |
|---|
| 3299 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L |
|---|
| 3300 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L |
|---|
| 3301 | #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L |
|---|
| 3302 | //SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 |
|---|
| 3303 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 |
|---|
| 3304 | #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL |
|---|
| 3305 | //SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 |
|---|
| 3306 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3307 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 |
|---|
| 3308 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3309 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L |
|---|
| 3310 | //SQ_THREAD_TRACE_WORD_WAVE |
|---|
| 3311 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3312 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 |
|---|
| 3313 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 |
|---|
| 3314 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 |
|---|
| 3315 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa |
|---|
| 3316 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe |
|---|
| 3317 | #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL |
|---|
| 3318 | #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L |
|---|
| 3319 | #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L |
|---|
| 3320 | #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L |
|---|
| 3321 | #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L |
|---|
| 3322 | #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L |
|---|
| 3323 | //SQ_THREAD_TRACE_WORD_WAVE_START |
|---|
| 3324 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 |
|---|
| 3325 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 |
|---|
| 3326 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 |
|---|
| 3327 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 |
|---|
| 3328 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa |
|---|
| 3329 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe |
|---|
| 3330 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 |
|---|
| 3331 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 |
|---|
| 3332 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 |
|---|
| 3333 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d |
|---|
| 3334 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL |
|---|
| 3335 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L |
|---|
| 3336 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L |
|---|
| 3337 | #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L |
|---|
| 3338 | #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L |
|---|
| 3339 | #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L |
|---|
| 3340 | #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L |
|---|
| 3341 | #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L |
|---|
| 3342 | #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L |
|---|
| 3343 | #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L |
|---|
| 3344 | //SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 |
|---|
| 3345 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 |
|---|
| 3346 | #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL |
|---|
| 3347 | //SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 |
|---|
| 3348 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 |
|---|
| 3349 | #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL |
|---|
| 3350 | //SQ_THREAD_TRACE_WORD_PERF_2_OF_2 |
|---|
| 3351 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 |
|---|
| 3352 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 |
|---|
| 3353 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 |
|---|
| 3354 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL |
|---|
| 3355 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L |
|---|
| 3356 | #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L |
|---|
| 3357 | //SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 |
|---|
| 3358 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 |
|---|
| 3359 | #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL |
|---|
| 3360 | //SQ_WREXEC_EXEC_HI |
|---|
| 3361 | #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 |
|---|
| 3362 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a |
|---|
| 3363 | #define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b |
|---|
| 3364 | #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c |
|---|
| 3365 | #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f |
|---|
| 3366 | #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL |
|---|
| 3367 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L |
|---|
| 3368 | #define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L |
|---|
| 3369 | #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L |
|---|
| 3370 | #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L |
|---|
| 3371 | //SQ_WREXEC_EXEC_LO |
|---|
| 3372 | #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 |
|---|
| 3373 | #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
|---|
| 3374 | //SQ_BUF_RSRC_WORD0 |
|---|
| 3375 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 |
|---|
| 3376 | #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL |
|---|
| 3377 | //SQ_BUF_RSRC_WORD1 |
|---|
| 3378 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 |
|---|
| 3379 | #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 |
|---|
| 3380 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e |
|---|
| 3381 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f |
|---|
| 3382 | #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL |
|---|
| 3383 | #define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L |
|---|
| 3384 | #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L |
|---|
| 3385 | #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L |
|---|
| 3386 | //SQ_BUF_RSRC_WORD2 |
|---|
| 3387 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 |
|---|
| 3388 | #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL |
|---|
| 3389 | //SQ_BUF_RSRC_WORD3 |
|---|
| 3390 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 |
|---|
| 3391 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 |
|---|
| 3392 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 |
|---|
| 3393 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 |
|---|
| 3394 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc |
|---|
| 3395 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf |
|---|
| 3396 | #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 |
|---|
| 3397 | #define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 |
|---|
| 3398 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 |
|---|
| 3399 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 |
|---|
| 3400 | #define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b |
|---|
| 3401 | #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e |
|---|
| 3402 | #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L |
|---|
| 3403 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L |
|---|
| 3404 | #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L |
|---|
| 3405 | #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L |
|---|
| 3406 | #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L |
|---|
| 3407 | #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L |
|---|
| 3408 | #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L |
|---|
| 3409 | #define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L |
|---|
| 3410 | #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L |
|---|
| 3411 | #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L |
|---|
| 3412 | #define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L |
|---|
| 3413 | #define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L |
|---|
| 3414 | //SQ_IMG_RSRC_WORD0 |
|---|
| 3415 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 |
|---|
| 3416 | #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL |
|---|
| 3417 | //SQ_IMG_RSRC_WORD1 |
|---|
| 3418 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 |
|---|
| 3419 | #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 |
|---|
| 3420 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 |
|---|
| 3421 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a |
|---|
| 3422 | #define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e |
|---|
| 3423 | #define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f |
|---|
| 3424 | #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL |
|---|
| 3425 | #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L |
|---|
| 3426 | #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L |
|---|
| 3427 | #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L |
|---|
| 3428 | #define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L |
|---|
| 3429 | #define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L |
|---|
| 3430 | //SQ_IMG_RSRC_WORD2 |
|---|
| 3431 | #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 |
|---|
| 3432 | #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe |
|---|
| 3433 | #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c |
|---|
| 3434 | #define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL |
|---|
| 3435 | #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L |
|---|
| 3436 | #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L |
|---|
| 3437 | //SQ_IMG_RSRC_WORD3 |
|---|
| 3438 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 |
|---|
| 3439 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 |
|---|
| 3440 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 |
|---|
| 3441 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 |
|---|
| 3442 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc |
|---|
| 3443 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 |
|---|
| 3444 | #define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 |
|---|
| 3445 | #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c |
|---|
| 3446 | #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L |
|---|
| 3447 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L |
|---|
| 3448 | #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L |
|---|
| 3449 | #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L |
|---|
| 3450 | #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L |
|---|
| 3451 | #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L |
|---|
| 3452 | #define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L |
|---|
| 3453 | #define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L |
|---|
| 3454 | //SQ_IMG_RSRC_WORD4 |
|---|
| 3455 | #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 |
|---|
| 3456 | #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd |
|---|
| 3457 | #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d |
|---|
| 3458 | #define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL |
|---|
| 3459 | #define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L |
|---|
| 3460 | #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L |
|---|
| 3461 | //SQ_IMG_RSRC_WORD5 |
|---|
| 3462 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 |
|---|
| 3463 | #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd |
|---|
| 3464 | #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 |
|---|
| 3465 | #define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 |
|---|
| 3466 | #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a |
|---|
| 3467 | #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b |
|---|
| 3468 | #define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c |
|---|
| 3469 | #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL |
|---|
| 3470 | #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L |
|---|
| 3471 | #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L |
|---|
| 3472 | #define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L |
|---|
| 3473 | #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L |
|---|
| 3474 | #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L |
|---|
| 3475 | #define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L |
|---|
| 3476 | //SQ_IMG_RSRC_WORD6 |
|---|
| 3477 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 |
|---|
| 3478 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc |
|---|
| 3479 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 |
|---|
| 3480 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 |
|---|
| 3481 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 |
|---|
| 3482 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 |
|---|
| 3483 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 |
|---|
| 3484 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c |
|---|
| 3485 | #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL |
|---|
| 3486 | #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L |
|---|
| 3487 | #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L |
|---|
| 3488 | #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L |
|---|
| 3489 | #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L |
|---|
| 3490 | #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L |
|---|
| 3491 | #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L |
|---|
| 3492 | #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L |
|---|
| 3493 | //SQ_IMG_RSRC_WORD7 |
|---|
| 3494 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 |
|---|
| 3495 | #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL |
|---|
| 3496 | //SQ_IMG_SAMP_WORD0 |
|---|
| 3497 | #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 |
|---|
| 3498 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 |
|---|
| 3499 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 |
|---|
| 3500 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 |
|---|
| 3501 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc |
|---|
| 3502 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf |
|---|
| 3503 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 |
|---|
| 3504 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 |
|---|
| 3505 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 |
|---|
| 3506 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 |
|---|
| 3507 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b |
|---|
| 3508 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c |
|---|
| 3509 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d |
|---|
| 3510 | #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f |
|---|
| 3511 | #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L |
|---|
| 3512 | #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L |
|---|
| 3513 | #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L |
|---|
| 3514 | #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L |
|---|
| 3515 | #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L |
|---|
| 3516 | #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L |
|---|
| 3517 | #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L |
|---|
| 3518 | #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L |
|---|
| 3519 | #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L |
|---|
| 3520 | #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L |
|---|
| 3521 | #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L |
|---|
| 3522 | #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L |
|---|
| 3523 | #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L |
|---|
| 3524 | #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L |
|---|
| 3525 | //SQ_IMG_SAMP_WORD1 |
|---|
| 3526 | #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 |
|---|
| 3527 | #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc |
|---|
| 3528 | #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 |
|---|
| 3529 | #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c |
|---|
| 3530 | #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL |
|---|
| 3531 | #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L |
|---|
| 3532 | #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L |
|---|
| 3533 | #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L |
|---|
| 3534 | //SQ_IMG_SAMP_WORD2 |
|---|
| 3535 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 |
|---|
| 3536 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe |
|---|
| 3537 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 |
|---|
| 3538 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 |
|---|
| 3539 | #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 |
|---|
| 3540 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a |
|---|
| 3541 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c |
|---|
| 3542 | #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d |
|---|
| 3543 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e |
|---|
| 3544 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f |
|---|
| 3545 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL |
|---|
| 3546 | #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L |
|---|
| 3547 | #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L |
|---|
| 3548 | #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L |
|---|
| 3549 | #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L |
|---|
| 3550 | #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L |
|---|
| 3551 | #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L |
|---|
| 3552 | #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L |
|---|
| 3553 | #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L |
|---|
| 3554 | #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L |
|---|
| 3555 | //SQ_IMG_SAMP_WORD3 |
|---|
| 3556 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 |
|---|
| 3557 | #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc |
|---|
| 3558 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e |
|---|
| 3559 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL |
|---|
| 3560 | #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L |
|---|
| 3561 | #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L |
|---|
| 3562 | //SQ_FLAT_SCRATCH_WORD0 |
|---|
| 3563 | #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 |
|---|
| 3564 | #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL |
|---|
| 3565 | //SQ_FLAT_SCRATCH_WORD1 |
|---|
| 3566 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 |
|---|
| 3567 | #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL |
|---|
| 3568 | //SQ_M0_GPR_IDX_WORD |
|---|
| 3569 | #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 |
|---|
| 3570 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc |
|---|
| 3571 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd |
|---|
| 3572 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe |
|---|
| 3573 | #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf |
|---|
| 3574 | #define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL |
|---|
| 3575 | #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L |
|---|
| 3576 | #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L |
|---|
| 3577 | #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L |
|---|
| 3578 | #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L |
|---|
| 3579 | //SQC_ICACHE_UTCL1_CNTL1 |
|---|
| 3580 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
|---|
| 3581 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
|---|
| 3582 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
|---|
| 3583 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
|---|
| 3584 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
|---|
| 3585 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
|---|
| 3586 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
|---|
| 3587 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
|---|
| 3588 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
|---|
| 3589 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
|---|
| 3590 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
|---|
| 3591 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
|---|
| 3592 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
|---|
| 3593 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
|---|
| 3594 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
|---|
| 3595 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
|---|
| 3596 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
|---|
| 3597 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
|---|
| 3598 | #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
|---|
| 3599 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
|---|
| 3600 | #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
|---|
| 3601 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
|---|
| 3602 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
|---|
| 3603 | #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
|---|
| 3604 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
|---|
| 3605 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
|---|
| 3606 | #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
|---|
| 3607 | #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
|---|
| 3608 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
|---|
| 3609 | #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
|---|
| 3610 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
|---|
| 3611 | #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
|---|
| 3612 | //SQC_ICACHE_UTCL1_CNTL2 |
|---|
| 3613 | #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
|---|
| 3614 | #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
|---|
| 3615 | #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
|---|
| 3616 | #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
|---|
| 3617 | #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
|---|
| 3618 | #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
|---|
| 3619 | #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
|---|
| 3620 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
|---|
| 3621 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
|---|
| 3622 | #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
|---|
| 3623 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
|---|
| 3624 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
|---|
| 3625 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
|---|
| 3626 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
|---|
| 3627 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
|---|
| 3628 | #define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
|---|
| 3629 | #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
|---|
| 3630 | #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
|---|
| 3631 | #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
|---|
| 3632 | #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
|---|
| 3633 | #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
|---|
| 3634 | #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
|---|
| 3635 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
|---|
| 3636 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
|---|
| 3637 | #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
|---|
| 3638 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
|---|
| 3639 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
|---|
| 3640 | #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
|---|
| 3641 | #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
|---|
| 3642 | #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
|---|
| 3643 | //SQC_DCACHE_UTCL1_CNTL1 |
|---|
| 3644 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
|---|
| 3645 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
|---|
| 3646 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
|---|
| 3647 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
|---|
| 3648 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
|---|
| 3649 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
|---|
| 3650 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
|---|
| 3651 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
|---|
| 3652 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 |
|---|
| 3653 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 |
|---|
| 3654 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 |
|---|
| 3655 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
|---|
| 3656 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
|---|
| 3657 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
|---|
| 3658 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
|---|
| 3659 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
|---|
| 3660 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
|---|
| 3661 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
|---|
| 3662 | #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
|---|
| 3663 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
|---|
| 3664 | #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
|---|
| 3665 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
|---|
| 3666 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
|---|
| 3667 | #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
|---|
| 3668 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L |
|---|
| 3669 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L |
|---|
| 3670 | #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L |
|---|
| 3671 | #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
|---|
| 3672 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
|---|
| 3673 | #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
|---|
| 3674 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
|---|
| 3675 | #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
|---|
| 3676 | //SQC_DCACHE_UTCL1_CNTL2 |
|---|
| 3677 | #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 |
|---|
| 3678 | #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
|---|
| 3679 | #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
|---|
| 3680 | #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
|---|
| 3681 | #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
|---|
| 3682 | #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
|---|
| 3683 | #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
|---|
| 3684 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
|---|
| 3685 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
|---|
| 3686 | #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
|---|
| 3687 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
|---|
| 3688 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
|---|
| 3689 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
|---|
| 3690 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
|---|
| 3691 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
|---|
| 3692 | #define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL |
|---|
| 3693 | #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
|---|
| 3694 | #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
|---|
| 3695 | #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
|---|
| 3696 | #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
|---|
| 3697 | #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
|---|
| 3698 | #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
|---|
| 3699 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
|---|
| 3700 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
|---|
| 3701 | #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
|---|
| 3702 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
|---|
| 3703 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
|---|
| 3704 | #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
|---|
| 3705 | #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
|---|
| 3706 | #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
|---|
| 3707 | //SQC_ICACHE_UTCL1_STATUS |
|---|
| 3708 | #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
|---|
| 3709 | #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
|---|
| 3710 | #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
|---|
| 3711 | #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
|---|
| 3712 | #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
|---|
| 3713 | #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
|---|
| 3714 | //SQC_DCACHE_UTCL1_STATUS |
|---|
| 3715 | #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
|---|
| 3716 | #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
|---|
| 3717 | #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
|---|
| 3718 | #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
|---|
| 3719 | #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
|---|
| 3720 | #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
|---|
| 3721 | |
|---|
| 3722 | |
|---|
| 3723 | // addressBlock: gc_shsdec |
|---|
| 3724 | //SX_DEBUG_BUSY |
|---|
| 3725 | #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 |
|---|
| 3726 | #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 |
|---|
| 3727 | #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 |
|---|
| 3728 | #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 |
|---|
| 3729 | #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 |
|---|
| 3730 | #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 |
|---|
| 3731 | #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 |
|---|
| 3732 | #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 |
|---|
| 3733 | #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 |
|---|
| 3734 | #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 |
|---|
| 3735 | #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa |
|---|
| 3736 | #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb |
|---|
| 3737 | #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc |
|---|
| 3738 | #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd |
|---|
| 3739 | #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe |
|---|
| 3740 | #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf |
|---|
| 3741 | #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 |
|---|
| 3742 | #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 |
|---|
| 3743 | #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 |
|---|
| 3744 | #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 |
|---|
| 3745 | #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 |
|---|
| 3746 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 |
|---|
| 3747 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 |
|---|
| 3748 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 |
|---|
| 3749 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 |
|---|
| 3750 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 |
|---|
| 3751 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a |
|---|
| 3752 | #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b |
|---|
| 3753 | #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c |
|---|
| 3754 | #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d |
|---|
| 3755 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e |
|---|
| 3756 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f |
|---|
| 3757 | #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L |
|---|
| 3758 | #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L |
|---|
| 3759 | #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L |
|---|
| 3760 | #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L |
|---|
| 3761 | #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L |
|---|
| 3762 | #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L |
|---|
| 3763 | #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L |
|---|
| 3764 | #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L |
|---|
| 3765 | #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L |
|---|
| 3766 | #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L |
|---|
| 3767 | #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L |
|---|
| 3768 | #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L |
|---|
| 3769 | #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L |
|---|
| 3770 | #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L |
|---|
| 3771 | #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L |
|---|
| 3772 | #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L |
|---|
| 3773 | #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L |
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| 3774 | #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L |
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| 3775 | #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L |
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| 3776 | #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L |
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| 3777 | #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L |
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| 3778 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L |
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| 3779 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L |
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| 3780 | #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L |
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| 3781 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L |
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| 3782 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L |
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| 3783 | #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L |
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| 3784 | #define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L |
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| 3785 | #define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L |
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| 3786 | #define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L |
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| 3787 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L |
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| 3788 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L |
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| 3789 | //SX_DEBUG_BUSY_2 |
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| 3790 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x0 |
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| 3791 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1 |
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| 3792 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x2 |
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| 3793 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x3 |
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| 3794 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x4 |
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| 3795 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x5 |
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| 3796 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x6 |
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| 3797 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x7 |
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| 3798 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x8 |
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| 3799 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x9 |
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| 3800 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0xa |
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| 3801 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0xb |
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| 3802 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0xc |
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| 3803 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0xd |
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| 3804 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0xe |
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| 3805 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0xf |
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| 3806 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x10 |
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| 3807 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x11 |
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| 3808 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x12 |
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| 3809 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x13 |
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| 3810 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x14 |
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| 3811 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x15 |
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| 3812 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x16 |
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| 3813 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x17 |
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| 3814 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x18 |
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| 3815 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x19 |
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| 3816 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x1a |
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| 3817 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x1b |
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| 3818 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x1c |
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| 3819 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x1d |
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| 3820 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x1e |
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| 3821 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x1f |
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| 3822 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L |
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| 3823 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L |
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| 3824 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L |
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| 3825 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L |
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| 3826 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L |
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| 3827 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L |
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| 3828 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L |
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| 3829 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L |
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| 3830 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L |
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| 3831 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L |
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| 3832 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L |
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| 3833 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L |
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| 3834 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L |
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| 3835 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L |
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| 3836 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L |
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| 3837 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L |
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| 3838 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L |
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| 3839 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L |
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| 3840 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L |
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| 3841 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L |
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| 3842 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L |
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| 3843 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L |
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| 3844 | #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L |
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| 3845 | #define |
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