1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _gc_9_2_1_SH_MASK_HEADER
22#define _gc_9_2_1_SH_MASK_HEADER
23
24
25// addressBlock: gc_grbmdec
26//GRBM_CNTL
27#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
28#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
29#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
30#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
31//GRBM_SKEW_CNTL
32#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
33#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
34#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
35#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
36//GRBM_STATUS2
37#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
38#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
39#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
40#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
41#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
42#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
43#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
44#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
45#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
46#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
47#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
48#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
49#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
50#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
51#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
52#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
53#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
54#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
55#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
56#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
57#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
58#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
59#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
60#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
61#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
62#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
63#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
64#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
65#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
66#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
67#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
68#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
69#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
70#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
71#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
72#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
73#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
74#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
75#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
76#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
77#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
78#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
79#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
80#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
81#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
82#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
83#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
84#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
85#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
86#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
87//GRBM_PWR_CNTL
88#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
89#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
90#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
91#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
92#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
93#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
94#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
95#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
96#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
97#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
98#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
99#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
100//GRBM_STATUS
101#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
102#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
103#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
104#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
105#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
106#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
107#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
108#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
109#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
110#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
111#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
112#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
113#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
114#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
115#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
116#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
117#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
118#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
119#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
120#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
121#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
122#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
123#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
124#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
125#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
126#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
127#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
128#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
129#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
130#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
131#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
132#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
133#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
134#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
135#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
136#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
137#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
138#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
139#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
140#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
141#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
142#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
143#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
144#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
145#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
146#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
147#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
148#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
149//GRBM_STATUS_SE0
150#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
151#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
152#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
153#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
154#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
155#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
156#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
157#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
158#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
159#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
160#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
161#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
162#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
163#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
164#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
165#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
166#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
167#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
168#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
169#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
170#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
171#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
172#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
173#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
174//GRBM_STATUS_SE1
175#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
176#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
177#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
178#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
179#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
180#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
181#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
182#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
183#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
184#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
185#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
186#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
187#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
188#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
189#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
190#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
191#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
192#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
193#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
194#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
195#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
196#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
197#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
198#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
199//GRBM_SOFT_RESET
200#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
201#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
202#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
203#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
204#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
205#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
206#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
207#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
208#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
209#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
210#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
211#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
212#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
213#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
214#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
215#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
216#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
217#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
218//GRBM_GFX_CLKEN_CNTL
219#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
220#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
221#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
222#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
223//GRBM_WAIT_IDLE_CLOCKS
224#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
225#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
226//GRBM_STATUS_SE2
227#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
228#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
229#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
230#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
231#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
232#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
233#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
234#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
235#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
236#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
237#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
238#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
239#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
240#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
241#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
242#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
243#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
244#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
245#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
246#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
247#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
248#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
249#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
250#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
251//GRBM_STATUS_SE3
252#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
253#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
254#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
255#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
256#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
257#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
258#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
259#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
260#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
261#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
262#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
263#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
264#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
265#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
266#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
267#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
268#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
269#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
270#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
271#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
272#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
273#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
274#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
275#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
276//GRBM_READ_ERROR
277#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
278#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
279#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
280#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
281#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
282#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
283#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
284#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
285//GRBM_READ_ERROR2
286#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
287#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
288#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
289#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
290#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
291#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
292#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
293#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
294#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
295#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
296#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
297#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
298#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
299#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
300#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
301#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
302#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
303#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
304#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
305#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
306#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
307#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
308#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
309#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
310#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
311#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
312#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
313#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
314#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
315#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
316#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
317#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
318//GRBM_INT_CNTL
319#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
320#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
321#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
322#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
323//GRBM_TRAP_OP
324#define GRBM_TRAP_OP__RW__SHIFT 0x0
325#define GRBM_TRAP_OP__RW_MASK 0x00000001L
326//GRBM_TRAP_ADDR
327#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
328#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
329//GRBM_TRAP_ADDR_MSK
330#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
331#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
332//GRBM_TRAP_WD
333#define GRBM_TRAP_WD__DATA__SHIFT 0x0
334#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
335//GRBM_TRAP_WD_MSK
336#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
337#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
338//GRBM_DSM_BYPASS
339#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
340#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
341#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
342#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
343//GRBM_WRITE_ERROR
344#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
345#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
346#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
347#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
348#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
349#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
350#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
351#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
352#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
353#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
354#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
355#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
356#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
357#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
358#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
359#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
360#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
361#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
362//GRBM_IOV_ERROR
363#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
364#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
365#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
366#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
367#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
368#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
369#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
370#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
371#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
372#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
373//GRBM_CHIP_REVISION
374#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
375#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
376//GRBM_GFX_CNTL
377#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
378#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
379#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
380#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
381#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
382#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
383#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
384#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
385//GRBM_RSMU_CFG
386#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
387#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
388#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
389#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11
390#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
391#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
392#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
393#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L
394//GRBM_IH_CREDIT
395#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
396#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
397#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
398#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
399//GRBM_PWR_CNTL2
400#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
401#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
402#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
403#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
404//GRBM_UTCL2_INVAL_RANGE_START
405#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
406#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
407//GRBM_UTCL2_INVAL_RANGE_END
408#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
409#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
410//GRBM_RSMU_READ_ERROR
411#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
412#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
413#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
414#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
415#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
416#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
417#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
418#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
419#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
420#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
421//GRBM_CHICKEN_BITS
422#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
423#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
424//GRBM_FENCE_RANGE0
425#define GRBM_FENCE_RANGE0__START__SHIFT 0x0
426#define GRBM_FENCE_RANGE0__END__SHIFT 0x10
427#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL
428#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L
429//GRBM_FENCE_RANGE1
430#define GRBM_FENCE_RANGE1__START__SHIFT 0x0
431#define GRBM_FENCE_RANGE1__END__SHIFT 0x10
432#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL
433#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L
434//GRBM_NOWHERE
435#define GRBM_NOWHERE__DATA__SHIFT 0x0
436#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
437//GRBM_SCRATCH_REG0
438#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
439#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
440//GRBM_SCRATCH_REG1
441#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
442#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
443//GRBM_SCRATCH_REG2
444#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
445#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
446//GRBM_SCRATCH_REG3
447#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
448#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
449//GRBM_SCRATCH_REG4
450#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
451#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
452//GRBM_SCRATCH_REG5
453#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
454#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
455//GRBM_SCRATCH_REG6
456#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
457#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
458//GRBM_SCRATCH_REG7
459#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
460#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
461
462
463// addressBlock: gc_cpdec
464//CP_CPC_STATUS
465#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
466#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
467#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
468#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
469#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
470#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
471#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
472#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
473#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
474#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
475#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
476#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
477#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
478#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
479#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
480#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
481#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
482#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
483#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
484#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
485#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
486#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
487#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
488#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
489#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
490#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
491#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
492#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
493#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
494#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
495#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
496#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
497//CP_CPC_BUSY_STAT
498#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
499#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
500#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
501#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
502#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
503#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
504#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
505#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
506#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
507#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
508#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
509#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
510#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
511#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
512#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
513#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
514#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
515#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
516#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
517#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
518#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
519#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
520#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
521#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
522#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
523#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
524#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
525#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
526#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
527#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
528#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
529#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
530#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
531#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
532#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
533#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
534#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
535#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
536#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
537#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
538#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
539#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
540#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
541#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
542#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
543#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
544#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
545#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
546#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
547#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
548#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
549#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
550#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
551#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
552#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
553#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
554//CP_CPC_STALLED_STAT1
555#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
556#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
557#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
558#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
559#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
560#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
561#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
562#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
563#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
564#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
565#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
566#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
567#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
568#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
569#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
570#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
571#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
572#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
573#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
574#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
575#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
576#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
577#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
578#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
579#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
580#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
581#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
582#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
583//CP_CPF_STATUS
584#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
585#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
586#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
587#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
588#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
589#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
590#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
591#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
592#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
593#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
594#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
595#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
596#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
597#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
598#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
599#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
600#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
601#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
602#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
603#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
604#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
605#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
606#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
607#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
608#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
609#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
610#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
611#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
612#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
613#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
614#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
615#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
616#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
617#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
618#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
619#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
620#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
621#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
622#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
623#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
624#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
625#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
626//CP_CPF_BUSY_STAT
627#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
628#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
629#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
630#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
631#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
632#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
633#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
634#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
635#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
636#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
637#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
638#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
639#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
640#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
641#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
642#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
643#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
644#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
645#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
646#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
647#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
648#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
649#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
650#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
651#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
652#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
653#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
654#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
655#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
656#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
657#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
658#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
659#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
660#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
661#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
662#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
663#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
664#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
665#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
666#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
667#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
668#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
669#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
670#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
671#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
672#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
673#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
674#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
675#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
676#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
677#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
678#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
679#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
680#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
681#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
682#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
683#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
684#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
685#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
686#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
687#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
688#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
689//CP_CPF_STALLED_STAT1
690#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
691#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
692#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
693#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
694#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
695#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
696#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
697#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
698#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
699#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
700#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
701#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
702#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
703#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
704#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
705#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
706#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
707#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
708#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
709#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
710#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
711#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
712//CP_CPC_GRBM_FREE_COUNT
713#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
714#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
715//CP_MEC_CNTL
716#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
717#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
718#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
719#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
720#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
721#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
722#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
723#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
724#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
725#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
726#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
727#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
728#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
729#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
730#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
731#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
732#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
733#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
734#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
735#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
736#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
737#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
738//CP_MEC_ME1_HEADER_DUMP
739#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
740#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
741//CP_MEC_ME2_HEADER_DUMP
742#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
743#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
744//CP_CPC_SCRATCH_INDEX
745#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
746#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
747//CP_CPC_SCRATCH_DATA
748#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
749#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
750//CP_CPF_GRBM_FREE_COUNT
751#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
752#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
753//CP_CPC_HALT_HYST_COUNT
754#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
755#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
756//CP_CE_COMPARE_COUNT
757#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
758#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
759//CP_CE_DE_COUNT
760#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
761#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
762//CP_DE_CE_COUNT
763#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
764#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
765//CP_DE_LAST_INVAL_COUNT
766#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
767#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
768//CP_DE_DE_COUNT
769#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
770#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
771//CP_STALLED_STAT3
772#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
773#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
774#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
775#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
776#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
777#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
778#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
779#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
780#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
781#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
782#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
783#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
784#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
785#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
786#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
787#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
788#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
789#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
790#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
791#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
792#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
793#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
794#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
795#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
796#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
797#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
798#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
799#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
800#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
801#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
802#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
803#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
804#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
805#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
806#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
807#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
808#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
809#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
810//CP_STALLED_STAT1
811#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
812#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
813#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
814#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
815#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
816#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
817#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
818#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
819#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
820#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
821#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
822#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
823#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
824#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
825#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
826#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
827#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
828#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
829#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
830#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
831#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
832#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
833#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
834#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
835#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
836#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
837#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
838#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
839#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
840#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
841#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
842#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
843//CP_STALLED_STAT2
844#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
845#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
846#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
847#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
848#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
849#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
850#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
851#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
852#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
853#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
854#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
855#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
856#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
857#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
858#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
859#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
860#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
861#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
862#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
863#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
864#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
865#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
866#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
867#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
868#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
869#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
870#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
871#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
872#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
873#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
874#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
875#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
876#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
877#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
878#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
879#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
880#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
881#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
882#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
883#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
884#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
885#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
886#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
887#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
888#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
889#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
890#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
891#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
892#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
893#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
894#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
895#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
896#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
897#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
898#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
899#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
900#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
901#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
902//CP_BUSY_STAT
903#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
904#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
905#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
906#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
907#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
908#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
909#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
910#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
911#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
912#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
913#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
914#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
915#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
916#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
917#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
918#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
919#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
920#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
921#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
922#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
923#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
924#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
925#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
926#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
927#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
928#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
929#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
930#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
931#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
932#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
933#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
934#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
935//CP_STAT
936#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
937#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
938#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
939#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
940#define CP_STAT__DC_BUSY__SHIFT 0xd
941#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
942#define CP_STAT__PFP_BUSY__SHIFT 0xf
943#define CP_STAT__MEQ_BUSY__SHIFT 0x10
944#define CP_STAT__ME_BUSY__SHIFT 0x11
945#define CP_STAT__QUERY_BUSY__SHIFT 0x12
946#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
947#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
948#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
949#define CP_STAT__DMA_BUSY__SHIFT 0x16
950#define CP_STAT__RCIU_BUSY__SHIFT 0x17
951#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
952#define CP_STAT__CE_BUSY__SHIFT 0x1a
953#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
954#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
955#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
956#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
957#define CP_STAT__CP_BUSY__SHIFT 0x1f
958#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
959#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
960#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
961#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
962#define CP_STAT__DC_BUSY_MASK 0x00002000L
963#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
964#define CP_STAT__PFP_BUSY_MASK 0x00008000L
965#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
966#define CP_STAT__ME_BUSY_MASK 0x00020000L
967#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
968#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
969#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
970#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
971#define CP_STAT__DMA_BUSY_MASK 0x00400000L
972#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
973#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
974#define CP_STAT__CE_BUSY_MASK 0x04000000L
975#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
976#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
977#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
978#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
979#define CP_STAT__CP_BUSY_MASK 0x80000000L
980//CP_ME_HEADER_DUMP
981#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
982#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
983//CP_PFP_HEADER_DUMP
984#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
985#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
986//CP_GRBM_FREE_COUNT
987#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
988#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
989#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
990#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
991#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
992#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
993//CP_CE_HEADER_DUMP
994#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
995#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
996//CP_PFP_INSTR_PNTR
997#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
998#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
999//CP_ME_INSTR_PNTR
1000#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1001#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1002//CP_CE_INSTR_PNTR
1003#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1004#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1005//CP_MEC1_INSTR_PNTR
1006#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1007#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1008//CP_MEC2_INSTR_PNTR
1009#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1010#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1011//CP_CSF_STAT
1012#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
1013#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
1014//CP_ME_CNTL
1015#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
1016#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
1017#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
1018#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
1019#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
1020#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
1021#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
1022#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
1023#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
1024#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
1025#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
1026#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
1027#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
1028#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
1029#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
1030#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
1031#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
1032#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
1033#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
1034#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
1035#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
1036#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
1037#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
1038#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
1039#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
1040#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
1041#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
1042#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
1043#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
1044#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
1045//CP_CNTX_STAT
1046#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
1047#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
1048#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
1049#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
1050#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
1051#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
1052#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
1053#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
1054//CP_ME_PREEMPTION
1055#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
1056#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
1057//CP_ROQ_THRESHOLDS
1058#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
1059#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
1060#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
1061#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
1062//CP_MEQ_STQ_THRESHOLD
1063#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
1064#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
1065//CP_RB2_RPTR
1066#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
1067#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
1068//CP_RB1_RPTR
1069#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
1070#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
1071//CP_RB0_RPTR
1072#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
1073#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
1074//CP_RB_RPTR
1075#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
1076#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
1077//CP_RB_WPTR_DELAY
1078#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
1079#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
1080#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
1081#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
1082//CP_RB_WPTR_POLL_CNTL
1083#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
1084#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1085#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
1086#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1087//CP_ROQ1_THRESHOLDS
1088#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
1089#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
1090#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
1091#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
1092#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
1093#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
1094#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
1095#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
1096//CP_ROQ2_THRESHOLDS
1097#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
1098#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
1099#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
1100#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
1101#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
1102#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
1103#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
1104#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
1105//CP_STQ_THRESHOLDS
1106#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
1107#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
1108#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
1109#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
1110#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
1111#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
1112//CP_QUEUE_THRESHOLDS
1113#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
1114#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
1115#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
1116#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
1117//CP_MEQ_THRESHOLDS
1118#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
1119#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
1120#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
1121#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
1122//CP_ROQ_AVAIL
1123#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
1124#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
1125#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
1126#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
1127//CP_STQ_AVAIL
1128#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
1129#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
1130//CP_ROQ2_AVAIL
1131#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
1132#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
1133//CP_MEQ_AVAIL
1134#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
1135#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
1136//CP_CMD_INDEX
1137#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
1138#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
1139#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
1140#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
1141#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
1142#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
1143//CP_CMD_DATA
1144#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
1145#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
1146//CP_ROQ_RB_STAT
1147#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
1148#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
1149#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
1150#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
1151//CP_ROQ_IB1_STAT
1152#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
1153#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
1154#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
1155#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
1156//CP_ROQ_IB2_STAT
1157#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
1158#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
1159#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
1160#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
1161//CP_STQ_STAT
1162#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
1163#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
1164//CP_STQ_WR_STAT
1165#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
1166#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
1167//CP_MEQ_STAT
1168#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
1169#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
1170#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
1171#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
1172//CP_CEQ1_AVAIL
1173#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
1174#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
1175#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
1176#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
1177//CP_CEQ2_AVAIL
1178#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
1179#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
1180//CP_CE_ROQ_RB_STAT
1181#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
1182#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
1183#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
1184#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
1185//CP_CE_ROQ_IB1_STAT
1186#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
1187#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
1188#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
1189#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
1190//CP_CE_ROQ_IB2_STAT
1191#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
1192#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
1193#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
1194#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
1195
1196
1197// addressBlock: gc_padec
1198//VGT_VTX_VECT_EJECT_REG
1199#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
1200#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
1201//VGT_DMA_DATA_FIFO_DEPTH
1202#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
1203#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
1204#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
1205#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
1206//VGT_DMA_REQ_FIFO_DEPTH
1207#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
1208#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
1209//VGT_DRAW_INIT_FIFO_DEPTH
1210#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
1211#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
1212//VGT_LAST_COPY_STATE
1213#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
1214#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
1215#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
1216#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
1217//VGT_CACHE_INVALIDATION
1218#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
1219#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
1220#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
1221#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
1222#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
1223#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
1224#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
1225#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
1226#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
1227#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
1228#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
1229#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
1230#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
1231#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
1232#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
1233#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
1234#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
1235#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
1236#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
1237#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
1238#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
1239#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
1240#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
1241#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
1242#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
1243#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
1244#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
1245#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
1246//VGT_STRMOUT_DELAY
1247#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
1248#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
1249#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
1250#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
1251#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
1252#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
1253#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
1254#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
1255#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
1256#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
1257//VGT_FIFO_DEPTHS
1258#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
1259#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
1260#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
1261#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
1262#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
1263#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
1264#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
1265#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
1266//VGT_GS_VERTEX_REUSE
1267#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
1268#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
1269//VGT_MC_LAT_CNTL
1270#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
1271#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
1272//IA_CNTL_STATUS
1273#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
1274#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
1275#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
1276#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
1277#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
1278#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
1279#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
1280#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
1281#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
1282#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
1283//VGT_CNTL_STATUS
1284#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
1285#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
1286#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
1287#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
1288#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
1289#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
1290#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
1291#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
1292#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
1293#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
1294#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
1295#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
1296#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
1297#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
1298#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
1299#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
1300#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
1301#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
1302#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
1303#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
1304#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
1305#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
1306//WD_CNTL_STATUS
1307#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
1308#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
1309#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
1310#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
1311#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
1312#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
1313#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
1314#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
1315//CC_GC_PRIM_CONFIG
1316#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
1317#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
1318#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
1319#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
1320//GC_USER_PRIM_CONFIG
1321#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
1322#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
1323#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
1324#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
1325//WD_QOS
1326#define WD_QOS__DRAW_STALL__SHIFT 0x0
1327#define WD_QOS__DRAW_STALL_MASK 0x00000001L
1328//WD_UTCL1_CNTL
1329#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
1330#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
1331#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
1332#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
1333#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
1334#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
1335#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
1336#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
1337#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
1338#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
1339#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
1340#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
1341#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
1342#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
1343#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
1344#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
1345//WD_UTCL1_STATUS
1346#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
1347#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
1348#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
1349#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
1350#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
1351#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
1352#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
1353#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
1354#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
1355#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
1356#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
1357#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
1358//IA_UTCL1_CNTL
1359#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
1360#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
1361#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
1362#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
1363#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
1364#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
1365#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
1366#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
1367#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
1368#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
1369#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
1370#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
1371#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
1372#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
1373#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
1374#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
1375//IA_UTCL1_STATUS
1376#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
1377#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
1378#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
1379#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
1380#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
1381#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
1382#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
1383#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
1384#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
1385#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
1386#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
1387#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
1388//VGT_SYS_CONFIG
1389#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
1390#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
1391#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
1392#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
1393#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
1394#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
1395//VGT_VS_MAX_WAVE_ID
1396#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
1397#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
1398//VGT_GS_MAX_WAVE_ID
1399#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
1400#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
1401//GFX_PIPE_CONTROL
1402#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
1403#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
1404#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
1405#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
1406#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
1407#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
1408//CC_GC_SHADER_ARRAY_CONFIG
1409#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
1410#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
1411//GC_USER_SHADER_ARRAY_CONFIG
1412#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
1413#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
1414//VGT_DMA_PRIMITIVE_TYPE
1415#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
1416#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
1417//VGT_DMA_CONTROL
1418#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
1419#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
1420#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
1421#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
1422#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
1423#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
1424#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
1425#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
1426#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
1427#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
1428#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
1429#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
1430#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
1431#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
1432//VGT_DMA_LS_HS_CONFIG
1433#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
1434#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
1435//WD_BUF_RESOURCE_1
1436#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
1437#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
1438#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
1439#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
1440//WD_BUF_RESOURCE_2
1441#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
1442#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
1443#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
1444#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
1445#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
1446#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
1447//PA_CL_CNTL_STATUS
1448#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
1449#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
1450#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
1451#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
1452#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
1453#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
1454//PA_CL_ENHANCE
1455#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
1456#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
1457#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
1458#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
1459#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
1460#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
1461#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
1462#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
1463#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
1464#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
1465#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
1466#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
1467#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11
1468#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12
1469#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13
1470#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14
1471#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15
1472#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
1473#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
1474#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
1475#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
1476#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
1477#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
1478#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
1479#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
1480#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L
1481#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
1482#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
1483#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
1484#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
1485#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
1486#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
1487#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
1488#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L
1489#define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L
1490#define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L
1491#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L
1492#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L
1493#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
1494#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
1495#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
1496#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
1497//PA_CL_RESET_DEBUG
1498#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
1499#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L
1500//PA_SU_CNTL_STATUS
1501#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
1502#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
1503//PA_SC_FIFO_DEPTH_CNTL
1504#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
1505#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
1506//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
1507#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1508#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1509//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
1510#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1511#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1512//PA_SC_TRAP_SCREEN_HV_LOCK
1513#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1514#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1515//PA_SC_FORCE_EOV_MAX_CNTS
1516#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
1517#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
1518#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
1519#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
1520//PA_SC_BINNER_EVENT_CNTL_0
1521#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
1522#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
1523#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
1524#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
1525#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
1526#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
1527#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
1528#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
1529#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
1530#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
1531#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
1532#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
1533#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
1534#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
1535#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
1536#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
1537#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
1538#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
1539#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
1540#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
1541#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
1542#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
1543#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
1544#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
1545#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
1546#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
1547#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
1548#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
1549#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
1550#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
1551#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
1552#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
1553//PA_SC_BINNER_EVENT_CNTL_1
1554#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
1555#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
1556#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
1557#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
1558#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
1559#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
1560#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
1561#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
1562#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
1563#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
1564#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
1565#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
1566#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
1567#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
1568#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
1569#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
1570#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
1571#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
1572#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
1573#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
1574#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
1575#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
1576#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
1577#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
1578#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
1579#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
1580#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
1581#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
1582#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
1583#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
1584#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
1585#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
1586//PA_SC_BINNER_EVENT_CNTL_2
1587#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
1588#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
1589#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
1590#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
1591#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
1592#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
1593#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
1594#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
1595#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
1596#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
1597#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
1598#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
1599#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
1600#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
1601#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
1602#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
1603#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
1604#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
1605#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
1606#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
1607#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
1608#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
1609#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
1610#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
1611#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
1612#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
1613#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
1614#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
1615#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
1616#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
1617#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
1618#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
1619//PA_SC_BINNER_EVENT_CNTL_3
1620#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
1621#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
1622#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
1623#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
1624#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
1625#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
1626#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
1627#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
1628#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
1629#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
1630#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
1631#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
1632#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
1633#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
1634#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
1635#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
1636#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
1637#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
1638#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
1639#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
1640#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
1641#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
1642#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
1643#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
1644#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
1645#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
1646#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
1647#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
1648#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
1649#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
1650#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
1651#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
1652//PA_SC_BINNER_TIMEOUT_COUNTER
1653#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
1654#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
1655//PA_SC_BINNER_PERF_CNTL_0
1656#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
1657#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
1658#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
1659#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
1660#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
1661#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
1662#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
1663#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
1664//PA_SC_BINNER_PERF_CNTL_1
1665#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
1666#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
1667#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
1668#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
1669#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
1670#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
1671//PA_SC_BINNER_PERF_CNTL_2
1672#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
1673#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
1674#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
1675#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
1676//PA_SC_BINNER_PERF_CNTL_3
1677#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
1678#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
1679//PA_SC_ENHANCE_2
1680#define PA_SC_ENHANCE_2__RESERVED_0__SHIFT 0x0
1681#define PA_SC_ENHANCE_2__RESERVED_1__SHIFT 0x1
1682#define PA_SC_ENHANCE_2__RESERVED_2__SHIFT 0x2
1683#define PA_SC_ENHANCE_2__RESERVED_3__SHIFT 0x3
1684#define PA_SC_ENHANCE_2__RESERVED_4__SHIFT 0x4
1685#define PA_SC_ENHANCE_2__RESERVED_5__SHIFT 0x5
1686#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6
1687#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT 0x7
1688#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x8
1689#define PA_SC_ENHANCE_2__RESERVED_0_MASK 0x00000001L
1690#define PA_SC_ENHANCE_2__RESERVED_1_MASK 0x00000002L
1691#define PA_SC_ENHANCE_2__RESERVED_2_MASK 0x00000004L
1692#define PA_SC_ENHANCE_2__RESERVED_3_MASK 0x00000008L
1693#define PA_SC_ENHANCE_2__RESERVED_4_MASK 0x00000010L
1694#define PA_SC_ENHANCE_2__RESERVED_5_MASK 0x00000020L
1695#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L
1696#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK 0x00000080L
1697#define PA_SC_ENHANCE_2__RSVD_MASK 0xFFFFFF00L
1698//PA_SC_FIFO_SIZE
1699#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
1700#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
1701#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
1702#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
1703#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
1704#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
1705#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
1706#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
1707//PA_SC_IF_FIFO_SIZE
1708#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
1709#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
1710#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
1711#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
1712#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
1713#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
1714#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
1715#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
1716//PA_SC_PKR_WAVE_TABLE_CNTL
1717#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
1718#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
1719//PA_UTCL1_CNTL1
1720#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
1721#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
1722#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
1723#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
1724#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
1725#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
1726#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
1727#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
1728#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
1729#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
1730#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
1731#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
1732#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
1733#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
1734#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
1735#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
1736#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
1737#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
1738#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
1739#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
1740#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
1741#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
1742#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
1743#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
1744#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
1745#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
1746#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
1747#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
1748#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
1749#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
1750#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
1751#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
1752#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
1753#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
1754//PA_UTCL1_CNTL2
1755#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
1756#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
1757#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
1758#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
1759#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
1760#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
1761#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
1762#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
1763#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
1764#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
1765#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
1766#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
1767#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
1768#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
1769#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
1770#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
1771#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
1772#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
1773#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
1774#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
1775#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
1776#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
1777#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
1778#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
1779#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
1780#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
1781#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
1782#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
1783#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
1784#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
1785#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
1786#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
1787#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
1788#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
1789//PA_SIDEBAND_REQUEST_DELAYS
1790#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
1791#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
1792#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
1793#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
1794//PA_SC_ENHANCE
1795#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
1796#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
1797#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
1798#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
1799#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
1800#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
1801#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
1802#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
1803#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
1804#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
1805#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
1806#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
1807#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
1808#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
1809#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
1810#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
1811#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
1812#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
1813#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
1814#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
1815#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
1816#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
1817#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
1818#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
1819#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
1820#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
1821#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
1822#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
1823#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
1824#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
1825#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
1826#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
1827#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
1828#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
1829#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
1830#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
1831#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
1832#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
1833#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
1834#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
1835#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
1836#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
1837#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
1838#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
1839#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
1840#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
1841#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
1842#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
1843#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
1844#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
1845#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
1846#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
1847#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
1848#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
1849#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
1850#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
1851#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
1852#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
1853#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
1854#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
1855//PA_SC_ENHANCE_1
1856#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
1857#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
1858#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
1859#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
1860#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
1861#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
1862#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
1863#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
1864#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
1865#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
1866#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
1867#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc
1868#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
1869#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
1870#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
1871#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
1872#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
1873#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
1874#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
1875#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
1876#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
1877#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
1878#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17
1879#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
1880#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19
1881#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a
1882#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b
1883#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c
1884#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d
1885#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e
1886#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x1f
1887#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
1888#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
1889#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
1890#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
1891#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
1892#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
1893#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
1894#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
1895#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
1896#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
1897#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
1898#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L
1899#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
1900#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
1901#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
1902#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
1903#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
1904#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
1905#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
1906#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
1907#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
1908#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
1909#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L
1910#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
1911#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L
1912#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L
1913#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L
1914#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L
1915#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L
1916#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L
1917#define PA_SC_ENHANCE_1__RSVD_MASK 0x80000000L
1918//PA_SC_DSM_CNTL
1919#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
1920#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
1921#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
1922#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
1923//PA_SC_TILE_STEERING_CREST_OVERRIDE
1924#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
1925#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
1926#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
1927#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
1928#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
1929#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
1930
1931
1932// addressBlock: gc_sqdec
1933//SQ_CONFIG
1934#define SQ_CONFIG__UNUSED__SHIFT 0x0
1935#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
1936#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
1937#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
1938#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
1939#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
1940#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
1941#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
1942#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
1943#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
1944#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
1945#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
1946#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
1947#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
1948#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
1949#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
1950#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
1951#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
1952#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
1953#define SQ_CONFIG__UNUSED_MASK 0x0000007FL
1954#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
1955#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
1956#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L
1957#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L
1958#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
1959#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
1960#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
1961#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
1962#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
1963#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
1964#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
1965#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
1966#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
1967#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
1968#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
1969#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
1970#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
1971#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
1972//SQC_CONFIG
1973#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
1974#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
1975#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
1976#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
1977#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
1978#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
1979#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
1980#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
1981#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
1982#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
1983#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
1984#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
1985#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
1986#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
1987#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
1988#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
1989#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
1990#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
1991#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
1992#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
1993#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
1994#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
1995#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
1996#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
1997#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
1998#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
1999#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
2000#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
2001#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
2002#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
2003//LDS_CONFIG
2004#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
2005#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING__SHIFT 0x2
2006#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
2007#define LDS_CONFIG__DISABLE_RAM_CLOCK_GATING_MASK 0x00000004L
2008//SQ_RANDOM_WAVE_PRI
2009#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
2010#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
2011#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
2012#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
2013#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
2014#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
2015//SQ_REG_CREDITS
2016#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
2017#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
2018#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
2019#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
2020#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
2021#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
2022#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
2023#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
2024#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
2025#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
2026#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
2027#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
2028//SQ_FIFO_SIZES
2029#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
2030#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
2031#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
2032#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
2033#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
2034#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
2035#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
2036#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
2037//SQ_DSM_CNTL
2038#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
2039#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
2040#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
2041#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
2042#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
2043#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
2044#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
2045#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
2046#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
2047#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
2048#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
2049#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
2050#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
2051#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
2052#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
2053#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2054#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
2055#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
2056#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
2057#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
2058#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
2059#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
2060#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
2061#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
2062#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
2063#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
2064#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
2065#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
2066#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
2067#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
2068#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
2069#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2070//SQ_DSM_CNTL2
2071#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
2072#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
2073#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
2074#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
2075#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
2076#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
2077#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
2078#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
2079#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
2080#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
2081#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
2082#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
2083#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
2084#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
2085#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
2086#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2087#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
2088#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
2089#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
2090#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
2091#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
2092#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
2093//SQ_RUNTIME_CONFIG
2094#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
2095#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
2096//SH_MEM_BASES
2097#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
2098#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
2099#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
2100#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
2101//SH_MEM_CONFIG
2102#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
2103#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
2104#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
2105#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
2106#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
2107#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
2108#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
2109#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
2110//CC_GC_SHADER_RATE_CONFIG
2111#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
2112#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
2113#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
2114#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
2115#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
2116#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
2117//GC_USER_SHADER_RATE_CONFIG
2118#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
2119#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
2120#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
2121#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
2122#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
2123#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
2124//SQ_INTERRUPT_AUTO_MASK
2125#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
2126#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
2127//SQ_INTERRUPT_MSG_CTRL
2128#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
2129#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
2130//SQ_UTCL1_CNTL1
2131#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
2132#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
2133#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
2134#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
2135#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
2136#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
2137#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
2138#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
2139#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
2140#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
2141#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
2142#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
2143#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
2144#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
2145#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
2146#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
2147#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
2148#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
2149#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
2150#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
2151#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
2152#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
2153#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
2154#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
2155#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
2156#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
2157#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
2158#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
2159#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
2160#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
2161#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
2162#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
2163#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
2164#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
2165//SQ_UTCL1_CNTL2
2166#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
2167#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
2168#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
2169#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
2170#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
2171#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
2172#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
2173#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
2174#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
2175#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
2176#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
2177#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
2178#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
2179#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
2180#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
2181#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
2182#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
2183#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
2184#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
2185#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
2186#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
2187#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
2188//SQ_UTCL1_STATUS
2189#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
2190#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
2191#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
2192#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
2193#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
2194#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
2195#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
2196#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
2197#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
2198#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
2199//SQ_SHADER_TBA_LO
2200#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
2201#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
2202//SQ_SHADER_TBA_HI
2203#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
2204#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
2205//SQ_SHADER_TMA_LO
2206#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
2207#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
2208//SQ_SHADER_TMA_HI
2209#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
2210#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
2211//SQC_DSM_CNTL
2212#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
2213#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
2214#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
2215#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
2216#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2217#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2218#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
2219#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
2220#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
2221#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
2222#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
2223#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
2224#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2225#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2226#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
2227#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2228#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
2229#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2230#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2231#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2232#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
2233#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2234#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
2235#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2236#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
2237#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2238#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2239#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2240//SQC_DSM_CNTLA
2241#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
2242#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
2243#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
2244#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
2245#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2246#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2247#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
2248#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
2249#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
2250#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
2251#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
2252#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
2253#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2254#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2255#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
2256#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
2257#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
2258#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2259#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
2260#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2261#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
2262#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2263#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2264#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2265#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
2266#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2267#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
2268#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2269#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
2270#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2271#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2272#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2273#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
2274#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
2275#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
2276#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2277//SQC_DSM_CNTLB
2278#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
2279#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
2280#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
2281#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
2282#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2283#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2284#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
2285#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
2286#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
2287#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
2288#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
2289#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
2290#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2291#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2292#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
2293#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
2294#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
2295#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2296#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
2297#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2298#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
2299#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2300#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2301#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2302#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
2303#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2304#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
2305#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2306#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
2307#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2308#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2309#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2310#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
2311#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
2312#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
2313#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2314//SQC_DSM_CNTL2
2315#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
2316#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
2317#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
2318#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
2319#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2320#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2321#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
2322#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
2323#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
2324#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
2325#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
2326#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
2327#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2328#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2329#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
2330#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
2331#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
2332#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
2333#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
2334#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2335#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2336#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
2337#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
2338#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
2339#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
2340#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
2341#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
2342#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2343#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2344#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
2345//SQC_DSM_CNTL2A
2346#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
2347#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
2348#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
2349#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
2350#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2351#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2352#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
2353#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
2354#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
2355#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
2356#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
2357#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
2358#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2359#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2360#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
2361#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
2362#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
2363#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
2364#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
2365#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
2366#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
2367#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
2368#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2369#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2370#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
2371#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
2372#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
2373#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
2374#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
2375#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
2376#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2377#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2378#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
2379#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
2380#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
2381#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
2382//SQC_DSM_CNTL2B
2383#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
2384#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
2385#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
2386#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
2387#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2388#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2389#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
2390#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
2391#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
2392#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
2393#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
2394#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
2395#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2396#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2397#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
2398#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
2399#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
2400#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
2401#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
2402#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
2403#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
2404#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
2405#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2406#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2407#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
2408#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
2409#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
2410#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
2411#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
2412#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
2413#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2414#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2415#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
2416#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
2417#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
2418#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
2419//SQ_REG_TIMESTAMP
2420#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
2421#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
2422//SQ_CMD_TIMESTAMP
2423#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
2424#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
2425//SQ_IND_INDEX
2426#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
2427#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
2428#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
2429#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
2430#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
2431#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
2432#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
2433#define SQ_IND_INDEX__INDEX__SHIFT 0x10
2434#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
2435#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
2436#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
2437#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
2438#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
2439#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
2440#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
2441#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
2442//SQ_IND_DATA
2443#define SQ_IND_DATA__DATA__SHIFT 0x0
2444#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
2445//SQ_CMD
2446#define SQ_CMD__CMD__SHIFT 0x0
2447#define SQ_CMD__MODE__SHIFT 0x4
2448#define SQ_CMD__CHECK_VMID__SHIFT 0x7
2449#define SQ_CMD__DATA__SHIFT 0x8
2450#define SQ_CMD__WAVE_ID__SHIFT 0x10
2451#define SQ_CMD__SIMD_ID__SHIFT 0x14
2452#define SQ_CMD__QUEUE_ID__SHIFT 0x18
2453#define SQ_CMD__VM_ID__SHIFT 0x1c
2454#define SQ_CMD__CMD_MASK 0x00000007L
2455#define SQ_CMD__MODE_MASK 0x00000070L
2456#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
2457#define SQ_CMD__DATA_MASK 0x00000F00L
2458#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
2459#define SQ_CMD__SIMD_ID_MASK 0x00300000L
2460#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
2461#define SQ_CMD__VM_ID_MASK 0xF0000000L
2462//SQ_TIME_HI
2463#define SQ_TIME_HI__TIME__SHIFT 0x0
2464#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
2465//SQ_TIME_LO
2466#define SQ_TIME_LO__TIME__SHIFT 0x0
2467#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
2468//SQ_DS_0
2469#define SQ_DS_0__OFFSET0__SHIFT 0x0
2470#define SQ_DS_0__OFFSET1__SHIFT 0x8
2471#define SQ_DS_0__GDS__SHIFT 0x10
2472#define SQ_DS_0__OP__SHIFT 0x11
2473#define SQ_DS_0__ENCODING__SHIFT 0x1a
2474#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
2475#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
2476#define SQ_DS_0__GDS_MASK 0x00010000L
2477#define SQ_DS_0__OP_MASK 0x01FE0000L
2478#define SQ_DS_0__ENCODING_MASK 0xFC000000L
2479//SQ_DS_1
2480#define SQ_DS_1__ADDR__SHIFT 0x0
2481#define SQ_DS_1__DATA0__SHIFT 0x8
2482#define SQ_DS_1__DATA1__SHIFT 0x10
2483#define SQ_DS_1__VDST__SHIFT 0x18
2484#define SQ_DS_1__ADDR_MASK 0x000000FFL
2485#define SQ_DS_1__DATA0_MASK 0x0000FF00L
2486#define SQ_DS_1__DATA1_MASK 0x00FF0000L
2487#define SQ_DS_1__VDST_MASK 0xFF000000L
2488//SQ_EXP_0
2489#define SQ_EXP_0__EN__SHIFT 0x0
2490#define SQ_EXP_0__TGT__SHIFT 0x4
2491#define SQ_EXP_0__COMPR__SHIFT 0xa
2492#define SQ_EXP_0__DONE__SHIFT 0xb
2493#define SQ_EXP_0__VM__SHIFT 0xc
2494#define SQ_EXP_0__ENCODING__SHIFT 0x1a
2495#define SQ_EXP_0__EN_MASK 0x0000000FL
2496#define SQ_EXP_0__TGT_MASK 0x000003F0L
2497#define SQ_EXP_0__COMPR_MASK 0x00000400L
2498#define SQ_EXP_0__DONE_MASK 0x00000800L
2499#define SQ_EXP_0__VM_MASK 0x00001000L
2500#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
2501//SQ_EXP_1
2502#define SQ_EXP_1__VSRC0__SHIFT 0x0
2503#define SQ_EXP_1__VSRC1__SHIFT 0x8
2504#define SQ_EXP_1__VSRC2__SHIFT 0x10
2505#define SQ_EXP_1__VSRC3__SHIFT 0x18
2506#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
2507#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
2508#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
2509#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
2510//SQ_FLAT_0
2511#define SQ_FLAT_0__OFFSET__SHIFT 0x0
2512#define SQ_FLAT_0__LDS__SHIFT 0xd
2513#define SQ_FLAT_0__SEG__SHIFT 0xe
2514#define SQ_FLAT_0__GLC__SHIFT 0x10
2515#define SQ_FLAT_0__SLC__SHIFT 0x11
2516#define SQ_FLAT_0__OP__SHIFT 0x12
2517#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
2518#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
2519#define SQ_FLAT_0__LDS_MASK 0x00002000L
2520#define SQ_FLAT_0__SEG_MASK 0x0000C000L
2521#define SQ_FLAT_0__GLC_MASK 0x00010000L
2522#define SQ_FLAT_0__SLC_MASK 0x00020000L
2523#define SQ_FLAT_0__OP_MASK 0x01FC0000L
2524#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
2525//SQ_FLAT_1
2526#define SQ_FLAT_1__ADDR__SHIFT 0x0
2527#define SQ_FLAT_1__DATA__SHIFT 0x8
2528#define SQ_FLAT_1__SADDR__SHIFT 0x10
2529#define SQ_FLAT_1__NV__SHIFT 0x17
2530#define SQ_FLAT_1__VDST__SHIFT 0x18
2531#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
2532#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
2533#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
2534#define SQ_FLAT_1__NV_MASK 0x00800000L
2535#define SQ_FLAT_1__VDST_MASK 0xFF000000L
2536//SQ_GLBL_0
2537#define SQ_GLBL_0__OFFSET__SHIFT 0x0
2538#define SQ_GLBL_0__LDS__SHIFT 0xd
2539#define SQ_GLBL_0__SEG__SHIFT 0xe
2540#define SQ_GLBL_0__GLC__SHIFT 0x10
2541#define SQ_GLBL_0__SLC__SHIFT 0x11
2542#define SQ_GLBL_0__OP__SHIFT 0x12
2543#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
2544#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
2545#define SQ_GLBL_0__LDS_MASK 0x00002000L
2546#define SQ_GLBL_0__SEG_MASK 0x0000C000L
2547#define SQ_GLBL_0__GLC_MASK 0x00010000L
2548#define SQ_GLBL_0__SLC_MASK 0x00020000L
2549#define SQ_GLBL_0__OP_MASK 0x01FC0000L
2550#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
2551//SQ_GLBL_1
2552#define SQ_GLBL_1__ADDR__SHIFT 0x0
2553#define SQ_GLBL_1__DATA__SHIFT 0x8
2554#define SQ_GLBL_1__SADDR__SHIFT 0x10
2555#define SQ_GLBL_1__NV__SHIFT 0x17
2556#define SQ_GLBL_1__VDST__SHIFT 0x18
2557#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
2558#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
2559#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
2560#define SQ_GLBL_1__NV_MASK 0x00800000L
2561#define SQ_GLBL_1__VDST_MASK 0xFF000000L
2562//SQ_INST
2563#define SQ_INST__ENCODING__SHIFT 0x0
2564#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
2565//SQ_MIMG_0
2566#define SQ_MIMG_0__OPM__SHIFT 0x0
2567#define SQ_MIMG_0__DMASK__SHIFT 0x8
2568#define SQ_MIMG_0__UNORM__SHIFT 0xc
2569#define SQ_MIMG_0__GLC__SHIFT 0xd
2570#define SQ_MIMG_0__DA__SHIFT 0xe
2571#define SQ_MIMG_0__A16__SHIFT 0xf
2572#define SQ_MIMG_0__TFE__SHIFT 0x10
2573#define SQ_MIMG_0__LWE__SHIFT 0x11
2574#define SQ_MIMG_0__OP__SHIFT 0x12
2575#define SQ_MIMG_0__SLC__SHIFT 0x19
2576#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
2577#define SQ_MIMG_0__OPM_MASK 0x00000001L
2578#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
2579#define SQ_MIMG_0__UNORM_MASK 0x00001000L
2580#define SQ_MIMG_0__GLC_MASK 0x00002000L
2581#define SQ_MIMG_0__DA_MASK 0x00004000L
2582#define SQ_MIMG_0__A16_MASK 0x00008000L
2583#define SQ_MIMG_0__TFE_MASK 0x00010000L
2584#define SQ_MIMG_0__LWE_MASK 0x00020000L
2585#define SQ_MIMG_0__OP_MASK 0x01FC0000L
2586#define SQ_MIMG_0__SLC_MASK 0x02000000L
2587#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
2588//SQ_MIMG_1
2589#define SQ_MIMG_1__VADDR__SHIFT 0x0
2590#define SQ_MIMG_1__VDATA__SHIFT 0x8
2591#define SQ_MIMG_1__SRSRC__SHIFT 0x10
2592#define SQ_MIMG_1__SSAMP__SHIFT 0x15
2593#define SQ_MIMG_1__D16__SHIFT 0x1f
2594#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
2595#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
2596#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
2597#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
2598#define SQ_MIMG_1__D16_MASK 0x80000000L
2599//SQ_MTBUF_0
2600#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
2601#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
2602#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
2603#define SQ_MTBUF_0__GLC__SHIFT 0xe
2604#define SQ_MTBUF_0__OP__SHIFT 0xf
2605#define SQ_MTBUF_0__DFMT__SHIFT 0x13
2606#define SQ_MTBUF_0__NFMT__SHIFT 0x17
2607#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
2608#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
2609#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
2610#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
2611#define SQ_MTBUF_0__GLC_MASK 0x00004000L
2612#define SQ_MTBUF_0__OP_MASK 0x00078000L
2613#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
2614#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
2615#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
2616//SQ_MTBUF_1
2617#define SQ_MTBUF_1__VADDR__SHIFT 0x0
2618#define SQ_MTBUF_1__VDATA__SHIFT 0x8
2619#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
2620#define SQ_MTBUF_1__SLC__SHIFT 0x16
2621#define SQ_MTBUF_1__TFE__SHIFT 0x17
2622#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
2623#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
2624#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
2625#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
2626#define SQ_MTBUF_1__SLC_MASK 0x00400000L
2627#define SQ_MTBUF_1__TFE_MASK 0x00800000L
2628#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
2629//SQ_MUBUF_0
2630#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
2631#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
2632#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
2633#define SQ_MUBUF_0__GLC__SHIFT 0xe
2634#define SQ_MUBUF_0__LDS__SHIFT 0x10
2635#define SQ_MUBUF_0__SLC__SHIFT 0x11
2636#define SQ_MUBUF_0__OP__SHIFT 0x12
2637#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
2638#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
2639#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
2640#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
2641#define SQ_MUBUF_0__GLC_MASK 0x00004000L
2642#define SQ_MUBUF_0__LDS_MASK 0x00010000L
2643#define SQ_MUBUF_0__SLC_MASK 0x00020000L
2644#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
2645#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
2646//SQ_MUBUF_1
2647#define SQ_MUBUF_1__VADDR__SHIFT 0x0
2648#define SQ_MUBUF_1__VDATA__SHIFT 0x8
2649#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
2650#define SQ_MUBUF_1__TFE__SHIFT 0x17
2651#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
2652#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
2653#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
2654#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
2655#define SQ_MUBUF_1__TFE_MASK 0x00800000L
2656#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
2657//SQ_SCRATCH_0
2658#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
2659#define SQ_SCRATCH_0__LDS__SHIFT 0xd
2660#define SQ_SCRATCH_0__SEG__SHIFT 0xe
2661#define SQ_SCRATCH_0__GLC__SHIFT 0x10
2662#define SQ_SCRATCH_0__SLC__SHIFT 0x11
2663#define SQ_SCRATCH_0__OP__SHIFT 0x12
2664#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
2665#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
2666#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
2667#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
2668#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
2669#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
2670#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
2671#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
2672//SQ_SCRATCH_1
2673#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
2674#define SQ_SCRATCH_1__DATA__SHIFT 0x8
2675#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
2676#define SQ_SCRATCH_1__NV__SHIFT 0x17
2677#define SQ_SCRATCH_1__VDST__SHIFT 0x18
2678#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
2679#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
2680#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
2681#define SQ_SCRATCH_1__NV_MASK 0x00800000L
2682#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
2683//SQ_SMEM_0
2684#define SQ_SMEM_0__SBASE__SHIFT 0x0
2685#define SQ_SMEM_0__SDATA__SHIFT 0x6
2686#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
2687#define SQ_SMEM_0__NV__SHIFT 0xf
2688#define SQ_SMEM_0__GLC__SHIFT 0x10
2689#define SQ_SMEM_0__IMM__SHIFT 0x11
2690#define SQ_SMEM_0__OP__SHIFT 0x12
2691#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
2692#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
2693#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
2694#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
2695#define SQ_SMEM_0__NV_MASK 0x00008000L
2696#define SQ_SMEM_0__GLC_MASK 0x00010000L
2697#define SQ_SMEM_0__IMM_MASK 0x00020000L
2698#define SQ_SMEM_0__OP_MASK 0x03FC0000L
2699#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
2700//SQ_SMEM_1
2701#define SQ_SMEM_1__OFFSET__SHIFT 0x0
2702#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
2703#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
2704#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
2705//SQ_SOP1
2706#define SQ_SOP1__SSRC0__SHIFT 0x0
2707#define SQ_SOP1__OP__SHIFT 0x8
2708#define SQ_SOP1__SDST__SHIFT 0x10
2709#define SQ_SOP1__ENCODING__SHIFT 0x17
2710#define SQ_SOP1__SSRC0_MASK 0x000000FFL
2711#define SQ_SOP1__OP_MASK 0x0000FF00L
2712#define SQ_SOP1__SDST_MASK 0x007F0000L
2713#define SQ_SOP1__ENCODING_MASK 0xFF800000L
2714//SQ_SOP2
2715#define SQ_SOP2__SSRC0__SHIFT 0x0
2716#define SQ_SOP2__SSRC1__SHIFT 0x8
2717#define SQ_SOP2__SDST__SHIFT 0x10
2718#define SQ_SOP2__OP__SHIFT 0x17
2719#define SQ_SOP2__ENCODING__SHIFT 0x1e
2720#define SQ_SOP2__SSRC0_MASK 0x000000FFL
2721#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
2722#define SQ_SOP2__SDST_MASK 0x007F0000L
2723#define SQ_SOP2__OP_MASK 0x3F800000L
2724#define SQ_SOP2__ENCODING_MASK 0xC0000000L
2725//SQ_SOPC
2726#define SQ_SOPC__SSRC0__SHIFT 0x0
2727#define SQ_SOPC__SSRC1__SHIFT 0x8
2728#define SQ_SOPC__OP__SHIFT 0x10
2729#define SQ_SOPC__ENCODING__SHIFT 0x17
2730#define SQ_SOPC__SSRC0_MASK 0x000000FFL
2731#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
2732#define SQ_SOPC__OP_MASK 0x007F0000L
2733#define SQ_SOPC__ENCODING_MASK 0xFF800000L
2734//SQ_SOPK
2735#define SQ_SOPK__SIMM16__SHIFT 0x0
2736#define SQ_SOPK__SDST__SHIFT 0x10
2737#define SQ_SOPK__OP__SHIFT 0x17
2738#define SQ_SOPK__ENCODING__SHIFT 0x1c
2739#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
2740#define SQ_SOPK__SDST_MASK 0x007F0000L
2741#define SQ_SOPK__OP_MASK 0x0F800000L
2742#define SQ_SOPK__ENCODING_MASK 0xF0000000L
2743//SQ_SOPP
2744#define SQ_SOPP__SIMM16__SHIFT 0x0
2745#define SQ_SOPP__OP__SHIFT 0x10
2746#define SQ_SOPP__ENCODING__SHIFT 0x17
2747#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
2748#define SQ_SOPP__OP_MASK 0x007F0000L
2749#define SQ_SOPP__ENCODING_MASK 0xFF800000L
2750//SQ_VINTRP
2751#define SQ_VINTRP__VSRC__SHIFT 0x0
2752#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
2753#define SQ_VINTRP__ATTR__SHIFT 0xa
2754#define SQ_VINTRP__OP__SHIFT 0x10
2755#define SQ_VINTRP__VDST__SHIFT 0x12
2756#define SQ_VINTRP__ENCODING__SHIFT 0x1a
2757#define SQ_VINTRP__VSRC_MASK 0x000000FFL
2758#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
2759#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
2760#define SQ_VINTRP__OP_MASK 0x00030000L
2761#define SQ_VINTRP__VDST_MASK 0x03FC0000L
2762#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
2763//SQ_VOP1
2764#define SQ_VOP1__SRC0__SHIFT 0x0
2765#define SQ_VOP1__OP__SHIFT 0x9
2766#define SQ_VOP1__VDST__SHIFT 0x11
2767#define SQ_VOP1__ENCODING__SHIFT 0x19
2768#define SQ_VOP1__SRC0_MASK 0x000001FFL
2769#define SQ_VOP1__OP_MASK 0x0001FE00L
2770#define SQ_VOP1__VDST_MASK 0x01FE0000L
2771#define SQ_VOP1__ENCODING_MASK 0xFE000000L
2772//SQ_VOP2
2773#define SQ_VOP2__SRC0__SHIFT 0x0
2774#define SQ_VOP2__VSRC1__SHIFT 0x9
2775#define SQ_VOP2__VDST__SHIFT 0x11
2776#define SQ_VOP2__OP__SHIFT 0x19
2777#define SQ_VOP2__ENCODING__SHIFT 0x1f
2778#define SQ_VOP2__SRC0_MASK 0x000001FFL
2779#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
2780#define SQ_VOP2__VDST_MASK 0x01FE0000L
2781#define SQ_VOP2__OP_MASK 0x7E000000L
2782#define SQ_VOP2__ENCODING_MASK 0x80000000L
2783//SQ_VOP3P_0
2784#define SQ_VOP3P_0__VDST__SHIFT 0x0
2785#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
2786#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
2787#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
2788#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
2789#define SQ_VOP3P_0__OP__SHIFT 0x10
2790#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
2791#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
2792#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
2793#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
2794#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
2795#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
2796#define SQ_VOP3P_0__OP_MASK 0x007F0000L
2797#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
2798//SQ_VOP3P_1
2799#define SQ_VOP3P_1__SRC0__SHIFT 0x0
2800#define SQ_VOP3P_1__SRC1__SHIFT 0x9
2801#define SQ_VOP3P_1__SRC2__SHIFT 0x12
2802#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
2803#define SQ_VOP3P_1__NEG__SHIFT 0x1d
2804#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
2805#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
2806#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
2807#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
2808#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
2809//SQ_VOP3_0
2810#define SQ_VOP3_0__VDST__SHIFT 0x0
2811#define SQ_VOP3_0__ABS__SHIFT 0x8
2812#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
2813#define SQ_VOP3_0__CLAMP__SHIFT 0xf
2814#define SQ_VOP3_0__OP__SHIFT 0x10
2815#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
2816#define SQ_VOP3_0__VDST_MASK 0x000000FFL
2817#define SQ_VOP3_0__ABS_MASK 0x00000700L
2818#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
2819#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
2820#define SQ_VOP3_0__OP_MASK 0x03FF0000L
2821#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
2822//SQ_VOP3_0_SDST_ENC
2823#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
2824#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
2825#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
2826#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
2827#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
2828#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
2829#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
2830#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
2831#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
2832#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
2833//SQ_VOP3_1
2834#define SQ_VOP3_1__SRC0__SHIFT 0x0
2835#define SQ_VOP3_1__SRC1__SHIFT 0x9
2836#define SQ_VOP3_1__SRC2__SHIFT 0x12
2837#define SQ_VOP3_1__OMOD__SHIFT 0x1b
2838#define SQ_VOP3_1__NEG__SHIFT 0x1d
2839#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
2840#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
2841#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
2842#define SQ_VOP3_1__OMOD_MASK 0x18000000L
2843#define SQ_VOP3_1__NEG_MASK 0xE0000000L
2844//SQ_VOPC
2845#define SQ_VOPC__SRC0__SHIFT 0x0
2846#define SQ_VOPC__VSRC1__SHIFT 0x9
2847#define SQ_VOPC__OP__SHIFT 0x11
2848#define SQ_VOPC__ENCODING__SHIFT 0x19
2849#define SQ_VOPC__SRC0_MASK 0x000001FFL
2850#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
2851#define SQ_VOPC__OP_MASK 0x01FE0000L
2852#define SQ_VOPC__ENCODING_MASK 0xFE000000L
2853//SQ_VOP_DPP
2854#define SQ_VOP_DPP__SRC0__SHIFT 0x0
2855#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
2856#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
2857#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
2858#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
2859#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
2860#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
2861#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
2862#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
2863#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
2864#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
2865#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
2866#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
2867#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
2868#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
2869#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
2870#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
2871#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
2872//SQ_VOP_SDWA
2873#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
2874#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
2875#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
2876#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
2877#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
2878#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
2879#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
2880#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
2881#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
2882#define SQ_VOP_SDWA__S0__SHIFT 0x17
2883#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
2884#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
2885#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
2886#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
2887#define SQ_VOP_SDWA__S1__SHIFT 0x1f
2888#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
2889#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
2890#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
2891#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
2892#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
2893#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
2894#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
2895#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
2896#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
2897#define SQ_VOP_SDWA__S0_MASK 0x00800000L
2898#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
2899#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
2900#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
2901#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
2902#define SQ_VOP_SDWA__S1_MASK 0x80000000L
2903//SQ_VOP_SDWA_SDST_ENC
2904#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
2905#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
2906#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
2907#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
2908#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
2909#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
2910#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
2911#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
2912#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
2913#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
2914#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
2915#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
2916#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
2917#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
2918#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
2919#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
2920#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
2921#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
2922#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
2923#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
2924#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
2925#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
2926#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
2927#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
2928#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
2929#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
2930//SQ_LB_CTR_CTRL
2931#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
2932#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
2933#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
2934#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
2935#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
2936#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
2937//SQ_LB_DATA0
2938#define SQ_LB_DATA0__DATA__SHIFT 0x0
2939#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
2940//SQ_LB_DATA1
2941#define SQ_LB_DATA1__DATA__SHIFT 0x0
2942#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
2943//SQ_LB_DATA2
2944#define SQ_LB_DATA2__DATA__SHIFT 0x0
2945#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
2946//SQ_LB_DATA3
2947#define SQ_LB_DATA3__DATA__SHIFT 0x0
2948#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
2949//SQ_LB_CTR_SEL
2950#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
2951#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
2952#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
2953#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
2954#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
2955#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
2956#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
2957#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
2958//SQ_LB_CTR0_CU
2959#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
2960#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
2961#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
2962#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
2963//SQ_LB_CTR1_CU
2964#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
2965#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
2966#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
2967#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
2968//SQ_LB_CTR2_CU
2969#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
2970#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
2971#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
2972#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
2973//SQ_LB_CTR3_CU
2974#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
2975#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
2976#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
2977#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
2978//SQ_THREAD_TRACE_WORD_CMN
2979#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
2980#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
2981#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
2982#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
2983//SQ_THREAD_TRACE_WORD_EVENT
2984#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
2985#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
2986#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
2987#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
2988#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
2989#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
2990#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
2991#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
2992#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
2993#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
2994//SQ_THREAD_TRACE_WORD_INST
2995#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
2996#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
2997#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
2998#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
2999#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
3000#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
3001#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
3002#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
3003#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
3004#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
3005//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
3006#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3007#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
3008#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
3009#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
3010#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
3011#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
3012#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3013#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
3014#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
3015#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
3016#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
3017#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
3018//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
3019#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3020#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
3021#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
3022#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
3023#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
3024#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
3025#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
3026#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3027#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
3028#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
3029#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
3030#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
3031#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
3032#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
3033//SQ_THREAD_TRACE_WORD_ISSUE
3034#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
3035#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
3036#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
3037#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
3038#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
3039#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
3040#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
3041#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
3042#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
3043#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
3044#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
3045#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
3046#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
3047#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
3048#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
3049#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
3050#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
3051#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
3052#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
3053#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
3054#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
3055#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
3056#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
3057#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
3058#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
3059#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
3060//SQ_THREAD_TRACE_WORD_MISC
3061#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
3062#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
3063#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
3064#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
3065#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
3066#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
3067#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
3068#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
3069//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
3070#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3071#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
3072#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
3073#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
3074#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
3075#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
3076#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
3077#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3078#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
3079#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
3080#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
3081#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
3082#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
3083#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
3084//SQ_THREAD_TRACE_WORD_REG_1_OF_2
3085#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3086#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
3087#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
3088#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
3089#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
3090#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
3091#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
3092#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
3093#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
3094#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3095#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
3096#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
3097#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
3098#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
3099#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
3100#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
3101#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
3102#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
3103//SQ_THREAD_TRACE_WORD_REG_2_OF_2
3104#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
3105#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
3106//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
3107#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3108#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
3109#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
3110#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
3111#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
3112#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
3113#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3114#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
3115#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
3116#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
3117#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
3118#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
3119//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
3120#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
3121#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
3122//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
3123#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3124#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
3125#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3126#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
3127//SQ_THREAD_TRACE_WORD_WAVE
3128#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
3129#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
3130#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
3131#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
3132#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
3133#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
3134#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
3135#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
3136#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
3137#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
3138#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
3139#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
3140//SQ_THREAD_TRACE_WORD_WAVE_START
3141#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
3142#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
3143#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
3144#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
3145#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
3146#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
3147#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
3148#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
3149#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
3150#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
3151#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
3152#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
3153#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
3154#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
3155#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
3156#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
3157#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
3158#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
3159#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
3160#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
3161//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
3162#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
3163#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
3164//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
3165#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
3166#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
3167//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
3168#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
3169#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
3170#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
3171#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
3172#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
3173#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
3174//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
3175#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
3176#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
3177//SQ_WREXEC_EXEC_HI
3178#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
3179#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
3180#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
3181#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
3182#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
3183#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
3184#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
3185#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
3186#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
3187#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
3188//SQ_WREXEC_EXEC_LO
3189#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
3190#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
3191//SQ_BUF_RSRC_WORD0
3192#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
3193#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
3194//SQ_BUF_RSRC_WORD1
3195#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
3196#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
3197#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
3198#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
3199#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
3200#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
3201#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
3202#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
3203//SQ_BUF_RSRC_WORD2
3204#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
3205#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
3206//SQ_BUF_RSRC_WORD3
3207#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
3208#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
3209#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
3210#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
3211#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
3212#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
3213#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
3214#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
3215#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
3216#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
3217#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
3218#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
3219#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
3220#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
3221#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
3222#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
3223#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
3224#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
3225#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
3226#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
3227#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
3228#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
3229#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
3230#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
3231//SQ_IMG_RSRC_WORD0
3232#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
3233#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
3234//SQ_IMG_RSRC_WORD1
3235#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
3236#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
3237#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
3238#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
3239#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
3240#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
3241#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
3242#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
3243#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
3244#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
3245#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
3246#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
3247//SQ_IMG_RSRC_WORD2
3248#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
3249#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
3250#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
3251#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
3252#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
3253#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
3254//SQ_IMG_RSRC_WORD3
3255#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
3256#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
3257#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
3258#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
3259#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
3260#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
3261#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
3262#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
3263#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
3264#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
3265#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
3266#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
3267#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
3268#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
3269#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
3270#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
3271//SQ_IMG_RSRC_WORD4
3272#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
3273#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
3274#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
3275#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
3276#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
3277#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
3278//SQ_IMG_RSRC_WORD5
3279#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
3280#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
3281#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
3282#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
3283#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
3284#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
3285#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
3286#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
3287#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
3288#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
3289#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
3290#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
3291#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
3292#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
3293//SQ_IMG_RSRC_WORD6
3294#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
3295#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
3296#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
3297#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
3298#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
3299#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
3300#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
3301#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
3302#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
3303#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
3304#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
3305#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
3306#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
3307#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
3308#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
3309#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
3310//SQ_IMG_RSRC_WORD7
3311#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
3312#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
3313//SQ_IMG_SAMP_WORD0
3314#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
3315#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
3316#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
3317#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
3318#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
3319#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
3320#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
3321#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
3322#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
3323#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
3324#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
3325#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
3326#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
3327#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
3328#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
3329#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
3330#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
3331#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
3332#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
3333#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
3334#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
3335#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
3336#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
3337#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
3338#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
3339#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
3340#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
3341#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
3342//SQ_IMG_SAMP_WORD1
3343#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
3344#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
3345#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
3346#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
3347#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
3348#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
3349#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
3350#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
3351//SQ_IMG_SAMP_WORD2
3352#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
3353#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
3354#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
3355#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
3356#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
3357#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
3358#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
3359#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
3360#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
3361#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
3362#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
3363#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
3364#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
3365#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
3366#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
3367#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
3368#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
3369#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
3370#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
3371#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
3372//SQ_IMG_SAMP_WORD3
3373#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
3374#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
3375#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
3376#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
3377#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
3378#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
3379//SQ_FLAT_SCRATCH_WORD0
3380#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
3381#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
3382//SQ_FLAT_SCRATCH_WORD1
3383#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
3384#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
3385//SQ_M0_GPR_IDX_WORD
3386#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
3387#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
3388#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
3389#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
3390#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
3391#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
3392#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
3393#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
3394#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
3395#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
3396//SQC_ICACHE_UTCL1_CNTL1
3397#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
3398#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
3399#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
3400#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
3401#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
3402#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
3403#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
3404#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
3405#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
3406#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
3407#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
3408#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
3409#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
3410#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
3411#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
3412#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
3413#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
3414#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
3415#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
3416#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
3417#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
3418#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
3419#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
3420#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
3421#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
3422#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
3423#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
3424#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
3425#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
3426#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
3427#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
3428#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
3429//SQC_ICACHE_UTCL1_CNTL2
3430#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
3431#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
3432#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
3433#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3434#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
3435#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
3436#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
3437#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
3438#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
3439#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
3440#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
3441#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
3442#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
3443#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
3444#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
3445#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
3446#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
3447#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
3448#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
3449#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
3450#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
3451#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
3452#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
3453#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
3454#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
3455#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
3456#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
3457#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
3458//SQC_DCACHE_UTCL1_CNTL1
3459#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
3460#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
3461#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
3462#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
3463#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
3464#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
3465#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
3466#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
3467#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
3468#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
3469#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
3470#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
3471#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
3472#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
3473#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
3474#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
3475#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
3476#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
3477#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
3478#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
3479#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
3480#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
3481#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
3482#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
3483#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
3484#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
3485#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
3486#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
3487#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
3488#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
3489#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
3490#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
3491//SQC_DCACHE_UTCL1_CNTL2
3492#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
3493#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
3494#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
3495#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3496#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
3497#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
3498#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
3499#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
3500#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
3501#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
3502#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
3503#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
3504#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
3505#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
3506#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
3507#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
3508#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
3509#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
3510#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
3511#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
3512#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
3513#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
3514#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
3515#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
3516#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
3517#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
3518#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
3519#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
3520//SQC_ICACHE_UTCL1_STATUS
3521#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
3522#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
3523#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
3524#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
3525#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
3526#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
3527//SQC_DCACHE_UTCL1_STATUS
3528#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
3529#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
3530#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
3531#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
3532#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
3533#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
3534
3535
3536// addressBlock: gc_shsdec
3537//SX_DEBUG_1
3538#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
3539#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
3540#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
3541#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
3542#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
3543#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
3544#define SX_DEBUG_1__DISABLE_SX_DB_FGCG__SHIFT 0xd
3545#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
3546#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
3547#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
3548#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
3549#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
3550#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
3551#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
3552#define SX_DEBUG_1__DISABLE_SX_DB_FGCG_MASK 0x00002000L
3553#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
3554//SPI_PS_MAX_WAVE_ID
3555#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
3556#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
3557#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
3558#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
3559//SPI_START_PHASE
3560#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
3561#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
3562#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
3563#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
3564#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
3565#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
3566//SPI_GFX_CNTL
3567#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
3568#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
3569//SPI_DSM_CNTL
3570#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
3571#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
3572#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
3573#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
3574#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
3575#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
3576//SPI_DSM_CNTL2
3577#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
3578#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
3579#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
3580#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
3581#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
3582#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
3583#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
3584#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
3585//SPI_DEBUG_BUSY
3586#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0
3587#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1
3588#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x2
3589#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x3
3590#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x4
3591#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x5
3592#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x6
3593#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x7
3594#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0x8
3595#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0x9
3596#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xa
3597#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xb
3598#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xc
3599#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xd
3600#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0xe
3601#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0xf
3602#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x10
3603#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x11
3604#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12
3605#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x13
3606#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x14
3607#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x15
3608#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L
3609#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L
3610#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000004L
3611#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000008L
3612#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000010L
3613#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000020L
3614#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000040L
3615#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000080L
3616#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000100L
3617#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000200L
3618#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00000400L
3619#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00000800L
3620#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00001000L
3621#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00002000L
3622#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00004000L
3623#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00008000L
3624#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00010000L
3625#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00020000L
3626#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L
3627#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00080000L
3628#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00100000L
3629#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00200000L
3630//SPI_CONFIG_PS_CU_EN
3631#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
3632#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
3633#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
3634#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
3635#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
3636#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
3637//SPI_WF_LIFETIME_CNTL
3638#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
3639#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
3640#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
3641#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
3642//SPI_WF_LIFETIME_LIMIT_0
3643#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
3644#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
3645#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
3646#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
3647//SPI_WF_LIFETIME_LIMIT_1
3648#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
3649#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
3650#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
3651#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
3652//SPI_WF_LIFETIME_LIMIT_2
3653#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
3654#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
3655#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
3656#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
3657//SPI_WF_LIFETIME_LIMIT_3
3658#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
3659#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
3660#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
3661#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
3662//SPI_WF_LIFETIME_LIMIT_4
3663#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
3664#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
3665#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
3666#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
3667//SPI_WF_LIFETIME_LIMIT_5
3668#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
3669#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
3670#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
3671#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
3672//SPI_WF_LIFETIME_LIMIT_6
3673#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
3674#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
3675#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
3676#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
3677//SPI_WF_LIFETIME_LIMIT_7
3678#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
3679#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
3680#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
3681#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
3682//SPI_WF_LIFETIME_LIMIT_8
3683#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
3684#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
3685#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
3686#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
3687//SPI_WF_LIFETIME_LIMIT_9
3688#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
3689#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
3690#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
3691#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
3692//SPI_WF_LIFETIME_STATUS_0
3693#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
3694#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
3695#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
3696#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
3697//SPI_WF_LIFETIME_STATUS_1
3698#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
3699#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
3700#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
3701#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
3702//SPI_WF_LIFETIME_STATUS_2
3703#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
3704#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
3705#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
3706#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
3707//SPI_WF_LIFETIME_STATUS_3
3708#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
3709#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
3710#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
3711#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
3712//SPI_WF_LIFETIME_STATUS_4
3713#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
3714#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
3715#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
3716#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
3717//SPI_WF_LIFETIME_STATUS_5
3718#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
3719#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
3720#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
3721#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
3722//SPI_WF_LIFETIME_STATUS_6
3723#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
3724#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
3725#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
3726#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
3727//SPI_WF_LIFETIME_STATUS_7
3728#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
3729#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
3730#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
3731#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
3732//SPI_WF_LIFETIME_STATUS_8
3733#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
3734#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
3735#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
3736#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
3737//SPI_WF_LIFETIME_STATUS_9
3738#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
3739#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
3740#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
3741#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
3742//SPI_WF_LIFETIME_STATUS_10
3743#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
3744#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
3745#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
3746#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
3747//SPI_WF_LIFETIME_STATUS_11
3748#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
3749#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
3750#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
3751#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
3752//SPI_WF_LIFETIME_STATUS_12
3753#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
3754#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
3755#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
3756#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
3757//SPI_WF_LIFETIME_STATUS_13
3758#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
3759#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
3760#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
3761#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
3762//SPI_WF_LIFETIME_STATUS_14
3763#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
3764#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
3765#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
3766#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
3767//SPI_WF_LIFETIME_STATUS_15
3768#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
3769#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
3770#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
3771#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
3772//SPI_WF_LIFETIME_STATUS_16
3773#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
3774#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
3775#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
3776#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
3777//SPI_WF_LIFETIME_STATUS_17
3778#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
3779#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
3780#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
3781#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
3782//SPI_WF_LIFETIME_STATUS_18
3783#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
3784#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
3785#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
3786#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
3787//SPI_WF_LIFETIME_STATUS_19
3788#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
3789#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
3790#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
3791#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
3792//SPI_WF_LIFETIME_STATUS_20
3793#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
3794#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
3795#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
3796#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
3797//SPI_LB_CTR_CTRL
3798#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
3799#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
3800#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
3801#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
3802#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
3803#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
3804#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
3805#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
3806//SPI_LB_CU_MASK
3807#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
3808#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
3809//SPI_LB_DATA_REG
3810#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
3811#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
3812//SPI_PG_ENABLE_STATIC_CU_MASK
3813#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
3814#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
3815//SPI_GDS_CREDITS
3816#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
3817#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
3818#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
3819#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
3820#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
3821#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
3822//SPI_SX_EXPORT_BUFFER_SIZES
3823#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
3824#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
3825#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
3826#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
3827//SPI_SX_SCOREBOARD_BUFFER_SIZES
3828#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
3829#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
3830#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
3831#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
3832//SPI_CSQ_WF_ACTIVE_STATUS
3833#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
3834#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
3835//SPI_CSQ_WF_ACTIVE_COUNT_0
3836#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
3837#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
3838#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
3839#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
3840//SPI_CSQ_WF_ACTIVE_COUNT_1
3841#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
3842#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
3843#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
3844#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
3845//SPI_CSQ_WF_ACTIVE_COUNT_2
3846#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
3847#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
3848#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
3849#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
3850//SPI_CSQ_WF_ACTIVE_COUNT_3
3851#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
3852#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
3853#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
3854#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
3855//SPI_CSQ_WF_ACTIVE_COUNT_4
3856#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
3857#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
3858#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
3859#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
3860//SPI_CSQ_WF_ACTIVE_COUNT_5
3861#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
3862#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
3863#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
3864#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
3865//SPI_CSQ_WF_ACTIVE_COUNT_6
3866#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
3867#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
3868#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
3869#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
3870//SPI_CSQ_WF_ACTIVE_COUNT_7
3871#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
3872#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
3873#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
3874#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
3875//SPI_LB_DATA_WAVES
3876#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
3877#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
3878#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
3879#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
3880//SPI_LB_DATA_PERCU_WAVE_HSGS
3881#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
3882#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
3883#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
3884#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
3885//SPI_LB_DATA_PERCU_WAVE_VSPS
3886#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
3887#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
3888#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
3889#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
3890//SPI_LB_DATA_PERCU_WAVE_CS
3891#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
3892#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
3893//SPI_P0_TRAP_SCREEN_PSBA_LO
3894#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
3895#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
3896//SPI_P0_TRAP_SCREEN_PSBA_HI
3897#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
3898#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
3899//SPI_P0_TRAP_SCREEN_PSMA_LO
3900#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
3901#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
3902//SPI_P0_TRAP_SCREEN_PSMA_HI
3903#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
3904#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
3905//SPI_P0_TRAP_SCREEN_GPR_MIN
3906#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
3907#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
3908#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
3909#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
3910//SPI_P1_TRAP_SCREEN_PSBA_LO
3911#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
3912#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
3913//SPI_P1_TRAP_SCREEN_PSBA_HI
3914#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
3915#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
3916//SPI_P1_TRAP_SCREEN_PSMA_LO
3917#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
3918#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
3919//SPI_P1_TRAP_SCREEN_PSMA_HI
3920#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
3921#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
3922//SPI_P1_TRAP_SCREEN_GPR_MIN
3923#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
3924#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
3925#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
3926#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
3927
3928
3929// addressBlock: gc_tpdec
3930//TD_CNTL
3931#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
3932#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
3933#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
3934#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
3935#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
3936#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
3937#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
3938#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
3939#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
3940#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
3941#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
3942#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
3943#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
3944#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
3945#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
3946#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
3947#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
3948#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
3949#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
3950#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
3951#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
3952#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
3953#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
3954#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
3955#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
3956#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
3957//TD_STATUS
3958#define TD_STATUS__BUSY__SHIFT 0x1f
3959#define TD_STATUS__BUSY_MASK 0x80000000L
3960//TD_DSM_CNTL
3961#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
3962#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
3963#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
3964#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
3965#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
3966#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
3967#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
3968#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
3969#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
3970#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
3971#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
3972#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
3973//TD_DSM_CNTL2
3974#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
3975#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
3976#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
3977#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
3978#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
3979#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
3980#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
3981#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
3982#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
3983#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
3984#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
3985#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
3986#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
3987#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
3988//TD_SCRATCH
3989#define TD_SCRATCH__SCRATCH__SHIFT 0x0
3990#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
3991//TA_CNTL
3992#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
3993#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
3994#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
3995#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
3996#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
3997#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
3998#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
3999#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
4000#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
4001#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
4002//TA_CNTL_AUX
4003#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
4004#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
4005#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
4006#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
4007#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
4008#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
4009#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
4010#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
4011#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
4012#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
4013#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
4014#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
4015#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
4016#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
4017#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
4018#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
4019#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
4020#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
4021#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
4022#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
4023#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
4024#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
4025#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
4026#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
4027#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
4028#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
4029#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
4030#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
4031#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
4032#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
4033#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
4034#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
4035#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
4036#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
4037#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
4038#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
4039#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
4040#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
4041#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
4042#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
4043#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
4044#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
4045#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
4046#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
4047#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
4048#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
4049#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
4050#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
4051#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
4052#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
4053#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
4054#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
4055//TA_RESERVED_010C
4056#define TA_RESERVED_010C__Unused__SHIFT 0x0
4057#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
4058//TA_STATUS
4059#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
4060#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
4061#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
4062#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
4063#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
4064#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
4065#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
4066#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
4067#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
4068#define TA_STATUS__IN_BUSY__SHIFT 0x18
4069#define TA_STATUS__FG_BUSY__SHIFT 0x19
4070#define TA_STATUS__LA_BUSY__SHIFT 0x1a
4071#define TA_STATUS__FL_BUSY__SHIFT 0x1b
4072#define TA_STATUS__TA_BUSY__SHIFT 0x1c
4073#define TA_STATUS__FA_BUSY__SHIFT 0x1d
4074#define TA_STATUS__AL_BUSY__SHIFT 0x1e
4075#define TA_STATUS__BUSY__SHIFT 0x1f
4076#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
4077#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
4078#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
4079#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
4080#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
4081#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
4082#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
4083#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
4084#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
4085#define TA_STATUS__IN_BUSY_MASK 0x01000000L
4086#define TA_STATUS__FG_BUSY_MASK 0x02000000L
4087#define TA_STATUS__LA_BUSY_MASK 0x04000000L
4088#define TA_STATUS__FL_BUSY_MASK 0x08000000L
4089#define TA_STATUS__TA_BUSY_MASK 0x10000000L
4090#define TA_STATUS__FA_BUSY_MASK 0x20000000L
4091#define TA_STATUS__AL_BUSY_MASK 0x40000000L
4092#define TA_STATUS__BUSY_MASK 0x80000000L
4093//TA_SCRATCH
4094#define TA_SCRATCH__SCRATCH__SHIFT 0x0
4095#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
4096
4097
4098// addressBlock: gc_gdsdec
4099//GDS_CONFIG
4100#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
4101#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
4102#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
4103#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
4104#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
4105#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
4106#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
4107#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
4108//GDS_CNTL_STATUS
4109#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
4110#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
4111#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
4112#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
4113#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
4114#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
4115#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
4116#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
4117#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
4118#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
4119#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
4120#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
4121#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
4122#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
4123#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
4124#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
4125#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
4126#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
4127#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
4128#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
4129#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
4130#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
4131#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
4132#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
4133#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
4134#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
4135#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
4136#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
4137#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
4138#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
4139//GDS_ENHANCE2
4140#define GDS_ENHANCE2__MISC__SHIFT 0x0
4141#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
4142#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
4143#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
4144//GDS_PROTECTION_FAULT
4145#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
4146#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
4147#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
4148#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
4149#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
4150#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
4151#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
4152#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
4153#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
4154#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
4155#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
4156#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
4157#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
4158#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
4159//GDS_VM_PROTECTION_FAULT
4160#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
4161#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
4162#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
4163#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
4164#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
4165#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
4166#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
4167#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
4168#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
4169#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
4170#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
4171#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
4172//GDS_DSM_CNTL
4173#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
4174#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
4175#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
4176#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
4177#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
4178#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
4179#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
4180#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
4181#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
4182#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
4183#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
4184#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
4185#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
4186#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
4187#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
4188#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
4189#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
4190#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
4191#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
4192#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
4193#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
4194#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
4195#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
4196#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
4197#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
4198#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
4199#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
4200#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
4201#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
4202#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
4203#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
4204#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
4205//GDS_DSM_CNTL2
4206#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
4207#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
4208#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
4209#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
4210#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
4211#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
4212#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
4213#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
4214#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
4215#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
4216#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
4217#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
4218#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
4219#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
4220#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
4221#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
4222#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
4223#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
4224#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
4225#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
4226#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
4227#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
4228#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
4229#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
4230//GDS_WD_GDS_CSB
4231#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
4232#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
4233#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
4234#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
4235
4236
4237// addressBlock: gc_rbdec
4238//DB_DEBUG
4239#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
4240#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
4241#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
4242#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
4243#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
4244#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
4245#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
4246#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
4247#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
4248#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
4249#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
4250#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
4251#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
4252#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
4253#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
4254#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
4255#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
4256#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
4257#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
4258#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
4259#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
4260#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
4261#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
4262#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
4263#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
4264#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
4265#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
4266#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
4267#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
4268#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
4269#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
4270#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
4271#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
4272#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
4273#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
4274#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
4275#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
4276#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
4277#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
4278#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
4279#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
4280#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
4281#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
4282#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
4283#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
4284#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
4285#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
4286#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
4287//DB_DEBUG2
4288#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
4289#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
4290#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
4291#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
4292#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
4293#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
4294#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
4295#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
4296#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
4297#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
4298#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
4299#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
4300#define DB_DEBUG2__RESERVED__SHIFT 0x10
4301#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
4302#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
4303#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
4304#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a
4305#define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b
4306#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
4307#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
4308#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
4309#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
4310#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
4311#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
4312#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
4313#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
4314#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
4315#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
4316#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
4317#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
4318#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
4319#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
4320#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
4321#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
4322#define DB_DEBUG2__RESERVED_MASK 0x00010000L
4323#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
4324#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
4325#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
4326#define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L
4327#define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L
4328#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
4329#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
4330#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
4331#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
4332//DB_DEBUG3
4333#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
4334#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
4335#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
4336#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
4337#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
4338#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
4339#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
4340#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
4341#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
4342#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
4343#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
4344#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
4345#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
4346#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
4347#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
4348#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
4349#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
4350#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
4351#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
4352#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
4353#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
4354#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
4355#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
4356#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
4357#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
4358#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
4359#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
4360#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
4361#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
4362#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
4363#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
4364#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
4365#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
4366#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
4367#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
4368#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
4369#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
4370#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
4371#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
4372#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
4373#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
4374#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
4375#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
4376#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
4377#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
4378#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
4379#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
4380#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
4381#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
4382#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
4383#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
4384#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
4385#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
4386#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
4387#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
4388#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
4389#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
4390#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
4391#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
4392#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
4393#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
4394#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
4395#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
4396#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
4397//DB_DEBUG4
4398#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
4399#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
4400#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
4401#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
4402#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
4403#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
4404#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
4405#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
4406#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
4407#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
4408#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
4409#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
4410#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
4411#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
4412#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
4413#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
4414#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
4415#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
4416#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
4417#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
4418#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS__SHIFT 0x1e
4419#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0x1f
4420#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
4421#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
4422#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
4423#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
4424#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
4425#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
4426#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
4427#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
4428#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
4429#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
4430#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
4431#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
4432#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
4433#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
4434#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
4435#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
4436#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
4437#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
4438#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
4439#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0x3FF80000L
4440#define DB_DEBUG4__DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS_MASK 0x40000000L
4441#define DB_DEBUG4__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x80000000L
4442//DB_CREDIT_LIMIT
4443#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
4444#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
4445#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4446#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
4447#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
4448#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
4449#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
4450#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
4451//DB_WATERMARKS
4452#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
4453#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
4454#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
4455#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
4456#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
4457#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
4458#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
4459#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
4460#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
4461#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
4462#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
4463#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
4464#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
4465#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
4466//DB_SUBTILE_CONTROL
4467#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
4468#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
4469#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
4470#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
4471#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
4472#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4473#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
4474#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
4475#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
4476#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
4477#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
4478#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
4479#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
4480#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
4481#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
4482#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
4483#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
4484#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
4485#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
4486#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
4487//DB_FREE_CACHELINES
4488#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
4489#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
4490#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
4491#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
4492#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
4493#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
4494#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
4495#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
4496#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
4497#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
4498//DB_FIFO_DEPTH1
4499#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
4500#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
4501#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4502#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
4503#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
4504#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
4505#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
4506#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
4507#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
4508#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
4509//DB_FIFO_DEPTH2
4510#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
4511#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
4512#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
4513#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
4514#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
4515#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
4516#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
4517#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
4518//DB_EXCEPTION_CONTROL
4519#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
4520#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
4521#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
4522#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
4523#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
4524#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
4525//DB_RING_CONTROL
4526#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
4527#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
4528//DB_MEM_ARB_WATERMARKS
4529#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
4530#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
4531#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
4532#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
4533#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
4534#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
4535#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
4536#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
4537//DB_RMI_CACHE_POLICY
4538#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
4539#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
4540#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
4541#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
4542#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
4543#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
4544#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
4545#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
4546#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
4547#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
4548#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
4549#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
4550#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
4551#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
4552#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
4553#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
4554#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
4555#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
4556#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
4557#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
4558#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
4559#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
4560#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
4561#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
4562#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
4563#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
4564#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
4565#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
4566#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
4567#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
4568//DB_DFSM_CONFIG
4569#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
4570#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
4571#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
4572#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
4573#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
4574#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
4575#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
4576#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
4577#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
4578#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
4579//DB_DFSM_WATERMARK
4580#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
4581#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
4582#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
4583#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
4584//DB_DFSM_TILES_IN_FLIGHT
4585#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
4586#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
4587#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
4588#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
4589//DB_DFSM_PRIMS_IN_FLIGHT
4590#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
4591#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
4592#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
4593#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
4594//DB_DFSM_WATCHDOG
4595#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
4596#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
4597//DB_DFSM_FLUSH_ENABLE
4598#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
4599#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
4600#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
4601#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
4602#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
4603#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
4604//DB_DFSM_FLUSH_AUX_EVENT
4605#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
4606#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
4607#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
4608#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
4609#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
4610#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
4611#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
4612#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
4613//CC_RB_REDUNDANCY
4614#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4615#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4616#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4617#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4618#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
4619#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
4620#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
4621#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
4622//CC_RB_BACKEND_DISABLE
4623#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4624#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
4625//GB_ADDR_CONFIG
4626#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
4627#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
4628#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
4629#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
4630#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
4631#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
4632#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
4633#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
4634#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
4635#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
4636#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
4637#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
4638#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
4639#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
4640#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
4641#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
4642#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
4643#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
4644#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
4645#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
4646#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
4647#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
4648#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
4649#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
4650#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
4651#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
4652//GB_BACKEND_MAP
4653#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
4654#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
4655//GB_GPU_ID
4656#define GB_GPU_ID__GPU_ID__SHIFT 0x0
4657#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
4658//CC_RB_DAISY_CHAIN
4659#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
4660#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
4661#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
4662#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
4663#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
4664#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
4665#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
4666#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
4667#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
4668#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
4669#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
4670#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
4671#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
4672#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
4673#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
4674#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
4675//GB_ADDR_CONFIG_READ
4676#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
4677#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
4678#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
4679#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
4680#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
4681#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
4682#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
4683#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
4684#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
4685#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
4686#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
4687#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
4688#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
4689#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
4690#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
4691#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
4692#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
4693#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
4694#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
4695#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
4696#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
4697#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
4698#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
4699#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
4700#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
4701#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
4702//GB_TILE_MODE0
4703#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
4704#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
4705#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
4706#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
4707#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
4708#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
4709#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
4710#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
4711#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4712#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
4713//GB_TILE_MODE1
4714#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
4715#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
4716#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
4717#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
4718#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
4719#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
4720#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
4721#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
4722#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4723#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
4724//GB_TILE_MODE2
4725#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
4726#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
4727#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
4728#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
4729#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
4730#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
4731#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
4732#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
4733#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4734#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
4735//GB_TILE_MODE3
4736#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
4737#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
4738#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
4739#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
4740#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
4741#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
4742#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
4743#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
4744#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4745#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
4746//GB_TILE_MODE4
4747#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
4748#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
4749#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
4750#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
4751#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
4752#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
4753#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
4754#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
4755#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4756#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
4757//GB_TILE_MODE5
4758#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
4759#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
4760#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
4761#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
4762#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
4763#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
4764#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
4765#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
4766#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4767#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
4768//GB_TILE_MODE6
4769#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
4770#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
4771#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
4772#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
4773#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
4774#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
4775#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
4776#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
4777#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4778#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
4779//GB_TILE_MODE7
4780#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
4781#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
4782#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
4783#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
4784#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
4785#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
4786#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
4787#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
4788#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4789#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
4790//GB_TILE_MODE8
4791#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
4792#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
4793#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
4794#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
4795#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
4796#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
4797#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
4798#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
4799#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4800#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
4801//GB_TILE_MODE9
4802#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
4803#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
4804#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
4805#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
4806#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
4807#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
4808#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
4809#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
4810#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4811#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
4812//GB_TILE_MODE10
4813#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
4814#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
4815#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
4816#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
4817#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
4818#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
4819#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
4820#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
4821#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4822#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
4823//GB_TILE_MODE11
4824#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
4825#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
4826#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
4827#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
4828#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
4829#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
4830#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
4831#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
4832#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4833#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
4834//GB_TILE_MODE12
4835#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
4836#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
4837#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
4838#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
4839#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
4840#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
4841#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
4842#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
4843#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4844#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
4845//GB_TILE_MODE13
4846#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
4847#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
4848#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
4849#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
4850#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
4851#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
4852#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
4853#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
4854#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4855#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
4856//GB_TILE_MODE14
4857#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
4858#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
4859#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
4860#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
4861#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
4862#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
4863#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
4864#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
4865#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4866#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
4867//GB_TILE_MODE15
4868#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
4869#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
4870#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
4871#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
4872#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
4873#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
4874#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
4875#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
4876#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4877#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
4878//GB_TILE_MODE16
4879#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
4880#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
4881#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
4882#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
4883#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
4884#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
4885#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
4886#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
4887#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4888#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
4889//GB_TILE_MODE17
4890#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
4891#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
4892#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
4893#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
4894#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
4895#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
4896#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
4897#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
4898#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4899#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
4900//GB_TILE_MODE18
4901#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
4902#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
4903#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
4904#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
4905#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
4906#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
4907#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
4908#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
4909#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4910#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
4911//GB_TILE_MODE19
4912#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
4913#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
4914#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
4915#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
4916#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
4917#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
4918#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
4919#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
4920#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4921#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
4922//GB_TILE_MODE20
4923#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
4924#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
4925#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
4926#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
4927#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
4928#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
4929#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
4930#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
4931#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4932#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
4933//GB_TILE_MODE21
4934#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
4935#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
4936#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
4937#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
4938#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
4939#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
4940#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
4941#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
4942#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4943#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
4944//GB_TILE_MODE22
4945#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
4946#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
4947#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
4948#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
4949#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
4950#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
4951#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
4952#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
4953#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4954#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
4955//GB_TILE_MODE23
4956#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
4957#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
4958#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
4959#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
4960#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
4961#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
4962#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
4963#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
4964#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4965#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
4966//GB_TILE_MODE24
4967#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
4968#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
4969#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
4970#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
4971#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
4972#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
4973#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
4974#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
4975#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4976#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
4977//GB_TILE_MODE25
4978#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
4979#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
4980#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
4981#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
4982#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
4983#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
4984#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
4985#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
4986#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4987#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
4988//GB_TILE_MODE26
4989#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
4990#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
4991#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
4992#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
4993#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
4994#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
4995#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
4996#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
4997#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
4998#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
4999//GB_TILE_MODE27
5000#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
5001#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
5002#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
5003#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
5004#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
5005#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
5006#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
5007#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
5008#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5009#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
5010//GB_TILE_MODE28
5011#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
5012#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
5013#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
5014#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
5015#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
5016#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
5017#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
5018#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
5019#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5020#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
5021//GB_TILE_MODE29
5022#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
5023#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
5024#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
5025#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
5026#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
5027#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
5028#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
5029#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
5030#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5031#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
5032//GB_TILE_MODE30
5033#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
5034#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
5035#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
5036#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
5037#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
5038#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
5039#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
5040#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
5041#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5042#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
5043//GB_TILE_MODE31
5044#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
5045#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
5046#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
5047#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
5048#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
5049#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
5050#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
5051#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
5052#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5053#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
5054//GB_MACROTILE_MODE0
5055#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
5056#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
5057#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
5058#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
5059#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
5060#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
5061#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
5062#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
5063//GB_MACROTILE_MODE1
5064#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
5065#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
5066#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
5067#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
5068#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
5069#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
5070#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
5071#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
5072//GB_MACROTILE_MODE2
5073#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
5074#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
5075#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
5076#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
5077#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
5078#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
5079#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
5080#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
5081//GB_MACROTILE_MODE3
5082#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
5083#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
5084#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
5085#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
5086#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
5087#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
5088#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
5089#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
5090//GB_MACROTILE_MODE4
5091#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
5092#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
5093#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
5094#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
5095#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
5096#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
5097#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
5098#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
5099//GB_MACROTILE_MODE5
5100#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
5101#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
5102#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
5103#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
5104#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
5105#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
5106#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
5107#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
5108//GB_MACROTILE_MODE6
5109#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
5110#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
5111#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
5112#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
5113#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
5114#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
5115#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
5116#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
5117//GB_MACROTILE_MODE7
5118#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
5119#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
5120#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
5121#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
5122#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
5123#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
5124#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
5125#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
5126//GB_MACROTILE_MODE8
5127#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
5128#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
5129#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
5130#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
5131#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
5132#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
5133#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
5134#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
5135//GB_MACROTILE_MODE9
5136#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
5137#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
5138#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
5139#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
5140#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
5141#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
5142#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
5143#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
5144//GB_MACROTILE_MODE10
5145#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
5146#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
5147#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
5148#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
5149#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
5150#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
5151#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
5152#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
5153//GB_MACROTILE_MODE11
5154#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
5155#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
5156#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
5157#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
5158#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
5159#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
5160#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
5161#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
5162//GB_MACROTILE_MODE12
5163#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
5164#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
5165#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
5166#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
5167#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
5168#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
5169#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
5170#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
5171//GB_MACROTILE_MODE13
5172#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
5173#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
5174#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
5175#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
5176#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
5177#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
5178#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
5179#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
5180//GB_MACROTILE_MODE14
5181#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
5182#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
5183#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
5184#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
5185#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
5186#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
5187#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
5188#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
5189//GB_MACROTILE_MODE15
5190#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
5191#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
5192#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
5193#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
5194#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
5195#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
5196#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
5197#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
5198//CB_HW_CONTROL
5199#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
5200#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
5201#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
5202#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
5203#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
5204#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
5205#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
5206#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
5207#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
5208#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
5209#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
5210#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
5211#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
5212#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
5213#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
5214#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
5215#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
5216#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
5217#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
5218#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
5219#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
5220#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
5221#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
5222#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
5223#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
5224#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
5225#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
5226#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
5227#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
5228#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
5229#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
5230#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
5231#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
5232#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
5233#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
5234#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
5235//CB_HW_CONTROL_1
5236#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
5237#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
5238#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
5239#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
5240#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
5241#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
5242#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
5243#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
5244#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
5245#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
5246//CB_HW_CONTROL_2
5247#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
5248#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
5249#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
5250#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
5251#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
5252#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
5253#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
5254#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
5255#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
5256#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
5257//CB_HW_CONTROL_3
5258#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
5259#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
5260#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
5261#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
5262#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
5263#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
5264#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
5265#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
5266#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
5267#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
5268#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
5269#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
5270#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
5271#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
5272#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
5273#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
5274#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
5275#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
5276#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
5277#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
5278#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
5279#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
5280#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
5281#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
5282#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
5283#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
5284#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
5285#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
5286#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
5287#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
5288#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
5289#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
5290#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
5291#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
5292#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
5293#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
5294#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
5295#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
5296#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
5297#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
5298#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
5299#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
5300#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
5301#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
5302#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
5303#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
5304#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
5305#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
5306#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
5307#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
5308#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
5309#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
5310#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
5311#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
5312#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
5313#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
5314#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
5315#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
5316//CB_HW_MEM_ARBITER_RD
5317#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
5318#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
5319#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
5320#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
5321#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
5322#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
5323#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
5324#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
5325#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
5326#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
5327#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
5328#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
5329#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
5330#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
5331#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
5332#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
5333#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
5334#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
5335#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
5336#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
5337#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
5338#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
5339#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
5340#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
5341#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
5342#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
5343//CB_HW_MEM_ARBITER_WR
5344#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
5345#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
5346#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
5347#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
5348#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
5349#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
5350#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
5351#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
5352#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
5353#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
5354#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
5355#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
5356#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
5357#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
5358#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
5359#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
5360#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
5361#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
5362#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
5363#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
5364#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
5365#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
5366#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
5367#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
5368#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
5369#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
5370//CB_DCC_CONFIG
5371#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
5372#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
5373#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
5374#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7
5375#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
5376#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
5377#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
5378#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
5379#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
5380#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
5381#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
5382#define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L
5383#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
5384#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
5385#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
5386#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
5387//GC_USER_RB_REDUNDANCY
5388#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
5389#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
5390#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
5391#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
5392#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
5393#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
5394#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
5395#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
5396//GC_USER_RB_BACKEND_DISABLE
5397#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
5398#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
5399
5400
5401// addressBlock: gc_ea_gceadec2
5402//GCEA_PERFCOUNTER_RSLT_CNTL
5403#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5404#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5405#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5406#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5407#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5408#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5409#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
5410#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
5411#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
5412#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
5413#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
5414#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
5415//GCEA_DSM_CNTL
5416#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
5417#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
5418#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
5419#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
5420#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
5421#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
5422#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
5423#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
5424#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
5425#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
5426#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
5427#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
5428#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
5429#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
5430#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15
5431#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17
5432#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
5433#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
5434#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
5435#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
5436#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
5437#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
5438#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
5439#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
5440#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
5441#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
5442#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
5443#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
5444#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
5445#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
5446#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L
5447#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
5448//GCEA_DSM_CNTLA
5449#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0
5450#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
5451#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3
5452#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
5453#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6
5454#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
5455#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9
5456#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
5457#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc
5458#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
5459#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf
5460#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11
5461#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12
5462#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14
5463#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
5464#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
5465#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
5466#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
5467#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
5468#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
5469#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
5470#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
5471#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L
5472#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
5473#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L
5474#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L
5475#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L
5476#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L
5477//GCEA_DSM_CNTLB
5478#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
5479#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
5480#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3
5481#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5
5482#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6
5483#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8
5484#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9
5485#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb
5486#define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
5487#define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
5488#define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L
5489#define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L
5490#define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L
5491#define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
5492#define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L
5493#define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
5494//GCEA_DSM_CNTL2
5495#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
5496#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2
5497#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
5498#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5
5499#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
5500#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8
5501#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
5502#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb
5503#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
5504#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe
5505#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
5506#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11
5507#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
5508#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14
5509#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15
5510#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17
5511#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
5512#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
5513#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
5514#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
5515#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
5516#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
5517#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
5518#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
5519#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
5520#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
5521#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
5522#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
5523#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
5524#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
5525#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
5526#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L
5527#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L
5528#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
5529//GCEA_DSM_CNTL2A
5530#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0
5531#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2
5532#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3
5533#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5
5534#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6
5535#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8
5536#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9
5537#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb
5538#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc
5539#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe
5540#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf
5541#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11
5542#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12
5543#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14
5544#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
5545#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L
5546#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
5547#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L
5548#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
5549#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L
5550#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
5551#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L
5552#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
5553#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L
5554#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L
5555#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L
5556#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L
5557#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L
5558//GCEA_DSM_CNTL2B
5559#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
5560#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2
5561#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3
5562#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5
5563#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6
5564#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8
5565#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9
5566#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb
5567#define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
5568#define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
5569#define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L
5570#define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L
5571#define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
5572#define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L
5573#define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L
5574#define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L
5575//GCEA_TCC_XBR_CREDITS
5576#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0
5577#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6
5578#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8
5579#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe
5580#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10
5581#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16
5582#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18
5583#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e
5584#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL
5585#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L
5586#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L
5587#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L
5588#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L
5589#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L
5590#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L
5591#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L
5592//GCEA_TCC_XBR_MAXBURST
5593#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0
5594#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4
5595#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8
5596#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc
5597#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL
5598#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L
5599#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L
5600#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L
5601//GCEA_PROBE_CNTL
5602#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0
5603#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5
5604#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL
5605#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L
5606//GCEA_PROBE_MAP
5607#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0
5608#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1
5609#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2
5610#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3
5611#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4
5612#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5
5613#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6
5614#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7
5615#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8
5616#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9
5617#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa
5618#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb
5619#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc
5620#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd
5621#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe
5622#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf
5623#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10
5624#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L
5625#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L
5626#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L
5627#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L
5628#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L
5629#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L
5630#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L
5631#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L
5632#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L
5633#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L
5634#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L
5635#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L
5636#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L
5637#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L
5638#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L
5639#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L
5640#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L
5641//GCEA_ERR_STATUS
5642#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0
5643#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4
5644#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8
5645#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa
5646#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb
5647#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc
5648#define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd
5649#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL
5650#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L
5651#define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L
5652#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L
5653#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L
5654#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L
5655#define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L
5656//GCEA_MISC2
5657#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0
5658#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1
5659#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2
5660#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7
5661#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc
5662#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L
5663#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L
5664#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL
5665#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L
5666#define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L
5667//GCEA_DRAM_BANK_ARB
5668#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0
5669#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1
5670#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x8
5671#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xe
5672#define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L
5673#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000000FEL
5674#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00003F00L
5675#define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00004000L
5676//GCEA_SDP_BACKDOOR_CMDCREDITS0
5677#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
5678#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
5679#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
5680#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
5681#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
5682#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
5683#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
5684#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
5685#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
5686#define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
5687//GCEA_SDP_BACKDOOR_CMDCREDITS1
5688#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
5689#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
5690#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
5691#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
5692#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
5693#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
5694#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
5695#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
5696#define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
5697#define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
5698//GCEA_SDP_BACKDOOR_DATACREDITS0
5699#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0
5700#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7
5701#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe
5702#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15
5703#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c
5704#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL
5705#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L
5706#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L
5707#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L
5708#define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L
5709//GCEA_SDP_BACKDOOR_DATACREDITS1
5710#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0
5711#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3
5712#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa
5713#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11
5714#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18
5715#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L
5716#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L
5717#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L
5718#define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L
5719#define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L
5720//GCEA_SDP_BACKDOOR_MISCCREDITS
5721#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0
5722#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8
5723#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10
5724#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17
5725#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL
5726#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L
5727#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L
5728#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L
5729//GCEA_SDP_ENABLE
5730#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0
5731#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L
5732
5733
5734// addressBlock: gc_rmi_rmidec
5735//RMI_GENERAL_CNTL
5736#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
5737#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
5738#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
5739#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
5740#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
5741#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
5742#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
5743#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
5744#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
5745#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
5746#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
5747#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
5748#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
5749#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
5750#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
5751#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
5752#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
5753#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
5754#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
5755#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
5756#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
5757#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
5758#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
5759#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
5760//RMI_GENERAL_CNTL1
5761#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
5762#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
5763#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
5764#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
5765#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
5766#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
5767#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
5768#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
5769#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
5770#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
5771#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
5772#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
5773#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
5774#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
5775#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
5776#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
5777//RMI_GENERAL_STATUS
5778#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
5779#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
5780#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
5781#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
5782#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
5783#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
5784#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
5785#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
5786#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
5787#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
5788#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
5789#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
5790#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
5791#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
5792#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
5793#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
5794#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
5795#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
5796#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
5797#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
5798#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
5799#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
5800#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
5801#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
5802#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
5803#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
5804#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
5805#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
5806#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
5807#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
5808#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
5809#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
5810#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
5811#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
5812#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
5813#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
5814#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
5815#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
5816#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
5817#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
5818#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
5819#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
5820#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
5821#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
5822#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
5823#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
5824#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
5825#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
5826#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
5827#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
5828//RMI_SUBBLOCK_STATUS0
5829#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
5830#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
5831#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
5832#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
5833#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
5834#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
5835#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
5836#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
5837#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
5838#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
5839#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
5840#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
5841#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
5842#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
5843//RMI_SUBBLOCK_STATUS1
5844#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
5845#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
5846#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
5847#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
5848#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
5849#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
5850//RMI_SUBBLOCK_STATUS2
5851#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
5852#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
5853#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
5854#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
5855//RMI_SUBBLOCK_STATUS3
5856#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
5857#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
5858#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
5859#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
5860//RMI_XBAR_CONFIG
5861#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
5862#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
5863#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
5864#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
5865#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
5866#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
5867#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
5868#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
5869#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
5870#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
5871#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
5872#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
5873#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
5874#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
5875#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
5876#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
5877//RMI_PROBE_POP_LOGIC_CNTL
5878#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
5879#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
5880#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
5881#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
5882#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
5883#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
5884#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
5885#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
5886#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
5887#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
5888//RMI_UTC_XNACK_N_MISC_CNTL
5889#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
5890#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
5891#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
5892#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
5893#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
5894#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
5895#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
5896#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
5897//RMI_DEMUX_CNTL
5898#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
5899#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
5900#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
5901#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
5902#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
5903#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
5904#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
5905#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
5906#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
5907#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
5908#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
5909#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
5910#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
5911#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
5912#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
5913#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
5914#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
5915#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
5916#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
5917#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
5918//RMI_UTCL1_CNTL1
5919#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
5920#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
5921#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
5922#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
5923#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
5924#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
5925#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
5926#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
5927#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
5928#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
5929#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
5930#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
5931#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
5932#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
5933#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
5934#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
5935#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
5936#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
5937#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
5938#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
5939#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
5940#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
5941#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
5942#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
5943#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
5944#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
5945#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
5946#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
5947#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
5948#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
5949#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
5950#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
5951#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
5952#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
5953//RMI_UTCL1_CNTL2
5954#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
5955#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
5956#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
5957#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
5958#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
5959#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
5960#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
5961#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
5962#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
5963#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
5964#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
5965#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
5966#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
5967#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
5968#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
5969#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
5970#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
5971#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
5972#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
5973#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
5974#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
5975#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
5976#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
5977#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
5978#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
5979#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
5980#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
5981#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
5982//RMI_TCIW_FORMATTER0_CNTL
5983#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
5984#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
5985#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
5986#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
5987#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
5988#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
5989#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
5990#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
5991#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
5992#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
5993#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
5994#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
5995#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
5996#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
5997#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
5998#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
5999#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
6000#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
6001//RMI_TCIW_FORMATTER1_CNTL
6002#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
6003#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
6004#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
6005#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
6006#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
6007#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
6008#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
6009#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
6010#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
6011#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
6012#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
6013#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
6014#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
6015#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
6016#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
6017#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
6018#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
6019#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
6020//RMI_SCOREBOARD_CNTL
6021#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
6022#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
6023#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
6024#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
6025#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
6026#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
6027#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
6028#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
6029#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
6030#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
6031#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
6032#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
6033#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
6034#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
6035#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
6036#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
6037#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
6038#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
6039#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
6040#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
6041//RMI_SCOREBOARD_STATUS0
6042#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
6043#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
6044#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
6045#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
6046#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
6047#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
6048#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
6049#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
6050#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
6051#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
6052#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
6053#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
6054#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
6055#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
6056//RMI_SCOREBOARD_STATUS1
6057#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
6058#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
6059#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
6060#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
6061#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
6062#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
6063#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
6064#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
6065#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
6066#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
6067#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
6068#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
6069#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
6070#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
6071#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
6072#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
6073#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
6074#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
6075//RMI_SCOREBOARD_STATUS2
6076#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
6077#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
6078#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
6079#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
6080#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
6081#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
6082#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
6083#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
6084#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
6085#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
6086#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
6087#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
6088#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
6089#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
6090#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
6091#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
6092#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
6093#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
6094#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
6095#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
6096//RMI_XBAR_ARBITER_CONFIG
6097#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
6098#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
6099#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
6100#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
6101#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
6102#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
6103#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
6104#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
6105#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
6106#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
6107#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
6108#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
6109#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
6110#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
6111#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
6112#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
6113#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
6114#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
6115#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
6116#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
6117#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
6118#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
6119#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
6120#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
6121//RMI_XBAR_ARBITER_CONFIG_1
6122#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
6123#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
6124#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
6125#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
6126#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
6127#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
6128#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
6129#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
6130//RMI_CLOCK_CNTRL
6131#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
6132#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
6133#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
6134#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
6135#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
6136#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
6137#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
6138#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
6139#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
6140#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
6141#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
6142#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
6143//RMI_UTCL1_STATUS
6144#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
6145#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
6146#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
6147#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
6148#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
6149#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
6150//RMI_SPARE
6151#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
6152#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
6153#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
6154#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
6155#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
6156#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
6157#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
6158#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
6159#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
6160#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
6161#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
6162#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
6163#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
6164#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
6165#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
6166#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
6167#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
6168#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
6169#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
6170#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
6171//RMI_SPARE_1
6172#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
6173#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
6174#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
6175#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
6176#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
6177#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
6178#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
6179#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
6180#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
6181#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
6182#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
6183#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
6184#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
6185#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
6186#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
6187#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
6188#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
6189#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
6190#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
6191#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
6192//RMI_SPARE_2
6193#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
6194#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
6195#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
6196#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
6197#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
6198#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
6199#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
6200#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
6201#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
6202#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
6203#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
6204#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
6205#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
6206#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
6207#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
6208#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
6209#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
6210#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
6211#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
6212#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
6213#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
6214#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
6215#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
6216#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
6217
6218
6219// addressBlock: gc_utcl2_atcl2dec
6220//ATC_L2_CNTL
6221#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
6222#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
6223#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
6224#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
6225#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
6226#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
6227#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
6228#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
6229#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
6230#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
6231#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
6232#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
6233//ATC_L2_CNTL2
6234#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
6235#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6236#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
6237#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
6238#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
6239#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
6240#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
6241#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
6242#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
6243#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
6244#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
6245#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
6246//ATC_L2_CACHE_DATA0
6247#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
6248#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
6249#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
6250#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
6251#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
6252#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
6253#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
6254#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
6255//ATC_L2_CACHE_DATA1
6256#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
6257#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
6258//ATC_L2_CACHE_DATA2
6259#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
6260#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
6261//ATC_L2_CNTL3
6262#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
6263#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
6264#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9
6265#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
6266#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
6267#define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L
6268//ATC_L2_STATUS
6269#define ATC_L2_STATUS__BUSY__SHIFT 0x0
6270#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
6271#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
6272#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
6273//ATC_L2_STATUS2
6274#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
6275#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
6276#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
6277#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
6278//ATC_L2_MISC_CG
6279#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
6280#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
6281#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
6282#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
6283#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
6284#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
6285//ATC_L2_MEM_POWER_LS
6286#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
6287#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
6288#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
6289#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
6290//ATC_L2_CGTT_CLK_CTRL
6291#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
6292#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
6293#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
6294#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
6295#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
6296#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
6297#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
6298#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
6299#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
6300#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
6301
6302
6303// addressBlock: gc_utcl2_vml2pfdec
6304//VM_L2_CNTL
6305#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
6306#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
6307#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
6308#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
6309#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
6310#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
6311#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
6312#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
6313#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
6314#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
6315#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
6316#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
6317#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
6318#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
6319#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
6320#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
6321#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
6322#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
6323#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
6324#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
6325#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
6326#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
6327#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
6328#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
6329#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
6330#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
6331#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
6332#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
6333//VM_L2_CNTL2
6334#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
6335#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
6336#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
6337#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
6338#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
6339#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
6340#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
6341#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
6342#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
6343#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
6344#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
6345#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
6346#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
6347#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
6348//VM_L2_CNTL3
6349#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
6350#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6351#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
6352#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
6353#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
6354#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
6355#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
6356#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
6357#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
6358#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
6359#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
6360#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
6361#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
6362#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
6363#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
6364#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
6365#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
6366#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
6367#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
6368#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
6369#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
6370#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
6371//VM_L2_STATUS
6372#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
6373#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
6374#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
6375#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
6376#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
6377#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
6378#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
6379#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
6380#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
6381#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
6382#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
6383#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
6384#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
6385#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
6386//VM_DUMMY_PAGE_FAULT_CNTL
6387#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
6388#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
6389#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
6390#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
6391#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
6392#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
6393//VM_DUMMY_PAGE_FAULT_ADDR_LO32
6394#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
6395#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6396//VM_DUMMY_PAGE_FAULT_ADDR_HI32
6397#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
6398#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
6399//VM_L2_PROTECTION_FAULT_CNTL
6400#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6401#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
6402#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
6403#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
6404#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
6405#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
6406#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
6407#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
6408#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
6409#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
6410#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6411#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
6412#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6413#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
6414#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
6415#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
6416#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
6417#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
6418#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
6419#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
6420#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
6421#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
6422#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
6423#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
6424#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
6425#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
6426#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
6427#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6428#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
6429#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6430#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
6431#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
6432#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
6433#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
6434//VM_L2_PROTECTION_FAULT_CNTL2
6435#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
6436#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
6437#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
6438#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
6439#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
6440#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
6441#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
6442#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
6443#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
6444#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
6445//VM_L2_PROTECTION_FAULT_MM_CNTL3
6446#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
6447#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
6448//VM_L2_PROTECTION_FAULT_MM_CNTL4
6449#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
6450#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
6451//VM_L2_PROTECTION_FAULT_STATUS
6452#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
6453#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
6454#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
6455#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
6456#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
6457#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
6458#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
6459#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
6460#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
6461#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
6462#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
6463#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
6464#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
6465#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
6466#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
6467#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
6468#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
6469#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
6470#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
6471#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
6472//VM_L2_PROTECTION_FAULT_ADDR_LO32
6473#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
6474#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6475//VM_L2_PROTECTION_FAULT_ADDR_HI32
6476#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
6477#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
6478//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
6479#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
6480#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6481//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
6482#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
6483#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
6484//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
6485#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
6486#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
6487//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
6488#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
6489#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
6490//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
6491#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
6492#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
6493//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
6494#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
6495#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
6496//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
6497#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
6498#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
6499//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
6500#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
6501#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
6502//VM_L2_CNTL4
6503#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
6504#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
6505#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
6506#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
6507#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
6508#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
6509#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
6510#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
6511#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
6512#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
6513#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
6514#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
6515//VM_L2_MM_GROUP_RT_CLASSES
6516#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
6517#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
6518#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
6519#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
6520#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
6521#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
6522#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
6523#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
6524#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
6525#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
6526#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
6527#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
6528#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
6529#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
6530#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
6531#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
6532#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
6533#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
6534#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
6535#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
6536#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
6537#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
6538#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
6539#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
6540#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
6541#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
6542#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
6543#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
6544#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
6545#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
6546#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
6547#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
6548#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
6549#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
6550#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
6551#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
6552#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
6553#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
6554#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
6555#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
6556#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
6557#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
6558#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
6559#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
6560#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
6561#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
6562#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
6563#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
6564#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
6565#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
6566#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
6567#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
6568#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
6569#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
6570#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
6571#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
6572#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
6573#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
6574#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
6575#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
6576#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
6577#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
6578#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
6579#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
6580//VM_L2_BANK_SELECT_RESERVED_CID
6581#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6582#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6583#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
6584#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6585#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6586#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
6587#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
6588#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
6589#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
6590#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
6591//VM_L2_BANK_SELECT_RESERVED_CID2
6592#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6593#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6594#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
6595#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6596#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6597#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
6598#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
6599#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
6600#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
6601#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
6602//VM_L2_CACHE_PARITY_CNTL
6603#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
6604#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
6605#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
6606#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3
6607#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4
6608#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5
6609#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6
6610#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9
6611#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc
6612#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L
6613#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L
6614#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L
6615#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L
6616#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L
6617#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L
6618#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L
6619#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L
6620#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L
6621//VM_L2_CGTT_CLK_CTRL
6622#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
6623#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
6624#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
6625#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
6626#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
6627#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
6628#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
6629#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
6630#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
6631#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
6632
6633
6634// addressBlock: gc_utcl2_vml2vcdec
6635//VM_CONTEXT0_CNTL
6636#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6637#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6638#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6639#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6640#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6641#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6642#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6643#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6644#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6645#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6646#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6647#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6648#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6649#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6650#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6651#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6652#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6653#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6654#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6655#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6656#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6657#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6658#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6659#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6660#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6661#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6662#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6663#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6664#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6665#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6666#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6667#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6668#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6669#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6670#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6671#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6672#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6673#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6674//VM_CONTEXT1_CNTL
6675#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6676#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6677#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6678#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6679#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6680#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6681#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6682#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6683#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6684#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6685#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6686#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6687#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6688#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6689#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6690#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6691#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6692#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6693#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6694#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6695#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6696#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6697#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6698#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6699#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6700#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6701#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6702#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6703#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6704#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6705#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6706#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6707#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6708#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6709#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6710#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6711#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6712#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6713//VM_CONTEXT2_CNTL
6714#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6715#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6716#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6717#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6718#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6719#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6720#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6721#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6722#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6723#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6724#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6725#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6726#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6727#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6728#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6729#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6730#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6731#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6732#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6733#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6734#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6735#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6736#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6737#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6738#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6739#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6740#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6741#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6742#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6743#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6744#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6745#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6746#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6747#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6748#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6749#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6750#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6751#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6752//VM_CONTEXT3_CNTL
6753#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6754#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6755#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6756#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6757#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6758#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6759#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6760#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6761#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6762#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6763#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6764#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6765#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6766#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6767#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6768#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6769#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6770#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6771#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6772#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6773#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6774#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6775#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6776#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6777#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6778#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6779#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6780#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6781#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6782#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6783#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6784#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6785#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6786#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6787#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6788#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6789#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6790#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6791//VM_CONTEXT4_CNTL
6792#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6793#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6794#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6795#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6796#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6797#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6798#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6799#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6800#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6801#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6802#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6803#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6804#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6805#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6806#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6807#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6808#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6809#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6810#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6811#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6812#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6813#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6814#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6815#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6816#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6817#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6818#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6819#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6820#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6821#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6822#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6823#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6824#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6825#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6826#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6827#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6828#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6829#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6830//VM_CONTEXT5_CNTL
6831#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6832#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6833#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6834#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6835#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6836#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6837#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6838#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6839#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6840#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6841#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6842#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6843#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6844#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6845#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6846#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6847#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6848#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6849#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6850#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6851#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6852#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6853#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6854#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6855#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6856#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6857#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6858#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6859#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6860#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6861#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6862#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6863#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6864#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6865#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6866#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6867#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6868#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6869//VM_CONTEXT6_CNTL
6870#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6871#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6872#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6873#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6874#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6875#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6876#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6877#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6878#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6879#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6880#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6881#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6882#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6883#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6884#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6885#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6886#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6887#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6888#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6889#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6890#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6891#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6892#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6893#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6894#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6895#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6896#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6897#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6898#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6899#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6900#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6901#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6902#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6903#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6904#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6905#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6906#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6907#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6908//VM_CONTEXT7_CNTL
6909#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6910#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6911#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6912#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6913#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6914#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6915#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6916#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6917#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6918#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6919#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6920#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6921#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6922#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6923#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6924#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6925#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6926#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6927#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6928#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6929#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6930#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6931#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6932#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6933#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6934#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6935#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6936#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6937#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6938#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6939#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6940#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6941#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6942#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6943#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6944#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6945#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6946#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6947//VM_CONTEXT8_CNTL
6948#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6949#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6950#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6951#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6952#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6953#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6954#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6955#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6956#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6957#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6958#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6959#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6960#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6961#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
6962#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
6963#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
6964#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
6965#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6966#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6967#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
6968#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
6969#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
6970#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
6971#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
6972#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
6973#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6974#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
6975#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6976#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
6977#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
6978#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
6979#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
6980#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
6981#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
6982#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
6983#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
6984#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
6985#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
6986//VM_CONTEXT9_CNTL
6987#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6988#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6989#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
6990#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
6991#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
6992#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6993#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6994#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
6995#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6996#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
6997#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
6998#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6999#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7000#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7001#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7002#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7003#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7004#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7005#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7006#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7007#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7008#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7009#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7010#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7011#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7012#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7013#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7014#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7015#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7016#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7017#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7018#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7019#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7020#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7021#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7022#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7023#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7024#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7025//VM_CONTEXT10_CNTL
7026#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7027#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7028#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7029#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7030#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7031#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7032#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7033#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7034#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7035#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7036#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7037#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7038#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7039#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7040#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7041#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7042#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7043#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7044#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7045#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7046#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7047#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7048#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7049#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7050#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7051#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7052#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7053#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7054#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7055#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7056#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7057#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7058#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7059#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7060#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7061#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7062#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7063#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7064//VM_CONTEXT11_CNTL
7065#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7066#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7067#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7068#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7069#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7070#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7071#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7072#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7073#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7074#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7075#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7076#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7077#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7078#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7079#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7080#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7081#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7082#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7083#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7084#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7085#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7086#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7087#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7088#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7089#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7090#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7091#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7092#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7093#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7094#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7095#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7096#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7097#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7098#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7099#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7100#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7101#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7102#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7103//VM_CONTEXT12_CNTL
7104#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7105#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7106#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7107#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7108#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7109#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7110#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7111#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7112#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7113#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7114#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7115#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7116#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7117#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7118#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7119#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7120#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7121#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7122#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7123#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7124#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7125#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7126#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7127#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7128#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7129#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7130#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7131#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7132#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7133#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7134#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7135#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7136#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7137#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7138#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7139#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7140#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7141#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7142//VM_CONTEXT13_CNTL
7143#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7144#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7145#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7146#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7147#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7148#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7149#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7150#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7151#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7152#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7153#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7154#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7155#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7156#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7157#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7158#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7159#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7160#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7161#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7162#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7163#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7164#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7165#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7166#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7167#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7168#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7169#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7170#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7171#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7172#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7173#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7174#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7175#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7176#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7177#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7178#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7179#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7180#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7181//VM_CONTEXT14_CNTL
7182#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7183#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7184#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7185#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7186#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7187#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7188#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7189#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7190#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7191#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7192#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7193#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7194#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7195#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7196#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7197#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7198#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7199#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7200#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7201#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7202#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7203#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7204#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7205#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7206#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7207#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7208#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7209#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7210#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7211#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7212#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7213#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7214#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7215#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7216#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7217#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7218#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7219#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7220//VM_CONTEXT15_CNTL
7221#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0
7222#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
7223#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3
7224#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7
7225#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8
7226#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
7227#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
7228#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb
7229#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
7230#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd
7231#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe
7232#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
7233#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
7234#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11
7235#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12
7236#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13
7237#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14
7238#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
7239#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
7240#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L
7241#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L
7242#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L
7243#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L
7244#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L
7245#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L
7246#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
7247#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L
7248#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
7249#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L
7250#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L
7251#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L
7252#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7253#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L
7254#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L
7255#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L
7256#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L
7257#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L
7258#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L
7259//VM_CONTEXTS_DISABLE
7260#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
7261#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
7262#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
7263#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
7264#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
7265#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
7266#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
7267#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
7268#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
7269#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
7270#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
7271#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
7272#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
7273#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
7274#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
7275#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
7276#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L
7277#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L
7278#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L
7279#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L
7280#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L
7281#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L
7282#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L
7283#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L
7284#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L
7285#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L
7286#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L
7287#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L
7288#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L
7289#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L
7290#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L
7291#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L
7292//VM_INVALIDATE_ENG0_SEM
7293#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0
7294#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L
7295//VM_INVALIDATE_ENG1_SEM
7296#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0
7297#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L
7298//VM_INVALIDATE_ENG2_SEM
7299#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0
7300#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L
7301//VM_INVALIDATE_ENG3_SEM
7302#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0
7303#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L
7304//VM_INVALIDATE_ENG4_SEM
7305#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0
7306#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L
7307//VM_INVALIDATE_ENG5_SEM
7308#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0
7309#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L
7310//VM_INVALIDATE_ENG6_SEM
7311#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0
7312#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L
7313//VM_INVALIDATE_ENG7_SEM
7314#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0
7315#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L
7316//VM_INVALIDATE_ENG8_SEM
7317#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0
7318#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L
7319//VM_INVALIDATE_ENG9_SEM
7320#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0
7321#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L
7322//VM_INVALIDATE_ENG10_SEM
7323#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0
7324#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L
7325//VM_INVALIDATE_ENG11_SEM
7326#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0
7327#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L
7328//VM_INVALIDATE_ENG12_SEM
7329#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0
7330#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L
7331//VM_INVALIDATE_ENG13_SEM
7332#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0
7333#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L
7334//VM_INVALIDATE_ENG14_SEM
7335#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0
7336#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L
7337//VM_INVALIDATE_ENG15_SEM
7338#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0
7339#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L
7340//VM_INVALIDATE_ENG16_SEM
7341#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0
7342#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L
7343//VM_INVALIDATE_ENG17_SEM
7344#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0
7345#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L
7346//VM_INVALIDATE_ENG0_REQ
7347#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7348#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10
7349#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7350#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7351#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7352#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7353#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7354#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7355#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7356#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L
7357#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7358#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7359#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7360#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7361#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7362#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7363//VM_INVALIDATE_ENG1_REQ
7364#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7365#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10
7366#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7367#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7368#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7369#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7370#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7371#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7372#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7373#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L
7374#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7375#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7376#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7377#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7378#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7379#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7380//VM_INVALIDATE_ENG2_REQ
7381#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7382#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10
7383#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7384#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7385#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7386#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7387#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7388#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7389#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7390#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L
7391#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7392#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7393#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7394#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7395#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7396#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7397//VM_INVALIDATE_ENG3_REQ
7398#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7399#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10
7400#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7401#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7402#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7403#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7404#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7405#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7406#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7407#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L
7408#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7409#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7410#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7411#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7412#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7413#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7414//VM_INVALIDATE_ENG4_REQ
7415#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7416#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10
7417#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7418#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7419#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7420#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7421#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7422#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7423#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7424#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L
7425#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7426#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7427#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7428#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7429#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7430#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7431//VM_INVALIDATE_ENG5_REQ
7432#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7433#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10
7434#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7435#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7436#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7437#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7438#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7439#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7440#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7441#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L
7442#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7443#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7444#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7445#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7446#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7447#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7448//VM_INVALIDATE_ENG6_REQ
7449#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7450#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10
7451#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7452#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7453#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7454#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7455#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7456#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7457#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7458#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L
7459#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7460#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7461#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7462#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7463#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7464#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7465//VM_INVALIDATE_ENG7_REQ
7466#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7467#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10
7468#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7469#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7470#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7471#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7472#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7473#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7474#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7475#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L
7476#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7477#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7478#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7479#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7480#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7481#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7482//VM_INVALIDATE_ENG8_REQ
7483#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7484#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10
7485#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7486#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7487#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7488#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7489#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7490#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7491#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7492#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L
7493#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7494#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7495#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7496#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7497#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7498#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7499//VM_INVALIDATE_ENG9_REQ
7500#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7501#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10
7502#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7503#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7504#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7505#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7506#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7507#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7508#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7509#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L
7510#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7511#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7512#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7513#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7514#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7515#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7516//VM_INVALIDATE_ENG10_REQ
7517#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7518#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10
7519#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7520#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7521#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7522#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7523#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7524#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7525#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7526#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L
7527#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7528#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7529#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7530#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7531#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7532#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7533//VM_INVALIDATE_ENG11_REQ
7534#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7535#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10
7536#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7537#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7538#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7539#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7540#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7541#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7542#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7543#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L
7544#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7545#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7546#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7547#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7548#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7549#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7550//VM_INVALIDATE_ENG12_REQ
7551#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7552#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10
7553#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7554#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7555#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7556#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7557#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7558#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7559#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7560#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L
7561#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7562#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7563#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7564#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7565#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7566#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7567//VM_INVALIDATE_ENG13_REQ
7568#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7569#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10
7570#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7571#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7572#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7573#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7574#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7575#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7576#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7577#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L
7578#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7579#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7580#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7581#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7582#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7583#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7584//VM_INVALIDATE_ENG14_REQ
7585#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7586#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10
7587#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7588#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7589#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7590#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7591#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7592#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7593#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7594#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L
7595#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7596#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7597#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7598#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7599#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7600#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7601//VM_INVALIDATE_ENG15_REQ
7602#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7603#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10
7604#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7605#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7606#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7607#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7608#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7609#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7610#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7611#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L
7612#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7613#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7614#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7615#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7616#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7617#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7618//VM_INVALIDATE_ENG16_REQ
7619#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7620#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10
7621#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7622#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7623#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7624#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7625#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7626#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7627#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7628#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L
7629#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7630#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7631#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7632#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7633#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7634#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7635//VM_INVALIDATE_ENG17_REQ
7636#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0
7637#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10
7638#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12
7639#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13
7640#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14
7641#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15
7642#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16
7643#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17
7644#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL
7645#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L
7646#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L
7647#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L
7648#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L
7649#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L
7650#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L
7651#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L
7652//VM_INVALIDATE_ENG0_ACK
7653#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7654#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10
7655#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7656#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L
7657//VM_INVALIDATE_ENG1_ACK
7658#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7659#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10
7660#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7661#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L
7662//VM_INVALIDATE_ENG2_ACK
7663#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7664#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10
7665#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7666#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L
7667//VM_INVALIDATE_ENG3_ACK
7668#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7669#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10
7670#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7671#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L
7672//VM_INVALIDATE_ENG4_ACK
7673#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7674#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10
7675#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7676#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L
7677//VM_INVALIDATE_ENG5_ACK
7678#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7679#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10
7680#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7681#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L
7682//VM_INVALIDATE_ENG6_ACK
7683#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7684#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10
7685#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7686#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L
7687//VM_INVALIDATE_ENG7_ACK
7688#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7689#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10
7690#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7691#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L
7692//VM_INVALIDATE_ENG8_ACK
7693#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7694#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10
7695#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7696#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L
7697//VM_INVALIDATE_ENG9_ACK
7698#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7699#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10
7700#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7701#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L
7702//VM_INVALIDATE_ENG10_ACK
7703#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7704#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10
7705#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7706#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L
7707//VM_INVALIDATE_ENG11_ACK
7708#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7709#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10
7710#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7711#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L
7712//VM_INVALIDATE_ENG12_ACK
7713#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7714#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10
7715#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7716#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L
7717//VM_INVALIDATE_ENG13_ACK
7718#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7719#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10
7720#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7721#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L
7722//VM_INVALIDATE_ENG14_ACK
7723#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7724#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10
7725#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7726#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L
7727//VM_INVALIDATE_ENG15_ACK
7728#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7729#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10
7730#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7731#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L
7732//VM_INVALIDATE_ENG16_ACK
7733#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7734#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10
7735#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7736#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L
7737//VM_INVALIDATE_ENG17_ACK
7738#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0
7739#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10
7740#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL
7741#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L
7742//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
7743#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7744#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7745#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7746#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7747//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
7748#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7749#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7750//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
7751#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7752#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7753#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7754#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7755//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
7756#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7757#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7758//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
7759#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7760#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7761#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7762#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7763//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
7764#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7765#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7766//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
7767#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7768#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7769#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7770#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7771//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
7772#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7773#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7774//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
7775#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7776#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7777#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7778#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7779//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
7780#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7781#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7782//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
7783#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7784#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7785#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7786#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7787//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
7788#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7789#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7790//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
7791#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7792#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7793#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7794#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7795//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
7796#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7797#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7798//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
7799#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7800#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7801#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7802#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7803//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
7804#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7805#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7806//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
7807#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7808#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7809#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7810#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7811//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
7812#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7813#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7814//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
7815#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7816#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7817#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7818#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7819//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
7820#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7821#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7822//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
7823#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7824#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7825#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7826#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7827//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
7828#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7829#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7830//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
7831#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7832#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7833#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7834#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7835//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
7836#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7837#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7838//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
7839#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7840#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7841#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7842#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7843//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
7844#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7845#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7846//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
7847#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7848#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7849#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7850#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7851//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
7852#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7853#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7854//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
7855#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7856#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7857#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7858#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7859//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
7860#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7861#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7862//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
7863#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7864#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7865#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7866#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7867//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
7868#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7869#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7870//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
7871#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7872#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7873#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7874#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7875//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
7876#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7877#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7878//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
7879#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
7880#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1
7881#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L
7882#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL
7883//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
7884#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0
7885#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL
7886//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
7887#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7888#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7889//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
7890#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7891#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7892//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
7893#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7894#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7895//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
7896#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7897#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7898//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
7899#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7900#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7901//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
7902#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7903#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7904//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
7905#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7906#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7907//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
7908#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7909#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7910//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
7911#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7912#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7913//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
7914#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7915#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7916//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
7917#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7918#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7919//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
7920#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7921#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7922//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
7923#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7924#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7925//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
7926#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7927#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7928//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
7929#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7930#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7931//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
7932#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7933#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7934//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
7935#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7936#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7937//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
7938#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7939#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7940//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
7941#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7942#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7943//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
7944#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7945#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7946//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
7947#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7948#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7949//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
7950#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7951#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7952//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
7953#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7954#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7955//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
7956#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7957#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7958//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
7959#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7960#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7961//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
7962#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7963#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7964//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
7965#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7966#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7967//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
7968#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7969#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7970//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
7971#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7972#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7973//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
7974#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7975#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7976//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
7977#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0
7978#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL
7979//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
7980#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0
7981#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL
7982//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
7983#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
7984#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
7985//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
7986#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
7987#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
7988//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
7989#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
7990#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
7991//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
7992#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
7993#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
7994//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
7995#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
7996#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
7997//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
7998#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
7999#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8000//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
8001#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8002#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8003//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
8004#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8005#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8006//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
8007#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8008#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8009//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
8010#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8011#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8012//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
8013#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8014#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8015//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
8016#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8017#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8018//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
8019#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8020#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8021//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
8022#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8023#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8024//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
8025#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8026#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8027//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
8028#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8029#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8030//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
8031#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8032#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8033//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
8034#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8035#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8036//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
8037#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8038#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8039//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
8040#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8041#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8042//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
8043#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8044#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8045//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
8046#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8047#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8048//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
8049#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8050#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8051//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
8052#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8053#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8054//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
8055#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8056#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8057//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
8058#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8059#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8060//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
8061#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8062#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8063//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
8064#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8065#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8066//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
8067#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8068#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8069//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
8070#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8071#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8072//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
8073#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8074#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8075//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
8076#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8077#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8078//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
8079#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8080#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8081//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
8082#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8083#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8084//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
8085#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8086#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8087//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
8088#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8089#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8090//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
8091#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8092#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8093//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
8094#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8095#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8096//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
8097#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8098#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8099//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
8100#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8101#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8102//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
8103#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8104#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8105//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
8106#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8107#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8108//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
8109#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8110#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8111//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
8112#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8113#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8114//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
8115#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8116#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8117//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
8118#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8119#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8120//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
8121#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8122#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8123//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
8124#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8125#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8126//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
8127#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8128#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8129//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
8130#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8131#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8132//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
8133#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8134#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8135//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
8136#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8137#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8138//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
8139#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8140#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8141//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
8142#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8143#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8144//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
8145#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8146#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8147//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
8148#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8149#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8150//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
8151#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8152#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8153//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
8154#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8155#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8156//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
8157#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8158#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8159//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
8160#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8161#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8162//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
8163#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8164#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8165//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
8166#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8167#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8168//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
8169#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
8170#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
8171//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
8172#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
8173#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
8174
8175
8176// addressBlock: gc_utcl2_vmsharedpfdec
8177//MC_VM_NB_MMIOBASE
8178#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
8179#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL
8180//MC_VM_NB_MMIOLIMIT
8181#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
8182#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL
8183//MC_VM_NB_PCI_CTRL
8184#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
8185#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L
8186//MC_VM_NB_PCI_ARB
8187#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
8188#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L
8189//MC_VM_NB_TOP_OF_DRAM_SLOT1
8190#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
8191#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L
8192//MC_VM_NB_LOWER_TOP_OF_DRAM2
8193#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
8194#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
8195#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L
8196#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L
8197//MC_VM_NB_UPPER_TOP_OF_DRAM2
8198#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
8199#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL
8200//MC_VM_FB_OFFSET
8201#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
8202#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL
8203//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
8204#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0
8205#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL
8206//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
8207#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0
8208#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL
8209//MC_VM_STEERING
8210#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
8211#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L
8212//MC_SHARED_VIRT_RESET_REQ
8213#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
8214#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
8215#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL
8216#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L
8217//MC_MEM_POWER_LS
8218#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
8219#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
8220#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
8221#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
8222//MC_VM_CACHEABLE_DRAM_ADDRESS_START
8223#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0
8224#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
8225//MC_VM_CACHEABLE_DRAM_ADDRESS_END
8226#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0
8227#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
8228//MC_VM_APT_CNTL
8229#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0
8230#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1
8231#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L
8232#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L
8233//MC_VM_LOCAL_HBM_ADDRESS_START
8234#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0
8235#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL
8236//MC_VM_LOCAL_HBM_ADDRESS_END
8237#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0
8238#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL
8239//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
8240#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0
8241#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L
8242//MC_VM_XGMI_LFB_CNTL
8243#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0
8244#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4
8245#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L
8246#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L
8247//MC_VM_XGMI_LFB_SIZE
8248#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0
8249#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL
8250
8251
8252// addressBlock: gc_utcl2_vmsharedvcdec
8253//MC_VM_FB_LOCATION_BASE
8254#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0
8255#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL
8256//MC_VM_FB_LOCATION_TOP
8257#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0
8258#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL
8259//MC_VM_AGP_TOP
8260#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
8261#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL
8262//MC_VM_AGP_BOT
8263#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
8264#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL
8265//MC_VM_AGP_BASE
8266#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
8267#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL
8268//MC_VM_SYSTEM_APERTURE_LOW_ADDR
8269#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0
8270#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
8271//MC_VM_SYSTEM_APERTURE_HIGH_ADDR
8272#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0
8273#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL
8274//MC_VM_MX_L1_TLB_CNTL
8275#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
8276#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
8277#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
8278#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
8279#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
8280#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb
8281#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd
8282#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L
8283#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L
8284#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L
8285#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L
8286#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L
8287#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L
8288#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L
8289
8290
8291// addressBlock: gc_ea_gceadec
8292//GCEA_DRAM_RD_CLI2GRP_MAP0
8293#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
8294#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
8295#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
8296#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
8297#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
8298#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8299#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
8300#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
8301#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
8302#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
8303#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
8304#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
8305#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
8306#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
8307#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
8308#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
8309#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
8310#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
8311#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
8312#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
8313#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
8314#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
8315#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
8316#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
8317#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
8318#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
8319#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
8320#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
8321#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
8322#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
8323#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
8324#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
8325//GCEA_DRAM_RD_CLI2GRP_MAP1
8326#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
8327#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
8328#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
8329#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
8330#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
8331#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8332#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
8333#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
8334#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
8335#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
8336#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
8337#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
8338#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
8339#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
8340#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
8341#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
8342#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
8343#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
8344#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
8345#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
8346#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
8347#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
8348#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
8349#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
8350#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
8351#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
8352#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
8353#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
8354#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
8355#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
8356#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
8357#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
8358//GCEA_DRAM_WR_CLI2GRP_MAP0
8359#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
8360#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
8361#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
8362#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
8363#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
8364#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
8365#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
8366#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
8367#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
8368#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
8369#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
8370#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
8371#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
8372#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
8373#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
8374#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
8375#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
8376#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
8377#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
8378#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
8379#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
8380#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
8381#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
8382#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
8383#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
8384#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
8385#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
8386#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
8387#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
8388#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
8389#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
8390#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
8391//GCEA_DRAM_WR_CLI2GRP_MAP1
8392#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
8393#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
8394#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
8395#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
8396#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
8397#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
8398#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
8399#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
8400#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
8401#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
8402#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
8403#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
8404#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
8405#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
8406#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
8407#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
8408#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
8409#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
8410#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
8411#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
8412#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
8413#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
8414#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
8415#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
8416#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
8417#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
8418#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
8419#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
8420#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
8421#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
8422#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
8423#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
8424//GCEA_DRAM_RD_GRP2VC_MAP
8425#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
8426#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
8427#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
8428#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
8429#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
8430#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
8431#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
8432#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
8433//GCEA_DRAM_WR_GRP2VC_MAP
8434#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
8435#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
8436#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
8437#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
8438#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
8439#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
8440#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
8441#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
8442//GCEA_DRAM_RD_LAZY
8443#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
8444#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
8445#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
8446#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
8447#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
8448#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
8449#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
8450#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
8451#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
8452#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
8453#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
8454#define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
8455//GCEA_DRAM_WR_LAZY
8456#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
8457#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
8458#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
8459#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
8460#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc
8461#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14
8462#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
8463#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
8464#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
8465#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
8466#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L
8467#define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L
8468//GCEA_DRAM_RD_CAM_CNTL
8469#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
8470#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
8471#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
8472#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
8473#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
8474#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
8475#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
8476#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
8477#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
8478#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
8479#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
8480#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
8481#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
8482#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
8483#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
8484#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
8485//GCEA_DRAM_WR_CAM_CNTL
8486#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
8487#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
8488#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
8489#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
8490#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
8491#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
8492#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
8493#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
8494#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
8495#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
8496#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
8497#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
8498#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
8499#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
8500#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
8501#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
8502//GCEA_DRAM_PAGE_BURST
8503#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
8504#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
8505#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
8506#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
8507#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
8508#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
8509#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
8510#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
8511//GCEA_DRAM_RD_PRI_AGE
8512#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
8513#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
8514#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
8515#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
8516#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
8517#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
8518#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
8519#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
8520#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
8521#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
8522#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
8523#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
8524#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
8525#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
8526#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
8527#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
8528//GCEA_DRAM_WR_PRI_AGE
8529#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
8530#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
8531#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
8532#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
8533#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
8534#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
8535#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
8536#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
8537#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
8538#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
8539#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
8540#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
8541#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
8542#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
8543#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
8544#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
8545//GCEA_DRAM_RD_PRI_QUEUING
8546#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
8547#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
8548#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
8549#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
8550#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
8551#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
8552#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
8553#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
8554//GCEA_DRAM_WR_PRI_QUEUING
8555#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
8556#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
8557#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
8558#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
8559#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
8560#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
8561#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
8562#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
8563//GCEA_DRAM_RD_PRI_FIXED
8564#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
8565#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
8566#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
8567#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
8568#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
8569#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
8570#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
8571#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
8572//GCEA_DRAM_WR_PRI_FIXED
8573#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
8574#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
8575#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
8576#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
8577#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
8578#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
8579#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
8580#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
8581//GCEA_DRAM_RD_PRI_URGENCY
8582#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
8583#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
8584#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
8585#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
8586#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
8587#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
8588#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
8589#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
8590#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
8591#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
8592#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
8593#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
8594#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
8595#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
8596#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
8597#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
8598//GCEA_DRAM_WR_PRI_URGENCY
8599#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
8600#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
8601#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
8602#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
8603#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
8604#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
8605#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
8606#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
8607#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
8608#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
8609#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
8610#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
8611#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
8612#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
8613#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
8614#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
8615//GCEA_DRAM_RD_PRI_QUANT_PRI1
8616#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
8617#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
8618#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
8619#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
8620#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
8621#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
8622#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
8623#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
8624//GCEA_DRAM_RD_PRI_QUANT_PRI2
8625#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
8626#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
8627#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
8628#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
8629#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
8630#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
8631#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
8632#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
8633//GCEA_DRAM_RD_PRI_QUANT_PRI3
8634#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
8635#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
8636#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
8637#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
8638#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
8639#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
8640#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
8641#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
8642//GCEA_DRAM_WR_PRI_QUANT_PRI1
8643#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
8644#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
8645#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
8646#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
8647#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
8648#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
8649#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
8650#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
8651//GCEA_DRAM_WR_PRI_QUANT_PRI2
8652#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
8653#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
8654#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
8655#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
8656#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
8657#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
8658#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
8659#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
8660//GCEA_DRAM_WR_PRI_QUANT_PRI3
8661#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
8662#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
8663#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
8664#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
8665#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
8666#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
8667#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
8668#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
8669//GCEA_ADDRNORM_BASE_ADDR0
8670#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
8671#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
8672#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
8673#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
8674#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
8675#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
8676#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
8677#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
8678#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
8679#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
8680//GCEA_ADDRNORM_LIMIT_ADDR0
8681#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
8682#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
8683#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
8684#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
8685#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL
8686#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
8687#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
8688#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
8689//GCEA_ADDRNORM_BASE_ADDR1
8690#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
8691#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
8692#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
8693#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
8694#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
8695#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
8696#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
8697#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
8698#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
8699#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
8700//GCEA_ADDRNORM_LIMIT_ADDR1
8701#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
8702#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
8703#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
8704#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
8705#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL
8706#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
8707#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
8708#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
8709//GCEA_ADDRNORM_OFFSET_ADDR1
8710#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
8711#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
8712#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
8713#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
8714//GCEA_ADDRNORMDRAM_HOLE_CNTL
8715#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
8716#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
8717#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
8718#define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
8719//GCEA_ADDRNORMDRAM_TRICHANNEL_CFG
8720#define GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0
8721#define GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL
8722//GCEA_ADDRDEC_BANK_CFG
8723#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
8724#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
8725#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
8726#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
8727#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
8728#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
8729#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
8730#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
8731#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
8732#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
8733#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
8734#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
8735//GCEA_ADDRDEC_MISC_CFG
8736#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
8737#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
8738#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
8739#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
8740#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
8741#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
8742#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
8743#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
8744#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11
8745#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16
8746#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18
8747#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a
8748#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d
8749#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
8750#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
8751#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
8752#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
8753#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
8754#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
8755#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
8756#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L
8757#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L
8758#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L
8759#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L
8760#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L
8761#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L
8762//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0
8763#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
8764#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
8765#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
8766#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
8767#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
8768#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
8769//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1
8770#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
8771#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
8772#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
8773#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
8774#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
8775#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
8776//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2
8777#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
8778#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
8779#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
8780#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
8781#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
8782#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L
8783//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3
8784#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0
8785#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1
8786#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe
8787#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L
8788#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL
8789#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L
8790//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4
8791#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0
8792#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1
8793#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe
8794#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L
8795#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL
8796#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L
8797//GCEA_ADDRDECDRAM_ADDR_HASH_PC
8798#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0
8799#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1
8800#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe
8801#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L
8802#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL
8803#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L
8804//GCEA_ADDRDECDRAM_ADDR_HASH_PC2
8805#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0
8806#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL
8807//GCEA_ADDRDECDRAM_ADDR_HASH_CS0
8808#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0
8809#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1
8810#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L
8811#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL
8812//GCEA_ADDRDECDRAM_ADDR_HASH_CS1
8813#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0
8814#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1
8815#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L
8816#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL
8817//GCEA_ADDRDECDRAM_HARVEST_ENABLE
8818#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0
8819#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1
8820#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2
8821#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3
8822#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L
8823#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L
8824#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L
8825#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L
8826//GCEA_ADDRDEC0_BASE_ADDR_CS0
8827#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
8828#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
8829#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
8830#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
8831//GCEA_ADDRDEC0_BASE_ADDR_CS1
8832#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
8833#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
8834#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
8835#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
8836//GCEA_ADDRDEC0_BASE_ADDR_CS2
8837#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
8838#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
8839#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
8840#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
8841//GCEA_ADDRDEC0_BASE_ADDR_CS3
8842#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
8843#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
8844#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
8845#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
8846//GCEA_ADDRDEC0_BASE_ADDR_SECCS0
8847#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
8848#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
8849#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
8850#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
8851//GCEA_ADDRDEC0_BASE_ADDR_SECCS1
8852#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
8853#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
8854#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
8855#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
8856//GCEA_ADDRDEC0_BASE_ADDR_SECCS2
8857#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
8858#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
8859#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
8860#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
8861//GCEA_ADDRDEC0_BASE_ADDR_SECCS3
8862#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
8863#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
8864#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
8865#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
8866//GCEA_ADDRDEC0_ADDR_MASK_CS01
8867#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
8868#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
8869//GCEA_ADDRDEC0_ADDR_MASK_CS23
8870#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
8871#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
8872//GCEA_ADDRDEC0_ADDR_MASK_SECCS01
8873#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
8874#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
8875//GCEA_ADDRDEC0_ADDR_MASK_SECCS23
8876#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
8877#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
8878//GCEA_ADDRDEC0_ADDR_CFG_CS01
8879#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
8880#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
8881#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
8882#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
8883#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
8884#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
8885#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
8886#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
8887#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
8888#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
8889#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
8890#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
8891#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
8892#define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
8893//GCEA_ADDRDEC0_ADDR_CFG_CS23
8894#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
8895#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
8896#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
8897#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
8898#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
8899#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
8900#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
8901#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
8902#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
8903#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
8904#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
8905#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
8906#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
8907#define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
8908//GCEA_ADDRDEC0_ADDR_SEL_CS01
8909#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0
8910#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4
8911#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8
8912#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc
8913#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10
8914#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
8915#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
8916#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
8917#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
8918#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
8919#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
8920#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
8921#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
8922#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
8923//GCEA_ADDRDEC0_ADDR_SEL_CS23
8924#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0
8925#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4
8926#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8
8927#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc
8928#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10
8929#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
8930#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
8931#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
8932#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
8933#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
8934#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
8935#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
8936#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
8937#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
8938//GCEA_ADDRDEC0_COL_SEL_LO_CS01
8939#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0
8940#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4
8941#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8
8942#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc
8943#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10
8944#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14
8945#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18
8946#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
8947#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
8948#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
8949#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
8950#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
8951#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
8952#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
8953#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
8954#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
8955//GCEA_ADDRDEC0_COL_SEL_LO_CS23
8956#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0
8957#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4
8958#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8
8959#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc
8960#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10
8961#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14
8962#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18
8963#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
8964#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
8965#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
8966#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
8967#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
8968#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
8969#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
8970#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
8971#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
8972//GCEA_ADDRDEC0_COL_SEL_HI_CS01
8973#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0
8974#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4
8975#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8
8976#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc
8977#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10
8978#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14
8979#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18
8980#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
8981#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
8982#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
8983#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
8984#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
8985#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
8986#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
8987#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
8988#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
8989//GCEA_ADDRDEC0_COL_SEL_HI_CS23
8990#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0
8991#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4
8992#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8
8993#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc
8994#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10
8995#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14
8996#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18
8997#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
8998#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
8999#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
9000#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
9001#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
9002#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
9003#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
9004#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
9005#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
9006//GCEA_ADDRDEC0_RM_SEL_CS01
9007#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0
9008#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4
9009#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8
9010#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
9011#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9012#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9013#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL
9014#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L
9015#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L
9016#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
9017#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9018#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9019//GCEA_ADDRDEC0_RM_SEL_CS23
9020#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0
9021#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4
9022#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8
9023#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
9024#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9025#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9026#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL
9027#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L
9028#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L
9029#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
9030#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9031#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9032//GCEA_ADDRDEC0_RM_SEL_SECCS01
9033#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0
9034#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4
9035#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8
9036#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
9037#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9038#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9039#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
9040#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
9041#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
9042#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
9043#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9044#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9045//GCEA_ADDRDEC0_RM_SEL_SECCS23
9046#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0
9047#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4
9048#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8
9049#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
9050#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9051#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9052#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
9053#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
9054#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
9055#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
9056#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9057#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9058//GCEA_ADDRDEC1_BASE_ADDR_CS0
9059#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0
9060#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1
9061#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L
9062#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL
9063//GCEA_ADDRDEC1_BASE_ADDR_CS1
9064#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0
9065#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1
9066#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L
9067#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL
9068//GCEA_ADDRDEC1_BASE_ADDR_CS2
9069#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0
9070#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1
9071#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L
9072#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL
9073//GCEA_ADDRDEC1_BASE_ADDR_CS3
9074#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0
9075#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1
9076#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L
9077#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL
9078//GCEA_ADDRDEC1_BASE_ADDR_SECCS0
9079#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0
9080#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1
9081#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L
9082#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL
9083//GCEA_ADDRDEC1_BASE_ADDR_SECCS1
9084#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0
9085#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1
9086#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L
9087#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL
9088//GCEA_ADDRDEC1_BASE_ADDR_SECCS2
9089#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0
9090#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1
9091#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L
9092#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL
9093//GCEA_ADDRDEC1_BASE_ADDR_SECCS3
9094#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0
9095#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1
9096#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L
9097#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL
9098//GCEA_ADDRDEC1_ADDR_MASK_CS01
9099#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1
9100#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL
9101//GCEA_ADDRDEC1_ADDR_MASK_CS23
9102#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1
9103#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL
9104//GCEA_ADDRDEC1_ADDR_MASK_SECCS01
9105#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1
9106#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL
9107//GCEA_ADDRDEC1_ADDR_MASK_SECCS23
9108#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1
9109#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL
9110//GCEA_ADDRDEC1_ADDR_CFG_CS01
9111#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2
9112#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4
9113#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8
9114#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc
9115#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10
9116#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14
9117#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f
9118#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL
9119#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L
9120#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L
9121#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L
9122#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L
9123#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L
9124#define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L
9125//GCEA_ADDRDEC1_ADDR_CFG_CS23
9126#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2
9127#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4
9128#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8
9129#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc
9130#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10
9131#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14
9132#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f
9133#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL
9134#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L
9135#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L
9136#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L
9137#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L
9138#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L
9139#define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L
9140//GCEA_ADDRDEC1_ADDR_SEL_CS01
9141#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0
9142#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4
9143#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8
9144#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc
9145#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10
9146#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18
9147#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c
9148#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL
9149#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L
9150#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L
9151#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L
9152#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L
9153#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L
9154#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L
9155//GCEA_ADDRDEC1_ADDR_SEL_CS23
9156#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0
9157#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4
9158#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8
9159#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc
9160#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10
9161#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18
9162#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c
9163#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL
9164#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L
9165#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L
9166#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L
9167#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L
9168#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L
9169#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L
9170//GCEA_ADDRDEC1_COL_SEL_LO_CS01
9171#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0
9172#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4
9173#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8
9174#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc
9175#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10
9176#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14
9177#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18
9178#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c
9179#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL
9180#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L
9181#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L
9182#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L
9183#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L
9184#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L
9185#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L
9186#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L
9187//GCEA_ADDRDEC1_COL_SEL_LO_CS23
9188#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0
9189#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4
9190#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8
9191#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc
9192#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10
9193#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14
9194#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18
9195#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c
9196#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL
9197#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L
9198#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L
9199#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L
9200#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L
9201#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L
9202#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L
9203#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L
9204//GCEA_ADDRDEC1_COL_SEL_HI_CS01
9205#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0
9206#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4
9207#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8
9208#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc
9209#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10
9210#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14
9211#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18
9212#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c
9213#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL
9214#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L
9215#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L
9216#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L
9217#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L
9218#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L
9219#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L
9220#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L
9221//GCEA_ADDRDEC1_COL_SEL_HI_CS23
9222#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0
9223#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4
9224#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8
9225#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc
9226#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10
9227#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14
9228#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18
9229#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c
9230#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL
9231#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L
9232#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L
9233#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L
9234#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L
9235#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L
9236#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L
9237#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L
9238//GCEA_ADDRDEC1_RM_SEL_CS01
9239#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0
9240#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4
9241#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8
9242#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc
9243#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9244#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9245#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL
9246#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L
9247#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L
9248#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L
9249#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9250#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9251//GCEA_ADDRDEC1_RM_SEL_CS23
9252#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0
9253#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4
9254#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8
9255#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc
9256#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9257#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9258#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL
9259#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L
9260#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L
9261#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L
9262#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9263#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9264//GCEA_ADDRDEC1_RM_SEL_SECCS01
9265#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0
9266#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4
9267#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8
9268#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc
9269#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9270#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9271#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL
9272#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L
9273#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L
9274#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L
9275#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9276#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9277//GCEA_ADDRDEC1_RM_SEL_SECCS23
9278#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0
9279#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4
9280#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8
9281#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc
9282#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10
9283#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12
9284#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL
9285#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L
9286#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L
9287#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L
9288#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L
9289#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L
9290//GCEA_IO_RD_CLI2GRP_MAP0
9291#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
9292#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
9293#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
9294#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
9295#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
9296#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9297#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
9298#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
9299#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
9300#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
9301#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
9302#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
9303#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
9304#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
9305#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
9306#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
9307#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
9308#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
9309#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
9310#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
9311#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
9312#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
9313#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
9314#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
9315#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
9316#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
9317#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
9318#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
9319#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
9320#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
9321#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
9322#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
9323//GCEA_IO_RD_CLI2GRP_MAP1
9324#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
9325#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
9326#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
9327#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
9328#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
9329#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9330#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
9331#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
9332#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
9333#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
9334#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
9335#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
9336#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
9337#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
9338#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
9339#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
9340#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
9341#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
9342#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
9343#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
9344#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
9345#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
9346#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
9347#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
9348#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
9349#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
9350#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
9351#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
9352#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
9353#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
9354#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
9355#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
9356//GCEA_IO_WR_CLI2GRP_MAP0
9357#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
9358#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
9359#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
9360#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
9361#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
9362#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
9363#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
9364#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
9365#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
9366#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
9367#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
9368#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
9369#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
9370#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
9371#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
9372#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
9373#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
9374#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
9375#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
9376#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
9377#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
9378#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
9379#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
9380#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
9381#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
9382#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
9383#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
9384#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
9385#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
9386#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
9387#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
9388#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
9389//GCEA_IO_WR_CLI2GRP_MAP1
9390#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
9391#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
9392#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
9393#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
9394#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
9395#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
9396#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
9397#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
9398#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
9399#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
9400#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
9401#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
9402#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
9403#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
9404#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
9405#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
9406#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
9407#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
9408#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
9409#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
9410#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
9411#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
9412#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
9413#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
9414#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
9415#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
9416#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
9417#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
9418#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
9419#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
9420#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
9421#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
9422//GCEA_IO_RD_COMBINE_FLUSH
9423#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
9424#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
9425#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
9426#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
9427#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
9428#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
9429#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
9430#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
9431//GCEA_IO_WR_COMBINE_FLUSH
9432#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0
9433#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4
9434#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8
9435#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc
9436#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL
9437#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L
9438#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L
9439#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L
9440//GCEA_IO_GROUP_BURST
9441#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0
9442#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8
9443#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10
9444#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18
9445#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL
9446#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
9447#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
9448#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L
9449//GCEA_IO_RD_PRI_AGE
9450#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
9451#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
9452#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
9453#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
9454#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
9455#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
9456#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
9457#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
9458#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
9459#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
9460#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
9461#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
9462#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
9463#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
9464#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
9465#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
9466//GCEA_IO_WR_PRI_AGE
9467#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
9468#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
9469#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
9470#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
9471#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
9472#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
9473#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
9474#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
9475#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
9476#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
9477#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
9478#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
9479#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
9480#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
9481#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
9482#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
9483//GCEA_IO_RD_PRI_QUEUING
9484#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
9485#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
9486#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
9487#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
9488#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
9489#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
9490#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
9491#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
9492//GCEA_IO_WR_PRI_QUEUING
9493#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
9494#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
9495#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
9496#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
9497#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
9498#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
9499#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
9500#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
9501//GCEA_IO_RD_PRI_FIXED
9502#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
9503#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
9504#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
9505#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
9506#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
9507#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
9508#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
9509#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
9510//GCEA_IO_WR_PRI_FIXED
9511#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
9512#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
9513#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
9514#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
9515#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
9516#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
9517#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
9518#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
9519//GCEA_IO_RD_PRI_URGENCY
9520#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
9521#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
9522#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
9523#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
9524#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
9525#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
9526#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
9527#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
9528#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
9529#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
9530#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
9531#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
9532#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
9533#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
9534#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
9535#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
9536//GCEA_IO_WR_PRI_URGENCY
9537#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
9538#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
9539#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
9540#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
9541#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
9542#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
9543#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
9544#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
9545#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
9546#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
9547#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
9548#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
9549#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
9550#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
9551#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
9552#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
9553//GCEA_IO_RD_PRI_URGENCY_MASK
9554#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
9555#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
9556#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
9557#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
9558#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
9559#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
9560#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
9561#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
9562#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
9563#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
9564#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9565#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
9566#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
9567#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
9568#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
9569#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
9570#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
9571#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
9572#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
9573#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
9574#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
9575#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
9576#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
9577#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
9578#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
9579#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
9580#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
9581#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
9582#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
9583#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
9584#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
9585#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
9586#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
9587#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
9588#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
9589#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
9590#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
9591#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
9592#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
9593#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
9594#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
9595#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
9596#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
9597#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
9598#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
9599#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
9600#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
9601#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
9602#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
9603#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
9604#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
9605#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
9606#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
9607#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
9608#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
9609#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
9610#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
9611#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
9612#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
9613#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
9614#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
9615#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
9616#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
9617#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
9618//GCEA_IO_WR_PRI_URGENCY_MASK
9619#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0
9620#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1
9621#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2
9622#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3
9623#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4
9624#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5
9625#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6
9626#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7
9627#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8
9628#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9
9629#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa
9630#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb
9631#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc
9632#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd
9633#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe
9634#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf
9635#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10
9636#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11
9637#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12
9638#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13
9639#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14
9640#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15
9641#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16
9642#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17
9643#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18
9644#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19
9645#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a
9646#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b
9647#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c
9648#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d
9649#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e
9650#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f
9651#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L
9652#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L
9653#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L
9654#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L
9655#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L
9656#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L
9657#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L
9658#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L
9659#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L
9660#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L
9661#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L
9662#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L
9663#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L
9664#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L
9665#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L
9666#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L
9667#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L
9668#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L
9669#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L
9670#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L
9671#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L
9672#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L
9673#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L
9674#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L
9675#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L
9676#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L
9677#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L
9678#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L
9679#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L
9680#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L
9681#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L
9682#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L
9683//GCEA_IO_RD_PRI_QUANT_PRI1
9684#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
9685#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
9686#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
9687#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
9688#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
9689#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
9690#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
9691#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
9692//GCEA_IO_RD_PRI_QUANT_PRI2
9693#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
9694#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
9695#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
9696#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
9697#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
9698#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
9699#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
9700#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
9701//GCEA_IO_RD_PRI_QUANT_PRI3
9702#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
9703#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
9704#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
9705#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
9706#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
9707#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
9708#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
9709#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
9710//GCEA_IO_WR_PRI_QUANT_PRI1
9711#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
9712#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
9713#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
9714#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
9715#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
9716#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
9717#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
9718#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
9719//GCEA_IO_WR_PRI_QUANT_PRI2
9720#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
9721#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
9722#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
9723#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
9724#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
9725#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
9726#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
9727#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
9728//GCEA_IO_WR_PRI_QUANT_PRI3
9729#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
9730#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
9731#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
9732#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
9733#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
9734#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
9735#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
9736#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
9737//GCEA_SDP_ARB_DRAM
9738#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0
9739#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8
9740#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10
9741#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11
9742#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12
9743#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13
9744#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14
9745#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL
9746#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L
9747#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L
9748#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L
9749#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L
9750#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L
9751#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L
9752//GCEA_SDP_ARB_FINAL
9753#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0
9754#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5
9755#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa
9756#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf
9757#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11
9758#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12
9759#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13
9760#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14
9761#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15
9762#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16
9763#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17
9764#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18
9765#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19
9766#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a
9767#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL
9768#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L
9769#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L
9770#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L
9771#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L
9772#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L
9773#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L
9774#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L
9775#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L
9776#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L
9777#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L
9778#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L
9779#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L
9780#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L
9781//GCEA_SDP_DRAM_PRIORITY
9782#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
9783#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
9784#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
9785#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
9786#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
9787#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
9788#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
9789#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
9790#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
9791#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
9792#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
9793#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
9794#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
9795#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
9796#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
9797#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
9798//GCEA_SDP_IO_PRIORITY
9799#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0
9800#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4
9801#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8
9802#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc
9803#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10
9804#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14
9805#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18
9806#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c
9807#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL
9808#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L
9809#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L
9810#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L
9811#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L
9812#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L
9813#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L
9814#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L
9815//GCEA_SDP_CREDITS
9816#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0
9817#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8
9818#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10
9819#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18
9820#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL
9821#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L
9822#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L
9823#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L
9824//GCEA_SDP_TAG_RESERVE0
9825#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0
9826#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8
9827#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10
9828#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18
9829#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL
9830#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L
9831#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L
9832#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L
9833//GCEA_SDP_TAG_RESERVE1
9834#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0
9835#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8
9836#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10
9837#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18
9838#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL
9839#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L
9840#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L
9841#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L
9842//GCEA_SDP_VCC_RESERVE0
9843#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0
9844#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6
9845#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc
9846#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12
9847#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18
9848#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
9849#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
9850#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
9851#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
9852#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
9853//GCEA_SDP_VCC_RESERVE1
9854#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0
9855#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6
9856#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc
9857#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
9858#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
9859#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
9860#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
9861#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
9862//GCEA_SDP_VCD_RESERVE0
9863#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0
9864#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6
9865#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc
9866#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12
9867#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18
9868#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL
9869#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L
9870#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
9871#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L
9872#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L
9873//GCEA_SDP_VCD_RESERVE1
9874#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0
9875#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6
9876#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc
9877#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f
9878#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL
9879#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L
9880#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L
9881#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L
9882//GCEA_SDP_REQ_CNTL
9883#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0
9884#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1
9885#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2
9886#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3
9887#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4
9888#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L
9889#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L
9890#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L
9891#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L
9892#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L
9893//GCEA_MISC
9894#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0
9895#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1
9896#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2
9897#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3
9898#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4
9899#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5
9900#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6
9901#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7
9902#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8
9903#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9
9904#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa
9905#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb
9906#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc
9907#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd
9908#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe
9909#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf
9910#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11
9911#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13
9912#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15
9913#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a
9914#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b
9915#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c
9916#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d
9917#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e
9918#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f
9919#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L
9920#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L
9921#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L
9922#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L
9923#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L
9924#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L
9925#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L
9926#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L
9927#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L
9928#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L
9929#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L
9930#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L
9931#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L
9932#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L
9933#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L
9934#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L
9935#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L
9936#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L
9937#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L
9938#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L
9939#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L
9940#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L
9941#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L
9942#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L
9943#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L
9944//GCEA_LATENCY_SAMPLING
9945#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0
9946#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1
9947#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2
9948#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3
9949#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4
9950#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5
9951#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6
9952#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7
9953#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8
9954#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9
9955#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa
9956#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb
9957#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc
9958#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd
9959#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe
9960#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16
9961#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L
9962#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L
9963#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L
9964#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L
9965#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L
9966#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L
9967#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L
9968#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L
9969#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L
9970#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L
9971#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L
9972#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L
9973#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L
9974#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L
9975#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L
9976#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L
9977//GCEA_PERFCOUNTER_LO
9978#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
9979#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
9980//GCEA_PERFCOUNTER_HI
9981#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
9982#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
9983#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
9984#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
9985//GCEA_PERFCOUNTER0_CFG
9986#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
9987#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
9988#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
9989#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
9990#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
9991#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
9992#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
9993#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
9994#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
9995#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
9996//GCEA_PERFCOUNTER1_CFG
9997#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
9998#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
9999#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
10000#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
10001#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
10002#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
10003#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
10004#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
10005#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
10006#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
10007
10008
10009// addressBlock: gc_tcdec
10010//TCP_INVALIDATE
10011#define TCP_INVALIDATE__START__SHIFT 0x0
10012#define TCP_INVALIDATE__START_MASK 0x00000001L
10013//TCP_STATUS
10014#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
10015#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
10016#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
10017#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
10018#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
10019#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
10020#define TCP_STATUS__READ_BUSY__SHIFT 0x6
10021#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
10022#define TCP_STATUS__VM_BUSY__SHIFT 0x8
10023#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L
10024#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L
10025#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L
10026#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L
10027#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L
10028#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L
10029#define TCP_STATUS__READ_BUSY_MASK 0x00000040L
10030#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L
10031#define TCP_STATUS__VM_BUSY_MASK 0x00000100L
10032//TCP_CNTL
10033#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
10034#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
10035#define TCP_CNTL__L1_SIZE__SHIFT 0x2
10036#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
10037#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
10038#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
10039#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
10040#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
10041#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
10042#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e
10043#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L
10044#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L
10045#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL
10046#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L
10047#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L
10048#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L
10049#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L
10050#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L
10051#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L
10052#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L
10053//TCP_CHAN_STEER_LO
10054#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
10055#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
10056#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
10057#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
10058#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
10059#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
10060#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
10061#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
10062#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL
10063#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L
10064#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L
10065#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L
10066#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L
10067#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L
10068#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L
10069#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L
10070//TCP_CHAN_STEER_HI
10071#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
10072#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
10073#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
10074#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
10075#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
10076#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
10077#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
10078#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
10079#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL
10080#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L
10081#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L
10082#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L
10083#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L
10084#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L
10085#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L
10086#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L
10087//TCP_ADDR_CONFIG
10088#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
10089#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
10090#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
10091#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
10092#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL
10093#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L
10094#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L
10095#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L
10096//TCP_CREDIT
10097#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
10098#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
10099#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
10100#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL
10101#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L
10102#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L
10103//TCP_BUFFER_ADDR_HASH_CNTL
10104#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
10105#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
10106#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
10107#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
10108#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L
10109#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L
10110#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L
10111#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L
10112//TC_CFG_L1_LOAD_POLICY0
10113#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
10114#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
10115#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
10116#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
10117#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
10118#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10119#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
10120#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
10121#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
10122#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
10123#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
10124#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
10125#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
10126#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
10127#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
10128#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
10129#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
10130#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
10131#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
10132#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
10133#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
10134#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
10135#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
10136#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
10137#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
10138#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
10139#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
10140#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
10141#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
10142#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
10143#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
10144#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
10145//TC_CFG_L1_LOAD_POLICY1
10146#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
10147#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
10148#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
10149#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
10150#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
10151#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10152#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
10153#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
10154#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
10155#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
10156#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
10157#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
10158#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
10159#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
10160#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
10161#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
10162#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
10163#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
10164#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
10165#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
10166#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
10167#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
10168#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
10169#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
10170#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
10171#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
10172#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
10173#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
10174#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
10175#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
10176#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
10177#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
10178//TC_CFG_L1_STORE_POLICY
10179#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
10180#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
10181#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
10182#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
10183#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
10184#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
10185#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
10186#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
10187#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
10188#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
10189#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
10190#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
10191#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
10192#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
10193#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
10194#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
10195#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
10196#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
10197#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
10198#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
10199#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
10200#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
10201#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
10202#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
10203#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
10204#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
10205#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
10206#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
10207#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
10208#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
10209#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
10210#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
10211#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L
10212#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L
10213#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L
10214#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L
10215#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L
10216#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L
10217#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L
10218#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L
10219#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L
10220#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L
10221#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L
10222#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L
10223#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L
10224#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L
10225#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L
10226#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L
10227#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L
10228#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L
10229#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L
10230#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L
10231#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L
10232#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L
10233#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L
10234#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L
10235#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L
10236#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L
10237#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L
10238#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L
10239#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L
10240#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L
10241#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L
10242#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L
10243//TC_CFG_L2_LOAD_POLICY0
10244#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
10245#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
10246#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
10247#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
10248#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
10249#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
10250#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
10251#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
10252#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
10253#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
10254#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
10255#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
10256#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
10257#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
10258#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
10259#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
10260#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L
10261#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL
10262#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L
10263#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L
10264#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L
10265#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L
10266#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L
10267#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L
10268#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L
10269#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L
10270#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L
10271#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L
10272#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L
10273#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L
10274#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L
10275#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L
10276//TC_CFG_L2_LOAD_POLICY1
10277#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
10278#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
10279#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
10280#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
10281#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
10282#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
10283#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
10284#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
10285#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
10286#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
10287#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
10288#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
10289#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
10290#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
10291#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
10292#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
10293#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L
10294#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL
10295#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L
10296#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L
10297#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L
10298#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L
10299#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L
10300#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L
10301#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L
10302#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L
10303#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L
10304#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L
10305#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L
10306#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L
10307#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L
10308#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L
10309//TC_CFG_L2_STORE_POLICY0
10310#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
10311#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
10312#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
10313#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
10314#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
10315#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
10316#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
10317#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
10318#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
10319#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
10320#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
10321#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
10322#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
10323#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
10324#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
10325#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
10326#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L
10327#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL
10328#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L
10329#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L
10330#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L
10331#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L
10332#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L
10333#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L
10334#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L
10335#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L
10336#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L
10337#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L
10338#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L
10339#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L
10340#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L
10341#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L
10342//TC_CFG_L2_STORE_POLICY1
10343#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
10344#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
10345#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
10346#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
10347#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
10348#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
10349#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
10350#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
10351#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
10352#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
10353#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
10354#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
10355#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
10356#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
10357#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
10358#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
10359#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L
10360#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL
10361#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L
10362#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L
10363#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L
10364#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L
10365#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L
10366#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L
10367#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L
10368#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L
10369#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L
10370#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L
10371#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L
10372#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L
10373#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L
10374#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L
10375//TC_CFG_L2_ATOMIC_POLICY
10376#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
10377#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
10378#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
10379#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
10380#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
10381#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
10382#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
10383#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
10384#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
10385#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
10386#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
10387#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
10388#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
10389#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
10390#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
10391#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
10392#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L
10393#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL
10394#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L
10395#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L
10396#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L
10397#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L
10398#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L
10399#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L
10400#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L
10401#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L
10402#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L
10403#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L
10404#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L
10405#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L
10406#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L
10407#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L
10408//TC_CFG_L1_VOLATILE
10409#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
10410#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL
10411//TC_CFG_L2_VOLATILE
10412#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
10413#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL
10414//TCI_STATUS
10415#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
10416#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L
10417//TCI_CNTL_1
10418#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
10419#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
10420#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
10421#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL
10422#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L
10423#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L
10424//TCI_CNTL_2
10425#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
10426#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
10427#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L
10428#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL
10429//TCC_CTRL
10430#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
10431#define TCC_CTRL__RATE__SHIFT 0x2
10432#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
10433#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
10434#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
10435#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
10436#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15
10437#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
10438#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
10439#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
10440#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L
10441#define TCC_CTRL__RATE_MASK 0x0000000CL
10442#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L
10443#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L
10444#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L
10445#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L
10446#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L
10447#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L
10448#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L
10449#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L
10450//TCC_CTRL2
10451#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0
10452#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL
10453//TCC_REDUNDANCY
10454#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
10455#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
10456#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L
10457#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L
10458//TCC_EXE_DISABLE
10459#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
10460#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L
10461//TCC_DSM_CNTL
10462#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0
10463#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
10464#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3
10465#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
10466#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6
10467#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
10468#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9
10469#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
10470#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc
10471#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
10472#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf
10473#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
10474#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12
10475#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
10476#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15
10477#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
10478#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18
10479#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
10480#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b
10481#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
10482#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L
10483#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
10484#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L
10485#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
10486#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L
10487#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
10488#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L
10489#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
10490#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L
10491#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
10492#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L
10493#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
10494#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L
10495#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
10496#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L
10497#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
10498#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L
10499#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
10500#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L
10501#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
10502//TCC_DSM_CNTLA
10503#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0
10504#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
10505#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3
10506#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
10507#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6
10508#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8
10509#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9
10510#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb
10511#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc
10512#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe
10513#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf
10514#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11
10515#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12
10516#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14
10517#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15
10518#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17
10519#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18
10520#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a
10521#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b
10522#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d
10523#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L
10524#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
10525#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L
10526#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
10527#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L
10528#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L
10529#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L
10530#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L
10531#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L
10532#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L
10533#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L
10534#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L
10535#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L
10536#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L
10537#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L
10538#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L
10539#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L
10540#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L
10541#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L
10542#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L
10543//TCC_DSM_CNTL2
10544#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0
10545#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2
10546#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3
10547#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5
10548#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6
10549#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8
10550#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9
10551#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb
10552#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc
10553#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe
10554#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf
10555#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11
10556#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12
10557#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14
10558#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15
10559#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17
10560#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
10561#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L
10562#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L
10563#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L
10564#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L
10565#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L
10566#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L
10567#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L
10568#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L
10569#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L
10570#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L
10571#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L
10572#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L
10573#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L
10574#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L
10575#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L
10576#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L
10577#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
10578//TCC_DSM_CNTL2A
10579#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0
10580#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2
10581#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3
10582#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5
10583#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6
10584#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8
10585#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9
10586#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb
10587#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
10588#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe
10589#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf
10590#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11
10591#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12
10592#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14
10593#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15
10594#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17
10595#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
10596#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
10597#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b
10598#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d
10599#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L
10600#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L
10601#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L
10602#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L
10603#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L
10604#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L
10605#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L
10606#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L
10607#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
10608#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
10609#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L
10610#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L
10611#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L
10612#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L
10613#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L
10614#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L
10615#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
10616#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
10617#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L
10618#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L
10619//TCC_DSM_CNTL2B
10620#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
10621#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2
10622#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3
10623#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5
10624#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
10625#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
10626#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L
10627#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L
10628//TCC_WBINVL2
10629#define TCC_WBINVL2__DONE__SHIFT 0x4
10630#define TCC_WBINVL2__DONE_MASK 0x00000010L
10631//TCC_SOFT_RESET
10632#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0
10633#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L
10634//TCA_CTRL
10635#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
10636#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4
10637#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5
10638#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6
10639#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7
10640#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL
10641#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L
10642#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L
10643#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L
10644#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L
10645//TCA_BURST_MASK
10646#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0
10647#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL
10648//TCA_BURST_CTRL
10649#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0
10650#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3
10651#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4
10652#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5
10653#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6
10654#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7
10655#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8
10656#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9
10657#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa
10658#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb
10659#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc
10660#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd
10661#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe
10662#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L
10663#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L
10664#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L
10665#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L
10666#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L
10667#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L
10668#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L
10669#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L
10670#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L
10671#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L
10672#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L
10673#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L
10674#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L
10675//TCA_DSM_CNTL
10676#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0
10677#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
10678#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3
10679#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
10680#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L
10681#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L
10682#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L
10683#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L
10684//TCA_DSM_CNTL2
10685#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0
10686#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2
10687#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3
10688#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5
10689#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
10690#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L
10691#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L
10692#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L
10693#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L
10694#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
10695
10696
10697// addressBlock: gc_shdec
10698//SPI_SHADER_PGM_RSRC3_PS
10699#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
10700#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
10701#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
10702#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a
10703#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL
10704#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L
10705#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
10706#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L
10707//SPI_SHADER_PGM_LO_PS
10708#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
10709#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL
10710//SPI_SHADER_PGM_HI_PS
10711#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
10712#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL
10713//SPI_SHADER_PGM_RSRC1_PS
10714#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
10715#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
10716#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
10717#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
10718#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
10719#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
10720#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
10721#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
10722#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
10723#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
10724#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d
10725#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL
10726#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L
10727#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L
10728#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L
10729#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L
10730#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L
10731#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L
10732#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L
10733#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L
10734#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L
10735#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L
10736//SPI_SHADER_PGM_RSRC2_PS
10737#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
10738#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
10739#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
10740#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
10741#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
10742#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
10743#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19
10744#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a
10745#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b
10746#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c
10747#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L
10748#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL
10749#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L
10750#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L
10751#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L
10752#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L
10753#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L
10754#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L
10755#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L
10756#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L
10757//SPI_SHADER_USER_DATA_PS_0
10758#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
10759#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL
10760//SPI_SHADER_USER_DATA_PS_1
10761#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
10762#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL
10763//SPI_SHADER_USER_DATA_PS_2
10764#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
10765#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL
10766//SPI_SHADER_USER_DATA_PS_3
10767#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
10768#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL
10769//SPI_SHADER_USER_DATA_PS_4
10770#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
10771#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL
10772//SPI_SHADER_USER_DATA_PS_5
10773#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
10774#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL
10775//SPI_SHADER_USER_DATA_PS_6
10776#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
10777#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL
10778//SPI_SHADER_USER_DATA_PS_7
10779#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
10780#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL
10781//SPI_SHADER_USER_DATA_PS_8
10782#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
10783#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL
10784//SPI_SHADER_USER_DATA_PS_9
10785#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
10786#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL
10787//SPI_SHADER_USER_DATA_PS_10
10788#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
10789#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL
10790//SPI_SHADER_USER_DATA_PS_11
10791#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
10792#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL
10793//SPI_SHADER_USER_DATA_PS_12
10794#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
10795#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL
10796//SPI_SHADER_USER_DATA_PS_13
10797#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
10798#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL
10799//SPI_SHADER_USER_DATA_PS_14
10800#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
10801#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL
10802//SPI_SHADER_USER_DATA_PS_15
10803#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
10804#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL
10805//SPI_SHADER_USER_DATA_PS_16
10806#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0
10807#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL
10808//SPI_SHADER_USER_DATA_PS_17
10809#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0
10810#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL
10811//SPI_SHADER_USER_DATA_PS_18
10812#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0
10813#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL
10814//SPI_SHADER_USER_DATA_PS_19
10815#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0
10816#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL
10817//SPI_SHADER_USER_DATA_PS_20
10818#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0
10819#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL
10820//SPI_SHADER_USER_DATA_PS_21
10821#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0
10822#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL
10823//SPI_SHADER_USER_DATA_PS_22
10824#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0
10825#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL
10826//SPI_SHADER_USER_DATA_PS_23
10827#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0
10828#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL
10829//SPI_SHADER_USER_DATA_PS_24
10830#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0
10831#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL
10832//SPI_SHADER_USER_DATA_PS_25
10833#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0
10834#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL
10835//SPI_SHADER_USER_DATA_PS_26
10836#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0
10837#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL
10838//SPI_SHADER_USER_DATA_PS_27
10839#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0
10840#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL
10841//SPI_SHADER_USER_DATA_PS_28
10842#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0
10843#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL
10844//SPI_SHADER_USER_DATA_PS_29
10845#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0
10846#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL
10847//SPI_SHADER_USER_DATA_PS_30
10848#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0
10849#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL
10850//SPI_SHADER_USER_DATA_PS_31
10851#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0
10852#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL
10853//SPI_SHADER_PGM_RSRC3_VS
10854#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
10855#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
10856#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
10857#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a
10858#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL
10859#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L
10860#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
10861#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L
10862//SPI_SHADER_LATE_ALLOC_VS
10863#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
10864#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL
10865//SPI_SHADER_PGM_LO_VS
10866#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
10867#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL
10868//SPI_SHADER_PGM_HI_VS
10869#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
10870#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL
10871//SPI_SHADER_PGM_RSRC1_VS
10872#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
10873#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
10874#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
10875#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
10876#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
10877#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
10878#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
10879#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
10880#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
10881#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
10882#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
10883#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f
10884#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL
10885#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L
10886#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L
10887#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L
10888#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L
10889#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L
10890#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x00400000L
10891#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L
10892#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L
10893#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L
10894#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000L
10895#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L
10896//SPI_SHADER_PGM_RSRC2_VS
10897#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
10898#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
10899#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
10900#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
10901#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
10902#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
10903#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
10904#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
10905#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
10906#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
10907#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16
10908#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
10909#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b
10910#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c
10911#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L
10912#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL
10913#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L
10914#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L
10915#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L
10916#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L
10917#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L
10918#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L
10919#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L
10920#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L
10921#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L
10922#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L
10923#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L
10924#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L
10925//SPI_SHADER_USER_DATA_VS_0
10926#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
10927#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL
10928//SPI_SHADER_USER_DATA_VS_1
10929#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
10930#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL
10931//SPI_SHADER_USER_DATA_VS_2
10932#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
10933#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL
10934//SPI_SHADER_USER_DATA_VS_3
10935#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
10936#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL
10937//SPI_SHADER_USER_DATA_VS_4
10938#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
10939#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL
10940//SPI_SHADER_USER_DATA_VS_5
10941#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
10942#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL
10943//SPI_SHADER_USER_DATA_VS_6
10944#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
10945#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL
10946//SPI_SHADER_USER_DATA_VS_7
10947#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
10948#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL
10949//SPI_SHADER_USER_DATA_VS_8
10950#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
10951#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL
10952//SPI_SHADER_USER_DATA_VS_9
10953#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
10954#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL
10955//SPI_SHADER_USER_DATA_VS_10
10956#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
10957#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL
10958//SPI_SHADER_USER_DATA_VS_11
10959#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
10960#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL
10961//SPI_SHADER_USER_DATA_VS_12
10962#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
10963#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL
10964//SPI_SHADER_USER_DATA_VS_13
10965#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
10966#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL
10967//SPI_SHADER_USER_DATA_VS_14
10968#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
10969#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL
10970//SPI_SHADER_USER_DATA_VS_15
10971#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
10972#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL
10973//SPI_SHADER_USER_DATA_VS_16
10974#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0
10975#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL
10976//SPI_SHADER_USER_DATA_VS_17
10977#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0
10978#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL
10979//SPI_SHADER_USER_DATA_VS_18
10980#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0
10981#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL
10982//SPI_SHADER_USER_DATA_VS_19
10983#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0
10984#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL
10985//SPI_SHADER_USER_DATA_VS_20
10986#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0
10987#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL
10988//SPI_SHADER_USER_DATA_VS_21
10989#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0
10990#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL
10991//SPI_SHADER_USER_DATA_VS_22
10992#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0
10993#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL
10994//SPI_SHADER_USER_DATA_VS_23
10995#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0
10996#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL
10997//SPI_SHADER_USER_DATA_VS_24
10998#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0
10999#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL
11000//SPI_SHADER_USER_DATA_VS_25
11001#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0
11002#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL
11003//SPI_SHADER_USER_DATA_VS_26
11004#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0
11005#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL
11006//SPI_SHADER_USER_DATA_VS_27
11007#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0
11008#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL
11009//SPI_SHADER_USER_DATA_VS_28
11010#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0
11011#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL
11012//SPI_SHADER_USER_DATA_VS_29
11013#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0
11014#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL
11015//SPI_SHADER_USER_DATA_VS_30
11016#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0
11017#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL
11018//SPI_SHADER_USER_DATA_VS_31
11019#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0
11020#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL
11021//SPI_SHADER_PGM_RSRC2_GS_VS
11022#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0
11023#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1
11024#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6
11025#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7
11026#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10
11027#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12
11028#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13
11029#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b
11030#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c
11031#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L
11032#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL
11033#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L
11034#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L
11035#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L
11036#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L
11037#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L
11038#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L
11039#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L
11040//SPI_SHADER_PGM_RSRC4_GS
11041#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0
11042#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7
11043#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
11044#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L
11045//SPI_SHADER_USER_DATA_ADDR_LO_GS
11046#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0
11047#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
11048//SPI_SHADER_USER_DATA_ADDR_HI_GS
11049#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0
11050#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL
11051//SPI_SHADER_PGM_LO_ES
11052#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
11053#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL
11054//SPI_SHADER_PGM_HI_ES
11055#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
11056#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL
11057//SPI_SHADER_PGM_RSRC3_GS
11058#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
11059#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
11060#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
11061#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a
11062#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL
11063#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L
11064#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L
11065#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L
11066//SPI_SHADER_PGM_LO_GS
11067#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
11068#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL
11069//SPI_SHADER_PGM_HI_GS
11070#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
11071#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL
11072//SPI_SHADER_PGM_RSRC1_GS
11073#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
11074#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
11075#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
11076#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
11077#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
11078#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
11079#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
11080#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
11081#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
11082#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
11083#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d
11084#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f
11085#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL
11086#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L
11087#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L
11088#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L
11089#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L
11090#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L
11091#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L
11092#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L
11093#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L
11094#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L
11095#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L
11096#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L
11097//SPI_SHADER_PGM_RSRC2_GS
11098#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
11099#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
11100#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
11101#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
11102#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10
11103#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12
11104#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13
11105#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b
11106#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c
11107#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L
11108#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL
11109#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L
11110#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L
11111#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L
11112#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L
11113#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L
11114#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L
11115#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L
11116//SPI_SHADER_USER_DATA_ES_0
11117#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
11118#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL
11119//SPI_SHADER_USER_DATA_ES_1
11120#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
11121#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL
11122//SPI_SHADER_USER_DATA_ES_2
11123#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
11124#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL
11125//SPI_SHADER_USER_DATA_ES_3
11126#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
11127#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL
11128//SPI_SHADER_USER_DATA_ES_4
11129#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
11130#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL
11131//SPI_SHADER_USER_DATA_ES_5
11132#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
11133#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL
11134//SPI_SHADER_USER_DATA_ES_6
11135#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
11136#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL
11137//SPI_SHADER_USER_DATA_ES_7
11138#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
11139#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL
11140//SPI_SHADER_USER_DATA_ES_8
11141#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
11142#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL
11143//SPI_SHADER_USER_DATA_ES_9
11144#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
11145#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL
11146//SPI_SHADER_USER_DATA_ES_10
11147#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
11148#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL
11149//SPI_SHADER_USER_DATA_ES_11
11150#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
11151#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL
11152//SPI_SHADER_USER_DATA_ES_12
11153#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
11154#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL
11155//SPI_SHADER_USER_DATA_ES_13
11156#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
11157#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL
11158//SPI_SHADER_USER_DATA_ES_14
11159#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
11160#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL
11161//SPI_SHADER_USER_DATA_ES_15
11162#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
11163#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL
11164//SPI_SHADER_USER_DATA_ES_16
11165#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0
11166#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL
11167//SPI_SHADER_USER_DATA_ES_17
11168#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0
11169#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL
11170//SPI_SHADER_USER_DATA_ES_18
11171#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0
11172#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL
11173//SPI_SHADER_USER_DATA_ES_19
11174#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0
11175#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL
11176//SPI_SHADER_USER_DATA_ES_20
11177#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0
11178#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL
11179//SPI_SHADER_USER_DATA_ES_21
11180#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0
11181#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL
11182//SPI_SHADER_USER_DATA_ES_22
11183#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0
11184#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL
11185//SPI_SHADER_USER_DATA_ES_23
11186#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0
11187#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL
11188//SPI_SHADER_USER_DATA_ES_24
11189#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0
11190#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL
11191//SPI_SHADER_USER_DATA_ES_25
11192#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0
11193#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL
11194//SPI_SHADER_USER_DATA_ES_26
11195#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0
11196#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL
11197//SPI_SHADER_USER_DATA_ES_27
11198#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0
11199#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL
11200//SPI_SHADER_USER_DATA_ES_28
11201#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0
11202#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL
11203//SPI_SHADER_USER_DATA_ES_29
11204#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0
11205#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL
11206//SPI_SHADER_USER_DATA_ES_30
11207#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0
11208#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL
11209//SPI_SHADER_USER_DATA_ES_31
11210#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0
11211#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL
11212//SPI_SHADER_PGM_RSRC4_HS
11213#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0
11214#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL
11215//SPI_SHADER_USER_DATA_ADDR_LO_HS
11216#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0
11217#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
11218//SPI_SHADER_USER_DATA_ADDR_HI_HS
11219#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0
11220#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL
11221//SPI_SHADER_PGM_LO_LS
11222#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
11223#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL
11224//SPI_SHADER_PGM_HI_LS
11225#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
11226#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL
11227//SPI_SHADER_PGM_RSRC3_HS
11228#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
11229#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
11230#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa
11231#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10
11232#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL
11233#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L
11234#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L
11235#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L
11236//SPI_SHADER_PGM_LO_HS
11237#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
11238#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL
11239//SPI_SHADER_PGM_HI_HS
11240#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
11241#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL
11242//SPI_SHADER_PGM_RSRC1_HS
11243#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
11244#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
11245#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
11246#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
11247#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
11248#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
11249#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
11250#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
11251#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
11252#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c
11253#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e
11254#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL
11255#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L
11256#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L
11257#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L
11258#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L
11259#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L
11260#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L
11261#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L
11262#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L
11263#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L
11264#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L
11265//SPI_SHADER_PGM_RSRC2_HS
11266#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
11267#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
11268#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
11269#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7
11270#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10
11271#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b
11272#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c
11273#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L
11274#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL
11275#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L
11276#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L
11277#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L
11278#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L
11279#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L
11280//SPI_SHADER_USER_DATA_LS_0
11281#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
11282#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL
11283//SPI_SHADER_USER_DATA_LS_1
11284#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
11285#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL
11286//SPI_SHADER_USER_DATA_LS_2
11287#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
11288#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL
11289//SPI_SHADER_USER_DATA_LS_3
11290#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
11291#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL
11292//SPI_SHADER_USER_DATA_LS_4
11293#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
11294#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL
11295//SPI_SHADER_USER_DATA_LS_5
11296#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
11297#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL
11298//SPI_SHADER_USER_DATA_LS_6
11299#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
11300#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL
11301//SPI_SHADER_USER_DATA_LS_7
11302#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
11303#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL
11304//SPI_SHADER_USER_DATA_LS_8
11305#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
11306#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL
11307//SPI_SHADER_USER_DATA_LS_9
11308#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
11309#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL
11310//SPI_SHADER_USER_DATA_LS_10
11311#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
11312#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL
11313//SPI_SHADER_USER_DATA_LS_11
11314#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
11315#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL
11316//SPI_SHADER_USER_DATA_LS_12
11317#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
11318#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL
11319//SPI_SHADER_USER_DATA_LS_13
11320#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
11321#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL
11322//SPI_SHADER_USER_DATA_LS_14
11323#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
11324#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL
11325//SPI_SHADER_USER_DATA_LS_15
11326#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
11327#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL
11328//SPI_SHADER_USER_DATA_LS_16
11329#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0
11330#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL
11331//SPI_SHADER_USER_DATA_LS_17
11332#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0
11333#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL
11334//SPI_SHADER_USER_DATA_LS_18
11335#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0
11336#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL
11337//SPI_SHADER_USER_DATA_LS_19
11338#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0
11339#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL
11340//SPI_SHADER_USER_DATA_LS_20
11341#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0
11342#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL
11343//SPI_SHADER_USER_DATA_LS_21
11344#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0
11345#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL
11346//SPI_SHADER_USER_DATA_LS_22
11347#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0
11348#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL
11349//SPI_SHADER_USER_DATA_LS_23
11350#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0
11351#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL
11352//SPI_SHADER_USER_DATA_LS_24
11353#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0
11354#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL
11355//SPI_SHADER_USER_DATA_LS_25
11356#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0
11357#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL
11358//SPI_SHADER_USER_DATA_LS_26
11359#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0
11360#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL
11361//SPI_SHADER_USER_DATA_LS_27
11362#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0
11363#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL
11364//SPI_SHADER_USER_DATA_LS_28
11365#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0
11366#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL
11367//SPI_SHADER_USER_DATA_LS_29
11368#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0
11369#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL
11370//SPI_SHADER_USER_DATA_LS_30
11371#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0
11372#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL
11373//SPI_SHADER_USER_DATA_LS_31
11374#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0
11375#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL
11376//SPI_SHADER_USER_DATA_COMMON_0
11377#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0
11378#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL
11379//SPI_SHADER_USER_DATA_COMMON_1
11380#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0
11381#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL
11382//SPI_SHADER_USER_DATA_COMMON_2
11383#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0
11384#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL
11385//SPI_SHADER_USER_DATA_COMMON_3
11386#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0
11387#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL
11388//SPI_SHADER_USER_DATA_COMMON_4
11389#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0
11390#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL
11391//SPI_SHADER_USER_DATA_COMMON_5
11392#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0
11393#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL
11394//SPI_SHADER_USER_DATA_COMMON_6
11395#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0
11396#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL
11397//SPI_SHADER_USER_DATA_COMMON_7
11398#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0
11399#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL
11400//SPI_SHADER_USER_DATA_COMMON_8
11401#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0
11402#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL
11403//SPI_SHADER_USER_DATA_COMMON_9
11404#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0
11405#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL
11406//SPI_SHADER_USER_DATA_COMMON_10
11407#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0
11408#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL
11409//SPI_SHADER_USER_DATA_COMMON_11
11410#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0
11411#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL
11412//SPI_SHADER_USER_DATA_COMMON_12
11413#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0
11414#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL
11415//SPI_SHADER_USER_DATA_COMMON_13
11416#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0
11417#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL
11418//SPI_SHADER_USER_DATA_COMMON_14
11419#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0
11420#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL
11421//SPI_SHADER_USER_DATA_COMMON_15
11422#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0
11423#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL
11424//SPI_SHADER_USER_DATA_COMMON_16
11425#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0
11426#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL
11427//SPI_SHADER_USER_DATA_COMMON_17
11428#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0
11429#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL
11430//SPI_SHADER_USER_DATA_COMMON_18
11431#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0
11432#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL
11433//SPI_SHADER_USER_DATA_COMMON_19
11434#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0
11435#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL
11436//SPI_SHADER_USER_DATA_COMMON_20
11437#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0
11438#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL
11439//SPI_SHADER_USER_DATA_COMMON_21
11440#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0
11441#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL
11442//SPI_SHADER_USER_DATA_COMMON_22
11443#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0
11444#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL
11445//SPI_SHADER_USER_DATA_COMMON_23
11446#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0
11447#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL
11448//SPI_SHADER_USER_DATA_COMMON_24
11449#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0
11450#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL
11451//SPI_SHADER_USER_DATA_COMMON_25
11452#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0
11453#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL
11454//SPI_SHADER_USER_DATA_COMMON_26
11455#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0
11456#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL
11457//SPI_SHADER_USER_DATA_COMMON_27
11458#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0
11459#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL
11460//SPI_SHADER_USER_DATA_COMMON_28
11461#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0
11462#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL
11463//SPI_SHADER_USER_DATA_COMMON_29
11464#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0
11465#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL
11466//SPI_SHADER_USER_DATA_COMMON_30
11467#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0
11468#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL
11469//SPI_SHADER_USER_DATA_COMMON_31
11470#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0
11471#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL
11472//COMPUTE_DISPATCH_INITIATOR
11473#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
11474#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
11475#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
11476#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
11477#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
11478#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
11479#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
11480#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
11481#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
11482#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc
11483#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
11484#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
11485#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
11486#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
11487#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
11488#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
11489#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
11490#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
11491#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
11492#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
11493#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L
11494#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
11495//COMPUTE_DIM_X
11496#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
11497#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL
11498//COMPUTE_DIM_Y
11499#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
11500#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL
11501//COMPUTE_DIM_Z
11502#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
11503#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL
11504//COMPUTE_START_X
11505#define COMPUTE_START_X__START__SHIFT 0x0
11506#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL
11507//COMPUTE_START_Y
11508#define COMPUTE_START_Y__START__SHIFT 0x0
11509#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL
11510//COMPUTE_START_Z
11511#define COMPUTE_START_Z__START__SHIFT 0x0
11512#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL
11513//COMPUTE_NUM_THREAD_X
11514#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
11515#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
11516#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL
11517#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
11518//COMPUTE_NUM_THREAD_Y
11519#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
11520#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
11521#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL
11522#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
11523//COMPUTE_NUM_THREAD_Z
11524#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
11525#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
11526#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL
11527#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L
11528//COMPUTE_PIPELINESTAT_ENABLE
11529#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
11530#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L
11531//COMPUTE_PERFCOUNT_ENABLE
11532#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
11533#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L
11534//COMPUTE_PGM_LO
11535#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
11536#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL
11537//COMPUTE_PGM_HI
11538#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
11539#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL
11540//COMPUTE_DISPATCH_PKT_ADDR_LO
11541#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0
11542#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL
11543//COMPUTE_DISPATCH_PKT_ADDR_HI
11544#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0
11545#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL
11546//COMPUTE_DISPATCH_SCRATCH_BASE_LO
11547#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0
11548#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL
11549//COMPUTE_DISPATCH_SCRATCH_BASE_HI
11550#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0
11551#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL
11552//COMPUTE_PGM_RSRC1
11553#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
11554#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
11555#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
11556#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
11557#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
11558#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
11559#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
11560#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
11561#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
11562#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
11563#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a
11564#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL
11565#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L
11566#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L
11567#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L
11568#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
11569#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
11570#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
11571#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
11572#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
11573#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
11574#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L
11575//COMPUTE_PGM_RSRC2
11576#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
11577#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
11578#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
11579#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
11580#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
11581#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
11582#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
11583#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
11584#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
11585#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
11586#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
11587#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f
11588#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
11589#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL
11590#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
11591#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
11592#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
11593#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
11594#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
11595#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
11596#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
11597#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L
11598#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L
11599#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L
11600//COMPUTE_VMID
11601#define COMPUTE_VMID__DATA__SHIFT 0x0
11602#define COMPUTE_VMID__DATA_MASK 0x0000000FL
11603//COMPUTE_RESOURCE_LIMITS
11604#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
11605#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
11606#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
11607#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
11608#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
11609#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
11610#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b
11611#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL
11612#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L
11613#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L
11614#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
11615#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
11616#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
11617#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L
11618//COMPUTE_STATIC_THREAD_MGMT_SE0
11619#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
11620#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
11621#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL
11622#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L
11623//COMPUTE_STATIC_THREAD_MGMT_SE1
11624#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
11625#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
11626#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL
11627#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L
11628//COMPUTE_TMPRING_SIZE
11629#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
11630#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
11631#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
11632#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
11633//COMPUTE_STATIC_THREAD_MGMT_SE2
11634#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
11635#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
11636#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL
11637#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L
11638//COMPUTE_STATIC_THREAD_MGMT_SE3
11639#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
11640#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
11641#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL
11642#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L
11643//COMPUTE_RESTART_X
11644#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
11645#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL
11646//COMPUTE_RESTART_Y
11647#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
11648#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL
11649//COMPUTE_RESTART_Z
11650#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
11651#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL
11652//COMPUTE_THREAD_TRACE_ENABLE
11653#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
11654#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L
11655//COMPUTE_MISC_RESERVED
11656#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
11657#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
11658#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
11659#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
11660#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
11661#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L
11662#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L
11663#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L
11664#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L
11665#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L
11666//COMPUTE_DISPATCH_ID
11667#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
11668#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL
11669//COMPUTE_THREADGROUP_ID
11670#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
11671#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL
11672//COMPUTE_RELAUNCH
11673#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
11674#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
11675#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
11676#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL
11677#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L
11678#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L
11679//COMPUTE_WAVE_RESTORE_ADDR_LO
11680#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
11681#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL
11682//COMPUTE_WAVE_RESTORE_ADDR_HI
11683#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
11684#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL
11685//COMPUTE_SHADER_CHKSUM
11686#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0
11687#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL
11688//COMPUTE_USER_DATA_0
11689#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
11690#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL
11691//COMPUTE_USER_DATA_1
11692#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
11693#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL
11694//COMPUTE_USER_DATA_2
11695#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
11696#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL
11697//COMPUTE_USER_DATA_3
11698#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
11699#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL
11700//COMPUTE_USER_DATA_4
11701#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
11702#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL
11703//COMPUTE_USER_DATA_5
11704#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
11705#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL
11706//COMPUTE_USER_DATA_6
11707#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
11708#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL
11709//COMPUTE_USER_DATA_7
11710#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
11711#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL
11712//COMPUTE_USER_DATA_8
11713#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
11714#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL
11715//COMPUTE_USER_DATA_9
11716#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
11717#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL
11718//COMPUTE_USER_DATA_10
11719#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
11720#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL
11721//COMPUTE_USER_DATA_11
11722#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
11723#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL
11724//COMPUTE_USER_DATA_12
11725#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
11726#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL
11727//COMPUTE_USER_DATA_13
11728#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
11729#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL
11730//COMPUTE_USER_DATA_14
11731#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
11732#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL
11733//COMPUTE_USER_DATA_15
11734#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
11735#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL
11736//COMPUTE_DISPATCH_END
11737#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0
11738#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL
11739//COMPUTE_NOWHERE
11740#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
11741#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL
11742
11743
11744// addressBlock: gc_cppdec
11745//CP_DFY_CNTL
11746#define CP_DFY_CNTL__POLICY__SHIFT 0x0
11747#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
11748#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a
11749#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
11750#define CP_DFY_CNTL__MODE__SHIFT 0x1d
11751#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
11752#define CP_DFY_CNTL__POLICY_MASK 0x00000001L
11753#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL
11754#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L
11755#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L
11756#define CP_DFY_CNTL__MODE_MASK 0x60000000L
11757#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L
11758//CP_DFY_STAT
11759#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
11760#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
11761#define CP_DFY_STAT__BUSY__SHIFT 0x1f
11762#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL
11763#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L
11764#define CP_DFY_STAT__BUSY_MASK 0x80000000L
11765//CP_DFY_ADDR_HI
11766#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
11767#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
11768//CP_DFY_ADDR_LO
11769#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
11770#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L
11771//CP_DFY_DATA_0
11772#define CP_DFY_DATA_0__DATA__SHIFT 0x0
11773#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL
11774//CP_DFY_DATA_1
11775#define CP_DFY_DATA_1__DATA__SHIFT 0x0
11776#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL
11777//CP_DFY_DATA_2
11778#define CP_DFY_DATA_2__DATA__SHIFT 0x0
11779#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL
11780//CP_DFY_DATA_3
11781#define CP_DFY_DATA_3__DATA__SHIFT 0x0
11782#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL
11783//CP_DFY_DATA_4
11784#define CP_DFY_DATA_4__DATA__SHIFT 0x0
11785#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL
11786//CP_DFY_DATA_5
11787#define CP_DFY_DATA_5__DATA__SHIFT 0x0
11788#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL
11789//CP_DFY_DATA_6
11790#define CP_DFY_DATA_6__DATA__SHIFT 0x0
11791#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL
11792//CP_DFY_DATA_7
11793#define CP_DFY_DATA_7__DATA__SHIFT 0x0
11794#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL
11795//CP_DFY_DATA_8
11796#define CP_DFY_DATA_8__DATA__SHIFT 0x0
11797#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL
11798//CP_DFY_DATA_9
11799#define CP_DFY_DATA_9__DATA__SHIFT 0x0
11800#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL
11801//CP_DFY_DATA_10
11802#define CP_DFY_DATA_10__DATA__SHIFT 0x0
11803#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL
11804//CP_DFY_DATA_11
11805#define CP_DFY_DATA_11__DATA__SHIFT 0x0
11806#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL
11807//CP_DFY_DATA_12
11808#define CP_DFY_DATA_12__DATA__SHIFT 0x0
11809#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL
11810//CP_DFY_DATA_13
11811#define CP_DFY_DATA_13__DATA__SHIFT 0x0
11812#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL
11813//CP_DFY_DATA_14
11814#define CP_DFY_DATA_14__DATA__SHIFT 0x0
11815#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL
11816//CP_DFY_DATA_15
11817#define CP_DFY_DATA_15__DATA__SHIFT 0x0
11818#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL
11819//CP_DFY_CMD
11820#define CP_DFY_CMD__OFFSET__SHIFT 0x0
11821#define CP_DFY_CMD__SIZE__SHIFT 0x10
11822#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL
11823#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L
11824//CP_EOPQ_WAIT_TIME
11825#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0
11826#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa
11827#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL
11828#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L
11829//CP_CPC_MGCG_SYNC_CNTL
11830#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
11831#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
11832#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL
11833#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L
11834//CPC_INT_INFO
11835#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0
11836#define CPC_INT_INFO__TYPE__SHIFT 0x10
11837#define CPC_INT_INFO__VMID__SHIFT 0x14
11838#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c
11839#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL
11840#define CPC_INT_INFO__TYPE_MASK 0x00010000L
11841#define CPC_INT_INFO__VMID_MASK 0x00F00000L
11842#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L
11843//CP_VIRT_STATUS
11844#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
11845#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL
11846//CPC_INT_ADDR
11847#define CPC_INT_ADDR__ADDR__SHIFT 0x0
11848#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL
11849//CPC_INT_PASID
11850#define CPC_INT_PASID__PASID__SHIFT 0x0
11851#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL
11852//CP_GFX_ERROR
11853#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4
11854#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5
11855#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6
11856#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7
11857#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8
11858#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9
11859#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa
11860#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb
11861#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc
11862#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd
11863#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe
11864#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf
11865#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10
11866#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11
11867#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12
11868#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13
11869#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14
11870#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15
11871#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16
11872#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17
11873#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18
11874#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19
11875#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a
11876#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b
11877#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c
11878#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d
11879#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e
11880#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f
11881#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L
11882#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L
11883#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L
11884#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L
11885#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L
11886#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L
11887#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L
11888#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L
11889#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L
11890#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L
11891#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L
11892#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L
11893#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L
11894#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L
11895#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L
11896#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L
11897#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L
11898#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L
11899#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L
11900#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L
11901#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L
11902#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L
11903#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L
11904#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L
11905#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L
11906#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L
11907#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L
11908#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L
11909//CPG_UTCL1_CNTL
11910#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
11911#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
11912#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
11913#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19
11914#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
11915#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
11916#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
11917#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
11918#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
11919#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
11920#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
11921#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
11922#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L
11923#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
11924#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
11925#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
11926#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
11927#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
11928//CPC_UTCL1_CNTL
11929#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
11930#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
11931#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19
11932#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
11933#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
11934#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
11935#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
11936#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
11937#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
11938#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
11939#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L
11940#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
11941#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
11942#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
11943#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
11944#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
11945//CPF_UTCL1_CNTL
11946#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
11947#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
11948#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
11949#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19
11950#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
11951#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
11952#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
11953#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
11954#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e
11955#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f
11956#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
11957#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
11958#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
11959#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L
11960#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
11961#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
11962#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
11963#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
11964#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L
11965#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L
11966//CP_AQL_SMM_STATUS
11967#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0
11968#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL
11969//CP_RB0_BASE
11970#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
11971#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL
11972//CP_RB_BASE
11973#define CP_RB_BASE__RB_BASE__SHIFT 0x0
11974#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL
11975//CP_RB0_CNTL
11976#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
11977#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
11978#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
11979#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
11980#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
11981#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
11982#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
11983#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
11984#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL
11985#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L
11986#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L
11987#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
11988#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
11989#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L
11990#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
11991#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
11992//CP_RB_CNTL
11993#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
11994#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
11995#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
11996#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
11997#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
11998#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
11999#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
12000#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL
12001#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L
12002#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
12003#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
12004#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L
12005#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
12006#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
12007//CP_RB_RPTR_WR
12008#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
12009#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL
12010//CP_RB0_RPTR_ADDR
12011#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
12012#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
12013//CP_RB_RPTR_ADDR
12014#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
12015#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
12016//CP_RB0_RPTR_ADDR_HI
12017#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
12018#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
12019//CP_RB_RPTR_ADDR_HI
12020#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
12021#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
12022//CP_RB0_BUFSZ_MASK
12023#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0
12024#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
12025//CP_RB_BUFSZ_MASK
12026#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0
12027#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL
12028//CP_RB_WPTR_POLL_ADDR_LO
12029#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
12030#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL
12031//CP_RB_WPTR_POLL_ADDR_HI
12032#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
12033#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL
12034//CP_INT_CNTL
12035#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
12036#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12037#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12038#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12039#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
12040#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
12041#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
12042#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
12043#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
12044#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12045#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12046#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12047#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12048#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12049#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12050#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12051#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
12052#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12053#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12054#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12055#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
12056#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
12057#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
12058#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
12059#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
12060#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12061#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12062#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12063#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12064#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12065#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12066#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12067//CP_INT_STATUS
12068#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
12069#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
12070#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10
12071#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
12072#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
12073#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
12074#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
12075#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
12076#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
12077#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
12078#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
12079#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
12080#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
12081#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
12082#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
12083#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
12084#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
12085#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
12086#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L
12087#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
12088#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L
12089#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
12090#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
12091#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L
12092#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
12093#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
12094#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
12095#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
12096#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
12097#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
12098#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
12099#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
12100//CP_DEVICE_ID
12101#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
12102#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL
12103//CP_ME0_PIPE_PRIORITY_CNTS
12104#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
12105#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
12106#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
12107#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
12108#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
12109#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
12110#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
12111#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
12112//CP_RING_PRIORITY_CNTS
12113#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
12114#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
12115#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
12116#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
12117#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
12118#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
12119#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
12120#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
12121//CP_ME0_PIPE0_PRIORITY
12122#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
12123#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
12124//CP_RING0_PRIORITY
12125#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
12126#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
12127//CP_ME0_PIPE1_PRIORITY
12128#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
12129#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
12130//CP_RING1_PRIORITY
12131#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
12132#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
12133//CP_ME0_PIPE2_PRIORITY
12134#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
12135#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
12136//CP_RING2_PRIORITY
12137#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
12138#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
12139//CP_FATAL_ERROR
12140#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0
12141#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1
12142#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2
12143#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3
12144#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4
12145#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L
12146#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L
12147#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L
12148#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L
12149#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L
12150//CP_RB_VMID
12151#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
12152#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
12153#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
12154#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL
12155#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L
12156#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L
12157//CP_ME0_PIPE0_VMID
12158#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
12159#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL
12160//CP_ME0_PIPE1_VMID
12161#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
12162#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL
12163//CP_RB0_WPTR
12164#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
12165#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
12166//CP_RB_WPTR
12167#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
12168#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
12169//CP_RB0_WPTR_HI
12170#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0
12171#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
12172//CP_RB_WPTR_HI
12173#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0
12174#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
12175//CP_RB1_WPTR
12176#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
12177#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL
12178//CP_RB1_WPTR_HI
12179#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0
12180#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL
12181//CP_RB2_WPTR
12182#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
12183#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL
12184//CP_RB_DOORBELL_CONTROL
12185#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
12186#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
12187#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
12188#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
12189#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
12190#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
12191#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
12192#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
12193//CP_RB_DOORBELL_RANGE_LOWER
12194#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
12195#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
12196//CP_RB_DOORBELL_RANGE_UPPER
12197#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
12198#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
12199//CP_MEC_DOORBELL_RANGE_LOWER
12200#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
12201#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL
12202//CP_MEC_DOORBELL_RANGE_UPPER
12203#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
12204#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL
12205//CPG_UTCL1_ERROR
12206#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
12207#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
12208//CPC_UTCL1_ERROR
12209#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0
12210#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L
12211//CP_RB1_BASE
12212#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
12213#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL
12214//CP_RB1_CNTL
12215#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
12216#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
12217#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
12218#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
12219#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
12220#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
12221#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
12222#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL
12223#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L
12224#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
12225#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
12226#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L
12227#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
12228#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
12229//CP_RB1_RPTR_ADDR
12230#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
12231#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
12232//CP_RB1_RPTR_ADDR_HI
12233#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
12234#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
12235//CP_RB2_BASE
12236#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
12237#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL
12238//CP_RB2_CNTL
12239#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
12240#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
12241#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
12242#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
12243#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
12244#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
12245#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
12246#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL
12247#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L
12248#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
12249#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L
12250#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L
12251#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
12252#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
12253//CP_RB2_RPTR_ADDR
12254#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
12255#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL
12256//CP_RB2_RPTR_ADDR_HI
12257#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
12258#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL
12259//CP_RB0_ACTIVE
12260#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0
12261#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L
12262//CP_RB_ACTIVE
12263#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0
12264#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L
12265//CP_INT_CNTL_RING0
12266#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
12267#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12268#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10
12269#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12270#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
12271#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
12272#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
12273#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
12274#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
12275#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
12276#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12277#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12278#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12279#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
12280#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
12281#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
12282#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
12283#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12284#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L
12285#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12286#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
12287#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
12288#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
12289#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
12290#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
12291#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12292#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12293#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12294#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12295#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
12296#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
12297#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
12298//CP_INT_CNTL_RING1
12299#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
12300#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12301#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10
12302#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12303#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
12304#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
12305#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
12306#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
12307#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
12308#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
12309#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12310#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12311#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12312#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
12313#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
12314#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
12315#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
12316#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12317#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L
12318#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12319#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
12320#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
12321#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
12322#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
12323#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
12324#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12325#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12326#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12327#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12328#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
12329#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
12330#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
12331//CP_INT_CNTL_RING2
12332#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
12333#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12334#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10
12335#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12336#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
12337#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
12338#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
12339#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
12340#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
12341#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
12342#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12343#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12344#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12345#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
12346#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
12347#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
12348#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L
12349#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12350#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L
12351#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12352#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L
12353#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
12354#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
12355#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L
12356#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
12357#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12358#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12359#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12360#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12361#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
12362#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
12363#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
12364//CP_INT_STATUS_RING0
12365#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
12366#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
12367#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10
12368#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
12369#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
12370#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
12371#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
12372#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
12373#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
12374#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
12375#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
12376#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
12377#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
12378#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
12379#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
12380#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
12381#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
12382#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
12383#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L
12384#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
12385#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L
12386#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L
12387#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
12388#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L
12389#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
12390#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
12391#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
12392#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
12393#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
12394#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
12395#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
12396#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
12397//CP_INT_STATUS_RING1
12398#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
12399#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
12400#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10
12401#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
12402#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
12403#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
12404#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
12405#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
12406#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
12407#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
12408#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
12409#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
12410#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
12411#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
12412#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
12413#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
12414#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
12415#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
12416#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L
12417#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
12418#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L
12419#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
12420#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
12421#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L
12422#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
12423#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
12424#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
12425#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
12426#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
12427#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
12428#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
12429#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
12430//CP_INT_STATUS_RING2
12431#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
12432#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
12433#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10
12434#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
12435#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
12436#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
12437#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
12438#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
12439#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
12440#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
12441#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
12442#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
12443#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
12444#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
12445#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
12446#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
12447#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L
12448#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
12449#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L
12450#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
12451#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L
12452#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
12453#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
12454#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L
12455#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
12456#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
12457#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
12458#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
12459#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
12460#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
12461#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
12462#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
12463//CP_PWR_CNTL
12464#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
12465#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
12466#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
12467#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
12468#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
12469#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
12470#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
12471#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
12472#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
12473#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
12474#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L
12475#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L
12476#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L
12477#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L
12478#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L
12479#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L
12480#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L
12481#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L
12482#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L
12483#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L
12484//CP_MEM_SLP_CNTL
12485#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
12486#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
12487#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
12488#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
12489#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
12490#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
12491#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
12492#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
12493#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
12494#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
12495#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
12496#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L
12497#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
12498#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
12499//CP_ECC_FIRSTOCCURRENCE
12500#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
12501#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
12502#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
12503#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
12504#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
12505#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
12506#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
12507#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L
12508#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L
12509#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L
12510#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L
12511#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L
12512//CP_ECC_FIRSTOCCURRENCE_RING0
12513#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
12514#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL
12515//CP_ECC_FIRSTOCCURRENCE_RING1
12516#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
12517#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL
12518//CP_ECC_FIRSTOCCURRENCE_RING2
12519#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
12520#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL
12521//CP_PQ_WPTR_POLL_CNTL
12522#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
12523#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d
12524#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
12525#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
12526#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL
12527#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L
12528#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L
12529#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L
12530//CP_PQ_WPTR_POLL_CNTL1
12531#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
12532#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL
12533//CP_ME1_PIPE0_INT_CNTL
12534#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12535#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12536#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12537#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12538#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12539#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12540#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12541#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12542#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12543#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12544#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12545#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12546#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12547#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12548#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12549#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12550#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12551#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12552#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12553#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12554#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12555#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12556#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12557#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12558#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12559#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12560//CP_ME1_PIPE1_INT_CNTL
12561#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12562#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12563#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12564#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12565#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12566#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12567#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12568#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12569#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12570#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12571#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12572#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12573#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12574#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12575#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12576#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12577#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12578#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12579#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12580#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12581#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12582#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12583#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12584#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12585#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12586#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12587//CP_ME1_PIPE2_INT_CNTL
12588#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12589#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12590#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12591#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12592#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12593#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12594#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12595#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12596#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12597#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12598#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12599#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12600#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12601#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12602#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12603#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12604#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12605#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12606#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12607#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12608#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12609#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12610#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12611#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12612#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12613#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12614//CP_ME1_PIPE3_INT_CNTL
12615#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12616#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12617#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12618#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12619#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12620#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12621#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12622#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12623#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12624#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12625#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12626#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12627#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12628#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12629#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12630#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12631#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12632#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12633#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12634#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12635#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12636#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12637#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12638#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12639#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12640#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12641//CP_ME2_PIPE0_INT_CNTL
12642#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12643#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12644#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12645#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12646#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12647#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12648#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12649#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12650#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12651#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12652#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12653#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12654#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12655#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12656#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12657#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12658#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12659#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12660#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12661#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12662#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12663#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12664#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12665#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12666#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12667#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12668//CP_ME2_PIPE1_INT_CNTL
12669#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12670#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12671#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12672#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12673#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12674#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12675#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12676#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12677#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12678#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12679#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12680#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12681#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12682#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12683#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12684#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12685#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12686#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12687#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12688#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12689#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12690#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12691#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12692#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12693#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12694#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12695//CP_ME2_PIPE2_INT_CNTL
12696#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12697#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12698#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12699#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12700#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12701#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12702#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12703#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12704#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12705#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12706#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12707#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12708#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12709#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12710#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12711#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12712#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12713#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12714#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12715#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12716#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12717#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12718#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12719#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12720#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12721#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12722//CP_ME2_PIPE3_INT_CNTL
12723#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
12724#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
12725#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
12726#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
12727#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
12728#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
12729#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
12730#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
12731#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
12732#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
12733#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
12734#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
12735#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
12736#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
12737#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
12738#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
12739#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
12740#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
12741#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
12742#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
12743#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
12744#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
12745#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
12746#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
12747#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
12748#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
12749//CP_ME1_PIPE0_INT_STATUS
12750#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12751#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12752#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12753#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12754#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12755#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12756#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12757#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12758#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12759#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12760#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12761#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12762#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12763#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12764#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12765#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12766#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12767#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12768#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12769#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12770#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12771#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12772#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12773#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12774#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12775#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12776//CP_ME1_PIPE1_INT_STATUS
12777#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12778#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12779#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12780#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12781#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12782#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12783#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12784#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12785#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12786#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12787#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12788#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12789#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12790#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12791#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12792#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12793#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12794#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12795#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12796#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12797#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12798#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12799#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12800#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12801#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12802#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12803//CP_ME1_PIPE2_INT_STATUS
12804#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12805#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12806#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12807#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12808#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12809#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12810#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12811#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12812#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12813#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12814#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12815#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12816#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12817#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12818#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12819#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12820#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12821#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12822#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12823#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12824#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12825#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12826#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12827#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12828#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12829#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12830//CP_ME1_PIPE3_INT_STATUS
12831#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12832#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12833#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12834#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12835#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12836#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12837#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12838#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12839#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12840#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12841#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12842#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12843#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12844#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12845#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12846#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12847#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12848#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12849#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12850#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12851#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12852#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12853#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12854#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12855#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12856#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12857//CP_ME2_PIPE0_INT_STATUS
12858#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12859#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12860#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12861#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12862#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12863#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12864#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12865#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12866#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12867#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12868#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12869#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12870#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12871#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12872#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12873#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12874#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12875#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12876#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12877#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12878#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12879#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12880#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12881#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12882#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12883#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12884//CP_ME2_PIPE1_INT_STATUS
12885#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12886#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12887#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12888#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12889#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12890#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12891#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12892#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12893#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12894#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12895#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12896#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12897#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12898#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12899#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12900#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12901#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12902#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12903#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12904#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12905#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12906#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12907#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12908#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12909#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12910#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12911//CP_ME2_PIPE2_INT_STATUS
12912#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12913#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12914#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12915#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12916#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12917#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12918#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12919#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12920#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12921#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12922#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12923#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12924#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12925#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12926#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12927#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12928#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12929#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12930#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12931#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12932#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12933#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12934#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12935#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12936#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12937#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12938//CP_ME2_PIPE3_INT_STATUS
12939#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
12940#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
12941#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
12942#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
12943#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
12944#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
12945#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
12946#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
12947#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
12948#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
12949#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
12950#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
12951#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
12952#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
12953#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
12954#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
12955#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
12956#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
12957#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
12958#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
12959#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
12960#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
12961#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
12962#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
12963#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
12964#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
12965//CP_ME1_PIPE_PRIORITY_CNTS
12966#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
12967#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
12968#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
12969#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
12970#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
12971#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
12972#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
12973#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
12974//CP_ME1_PIPE0_PRIORITY
12975#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
12976#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
12977//CP_ME1_PIPE1_PRIORITY
12978#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
12979#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
12980//CP_ME1_PIPE2_PRIORITY
12981#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
12982#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
12983//CP_ME1_PIPE3_PRIORITY
12984#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
12985#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
12986//CP_ME2_PIPE_PRIORITY_CNTS
12987#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
12988#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
12989#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
12990#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
12991#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
12992#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
12993#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
12994#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
12995//CP_ME2_PIPE0_PRIORITY
12996#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
12997#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
12998//CP_ME2_PIPE1_PRIORITY
12999#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
13000#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
13001//CP_ME2_PIPE2_PRIORITY
13002#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
13003#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
13004//CP_ME2_PIPE3_PRIORITY
13005#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
13006#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
13007//CP_CE_PRGRM_CNTR_START
13008#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
13009#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL
13010//CP_PFP_PRGRM_CNTR_START
13011#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
13012#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL
13013//CP_ME_PRGRM_CNTR_START
13014#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
13015#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL
13016//CP_MEC1_PRGRM_CNTR_START
13017#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
13018#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
13019//CP_MEC2_PRGRM_CNTR_START
13020#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
13021#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL
13022//CP_CE_INTR_ROUTINE_START
13023#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
13024#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL
13025//CP_PFP_INTR_ROUTINE_START
13026#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
13027#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL
13028//CP_ME_INTR_ROUTINE_START
13029#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
13030#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL
13031//CP_MEC1_INTR_ROUTINE_START
13032#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
13033#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
13034//CP_MEC2_INTR_ROUTINE_START
13035#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
13036#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL
13037//CP_CONTEXT_CNTL
13038#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
13039#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
13040#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
13041#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
13042#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L
13043#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L
13044#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L
13045#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L
13046//CP_MAX_CONTEXT
13047#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
13048#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L
13049//CP_IQ_WAIT_TIME1
13050#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
13051#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
13052#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
13053#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
13054#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL
13055#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L
13056#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L
13057#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L
13058//CP_IQ_WAIT_TIME2
13059#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
13060#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
13061#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
13062#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
13063#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL
13064#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L
13065#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L
13066#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L
13067//CP_RB0_BASE_HI
13068#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
13069#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
13070//CP_RB1_BASE_HI
13071#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
13072#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL
13073//CP_VMID_RESET
13074#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
13075#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL
13076//CPC_INT_CNTL
13077#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
13078#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
13079#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
13080#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
13081#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10
13082#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
13083#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
13084#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
13085#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
13086#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
13087#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
13088#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
13089#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
13090#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L
13091#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L
13092#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
13093#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L
13094#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L
13095#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
13096#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
13097#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
13098#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
13099#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
13100#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
13101#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
13102#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
13103//CPC_INT_STATUS
13104#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
13105#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
13106#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
13107#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
13108#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10
13109#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
13110#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
13111#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
13112#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
13113#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
13114#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
13115#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
13116#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
13117#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L
13118#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L
13119#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L
13120#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L
13121#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L
13122#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L
13123#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L
13124#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L
13125#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L
13126#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L
13127#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L
13128#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L
13129#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L
13130//CP_VMID_PREEMPT
13131#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
13132#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
13133#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL
13134#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L
13135//CPC_INT_CNTX_ID
13136#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
13137#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
13138//CP_PQ_STATUS
13139#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
13140#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
13141#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
13142#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
13143//CP_CPC_IC_BASE_LO
13144#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
13145#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
13146//CP_CPC_IC_BASE_HI
13147#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
13148#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
13149//CP_CPC_IC_BASE_CNTL
13150#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
13151#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
13152#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL
13153#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L
13154//CP_CPC_IC_OP_CNTL
13155#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
13156#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
13157#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
13158#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
13159#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
13160#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
13161//CP_MEC1_F32_INT_DIS
13162#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
13163#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
13164#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
13165#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
13166#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
13167#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13168#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
13169#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
13170#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
13171#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
13172#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
13173#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
13174#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
13175#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
13176#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
13177#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
13178#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
13179#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
13180//CP_MEC2_F32_INT_DIS
13181#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
13182#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
13183#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
13184#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
13185#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
13186#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa
13187#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb
13188#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc
13189#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe
13190#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L
13191#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L
13192#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L
13193#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L
13194#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L
13195#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L
13196#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L
13197#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L
13198#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L
13199//CP_VMID_STATUS
13200#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
13201#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
13202#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL
13203#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L
13204
13205
13206// addressBlock: gc_cppdec2
13207//CP_RB_DOORBELL_CONTROL_SCH_0
13208#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2
13209#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e
13210#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f
13211#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13212#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L
13213#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L
13214//CP_RB_DOORBELL_CONTROL_SCH_1
13215#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2
13216#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e
13217#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f
13218#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13219#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L
13220#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L
13221//CP_RB_DOORBELL_CONTROL_SCH_2
13222#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2
13223#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e
13224#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f
13225#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13226#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L
13227#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L
13228//CP_RB_DOORBELL_CONTROL_SCH_3
13229#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2
13230#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e
13231#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f
13232#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13233#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L
13234#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L
13235//CP_RB_DOORBELL_CONTROL_SCH_4
13236#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2
13237#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e
13238#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f
13239#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13240#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L
13241#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L
13242//CP_RB_DOORBELL_CONTROL_SCH_5
13243#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2
13244#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e
13245#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f
13246#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13247#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L
13248#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L
13249//CP_RB_DOORBELL_CONTROL_SCH_6
13250#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2
13251#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e
13252#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f
13253#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13254#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L
13255#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L
13256//CP_RB_DOORBELL_CONTROL_SCH_7
13257#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2
13258#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e
13259#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f
13260#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
13261#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L
13262#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L
13263//CP_RB_DOORBELL_CLEAR
13264#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0
13265#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8
13266#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9
13267#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa
13268#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb
13269#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc
13270#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd
13271#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L
13272#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L
13273#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L
13274#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L
13275#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L
13276#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L
13277#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L
13278//CP_GFX_MQD_CONTROL
13279#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0
13280#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
13281#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
13282#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL
13283#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
13284#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
13285//CP_GFX_MQD_BASE_ADDR
13286#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
13287#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
13288//CP_GFX_MQD_BASE_ADDR_HI
13289#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
13290#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
13291//CP_RB_STATUS
13292#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0
13293#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1
13294#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L
13295#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L
13296//CPG_UTCL1_STATUS
13297#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
13298#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
13299#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
13300#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
13301#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
13302#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
13303#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
13304#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
13305#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
13306#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
13307#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
13308#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
13309//CPC_UTCL1_STATUS
13310#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
13311#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
13312#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
13313#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
13314#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
13315#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
13316#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
13317#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
13318#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
13319#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
13320#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
13321#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
13322//CPF_UTCL1_STATUS
13323#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
13324#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
13325#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
13326#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
13327#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
13328#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
13329#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
13330#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
13331#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
13332#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
13333#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
13334#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
13335//CP_SD_CNTL
13336#define CP_SD_CNTL__CPF_EN__SHIFT 0x0
13337#define CP_SD_CNTL__CPG_EN__SHIFT 0x1
13338#define CP_SD_CNTL__CPC_EN__SHIFT 0x2
13339#define CP_SD_CNTL__RLC_EN__SHIFT 0x3
13340#define CP_SD_CNTL__SPI_EN__SHIFT 0x4
13341#define CP_SD_CNTL__WD_EN__SHIFT 0x5
13342#define CP_SD_CNTL__IA_EN__SHIFT 0x6
13343#define CP_SD_CNTL__PA_EN__SHIFT 0x7
13344#define CP_SD_CNTL__RMI_EN__SHIFT 0x8
13345#define CP_SD_CNTL__EA_EN__SHIFT 0x9
13346#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L
13347#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L
13348#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L
13349#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L
13350#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L
13351#define CP_SD_CNTL__WD_EN_MASK 0x00000020L
13352#define CP_SD_CNTL__IA_EN_MASK 0x00000040L
13353#define CP_SD_CNTL__PA_EN_MASK 0x00000080L
13354#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L
13355#define CP_SD_CNTL__EA_EN_MASK 0x00000200L
13356//CP_SOFT_RESET_CNTL
13357#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0
13358#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1
13359#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2
13360#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3
13361#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4
13362#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5
13363#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6
13364#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L
13365#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L
13366#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L
13367#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L
13368#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L
13369#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L
13370#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L
13371//CP_CPC_GFX_CNTL
13372#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0
13373#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3
13374#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5
13375#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7
13376#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L
13377#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L
13378#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L
13379#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L
13380
13381
13382// addressBlock: gc_spipdec
13383//SPI_ARB_PRIORITY
13384#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
13385#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
13386#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
13387#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
13388#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
13389#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
13390#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
13391#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
13392#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L
13393#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L
13394#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L
13395#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L
13396#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L
13397#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L
13398#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L
13399#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L
13400//SPI_ARB_CYCLES_0
13401#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
13402#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
13403#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL
13404#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L
13405//SPI_ARB_CYCLES_1
13406#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
13407#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
13408#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL
13409#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L
13410//SPI_CDBG_SYS_GFX
13411#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
13412#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
13413#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
13414#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
13415#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
13416#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
13417#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
13418#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L
13419#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x0002L
13420#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L
13421#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x0008L
13422#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L
13423#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x0020L
13424#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L
13425//SPI_CDBG_SYS_HP3D
13426#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
13427#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
13428#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
13429#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
13430#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
13431#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
13432#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L
13433#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x0002L
13434#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L
13435#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x0008L
13436#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L
13437#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x0020L
13438//SPI_CDBG_SYS_CS0
13439#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
13440#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
13441#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
13442#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
13443#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL
13444#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L
13445#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L
13446#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L
13447//SPI_CDBG_SYS_CS1
13448#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
13449#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
13450#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
13451#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
13452#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0x000000FFL
13453#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0x0000FF00L
13454#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0x00FF0000L
13455#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xFF000000L
13456//SPI_WCL_PIPE_PERCENT_GFX
13457#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
13458#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
13459#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
13460#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
13461#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
13462#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL
13463#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L
13464#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L
13465#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L
13466#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L
13467//SPI_WCL_PIPE_PERCENT_HP3D
13468#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
13469#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
13470#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
13471#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL
13472#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L
13473#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L
13474//SPI_WCL_PIPE_PERCENT_CS0
13475#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
13476#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL
13477//SPI_WCL_PIPE_PERCENT_CS1
13478#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
13479#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL
13480//SPI_WCL_PIPE_PERCENT_CS2
13481#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
13482#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL
13483//SPI_WCL_PIPE_PERCENT_CS3
13484#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
13485#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL
13486//SPI_WCL_PIPE_PERCENT_CS4
13487#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
13488#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL
13489//SPI_WCL_PIPE_PERCENT_CS5
13490#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
13491#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL
13492//SPI_WCL_PIPE_PERCENT_CS6
13493#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
13494#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL
13495//SPI_WCL_PIPE_PERCENT_CS7
13496#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
13497#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL
13498//SPI_GDBG_WAVE_CNTL
13499#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
13500#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
13501#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L
13502#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL
13503//SPI_GDBG_TRAP_CONFIG
13504#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
13505#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
13506#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
13507#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
13508#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
13509#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
13510#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
13511#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
13512#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L
13513#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL
13514#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L
13515#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L
13516#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L
13517#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L
13518#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L
13519#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L
13520//SPI_GDBG_TRAP_MASK
13521#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
13522#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
13523#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL
13524#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L
13525//SPI_GDBG_WAVE_CNTL2
13526#define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0
13527#define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10
13528#define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL
13529#define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L
13530//SPI_GDBG_WAVE_CNTL3
13531#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0
13532#define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1
13533#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2
13534#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3
13535#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4
13536#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5
13537#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6
13538#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7
13539#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8
13540#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9
13541#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa
13542#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb
13543#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc
13544#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd
13545#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c
13546#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L
13547#define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L
13548#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L
13549#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L
13550#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L
13551#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L
13552#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L
13553#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L
13554#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L
13555#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L
13556#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L
13557#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L
13558#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L
13559#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L
13560#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L
13561//SPI_GDBG_TRAP_DATA0
13562#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
13563#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL
13564//SPI_GDBG_TRAP_DATA1
13565#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
13566#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL
13567//SPI_COMPUTE_QUEUE_RESET
13568#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
13569#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L
13570//SPI_RESOURCE_RESERVE_CU_0
13571#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
13572#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
13573#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
13574#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
13575#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
13576#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL
13577#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L
13578#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L
13579#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L
13580#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L
13581//SPI_RESOURCE_RESERVE_CU_1
13582#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
13583#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
13584#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
13585#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
13586#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
13587#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL
13588#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L
13589#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L
13590#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L
13591#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L
13592//SPI_RESOURCE_RESERVE_CU_2
13593#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
13594#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
13595#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
13596#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
13597#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
13598#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL
13599#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L
13600#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L
13601#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L
13602#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L
13603//SPI_RESOURCE_RESERVE_CU_3
13604#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
13605#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
13606#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
13607#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
13608#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
13609#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL
13610#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L
13611#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L
13612#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L
13613#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L
13614//SPI_RESOURCE_RESERVE_CU_4
13615#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
13616#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
13617#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
13618#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
13619#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
13620#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL
13621#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L
13622#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L
13623#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L
13624#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L
13625//SPI_RESOURCE_RESERVE_CU_5
13626#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
13627#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
13628#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
13629#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
13630#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
13631#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL
13632#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L
13633#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L
13634#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L
13635#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L
13636//SPI_RESOURCE_RESERVE_CU_6
13637#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
13638#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
13639#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
13640#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
13641#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
13642#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL
13643#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L
13644#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L
13645#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L
13646#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L
13647//SPI_RESOURCE_RESERVE_CU_7
13648#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
13649#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
13650#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
13651#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
13652#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
13653#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL
13654#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L
13655#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L
13656#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L
13657#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L
13658//SPI_RESOURCE_RESERVE_CU_8
13659#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
13660#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
13661#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
13662#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
13663#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
13664#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL
13665#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L
13666#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L
13667#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L
13668#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L
13669//SPI_RESOURCE_RESERVE_CU_9
13670#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
13671#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
13672#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
13673#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
13674#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
13675#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL
13676#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L
13677#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L
13678#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L
13679#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L
13680//SPI_RESOURCE_RESERVE_EN_CU_0
13681#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
13682#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
13683#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
13684#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
13685#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L
13686#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL
13687#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L
13688#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L
13689//SPI_RESOURCE_RESERVE_EN_CU_1
13690#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
13691#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
13692#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
13693#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
13694#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L
13695#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL
13696#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L
13697#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L
13698//SPI_RESOURCE_RESERVE_EN_CU_2
13699#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
13700#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
13701#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
13702#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
13703#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L
13704#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL
13705#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L
13706#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L
13707//SPI_RESOURCE_RESERVE_EN_CU_3
13708#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
13709#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
13710#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
13711#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
13712#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L
13713#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL
13714#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L
13715#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L
13716//SPI_RESOURCE_RESERVE_EN_CU_4
13717#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
13718#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
13719#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
13720#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
13721#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L
13722#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL
13723#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L
13724#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L
13725//SPI_RESOURCE_RESERVE_EN_CU_5
13726#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
13727#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
13728#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
13729#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
13730#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L
13731#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL
13732#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L
13733#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L
13734//SPI_RESOURCE_RESERVE_EN_CU_6
13735#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
13736#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
13737#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
13738#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
13739#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L
13740#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL
13741#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L
13742#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L
13743//SPI_RESOURCE_RESERVE_EN_CU_7
13744#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
13745#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
13746#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
13747#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
13748#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L
13749#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL
13750#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L
13751#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L
13752//SPI_RESOURCE_RESERVE_EN_CU_8
13753#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
13754#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
13755#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
13756#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
13757#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L
13758#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL
13759#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L
13760#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L
13761//SPI_RESOURCE_RESERVE_EN_CU_9
13762#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
13763#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
13764#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
13765#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
13766#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L
13767#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL
13768#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L
13769#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L
13770//SPI_RESOURCE_RESERVE_CU_10
13771#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
13772#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
13773#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
13774#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
13775#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
13776#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL
13777#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L
13778#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L
13779#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L
13780#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L
13781//SPI_RESOURCE_RESERVE_CU_11
13782#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
13783#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
13784#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
13785#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
13786#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
13787#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL
13788#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L
13789#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L
13790#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L
13791#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L
13792//SPI_RESOURCE_RESERVE_EN_CU_10
13793#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
13794#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
13795#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
13796#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
13797#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L
13798#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL
13799#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L
13800#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L
13801//SPI_RESOURCE_RESERVE_EN_CU_11
13802#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
13803#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
13804#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
13805#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
13806#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L
13807#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL
13808#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L
13809#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L
13810//SPI_RESOURCE_RESERVE_CU_12
13811#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
13812#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
13813#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
13814#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
13815#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
13816#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL
13817#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L
13818#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L
13819#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L
13820#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L
13821//SPI_RESOURCE_RESERVE_CU_13
13822#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
13823#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
13824#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
13825#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
13826#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
13827#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL
13828#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L
13829#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L
13830#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L
13831#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L
13832//SPI_RESOURCE_RESERVE_CU_14
13833#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
13834#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
13835#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
13836#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
13837#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
13838#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL
13839#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L
13840#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L
13841#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L
13842#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L
13843//SPI_RESOURCE_RESERVE_CU_15
13844#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
13845#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
13846#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
13847#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
13848#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
13849#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL
13850#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L
13851#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L
13852#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L
13853#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L
13854//SPI_RESOURCE_RESERVE_EN_CU_12
13855#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
13856#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
13857#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
13858#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
13859#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L
13860#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL
13861#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L
13862#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L
13863//SPI_RESOURCE_RESERVE_EN_CU_13
13864#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
13865#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
13866#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
13867#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
13868#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L
13869#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL
13870#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L
13871#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L
13872//SPI_RESOURCE_RESERVE_EN_CU_14
13873#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
13874#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
13875#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
13876#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
13877#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L
13878#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL
13879#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L
13880#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L
13881//SPI_RESOURCE_RESERVE_EN_CU_15
13882#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
13883#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
13884#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
13885#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
13886#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L
13887#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL
13888#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L
13889#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L
13890//SPI_COMPUTE_WF_CTX_SAVE
13891#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
13892#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
13893#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
13894#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
13895#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
13896#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L
13897#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L
13898#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L
13899#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L
13900#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L
13901//SPI_ARB_CNTL_0
13902#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0
13903#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4
13904#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8
13905#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL
13906#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L
13907#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L
13908
13909
13910// addressBlock: gc_cpphqddec
13911//CP_HQD_GFX_CONTROL
13912#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0
13913#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4
13914#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf
13915#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL
13916#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L
13917#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L
13918//CP_HQD_GFX_STATUS
13919#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0
13920#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL
13921//CP_HPD_ROQ_OFFSETS
13922#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
13923#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
13924#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
13925#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L
13926#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L
13927#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L
13928//CP_HPD_STATUS0
13929#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
13930#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
13931#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
13932#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10
13933#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11
13934#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12
13935#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14
13936#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f
13937#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL
13938#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L
13939#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L
13940#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L
13941#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L
13942#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L
13943#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L
13944#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L
13945//CP_HPD_UTCL1_CNTL
13946#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0
13947#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL
13948//CP_HPD_UTCL1_ERROR
13949#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0
13950#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10
13951#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14
13952#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL
13953#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L
13954#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L
13955//CP_HPD_UTCL1_ERROR_ADDR
13956#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc
13957#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L
13958//CP_MQD_BASE_ADDR
13959#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
13960#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL
13961//CP_MQD_BASE_ADDR_HI
13962#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
13963#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL
13964//CP_HQD_ACTIVE
13965#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
13966#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
13967#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L
13968#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L
13969//CP_HQD_VMID
13970#define CP_HQD_VMID__VMID__SHIFT 0x0
13971#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
13972#define CP_HQD_VMID__VQID__SHIFT 0x10
13973#define CP_HQD_VMID__VMID_MASK 0x0000000FL
13974#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L
13975#define CP_HQD_VMID__VQID_MASK 0x03FF0000L
13976//CP_HQD_PERSISTENT_STATE
13977#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
13978#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
13979#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15
13980#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16
13981#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17
13982#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18
13983#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19
13984#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a
13985#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b
13986#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
13987#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
13988#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
13989#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
13990#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L
13991#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L
13992#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L
13993#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L
13994#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L
13995#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L
13996#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L
13997#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L
13998#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L
13999#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L
14000#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L
14001#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L
14002#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L
14003//CP_HQD_PIPE_PRIORITY
14004#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
14005#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L
14006//CP_HQD_QUEUE_PRIORITY
14007#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
14008#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL
14009//CP_HQD_QUANTUM
14010#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
14011#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
14012#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
14013#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
14014#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L
14015#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L
14016#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L
14017#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L
14018//CP_HQD_PQ_BASE
14019#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
14020#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL
14021//CP_HQD_PQ_BASE_HI
14022#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
14023#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL
14024//CP_HQD_PQ_RPTR
14025#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
14026#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL
14027//CP_HQD_PQ_RPTR_REPORT_ADDR
14028#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
14029#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL
14030//CP_HQD_PQ_RPTR_REPORT_ADDR_HI
14031#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
14032#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL
14033//CP_HQD_PQ_WPTR_POLL_ADDR
14034#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3
14035#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L
14036//CP_HQD_PQ_WPTR_POLL_ADDR_HI
14037#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
14038#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL
14039//CP_HQD_PQ_DOORBELL_CONTROL
14040#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
14041#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
14042#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
14043#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
14044#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
14045#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
14046#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
14047#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L
14048#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L
14049#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL
14050#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L
14051#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L
14052#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L
14053#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L
14054//CP_HQD_PQ_CONTROL
14055#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
14056#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6
14057#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7
14058#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
14059#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe
14060#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf
14061#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10
14062#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
14063#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
14064#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17
14065#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
14066#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
14067#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
14068#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
14069#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
14070#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
14071#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
14072#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL
14073#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L
14074#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L
14075#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L
14076#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L
14077#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L
14078#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L
14079#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L
14080#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L
14081#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L
14082#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L
14083#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L
14084#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L
14085#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L
14086#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L
14087#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L
14088#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L
14089//CP_HQD_IB_BASE_ADDR
14090#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
14091#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL
14092//CP_HQD_IB_BASE_ADDR_HI
14093#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
14094#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL
14095//CP_HQD_IB_RPTR
14096#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
14097#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL
14098//CP_HQD_IB_CONTROL
14099#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
14100#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
14101#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17
14102#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
14103#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
14104#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL
14105#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L
14106#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L
14107#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L
14108#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L
14109//CP_HQD_IQ_TIMER
14110#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
14111#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
14112#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
14113#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
14114#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
14115#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
14116#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
14117#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17
14118#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
14119#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19
14120#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c
14121#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
14122#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
14123#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
14124#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL
14125#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L
14126#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L
14127#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L
14128#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L
14129#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L
14130#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L
14131#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L
14132#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L
14133#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L
14134#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L
14135#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L
14136#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L
14137#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L
14138//CP_HQD_IQ_RPTR
14139#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
14140#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL
14141//CP_HQD_DEQUEUE_REQUEST
14142#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
14143#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
14144#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
14145#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
14146#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
14147#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L
14148#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L
14149#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L
14150#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L
14151#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L
14152//CP_HQD_DMA_OFFLOAD
14153#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
14154#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
14155//CP_HQD_OFFLOAD
14156#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
14157#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
14158#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2
14159#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3
14160#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
14161#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
14162#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L
14163#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L
14164#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L
14165#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L
14166#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L
14167#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L
14168//CP_HQD_SEMA_CMD
14169#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
14170#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
14171#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L
14172#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L
14173//CP_HQD_MSG_TYPE
14174#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
14175#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
14176#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L
14177#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L
14178//CP_HQD_ATOMIC0_PREOP_LO
14179#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
14180#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
14181//CP_HQD_ATOMIC0_PREOP_HI
14182#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
14183#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
14184//CP_HQD_ATOMIC1_PREOP_LO
14185#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
14186#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
14187//CP_HQD_ATOMIC1_PREOP_HI
14188#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
14189#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
14190//CP_HQD_HQ_SCHEDULER0
14191#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
14192#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL
14193//CP_HQD_HQ_STATUS0
14194#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
14195#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
14196#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
14197#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
14198#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
14199#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
14200#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa
14201#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e
14202#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f
14203#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L
14204#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL
14205#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L
14206#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L
14207#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L
14208#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L
14209#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L
14210#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L
14211#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L
14212//CP_HQD_HQ_CONTROL0
14213#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
14214#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL
14215//CP_HQD_HQ_SCHEDULER1
14216#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
14217#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL
14218//CP_MQD_CONTROL
14219#define CP_MQD_CONTROL__VMID__SHIFT 0x0
14220#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
14221#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
14222#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
14223#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17
14224#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
14225#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL
14226#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L
14227#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L
14228#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L
14229#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L
14230#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L
14231//CP_HQD_HQ_STATUS1
14232#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
14233#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL
14234//CP_HQD_HQ_CONTROL1
14235#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
14236#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL
14237//CP_HQD_EOP_BASE_ADDR
14238#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
14239#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
14240//CP_HQD_EOP_BASE_ADDR_HI
14241#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
14242#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL
14243//CP_HQD_EOP_CONTROL
14244#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
14245#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
14246#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
14247#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
14248#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
14249#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15
14250#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16
14251#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17
14252#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
14253#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
14254#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
14255#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL
14256#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L
14257#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L
14258#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L
14259#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L
14260#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L
14261#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L
14262#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L
14263#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L
14264#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L
14265#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L
14266//CP_HQD_EOP_RPTR
14267#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
14268#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c
14269#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d
14270#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
14271#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
14272#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL
14273#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L
14274#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L
14275#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L
14276#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L
14277//CP_HQD_EOP_WPTR
14278#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
14279#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf
14280#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
14281#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL
14282#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L
14283#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L
14284//CP_HQD_EOP_EVENTS
14285#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
14286#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
14287#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL
14288#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L
14289//CP_HQD_CTX_SAVE_BASE_ADDR_LO
14290#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
14291#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L
14292//CP_HQD_CTX_SAVE_BASE_ADDR_HI
14293#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
14294#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
14295//CP_HQD_CTX_SAVE_CONTROL
14296#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
14297#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17
14298#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L
14299#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L
14300//CP_HQD_CNTL_STACK_OFFSET
14301#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
14302#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL
14303//CP_HQD_CNTL_STACK_SIZE
14304#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
14305#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L
14306//CP_HQD_WG_STATE_OFFSET
14307#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
14308#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL
14309//CP_HQD_CTX_SAVE_SIZE
14310#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
14311#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L
14312//CP_HQD_GDS_RESOURCE_STATE
14313#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
14314#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
14315#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
14316#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
14317#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L
14318#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L
14319#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L
14320#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L
14321//CP_HQD_ERROR
14322#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
14323#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5
14324#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8
14325#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9
14326#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa
14327#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb
14328#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc
14329#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd
14330#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe
14331#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf
14332#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10
14333#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11
14334#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12
14335#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13
14336#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L
14337#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L
14338#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L
14339#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L
14340#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L
14341#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L
14342#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L
14343#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L
14344#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L
14345#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L
14346#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L
14347#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L
14348#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L
14349#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L
14350//CP_HQD_EOP_WPTR_MEM
14351#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
14352#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL
14353//CP_HQD_AQL_CONTROL
14354#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0
14355#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf
14356#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10
14357#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f
14358#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL
14359#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L
14360#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L
14361#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L
14362//CP_HQD_PQ_WPTR_LO
14363#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0
14364#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL
14365//CP_HQD_PQ_WPTR_HI
14366#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0
14367#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL
14368
14369
14370// addressBlock: gc_didtdec
14371//DIDT_IND_INDEX
14372#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
14373#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL
14374//DIDT_IND_DATA
14375#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
14376#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL
14377//DIDT_INDEX_AUTO_INCR_EN
14378#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0
14379#define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L
14380
14381
14382// addressBlock: gc_gccacdec
14383//GC_CAC_CTRL_1
14384#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0
14385#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18
14386#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL
14387#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L
14388//GC_CAC_CTRL_2
14389#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0
14390#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1
14391#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2
14392#define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3
14393#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L
14394#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L
14395#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L
14396#define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L
14397//GC_CAC_INDEX_AUTO_INCR_EN
14398#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x0
14399#define GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000001L
14400//GC_CAC_AGGR_LOWER
14401#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0
14402#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL
14403//GC_CAC_AGGR_UPPER
14404#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0
14405#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL
14406//PCC_PERF_COUNTER
14407#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0
14408#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL
14409//GC_CAC_SOFT_CTRL
14410#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0
14411#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L
14412//GC_DIDT_CTRL0
14413#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
14414#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1
14415#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3
14416#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
14417#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5
14418#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
14419#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L
14420#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L
14421#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
14422#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L
14423//GC_DIDT_CTRL1
14424#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0
14425#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10
14426#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL
14427#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L
14428//GC_DIDT_CTRL2
14429#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
14430#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
14431#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
14432#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
14433#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
14434#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
14435//GC_DIDT_WEIGHT
14436#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0
14437#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8
14438#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10
14439#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18
14440#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL
14441#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L
14442#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L
14443#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L
14444//GC_EDC_CTRL
14445#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0
14446#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
14447#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
14448#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
14449#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
14450#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9
14451#define GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT 0xb
14452#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xc
14453#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x10
14454#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0x14
14455#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L
14456#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
14457#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
14458#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
14459#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
14460#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L
14461#define GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000800L
14462#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x0000F000L
14463#define GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x000F0000L
14464#define GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK 0x3FF00000L
14465//GC_EDC_THRESHOLD
14466#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
14467#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
14468//GC_DIDT_DROOP_CTRL
14469#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0
14470#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1
14471#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf
14472#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13
14473#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f
14474#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L
14475#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL
14476#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L
14477#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L
14478#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L
14479//GC_DIDT_DROOP_CTRL1
14480#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN__SHIFT 0x0
14481#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD__SHIFT 0x1
14482#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN_MASK 0x00000001L
14483#define GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD_MASK 0x00007FFEL
14484//GC_EDC_DROOP_CTRL
14485#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0
14486#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1
14487#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf
14488#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14
14489#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15
14490#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L
14491#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL
14492#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L
14493#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L
14494#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L
14495//GC_THROTTLE_CTRL
14496#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0
14497#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x2
14498#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x3
14499#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x7
14500#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0x9
14501#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT 0xa
14502#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT 0x14
14503#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT 0x19
14504#define GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT 0x1e
14505#define GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT 0x1f
14506#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L
14507#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000004L
14508#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000008L
14509#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000080L
14510#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000200L
14511#define GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK 0x000FFC00L
14512#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK 0x01F00000L
14513#define GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK 0x3E000000L
14514#define GC_THROTTLE_CTRL__INST_THROT_INCR_MASK 0x40000000L
14515#define GC_THROTTLE_CTRL__INST_THROT_DECR_MASK 0x80000000L
14516//GC_CAC_IND_INDEX
14517#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0
14518#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL
14519//GC_CAC_IND_DATA
14520#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0
14521#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL
14522//SE_CAC_IND_INDEX
14523#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0
14524#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL
14525//SE_CAC_IND_DATA
14526#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0
14527#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL
14528
14529
14530// addressBlock: gc_tcpdec
14531//TCP_WATCH0_ADDR_H
14532#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
14533#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL
14534//TCP_WATCH0_ADDR_L
14535#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
14536#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L
14537//TCP_WATCH0_CNTL
14538#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
14539#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
14540#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c
14541#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
14542#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
14543#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL
14544#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L
14545#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L
14546#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L
14547#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L
14548//TCP_WATCH1_ADDR_H
14549#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
14550#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL
14551//TCP_WATCH1_ADDR_L
14552#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
14553#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L
14554//TCP_WATCH1_CNTL
14555#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
14556#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
14557#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c
14558#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
14559#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
14560#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL
14561#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L
14562#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L
14563#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L
14564#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L
14565//TCP_WATCH2_ADDR_H
14566#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
14567#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL
14568//TCP_WATCH2_ADDR_L
14569#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
14570#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L
14571//TCP_WATCH2_CNTL
14572#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
14573#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
14574#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c
14575#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
14576#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
14577#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL
14578#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L
14579#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L
14580#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L
14581#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L
14582//TCP_WATCH3_ADDR_H
14583#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
14584#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL
14585//TCP_WATCH3_ADDR_L
14586#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
14587#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L
14588//TCP_WATCH3_CNTL
14589#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
14590#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
14591#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c
14592#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
14593#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
14594#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL
14595#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L
14596#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L
14597#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L
14598#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L
14599//TCP_GATCL1_CNTL
14600#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
14601#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
14602#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
14603#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
14604#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
14605#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L
14606#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L
14607#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L
14608#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
14609#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
14610//TCP_GATCL1_DSM_CNTL
14611#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
14612#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
14613#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
14614#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L
14615#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L
14616#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L
14617//TCP_CNTL2
14618#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
14619#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT 0x8
14620#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9
14621#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL
14622#define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK 0x00000100L
14623#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L
14624//TCP_UTCL1_CNTL1
14625#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
14626#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
14627#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
14628#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
14629#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
14630#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
14631#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
14632#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
14633#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
14634#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
14635#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
14636#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
14637#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
14638#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
14639#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
14640#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
14641#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
14642#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
14643#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
14644#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
14645#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
14646#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
14647#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
14648#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
14649#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
14650#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
14651//TCP_UTCL1_CNTL2
14652#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0
14653#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
14654#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa
14655#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
14656#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
14657#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
14658#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
14659#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
14660#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
14661#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L
14662#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
14663#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
14664#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
14665#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
14666//TCP_UTCL1_STATUS
14667#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
14668#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
14669#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
14670#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
14671#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
14672#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
14673//TCP_PERFCOUNTER_FILTER
14674#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0
14675#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1
14676#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2
14677#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5
14678#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb
14679#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf
14680#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14
14681#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16
14682#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19
14683#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a
14684#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b
14685#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c
14686#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L
14687#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L
14688#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL
14689#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L
14690#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L
14691#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L
14692#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L
14693#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L
14694#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L
14695#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L
14696#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L
14697#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L
14698//TCP_PERFCOUNTER_FILTER_EN
14699#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0
14700#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1
14701#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2
14702#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3
14703#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4
14704#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5
14705#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6
14706#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7
14707#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8
14708#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9
14709#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa
14710#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb
14711#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L
14712#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L
14713#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L
14714#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L
14715#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L
14716#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L
14717#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L
14718#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L
14719#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L
14720#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L
14721#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L
14722#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L
14723
14724
14725// addressBlock: gc_gdspdec
14726//GDS_VMID0_BASE
14727#define GDS_VMID0_BASE__BASE__SHIFT 0x0
14728#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL
14729//GDS_VMID0_SIZE
14730#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
14731#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL
14732//GDS_VMID1_BASE
14733#define GDS_VMID1_BASE__BASE__SHIFT 0x0
14734#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL
14735//GDS_VMID1_SIZE
14736#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
14737#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL
14738//GDS_VMID2_BASE
14739#define GDS_VMID2_BASE__BASE__SHIFT 0x0
14740#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL
14741//GDS_VMID2_SIZE
14742#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
14743#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL
14744//GDS_VMID3_BASE
14745#define GDS_VMID3_BASE__BASE__SHIFT 0x0
14746#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL
14747//GDS_VMID3_SIZE
14748#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
14749#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL
14750//GDS_VMID4_BASE
14751#define GDS_VMID4_BASE__BASE__SHIFT 0x0
14752#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL
14753//GDS_VMID4_SIZE
14754#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
14755#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL
14756//GDS_VMID5_BASE
14757#define GDS_VMID5_BASE__BASE__SHIFT 0x0
14758#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL
14759//GDS_VMID5_SIZE
14760#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
14761#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL
14762//GDS_VMID6_BASE
14763#define GDS_VMID6_BASE__BASE__SHIFT 0x0
14764#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL
14765//GDS_VMID6_SIZE
14766#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
14767#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL
14768//GDS_VMID7_BASE
14769#define GDS_VMID7_BASE__BASE__SHIFT 0x0
14770#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL
14771//GDS_VMID7_SIZE
14772#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
14773#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL
14774//GDS_VMID8_BASE
14775#define GDS_VMID8_BASE__BASE__SHIFT 0x0
14776#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL
14777//GDS_VMID8_SIZE
14778#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
14779#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL
14780//GDS_VMID9_BASE
14781#define GDS_VMID9_BASE__BASE__SHIFT 0x0
14782#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL
14783//GDS_VMID9_SIZE
14784#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
14785#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL
14786//GDS_VMID10_BASE
14787#define GDS_VMID10_BASE__BASE__SHIFT 0x0
14788#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL
14789//GDS_VMID10_SIZE
14790#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
14791#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL
14792//GDS_VMID11_BASE
14793#define GDS_VMID11_BASE__BASE__SHIFT 0x0
14794#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL
14795//GDS_VMID11_SIZE
14796#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
14797#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL
14798//GDS_VMID12_BASE
14799#define GDS_VMID12_BASE__BASE__SHIFT 0x0
14800#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL
14801//GDS_VMID12_SIZE
14802#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
14803#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL
14804//GDS_VMID13_BASE
14805#define GDS_VMID13_BASE__BASE__SHIFT 0x0
14806#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL
14807//GDS_VMID13_SIZE
14808#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
14809#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL
14810//GDS_VMID14_BASE
14811#define GDS_VMID14_BASE__BASE__SHIFT 0x0
14812#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL
14813//GDS_VMID14_SIZE
14814#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
14815#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL
14816//GDS_VMID15_BASE
14817#define GDS_VMID15_BASE__BASE__SHIFT 0x0
14818#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL
14819//GDS_VMID15_SIZE
14820#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
14821#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL
14822//GDS_GWS_VMID0
14823#define GDS_GWS_VMID0__BASE__SHIFT 0x0
14824#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
14825#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL
14826#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L
14827//GDS_GWS_VMID1
14828#define GDS_GWS_VMID1__BASE__SHIFT 0x0
14829#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
14830#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL
14831#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L
14832//GDS_GWS_VMID2
14833#define GDS_GWS_VMID2__BASE__SHIFT 0x0
14834#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
14835#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL
14836#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L
14837//GDS_GWS_VMID3
14838#define GDS_GWS_VMID3__BASE__SHIFT 0x0
14839#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
14840#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL
14841#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L
14842//GDS_GWS_VMID4
14843#define GDS_GWS_VMID4__BASE__SHIFT 0x0
14844#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
14845#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL
14846#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L
14847//GDS_GWS_VMID5
14848#define GDS_GWS_VMID5__BASE__SHIFT 0x0
14849#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
14850#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL
14851#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L
14852//GDS_GWS_VMID6
14853#define GDS_GWS_VMID6__BASE__SHIFT 0x0
14854#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
14855#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL
14856#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L
14857//GDS_GWS_VMID7
14858#define GDS_GWS_VMID7__BASE__SHIFT 0x0
14859#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
14860#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL
14861#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L
14862//GDS_GWS_VMID8
14863#define GDS_GWS_VMID8__BASE__SHIFT 0x0
14864#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
14865#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL
14866#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L
14867//GDS_GWS_VMID9
14868#define GDS_GWS_VMID9__BASE__SHIFT 0x0
14869#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
14870#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL
14871#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L
14872//GDS_GWS_VMID10
14873#define GDS_GWS_VMID10__BASE__SHIFT 0x0
14874#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
14875#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL
14876#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L
14877//GDS_GWS_VMID11
14878#define GDS_GWS_VMID11__BASE__SHIFT 0x0
14879#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
14880#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL
14881#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L
14882//GDS_GWS_VMID12
14883#define GDS_GWS_VMID12__BASE__SHIFT 0x0
14884#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
14885#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL
14886#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L
14887//GDS_GWS_VMID13
14888#define GDS_GWS_VMID13__BASE__SHIFT 0x0
14889#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
14890#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL
14891#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L
14892//GDS_GWS_VMID14
14893#define GDS_GWS_VMID14__BASE__SHIFT 0x0
14894#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
14895#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL
14896#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L
14897//GDS_GWS_VMID15
14898#define GDS_GWS_VMID15__BASE__SHIFT 0x0
14899#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
14900#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL
14901#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L
14902//GDS_OA_VMID0
14903#define GDS_OA_VMID0__MASK__SHIFT 0x0
14904#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
14905#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL
14906#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L
14907//GDS_OA_VMID1
14908#define GDS_OA_VMID1__MASK__SHIFT 0x0
14909#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
14910#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL
14911#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L
14912//GDS_OA_VMID2
14913#define GDS_OA_VMID2__MASK__SHIFT 0x0
14914#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
14915#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL
14916#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L
14917//GDS_OA_VMID3
14918#define GDS_OA_VMID3__MASK__SHIFT 0x0
14919#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
14920#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL
14921#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L
14922//GDS_OA_VMID4
14923#define GDS_OA_VMID4__MASK__SHIFT 0x0
14924#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
14925#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL
14926#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L
14927//GDS_OA_VMID5
14928#define GDS_OA_VMID5__MASK__SHIFT 0x0
14929#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
14930#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL
14931#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L
14932//GDS_OA_VMID6
14933#define GDS_OA_VMID6__MASK__SHIFT 0x0
14934#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
14935#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL
14936#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L
14937//GDS_OA_VMID7
14938#define GDS_OA_VMID7__MASK__SHIFT 0x0
14939#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
14940#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL
14941#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L
14942//GDS_OA_VMID8
14943#define GDS_OA_VMID8__MASK__SHIFT 0x0
14944#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
14945#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL
14946#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L
14947//GDS_OA_VMID9
14948#define GDS_OA_VMID9__MASK__SHIFT 0x0
14949#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
14950#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL
14951#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L
14952//GDS_OA_VMID10
14953#define GDS_OA_VMID10__MASK__SHIFT 0x0
14954#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
14955#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL
14956#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L
14957//GDS_OA_VMID11
14958#define GDS_OA_VMID11__MASK__SHIFT 0x0
14959#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
14960#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL
14961#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L
14962//GDS_OA_VMID12
14963#define GDS_OA_VMID12__MASK__SHIFT 0x0
14964#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
14965#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL
14966#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L
14967//GDS_OA_VMID13
14968#define GDS_OA_VMID13__MASK__SHIFT 0x0
14969#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
14970#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL
14971#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L
14972//GDS_OA_VMID14
14973#define GDS_OA_VMID14__MASK__SHIFT 0x0
14974#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
14975#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL
14976#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L
14977//GDS_OA_VMID15
14978#define GDS_OA_VMID15__MASK__SHIFT 0x0
14979#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
14980#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL
14981#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L
14982//GDS_GWS_RESET0
14983#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
14984#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
14985#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
14986#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
14987#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
14988#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
14989#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
14990#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
14991#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
14992#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
14993#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
14994#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
14995#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
14996#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
14997#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
14998#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
14999#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
15000#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
15001#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
15002#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
15003#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
15004#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
15005#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
15006#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
15007#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
15008#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
15009#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
15010#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
15011#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
15012#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
15013#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
15014#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
15015#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L
15016#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L
15017#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L
15018#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L
15019#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L
15020#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L
15021#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L
15022#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L
15023#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L
15024#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L
15025#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L
15026#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L
15027#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L
15028#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L
15029#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L
15030#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L
15031#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L
15032#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L
15033#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L
15034#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L
15035#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L
15036#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L
15037#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L
15038#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L
15039#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L
15040#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L
15041#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L
15042#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L
15043#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L
15044#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L
15045#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L
15046#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L
15047//GDS_GWS_RESET1
15048#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
15049#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
15050#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
15051#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
15052#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
15053#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
15054#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
15055#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
15056#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
15057#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
15058#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
15059#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
15060#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
15061#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
15062#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
15063#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
15064#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
15065#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
15066#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
15067#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
15068#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
15069#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
15070#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
15071#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
15072#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
15073#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
15074#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
15075#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
15076#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
15077#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
15078#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
15079#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
15080#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L
15081#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L
15082#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L
15083#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L
15084#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L
15085#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L
15086#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L
15087#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L
15088#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L
15089#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L
15090#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L
15091#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L
15092#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L
15093#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L
15094#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L
15095#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L
15096#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L
15097#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L
15098#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L
15099#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L
15100#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L
15101#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L
15102#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L
15103#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L
15104#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L
15105#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L
15106#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L
15107#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L
15108#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L
15109#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L
15110#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L
15111#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L
15112//GDS_GWS_RESOURCE_RESET
15113#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
15114#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
15115#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L
15116#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L
15117//GDS_COMPUTE_MAX_WAVE_ID
15118#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
15119#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
15120//GDS_OA_RESET_MASK
15121#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
15122#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
15123#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
15124#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3
15125#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
15126#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
15127#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
15128#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
15129#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
15130#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
15131#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
15132#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
15133#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
15134#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L
15135#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L
15136#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L
15137#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L
15138#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L
15139#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L
15140#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L
15141#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L
15142#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L
15143#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L
15144#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L
15145#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L
15146#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L
15147//GDS_OA_RESET
15148#define GDS_OA_RESET__RESET__SHIFT 0x0
15149#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
15150#define GDS_OA_RESET__RESET_MASK 0x00000001L
15151#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L
15152//GDS_ENHANCE
15153#define GDS_ENHANCE__MISC__SHIFT 0x0
15154#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
15155#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
15156#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12
15157#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13
15158#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14
15159#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15
15160#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT 0x16
15161#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT 0x17
15162#define GDS_ENHANCE__UNUSED__SHIFT 0x18
15163#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL
15164#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L
15165#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L
15166#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L
15167#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L
15168#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L
15169#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L
15170#define GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L
15171#define GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK 0x00800000L
15172#define GDS_ENHANCE__UNUSED_MASK 0xFF000000L
15173//GDS_OA_CGPG_RESTORE
15174#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
15175#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
15176#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
15177#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
15178#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
15179#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL
15180#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L
15181#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L
15182#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L
15183#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L
15184//GDS_CS_CTXSW_STATUS
15185#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
15186#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
15187#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
15188#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L
15189#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L
15190#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
15191//GDS_CS_CTXSW_CNT0
15192#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
15193#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
15194#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15195#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15196//GDS_CS_CTXSW_CNT1
15197#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
15198#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
15199#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15200#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15201//GDS_CS_CTXSW_CNT2
15202#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
15203#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
15204#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15205#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15206//GDS_CS_CTXSW_CNT3
15207#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
15208#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
15209#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15210#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15211//GDS_GFX_CTXSW_STATUS
15212#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
15213#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
15214#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
15215#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L
15216#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L
15217#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL
15218//GDS_VS_CTXSW_CNT0
15219#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
15220#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
15221#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15222#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15223//GDS_VS_CTXSW_CNT1
15224#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
15225#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
15226#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15227#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15228//GDS_VS_CTXSW_CNT2
15229#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
15230#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
15231#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15232#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15233//GDS_VS_CTXSW_CNT3
15234#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
15235#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
15236#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15237#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15238//GDS_PS0_CTXSW_CNT0
15239#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
15240#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
15241#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15242#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15243//GDS_PS0_CTXSW_CNT1
15244#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
15245#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
15246#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15247#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15248//GDS_PS0_CTXSW_CNT2
15249#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
15250#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
15251#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15252#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15253//GDS_PS0_CTXSW_CNT3
15254#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
15255#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
15256#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15257#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15258//GDS_PS1_CTXSW_CNT0
15259#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
15260#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
15261#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15262#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15263//GDS_PS1_CTXSW_CNT1
15264#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
15265#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
15266#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15267#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15268//GDS_PS1_CTXSW_CNT2
15269#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
15270#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
15271#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15272#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15273//GDS_PS1_CTXSW_CNT3
15274#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
15275#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
15276#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15277#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15278//GDS_PS2_CTXSW_CNT0
15279#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
15280#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
15281#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15282#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15283//GDS_PS2_CTXSW_CNT1
15284#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
15285#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
15286#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15287#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15288//GDS_PS2_CTXSW_CNT2
15289#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
15290#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
15291#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15292#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15293//GDS_PS2_CTXSW_CNT3
15294#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
15295#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
15296#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15297#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15298//GDS_PS3_CTXSW_CNT0
15299#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
15300#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
15301#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15302#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15303//GDS_PS3_CTXSW_CNT1
15304#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
15305#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
15306#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15307#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15308//GDS_PS3_CTXSW_CNT2
15309#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
15310#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
15311#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15312#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15313//GDS_PS3_CTXSW_CNT3
15314#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
15315#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
15316#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15317#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15318//GDS_PS4_CTXSW_CNT0
15319#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
15320#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
15321#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15322#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15323//GDS_PS4_CTXSW_CNT1
15324#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
15325#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
15326#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15327#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15328//GDS_PS4_CTXSW_CNT2
15329#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
15330#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
15331#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15332#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15333//GDS_PS4_CTXSW_CNT3
15334#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
15335#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
15336#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15337#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15338//GDS_PS5_CTXSW_CNT0
15339#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
15340#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
15341#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15342#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15343//GDS_PS5_CTXSW_CNT1
15344#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
15345#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
15346#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15347#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15348//GDS_PS5_CTXSW_CNT2
15349#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
15350#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
15351#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15352#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15353//GDS_PS5_CTXSW_CNT3
15354#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
15355#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
15356#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15357#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15358//GDS_PS6_CTXSW_CNT0
15359#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
15360#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
15361#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15362#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15363//GDS_PS6_CTXSW_CNT1
15364#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
15365#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
15366#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15367#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15368//GDS_PS6_CTXSW_CNT2
15369#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
15370#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
15371#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15372#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15373//GDS_PS6_CTXSW_CNT3
15374#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
15375#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
15376#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15377#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15378//GDS_PS7_CTXSW_CNT0
15379#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
15380#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
15381#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15382#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15383//GDS_PS7_CTXSW_CNT1
15384#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
15385#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
15386#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15387#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15388//GDS_PS7_CTXSW_CNT2
15389#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
15390#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
15391#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15392#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15393//GDS_PS7_CTXSW_CNT3
15394#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
15395#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
15396#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15397#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15398//GDS_GS_CTXSW_CNT0
15399#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0
15400#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10
15401#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL
15402#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L
15403//GDS_GS_CTXSW_CNT1
15404#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0
15405#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10
15406#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL
15407#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L
15408//GDS_GS_CTXSW_CNT2
15409#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0
15410#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10
15411#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL
15412#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L
15413//GDS_GS_CTXSW_CNT3
15414#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0
15415#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10
15416#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL
15417#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L
15418
15419
15420// addressBlock: gc_rasdec
15421//RAS_SIGNATURE_CONTROL
15422#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
15423#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L
15424//RAS_SIGNATURE_MASK
15425#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
15426#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL
15427//RAS_SX_SIGNATURE0
15428#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
15429#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15430//RAS_SX_SIGNATURE1
15431#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
15432#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15433//RAS_SX_SIGNATURE2
15434#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
15435#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
15436//RAS_SX_SIGNATURE3
15437#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
15438#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
15439//RAS_DB_SIGNATURE0
15440#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
15441#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15442//RAS_PA_SIGNATURE0
15443#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
15444#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15445//RAS_VGT_SIGNATURE0
15446#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
15447#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15448//RAS_SQ_SIGNATURE0
15449#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
15450#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15451//RAS_SC_SIGNATURE0
15452#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
15453#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15454//RAS_SC_SIGNATURE1
15455#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
15456#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15457//RAS_SC_SIGNATURE2
15458#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
15459#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL
15460//RAS_SC_SIGNATURE3
15461#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
15462#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL
15463//RAS_SC_SIGNATURE4
15464#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
15465#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL
15466//RAS_SC_SIGNATURE5
15467#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
15468#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL
15469//RAS_SC_SIGNATURE6
15470#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
15471#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL
15472//RAS_SC_SIGNATURE7
15473#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
15474#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL
15475//RAS_IA_SIGNATURE0
15476#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
15477#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15478//RAS_IA_SIGNATURE1
15479#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
15480#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15481//RAS_SPI_SIGNATURE0
15482#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
15483#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15484//RAS_SPI_SIGNATURE1
15485#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
15486#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15487//RAS_TA_SIGNATURE0
15488#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
15489#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15490//RAS_TD_SIGNATURE0
15491#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
15492#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15493//RAS_CB_SIGNATURE0
15494#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
15495#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15496//RAS_BCI_SIGNATURE0
15497#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
15498#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL
15499//RAS_BCI_SIGNATURE1
15500#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
15501#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15502//RAS_TA_SIGNATURE1
15503#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
15504#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL
15505
15506
15507// addressBlock: gc_gfxdec0
15508//DB_RENDER_CONTROL
15509#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
15510#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
15511#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
15512#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
15513#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
15514#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
15515#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
15516#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
15517#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
15518#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
15519#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
15520#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
15521#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
15522#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
15523#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
15524#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
15525#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
15526#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
15527#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L
15528#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L
15529//DB_COUNT_CONTROL
15530#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
15531#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
15532#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
15533#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
15534#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
15535#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
15536#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
15537#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
15538#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
15539#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
15540#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
15541#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
15542#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L
15543#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L
15544#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L
15545#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L
15546#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L
15547#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L
15548//DB_DEPTH_VIEW
15549#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
15550#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
15551#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
15552#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
15553#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a
15554#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL
15555#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L
15556#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
15557#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
15558#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L
15559//DB_RENDER_OVERRIDE
15560#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
15561#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
15562#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
15563#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
15564#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
15565#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
15566#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
15567#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
15568#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
15569#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
15570#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
15571#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
15572#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
15573#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
15574#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
15575#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
15576#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
15577#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
15578#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
15579#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
15580#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
15581#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
15582#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
15583#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
15584#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL
15585#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
15586#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
15587#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
15588#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
15589#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
15590#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
15591#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
15592#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
15593#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
15594#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
15595#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
15596#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
15597#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
15598#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
15599#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L
15600#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
15601#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
15602#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
15603#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
15604#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
15605#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
15606//DB_RENDER_OVERRIDE2
15607#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
15608#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
15609#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
15610#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
15611#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
15612#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
15613#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
15614#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
15615#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
15616#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
15617#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
15618#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
15619#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
15620#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
15621#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
15622#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19
15623#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
15624#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL
15625#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
15626#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
15627#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
15628#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
15629#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
15630#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
15631#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
15632#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
15633#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
15634#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L
15635#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
15636#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
15637#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
15638#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L
15639//DB_HTILE_DATA_BASE
15640#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
15641#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL
15642//DB_HTILE_DATA_BASE_HI
15643#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0
15644#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL
15645//DB_DEPTH_SIZE
15646#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0
15647#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10
15648#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL
15649#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L
15650//DB_DEPTH_BOUNDS_MIN
15651#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
15652#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL
15653//DB_DEPTH_BOUNDS_MAX
15654#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
15655#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL
15656//DB_STENCIL_CLEAR
15657#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
15658#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL
15659//DB_DEPTH_CLEAR
15660#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
15661#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL
15662//PA_SC_SCREEN_SCISSOR_TL
15663#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
15664#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
15665#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL
15666#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L
15667//PA_SC_SCREEN_SCISSOR_BR
15668#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
15669#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
15670#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL
15671#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L
15672//DB_Z_INFO
15673#define DB_Z_INFO__FORMAT__SHIFT 0x0
15674#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
15675#define DB_Z_INFO__SW_MODE__SHIFT 0x4
15676#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
15677#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd
15678#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf
15679#define DB_Z_INFO__MAXMIP__SHIFT 0x10
15680#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
15681#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
15682#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
15683#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
15684#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
15685#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
15686#define DB_Z_INFO__FORMAT_MASK 0x00000003L
15687#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL
15688#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L
15689#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
15690#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
15691#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L
15692#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L
15693#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L
15694#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
15695#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
15696#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
15697#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
15698#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
15699//DB_STENCIL_INFO
15700#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
15701#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4
15702#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc
15703#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd
15704#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf
15705#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
15706#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
15707#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
15708#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
15709#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L
15710#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L
15711#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L
15712#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L
15713#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
15714#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
15715#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L
15716//DB_Z_READ_BASE
15717#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
15718#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
15719//DB_Z_READ_BASE_HI
15720#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0
15721#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
15722//DB_STENCIL_READ_BASE
15723#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
15724#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL
15725//DB_STENCIL_READ_BASE_HI
15726#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0
15727#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL
15728//DB_Z_WRITE_BASE
15729#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
15730#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
15731//DB_Z_WRITE_BASE_HI
15732#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
15733#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
15734//DB_STENCIL_WRITE_BASE
15735#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
15736#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL
15737//DB_STENCIL_WRITE_BASE_HI
15738#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0
15739#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL
15740//DB_DFSM_CONTROL
15741#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0
15742#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2
15743#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3
15744#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
15745#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
15746#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
15747//DB_Z_INFO2
15748#define DB_Z_INFO2__EPITCH__SHIFT 0x0
15749#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
15750//DB_STENCIL_INFO2
15751#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0
15752#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL
15753//TA_BC_BASE_ADDR
15754#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
15755#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
15756//TA_BC_BASE_ADDR_HI
15757#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
15758#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
15759//COHER_DEST_BASE_HI_0
15760#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
15761#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL
15762//COHER_DEST_BASE_HI_1
15763#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
15764#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL
15765//COHER_DEST_BASE_HI_2
15766#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
15767#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL
15768//COHER_DEST_BASE_HI_3
15769#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
15770#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL
15771//COHER_DEST_BASE_2
15772#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
15773#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL
15774//COHER_DEST_BASE_3
15775#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
15776#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL
15777//PA_SC_WINDOW_OFFSET
15778#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
15779#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
15780#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL
15781#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L
15782//PA_SC_WINDOW_SCISSOR_TL
15783#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
15784#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
15785#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15786#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL
15787#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
15788#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15789//PA_SC_WINDOW_SCISSOR_BR
15790#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
15791#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
15792#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL
15793#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
15794//PA_SC_CLIPRECT_RULE
15795#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
15796#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL
15797//PA_SC_CLIPRECT_0_TL
15798#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
15799#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
15800#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL
15801#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L
15802//PA_SC_CLIPRECT_0_BR
15803#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
15804#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
15805#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL
15806#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L
15807//PA_SC_CLIPRECT_1_TL
15808#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
15809#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
15810#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL
15811#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L
15812//PA_SC_CLIPRECT_1_BR
15813#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
15814#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
15815#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL
15816#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L
15817//PA_SC_CLIPRECT_2_TL
15818#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
15819#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
15820#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL
15821#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L
15822//PA_SC_CLIPRECT_2_BR
15823#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
15824#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
15825#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL
15826#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L
15827//PA_SC_CLIPRECT_3_TL
15828#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
15829#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
15830#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL
15831#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L
15832//PA_SC_CLIPRECT_3_BR
15833#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
15834#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
15835#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL
15836#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L
15837//PA_SC_EDGERULE
15838#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
15839#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
15840#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
15841#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
15842#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
15843#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
15844#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
15845#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL
15846#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L
15847#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L
15848#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L
15849#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L
15850#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L
15851#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L
15852//PA_SU_HARDWARE_SCREEN_OFFSET
15853#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
15854#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
15855#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL
15856#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L
15857//CB_TARGET_MASK
15858#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
15859#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
15860#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
15861#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
15862#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
15863#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
15864#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
15865#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
15866#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL
15867#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L
15868#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L
15869#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L
15870#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L
15871#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L
15872#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L
15873#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L
15874//CB_SHADER_MASK
15875#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
15876#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
15877#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
15878#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
15879#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
15880#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
15881#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
15882#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
15883#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL
15884#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L
15885#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L
15886#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L
15887#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L
15888#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L
15889#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L
15890#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L
15891//PA_SC_GENERIC_SCISSOR_TL
15892#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
15893#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
15894#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15895#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL
15896#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L
15897#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15898//PA_SC_GENERIC_SCISSOR_BR
15899#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
15900#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
15901#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL
15902#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L
15903//COHER_DEST_BASE_0
15904#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
15905#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL
15906//COHER_DEST_BASE_1
15907#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
15908#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL
15909//PA_SC_VPORT_SCISSOR_0_TL
15910#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
15911#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
15912#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15913#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL
15914#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L
15915#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15916//PA_SC_VPORT_SCISSOR_0_BR
15917#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
15918#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
15919#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL
15920#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L
15921//PA_SC_VPORT_SCISSOR_1_TL
15922#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
15923#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
15924#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15925#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL
15926#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L
15927#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15928//PA_SC_VPORT_SCISSOR_1_BR
15929#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
15930#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
15931#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL
15932#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L
15933//PA_SC_VPORT_SCISSOR_2_TL
15934#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
15935#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
15936#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15937#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL
15938#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L
15939#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15940//PA_SC_VPORT_SCISSOR_2_BR
15941#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
15942#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
15943#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL
15944#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L
15945//PA_SC_VPORT_SCISSOR_3_TL
15946#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
15947#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
15948#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15949#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL
15950#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L
15951#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15952//PA_SC_VPORT_SCISSOR_3_BR
15953#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
15954#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
15955#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL
15956#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L
15957//PA_SC_VPORT_SCISSOR_4_TL
15958#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
15959#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
15960#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15961#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL
15962#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L
15963#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15964//PA_SC_VPORT_SCISSOR_4_BR
15965#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
15966#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
15967#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL
15968#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L
15969//PA_SC_VPORT_SCISSOR_5_TL
15970#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
15971#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
15972#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15973#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL
15974#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L
15975#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15976//PA_SC_VPORT_SCISSOR_5_BR
15977#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
15978#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
15979#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL
15980#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L
15981//PA_SC_VPORT_SCISSOR_6_TL
15982#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
15983#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
15984#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15985#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL
15986#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L
15987#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
15988//PA_SC_VPORT_SCISSOR_6_BR
15989#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
15990#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
15991#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL
15992#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L
15993//PA_SC_VPORT_SCISSOR_7_TL
15994#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
15995#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
15996#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
15997#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL
15998#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L
15999#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16000//PA_SC_VPORT_SCISSOR_7_BR
16001#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
16002#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
16003#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL
16004#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L
16005//PA_SC_VPORT_SCISSOR_8_TL
16006#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
16007#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
16008#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16009#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL
16010#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L
16011#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16012//PA_SC_VPORT_SCISSOR_8_BR
16013#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
16014#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
16015#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL
16016#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L
16017//PA_SC_VPORT_SCISSOR_9_TL
16018#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
16019#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
16020#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16021#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL
16022#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L
16023#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16024//PA_SC_VPORT_SCISSOR_9_BR
16025#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
16026#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
16027#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL
16028#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L
16029//PA_SC_VPORT_SCISSOR_10_TL
16030#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
16031#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
16032#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16033#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL
16034#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L
16035#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16036//PA_SC_VPORT_SCISSOR_10_BR
16037#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
16038#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
16039#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL
16040#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L
16041//PA_SC_VPORT_SCISSOR_11_TL
16042#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
16043#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
16044#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16045#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL
16046#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L
16047#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16048//PA_SC_VPORT_SCISSOR_11_BR
16049#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
16050#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
16051#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL
16052#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L
16053//PA_SC_VPORT_SCISSOR_12_TL
16054#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
16055#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
16056#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16057#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL
16058#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L
16059#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16060//PA_SC_VPORT_SCISSOR_12_BR
16061#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
16062#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
16063#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL
16064#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L
16065//PA_SC_VPORT_SCISSOR_13_TL
16066#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
16067#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
16068#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16069#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL
16070#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L
16071#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16072//PA_SC_VPORT_SCISSOR_13_BR
16073#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
16074#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
16075#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL
16076#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L
16077//PA_SC_VPORT_SCISSOR_14_TL
16078#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
16079#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
16080#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16081#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL
16082#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L
16083#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16084//PA_SC_VPORT_SCISSOR_14_BR
16085#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
16086#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
16087#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL
16088#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L
16089//PA_SC_VPORT_SCISSOR_15_TL
16090#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
16091#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
16092#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
16093#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL
16094#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L
16095#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L
16096//PA_SC_VPORT_SCISSOR_15_BR
16097#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
16098#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
16099#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL
16100#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L
16101//PA_SC_VPORT_ZMIN_0
16102#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
16103#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL
16104//PA_SC_VPORT_ZMAX_0
16105#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
16106#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL
16107//PA_SC_VPORT_ZMIN_1
16108#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
16109#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL
16110//PA_SC_VPORT_ZMAX_1
16111#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
16112#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL
16113//PA_SC_VPORT_ZMIN_2
16114#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
16115#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL
16116//PA_SC_VPORT_ZMAX_2
16117#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
16118#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL
16119//PA_SC_VPORT_ZMIN_3
16120#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
16121#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL
16122//PA_SC_VPORT_ZMAX_3
16123#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
16124#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL
16125//PA_SC_VPORT_ZMIN_4
16126#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
16127#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL
16128//PA_SC_VPORT_ZMAX_4
16129#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
16130#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL
16131//PA_SC_VPORT_ZMIN_5
16132#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
16133#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL
16134//PA_SC_VPORT_ZMAX_5
16135#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
16136#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL
16137//PA_SC_VPORT_ZMIN_6
16138#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
16139#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL
16140//PA_SC_VPORT_ZMAX_6
16141#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
16142#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL
16143//PA_SC_VPORT_ZMIN_7
16144#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
16145#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL
16146//PA_SC_VPORT_ZMAX_7
16147#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
16148#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL
16149//PA_SC_VPORT_ZMIN_8
16150#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
16151#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL
16152//PA_SC_VPORT_ZMAX_8
16153#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
16154#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL
16155//PA_SC_VPORT_ZMIN_9
16156#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
16157#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL
16158//PA_SC_VPORT_ZMAX_9
16159#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
16160#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL
16161//PA_SC_VPORT_ZMIN_10
16162#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
16163#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL
16164//PA_SC_VPORT_ZMAX_10
16165#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
16166#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL
16167//PA_SC_VPORT_ZMIN_11
16168#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
16169#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL
16170//PA_SC_VPORT_ZMAX_11
16171#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
16172#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL
16173//PA_SC_VPORT_ZMIN_12
16174#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
16175#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL
16176//PA_SC_VPORT_ZMAX_12
16177#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
16178#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL
16179//PA_SC_VPORT_ZMIN_13
16180#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
16181#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL
16182//PA_SC_VPORT_ZMAX_13
16183#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
16184#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL
16185//PA_SC_VPORT_ZMIN_14
16186#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
16187#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL
16188//PA_SC_VPORT_ZMAX_14
16189#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
16190#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL
16191//PA_SC_VPORT_ZMIN_15
16192#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
16193#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL
16194//PA_SC_VPORT_ZMAX_15
16195#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
16196#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL
16197//PA_SC_RASTER_CONFIG
16198#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
16199#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
16200#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
16201#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
16202#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
16203#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
16204#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
16205#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
16206#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
16207#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
16208#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
16209#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
16210#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
16211#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
16212#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d
16213#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L
16214#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL
16215#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L
16216#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L
16217#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L
16218#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L
16219#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L
16220#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L
16221#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L
16222#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L
16223#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L
16224#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L
16225#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L
16226#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L
16227#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L
16228//PA_SC_RASTER_CONFIG_1
16229#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
16230#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
16231#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5
16232#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L
16233#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL
16234#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L
16235//PA_SC_SCREEN_EXTENT_CONTROL
16236#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
16237#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
16238#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L
16239#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL
16240//PA_SC_TILE_STEERING_OVERRIDE
16241#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
16242#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
16243#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
16244#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
16245#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
16246#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
16247//CP_PERFMON_CNTX_CNTL
16248#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
16249#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
16250//CP_PIPEID
16251#define CP_PIPEID__PIPE_ID__SHIFT 0x0
16252#define CP_PIPEID__PIPE_ID_MASK 0x00000003L
16253//CP_RINGID
16254#define CP_RINGID__RINGID__SHIFT 0x0
16255#define CP_RINGID__RINGID_MASK 0x00000003L
16256//CP_VMID
16257#define CP_VMID__VMID__SHIFT 0x0
16258#define CP_VMID__VMID_MASK 0x0000000FL
16259//PA_SC_RIGHT_VERT_GRID
16260#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0
16261#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8
16262#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
16263#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
16264#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
16265#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
16266#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
16267#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
16268//PA_SC_LEFT_VERT_GRID
16269#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0
16270#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8
16271#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10
16272#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18
16273#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL
16274#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L
16275#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L
16276#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L
16277//PA_SC_HORIZ_GRID
16278#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0
16279#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8
16280#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10
16281#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18
16282#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL
16283#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
16284#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
16285#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
16286//VGT_MULTI_PRIM_IB_RESET_INDX
16287#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
16288#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
16289//CB_BLEND_RED
16290#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
16291#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL
16292//CB_BLEND_GREEN
16293#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
16294#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL
16295//CB_BLEND_BLUE
16296#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
16297#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL
16298//CB_BLEND_ALPHA
16299#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
16300#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL
16301//CB_DCC_CONTROL
16302#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
16303#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
16304#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
16305#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8
16306#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9
16307#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa
16308#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc
16309#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd
16310#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe
16311#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
16312#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L
16313#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL
16314#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L
16315#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L
16316#define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L
16317#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L
16318#define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L
16319#define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L
16320//DB_STENCIL_CONTROL
16321#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
16322#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
16323#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
16324#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
16325#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
16326#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
16327#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL
16328#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L
16329#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L
16330#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L
16331#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L
16332#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L
16333//DB_STENCILREFMASK
16334#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
16335#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
16336#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
16337#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
16338#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL
16339#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L
16340#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L
16341#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L
16342//DB_STENCILREFMASK_BF
16343#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
16344#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
16345#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
16346#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
16347#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL
16348#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L
16349#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L
16350#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L
16351//PA_CL_VPORT_XSCALE
16352#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
16353#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL
16354//PA_CL_VPORT_XOFFSET
16355#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
16356#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16357//PA_CL_VPORT_YSCALE
16358#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
16359#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL
16360//PA_CL_VPORT_YOFFSET
16361#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
16362#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16363//PA_CL_VPORT_ZSCALE
16364#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
16365#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16366//PA_CL_VPORT_ZOFFSET
16367#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
16368#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16369//PA_CL_VPORT_XSCALE_1
16370#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
16371#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL
16372//PA_CL_VPORT_XOFFSET_1
16373#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
16374#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16375//PA_CL_VPORT_YSCALE_1
16376#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
16377#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL
16378//PA_CL_VPORT_YOFFSET_1
16379#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
16380#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16381//PA_CL_VPORT_ZSCALE_1
16382#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
16383#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16384//PA_CL_VPORT_ZOFFSET_1
16385#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
16386#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16387//PA_CL_VPORT_XSCALE_2
16388#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
16389#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL
16390//PA_CL_VPORT_XOFFSET_2
16391#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
16392#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16393//PA_CL_VPORT_YSCALE_2
16394#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
16395#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL
16396//PA_CL_VPORT_YOFFSET_2
16397#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
16398#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16399//PA_CL_VPORT_ZSCALE_2
16400#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
16401#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16402//PA_CL_VPORT_ZOFFSET_2
16403#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
16404#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16405//PA_CL_VPORT_XSCALE_3
16406#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
16407#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL
16408//PA_CL_VPORT_XOFFSET_3
16409#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
16410#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16411//PA_CL_VPORT_YSCALE_3
16412#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
16413#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL
16414//PA_CL_VPORT_YOFFSET_3
16415#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
16416#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16417//PA_CL_VPORT_ZSCALE_3
16418#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
16419#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16420//PA_CL_VPORT_ZOFFSET_3
16421#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
16422#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16423//PA_CL_VPORT_XSCALE_4
16424#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
16425#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL
16426//PA_CL_VPORT_XOFFSET_4
16427#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
16428#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16429//PA_CL_VPORT_YSCALE_4
16430#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
16431#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL
16432//PA_CL_VPORT_YOFFSET_4
16433#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
16434#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16435//PA_CL_VPORT_ZSCALE_4
16436#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
16437#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16438//PA_CL_VPORT_ZOFFSET_4
16439#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
16440#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16441//PA_CL_VPORT_XSCALE_5
16442#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
16443#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL
16444//PA_CL_VPORT_XOFFSET_5
16445#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
16446#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16447//PA_CL_VPORT_YSCALE_5
16448#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
16449#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL
16450//PA_CL_VPORT_YOFFSET_5
16451#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
16452#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16453//PA_CL_VPORT_ZSCALE_5
16454#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
16455#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16456//PA_CL_VPORT_ZOFFSET_5
16457#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
16458#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16459//PA_CL_VPORT_XSCALE_6
16460#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
16461#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL
16462//PA_CL_VPORT_XOFFSET_6
16463#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
16464#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16465//PA_CL_VPORT_YSCALE_6
16466#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
16467#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL
16468//PA_CL_VPORT_YOFFSET_6
16469#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
16470#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16471//PA_CL_VPORT_ZSCALE_6
16472#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
16473#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16474//PA_CL_VPORT_ZOFFSET_6
16475#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
16476#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16477//PA_CL_VPORT_XSCALE_7
16478#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
16479#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL
16480//PA_CL_VPORT_XOFFSET_7
16481#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
16482#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16483//PA_CL_VPORT_YSCALE_7
16484#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
16485#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL
16486//PA_CL_VPORT_YOFFSET_7
16487#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
16488#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16489//PA_CL_VPORT_ZSCALE_7
16490#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
16491#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16492//PA_CL_VPORT_ZOFFSET_7
16493#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
16494#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16495//PA_CL_VPORT_XSCALE_8
16496#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
16497#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL
16498//PA_CL_VPORT_XOFFSET_8
16499#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
16500#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16501//PA_CL_VPORT_YSCALE_8
16502#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
16503#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL
16504//PA_CL_VPORT_YOFFSET_8
16505#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
16506#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16507//PA_CL_VPORT_ZSCALE_8
16508#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
16509#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16510//PA_CL_VPORT_ZOFFSET_8
16511#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
16512#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16513//PA_CL_VPORT_XSCALE_9
16514#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
16515#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL
16516//PA_CL_VPORT_XOFFSET_9
16517#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
16518#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16519//PA_CL_VPORT_YSCALE_9
16520#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
16521#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL
16522//PA_CL_VPORT_YOFFSET_9
16523#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
16524#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16525//PA_CL_VPORT_ZSCALE_9
16526#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
16527#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16528//PA_CL_VPORT_ZOFFSET_9
16529#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
16530#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16531//PA_CL_VPORT_XSCALE_10
16532#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
16533#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL
16534//PA_CL_VPORT_XOFFSET_10
16535#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
16536#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16537//PA_CL_VPORT_YSCALE_10
16538#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
16539#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL
16540//PA_CL_VPORT_YOFFSET_10
16541#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
16542#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16543//PA_CL_VPORT_ZSCALE_10
16544#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
16545#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16546//PA_CL_VPORT_ZOFFSET_10
16547#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
16548#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16549//PA_CL_VPORT_XSCALE_11
16550#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
16551#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL
16552//PA_CL_VPORT_XOFFSET_11
16553#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
16554#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16555//PA_CL_VPORT_YSCALE_11
16556#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
16557#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL
16558//PA_CL_VPORT_YOFFSET_11
16559#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
16560#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16561//PA_CL_VPORT_ZSCALE_11
16562#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
16563#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16564//PA_CL_VPORT_ZOFFSET_11
16565#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
16566#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16567//PA_CL_VPORT_XSCALE_12
16568#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
16569#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL
16570//PA_CL_VPORT_XOFFSET_12
16571#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
16572#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16573//PA_CL_VPORT_YSCALE_12
16574#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
16575#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL
16576//PA_CL_VPORT_YOFFSET_12
16577#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
16578#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16579//PA_CL_VPORT_ZSCALE_12
16580#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
16581#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16582//PA_CL_VPORT_ZOFFSET_12
16583#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
16584#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16585//PA_CL_VPORT_XSCALE_13
16586#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
16587#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL
16588//PA_CL_VPORT_XOFFSET_13
16589#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
16590#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16591//PA_CL_VPORT_YSCALE_13
16592#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
16593#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL
16594//PA_CL_VPORT_YOFFSET_13
16595#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
16596#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16597//PA_CL_VPORT_ZSCALE_13
16598#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
16599#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16600//PA_CL_VPORT_ZOFFSET_13
16601#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
16602#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16603//PA_CL_VPORT_XSCALE_14
16604#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
16605#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL
16606//PA_CL_VPORT_XOFFSET_14
16607#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
16608#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16609//PA_CL_VPORT_YSCALE_14
16610#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
16611#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL
16612//PA_CL_VPORT_YOFFSET_14
16613#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
16614#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16615//PA_CL_VPORT_ZSCALE_14
16616#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
16617#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16618//PA_CL_VPORT_ZOFFSET_14
16619#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
16620#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16621//PA_CL_VPORT_XSCALE_15
16622#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
16623#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL
16624//PA_CL_VPORT_XOFFSET_15
16625#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
16626#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL
16627//PA_CL_VPORT_YSCALE_15
16628#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
16629#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL
16630//PA_CL_VPORT_YOFFSET_15
16631#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
16632#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL
16633//PA_CL_VPORT_ZSCALE_15
16634#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
16635#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL
16636//PA_CL_VPORT_ZOFFSET_15
16637#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
16638#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL
16639//PA_CL_UCP_0_X
16640#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
16641#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16642//PA_CL_UCP_0_Y
16643#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
16644#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16645//PA_CL_UCP_0_Z
16646#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
16647#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16648//PA_CL_UCP_0_W
16649#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
16650#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16651//PA_CL_UCP_1_X
16652#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
16653#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16654//PA_CL_UCP_1_Y
16655#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
16656#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16657//PA_CL_UCP_1_Z
16658#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
16659#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16660//PA_CL_UCP_1_W
16661#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
16662#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16663//PA_CL_UCP_2_X
16664#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
16665#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16666//PA_CL_UCP_2_Y
16667#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
16668#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16669//PA_CL_UCP_2_Z
16670#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
16671#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16672//PA_CL_UCP_2_W
16673#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
16674#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16675//PA_CL_UCP_3_X
16676#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
16677#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16678//PA_CL_UCP_3_Y
16679#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
16680#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16681//PA_CL_UCP_3_Z
16682#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
16683#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16684//PA_CL_UCP_3_W
16685#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
16686#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16687//PA_CL_UCP_4_X
16688#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
16689#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16690//PA_CL_UCP_4_Y
16691#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
16692#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16693//PA_CL_UCP_4_Z
16694#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
16695#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16696//PA_CL_UCP_4_W
16697#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
16698#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16699//PA_CL_UCP_5_X
16700#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
16701#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL
16702//PA_CL_UCP_5_Y
16703#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
16704#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL
16705//PA_CL_UCP_5_Z
16706#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
16707#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16708//PA_CL_UCP_5_W
16709#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
16710#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL
16711//PA_CL_PROG_NEAR_CLIP_Z
16712#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0
16713#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL
16714//SPI_PS_INPUT_CNTL_0
16715#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
16716#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
16717#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
16718#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
16719#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
16720#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
16721#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
16722#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
16723#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
16724#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16725#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
16726#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
16727#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL
16728#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L
16729#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L
16730#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L
16731#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L
16732#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L
16733#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L
16734#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L
16735#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16736#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16737#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L
16738#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L
16739//SPI_PS_INPUT_CNTL_1
16740#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
16741#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
16742#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
16743#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
16744#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
16745#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
16746#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
16747#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
16748#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
16749#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16750#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
16751#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
16752#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL
16753#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L
16754#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L
16755#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L
16756#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L
16757#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L
16758#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L
16759#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L
16760#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16761#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16762#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L
16763#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L
16764//SPI_PS_INPUT_CNTL_2
16765#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
16766#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
16767#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
16768#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
16769#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
16770#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
16771#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
16772#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
16773#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
16774#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16775#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
16776#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
16777#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL
16778#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L
16779#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L
16780#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L
16781#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L
16782#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L
16783#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L
16784#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L
16785#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16786#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16787#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L
16788#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L
16789//SPI_PS_INPUT_CNTL_3
16790#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
16791#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
16792#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
16793#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
16794#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
16795#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
16796#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
16797#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
16798#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
16799#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16800#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
16801#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
16802#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL
16803#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L
16804#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L
16805#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L
16806#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L
16807#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L
16808#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L
16809#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L
16810#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16811#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16812#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L
16813#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L
16814//SPI_PS_INPUT_CNTL_4
16815#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
16816#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
16817#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
16818#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
16819#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
16820#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
16821#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
16822#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
16823#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
16824#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16825#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
16826#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
16827#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL
16828#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L
16829#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L
16830#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L
16831#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L
16832#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L
16833#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L
16834#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L
16835#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16836#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16837#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L
16838#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L
16839//SPI_PS_INPUT_CNTL_5
16840#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
16841#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
16842#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
16843#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
16844#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
16845#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
16846#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
16847#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
16848#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
16849#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16850#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
16851#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
16852#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL
16853#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L
16854#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L
16855#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L
16856#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L
16857#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L
16858#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L
16859#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L
16860#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16861#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16862#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L
16863#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L
16864//SPI_PS_INPUT_CNTL_6
16865#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
16866#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
16867#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
16868#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
16869#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
16870#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
16871#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
16872#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
16873#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
16874#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16875#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
16876#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
16877#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL
16878#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L
16879#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L
16880#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L
16881#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L
16882#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L
16883#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L
16884#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L
16885#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16886#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16887#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L
16888#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L
16889//SPI_PS_INPUT_CNTL_7
16890#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
16891#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
16892#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
16893#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
16894#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
16895#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
16896#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
16897#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
16898#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
16899#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16900#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
16901#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
16902#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL
16903#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L
16904#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L
16905#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L
16906#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L
16907#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L
16908#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L
16909#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L
16910#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16911#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16912#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L
16913#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L
16914//SPI_PS_INPUT_CNTL_8
16915#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
16916#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
16917#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
16918#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
16919#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
16920#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
16921#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
16922#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
16923#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
16924#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16925#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
16926#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
16927#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL
16928#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L
16929#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L
16930#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L
16931#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L
16932#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L
16933#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L
16934#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L
16935#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16936#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16937#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L
16938#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L
16939//SPI_PS_INPUT_CNTL_9
16940#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
16941#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
16942#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
16943#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
16944#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
16945#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
16946#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
16947#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
16948#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
16949#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16950#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
16951#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
16952#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL
16953#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L
16954#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L
16955#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L
16956#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L
16957#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L
16958#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L
16959#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L
16960#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16961#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16962#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L
16963#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L
16964//SPI_PS_INPUT_CNTL_10
16965#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
16966#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
16967#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
16968#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
16969#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
16970#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
16971#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
16972#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
16973#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
16974#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
16975#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
16976#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
16977#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL
16978#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L
16979#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L
16980#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L
16981#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L
16982#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L
16983#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L
16984#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L
16985#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L
16986#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
16987#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L
16988#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L
16989//SPI_PS_INPUT_CNTL_11
16990#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
16991#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
16992#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
16993#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
16994#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
16995#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
16996#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
16997#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
16998#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
16999#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17000#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
17001#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
17002#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL
17003#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L
17004#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L
17005#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L
17006#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L
17007#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L
17008#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L
17009#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L
17010#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17011#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17012#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L
17013#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L
17014//SPI_PS_INPUT_CNTL_12
17015#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
17016#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
17017#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
17018#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
17019#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
17020#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
17021#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
17022#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
17023#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
17024#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17025#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
17026#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
17027#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL
17028#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L
17029#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L
17030#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L
17031#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L
17032#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L
17033#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L
17034#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L
17035#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17036#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17037#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L
17038#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L
17039//SPI_PS_INPUT_CNTL_13
17040#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
17041#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
17042#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
17043#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
17044#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
17045#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
17046#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
17047#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
17048#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
17049#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17050#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
17051#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
17052#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL
17053#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L
17054#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L
17055#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L
17056#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L
17057#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L
17058#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L
17059#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L
17060#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17061#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17062#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L
17063#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L
17064//SPI_PS_INPUT_CNTL_14
17065#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
17066#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
17067#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
17068#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
17069#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
17070#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
17071#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
17072#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
17073#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
17074#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17075#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
17076#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
17077#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL
17078#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L
17079#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L
17080#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L
17081#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L
17082#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L
17083#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L
17084#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L
17085#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17086#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17087#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L
17088#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L
17089//SPI_PS_INPUT_CNTL_15
17090#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
17091#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
17092#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
17093#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
17094#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
17095#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
17096#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
17097#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
17098#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
17099#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17100#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
17101#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
17102#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL
17103#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L
17104#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L
17105#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L
17106#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L
17107#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L
17108#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L
17109#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L
17110#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17111#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17112#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L
17113#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L
17114//SPI_PS_INPUT_CNTL_16
17115#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
17116#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
17117#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
17118#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
17119#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
17120#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
17121#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
17122#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
17123#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
17124#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17125#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
17126#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
17127#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL
17128#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L
17129#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L
17130#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L
17131#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L
17132#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L
17133#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L
17134#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L
17135#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17136#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17137#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L
17138#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L
17139//SPI_PS_INPUT_CNTL_17
17140#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
17141#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
17142#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
17143#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
17144#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
17145#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
17146#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
17147#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
17148#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
17149#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17150#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
17151#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
17152#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL
17153#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L
17154#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L
17155#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L
17156#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L
17157#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L
17158#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L
17159#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L
17160#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17161#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17162#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L
17163#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L
17164//SPI_PS_INPUT_CNTL_18
17165#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
17166#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
17167#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
17168#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
17169#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
17170#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
17171#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
17172#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
17173#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
17174#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17175#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
17176#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
17177#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL
17178#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L
17179#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L
17180#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L
17181#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L
17182#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L
17183#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L
17184#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L
17185#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17186#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17187#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L
17188#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L
17189//SPI_PS_INPUT_CNTL_19
17190#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
17191#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
17192#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
17193#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
17194#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
17195#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
17196#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
17197#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
17198#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
17199#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
17200#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
17201#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
17202#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL
17203#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L
17204#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L
17205#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L
17206#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L
17207#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L
17208#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L
17209#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L
17210#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17211#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L
17212#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L
17213#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L
17214//SPI_PS_INPUT_CNTL_20
17215#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
17216#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
17217#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
17218#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
17219#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
17220#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
17221#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
17222#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
17223#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
17224#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL
17225#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L
17226#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L
17227#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L
17228#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L
17229#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L
17230#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17231#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L
17232#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L
17233//SPI_PS_INPUT_CNTL_21
17234#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
17235#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
17236#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
17237#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
17238#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
17239#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
17240#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
17241#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
17242#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
17243#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL
17244#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L
17245#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L
17246#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L
17247#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L
17248#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L
17249#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17250#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L
17251#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L
17252//SPI_PS_INPUT_CNTL_22
17253#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
17254#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
17255#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
17256#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
17257#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
17258#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
17259#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
17260#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
17261#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
17262#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL
17263#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L
17264#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L
17265#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L
17266#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L
17267#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L
17268#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17269#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L
17270#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L
17271//SPI_PS_INPUT_CNTL_23
17272#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
17273#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
17274#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
17275#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
17276#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
17277#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
17278#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
17279#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
17280#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
17281#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL
17282#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L
17283#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L
17284#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L
17285#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L
17286#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L
17287#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17288#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L
17289#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L
17290//SPI_PS_INPUT_CNTL_24
17291#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
17292#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
17293#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
17294#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
17295#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
17296#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
17297#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
17298#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
17299#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
17300#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL
17301#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L
17302#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L
17303#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L
17304#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L
17305#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L
17306#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17307#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L
17308#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L
17309//SPI_PS_INPUT_CNTL_25
17310#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
17311#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
17312#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
17313#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
17314#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
17315#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
17316#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
17317#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
17318#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
17319#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL
17320#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L
17321#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L
17322#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L
17323#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L
17324#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L
17325#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17326#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L
17327#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L
17328//SPI_PS_INPUT_CNTL_26
17329#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
17330#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
17331#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
17332#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
17333#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
17334#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
17335#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
17336#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
17337#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
17338#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL
17339#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L
17340#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L
17341#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L
17342#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L
17343#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L
17344#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17345#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L
17346#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L
17347//SPI_PS_INPUT_CNTL_27
17348#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
17349#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
17350#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
17351#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
17352#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
17353#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
17354#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
17355#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
17356#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
17357#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL
17358#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L
17359#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L
17360#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L
17361#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L
17362#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L
17363#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17364#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L
17365#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L
17366//SPI_PS_INPUT_CNTL_28
17367#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
17368#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
17369#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
17370#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
17371#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
17372#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
17373#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
17374#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
17375#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
17376#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL
17377#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L
17378#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L
17379#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L
17380#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L
17381#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L
17382#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17383#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L
17384#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L
17385//SPI_PS_INPUT_CNTL_29
17386#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
17387#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
17388#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
17389#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
17390#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
17391#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
17392#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
17393#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
17394#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
17395#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL
17396#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L
17397#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L
17398#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L
17399#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L
17400#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L
17401#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17402#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L
17403#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L
17404//SPI_PS_INPUT_CNTL_30
17405#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
17406#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
17407#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
17408#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
17409#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
17410#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
17411#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
17412#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
17413#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
17414#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL
17415#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L
17416#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L
17417#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L
17418#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L
17419#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L
17420#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17421#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L
17422#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L
17423//SPI_PS_INPUT_CNTL_31
17424#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
17425#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
17426#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
17427#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
17428#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
17429#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
17430#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
17431#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
17432#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
17433#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL
17434#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L
17435#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L
17436#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L
17437#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L
17438#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L
17439#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L
17440#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L
17441#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L
17442//SPI_VS_OUT_CONFIG
17443#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
17444#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
17445#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL
17446#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L
17447//SPI_PS_INPUT_ENA
17448#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
17449#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
17450#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
17451#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
17452#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
17453#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
17454#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
17455#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
17456#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
17457#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
17458#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
17459#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
17460#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
17461#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
17462#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
17463#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
17464#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L
17465#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L
17466#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L
17467#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
17468#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L
17469#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L
17470#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L
17471#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
17472#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L
17473#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L
17474#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L
17475#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L
17476#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L
17477#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L
17478#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
17479#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L
17480//SPI_PS_INPUT_ADDR
17481#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
17482#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
17483#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
17484#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
17485#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
17486#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
17487#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
17488#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
17489#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
17490#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
17491#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
17492#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
17493#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
17494#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
17495#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
17496#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
17497#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L
17498#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L
17499#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L
17500#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L
17501#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L
17502#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L
17503#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L
17504#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L
17505#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L
17506#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L
17507#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L
17508#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L
17509#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L
17510#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L
17511#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L
17512#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L
17513//SPI_INTERP_CONTROL_0
17514#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
17515#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
17516#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
17517#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
17518#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
17519#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
17520#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
17521#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L
17522#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L
17523#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL
17524#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L
17525#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L
17526#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L
17527#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L
17528//SPI_PS_IN_CONTROL
17529#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
17530#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
17531#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7
17532#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8
17533#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
17534#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL
17535#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L
17536#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L
17537#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L
17538#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L
17539//SPI_BARYC_CNTL
17540#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
17541#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
17542#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
17543#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
17544#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
17545#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
17546#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
17547#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L
17548#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L
17549#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L
17550#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L
17551#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L
17552#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L
17553#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L
17554//SPI_TMPRING_SIZE
17555#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
17556#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
17557#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL
17558#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L
17559//SPI_SHADER_POS_FORMAT
17560#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
17561#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
17562#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
17563#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
17564#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL
17565#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L
17566#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L
17567#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L
17568//SPI_SHADER_Z_FORMAT
17569#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
17570#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL
17571//SPI_SHADER_COL_FORMAT
17572#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
17573#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
17574#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
17575#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
17576#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
17577#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
17578#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
17579#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
17580#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL
17581#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L
17582#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L
17583#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L
17584#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L
17585#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L
17586#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L
17587#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L
17588//SX_PS_DOWNCONVERT
17589#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0
17590#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4
17591#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8
17592#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc
17593#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10
17594#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14
17595#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18
17596#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c
17597#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL
17598#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L
17599#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L
17600#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L
17601#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L
17602#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L
17603#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L
17604#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L
17605//SX_BLEND_OPT_EPSILON
17606#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0
17607#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4
17608#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8
17609#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc
17610#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10
17611#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14
17612#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18
17613#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c
17614#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL
17615#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L
17616#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L
17617#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L
17618#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L
17619#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L
17620#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L
17621#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L
17622//SX_BLEND_OPT_CONTROL
17623#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0
17624#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1
17625#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4
17626#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5
17627#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8
17628#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9
17629#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc
17630#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd
17631#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10
17632#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11
17633#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14
17634#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15
17635#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18
17636#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19
17637#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c
17638#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d
17639#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f
17640#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L
17641#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L
17642#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L
17643#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L
17644#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L
17645#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L
17646#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L
17647#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L
17648#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L
17649#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L
17650#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L
17651#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L
17652#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L
17653#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L
17654#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L
17655#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L
17656#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L
17657//SX_MRT0_BLEND_OPT
17658#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17659#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17660#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17661#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17662#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17663#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17664#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17665#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17666#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17667#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17668#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17669#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17670//SX_MRT1_BLEND_OPT
17671#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17672#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17673#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17674#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17675#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17676#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17677#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17678#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17679#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17680#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17681#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17682#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17683//SX_MRT2_BLEND_OPT
17684#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17685#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17686#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17687#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17688#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17689#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17690#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17691#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17692#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17693#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17694#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17695#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17696//SX_MRT3_BLEND_OPT
17697#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17698#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17699#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17700#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17701#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17702#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17703#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17704#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17705#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17706#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17707#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17708#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17709//SX_MRT4_BLEND_OPT
17710#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17711#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17712#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17713#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17714#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17715#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17716#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17717#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17718#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17719#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17720#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17721#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17722//SX_MRT5_BLEND_OPT
17723#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17724#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17725#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17726#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17727#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17728#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17729#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17730#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17731#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17732#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17733#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17734#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17735//SX_MRT6_BLEND_OPT
17736#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17737#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17738#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17739#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17740#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17741#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17742#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17743#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17744#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17745#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17746#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17747#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17748//SX_MRT7_BLEND_OPT
17749#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0
17750#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4
17751#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8
17752#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10
17753#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14
17754#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18
17755#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L
17756#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L
17757#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L
17758#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L
17759#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L
17760#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L
17761//CB_BLEND0_CONTROL
17762#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17763#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17764#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17765#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17766#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17767#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17768#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17769#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
17770#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17771#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17772#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17773#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17774#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17775#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17776#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17777#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17778#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
17779#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17780//CB_BLEND1_CONTROL
17781#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17782#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17783#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17784#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17785#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17786#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17787#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17788#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
17789#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17790#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17791#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17792#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17793#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17794#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17795#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17796#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17797#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
17798#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17799//CB_BLEND2_CONTROL
17800#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17801#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17802#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17803#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17804#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17805#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17806#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17807#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
17808#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17809#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17810#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17811#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17812#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17813#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17814#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17815#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17816#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
17817#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17818//CB_BLEND3_CONTROL
17819#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17820#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17821#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17822#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17823#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17824#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17825#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17826#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
17827#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17828#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17829#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17830#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17831#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17832#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17833#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17834#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17835#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
17836#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17837//CB_BLEND4_CONTROL
17838#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17839#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17840#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17841#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17842#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17843#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17844#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17845#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
17846#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17847#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17848#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17849#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17850#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17851#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17852#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17853#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17854#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
17855#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17856//CB_BLEND5_CONTROL
17857#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17858#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17859#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17860#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17861#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17862#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17863#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17864#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
17865#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17866#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17867#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17868#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17869#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17870#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17871#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17872#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17873#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
17874#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17875//CB_BLEND6_CONTROL
17876#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17877#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17878#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17879#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17880#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17881#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17882#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17883#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
17884#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17885#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17886#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17887#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17888#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17889#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17890#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17891#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17892#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
17893#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17894//CB_BLEND7_CONTROL
17895#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
17896#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
17897#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
17898#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
17899#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
17900#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
17901#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
17902#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
17903#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
17904#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL
17905#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L
17906#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L
17907#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L
17908#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L
17909#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L
17910#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
17911#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
17912#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
17913//CB_MRT0_EPITCH
17914#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0
17915#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL
17916//CB_MRT1_EPITCH
17917#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0
17918#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL
17919//CB_MRT2_EPITCH
17920#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0
17921#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL
17922//CB_MRT3_EPITCH
17923#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0
17924#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL
17925//CB_MRT4_EPITCH
17926#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0
17927#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL
17928//CB_MRT5_EPITCH
17929#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0
17930#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL
17931//CB_MRT6_EPITCH
17932#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0
17933#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL
17934//CB_MRT7_EPITCH
17935#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0
17936#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL
17937//CS_COPY_STATE
17938#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
17939#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
17940//GFX_COPY_STATE
17941#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
17942#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
17943//PA_CL_POINT_X_RAD
17944#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
17945#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
17946//PA_CL_POINT_Y_RAD
17947#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
17948#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
17949//PA_CL_POINT_SIZE
17950#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
17951#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL
17952//PA_CL_POINT_CULL_RAD
17953#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
17954#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL
17955//VGT_DMA_BASE_HI
17956#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
17957#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL
17958//VGT_DMA_BASE
17959#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
17960#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL
17961//VGT_DRAW_INITIATOR
17962#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
17963#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
17964#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
17965#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
17966#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
17967#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7
17968#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8
17969#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d
17970#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L
17971#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL
17972#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L
17973#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L
17974#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L
17975#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L
17976#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L
17977#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L
17978//VGT_IMMED_DATA
17979#define VGT_IMMED_DATA__DATA__SHIFT 0x0
17980#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL
17981//VGT_EVENT_ADDRESS_REG
17982#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
17983#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL
17984//DB_DEPTH_CONTROL
17985#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
17986#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
17987#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
17988#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
17989#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
17990#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
17991#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
17992#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
17993#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
17994#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
17995#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
17996#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
17997#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
17998#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
17999#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
18000#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
18001#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
18002#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
18003#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
18004#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
18005//DB_EQAA
18006#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
18007#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
18008#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
18009#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
18010#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
18011#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
18012#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
18013#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
18014#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
18015#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
18016#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
18017#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
18018#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
18019#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
18020#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
18021#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
18022#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
18023#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
18024#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
18025#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
18026#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
18027#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
18028#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
18029#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
18030//CB_COLOR_CONTROL
18031#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0
18032#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
18033#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
18034#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
18035#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L
18036#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
18037#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
18038#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L
18039//DB_SHADER_CONTROL
18040#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
18041#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
18042#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
18043#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
18044#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
18045#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
18046#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
18047#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
18048#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
18049#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
18050#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
18051#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
18052#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf
18053#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10
18054#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11
18055#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14
18056#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
18057#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
18058#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
18059#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
18060#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
18061#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
18062#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
18063#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
18064#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
18065#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
18066#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
18067#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
18068#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L
18069#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L
18070#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L
18071#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L
18072//PA_CL_CLIP_CNTL
18073#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
18074#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
18075#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
18076#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
18077#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
18078#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
18079#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
18080#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
18081#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
18082#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
18083#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
18084#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
18085#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
18086#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
18087#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
18088#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
18089#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
18090#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
18091#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
18092#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c
18093#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L
18094#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L
18095#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L
18096#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L
18097#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L
18098#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L
18099#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L
18100#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L
18101#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L
18102#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L
18103#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L
18104#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L
18105#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L
18106#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L
18107#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L
18108#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L
18109#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L
18110#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L
18111#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L
18112#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L
18113//PA_SU_SC_MODE_CNTL
18114#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
18115#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
18116#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
18117#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
18118#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
18119#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
18120#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
18121#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
18122#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
18123#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
18124#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
18125#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
18126#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
18127#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16
18128#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17
18129#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L
18130#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L
18131#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L
18132#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L
18133#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L
18134#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L
18135#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L
18136#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L
18137#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L
18138#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L
18139#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L
18140#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L
18141#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L
18142#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L
18143#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L
18144//PA_CL_VTE_CNTL
18145#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
18146#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
18147#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
18148#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
18149#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
18150#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
18151#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
18152#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
18153#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
18154#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
18155#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L
18156#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L
18157#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L
18158#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L
18159#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L
18160#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L
18161#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L
18162#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L
18163#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L
18164#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L
18165//PA_CL_VS_OUT_CNTL
18166#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
18167#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
18168#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
18169#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
18170#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
18171#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
18172#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
18173#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
18174#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
18175#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
18176#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
18177#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
18178#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
18179#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
18180#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
18181#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
18182#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
18183#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
18184#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
18185#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
18186#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
18187#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
18188#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
18189#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
18190#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
18191#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
18192#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
18193#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b
18194#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L
18195#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L
18196#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L
18197#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L
18198#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L
18199#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L
18200#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L
18201#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L
18202#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L
18203#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L
18204#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L
18205#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L
18206#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L
18207#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L
18208#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L
18209#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L
18210#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L
18211#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L
18212#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L
18213#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L
18214#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L
18215#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L
18216#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L
18217#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L
18218#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L
18219#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L
18220#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L
18221#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L
18222//PA_CL_NANINF_CNTL
18223#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
18224#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
18225#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
18226#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
18227#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
18228#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
18229#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
18230#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
18231#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
18232#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
18233#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
18234#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
18235#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
18236#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
18237#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
18238#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
18239#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L
18240#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L
18241#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L
18242#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L
18243#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L
18244#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L
18245#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L
18246#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L
18247#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L
18248#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L
18249#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L
18250#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L
18251#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L
18252#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L
18253#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L
18254#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L
18255//PA_SU_LINE_STIPPLE_CNTL
18256#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
18257#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
18258#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
18259#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
18260#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L
18261#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L
18262#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L
18263#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L
18264//PA_SU_LINE_STIPPLE_SCALE
18265#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
18266#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL
18267//PA_SU_PRIM_FILTER_CNTL
18268#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
18269#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
18270#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
18271#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
18272#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
18273#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
18274#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
18275#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
18276#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
18277#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
18278#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
18279#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L
18280#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L
18281#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L
18282#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L
18283#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L
18284#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L
18285#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L
18286#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L
18287#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L
18288#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L
18289#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L
18290//PA_SU_SMALL_PRIM_FILTER_CNTL
18291#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0
18292#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1
18293#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
18294#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
18295#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
18296#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6
18297#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
18298#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
18299#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
18300#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
18301#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
18302#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L
18303//PA_CL_OBJPRIM_ID_CNTL
18304#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
18305#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
18306#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2
18307#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L
18308#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L
18309#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L
18310//PA_CL_NGG_CNTL
18311#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0
18312#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1
18313#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L
18314#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L
18315//PA_SU_OVER_RASTERIZATION_CNTL
18316#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0
18317#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1
18318#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2
18319#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3
18320#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4
18321#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L
18322#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L
18323#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L
18324#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L
18325#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L
18326//PA_STEREO_CNTL
18327#define PA_STEREO_CNTL__EN_STEREO__SHIFT 0x0
18328#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1
18329#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5
18330#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8
18331#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0xa
18332#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0xd
18333#define PA_STEREO_CNTL__EN_STEREO_MASK 0x00000001L
18334#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL
18335#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L
18336#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000300L
18337#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00001C00L
18338#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x0001E000L
18339//PA_SU_POINT_SIZE
18340#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
18341#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
18342#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL
18343#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L
18344//PA_SU_POINT_MINMAX
18345#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
18346#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
18347#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL
18348#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L
18349//PA_SU_LINE_CNTL
18350#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
18351#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL
18352//PA_SC_LINE_STIPPLE
18353#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
18354#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
18355#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
18356#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
18357#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL
18358#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L
18359#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L
18360#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L
18361//VGT_OUTPUT_PATH_CNTL
18362#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
18363#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L
18364//VGT_HOS_CNTL
18365#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
18366#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L
18367//VGT_HOS_MAX_TESS_LEVEL
18368#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
18369#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL
18370//VGT_HOS_MIN_TESS_LEVEL
18371#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
18372#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL
18373//VGT_HOS_REUSE_DEPTH
18374#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
18375#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL
18376//VGT_GROUP_PRIM_TYPE
18377#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
18378#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
18379#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
18380#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
18381#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL
18382#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L
18383#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L
18384#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L
18385//VGT_GROUP_FIRST_DECR
18386#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
18387#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL
18388//VGT_GROUP_DECR
18389#define VGT_GROUP_DECR__DECR__SHIFT 0x0
18390#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL
18391//VGT_GROUP_VECT_0_CNTL
18392#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
18393#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
18394#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
18395#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
18396#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
18397#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
18398#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L
18399#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L
18400#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L
18401#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L
18402#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L
18403#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L
18404//VGT_GROUP_VECT_1_CNTL
18405#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
18406#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
18407#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
18408#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
18409#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
18410#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
18411#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L
18412#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L
18413#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L
18414#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L
18415#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L
18416#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L
18417//VGT_GROUP_VECT_0_FMT_CNTL
18418#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
18419#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
18420#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
18421#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
18422#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
18423#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
18424#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
18425#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
18426#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL
18427#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
18428#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L
18429#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
18430#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L
18431#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
18432#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L
18433#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
18434//VGT_GROUP_VECT_1_FMT_CNTL
18435#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
18436#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
18437#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
18438#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
18439#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
18440#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
18441#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
18442#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
18443#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL
18444#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L
18445#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L
18446#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L
18447#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L
18448#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L
18449#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L
18450#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L
18451//VGT_GS_MODE
18452#define VGT_GS_MODE__MODE__SHIFT 0x0
18453#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
18454#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
18455#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
18456#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
18457#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
18458#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
18459#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
18460#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
18461#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
18462#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
18463#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
18464#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
18465#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
18466#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
18467#define VGT_GS_MODE__MODE_MASK 0x00000007L
18468#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L
18469#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L
18470#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L
18471#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L
18472#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L
18473#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L
18474#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L
18475#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L
18476#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L
18477#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L
18478#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L
18479#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L
18480#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L
18481#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L
18482//VGT_GS_ONCHIP_CNTL
18483#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
18484#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
18485#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16
18486#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL
18487#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L
18488#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L
18489//PA_SC_MODE_CNTL_0
18490#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
18491#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
18492#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
18493#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
18494#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4
18495#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5
18496#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6
18497#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L
18498#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L
18499#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L
18500#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L
18501#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L
18502#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L
18503#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L
18504//PA_SC_MODE_CNTL_1
18505#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
18506#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
18507#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
18508#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
18509#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
18510#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
18511#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
18512#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
18513#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
18514#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
18515#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
18516#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
18517#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
18518#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
18519#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
18520#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
18521#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
18522#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
18523#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
18524#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
18525#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
18526#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
18527#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
18528#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
18529#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L
18530#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L
18531#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L
18532#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L
18533#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L
18534#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L
18535#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L
18536#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L
18537#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L
18538#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L
18539#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L
18540#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L
18541#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L
18542#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L
18543#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L
18544#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L
18545#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L
18546#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L
18547#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L
18548#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L
18549#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L
18550#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L
18551#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L
18552#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L
18553//VGT_ENHANCE
18554#define VGT_ENHANCE__MISC__SHIFT 0x0
18555#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL
18556//VGT_GS_PER_ES
18557#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
18558#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL
18559//VGT_ES_PER_GS
18560#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
18561#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL
18562//VGT_GS_PER_VS
18563#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
18564#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL
18565//VGT_GSVS_RING_OFFSET_1
18566#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
18567#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL
18568//VGT_GSVS_RING_OFFSET_2
18569#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
18570#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL
18571//VGT_GSVS_RING_OFFSET_3
18572#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
18573#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL
18574//VGT_GS_OUT_PRIM_TYPE
18575#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
18576#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
18577#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
18578#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
18579#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
18580#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL
18581#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L
18582#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L
18583#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L
18584#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L
18585//IA_ENHANCE
18586#define IA_ENHANCE__MISC__SHIFT 0x0
18587#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL
18588//VGT_DMA_SIZE
18589#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
18590#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL
18591//VGT_DMA_MAX_SIZE
18592#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
18593#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL
18594//VGT_DMA_INDEX_TYPE
18595#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
18596#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
18597#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
18598#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
18599#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
18600#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
18601#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
18602#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
18603#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL
18604#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L
18605#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L
18606#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
18607#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L
18608#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L
18609//WD_ENHANCE
18610#define WD_ENHANCE__MISC__SHIFT 0x0
18611#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL
18612//VGT_PRIMITIVEID_EN
18613#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
18614#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
18615#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2
18616#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L
18617#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L
18618#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L
18619//VGT_DMA_NUM_INSTANCES
18620#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
18621#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
18622//VGT_PRIMITIVEID_RESET
18623#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
18624#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL
18625//VGT_EVENT_INITIATOR
18626#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
18627#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18628#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
18629#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
18630#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
18631#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
18632//VGT_GS_MAX_PRIMS_PER_SUBGROUP
18633#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0
18634#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL
18635//VGT_DRAW_PAYLOAD_CNTL
18636#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0
18637#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1
18638#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2
18639#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3
18640#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L
18641#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
18642#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
18643#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
18644//VGT_INSTANCE_STEP_RATE_0
18645#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
18646#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
18647//VGT_INSTANCE_STEP_RATE_1
18648#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
18649#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL
18650//IA_MULTI_VGT_PARAM_BC
18651//VGT_ESGS_RING_ITEMSIZE
18652#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
18653#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
18654//VGT_GSVS_RING_ITEMSIZE
18655#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
18656#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
18657//VGT_REUSE_OFF
18658#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
18659#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L
18660//VGT_VTX_CNT_EN
18661#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
18662#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L
18663//DB_HTILE_SURFACE
18664#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
18665#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
18666#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
18667#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
18668#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
18669#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
18670#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12
18671#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13
18672#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
18673#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
18674#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
18675#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L
18676#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L
18677#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
18678#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L
18679#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L
18680//DB_SRESULTS_COMPARE_STATE0
18681#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
18682#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
18683#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
18684#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
18685#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
18686#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L
18687#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L
18688#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
18689//DB_SRESULTS_COMPARE_STATE1
18690#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
18691#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
18692#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
18693#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
18694#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
18695#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L
18696#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L
18697#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
18698//DB_PRELOAD_CONTROL
18699#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
18700#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
18701#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
18702#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
18703#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL
18704#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L
18705#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L
18706#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L
18707//VGT_STRMOUT_BUFFER_SIZE_0
18708#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
18709#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL
18710//VGT_STRMOUT_VTX_STRIDE_0
18711#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
18712#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL
18713//VGT_STRMOUT_BUFFER_OFFSET_0
18714#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
18715#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL
18716//VGT_STRMOUT_BUFFER_SIZE_1
18717#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
18718#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL
18719//VGT_STRMOUT_VTX_STRIDE_1
18720#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
18721#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL
18722//VGT_STRMOUT_BUFFER_OFFSET_1
18723#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
18724#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL
18725//VGT_STRMOUT_BUFFER_SIZE_2
18726#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
18727#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL
18728//VGT_STRMOUT_VTX_STRIDE_2
18729#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
18730#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL
18731//VGT_STRMOUT_BUFFER_OFFSET_2
18732#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
18733#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL
18734//VGT_STRMOUT_BUFFER_SIZE_3
18735#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
18736#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL
18737//VGT_STRMOUT_VTX_STRIDE_3
18738#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
18739#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL
18740//VGT_STRMOUT_BUFFER_OFFSET_3
18741#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
18742#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL
18743//VGT_STRMOUT_DRAW_OPAQUE_OFFSET
18744#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
18745#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL
18746//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
18747#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
18748#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL
18749//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
18750#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
18751#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL
18752//VGT_GS_MAX_VERT_OUT
18753#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
18754#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL
18755//VGT_TESS_DISTRIBUTION
18756#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
18757#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
18758#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
18759#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18
18760#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d
18761#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL
18762#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L
18763#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L
18764#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L
18765#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L
18766//VGT_SHADER_STAGES_EN
18767#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
18768#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
18769#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
18770#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
18771#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
18772#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
18773#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
18774#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
18775#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
18776#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd
18777#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe
18778#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf
18779#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13
18780#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L
18781#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L
18782#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L
18783#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L
18784#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L
18785#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L
18786#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L
18787#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L
18788#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L
18789#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L
18790#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L
18791#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L
18792#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L
18793//VGT_LS_HS_CONFIG
18794#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
18795#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
18796#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
18797#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL
18798#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
18799#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L
18800//VGT_GS_VERT_ITEMSIZE
18801#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
18802#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL
18803//VGT_GS_VERT_ITEMSIZE_1
18804#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
18805#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL
18806//VGT_GS_VERT_ITEMSIZE_2
18807#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
18808#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL
18809//VGT_GS_VERT_ITEMSIZE_3
18810#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
18811#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL
18812//VGT_TF_PARAM
18813#define VGT_TF_PARAM__TYPE__SHIFT 0x0
18814#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
18815#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
18816#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
18817#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
18818#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
18819#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
18820#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
18821#define VGT_TF_PARAM__TYPE_MASK 0x00000003L
18822#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL
18823#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L
18824#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L
18825#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L
18826#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L
18827#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L
18828#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L
18829//DB_ALPHA_TO_MASK
18830#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
18831#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
18832#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
18833#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
18834#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
18835#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
18836#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
18837#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
18838#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L
18839#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
18840#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L
18841#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
18842//VGT_DISPATCH_DRAW_INDEX
18843#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
18844#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL
18845//PA_SU_POLY_OFFSET_DB_FMT_CNTL
18846#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
18847#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
18848#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL
18849#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L
18850//PA_SU_POLY_OFFSET_CLAMP
18851#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
18852#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL
18853//PA_SU_POLY_OFFSET_FRONT_SCALE
18854#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
18855#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL
18856//PA_SU_POLY_OFFSET_FRONT_OFFSET
18857#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
18858#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL
18859//PA_SU_POLY_OFFSET_BACK_SCALE
18860#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
18861#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL
18862//PA_SU_POLY_OFFSET_BACK_OFFSET
18863#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
18864#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL
18865//VGT_GS_INSTANCE_CNT
18866#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
18867#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
18868#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L
18869#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL
18870//VGT_STRMOUT_CONFIG
18871#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
18872#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
18873#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
18874#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
18875#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
18876#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7
18877#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
18878#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
18879#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L
18880#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L
18881#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L
18882#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L
18883#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L
18884#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L
18885#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L
18886#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L
18887//VGT_STRMOUT_BUFFER_CONFIG
18888#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
18889#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
18890#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
18891#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
18892#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL
18893#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L
18894#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L
18895#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L
18896//VGT_DMA_EVENT_INITIATOR
18897#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
18898#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa
18899#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
18900#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL
18901#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L
18902#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L
18903//PA_SC_CENTROID_PRIORITY_0
18904#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
18905#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
18906#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
18907#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
18908#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
18909#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
18910#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
18911#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
18912#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL
18913#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L
18914#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L
18915#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L
18916#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L
18917#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L
18918#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L
18919#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L
18920//PA_SC_CENTROID_PRIORITY_1
18921#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
18922#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
18923#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
18924#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
18925#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
18926#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
18927#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
18928#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
18929#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL
18930#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L
18931#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L
18932#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L
18933#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L
18934#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L
18935#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L
18936#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L
18937//PA_SC_LINE_CNTL
18938#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
18939#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
18940#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
18941#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
18942#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd
18943#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L
18944#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L
18945#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L
18946#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L
18947#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L
18948//PA_SC_AA_CONFIG
18949#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
18950#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
18951#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
18952#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
18953#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
18954#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a
18955#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L
18956#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L
18957#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L
18958#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L
18959#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L
18960#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L
18961//PA_SU_VTX_CNTL
18962#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
18963#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
18964#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
18965#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L
18966#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L
18967#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L
18968//PA_CL_GB_VERT_CLIP_ADJ
18969#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
18970#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
18971//PA_CL_GB_VERT_DISC_ADJ
18972#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
18973#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
18974//PA_CL_GB_HORZ_CLIP_ADJ
18975#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
18976#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
18977//PA_CL_GB_HORZ_DISC_ADJ
18978#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
18979#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL
18980//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
18981#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
18982#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
18983#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
18984#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
18985#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
18986#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
18987#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
18988#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
18989#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL
18990#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L
18991#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L
18992#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L
18993#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L
18994#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L
18995#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L
18996#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L
18997//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
18998#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
18999#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
19000#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
19001#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
19002#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
19003#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
19004#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
19005#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
19006#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL
19007#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L
19008#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L
19009#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L
19010#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L
19011#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L
19012#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L
19013#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L
19014//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
19015#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
19016#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
19017#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
19018#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
19019#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
19020#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
19021#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
19022#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
19023#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL
19024#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L
19025#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L
19026#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L
19027#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L
19028#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L
19029#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L
19030#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L
19031//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
19032#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
19033#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
19034#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
19035#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
19036#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
19037#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
19038#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
19039#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
19040#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL
19041#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L
19042#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L
19043#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L
19044#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L
19045#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L
19046#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L
19047#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L
19048//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
19049#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
19050#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
19051#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
19052#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
19053#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
19054#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
19055#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
19056#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
19057#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL
19058#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L
19059#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L
19060#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L
19061#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L
19062#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L
19063#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L
19064#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L
19065//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
19066#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
19067#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
19068#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
19069#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
19070#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
19071#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
19072#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
19073#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
19074#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL
19075#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L
19076#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L
19077#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L
19078#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L
19079#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L
19080#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L
19081#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L
19082//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
19083#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
19084#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
19085#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
19086#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
19087#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
19088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
19089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
19090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
19091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL
19092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L
19093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L
19094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L
19095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L
19096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L
19097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L
19098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L
19099//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
19100#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
19101#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
19102#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
19103#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
19104#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
19105#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
19106#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
19107#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
19108#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL
19109#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L
19110#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L
19111#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L
19112#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L
19113#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L
19114#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L
19115#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L
19116//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
19117#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
19118#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
19119#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
19120#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
19121#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
19122#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
19123#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
19124#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
19125#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL
19126#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L
19127#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L
19128#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L
19129#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L
19130#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L
19131#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L
19132#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L
19133//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
19134#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
19135#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
19136#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
19137#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
19138#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
19139#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
19140#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
19141#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
19142#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL
19143#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L
19144#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L
19145#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L
19146#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L
19147#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L
19148#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L
19149#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L
19150//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
19151#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
19152#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
19153#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
19154#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
19155#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
19156#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
19157#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
19158#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
19159#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL
19160#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L
19161#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L
19162#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L
19163#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L
19164#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L
19165#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L
19166#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L
19167//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
19168#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
19169#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
19170#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
19171#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
19172#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
19173#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
19174#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
19175#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
19176#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL
19177#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L
19178#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L
19179#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L
19180#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L
19181#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L
19182#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L
19183#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L
19184//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
19185#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
19186#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
19187#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
19188#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
19189#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
19190#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
19191#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
19192#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
19193#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL
19194#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L
19195#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L
19196#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L
19197#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L
19198#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L
19199#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L
19200#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L
19201//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
19202#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
19203#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
19204#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
19205#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
19206#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
19207#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
19208#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
19209#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
19210#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL
19211#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L
19212#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L
19213#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L
19214#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L
19215#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L
19216#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L
19217#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L
19218//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
19219#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
19220#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
19221#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
19222#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
19223#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
19224#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
19225#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
19226#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
19227#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL
19228#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L
19229#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L
19230#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L
19231#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L
19232#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L
19233#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L
19234#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L
19235//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
19236#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
19237#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
19238#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
19239#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
19240#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
19241#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
19242#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
19243#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
19244#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL
19245#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L
19246#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L
19247#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L
19248#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L
19249#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L
19250#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L
19251#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L
19252//PA_SC_AA_MASK_X0Y0_X1Y0
19253#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
19254#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
19255#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL
19256#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L
19257//PA_SC_AA_MASK_X0Y1_X1Y1
19258#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
19259#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
19260#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL
19261#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L
19262//PA_SC_SHADER_CONTROL
19263#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0
19264#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2
19265#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3
19266#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L
19267#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L
19268#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L
19269//PA_SC_BINNER_CNTL_0
19270#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0
19271#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2
19272#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3
19273#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4
19274#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7
19275#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa
19276#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd
19277#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12
19278#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13
19279#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b
19280#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c
19281#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L
19282#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L
19283#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L
19284#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L
19285#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L
19286#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L
19287#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L
19288#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L
19289#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L
19290#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L
19291#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L
19292//PA_SC_BINNER_CNTL_1
19293#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0
19294#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10
19295#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL
19296#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L
19297//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
19298#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0
19299#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1
19300#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5
19301#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6
19302#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa
19303#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb
19304#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc
19305#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd
19306#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe
19307#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf
19308#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10
19309#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12
19310#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13
19311#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14
19312#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15
19313#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16
19314#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17
19315#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18
19316#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L
19317#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL
19318#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L
19319#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L
19320#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L
19321#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L
19322#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L
19323#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L
19324#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L
19325#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L
19326#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L
19327#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L
19328#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L
19329#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L
19330#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L
19331#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L
19332#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L
19333#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L
19334//PA_SC_NGG_MODE_CNTL
19335#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0
19336#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL
19337//VGT_VERTEX_REUSE_BLOCK_CNTL
19338#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
19339#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL
19340//VGT_OUT_DEALLOC_CNTL
19341#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
19342#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL
19343//CB_COLOR0_BASE
19344#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
19345#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL
19346//CB_COLOR0_BASE_EXT
19347#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0
19348#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL
19349//CB_COLOR0_ATTRIB2
19350#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19351#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19352#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c
19353#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19354#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19355#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19356//CB_COLOR0_VIEW
19357#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
19358#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
19359#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18
19360#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL
19361#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L
19362#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L
19363//CB_COLOR0_INFO
19364#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
19365#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
19366#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
19367#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
19368#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
19369#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
19370#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
19371#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
19372#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
19373#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
19374#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19375#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19376#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19377#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19378#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
19379#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19380#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
19381#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL
19382#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
19383#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
19384#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
19385#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
19386#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
19387#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
19388#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19389#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
19390#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19391#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19392#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19393#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19394#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L
19395#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
19396//CB_COLOR0_ATTRIB
19397#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0
19398#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb
19399#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
19400#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
19401#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
19402#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
19403#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
19404#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
19405#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e
19406#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
19407#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
19408#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L
19409#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
19410#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
19411#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
19412#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
19413#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
19414#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
19415#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L
19416#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
19417//CB_COLOR0_DCC_CONTROL
19418#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
19419#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
19420#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
19421#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
19422#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
19423#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
19424#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
19425#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19426#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
19427#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
19428#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
19429#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
19430#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
19431#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
19432#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
19433#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
19434#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
19435#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
19436#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
19437#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
19438#define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
19439#define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
19440//CB_COLOR0_CMASK
19441#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
19442#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL
19443//CB_COLOR0_CMASK_BASE_EXT
19444#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19445#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19446//CB_COLOR0_FMASK
19447#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
19448#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL
19449//CB_COLOR0_FMASK_BASE_EXT
19450#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19451#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19452//CB_COLOR0_CLEAR_WORD0
19453#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
19454#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
19455//CB_COLOR0_CLEAR_WORD1
19456#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
19457#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
19458//CB_COLOR0_DCC_BASE
19459#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
19460#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
19461//CB_COLOR0_DCC_BASE_EXT
19462#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
19463#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
19464//CB_COLOR1_BASE
19465#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
19466#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL
19467//CB_COLOR1_BASE_EXT
19468#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0
19469#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL
19470//CB_COLOR1_ATTRIB2
19471#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19472#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19473#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c
19474#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19475#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19476#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19477//CB_COLOR1_VIEW
19478#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
19479#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
19480#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18
19481#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL
19482#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L
19483#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L
19484//CB_COLOR1_INFO
19485#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
19486#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
19487#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
19488#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
19489#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
19490#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
19491#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
19492#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
19493#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
19494#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
19495#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19496#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19497#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19498#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19499#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
19500#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19501#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
19502#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL
19503#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
19504#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
19505#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
19506#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
19507#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
19508#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
19509#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19510#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
19511#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19512#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19513#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19514#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19515#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L
19516#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
19517//CB_COLOR1_ATTRIB
19518#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0
19519#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb
19520#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
19521#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
19522#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
19523#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
19524#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
19525#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
19526#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e
19527#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
19528#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
19529#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L
19530#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
19531#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
19532#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
19533#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
19534#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
19535#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
19536#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L
19537#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
19538//CB_COLOR1_DCC_CONTROL
19539#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
19540#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
19541#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
19542#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
19543#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
19544#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
19545#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
19546#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19547#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
19548#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
19549#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
19550#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
19551#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
19552#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
19553#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
19554#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
19555#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
19556#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
19557#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
19558#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
19559#define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
19560#define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
19561//CB_COLOR1_CMASK
19562#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
19563#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL
19564//CB_COLOR1_CMASK_BASE_EXT
19565#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19566#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19567//CB_COLOR1_FMASK
19568#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
19569#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL
19570//CB_COLOR1_FMASK_BASE_EXT
19571#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19572#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19573//CB_COLOR1_CLEAR_WORD0
19574#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
19575#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
19576//CB_COLOR1_CLEAR_WORD1
19577#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
19578#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
19579//CB_COLOR1_DCC_BASE
19580#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
19581#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
19582//CB_COLOR1_DCC_BASE_EXT
19583#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
19584#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
19585//CB_COLOR2_BASE
19586#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
19587#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL
19588//CB_COLOR2_BASE_EXT
19589#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0
19590#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL
19591//CB_COLOR2_ATTRIB2
19592#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19593#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19594#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c
19595#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19596#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19597#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19598//CB_COLOR2_VIEW
19599#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
19600#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
19601#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18
19602#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL
19603#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L
19604#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L
19605//CB_COLOR2_INFO
19606#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
19607#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
19608#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
19609#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
19610#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
19611#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
19612#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
19613#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
19614#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
19615#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
19616#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19617#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19618#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19619#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19620#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
19621#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19622#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
19623#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL
19624#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
19625#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
19626#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
19627#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
19628#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
19629#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
19630#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19631#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
19632#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19633#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19634#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19635#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19636#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L
19637#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
19638//CB_COLOR2_ATTRIB
19639#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0
19640#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb
19641#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
19642#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
19643#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
19644#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
19645#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
19646#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
19647#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e
19648#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
19649#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
19650#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L
19651#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
19652#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
19653#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
19654#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
19655#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
19656#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
19657#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L
19658#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
19659//CB_COLOR2_DCC_CONTROL
19660#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
19661#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
19662#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
19663#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
19664#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
19665#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
19666#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
19667#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19668#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
19669#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
19670#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
19671#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
19672#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
19673#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
19674#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
19675#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
19676#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
19677#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
19678#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
19679#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
19680#define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
19681#define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
19682//CB_COLOR2_CMASK
19683#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
19684#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL
19685//CB_COLOR2_CMASK_BASE_EXT
19686#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19687#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19688//CB_COLOR2_FMASK
19689#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
19690#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL
19691//CB_COLOR2_FMASK_BASE_EXT
19692#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19693#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19694//CB_COLOR2_CLEAR_WORD0
19695#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
19696#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
19697//CB_COLOR2_CLEAR_WORD1
19698#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
19699#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
19700//CB_COLOR2_DCC_BASE
19701#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
19702#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
19703//CB_COLOR2_DCC_BASE_EXT
19704#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
19705#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
19706//CB_COLOR3_BASE
19707#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
19708#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL
19709//CB_COLOR3_BASE_EXT
19710#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0
19711#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL
19712//CB_COLOR3_ATTRIB2
19713#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19714#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19715#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c
19716#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19717#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19718#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19719//CB_COLOR3_VIEW
19720#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
19721#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
19722#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18
19723#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL
19724#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L
19725#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L
19726//CB_COLOR3_INFO
19727#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
19728#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
19729#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
19730#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
19731#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
19732#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
19733#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
19734#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
19735#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
19736#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
19737#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19738#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19739#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19740#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19741#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
19742#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19743#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
19744#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL
19745#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
19746#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
19747#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
19748#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
19749#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
19750#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
19751#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19752#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
19753#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19754#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19755#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19756#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19757#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L
19758#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
19759//CB_COLOR3_ATTRIB
19760#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0
19761#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb
19762#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
19763#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
19764#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
19765#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
19766#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
19767#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
19768#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e
19769#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
19770#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
19771#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L
19772#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
19773#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
19774#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
19775#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
19776#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
19777#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
19778#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L
19779#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
19780//CB_COLOR3_DCC_CONTROL
19781#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
19782#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
19783#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
19784#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
19785#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
19786#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
19787#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
19788#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19789#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
19790#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
19791#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
19792#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
19793#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
19794#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
19795#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
19796#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
19797#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
19798#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
19799#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
19800#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
19801#define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
19802#define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
19803//CB_COLOR3_CMASK
19804#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
19805#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL
19806//CB_COLOR3_CMASK_BASE_EXT
19807#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19808#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19809//CB_COLOR3_FMASK
19810#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
19811#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL
19812//CB_COLOR3_FMASK_BASE_EXT
19813#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19814#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19815//CB_COLOR3_CLEAR_WORD0
19816#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
19817#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
19818//CB_COLOR3_CLEAR_WORD1
19819#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
19820#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
19821//CB_COLOR3_DCC_BASE
19822#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
19823#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
19824//CB_COLOR3_DCC_BASE_EXT
19825#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
19826#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
19827//CB_COLOR4_BASE
19828#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
19829#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL
19830//CB_COLOR4_BASE_EXT
19831#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0
19832#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL
19833//CB_COLOR4_ATTRIB2
19834#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19835#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19836#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c
19837#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19838#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19839#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19840//CB_COLOR4_VIEW
19841#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
19842#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
19843#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18
19844#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL
19845#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L
19846#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L
19847//CB_COLOR4_INFO
19848#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
19849#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
19850#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
19851#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
19852#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
19853#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
19854#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
19855#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
19856#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
19857#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
19858#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19859#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19860#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19861#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19862#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
19863#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19864#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
19865#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL
19866#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
19867#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
19868#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
19869#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
19870#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
19871#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
19872#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19873#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
19874#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19875#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19876#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19877#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19878#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L
19879#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
19880//CB_COLOR4_ATTRIB
19881#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0
19882#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb
19883#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
19884#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
19885#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
19886#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
19887#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
19888#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
19889#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e
19890#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
19891#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
19892#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L
19893#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
19894#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
19895#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
19896#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
19897#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
19898#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
19899#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L
19900#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
19901//CB_COLOR4_DCC_CONTROL
19902#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
19903#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
19904#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
19905#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
19906#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
19907#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
19908#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
19909#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
19910#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
19911#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
19912#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
19913#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
19914#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
19915#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
19916#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
19917#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
19918#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
19919#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
19920#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
19921#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
19922#define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
19923#define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
19924//CB_COLOR4_CMASK
19925#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
19926#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL
19927//CB_COLOR4_CMASK_BASE_EXT
19928#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19929#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19930//CB_COLOR4_FMASK
19931#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
19932#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL
19933//CB_COLOR4_FMASK_BASE_EXT
19934#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
19935#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
19936//CB_COLOR4_CLEAR_WORD0
19937#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
19938#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
19939//CB_COLOR4_CLEAR_WORD1
19940#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
19941#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
19942//CB_COLOR4_DCC_BASE
19943#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
19944#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
19945//CB_COLOR4_DCC_BASE_EXT
19946#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
19947#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
19948//CB_COLOR5_BASE
19949#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
19950#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL
19951//CB_COLOR5_BASE_EXT
19952#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0
19953#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL
19954//CB_COLOR5_ATTRIB2
19955#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
19956#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
19957#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c
19958#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
19959#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
19960#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L
19961//CB_COLOR5_VIEW
19962#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
19963#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
19964#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18
19965#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL
19966#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L
19967#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L
19968//CB_COLOR5_INFO
19969#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
19970#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
19971#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
19972#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
19973#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
19974#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
19975#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
19976#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
19977#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
19978#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
19979#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
19980#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
19981#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
19982#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
19983#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
19984#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
19985#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
19986#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL
19987#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
19988#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
19989#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
19990#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
19991#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
19992#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
19993#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
19994#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
19995#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
19996#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
19997#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
19998#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
19999#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L
20000#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
20001//CB_COLOR5_ATTRIB
20002#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0
20003#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb
20004#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
20005#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
20006#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
20007#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
20008#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
20009#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
20010#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e
20011#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
20012#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
20013#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L
20014#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
20015#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
20016#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
20017#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
20018#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
20019#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
20020#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L
20021#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
20022//CB_COLOR5_DCC_CONTROL
20023#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
20024#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
20025#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
20026#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
20027#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
20028#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
20029#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
20030#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20031#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
20032#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
20033#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
20034#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
20035#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
20036#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
20037#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
20038#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
20039#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
20040#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
20041#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
20042#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
20043#define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
20044#define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
20045//CB_COLOR5_CMASK
20046#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
20047#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL
20048//CB_COLOR5_CMASK_BASE_EXT
20049#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20050#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20051//CB_COLOR5_FMASK
20052#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
20053#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL
20054//CB_COLOR5_FMASK_BASE_EXT
20055#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20056#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20057//CB_COLOR5_CLEAR_WORD0
20058#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
20059#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
20060//CB_COLOR5_CLEAR_WORD1
20061#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
20062#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
20063//CB_COLOR5_DCC_BASE
20064#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
20065#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
20066//CB_COLOR5_DCC_BASE_EXT
20067#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
20068#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
20069//CB_COLOR6_BASE
20070#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
20071#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL
20072//CB_COLOR6_BASE_EXT
20073#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0
20074#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL
20075//CB_COLOR6_ATTRIB2
20076#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
20077#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
20078#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c
20079#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
20080#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
20081#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L
20082//CB_COLOR6_VIEW
20083#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
20084#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
20085#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18
20086#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL
20087#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L
20088#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L
20089//CB_COLOR6_INFO
20090#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
20091#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
20092#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
20093#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
20094#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
20095#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
20096#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
20097#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
20098#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
20099#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
20100#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
20101#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
20102#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
20103#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
20104#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
20105#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
20106#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
20107#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL
20108#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
20109#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
20110#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
20111#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
20112#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
20113#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
20114#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
20115#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
20116#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
20117#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
20118#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
20119#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
20120#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L
20121#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
20122//CB_COLOR6_ATTRIB
20123#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0
20124#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb
20125#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
20126#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
20127#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
20128#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
20129#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
20130#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
20131#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e
20132#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
20133#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
20134#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L
20135#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
20136#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
20137#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
20138#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
20139#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
20140#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
20141#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L
20142#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
20143//CB_COLOR6_DCC_CONTROL
20144#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
20145#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
20146#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
20147#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
20148#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
20149#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
20150#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
20151#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20152#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
20153#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
20154#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
20155#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
20156#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
20157#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
20158#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
20159#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
20160#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
20161#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
20162#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
20163#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
20164#define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
20165#define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
20166//CB_COLOR6_CMASK
20167#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
20168#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL
20169//CB_COLOR6_CMASK_BASE_EXT
20170#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20171#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20172//CB_COLOR6_FMASK
20173#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
20174#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL
20175//CB_COLOR6_FMASK_BASE_EXT
20176#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20177#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20178//CB_COLOR6_CLEAR_WORD0
20179#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
20180#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
20181//CB_COLOR6_CLEAR_WORD1
20182#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
20183#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
20184//CB_COLOR6_DCC_BASE
20185#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
20186#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
20187//CB_COLOR6_DCC_BASE_EXT
20188#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
20189#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
20190//CB_COLOR7_BASE
20191#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
20192#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL
20193//CB_COLOR7_BASE_EXT
20194#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0
20195#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL
20196//CB_COLOR7_ATTRIB2
20197#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0
20198#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe
20199#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c
20200#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL
20201#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L
20202#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L
20203//CB_COLOR7_VIEW
20204#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
20205#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
20206#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18
20207#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL
20208#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L
20209#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L
20210//CB_COLOR7_INFO
20211#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
20212#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
20213#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
20214#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
20215#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
20216#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
20217#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
20218#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
20219#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
20220#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
20221#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
20222#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
20223#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
20224#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
20225#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
20226#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
20227#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
20228#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL
20229#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
20230#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
20231#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
20232#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
20233#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
20234#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
20235#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
20236#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
20237#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
20238#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
20239#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
20240#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L
20241#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L
20242#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L
20243//CB_COLOR7_ATTRIB
20244#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0
20245#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb
20246#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
20247#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
20248#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
20249#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12
20250#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17
20251#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c
20252#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e
20253#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f
20254#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL
20255#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L
20256#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
20257#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
20258#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
20259#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L
20260#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L
20261#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L
20262#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L
20263#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L
20264//CB_COLOR7_DCC_CONTROL
20265#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
20266#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
20267#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
20268#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
20269#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
20270#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
20271#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
20272#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
20273#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
20274#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12
20275#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13
20276#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
20277#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L
20278#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL
20279#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L
20280#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L
20281#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L
20282#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L
20283#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L
20284#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L
20285#define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L
20286#define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L
20287//CB_COLOR7_CMASK
20288#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
20289#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL
20290//CB_COLOR7_CMASK_BASE_EXT
20291#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20292#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20293//CB_COLOR7_FMASK
20294#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
20295#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL
20296//CB_COLOR7_FMASK_BASE_EXT
20297#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0
20298#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL
20299//CB_COLOR7_CLEAR_WORD0
20300#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
20301#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL
20302//CB_COLOR7_CLEAR_WORD1
20303#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
20304#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL
20305//CB_COLOR7_DCC_BASE
20306#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
20307#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL
20308//CB_COLOR7_DCC_BASE_EXT
20309#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0
20310#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL
20311
20312
20313// addressBlock: gc_gfxudec
20314//CP_EOP_DONE_ADDR_LO
20315#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
20316#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL
20317//CP_EOP_DONE_ADDR_HI
20318#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
20319#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20320//CP_EOP_DONE_DATA_LO
20321#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
20322#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL
20323//CP_EOP_DONE_DATA_HI
20324#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
20325#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL
20326//CP_EOP_LAST_FENCE_LO
20327#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
20328#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL
20329//CP_EOP_LAST_FENCE_HI
20330#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
20331#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL
20332//CP_STREAM_OUT_ADDR_LO
20333#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
20334#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL
20335//CP_STREAM_OUT_ADDR_HI
20336#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
20337#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL
20338//CP_NUM_PRIM_WRITTEN_COUNT0_LO
20339#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
20340#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL
20341//CP_NUM_PRIM_WRITTEN_COUNT0_HI
20342#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
20343#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL
20344//CP_NUM_PRIM_NEEDED_COUNT0_LO
20345#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
20346#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL
20347//CP_NUM_PRIM_NEEDED_COUNT0_HI
20348#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
20349#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL
20350//CP_NUM_PRIM_WRITTEN_COUNT1_LO
20351#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
20352#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL
20353//CP_NUM_PRIM_WRITTEN_COUNT1_HI
20354#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
20355#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL
20356//CP_NUM_PRIM_NEEDED_COUNT1_LO
20357#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
20358#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL
20359//CP_NUM_PRIM_NEEDED_COUNT1_HI
20360#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
20361#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL
20362//CP_NUM_PRIM_WRITTEN_COUNT2_LO
20363#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
20364#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL
20365//CP_NUM_PRIM_WRITTEN_COUNT2_HI
20366#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
20367#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL
20368//CP_NUM_PRIM_NEEDED_COUNT2_LO
20369#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
20370#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL
20371//CP_NUM_PRIM_NEEDED_COUNT2_HI
20372#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
20373#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL
20374//CP_NUM_PRIM_WRITTEN_COUNT3_LO
20375#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
20376#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL
20377//CP_NUM_PRIM_WRITTEN_COUNT3_HI
20378#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
20379#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL
20380//CP_NUM_PRIM_NEEDED_COUNT3_LO
20381#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
20382#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL
20383//CP_NUM_PRIM_NEEDED_COUNT3_HI
20384#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
20385#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL
20386//CP_PIPE_STATS_ADDR_LO
20387#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
20388#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL
20389//CP_PIPE_STATS_ADDR_HI
20390#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
20391#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL
20392//CP_VGT_IAVERT_COUNT_LO
20393#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
20394#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL
20395//CP_VGT_IAVERT_COUNT_HI
20396#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
20397#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL
20398//CP_VGT_IAPRIM_COUNT_LO
20399#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
20400#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL
20401//CP_VGT_IAPRIM_COUNT_HI
20402#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
20403#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL
20404//CP_VGT_GSPRIM_COUNT_LO
20405#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
20406#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL
20407//CP_VGT_GSPRIM_COUNT_HI
20408#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
20409#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL
20410//CP_VGT_VSINVOC_COUNT_LO
20411#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
20412#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20413//CP_VGT_VSINVOC_COUNT_HI
20414#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
20415#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20416//CP_VGT_GSINVOC_COUNT_LO
20417#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
20418#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20419//CP_VGT_GSINVOC_COUNT_HI
20420#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
20421#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20422//CP_VGT_HSINVOC_COUNT_LO
20423#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
20424#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20425//CP_VGT_HSINVOC_COUNT_HI
20426#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
20427#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20428//CP_VGT_DSINVOC_COUNT_LO
20429#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
20430#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20431//CP_VGT_DSINVOC_COUNT_HI
20432#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
20433#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20434//CP_PA_CINVOC_COUNT_LO
20435#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
20436#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20437//CP_PA_CINVOC_COUNT_HI
20438#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
20439#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20440//CP_PA_CPRIM_COUNT_LO
20441#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
20442#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL
20443//CP_PA_CPRIM_COUNT_HI
20444#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
20445#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL
20446//CP_SC_PSINVOC_COUNT0_LO
20447#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
20448#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL
20449//CP_SC_PSINVOC_COUNT0_HI
20450#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
20451#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL
20452//CP_SC_PSINVOC_COUNT1_LO
20453#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
20454#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL
20455//CP_SC_PSINVOC_COUNT1_HI
20456#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
20457#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL
20458//CP_VGT_CSINVOC_COUNT_LO
20459#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
20460#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL
20461//CP_VGT_CSINVOC_COUNT_HI
20462#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
20463#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL
20464//CP_PIPE_STATS_CONTROL
20465#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19
20466#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L
20467//CP_STREAM_OUT_CONTROL
20468#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19
20469#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L
20470//CP_STRMOUT_CNTL
20471#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
20472#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
20473//SCRATCH_REG0
20474#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
20475#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
20476//SCRATCH_REG1
20477#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
20478#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
20479//SCRATCH_REG2
20480#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
20481#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
20482//SCRATCH_REG3
20483#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
20484#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
20485//SCRATCH_REG4
20486#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
20487#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
20488//SCRATCH_REG5
20489#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
20490#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
20491//SCRATCH_REG6
20492#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
20493#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
20494//SCRATCH_REG7
20495#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
20496#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
20497//CP_APPEND_DATA_HI
20498#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0
20499#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL
20500//CP_APPEND_LAST_CS_FENCE_HI
20501#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0
20502#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
20503//CP_APPEND_LAST_PS_FENCE_HI
20504#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0
20505#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL
20506//SCRATCH_UMSK
20507#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
20508#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
20509#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL
20510#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L
20511//SCRATCH_ADDR
20512#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
20513#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL
20514//CP_PFP_ATOMIC_PREOP_LO
20515#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
20516#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
20517//CP_PFP_ATOMIC_PREOP_HI
20518#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
20519#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
20520//CP_PFP_GDS_ATOMIC0_PREOP_LO
20521#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
20522#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
20523//CP_PFP_GDS_ATOMIC0_PREOP_HI
20524#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
20525#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
20526//CP_PFP_GDS_ATOMIC1_PREOP_LO
20527#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
20528#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
20529//CP_PFP_GDS_ATOMIC1_PREOP_HI
20530#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
20531#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
20532//CP_APPEND_ADDR_LO
20533#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
20534#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL
20535//CP_APPEND_ADDR_HI
20536#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
20537#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
20538#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
20539#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
20540#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL
20541#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L
20542#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L
20543#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L
20544//CP_APPEND_DATA_LO
20545#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0
20546#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL
20547//CP_APPEND_LAST_CS_FENCE_LO
20548#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0
20549#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
20550//CP_APPEND_LAST_PS_FENCE_LO
20551#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0
20552#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL
20553//CP_ATOMIC_PREOP_LO
20554#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
20555#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
20556//CP_ME_ATOMIC_PREOP_LO
20557#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
20558#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL
20559//CP_ATOMIC_PREOP_HI
20560#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
20561#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
20562//CP_ME_ATOMIC_PREOP_HI
20563#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
20564#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL
20565//CP_GDS_ATOMIC0_PREOP_LO
20566#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
20567#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
20568//CP_ME_GDS_ATOMIC0_PREOP_LO
20569#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
20570#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL
20571//CP_GDS_ATOMIC0_PREOP_HI
20572#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
20573#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
20574//CP_ME_GDS_ATOMIC0_PREOP_HI
20575#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
20576#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL
20577//CP_GDS_ATOMIC1_PREOP_LO
20578#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
20579#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
20580//CP_ME_GDS_ATOMIC1_PREOP_LO
20581#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
20582#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL
20583//CP_GDS_ATOMIC1_PREOP_HI
20584#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
20585#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
20586//CP_ME_GDS_ATOMIC1_PREOP_HI
20587#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
20588#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL
20589//CP_ME_MC_WADDR_LO
20590#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
20591#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL
20592//CP_ME_MC_WADDR_HI
20593#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
20594#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
20595#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL
20596#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L
20597//CP_ME_MC_WDATA_LO
20598#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
20599#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL
20600//CP_ME_MC_WDATA_HI
20601#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
20602#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL
20603//CP_ME_MC_RADDR_LO
20604#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
20605#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL
20606//CP_ME_MC_RADDR_HI
20607#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
20608#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
20609#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL
20610#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L
20611//CP_SEM_WAIT_TIMER
20612#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
20613#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL
20614//CP_SIG_SEM_ADDR_LO
20615#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
20616#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
20617#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
20618#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
20619//CP_SIG_SEM_ADDR_HI
20620#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
20621#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
20622#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
20623#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
20624#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
20625#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
20626#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
20627#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
20628#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
20629#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
20630//CP_WAIT_REG_MEM_TIMEOUT
20631#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
20632#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL
20633//CP_WAIT_SEM_ADDR_LO
20634#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
20635#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
20636#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
20637#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L
20638//CP_WAIT_SEM_ADDR_HI
20639#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
20640#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
20641#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
20642#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
20643#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
20644#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL
20645#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
20646#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
20647#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
20648#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L
20649//CP_DMA_PFP_CONTROL
20650#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
20651#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
20652#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
20653#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
20654#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
20655#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
20656#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
20657#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L
20658#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
20659#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L
20660//CP_DMA_ME_CONTROL
20661#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa
20662#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
20663#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
20664#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
20665#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
20666#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L
20667#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L
20668#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L
20669#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L
20670#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L
20671//CP_COHER_BASE_HI
20672#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
20673#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
20674//CP_COHER_START_DELAY
20675#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
20676#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL
20677//CP_COHER_CNTL
20678#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
20679#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4
20680#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5
20681#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
20682#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
20683#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
20684#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
20685#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
20686#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
20687#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
20688#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
20689#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
20690#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
20691#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L
20692#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L
20693#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L
20694#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
20695#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
20696#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
20697#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
20698#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
20699#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
20700#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
20701#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
20702#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
20703#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L
20704//CP_COHER_SIZE
20705#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
20706#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
20707//CP_COHER_BASE
20708#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
20709#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
20710//CP_COHER_STATUS
20711#define CP_COHER_STATUS__MEID__SHIFT 0x18
20712#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
20713#define CP_COHER_STATUS__MEID_MASK 0x03000000L
20714#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
20715//CP_DMA_ME_SRC_ADDR
20716#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
20717#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
20718//CP_DMA_ME_SRC_ADDR_HI
20719#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
20720#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
20721//CP_DMA_ME_DST_ADDR
20722#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
20723#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
20724//CP_DMA_ME_DST_ADDR_HI
20725#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
20726#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
20727//CP_DMA_ME_COMMAND
20728#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
20729#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
20730#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
20731#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
20732#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
20733#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
20734#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f
20735#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
20736#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
20737#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
20738#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
20739#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
20740#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
20741#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L
20742//CP_DMA_PFP_SRC_ADDR
20743#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
20744#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL
20745//CP_DMA_PFP_SRC_ADDR_HI
20746#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
20747#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL
20748//CP_DMA_PFP_DST_ADDR
20749#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
20750#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL
20751//CP_DMA_PFP_DST_ADDR_HI
20752#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
20753#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL
20754//CP_DMA_PFP_COMMAND
20755#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
20756#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
20757#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
20758#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
20759#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
20760#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
20761#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f
20762#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL
20763#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
20764#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
20765#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
20766#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
20767#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
20768#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L
20769//CP_DMA_CNTL
20770#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0
20771#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
20772#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
20773#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
20774#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
20775#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
20776#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L
20777#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
20778#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L
20779#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
20780#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
20781#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L
20782//CP_DMA_READ_TAGS
20783#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
20784#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
20785#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL
20786#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
20787//CP_COHER_SIZE_HI
20788#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
20789#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
20790//CP_PFP_IB_CONTROL
20791#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
20792#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL
20793//CP_PFP_LOAD_CONTROL
20794#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
20795#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
20796#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
20797#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
20798#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
20799#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
20800#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
20801#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
20802//CP_SCRATCH_INDEX
20803#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
20804#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL
20805//CP_SCRATCH_DATA
20806#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
20807#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
20808//CP_RB_OFFSET
20809#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
20810#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
20811//CP_IB1_OFFSET
20812#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
20813#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
20814//CP_IB2_OFFSET
20815#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
20816#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
20817//CP_IB1_PREAMBLE_BEGIN
20818#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
20819#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL
20820//CP_IB1_PREAMBLE_END
20821#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
20822#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL
20823//CP_IB2_PREAMBLE_BEGIN
20824#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
20825#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL
20826//CP_IB2_PREAMBLE_END
20827#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
20828#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL
20829//CP_CE_IB1_OFFSET
20830#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
20831#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL
20832//CP_CE_IB2_OFFSET
20833#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
20834#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL
20835//CP_CE_COUNTER
20836#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
20837#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
20838//CP_CE_RB_OFFSET
20839#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
20840#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL
20841//CP_CE_INIT_CMD_BUFSZ
20842#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0
20843#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL
20844//CP_CE_IB1_CMD_BUFSZ
20845#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
20846#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
20847//CP_CE_IB2_CMD_BUFSZ
20848#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
20849#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
20850//CP_IB1_CMD_BUFSZ
20851#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0
20852#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL
20853//CP_IB2_CMD_BUFSZ
20854#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0
20855#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL
20856//CP_ST_CMD_BUFSZ
20857#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0
20858#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL
20859//CP_CE_INIT_BASE_LO
20860#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
20861#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L
20862//CP_CE_INIT_BASE_HI
20863#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
20864#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL
20865//CP_CE_INIT_BUFSZ
20866#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
20867#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL
20868//CP_CE_IB1_BASE_LO
20869#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
20870#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
20871//CP_CE_IB1_BASE_HI
20872#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
20873#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
20874//CP_CE_IB1_BUFSZ
20875#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
20876#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
20877//CP_CE_IB2_BASE_LO
20878#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
20879#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
20880//CP_CE_IB2_BASE_HI
20881#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
20882#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
20883//CP_CE_IB2_BUFSZ
20884#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
20885#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
20886//CP_IB1_BASE_LO
20887#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
20888#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL
20889//CP_IB1_BASE_HI
20890#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
20891#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL
20892//CP_IB1_BUFSZ
20893#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
20894#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL
20895//CP_IB2_BASE_LO
20896#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
20897#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL
20898//CP_IB2_BASE_HI
20899#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
20900#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL
20901//CP_IB2_BUFSZ
20902#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
20903#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL
20904//CP_ST_BASE_LO
20905#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
20906#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL
20907//CP_ST_BASE_HI
20908#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
20909#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL
20910//CP_ST_BUFSZ
20911#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
20912#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL
20913//CP_EOP_DONE_EVENT_CNTL
20914#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
20915#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
20916#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19
20917#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c
20918#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL
20919#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L
20920#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L
20921#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L
20922//CP_EOP_DONE_DATA_CNTL
20923#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
20924#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
20925#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
20926#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
20927#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
20928#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L
20929//CP_EOP_DONE_CNTX_ID
20930#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
20931#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL
20932//CP_PFP_COMPLETION_STATUS
20933#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
20934#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L
20935//CP_CE_COMPLETION_STATUS
20936#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
20937#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L
20938//CP_PRED_NOT_VISIBLE
20939#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
20940#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L
20941//CP_PFP_METADATA_BASE_ADDR
20942#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
20943#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20944//CP_PFP_METADATA_BASE_ADDR_HI
20945#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
20946#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20947//CP_CE_METADATA_BASE_ADDR
20948#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
20949#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20950//CP_CE_METADATA_BASE_ADDR_HI
20951#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
20952#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20953//CP_DRAW_INDX_INDR_ADDR
20954#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
20955#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20956//CP_DRAW_INDX_INDR_ADDR_HI
20957#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
20958#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20959//CP_DISPATCH_INDR_ADDR
20960#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
20961#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20962//CP_DISPATCH_INDR_ADDR_HI
20963#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
20964#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20965//CP_INDEX_BASE_ADDR
20966#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
20967#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20968//CP_INDEX_BASE_ADDR_HI
20969#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
20970#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20971//CP_INDEX_TYPE
20972#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
20973#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
20974//CP_GDS_BKUP_ADDR
20975#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
20976#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL
20977//CP_GDS_BKUP_ADDR_HI
20978#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
20979#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL
20980//CP_SAMPLE_STATUS
20981#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
20982#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
20983#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
20984#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
20985#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
20986#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
20987#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
20988#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
20989#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L
20990#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L
20991#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L
20992#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L
20993#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L
20994#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L
20995#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L
20996#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L
20997//CP_ME_COHER_CNTL
20998#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
20999#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
21000#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
21001#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
21002#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
21003#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
21004#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
21005#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
21006#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
21007#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
21008#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
21009#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
21010#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
21011#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
21012#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
21013#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
21014#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
21015#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
21016#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
21017#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
21018#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
21019#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
21020#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
21021#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
21022#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
21023#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
21024//CP_ME_COHER_SIZE
21025#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
21026#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL
21027//CP_ME_COHER_SIZE_HI
21028#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
21029#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL
21030//CP_ME_COHER_BASE
21031#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
21032#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL
21033//CP_ME_COHER_BASE_HI
21034#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
21035#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL
21036//CP_ME_COHER_STATUS
21037#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
21038#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f
21039#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL
21040#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L
21041//RLC_GPM_PERF_COUNT_0
21042#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
21043#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
21044#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
21045#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
21046#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
21047#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
21048#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
21049#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
21050#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL
21051#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L
21052#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L
21053#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L
21054#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L
21055#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L
21056#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L
21057#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L
21058//RLC_GPM_PERF_COUNT_1
21059#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
21060#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
21061#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
21062#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
21063#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
21064#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
21065#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
21066#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
21067#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL
21068#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L
21069#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L
21070#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L
21071#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L
21072#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L
21073#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L
21074#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L
21075//GRBM_GFX_INDEX
21076#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
21077#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
21078#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
21079#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
21080#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
21081#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
21082#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL
21083#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L
21084#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L
21085#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L
21086#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
21087#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L
21088//VGT_GSVS_RING_SIZE
21089#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
21090#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL
21091//VGT_PRIMITIVE_TYPE
21092#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
21093#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
21094//VGT_INDEX_TYPE
21095#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
21096#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8
21097#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L
21098#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L
21099//VGT_STRMOUT_BUFFER_FILLED_SIZE_0
21100#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
21101#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL
21102//VGT_STRMOUT_BUFFER_FILLED_SIZE_1
21103#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
21104#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL
21105//VGT_STRMOUT_BUFFER_FILLED_SIZE_2
21106#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
21107#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL
21108//VGT_STRMOUT_BUFFER_FILLED_SIZE_3
21109#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
21110#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL
21111//VGT_MAX_VTX_INDX
21112#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
21113#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL
21114//VGT_MIN_VTX_INDX
21115#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
21116#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL
21117//VGT_INDX_OFFSET
21118#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
21119#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL
21120//VGT_MULTI_PRIM_IB_RESET_EN
21121#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
21122#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1
21123#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L
21124#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L
21125//VGT_NUM_INDICES
21126#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
21127#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL
21128//VGT_NUM_INSTANCES
21129#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
21130#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL
21131//VGT_TF_RING_SIZE
21132#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
21133#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL
21134//VGT_HS_OFFCHIP_PARAM
21135#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
21136#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
21137#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL
21138#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L
21139//VGT_TF_MEMORY_BASE
21140#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
21141#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL
21142//VGT_TF_MEMORY_BASE_HI
21143#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0
21144#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL
21145//WD_POS_BUF_BASE
21146#define WD_POS_BUF_BASE__BASE__SHIFT 0x0
21147#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL
21148//WD_POS_BUF_BASE_HI
21149#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0
21150#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
21151//WD_CNTL_SB_BUF_BASE
21152#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0
21153#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL
21154//WD_CNTL_SB_BUF_BASE_HI
21155#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0
21156#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
21157//WD_INDEX_BUF_BASE
21158#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0
21159#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL
21160//WD_INDEX_BUF_BASE_HI
21161#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0
21162#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL
21163//IA_MULTI_VGT_PARAM
21164#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
21165#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
21166#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
21167#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
21168#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
21169#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
21170#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15
21171#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16
21172#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17
21173#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL
21174#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L
21175#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L
21176#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L
21177#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L
21178#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L
21179#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
21180#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
21181#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
21182//VGT_INSTANCE_BASE_ID
21183#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
21184#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
21185//PA_SU_LINE_STIPPLE_VALUE
21186#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
21187#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL
21188//PA_SC_LINE_STIPPLE_STATE
21189#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
21190#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
21191#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL
21192#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L
21193//PA_SC_SCREEN_EXTENT_MIN_0
21194#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
21195#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
21196#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL
21197#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L
21198//PA_SC_SCREEN_EXTENT_MAX_0
21199#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
21200#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
21201#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL
21202#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L
21203//PA_SC_SCREEN_EXTENT_MIN_1
21204#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
21205#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
21206#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL
21207#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L
21208//PA_SC_SCREEN_EXTENT_MAX_1
21209#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
21210#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
21211#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL
21212#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L
21213//PA_SC_P3D_TRAP_SCREEN_HV_EN
21214#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
21215#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
21216#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
21217#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
21218//PA_SC_P3D_TRAP_SCREEN_H
21219#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
21220#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
21221//PA_SC_P3D_TRAP_SCREEN_V
21222#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
21223#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
21224//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
21225#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
21226#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
21227//PA_SC_P3D_TRAP_SCREEN_COUNT
21228#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
21229#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
21230//PA_SC_HP3D_TRAP_SCREEN_HV_EN
21231#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
21232#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
21233#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
21234#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
21235//PA_SC_HP3D_TRAP_SCREEN_H
21236#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
21237#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
21238//PA_SC_HP3D_TRAP_SCREEN_V
21239#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
21240#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
21241//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
21242#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
21243#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
21244//PA_SC_HP3D_TRAP_SCREEN_COUNT
21245#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
21246#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
21247//PA_SC_TRAP_SCREEN_HV_EN
21248#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
21249#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
21250#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L
21251#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L
21252//PA_SC_TRAP_SCREEN_H
21253#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
21254#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL
21255//PA_SC_TRAP_SCREEN_V
21256#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
21257#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL
21258//PA_SC_TRAP_SCREEN_OCCURRENCE
21259#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
21260#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL
21261//PA_SC_TRAP_SCREEN_COUNT
21262#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
21263#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL
21264//PA_STATE_STEREO_X
21265#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0
21266#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL
21267//SQ_THREAD_TRACE_BASE
21268#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
21269#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL
21270//SQ_THREAD_TRACE_SIZE
21271#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
21272#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL
21273//SQ_THREAD_TRACE_MASK
21274#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
21275#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
21276#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
21277#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
21278#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
21279#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
21280#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
21281#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL
21282#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L
21283#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L
21284#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L
21285#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L
21286#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L
21287#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L
21288//SQ_THREAD_TRACE_TOKEN_MASK
21289#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
21290#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
21291#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
21292#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL
21293#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L
21294#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L
21295//SQ_THREAD_TRACE_PERF_MASK
21296#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
21297#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
21298#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL
21299#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L
21300//SQ_THREAD_TRACE_CTRL
21301#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
21302#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L
21303//SQ_THREAD_TRACE_MODE
21304#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
21305#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
21306#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
21307#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
21308#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
21309#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
21310#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
21311#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
21312#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
21313#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
21314#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a
21315#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
21316#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
21317#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
21318#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
21319#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L
21320#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L
21321#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L
21322#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L
21323#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L
21324#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L
21325#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L
21326#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L
21327#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L
21328#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L
21329#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L
21330#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L
21331#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L
21332#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L
21333#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L
21334//SQ_THREAD_TRACE_BASE2
21335#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
21336#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL
21337//SQ_THREAD_TRACE_TOKEN_MASK2
21338#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
21339#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL
21340//SQ_THREAD_TRACE_WPTR
21341#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
21342#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
21343#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL
21344#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L
21345//SQ_THREAD_TRACE_STATUS
21346#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
21347#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
21348#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c
21349#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
21350#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
21351#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
21352#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL
21353#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L
21354#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L
21355#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L
21356#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L
21357#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L
21358//SQ_THREAD_TRACE_HIWATER
21359#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
21360#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L
21361//SQ_THREAD_TRACE_CNTR
21362#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
21363#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL
21364//SQ_THREAD_TRACE_USERDATA_0
21365#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
21366#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL
21367//SQ_THREAD_TRACE_USERDATA_1
21368#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
21369#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL
21370//SQ_THREAD_TRACE_USERDATA_2
21371#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
21372#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL
21373//SQ_THREAD_TRACE_USERDATA_3
21374#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
21375#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL
21376//SQC_CACHES
21377#define SQC_CACHES__TARGET_INST__SHIFT 0x0
21378#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
21379#define SQC_CACHES__INVALIDATE__SHIFT 0x2
21380#define SQC_CACHES__WRITEBACK__SHIFT 0x3
21381#define SQC_CACHES__VOL__SHIFT 0x4
21382#define SQC_CACHES__COMPLETE__SHIFT 0x10
21383#define SQC_CACHES__TARGET_INST_MASK 0x00000001L
21384#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L
21385#define SQC_CACHES__INVALIDATE_MASK 0x00000004L
21386#define SQC_CACHES__WRITEBACK_MASK 0x00000008L
21387#define SQC_CACHES__VOL_MASK 0x00000010L
21388#define SQC_CACHES__COMPLETE_MASK 0x00010000L
21389//SQC_WRITEBACK
21390#define SQC_WRITEBACK__DWB__SHIFT 0x0
21391#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
21392#define SQC_WRITEBACK__DWB_MASK 0x00000001L
21393#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L
21394//TA_CS_BC_BASE_ADDR
21395#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
21396#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL
21397//TA_CS_BC_BASE_ADDR_HI
21398#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
21399#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
21400//DB_OCCLUSION_COUNT0_LOW
21401#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
21402#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
21403//DB_OCCLUSION_COUNT0_HI
21404#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
21405#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL
21406//DB_OCCLUSION_COUNT1_LOW
21407#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
21408#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
21409//DB_OCCLUSION_COUNT1_HI
21410#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
21411#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL
21412//DB_OCCLUSION_COUNT2_LOW
21413#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
21414#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
21415//DB_OCCLUSION_COUNT2_HI
21416#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
21417#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL
21418//DB_OCCLUSION_COUNT3_LOW
21419#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
21420#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
21421//DB_OCCLUSION_COUNT3_HI
21422#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
21423#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL
21424//DB_ZPASS_COUNT_LOW
21425#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
21426#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
21427//DB_ZPASS_COUNT_HI
21428#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
21429#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL
21430//GDS_RD_ADDR
21431#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
21432#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL
21433//GDS_RD_DATA
21434#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
21435#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL
21436//GDS_RD_BURST_ADDR
21437#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
21438#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL
21439//GDS_RD_BURST_COUNT
21440#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
21441#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL
21442//GDS_RD_BURST_DATA
21443#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
21444#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL
21445//GDS_WR_ADDR
21446#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
21447#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
21448//GDS_WR_DATA
21449#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
21450#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
21451//GDS_WR_BURST_ADDR
21452#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
21453#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL
21454//GDS_WR_BURST_DATA
21455#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
21456#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL
21457//GDS_WRITE_COMPLETE
21458#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
21459#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL
21460//GDS_ATOM_CNTL
21461#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
21462#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
21463#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
21464#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
21465#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL
21466#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L
21467#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L
21468#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L
21469//GDS_ATOM_COMPLETE
21470#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
21471#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
21472#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
21473#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL
21474//GDS_ATOM_BASE
21475#define GDS_ATOM_BASE__BASE__SHIFT 0x0
21476#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
21477#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL
21478#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L
21479//GDS_ATOM_SIZE
21480#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
21481#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
21482#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL
21483#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L
21484//GDS_ATOM_OFFSET0
21485#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
21486#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
21487#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL
21488#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L
21489//GDS_ATOM_OFFSET1
21490#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
21491#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
21492#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL
21493#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L
21494//GDS_ATOM_DST
21495#define GDS_ATOM_DST__DST__SHIFT 0x0
21496#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL
21497//GDS_ATOM_OP
21498#define GDS_ATOM_OP__OP__SHIFT 0x0
21499#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
21500#define GDS_ATOM_OP__OP_MASK 0x000000FFL
21501#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L
21502//GDS_ATOM_SRC0
21503#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
21504#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL
21505//GDS_ATOM_SRC0_U
21506#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
21507#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL
21508//GDS_ATOM_SRC1
21509#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
21510#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL
21511//GDS_ATOM_SRC1_U
21512#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
21513#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL
21514//GDS_ATOM_READ0
21515#define GDS_ATOM_READ0__DATA__SHIFT 0x0
21516#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL
21517//GDS_ATOM_READ0_U
21518#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
21519#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL
21520//GDS_ATOM_READ1
21521#define GDS_ATOM_READ1__DATA__SHIFT 0x0
21522#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL
21523//GDS_ATOM_READ1_U
21524#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
21525#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL
21526//GDS_GWS_RESOURCE_CNTL
21527#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
21528#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
21529#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL
21530#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L
21531//GDS_GWS_RESOURCE
21532#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
21533#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
21534#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
21535#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
21536#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
21537#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
21538#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c
21539#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d
21540#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e
21541#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f
21542#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L
21543#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL
21544#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L
21545#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L
21546#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L
21547#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L
21548#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L
21549#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L
21550#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L
21551#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L
21552//GDS_GWS_RESOURCE_CNT
21553#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
21554#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
21555#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL
21556#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L
21557//GDS_OA_CNTL
21558#define GDS_OA_CNTL__INDEX__SHIFT 0x0
21559#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
21560#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL
21561#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L
21562//GDS_OA_COUNTER
21563#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
21564#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL
21565//GDS_OA_ADDRESS
21566#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
21567#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
21568#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
21569#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
21570#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
21571#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
21572#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL
21573#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L
21574#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L
21575#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L
21576#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L
21577#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L
21578//GDS_OA_INCDEC
21579#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
21580#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
21581#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL
21582#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L
21583//GDS_OA_RING_SIZE
21584#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
21585#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL
21586//SPI_CONFIG_CNTL
21587#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
21588#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
21589#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
21590#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
21591#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
21592#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
21593#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c
21594#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d
21595#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e
21596#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL
21597#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L
21598#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L
21599#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L
21600#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L
21601#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L
21602#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L
21603#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L
21604#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L
21605//SPI_CONFIG_CNTL_1
21606#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
21607#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
21608#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5
21609#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
21610#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
21611#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
21612#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
21613#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
21614#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe
21615#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf
21616#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
21617#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL
21618#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L
21619#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L
21620#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L
21621#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L
21622#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L
21623#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L
21624#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L
21625#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L
21626#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L
21627#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L
21628//SPI_CONFIG_CNTL_2
21629#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
21630#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
21631#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL
21632#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L
21633//SPI_WAVE_LIMIT_CNTL
21634#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0
21635#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2
21636#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4
21637#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6
21638#define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L
21639#define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL
21640#define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L
21641#define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L
21642
21643
21644// addressBlock: gc_perfddec
21645//CPG_PERFCOUNTER1_LO
21646#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21647#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21648//CPG_PERFCOUNTER1_HI
21649#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21650#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21651//CPG_PERFCOUNTER0_LO
21652#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21653#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21654//CPG_PERFCOUNTER0_HI
21655#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21656#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21657//CPC_PERFCOUNTER1_LO
21658#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21659#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21660//CPC_PERFCOUNTER1_HI
21661#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21662#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21663//CPC_PERFCOUNTER0_LO
21664#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21665#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21666//CPC_PERFCOUNTER0_HI
21667#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21668#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21669//CPF_PERFCOUNTER1_LO
21670#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21671#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21672//CPF_PERFCOUNTER1_HI
21673#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21674#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21675//CPF_PERFCOUNTER0_LO
21676#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21677#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21678//CPF_PERFCOUNTER0_HI
21679#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21680#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21681//CPF_LATENCY_STATS_DATA
21682#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0
21683#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
21684//CPG_LATENCY_STATS_DATA
21685#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0
21686#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
21687//CPC_LATENCY_STATS_DATA
21688#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0
21689#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL
21690//GRBM_PERFCOUNTER0_LO
21691#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21692#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21693//GRBM_PERFCOUNTER0_HI
21694#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21695#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21696//GRBM_PERFCOUNTER1_LO
21697#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21698#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21699//GRBM_PERFCOUNTER1_HI
21700#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21701#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21702//GRBM_SE0_PERFCOUNTER_LO
21703#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
21704#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21705//GRBM_SE0_PERFCOUNTER_HI
21706#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
21707#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21708//GRBM_SE1_PERFCOUNTER_LO
21709#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
21710#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21711//GRBM_SE1_PERFCOUNTER_HI
21712#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
21713#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21714//GRBM_SE2_PERFCOUNTER_LO
21715#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
21716#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21717//GRBM_SE2_PERFCOUNTER_HI
21718#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
21719#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21720//GRBM_SE3_PERFCOUNTER_LO
21721#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
21722#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21723//GRBM_SE3_PERFCOUNTER_HI
21724#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
21725#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21726//WD_PERFCOUNTER0_LO
21727#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21728#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21729//WD_PERFCOUNTER0_HI
21730#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21731#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21732//WD_PERFCOUNTER1_LO
21733#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21734#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21735//WD_PERFCOUNTER1_HI
21736#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21737#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21738//WD_PERFCOUNTER2_LO
21739#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21740#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21741//WD_PERFCOUNTER2_HI
21742#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21743#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21744//WD_PERFCOUNTER3_LO
21745#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21746#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21747//WD_PERFCOUNTER3_HI
21748#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21749#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21750//IA_PERFCOUNTER0_LO
21751#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21752#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21753//IA_PERFCOUNTER0_HI
21754#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21755#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21756//IA_PERFCOUNTER1_LO
21757#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21758#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21759//IA_PERFCOUNTER1_HI
21760#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21761#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21762//IA_PERFCOUNTER2_LO
21763#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21764#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21765//IA_PERFCOUNTER2_HI
21766#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21767#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21768//IA_PERFCOUNTER3_LO
21769#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21770#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21771//IA_PERFCOUNTER3_HI
21772#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21773#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21774//VGT_PERFCOUNTER0_LO
21775#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21776#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21777//VGT_PERFCOUNTER0_HI
21778#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21779#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21780//VGT_PERFCOUNTER1_LO
21781#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21782#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21783//VGT_PERFCOUNTER1_HI
21784#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21785#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21786//VGT_PERFCOUNTER2_LO
21787#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21788#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21789//VGT_PERFCOUNTER2_HI
21790#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21791#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21792//VGT_PERFCOUNTER3_LO
21793#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21794#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21795//VGT_PERFCOUNTER3_HI
21796#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21797#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21798//PA_SU_PERFCOUNTER0_LO
21799#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21800#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21801//PA_SU_PERFCOUNTER0_HI
21802#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21803#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
21804//PA_SU_PERFCOUNTER1_LO
21805#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21806#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21807//PA_SU_PERFCOUNTER1_HI
21808#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21809#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
21810//PA_SU_PERFCOUNTER2_LO
21811#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21812#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21813//PA_SU_PERFCOUNTER2_HI
21814#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21815#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
21816//PA_SU_PERFCOUNTER3_LO
21817#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21818#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21819//PA_SU_PERFCOUNTER3_HI
21820#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21821#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL
21822//PA_SC_PERFCOUNTER0_LO
21823#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21824#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21825//PA_SC_PERFCOUNTER0_HI
21826#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21827#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21828//PA_SC_PERFCOUNTER1_LO
21829#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21830#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21831//PA_SC_PERFCOUNTER1_HI
21832#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21833#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21834//PA_SC_PERFCOUNTER2_LO
21835#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21836#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21837//PA_SC_PERFCOUNTER2_HI
21838#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21839#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21840//PA_SC_PERFCOUNTER3_LO
21841#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21842#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21843//PA_SC_PERFCOUNTER3_HI
21844#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21845#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21846//PA_SC_PERFCOUNTER4_LO
21847#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
21848#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21849//PA_SC_PERFCOUNTER4_HI
21850#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
21851#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21852//PA_SC_PERFCOUNTER5_LO
21853#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
21854#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21855//PA_SC_PERFCOUNTER5_HI
21856#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
21857#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21858//PA_SC_PERFCOUNTER6_LO
21859#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
21860#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21861//PA_SC_PERFCOUNTER6_HI
21862#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
21863#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21864//PA_SC_PERFCOUNTER7_LO
21865#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
21866#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21867//PA_SC_PERFCOUNTER7_HI
21868#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
21869#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21870//SPI_PERFCOUNTER0_HI
21871#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21872#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21873//SPI_PERFCOUNTER0_LO
21874#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21875#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21876//SPI_PERFCOUNTER1_HI
21877#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21878#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21879//SPI_PERFCOUNTER1_LO
21880#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21881#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21882//SPI_PERFCOUNTER2_HI
21883#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21884#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21885//SPI_PERFCOUNTER2_LO
21886#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21887#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21888//SPI_PERFCOUNTER3_HI
21889#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21890#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21891//SPI_PERFCOUNTER3_LO
21892#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21893#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21894//SPI_PERFCOUNTER4_HI
21895#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
21896#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21897//SPI_PERFCOUNTER4_LO
21898#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
21899#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21900//SPI_PERFCOUNTER5_HI
21901#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
21902#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21903//SPI_PERFCOUNTER5_LO
21904#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
21905#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21906//SQ_PERFCOUNTER0_LO
21907#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
21908#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21909//SQ_PERFCOUNTER0_HI
21910#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
21911#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21912//SQ_PERFCOUNTER1_LO
21913#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
21914#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21915//SQ_PERFCOUNTER1_HI
21916#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
21917#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21918//SQ_PERFCOUNTER2_LO
21919#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
21920#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21921//SQ_PERFCOUNTER2_HI
21922#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
21923#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21924//SQ_PERFCOUNTER3_LO
21925#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
21926#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21927//SQ_PERFCOUNTER3_HI
21928#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
21929#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21930//SQ_PERFCOUNTER4_LO
21931#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
21932#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21933//SQ_PERFCOUNTER4_HI
21934#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
21935#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21936//SQ_PERFCOUNTER5_LO
21937#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
21938#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21939//SQ_PERFCOUNTER5_HI
21940#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
21941#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21942//SQ_PERFCOUNTER6_LO
21943#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
21944#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21945//SQ_PERFCOUNTER6_HI
21946#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
21947#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21948//SQ_PERFCOUNTER7_LO
21949#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
21950#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21951//SQ_PERFCOUNTER7_HI
21952#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
21953#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21954//SQ_PERFCOUNTER8_LO
21955#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
21956#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21957//SQ_PERFCOUNTER8_HI
21958#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
21959#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21960//SQ_PERFCOUNTER9_LO
21961#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
21962#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21963//SQ_PERFCOUNTER9_HI
21964#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
21965#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21966//SQ_PERFCOUNTER10_LO
21967#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
21968#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21969//SQ_PERFCOUNTER10_HI
21970#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
21971#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21972//SQ_PERFCOUNTER11_LO
21973#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
21974#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21975//SQ_PERFCOUNTER11_HI
21976#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
21977#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21978//SQ_PERFCOUNTER12_LO
21979#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
21980#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21981//SQ_PERFCOUNTER12_HI
21982#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
21983#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21984//SQ_PERFCOUNTER13_LO
21985#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
21986#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21987//SQ_PERFCOUNTER13_HI
21988#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
21989#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21990//SQ_PERFCOUNTER14_LO
21991#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
21992#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21993//SQ_PERFCOUNTER14_HI
21994#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
21995#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
21996//SQ_PERFCOUNTER15_LO
21997#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
21998#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
21999//SQ_PERFCOUNTER15_HI
22000#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
22001#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22002//SX_PERFCOUNTER0_LO
22003#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22004#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22005//SX_PERFCOUNTER0_HI
22006#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22007#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22008//SX_PERFCOUNTER1_LO
22009#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22010#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22011//SX_PERFCOUNTER1_HI
22012#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22013#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22014//SX_PERFCOUNTER2_LO
22015#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22016#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22017//SX_PERFCOUNTER2_HI
22018#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22019#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22020//SX_PERFCOUNTER3_LO
22021#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22022#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22023//SX_PERFCOUNTER3_HI
22024#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22025#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22026//GDS_PERFCOUNTER0_LO
22027#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22028#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22029//GDS_PERFCOUNTER0_HI
22030#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22031#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22032//GDS_PERFCOUNTER1_LO
22033#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22034#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22035//GDS_PERFCOUNTER1_HI
22036#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22037#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22038//GDS_PERFCOUNTER2_LO
22039#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22040#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22041//GDS_PERFCOUNTER2_HI
22042#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22043#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22044//GDS_PERFCOUNTER3_LO
22045#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22046#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22047//GDS_PERFCOUNTER3_HI
22048#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22049#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22050//TA_PERFCOUNTER0_LO
22051#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22052#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22053//TA_PERFCOUNTER0_HI
22054#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22055#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22056//TA_PERFCOUNTER1_LO
22057#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22058#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22059//TA_PERFCOUNTER1_HI
22060#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22061#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22062//TD_PERFCOUNTER0_LO
22063#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22064#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22065//TD_PERFCOUNTER0_HI
22066#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22067#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22068//TD_PERFCOUNTER1_LO
22069#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22070#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22071//TD_PERFCOUNTER1_HI
22072#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22073#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22074//TCP_PERFCOUNTER0_LO
22075#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22076#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22077//TCP_PERFCOUNTER0_HI
22078#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22079#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22080//TCP_PERFCOUNTER1_LO
22081#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22082#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22083//TCP_PERFCOUNTER1_HI
22084#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22085#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22086//TCP_PERFCOUNTER2_LO
22087#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22088#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22089//TCP_PERFCOUNTER2_HI
22090#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22091#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22092//TCP_PERFCOUNTER3_LO
22093#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22094#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22095//TCP_PERFCOUNTER3_HI
22096#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22097#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22098//TCC_PERFCOUNTER0_LO
22099#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22100#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22101//TCC_PERFCOUNTER0_HI
22102#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22103#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22104//TCC_PERFCOUNTER1_LO
22105#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22106#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22107//TCC_PERFCOUNTER1_HI
22108#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22109#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22110//TCC_PERFCOUNTER2_LO
22111#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22112#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22113//TCC_PERFCOUNTER2_HI
22114#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22115#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22116//TCC_PERFCOUNTER3_LO
22117#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22118#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22119//TCC_PERFCOUNTER3_HI
22120#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22121#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22122//TCA_PERFCOUNTER0_LO
22123#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22124#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22125//TCA_PERFCOUNTER0_HI
22126#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22127#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22128//TCA_PERFCOUNTER1_LO
22129#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22130#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22131//TCA_PERFCOUNTER1_HI
22132#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22133#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22134//TCA_PERFCOUNTER2_LO
22135#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22136#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22137//TCA_PERFCOUNTER2_HI
22138#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22139#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22140//TCA_PERFCOUNTER3_LO
22141#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22142#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22143//TCA_PERFCOUNTER3_HI
22144#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22145#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22146//CB_PERFCOUNTER0_LO
22147#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22148#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22149//CB_PERFCOUNTER0_HI
22150#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22151#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22152//CB_PERFCOUNTER1_LO
22153#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22154#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22155//CB_PERFCOUNTER1_HI
22156#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22157#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22158//CB_PERFCOUNTER2_LO
22159#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22160#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22161//CB_PERFCOUNTER2_HI
22162#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22163#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22164//CB_PERFCOUNTER3_LO
22165#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22166#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22167//CB_PERFCOUNTER3_HI
22168#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22169#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22170//DB_PERFCOUNTER0_LO
22171#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22172#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22173//DB_PERFCOUNTER0_HI
22174#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22175#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22176//DB_PERFCOUNTER1_LO
22177#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22178#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22179//DB_PERFCOUNTER1_HI
22180#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22181#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22182//DB_PERFCOUNTER2_LO
22183#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22184#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22185//DB_PERFCOUNTER2_HI
22186#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22187#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22188//DB_PERFCOUNTER3_LO
22189#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22190#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22191//DB_PERFCOUNTER3_HI
22192#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22193#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22194//RLC_PERFCOUNTER0_LO
22195#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22196#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22197//RLC_PERFCOUNTER0_HI
22198#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22199#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22200//RLC_PERFCOUNTER1_LO
22201#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22202#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22203//RLC_PERFCOUNTER1_HI
22204#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22205#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22206//RMI_PERFCOUNTER0_LO
22207#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
22208#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22209//RMI_PERFCOUNTER0_HI
22210#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
22211#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22212//RMI_PERFCOUNTER1_LO
22213#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
22214#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22215//RMI_PERFCOUNTER1_HI
22216#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
22217#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22218//RMI_PERFCOUNTER2_LO
22219#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
22220#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22221//RMI_PERFCOUNTER2_HI
22222#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
22223#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22224//RMI_PERFCOUNTER3_LO
22225#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
22226#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL
22227//RMI_PERFCOUNTER3_HI
22228#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
22229#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL
22230
22231
22232// addressBlock: gc_utcl2_atcl2pfcntrdec
22233//ATC_L2_PERFCOUNTER_LO
22234#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
22235#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
22236//ATC_L2_PERFCOUNTER_HI
22237#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
22238#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
22239#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
22240#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
22241
22242
22243// addressBlock: gc_utcl2_vml2prdec
22244//MC_VM_L2_PERFCOUNTER_LO
22245#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
22246#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
22247//MC_VM_L2_PERFCOUNTER_HI
22248#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
22249#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
22250#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
22251#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
22252
22253
22254// addressBlock: gc_perfsdec
22255//CPG_PERFCOUNTER1_SELECT
22256#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
22257#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22258#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
22259#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
22260#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
22261#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
22262#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22263#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
22264#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
22265#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
22266//CPG_PERFCOUNTER0_SELECT1
22267#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
22268#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22269#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
22270#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
22271#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
22272#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
22273#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
22274#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
22275//CPG_PERFCOUNTER0_SELECT
22276#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
22277#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22278#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
22279#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
22280#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
22281#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
22282#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22283#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
22284#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
22285#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
22286//CPC_PERFCOUNTER1_SELECT
22287#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
22288#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22289#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
22290#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
22291#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
22292#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
22293#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22294#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
22295#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
22296#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
22297//CPC_PERFCOUNTER0_SELECT1
22298#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
22299#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22300#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
22301#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
22302#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
22303#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
22304#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
22305#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
22306//CPF_PERFCOUNTER1_SELECT
22307#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0
22308#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa
22309#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
22310#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18
22311#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c
22312#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL
22313#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22314#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
22315#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L
22316#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L
22317//CPF_PERFCOUNTER0_SELECT1
22318#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0
22319#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa
22320#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18
22321#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c
22322#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL
22323#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L
22324#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L
22325#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L
22326//CPF_PERFCOUNTER0_SELECT
22327#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
22328#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22329#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
22330#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
22331#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
22332#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
22333#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22334#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
22335#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
22336#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
22337//CP_PERFMON_CNTL
22338#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
22339#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
22340#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
22341#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
22342#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL
22343#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L
22344#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
22345#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
22346//CPC_PERFCOUNTER0_SELECT
22347#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0
22348#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa
22349#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
22350#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18
22351#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c
22352#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL
22353#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L
22354#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
22355#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L
22356#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L
22357//CPF_TC_PERF_COUNTER_WINDOW_SELECT
22358#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
22359#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
22360#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
22361#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L
22362#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
22363#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
22364//CPG_TC_PERF_COUNTER_WINDOW_SELECT
22365#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0
22366#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e
22367#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f
22368#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL
22369#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L
22370#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L
22371//CPF_LATENCY_STATS_SELECT
22372#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
22373#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
22374#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
22375#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL
22376#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
22377#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
22378//CPG_LATENCY_STATS_SELECT
22379#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
22380#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
22381#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
22382#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL
22383#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
22384#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
22385//CPC_LATENCY_STATS_SELECT
22386#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0
22387#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e
22388#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f
22389#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L
22390#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L
22391#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L
22392//CP_DRAW_OBJECT
22393#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
22394#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL
22395//CP_DRAW_OBJECT_COUNTER
22396#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
22397#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL
22398//CP_DRAW_WINDOW_MASK_HI
22399#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
22400#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL
22401//CP_DRAW_WINDOW_HI
22402#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
22403#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL
22404//CP_DRAW_WINDOW_LO
22405#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
22406#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
22407#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL
22408#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L
22409//CP_DRAW_WINDOW_CNTL
22410#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
22411#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
22412#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
22413#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
22414#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L
22415#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L
22416#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L
22417#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L
22418//GRBM_PERFCOUNTER0_SELECT
22419#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22420#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22421#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22422#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22423#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22424#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
22425#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22426#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22427#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22428#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22429#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22430#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22431#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22432#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
22433#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
22434#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
22435#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
22436#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
22437#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
22438#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
22439#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
22440#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
22441#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL
22442#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22443#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22444#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22445#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22446#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
22447#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22448#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22449#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22450#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22451#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22452#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22453#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22454#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
22455#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
22456#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
22457#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
22458#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
22459#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
22460#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
22461#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
22462#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
22463//GRBM_PERFCOUNTER1_SELECT
22464#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22465#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22466#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22467#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22468#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22469#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
22470#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22471#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22472#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22473#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22474#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22475#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22476#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22477#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
22478#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
22479#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
22480#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
22481#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
22482#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
22483#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d
22484#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e
22485#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f
22486#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL
22487#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22488#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22489#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22490#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22491#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L
22492#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22493#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22494#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22495#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22496#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22497#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22498#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22499#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L
22500#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L
22501#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L
22502#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L
22503#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L
22504#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L
22505#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L
22506#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L
22507#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L
22508//GRBM_SE0_PERFCOUNTER_SELECT
22509#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
22510#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22511#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22512#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22513#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22514#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
22515#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22516#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22517#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22518#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22519#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22520#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22521#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22522#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
22523#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22524#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22525#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22526#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22527#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
22528#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22529#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22530#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22531#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22532#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22533#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22534#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22535//GRBM_SE1_PERFCOUNTER_SELECT
22536#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
22537#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22538#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22539#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22540#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22541#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
22542#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22543#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22544#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22545#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22546#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22547#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22548#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22549#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
22550#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22551#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22552#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22553#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22554#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
22555#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22556#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22557#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22558#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22559#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22560#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22561#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22562//GRBM_SE2_PERFCOUNTER_SELECT
22563#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
22564#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22565#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22566#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22567#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22568#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
22569#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22570#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22571#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22572#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22573#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22574#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22575#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22576#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
22577#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22578#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22579#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22580#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22581#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
22582#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22583#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22584#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22585#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22586#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22587#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22588#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22589//GRBM_SE3_PERFCOUNTER_SELECT
22590#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
22591#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
22592#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
22593#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
22594#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
22595#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
22596#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
22597#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
22598#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
22599#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
22600#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
22601#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
22602#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16
22603#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL
22604#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L
22605#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L
22606#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L
22607#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L
22608#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L
22609#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L
22610#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L
22611#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L
22612#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L
22613#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L
22614#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L
22615#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L
22616//WD_PERFCOUNTER0_SELECT
22617#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22618#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22619#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
22620#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22621//WD_PERFCOUNTER1_SELECT
22622#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22623#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22624#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
22625#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22626//WD_PERFCOUNTER2_SELECT
22627#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22628#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22629#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
22630#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22631//WD_PERFCOUNTER3_SELECT
22632#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22633#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22634#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
22635#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22636//IA_PERFCOUNTER0_SELECT
22637#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22638#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22639#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
22640#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
22641#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22642#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
22643#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
22644#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
22645#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
22646#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22647//IA_PERFCOUNTER1_SELECT
22648#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22649#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22650#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
22651#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22652//IA_PERFCOUNTER2_SELECT
22653#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22654#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22655#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
22656#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22657//IA_PERFCOUNTER3_SELECT
22658#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22659#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22660#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
22661#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22662//IA_PERFCOUNTER0_SELECT1
22663#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
22664#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22665#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
22666#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
22667#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
22668#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22669#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
22670#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
22671//VGT_PERFCOUNTER0_SELECT
22672#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22673#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22674#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
22675#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
22676#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22677#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
22678#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
22679#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
22680#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
22681#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22682//VGT_PERFCOUNTER1_SELECT
22683#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22684#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22685#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
22686#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
22687#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22688#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
22689#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
22690#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
22691#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
22692#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22693//VGT_PERFCOUNTER2_SELECT
22694#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22695#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22696#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL
22697#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22698//VGT_PERFCOUNTER3_SELECT
22699#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22700#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22701#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL
22702#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22703//VGT_PERFCOUNTER0_SELECT1
22704#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
22705#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22706#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
22707#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
22708#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
22709#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22710#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
22711#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
22712//VGT_PERFCOUNTER1_SELECT1
22713#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
22714#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22715#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
22716#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
22717#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
22718#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22719#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
22720#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
22721//VGT_PERFCOUNTER_SEID_MASK
22722#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
22723#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL
22724//PA_SU_PERFCOUNTER0_SELECT
22725#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22726#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22727#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
22728#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
22729#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22730#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
22731#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
22732#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
22733#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
22734#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22735//PA_SU_PERFCOUNTER0_SELECT1
22736#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
22737#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22738#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
22739#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
22740#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
22741#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22742#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
22743#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
22744//PA_SU_PERFCOUNTER1_SELECT
22745#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22746#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22747#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
22748#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
22749#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22750#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
22751#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
22752#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
22753#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
22754#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22755//PA_SU_PERFCOUNTER1_SELECT1
22756#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
22757#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22758#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
22759#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
22760#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
22761#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22762#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
22763#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
22764//PA_SU_PERFCOUNTER2_SELECT
22765#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22766#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
22767#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22768#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
22769#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
22770#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22771//PA_SU_PERFCOUNTER3_SELECT
22772#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22773#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
22774#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22775#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
22776#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
22777#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22778//PA_SC_PERFCOUNTER0_SELECT
22779#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22780#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22781#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
22782#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
22783#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22784#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
22785#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
22786#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
22787#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
22788#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22789//PA_SC_PERFCOUNTER0_SELECT1
22790#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
22791#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22792#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
22793#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
22794#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
22795#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22796#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
22797#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
22798//PA_SC_PERFCOUNTER1_SELECT
22799#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22800#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
22801//PA_SC_PERFCOUNTER2_SELECT
22802#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22803#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
22804//PA_SC_PERFCOUNTER3_SELECT
22805#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22806#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
22807//PA_SC_PERFCOUNTER4_SELECT
22808#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
22809#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL
22810//PA_SC_PERFCOUNTER5_SELECT
22811#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
22812#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL
22813//PA_SC_PERFCOUNTER6_SELECT
22814#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
22815#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL
22816//PA_SC_PERFCOUNTER7_SELECT
22817#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
22818#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL
22819//SPI_PERFCOUNTER0_SELECT
22820#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22821#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
22822#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
22823#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
22824#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22825#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
22826#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
22827#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
22828#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
22829#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22830//SPI_PERFCOUNTER1_SELECT
22831#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22832#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
22833#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
22834#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
22835#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22836#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
22837#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
22838#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
22839#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
22840#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22841//SPI_PERFCOUNTER2_SELECT
22842#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22843#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
22844#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
22845#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
22846#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22847#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
22848#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
22849#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
22850#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
22851#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22852//SPI_PERFCOUNTER3_SELECT
22853#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22854#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
22855#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
22856#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
22857#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22858#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
22859#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
22860#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
22861#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
22862#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22863//SPI_PERFCOUNTER0_SELECT1
22864#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
22865#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
22866#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
22867#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
22868#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
22869#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22870#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
22871#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
22872//SPI_PERFCOUNTER1_SELECT1
22873#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
22874#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
22875#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
22876#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
22877#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
22878#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22879#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
22880#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
22881//SPI_PERFCOUNTER2_SELECT1
22882#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
22883#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
22884#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
22885#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
22886#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL
22887#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22888#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
22889#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
22890//SPI_PERFCOUNTER3_SELECT1
22891#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
22892#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
22893#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18
22894#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c
22895#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL
22896#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L
22897#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L
22898#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L
22899//SPI_PERFCOUNTER4_SELECT
22900#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
22901#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL
22902//SPI_PERFCOUNTER5_SELECT
22903#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
22904#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL
22905//SPI_PERFCOUNTER_BINS
22906#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
22907#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
22908#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
22909#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
22910#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
22911#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
22912#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
22913#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
22914#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL
22915#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L
22916#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L
22917#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L
22918#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L
22919#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L
22920#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L
22921#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L
22922//SQ_PERFCOUNTER0_SELECT
22923#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
22924#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
22925#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22926#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
22927#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
22928#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
22929#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
22930#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22931#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22932#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L
22933#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L
22934#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
22935//SQ_PERFCOUNTER1_SELECT
22936#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
22937#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
22938#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22939#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
22940#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
22941#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
22942#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
22943#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22944#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22945#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L
22946#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L
22947#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
22948//SQ_PERFCOUNTER2_SELECT
22949#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
22950#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
22951#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22952#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
22953#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
22954#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
22955#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
22956#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22957#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22958#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L
22959#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L
22960#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
22961//SQ_PERFCOUNTER3_SELECT
22962#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
22963#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
22964#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22965#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
22966#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
22967#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
22968#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
22969#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22970#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22971#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L
22972#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L
22973#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
22974//SQ_PERFCOUNTER4_SELECT
22975#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
22976#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
22977#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22978#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
22979#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
22980#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
22981#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL
22982#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22983#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22984#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L
22985#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L
22986#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L
22987//SQ_PERFCOUNTER5_SELECT
22988#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
22989#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
22990#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
22991#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
22992#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
22993#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
22994#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL
22995#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
22996#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
22997#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L
22998#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L
22999#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L
23000//SQ_PERFCOUNTER6_SELECT
23001#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
23002#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
23003#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23004#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
23005#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
23006#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
23007#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL
23008#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23009#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23010#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L
23011#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L
23012#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L
23013//SQ_PERFCOUNTER7_SELECT
23014#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
23015#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
23016#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23017#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
23018#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
23019#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
23020#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL
23021#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23022#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23023#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L
23024#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L
23025#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L
23026//SQ_PERFCOUNTER8_SELECT
23027#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
23028#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
23029#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23030#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
23031#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
23032#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
23033#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL
23034#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23035#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23036#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L
23037#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L
23038#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L
23039//SQ_PERFCOUNTER9_SELECT
23040#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
23041#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
23042#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23043#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
23044#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
23045#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
23046#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL
23047#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23048#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23049#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L
23050#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L
23051#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L
23052//SQ_PERFCOUNTER10_SELECT
23053#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
23054#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
23055#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23056#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
23057#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
23058#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
23059#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL
23060#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23061#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23062#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L
23063#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L
23064#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L
23065//SQ_PERFCOUNTER11_SELECT
23066#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
23067#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
23068#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23069#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
23070#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
23071#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
23072#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL
23073#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23074#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23075#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L
23076#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L
23077#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L
23078//SQ_PERFCOUNTER12_SELECT
23079#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
23080#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
23081#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23082#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
23083#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
23084#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
23085#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL
23086#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23087#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23088#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L
23089#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L
23090#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L
23091//SQ_PERFCOUNTER13_SELECT
23092#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
23093#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
23094#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23095#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
23096#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
23097#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
23098#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL
23099#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23100#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23101#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L
23102#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L
23103#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L
23104//SQ_PERFCOUNTER14_SELECT
23105#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
23106#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
23107#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23108#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
23109#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
23110#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
23111#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL
23112#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23113#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23114#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L
23115#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L
23116#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L
23117//SQ_PERFCOUNTER15_SELECT
23118#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
23119#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
23120#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
23121#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
23122#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
23123#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
23124#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL
23125#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L
23126#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L
23127#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L
23128#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L
23129#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L
23130//SQ_PERFCOUNTER_CTRL
23131#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
23132#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
23133#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
23134#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
23135#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
23136#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
23137#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
23138#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
23139#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
23140#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L
23141#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L
23142#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L
23143#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L
23144#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L
23145#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L
23146#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L
23147#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L
23148#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L
23149//SQ_PERFCOUNTER_MASK
23150#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
23151#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
23152#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL
23153#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L
23154//SQ_PERFCOUNTER_CTRL2
23155#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
23156#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L
23157//SX_PERFCOUNTER0_SELECT
23158#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23159#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23160#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23161#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23162#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23163#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23164#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23165#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23166#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23167#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23168//SX_PERFCOUNTER1_SELECT
23169#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23170#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23171#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23172#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23173#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23174#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23175#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23176#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23177#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23178#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23179//SX_PERFCOUNTER2_SELECT
23180#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23181#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23182#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23183#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23184#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23185#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23186//SX_PERFCOUNTER3_SELECT
23187#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23188#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23189#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23190#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23191#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23192#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23193//SX_PERFCOUNTER0_SELECT1
23194#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23195#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23196#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23197#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23198#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23199#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23200#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23201#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23202//SX_PERFCOUNTER1_SELECT1
23203#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
23204#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23205#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
23206#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
23207#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
23208#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23209#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
23210#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
23211//GDS_PERFCOUNTER0_SELECT
23212#define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23213#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23214#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23215#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23216#define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23217#define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23218#define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23219#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23220#define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23221#define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23222//GDS_PERFCOUNTER1_SELECT
23223#define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23224#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23225#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23226#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23227#define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23228#define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23229#define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23230#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23231#define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23232#define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23233//GDS_PERFCOUNTER2_SELECT
23234#define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23235#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23236#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23237#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
23238#define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23239#define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23240#define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
23241#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23242#define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
23243#define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23244//GDS_PERFCOUNTER3_SELECT
23245#define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23246#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
23247#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23248#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
23249#define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23250#define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23251#define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
23252#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23253#define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
23254#define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23255//GDS_PERFCOUNTER0_SELECT1
23256#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23257#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23258#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23259#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23260#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23261#define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23262#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23263#define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23264//TA_PERFCOUNTER0_SELECT
23265#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23266#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23267#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23268#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23269#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23270#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
23271#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
23272#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23273#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23274#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23275//TA_PERFCOUNTER0_SELECT1
23276#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23277#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23278#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23279#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23280#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
23281#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
23282#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23283#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23284//TA_PERFCOUNTER1_SELECT
23285#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23286#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23287#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23288#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
23289#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23290#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23291//TD_PERFCOUNTER0_SELECT
23292#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23293#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23294#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23295#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23296#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23297#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL
23298#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L
23299#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23300#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23301#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23302//TD_PERFCOUNTER0_SELECT1
23303#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23304#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23305#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23306#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23307#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL
23308#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L
23309#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23310#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23311//TD_PERFCOUNTER1_SELECT
23312#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23313#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23314#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23315#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL
23316#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23317#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23318//TCP_PERFCOUNTER0_SELECT
23319#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23320#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23321#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23322#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23323#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23324#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23325#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23326#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23327#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23328#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23329//TCP_PERFCOUNTER0_SELECT1
23330#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23331#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23332#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23333#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23334#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23335#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23336#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23337#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23338//TCP_PERFCOUNTER1_SELECT
23339#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23340#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23341#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23342#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23343#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23344#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23345#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23346#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23347#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23348#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23349//TCP_PERFCOUNTER1_SELECT1
23350#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
23351#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23352#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
23353#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
23354#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
23355#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23356#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
23357#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
23358//TCP_PERFCOUNTER2_SELECT
23359#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23360#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23361#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23362#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23363#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23364#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23365//TCP_PERFCOUNTER3_SELECT
23366#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23367#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23368#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23369#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23370#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23371#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23372//TCC_PERFCOUNTER0_SELECT
23373#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23374#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23375#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23376#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23377#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23378#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23379#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23380#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23381#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23382#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23383//TCC_PERFCOUNTER0_SELECT1
23384#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23385#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23386#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
23387#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
23388#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23389#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23390#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
23391#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
23392//TCC_PERFCOUNTER1_SELECT
23393#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23394#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23395#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23396#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23397#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23398#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23399#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23400#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23401#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23402#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23403//TCC_PERFCOUNTER1_SELECT1
23404#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
23405#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23406#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
23407#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
23408#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
23409#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23410#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
23411#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
23412//TCC_PERFCOUNTER2_SELECT
23413#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23414#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23415#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23416#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23417#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23418#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23419//TCC_PERFCOUNTER3_SELECT
23420#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23421#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23422#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23423#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23424#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23425#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23426//TCA_PERFCOUNTER0_SELECT
23427#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23428#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23429#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23430#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23431#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23432#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23433#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23434#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23435#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23436#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23437//TCA_PERFCOUNTER0_SELECT1
23438#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23439#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23440#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
23441#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
23442#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23443#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23444#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L
23445#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L
23446//TCA_PERFCOUNTER1_SELECT
23447#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23448#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23449#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23450#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23451#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23452#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23453#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23454#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23455#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23456#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23457//TCA_PERFCOUNTER1_SELECT1
23458#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
23459#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23460#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
23461#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
23462#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
23463#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23464#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L
23465#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L
23466//TCA_PERFCOUNTER2_SELECT
23467#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23468#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23469#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23470#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23471#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23472#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23473//TCA_PERFCOUNTER3_SELECT
23474#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23475#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23476#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23477#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23478#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23479#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23480//CB_PERFCOUNTER_FILTER
23481#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
23482#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
23483#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
23484#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
23485#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
23486#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
23487#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
23488#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
23489#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
23490#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
23491#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
23492#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
23493#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L
23494#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL
23495#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L
23496#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L
23497#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L
23498#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L
23499#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L
23500#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L
23501#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L
23502#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L
23503#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L
23504#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L
23505//CB_PERFCOUNTER0_SELECT
23506#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23507#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23508#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23509#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23510#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23511#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
23512#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
23513#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23514#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23515#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23516//CB_PERFCOUNTER0_SELECT1
23517#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23518#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23519#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23520#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23521#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
23522#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
23523#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23524#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23525//CB_PERFCOUNTER1_SELECT
23526#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23527#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23528#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
23529#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23530//CB_PERFCOUNTER2_SELECT
23531#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23532#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23533#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
23534#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23535//CB_PERFCOUNTER3_SELECT
23536#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23537#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23538#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
23539#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23540//DB_PERFCOUNTER0_SELECT
23541#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23542#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23543#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23544#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23545#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23546#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL
23547#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L
23548#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23549#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23550#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23551//DB_PERFCOUNTER0_SELECT1
23552#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23553#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23554#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23555#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23556#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL
23557#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23558#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23559#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23560//DB_PERFCOUNTER1_SELECT
23561#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23562#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
23563#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
23564#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
23565#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23566#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL
23567#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L
23568#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L
23569#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L
23570#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23571//DB_PERFCOUNTER1_SELECT1
23572#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
23573#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
23574#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
23575#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
23576#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL
23577#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L
23578#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L
23579#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L
23580//DB_PERFCOUNTER2_SELECT
23581#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23582#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23583#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23584#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
23585#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23586#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL
23587#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L
23588#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23589#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
23590#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23591//DB_PERFCOUNTER3_SELECT
23592#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23593#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
23594#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
23595#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
23596#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23597#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL
23598#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L
23599#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L
23600#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L
23601#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23602//RLC_SPM_PERFMON_CNTL
23603#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
23604#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
23605#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
23606#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
23607#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL
23608#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L
23609#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L
23610#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L
23611//RLC_SPM_PERFMON_RING_BASE_LO
23612#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
23613#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL
23614//RLC_SPM_PERFMON_RING_BASE_HI
23615#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
23616#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
23617#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL
23618#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L
23619//RLC_SPM_PERFMON_RING_SIZE
23620#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
23621#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL
23622//RLC_SPM_PERFMON_SEGMENT_SIZE
23623#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
23624#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
23625#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
23626#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
23627#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
23628#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
23629#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
23630#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL
23631#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L
23632#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L
23633#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L
23634#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L
23635#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L
23636#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L
23637//RLC_SPM_SE_MUXSEL_ADDR
23638#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
23639#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
23640//RLC_SPM_SE_MUXSEL_DATA
23641#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
23642#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
23643//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
23644#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23645#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23646#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23647#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23648//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
23649#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23650#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23651#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23652#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23653//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
23654#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23655#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23656#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23657#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23658//RLC_SPM_CB_PERFMON_SAMPLE_DELAY
23659#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23660#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23661#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23662#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23663//RLC_SPM_DB_PERFMON_SAMPLE_DELAY
23664#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23665#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23666#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23667#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23668//RLC_SPM_PA_PERFMON_SAMPLE_DELAY
23669#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23670#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23671#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23672#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23673//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
23674#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23675#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23676#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23677#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23678//RLC_SPM_IA_PERFMON_SAMPLE_DELAY
23679#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23680#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23681#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23682#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23683//RLC_SPM_SC_PERFMON_SAMPLE_DELAY
23684#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23685#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23686#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23687#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23688//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
23689#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23690#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23691#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23692#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23693//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
23694#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23695#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23696#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23697#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23698//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
23699#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23700#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23701#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23702#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23703//RLC_SPM_TA_PERFMON_SAMPLE_DELAY
23704#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23705#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23706#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23707#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23708//RLC_SPM_TD_PERFMON_SAMPLE_DELAY
23709#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23710#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23711#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23712#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23713//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
23714#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23715#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23716#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23717#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23718//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
23719#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23720#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23721#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23722#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23723//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
23724#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23725#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23726#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23727#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23728//RLC_SPM_SX_PERFMON_SAMPLE_DELAY
23729#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23730#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23731#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23732#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23733//RLC_SPM_GLOBAL_MUXSEL_ADDR
23734#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
23735#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL
23736//RLC_SPM_GLOBAL_MUXSEL_DATA
23737#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
23738#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL
23739//RLC_SPM_RING_RDPTR
23740#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
23741#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL
23742//RLC_SPM_SEGMENT_THRESHOLD
23743#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
23744#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL
23745//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
23746#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
23747#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
23748#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL
23749#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L
23750//RLC_SPM_PERFMON_SAMPLE_DELAY_MAX
23751#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT 0x0
23752#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT 0x8
23753#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK 0x000000FFL
23754#define RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK 0xFFFFFF00L
23755//RLC_PERFMON_CLK_CNTL_UCODE
23756#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0
23757#define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L
23758//RLC_PERFMON_CLK_CNTL
23759#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
23760#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L
23761//RLC_PERFMON_CNTL
23762#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
23763#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
23764#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L
23765#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
23766//RLC_PERFCOUNTER0_SELECT
23767#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
23768#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
23769//RLC_PERFCOUNTER1_SELECT
23770#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
23771#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL
23772//RLC_GPU_IOV_PERF_CNT_CNTL
23773#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0
23774#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1
23775#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2
23776#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3
23777#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L
23778#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L
23779#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L
23780#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L
23781//RLC_GPU_IOV_PERF_CNT_WR_ADDR
23782#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0
23783#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4
23784#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6
23785#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL
23786#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L
23787#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L
23788//RLC_GPU_IOV_PERF_CNT_WR_DATA
23789#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0
23790#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL
23791//RLC_GPU_IOV_PERF_CNT_RD_ADDR
23792#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0
23793#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4
23794#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6
23795#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL
23796#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L
23797#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L
23798//RLC_GPU_IOV_PERF_CNT_RD_DATA
23799#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0
23800#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL
23801//RMI_PERFCOUNTER0_SELECT
23802#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
23803#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
23804#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
23805#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
23806#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
23807#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL
23808#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L
23809#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L
23810#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L
23811#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L
23812//RMI_PERFCOUNTER0_SELECT1
23813#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
23814#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
23815#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
23816#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
23817#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL
23818#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L
23819#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L
23820#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L
23821//RMI_PERFCOUNTER1_SELECT
23822#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
23823#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
23824#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL
23825#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L
23826//RMI_PERFCOUNTER2_SELECT
23827#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
23828#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
23829#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
23830#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
23831#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
23832#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL
23833#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L
23834#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L
23835#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L
23836#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L
23837//RMI_PERFCOUNTER2_SELECT1
23838#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
23839#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
23840#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18
23841#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c
23842#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL
23843#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L
23844#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L
23845#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L
23846//RMI_PERFCOUNTER3_SELECT
23847#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
23848#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23849#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL
23850#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L
23851//RMI_PERF_COUNTER_CNTL
23852#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0
23853#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2
23854#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4
23855#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6
23856#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8
23857#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa
23858#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe
23859#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13
23860#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19
23861#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a
23862#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L
23863#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL
23864#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L
23865#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L
23866#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L
23867#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L
23868#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L
23869#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L
23870#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L
23871#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L
23872
23873
23874// addressBlock: gc_utcl2_atcl2pfcntldec
23875//ATC_L2_PERFCOUNTER0_CFG
23876#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
23877#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
23878#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
23879#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
23880#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
23881#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
23882#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
23883#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
23884#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
23885#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
23886//ATC_L2_PERFCOUNTER1_CFG
23887#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
23888#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
23889#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
23890#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
23891#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
23892#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
23893#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
23894#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
23895#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
23896#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
23897//ATC_L2_PERFCOUNTER_RSLT_CNTL
23898#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
23899#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
23900#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
23901#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
23902#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
23903#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
23904#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
23905#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
23906#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
23907#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
23908#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
23909#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
23910
23911
23912// addressBlock: gc_utcl2_vml2pldec
23913//MC_VM_L2_PERFCOUNTER0_CFG
23914#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
23915#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
23916#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
23917#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
23918#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
23919#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
23920#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
23921#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
23922#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
23923#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
23924//MC_VM_L2_PERFCOUNTER1_CFG
23925#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
23926#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
23927#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
23928#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
23929#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
23930#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
23931#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
23932#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
23933#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
23934#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
23935//MC_VM_L2_PERFCOUNTER2_CFG
23936#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
23937#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
23938#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
23939#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
23940#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
23941#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
23942#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
23943#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
23944#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
23945#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
23946//MC_VM_L2_PERFCOUNTER3_CFG
23947#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
23948#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
23949#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
23950#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
23951#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
23952#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL
23953#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L
23954#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L
23955#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L
23956#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L
23957//MC_VM_L2_PERFCOUNTER4_CFG
23958#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0
23959#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8
23960#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18
23961#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c
23962#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d
23963#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL
23964#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L
23965#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L
23966#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L
23967#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L
23968//MC_VM_L2_PERFCOUNTER5_CFG
23969#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0
23970#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8
23971#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18
23972#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c
23973#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d
23974#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL
23975#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L
23976#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L
23977#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L
23978#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L
23979//MC_VM_L2_PERFCOUNTER6_CFG
23980#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0
23981#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8
23982#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18
23983#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c
23984#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d
23985#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL
23986#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L
23987#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L
23988#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L
23989#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L
23990//MC_VM_L2_PERFCOUNTER7_CFG
23991#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0
23992#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8
23993#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18
23994#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c
23995#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d
23996#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL
23997#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L
23998#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L
23999#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L
24000#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L
24001//MC_VM_L2_PERFCOUNTER_RSLT_CNTL
24002#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
24003#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
24004#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
24005#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
24006#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
24007#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
24008#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
24009#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
24010#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
24011#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
24012#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
24013#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
24014
24015
24016// addressBlock: gc_rlcpdec
24017//RLC_CNTL
24018#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
24019#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
24020#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
24021#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
24022#define RLC_CNTL__RESERVED__SHIFT 0x4
24023#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L
24024#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L
24025#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L
24026#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L
24027#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L
24028//RLC_STAT
24029#define RLC_STAT__RLC_BUSY__SHIFT 0x0
24030#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1
24031#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2
24032#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3
24033#define RLC_STAT__MC_BUSY__SHIFT 0x4
24034#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5
24035#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6
24036#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7
24037#define RLC_STAT__RESERVED__SHIFT 0x8
24038#define RLC_STAT__RLC_BUSY_MASK 0x00000001L
24039#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L
24040#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L
24041#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L
24042#define RLC_STAT__MC_BUSY_MASK 0x00000010L
24043#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L
24044#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L
24045#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L
24046#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L
24047//RLC_SAFE_MODE
24048#define RLC_SAFE_MODE__CMD__SHIFT 0x0
24049#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
24050#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
24051#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
24052#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
24053#define RLC_SAFE_MODE__CMD_MASK 0x00000001L
24054#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL
24055#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L
24056#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L
24057#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
24058//RLC_MEM_SLP_CNTL
24059#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
24060#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
24061#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
24062#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
24063#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
24064#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
24065#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
24066#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L
24067#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L
24068#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL
24069#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L
24070#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L
24071#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L
24072#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L
24073//SMU_RLC_RESPONSE
24074#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
24075#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
24076//RLC_RLCV_SAFE_MODE
24077#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
24078#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
24079#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
24080#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
24081#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
24082#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L
24083#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL
24084#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L
24085#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L
24086#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
24087//RLC_SMU_SAFE_MODE
24088#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
24089#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
24090#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
24091#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
24092#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
24093#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L
24094#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL
24095#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L
24096#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L
24097#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L
24098//RLC_RLCV_COMMAND
24099#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
24100#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
24101#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL
24102#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L
24103//RLC_REFCLOCK_TIMESTAMP_LSB
24104#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0
24105#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL
24106//RLC_REFCLOCK_TIMESTAMP_MSB
24107#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0
24108#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL
24109//RLC_GPM_TIMER_INT_0
24110#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0
24111#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
24112//RLC_GPM_TIMER_INT_1
24113#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0
24114#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
24115//RLC_GPM_TIMER_INT_2
24116#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0
24117#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL
24118//RLC_GPM_TIMER_CTRL
24119#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
24120#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
24121#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2
24122#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3
24123#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4
24124#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
24125#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
24126#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L
24127#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L
24128#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L
24129//RLC_LB_CNTR_MAX
24130#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
24131#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL
24132//RLC_GPM_TIMER_STAT
24133#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
24134#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
24135#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2
24136#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3
24137#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
24138#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
24139#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa
24140#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb
24141#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0xc
24142#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
24143#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
24144#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L
24145#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L
24146#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
24147#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
24148#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L
24149#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L
24150#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFF000L
24151//RLC_GPM_TIMER_INT_3
24152#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0
24153#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL
24154//RLC_SERDES_WR_NONCU_MASTER_MASK_1
24155#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0
24156#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10
24157#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11
24158#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12
24159#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13
24160#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14
24161#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15
24162#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16
24163#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17
24164#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18
24165#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19
24166#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL
24167#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L
24168#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L
24169#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L
24170#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L
24171#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L
24172#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L
24173#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L
24174#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L
24175#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L
24176#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L
24177//RLC_SERDES_NONCU_MASTER_BUSY_1
24178#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0
24179#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10
24180#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11
24181#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12
24182#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13
24183#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14
24184#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15
24185#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16
24186#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17
24187#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18
24188#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19
24189#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL
24190#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L
24191#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L
24192#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L
24193#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L
24194#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L
24195#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L
24196#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L
24197#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L
24198#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L
24199#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L
24200//RLC_INT_STAT
24201#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0
24202#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8
24203#define RLC_INT_STAT__RESERVED__SHIFT 0x9
24204#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL
24205#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L
24206#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L
24207//RLC_LB_CNTL
24208#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
24209#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
24210#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
24211#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
24212#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
24213#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
24214#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L
24215#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L
24216#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L
24217#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L
24218#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L
24219#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L
24220//RLC_MGCG_CTRL
24221#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
24222#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
24223#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
24224#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
24225#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
24226#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf
24227#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10
24228#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11
24229#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L
24230#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L
24231#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L
24232#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L
24233#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L
24234#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L
24235#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L
24236#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
24237//RLC_LB_CNTR_INIT
24238#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
24239#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL
24240//RLC_LOAD_BALANCE_CNTR
24241#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
24242#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL
24243//RLC_JUMP_TABLE_RESTORE
24244#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
24245#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL
24246//RLC_PG_DELAY_2
24247#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
24248#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
24249#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
24250#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL
24251#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L
24252#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L
24253//RLC_GPU_CLOCK_COUNT_LSB
24254#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
24255#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
24256//RLC_GPU_CLOCK_COUNT_MSB
24257#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
24258#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
24259//RLC_CAPTURE_GPU_CLOCK_COUNT
24260#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
24261#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
24262#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L
24263#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL
24264//RLC_UCODE_CNTL
24265#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
24266#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL
24267//RLC_GPM_THREAD_RESET
24268#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
24269#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
24270#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
24271#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
24272#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
24273#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L
24274#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L
24275#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L
24276#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L
24277#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L
24278//RLC_GPM_CP_DMA_COMPLETE_T0
24279#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0
24280#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1
24281#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L
24282#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL
24283//RLC_GPM_CP_DMA_COMPLETE_T1
24284#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0
24285#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1
24286#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L
24287#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL
24288//RLC_FIREWALL_VIOLATION
24289#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0
24290#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL
24291//RLC_CLK_COUNT_GFXCLK_LSB
24292#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0
24293#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
24294//RLC_CLK_COUNT_GFXCLK_MSB
24295#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0
24296#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
24297//RLC_CLK_COUNT_REFCLK_LSB
24298#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0
24299#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL
24300//RLC_CLK_COUNT_REFCLK_MSB
24301#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0
24302#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL
24303//RLC_CLK_COUNT_CTRL
24304#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0
24305#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1
24306#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2
24307#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3
24308#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4
24309#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5
24310#define RLC_CLK_COUNT_CTRL__RESERVED__SHIFT 0x6
24311#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L
24312#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L
24313#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L
24314#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L
24315#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L
24316#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L
24317#define RLC_CLK_COUNT_CTRL__RESERVED_MASK 0xFFFFFFC0L
24318//RLC_CLK_COUNT_STAT
24319#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0
24320#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1
24321#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2
24322#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3
24323#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4
24324#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5
24325#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L
24326#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L
24327#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L
24328#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L
24329#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L
24330#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L
24331//RLC_GPM_STAT
24332#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
24333#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
24334#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
24335#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
24336#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
24337#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
24338#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
24339#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
24340#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
24341#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
24342#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
24343#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
24344#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
24345#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
24346#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
24347#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
24348#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
24349#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
24350#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12
24351#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13
24352#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14
24353#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15
24354#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16
24355#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17
24356#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
24357#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L
24358#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L
24359#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L
24360#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L
24361#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L
24362#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L
24363#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L
24364#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L
24365#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L
24366#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L
24367#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L
24368#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L
24369#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L
24370#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L
24371#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L
24372#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L
24373#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L
24374#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L
24375#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L
24376#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L
24377#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L
24378#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L
24379#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L
24380#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L
24381#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L
24382//RLC_GPU_CLOCK_32_RES_SEL
24383#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
24384#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
24385#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL
24386#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L
24387//RLC_GPU_CLOCK_32
24388#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
24389#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL
24390//RLC_PG_CNTL
24391#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
24392#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
24393#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
24394#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
24395#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
24396#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
24397#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
24398#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
24399#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
24400#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
24401#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
24402#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
24403#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14
24404#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15
24405#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16
24406#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L
24407#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L
24408#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L
24409#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L
24410#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L
24411#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L
24412#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L
24413#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L
24414#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L
24415#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L
24416#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L
24417#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L
24418#define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L
24419#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L
24420#define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L
24421//RLC_GPM_THREAD_PRIORITY
24422#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
24423#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
24424#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
24425#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
24426#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL
24427#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L
24428#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L
24429#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L
24430//RLC_GPM_THREAD_ENABLE
24431#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
24432#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
24433#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
24434#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
24435#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
24436#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L
24437#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L
24438#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L
24439#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L
24440#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L
24441//RLC_CGTT_MGCG_OVERRIDE
24442#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0
24443#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1
24444#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2
24445#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3
24446#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4
24447#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5
24448#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6
24449#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7
24450#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8
24451#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT 0x9
24452#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10
24453#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11
24454#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L
24455#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L
24456#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L
24457#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L
24458#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L
24459#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L
24460#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L
24461#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L
24462#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L
24463#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK 0x0000FE00L
24464#define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L
24465#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L
24466//RLC_CGCG_CGLS_CTRL
24467#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
24468#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
24469#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
24470#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
24471#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
24472#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
24473#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
24474#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
24475#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L
24476#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L
24477#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
24478#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
24479#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L
24480#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L
24481#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L
24482#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L
24483//RLC_CGCG_RAMP_CTRL
24484#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
24485#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
24486#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
24487#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
24488#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
24489#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
24490#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL
24491#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
24492#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L
24493#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L
24494#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L
24495#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L
24496//RLC_DYN_PG_STATUS
24497#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
24498#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
24499//RLC_DYN_PG_REQUEST
24500#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
24501#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL
24502//RLC_PG_DELAY
24503#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
24504#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
24505#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
24506#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
24507#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL
24508#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L
24509#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L
24510#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L
24511//RLC_CU_STATUS
24512#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
24513#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL
24514//RLC_LB_INIT_CU_MASK
24515#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
24516#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL
24517//RLC_LB_ALWAYS_ACTIVE_CU_MASK
24518#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
24519#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL
24520//RLC_LB_PARAMS
24521#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
24522#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
24523#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
24524#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
24525#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L
24526#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL
24527#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L
24528#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L
24529//RLC_THREAD1_DELAY
24530#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
24531#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
24532#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
24533#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
24534#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL
24535#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L
24536#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L
24537#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L
24538//RLC_PG_ALWAYS_ON_CU_MASK
24539#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
24540#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL
24541//RLC_MAX_PG_CU
24542#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
24543#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
24544#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL
24545#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L
24546//RLC_AUTO_PG_CTRL
24547#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
24548#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
24549#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
24550#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
24551#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
24552#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L
24553#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L
24554#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L
24555#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L
24556#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L
24557//RLC_SMU_GRBM_REG_SAVE_CTRL
24558#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
24559#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
24560#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L
24561#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL
24562//RLC_SERDES_RD_PENDING
24563#define RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT 0x0
24564#define RLC_SERDES_RD_PENDING__RD_PENDING_MASK 0x00000001L
24565//RLC_SERDES_RD_MASTER_INDEX
24566#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
24567#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
24568#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
24569#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
24570#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc
24571#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd
24572#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11
24573#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13
24574#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL
24575#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L
24576#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L
24577#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L
24578#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L
24579#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L
24580#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L
24581#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L
24582//RLC_SERDES_RD_DATA_0
24583#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
24584#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL
24585//RLC_SERDES_RD_DATA_1
24586#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
24587#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL
24588//RLC_SERDES_RD_DATA_2
24589#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
24590#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL
24591//RLC_SERDES_WR_CU_MASTER_MASK
24592#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
24593#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL
24594//RLC_SERDES_WR_NONCU_MASTER_MASK
24595#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
24596#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
24597#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
24598#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
24599#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
24600#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
24601#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
24602#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
24603#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
24604#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18
24605#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19
24606#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a
24607#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL
24608#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L
24609#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L
24610#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L
24611#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L
24612#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L
24613#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L
24614#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L
24615#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L
24616#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L
24617#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L
24618#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L
24619//RLC_SERDES_WR_CTRL
24620#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
24621#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
24622#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
24623#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
24624#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
24625#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
24626#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
24627#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
24628#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
24629#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
24630#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
24631#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
24632#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
24633#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL
24634#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L
24635#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L
24636#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L
24637#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L
24638#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L
24639#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L
24640#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L
24641#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L
24642#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L
24643#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L
24644#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L
24645#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L
24646//RLC_SERDES_WR_DATA
24647#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
24648#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL
24649//RLC_SERDES_CU_MASTER_BUSY
24650#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
24651#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL
24652//RLC_SERDES_NONCU_MASTER_BUSY
24653#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
24654#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
24655#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
24656#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
24657#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
24658#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
24659#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
24660#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
24661#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
24662#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18
24663#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19
24664#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a
24665#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL
24666#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L
24667#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L
24668#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L
24669#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L
24670#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L
24671#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L
24672#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L
24673#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L
24674#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L
24675#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L
24676#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L
24677//RLC_GPM_GENERAL_0
24678#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
24679#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL
24680//RLC_GPM_GENERAL_1
24681#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
24682#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL
24683//RLC_GPM_GENERAL_2
24684#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
24685#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL
24686//RLC_GPM_GENERAL_3
24687#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
24688#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL
24689//RLC_GPM_GENERAL_4
24690#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
24691#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL
24692//RLC_GPM_GENERAL_5
24693#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
24694#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL
24695//RLC_GPM_GENERAL_6
24696#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
24697#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL
24698//RLC_GPM_GENERAL_7
24699#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
24700#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL
24701//RLC_GPM_SCRATCH_ADDR
24702#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
24703#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
24704#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
24705#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
24706//RLC_GPM_SCRATCH_DATA
24707#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
24708#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
24709//RLC_STATIC_PG_STATUS
24710#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
24711#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL
24712//RLC_SPM_MC_CNTL
24713#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0
24714#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4
24715#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5
24716#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6
24717#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7
24718#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8
24719#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa
24720#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL
24721#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L
24722#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L
24723#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L
24724#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L
24725#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L
24726#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L
24727//RLC_SPM_INT_CNTL
24728#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
24729#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
24730#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L
24731#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL
24732//RLC_SPM_INT_STATUS
24733#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
24734#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
24735#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L
24736#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL
24737//RLC_SMU_MESSAGE
24738#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
24739#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL
24740//RLC_GPM_LOG_SIZE
24741#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
24742#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL
24743//RLC_PG_DELAY_3
24744#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
24745#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8
24746#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL
24747#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L
24748//RLC_GPR_REG1
24749#define RLC_GPR_REG1__DATA__SHIFT 0x0
24750#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL
24751//RLC_GPR_REG2
24752#define RLC_GPR_REG2__DATA__SHIFT 0x0
24753#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL
24754//RLC_GPM_LOG_CONT
24755#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
24756#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL
24757//RLC_GPM_INT_DISABLE_TH0
24758#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
24759#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL
24760//RLC_GPM_INT_FORCE_TH0
24761#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
24762#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL
24763//RLC_GPM_INT_FORCE_TH1
24764#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
24765#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL
24766//RLC_SRM_CNTL
24767#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
24768#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
24769#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
24770#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L
24771#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L
24772#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL
24773//RLC_SRM_ARAM_ADDR
24774#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0
24775#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc
24776#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL
24777#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L
24778//RLC_SRM_ARAM_DATA
24779#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
24780#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL
24781//RLC_SRM_DRAM_ADDR
24782#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0
24783#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc
24784#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL
24785#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L
24786//RLC_SRM_DRAM_DATA
24787#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
24788#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL
24789//RLC_SRM_GPM_COMMAND
24790#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
24791#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
24792#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
24793#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
24794#define RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT 0x10
24795#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
24796#define RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT 0x1d
24797#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
24798#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L
24799#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L
24800#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL
24801#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0000FFE0L
24802#define RLC_SRM_GPM_COMMAND__RESERVED_16_MASK 0x00010000L
24803#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L
24804#define RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK 0x60000000L
24805#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L
24806//RLC_SRM_GPM_COMMAND_STATUS
24807#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
24808#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
24809#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
24810#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
24811#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
24812#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
24813//RLC_SRM_RLCV_COMMAND
24814#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
24815#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
24816#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
24817#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
24818#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
24819#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
24820#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L
24821#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL
24822#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L
24823#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L
24824#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L
24825#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L
24826//RLC_SRM_RLCV_COMMAND_STATUS
24827#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
24828#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
24829#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
24830#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L
24831#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L
24832#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL
24833//RLC_SRM_INDEX_CNTL_ADDR_0
24834#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
24835#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
24836#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL
24837#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L
24838//RLC_SRM_INDEX_CNTL_ADDR_1
24839#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
24840#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
24841#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL
24842#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L
24843//RLC_SRM_INDEX_CNTL_ADDR_2
24844#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
24845#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
24846#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL
24847#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L
24848//RLC_SRM_INDEX_CNTL_ADDR_3
24849#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
24850#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
24851#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL
24852#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L
24853//RLC_SRM_INDEX_CNTL_ADDR_4
24854#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
24855#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
24856#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL
24857#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L
24858//RLC_SRM_INDEX_CNTL_ADDR_5
24859#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
24860#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
24861#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL
24862#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L
24863//RLC_SRM_INDEX_CNTL_ADDR_6
24864#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
24865#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
24866#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL
24867#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L
24868//RLC_SRM_INDEX_CNTL_ADDR_7
24869#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
24870#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
24871#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL
24872#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L
24873//RLC_SRM_INDEX_CNTL_DATA_0
24874#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
24875#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL
24876//RLC_SRM_INDEX_CNTL_DATA_1
24877#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
24878#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL
24879//RLC_SRM_INDEX_CNTL_DATA_2
24880#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
24881#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL
24882//RLC_SRM_INDEX_CNTL_DATA_3
24883#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
24884#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL
24885//RLC_SRM_INDEX_CNTL_DATA_4
24886#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
24887#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL
24888//RLC_SRM_INDEX_CNTL_DATA_5
24889#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
24890#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL
24891//RLC_SRM_INDEX_CNTL_DATA_6
24892#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
24893#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL
24894//RLC_SRM_INDEX_CNTL_DATA_7
24895#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
24896#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL
24897//RLC_SRM_STAT
24898#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0
24899#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1
24900#define RLC_SRM_STAT__RESERVED__SHIFT 0x2
24901#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L
24902#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L
24903#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL
24904//RLC_SRM_GPM_ABORT
24905#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
24906#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
24907#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L
24908#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL
24909//RLC_CSIB_ADDR_LO
24910#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
24911#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL
24912//RLC_CSIB_ADDR_HI
24913#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
24914#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL
24915//RLC_CSIB_LENGTH
24916#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
24917#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL
24918//RLC_SMU_COMMAND
24919#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
24920#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL
24921//RLC_CP_SCHEDULERS
24922#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
24923#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
24924#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
24925#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
24926#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL
24927#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L
24928#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L
24929#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L
24930//RLC_SMU_ARGUMENT_1
24931#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0
24932#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL
24933//RLC_SMU_ARGUMENT_2
24934#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0
24935#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL
24936//RLC_GPM_GENERAL_8
24937#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0
24938#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL
24939//RLC_GPM_GENERAL_9
24940#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0
24941#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL
24942//RLC_GPM_GENERAL_10
24943#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0
24944#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL
24945//RLC_GPM_GENERAL_11
24946#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0
24947#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL
24948//RLC_GPM_GENERAL_12
24949#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0
24950#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL
24951//RLC_GPM_UTCL1_CNTL_0
24952#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0
24953#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18
24954#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19
24955#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a
24956#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b
24957#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c
24958#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
24959#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e
24960#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
24961#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L
24962#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L
24963#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L
24964#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L
24965#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L
24966#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
24967#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L
24968//RLC_GPM_UTCL1_CNTL_1
24969#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0
24970#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18
24971#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19
24972#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a
24973#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b
24974#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c
24975#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
24976#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e
24977#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
24978#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L
24979#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L
24980#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L
24981#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L
24982#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L
24983#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
24984#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L
24985//RLC_GPM_UTCL1_CNTL_2
24986#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0
24987#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18
24988#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19
24989#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a
24990#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b
24991#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c
24992#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
24993#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e
24994#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
24995#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L
24996#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L
24997#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L
24998#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L
24999#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L
25000#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
25001#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L
25002//RLC_SPM_UTCL1_CNTL
25003#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
25004#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
25005#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19
25006#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
25007#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
25008#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
25009#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
25010#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e
25011#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
25012#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
25013#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L
25014#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
25015#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
25016#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
25017#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
25018#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
25019//RLC_UTCL1_STATUS_2
25020#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0
25021#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1
25022#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2
25023#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3
25024#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4
25025#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5
25026#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6
25027#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7
25028#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8
25029#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9
25030#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa
25031#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L
25032#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L
25033#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L
25034#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L
25035#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L
25036#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L
25037#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L
25038#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L
25039#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L
25040#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L
25041#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L
25042//RLC_LB_THR_CONFIG_2
25043#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0
25044#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL
25045//RLC_LB_THR_CONFIG_3
25046#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0
25047#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL
25048//RLC_LB_THR_CONFIG_4
25049#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0
25050#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL
25051//RLC_SPM_UTCL1_ERROR_1
25052#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0
25053#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
25054#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
25055#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L
25056#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
25057#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
25058//RLC_SPM_UTCL1_ERROR_2
25059#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
25060#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
25061//RLC_GPM_UTCL1_TH0_ERROR_1
25062#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0
25063#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
25064#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
25065#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L
25066#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
25067#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
25068//RLC_LB_THR_CONFIG_1
25069#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0
25070#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL
25071//RLC_GPM_UTCL1_TH0_ERROR_2
25072#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
25073#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
25074//RLC_GPM_UTCL1_TH1_ERROR_1
25075#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0
25076#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
25077#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
25078#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L
25079#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
25080#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
25081//RLC_GPM_UTCL1_TH1_ERROR_2
25082#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
25083#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
25084//RLC_GPM_UTCL1_TH2_ERROR_1
25085#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0
25086#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
25087#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6
25088#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L
25089#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL
25090#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L
25091//RLC_GPM_UTCL1_TH2_ERROR_2
25092#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0
25093#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL
25094//RLC_CGCG_CGLS_CTRL_3D
25095#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0
25096#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1
25097#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
25098#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
25099#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b
25100#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c
25101#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d
25102#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f
25103#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L
25104#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L
25105#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL
25106#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L
25107#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L
25108#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L
25109#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L
25110#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L
25111//RLC_CGCG_RAMP_CTRL_3D
25112#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0
25113#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4
25114#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8
25115#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc
25116#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10
25117#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c
25118#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL
25119#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L
25120#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L
25121#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L
25122#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L
25123#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L
25124//RLC_SEMAPHORE_0
25125#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
25126#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5
25127#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
25128#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
25129//RLC_SEMAPHORE_1
25130#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
25131#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5
25132#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
25133#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
25134//RLC_CP_EOF_INT
25135#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0
25136#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1
25137#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L
25138#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL
25139//RLC_CP_EOF_INT_CNT
25140#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0
25141#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL
25142//RLC_SPARE_INT
25143#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0
25144#define RLC_SPARE_INT__RESERVED__SHIFT 0x1
25145#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L
25146#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
25147//RLC_PREWALKER_UTCL1_CNTL
25148#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
25149#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
25150#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19
25151#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
25152#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
25153#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
25154#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
25155#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e
25156#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
25157#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
25158#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L
25159#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
25160#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
25161#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
25162#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
25163#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L
25164//RLC_PREWALKER_UTCL1_TRIG
25165#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0
25166#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1
25167#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5
25168#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6
25169#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7
25170#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8
25171#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9
25172#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f
25173#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L
25174#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL
25175#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L
25176#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L
25177#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L
25178#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L
25179#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L
25180#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L
25181//RLC_PREWALKER_UTCL1_ADDR_LSB
25182#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0
25183#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL
25184//RLC_PREWALKER_UTCL1_ADDR_MSB
25185#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0
25186#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL
25187//RLC_PREWALKER_UTCL1_SIZE_LSB
25188#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0
25189#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL
25190//RLC_PREWALKER_UTCL1_SIZE_MSB
25191#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0
25192#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L
25193//RLC_DSM_TRIG
25194#define RLC_DSM_TRIG__START__SHIFT 0x0
25195#define RLC_DSM_TRIG__START_MASK 0x00000001L
25196//RLC_UTCL1_STATUS
25197#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
25198#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
25199#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
25200#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3
25201#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
25202#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe
25203#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
25204#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16
25205#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
25206#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e
25207#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
25208#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
25209#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
25210#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L
25211#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
25212#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L
25213#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
25214#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L
25215#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
25216#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L
25217//RLC_R2I_CNTL_0
25218#define RLC_R2I_CNTL_0__Data__SHIFT 0x0
25219#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL
25220//RLC_R2I_CNTL_1
25221#define RLC_R2I_CNTL_1__Data__SHIFT 0x0
25222#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL
25223//RLC_R2I_CNTL_2
25224#define RLC_R2I_CNTL_2__Data__SHIFT 0x0
25225#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL
25226//RLC_R2I_CNTL_3
25227#define RLC_R2I_CNTL_3__Data__SHIFT 0x0
25228#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL
25229//RLC_UTCL2_CNTL
25230#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0
25231#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1
25232#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L
25233#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL
25234//RLC_LBPW_CU_STAT
25235#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0
25236#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10
25237#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL
25238#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L
25239//RLC_DS_CNTL
25240#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0
25241#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1
25242#define RLC_DS_CNTL__RESRVED__SHIFT 0x2
25243#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10
25244#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11
25245#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12
25246#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L
25247#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L
25248#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL
25249#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L
25250#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L
25251#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L
25252//RLC_GPM_INT_STAT_TH0
25253#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0
25254#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL
25255//RLC_GPM_GENERAL_13
25256#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0
25257#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL
25258//RLC_GPM_GENERAL_14
25259#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0
25260#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL
25261//RLC_GPM_GENERAL_15
25262#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0
25263#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL
25264//RLC_SPARE_INT_1
25265#define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0
25266#define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1
25267#define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
25268#define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
25269//RLC_RLCV_SPARE_INT_1
25270#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0
25271#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1
25272#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L
25273#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL
25274//RLC_SEMAPHORE_2
25275#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
25276#define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5
25277#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
25278#define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
25279//RLC_SEMAPHORE_3
25280#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
25281#define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5
25282#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
25283#define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
25284//RLC_SMU_ARGUMENT_3
25285#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0
25286#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL
25287//RLC_SMU_ARGUMENT_4
25288#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0
25289#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL
25290//RLC_GPU_CLOCK_COUNT_LSB_1
25291#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0
25292#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
25293//RLC_GPU_CLOCK_COUNT_MSB_1
25294#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0
25295#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
25296//RLC_CAPTURE_GPU_CLOCK_COUNT_1
25297#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0
25298#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1
25299#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L
25300#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL
25301//RLC_GPU_CLOCK_COUNT_LSB_2
25302#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0
25303#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL
25304//RLC_GPU_CLOCK_COUNT_MSB_2
25305#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0
25306#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL
25307//RLC_CAPTURE_GPU_CLOCK_COUNT_2
25308#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0
25309#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1
25310#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L
25311#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL
25312//RLC_CPG_STAT_INVAL
25313#define RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT 0x0
25314#define RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK 0x00000001L
25315//RLC_RLCV_SPARE_INT
25316#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0
25317#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1
25318#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L
25319#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL
25320//RLC_SMU_CLK_REQ
25321#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0
25322#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L
25323
25324
25325// addressBlock: gc_pwrdec
25326//CGTS_SM_CTRL_REG
25327#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
25328#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
25329#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
25330#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
25331#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
25332#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
25333#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
25334#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
25335#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
25336#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
25337#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL
25338#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L
25339#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
25340#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
25341#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L
25342#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
25343#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
25344#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
25345#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
25346#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L
25347//CGTS_RD_CTRL_REG
25348#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
25349#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
25350#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL
25351#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L
25352//CGTS_RD_REG
25353#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
25354#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL
25355//CGTS_TCC_DISABLE
25356#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
25357#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
25358//CGTS_USER_TCC_DISABLE
25359#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
25360#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L
25361//CGTS_CU0_SP0_CTRL_REG
25362#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
25363#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25364#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25365#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25366#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25367#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
25368#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25369#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25370#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25371#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25372#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25373#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25374#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25375#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25376#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25377#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25378#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25379#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25380#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25381#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25382//CGTS_CU0_LDS_SQ_CTRL_REG
25383#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25384#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25385#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25386#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25387#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25388#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25389#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25390#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25391#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25392#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25393#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25394#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25395#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25396#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25397#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25398#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25399#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25400#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25401#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25402#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25403//CGTS_CU0_TA_SQC_CTRL_REG
25404#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25405#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25406#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25407#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25408#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25409#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
25410#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
25411#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
25412#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
25413#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25414#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25415#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25416#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25417#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25418#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25419#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
25420#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
25421#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
25422#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
25423#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25424//CGTS_CU0_SP1_CTRL_REG
25425#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
25426#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25427#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25428#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25429#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25430#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
25431#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25432#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25433#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25434#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25435#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25436#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25437#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25438#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25439#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25440#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25441#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25442#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25443#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25444#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25445//CGTS_CU0_TD_TCP_CTRL_REG
25446#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25447#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25448#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25449#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25450#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25451#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25452#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25453#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25454#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25455#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25456#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25457#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25458#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25459#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25460#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25461#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25462#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25463#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25464#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25465#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25466//CGTS_CU1_SP0_CTRL_REG
25467#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
25468#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25469#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25470#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25471#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25472#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
25473#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25474#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25475#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25476#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25477#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25478#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25479#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25480#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25481#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25482#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25483#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25484#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25485#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25486#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25487//CGTS_CU1_LDS_SQ_CTRL_REG
25488#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25489#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25490#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25491#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25492#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25493#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25494#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25495#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25496#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25497#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25498#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25499#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25500#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25501#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25502#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25503#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25504#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25505#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25506#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25507#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25508//CGTS_CU1_TA_SQC_CTRL_REG
25509#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25510#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25511#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25512#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25513#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25514#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25515#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25516#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25517#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25518#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25519//CGTS_CU1_SP1_CTRL_REG
25520#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
25521#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25522#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25523#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25524#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25525#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
25526#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25527#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25528#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25529#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25530#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25531#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25532#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25533#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25534#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25535#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25536#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25537#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25538#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25539#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25540//CGTS_CU1_TD_TCP_CTRL_REG
25541#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25542#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25543#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25544#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25545#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25546#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25547#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25548#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25549#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25550#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25551#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25552#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25553#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25554#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25555#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25556#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25557#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25558#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25559#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25560#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25561//CGTS_CU2_SP0_CTRL_REG
25562#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
25563#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25564#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25565#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25566#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25567#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
25568#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25569#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25570#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25571#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25572#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25573#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25574#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25575#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25576#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25577#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25578#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25579#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25580#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25581#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25582//CGTS_CU2_LDS_SQ_CTRL_REG
25583#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25584#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25585#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25586#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25587#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25588#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25589#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25590#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25591#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25592#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25593#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25594#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25595#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25596#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25597#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25598#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25599#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25600#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25601#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25602#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25603//CGTS_CU2_TA_SQC_CTRL_REG
25604#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25605#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25606#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25607#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25608#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25609#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25610#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25611#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25612#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25613#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25614//CGTS_CU2_SP1_CTRL_REG
25615#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
25616#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25617#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25618#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25619#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25620#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
25621#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25622#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25623#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25624#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25625#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25626#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25627#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25628#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25629#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25630#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25631#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25632#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25633#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25634#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25635//CGTS_CU2_TD_TCP_CTRL_REG
25636#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25637#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25638#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25639#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25640#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25641#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25642#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25643#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25644#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25645#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25646#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25647#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25648#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25649#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25650#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25651#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25652#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25653#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25654#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25655#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25656//CGTS_CU3_SP0_CTRL_REG
25657#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
25658#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25659#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25660#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25661#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25662#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
25663#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25664#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25665#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25666#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25667#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25668#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25669#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25670#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25671#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25672#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25673#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25674#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25675#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25676#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25677//CGTS_CU3_LDS_SQ_CTRL_REG
25678#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25679#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25680#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25681#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25682#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25683#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25684#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25685#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25686#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25687#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25688#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25689#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25690#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25691#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25692#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25693#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25694#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25695#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25696#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25697#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25698//CGTS_CU3_TA_SQC_CTRL_REG
25699#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25700#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25701#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25702#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25703#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25704#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
25705#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
25706#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
25707#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
25708#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25709#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25710#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25711#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25712#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25713#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25714#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
25715#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
25716#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
25717#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
25718#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25719//CGTS_CU3_SP1_CTRL_REG
25720#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
25721#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25722#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25723#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25724#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25725#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
25726#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25727#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25728#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25729#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25730#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25731#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25732#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25733#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25734#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25735#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25736#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25737#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25738#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25739#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25740//CGTS_CU3_TD_TCP_CTRL_REG
25741#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25742#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25743#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25744#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25745#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25746#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25747#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25748#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25749#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25750#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25751#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25752#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25753#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25754#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25755#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25756#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25757#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25758#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25759#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25760#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25761//CGTS_CU4_SP0_CTRL_REG
25762#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
25763#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25764#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25765#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25766#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25767#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
25768#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25769#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25770#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25771#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25772#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25773#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25774#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25775#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25776#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25777#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25778#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25779#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25780#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25781#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25782//CGTS_CU4_LDS_SQ_CTRL_REG
25783#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25784#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25785#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25786#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25787#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25788#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25789#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25790#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25791#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25792#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25793#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25794#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25795#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25796#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25797#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25798#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25799#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25800#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25801#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25802#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25803//CGTS_CU4_TA_SQC_CTRL_REG
25804#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25805#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25806#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25807#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25808#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25809#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25810#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25811#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25812#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25813#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25814//CGTS_CU4_SP1_CTRL_REG
25815#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
25816#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25817#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25818#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25819#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25820#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
25821#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25822#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25823#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25824#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25825#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25826#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25827#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25828#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25829#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25830#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25831#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25832#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25833#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25834#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25835//CGTS_CU4_TD_TCP_CTRL_REG
25836#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25837#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25838#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25839#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25840#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25841#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25842#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25843#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25844#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25845#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25846#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25847#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25848#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25849#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25850#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25851#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25852#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25853#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25854#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25855#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25856//CGTS_CU5_SP0_CTRL_REG
25857#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
25858#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25859#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25860#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25861#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25862#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
25863#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25864#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25865#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25866#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25867#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25868#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25869#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25870#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25871#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25872#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25873#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25874#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25875#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25876#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25877//CGTS_CU5_LDS_SQ_CTRL_REG
25878#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25879#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25880#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25881#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25882#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25883#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25884#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25885#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25886#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25887#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25888#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25889#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25890#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25891#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25892#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25893#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25894#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25895#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25896#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25897#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25898//CGTS_CU5_TA_SQC_CTRL_REG
25899#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25900#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25901#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25902#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25903#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25904#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
25905#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
25906#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
25907#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
25908#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25909//CGTS_CU5_SP1_CTRL_REG
25910#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
25911#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
25912#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
25913#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
25914#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
25915#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
25916#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
25917#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
25918#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
25919#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25920#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL
25921#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
25922#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
25923#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
25924#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25925#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L
25926#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
25927#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
25928#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
25929#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25930//CGTS_CU5_TD_TCP_CTRL_REG
25931#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
25932#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
25933#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
25934#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
25935#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
25936#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
25937#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
25938#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
25939#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
25940#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25941#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
25942#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
25943#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
25944#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
25945#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25946#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
25947#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
25948#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
25949#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
25950#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25951//CGTS_CU6_SP0_CTRL_REG
25952#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
25953#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
25954#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
25955#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
25956#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
25957#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
25958#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
25959#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
25960#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
25961#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25962#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL
25963#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
25964#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
25965#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
25966#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25967#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L
25968#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
25969#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
25970#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
25971#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25972//CGTS_CU6_LDS_SQ_CTRL_REG
25973#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
25974#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
25975#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
25976#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
25977#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
25978#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
25979#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
25980#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
25981#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
25982#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
25983#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
25984#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
25985#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
25986#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
25987#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
25988#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
25989#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
25990#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
25991#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
25992#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
25993//CGTS_CU6_TA_SQC_CTRL_REG
25994#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0
25995#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
25996#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
25997#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
25998#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
25999#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
26000#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
26001#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
26002#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
26003#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26004#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26005#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26006#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26007#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26008#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26009#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
26010#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
26011#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
26012#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
26013#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26014//CGTS_CU6_SP1_CTRL_REG
26015#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
26016#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26017#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26018#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26019#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26020#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
26021#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26022#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26023#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26024#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26025#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26026#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26027#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26028#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26029#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26030#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26031#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26032#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26033#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26034#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26035//CGTS_CU6_TD_TCP_CTRL_REG
26036#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26037#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26038#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26039#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26040#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26041#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26042#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26043#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26044#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26045#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26046#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26047#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26048#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26049#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26050#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26051#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26052#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26053#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26054#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26055#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26056//CGTS_CU7_SP0_CTRL_REG
26057#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
26058#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26059#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26060#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26061#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26062#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
26063#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26064#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26065#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26066#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26067#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26068#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26069#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26070#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26071#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26072#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26073#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26074#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26075#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26076#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26077//CGTS_CU7_LDS_SQ_CTRL_REG
26078#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26079#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26080#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26081#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26082#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26083#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26084#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26085#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26086#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26087#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26088#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26089#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26090#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26091#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26092#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26093#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26094#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26095#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26096#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26097#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26098//CGTS_CU7_TA_SQC_CTRL_REG
26099#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26100#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26101#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26102#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26103#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26104#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26105#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26106#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26107#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26108#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26109//CGTS_CU7_SP1_CTRL_REG
26110#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
26111#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26112#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26113#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26114#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26115#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
26116#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26117#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26118#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26119#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26120#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26121#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26122#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26123#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26124#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26125#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26126#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26127#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26128#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26129#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26130//CGTS_CU7_TD_TCP_CTRL_REG
26131#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26132#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26133#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26134#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26135#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26136#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26137#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26138#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26139#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26140#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26141#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26142#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26143#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26144#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26145#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26146#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26147#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26148#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26149#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26150#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26151//CGTS_CU8_SP0_CTRL_REG
26152#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
26153#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26154#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26155#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26156#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26157#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
26158#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26159#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26160#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26161#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26162#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26163#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26164#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26165#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26166#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26167#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26168#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26169#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26170#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26171#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26172//CGTS_CU8_LDS_SQ_CTRL_REG
26173#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26174#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26175#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26176#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26177#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26178#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26179#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26180#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26181#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26182#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26183#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26184#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26185#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26186#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26187#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26188#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26189#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26190#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26191#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26192#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26193//CGTS_CU8_TA_SQC_CTRL_REG
26194#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26195#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26196#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26197#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26198#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26199#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26200#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26201#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26202#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26203#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26204//CGTS_CU8_SP1_CTRL_REG
26205#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
26206#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26207#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26208#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26209#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26210#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
26211#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26212#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26213#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26214#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26215#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26216#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26217#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26218#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26219#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26220#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26221#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26222#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26223#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26224#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26225//CGTS_CU8_TD_TCP_CTRL_REG
26226#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26227#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26228#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26229#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26230#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26231#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26232#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26233#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26234#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26235#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26236#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26237#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26238#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26239#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26240#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26241#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26242#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26243#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26244#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26245#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26246//CGTS_CU9_SP0_CTRL_REG
26247#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
26248#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26249#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26250#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26251#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26252#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
26253#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26254#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26255#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26256#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26257#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26258#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26259#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26260#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26261#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26262#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26263#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26264#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26265#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26266#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26267//CGTS_CU9_LDS_SQ_CTRL_REG
26268#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26269#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26270#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26271#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26272#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26273#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26274#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26275#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26276#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26277#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26278#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26279#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26280#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26281#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26282#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26283#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26284#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26285#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26286#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26287#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26288//CGTS_CU9_TA_SQC_CTRL_REG
26289#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26290#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26291#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26292#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26293#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26294#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
26295#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
26296#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
26297#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
26298#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26299#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26300#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26301#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26302#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26303#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26304#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
26305#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
26306#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
26307#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
26308#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26309//CGTS_CU9_SP1_CTRL_REG
26310#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
26311#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26312#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26313#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26314#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26315#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
26316#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26317#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26318#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26319#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26320#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26321#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26322#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26323#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26324#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26325#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26326#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26327#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26328#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26329#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26330//CGTS_CU9_TD_TCP_CTRL_REG
26331#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26332#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26333#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26334#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26335#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26336#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26337#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26338#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26339#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26340#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26341#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26342#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26343#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26344#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26345#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26346#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26347#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26348#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26349#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26350#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26351//CGTS_CU10_SP0_CTRL_REG
26352#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
26353#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26354#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26355#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26356#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26357#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
26358#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26359#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26360#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26361#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26362#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26363#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26364#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26365#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26366#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26367#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26368#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26369#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26370#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26371#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26372//CGTS_CU10_LDS_SQ_CTRL_REG
26373#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26374#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26375#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26376#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26377#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26378#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26379#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26380#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26381#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26382#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26383#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26384#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26385#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26386#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26387#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26388#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26389#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26390#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26391#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26392#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26393//CGTS_CU10_TA_SQC_CTRL_REG
26394#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26395#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26396#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26397#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26398#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26399#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26400#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26401#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26402#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26403#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26404//CGTS_CU10_SP1_CTRL_REG
26405#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
26406#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26407#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26408#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26409#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26410#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
26411#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26412#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26413#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26414#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26415#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26416#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26417#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26418#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26419#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26420#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26421#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26422#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26423#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26424#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26425//CGTS_CU10_TD_TCP_CTRL_REG
26426#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26427#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26428#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26429#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26430#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26431#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26432#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26433#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26434#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26435#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26436#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26437#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26438#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26439#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26440#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26441#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26442#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26443#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26444#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26445#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26446//CGTS_CU11_SP0_CTRL_REG
26447#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
26448#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26449#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26450#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26451#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26452#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
26453#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26454#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26455#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26456#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26457#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26458#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26459#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26460#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26461#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26462#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26463#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26464#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26465#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26466#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26467//CGTS_CU11_LDS_SQ_CTRL_REG
26468#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26469#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26470#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26471#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26472#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26473#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26474#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26475#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26476#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26477#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26478#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26479#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26480#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26481#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26482#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26483#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26484#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26485#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26486#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26487#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26488//CGTS_CU11_TA_SQC_CTRL_REG
26489#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26490#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26491#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26492#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26493#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26494#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26495#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26496#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26497#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26498#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26499//CGTS_CU11_SP1_CTRL_REG
26500#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
26501#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26502#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26503#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26504#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26505#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
26506#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26507#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26508#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26509#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26510#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26511#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26512#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26513#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26514#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26515#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26516#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26517#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26518#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26519#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26520//CGTS_CU11_TD_TCP_CTRL_REG
26521#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26522#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26523#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26524#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26525#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26526#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26527#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26528#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26529#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26530#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26531#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26532#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26533#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26534#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26535#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26536#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26537#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26538#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26539#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26540#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26541//CGTS_CU12_SP0_CTRL_REG
26542#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
26543#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26544#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26545#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26546#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26547#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
26548#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26549#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26550#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26551#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26552#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26553#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26554#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26555#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26556#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26557#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26558#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26559#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26560#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26561#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26562//CGTS_CU12_LDS_SQ_CTRL_REG
26563#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26564#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26565#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26566#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26567#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26568#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26569#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26570#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26571#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26572#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26573#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26574#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26575#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26576#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26577#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26578#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26579#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26580#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26581#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26582#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26583//CGTS_CU12_TA_SQC_CTRL_REG
26584#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26585#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26586#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26587#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26588#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26589#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
26590#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
26591#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
26592#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
26593#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26594#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26595#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26596#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26597#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26598#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26599#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
26600#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
26601#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
26602#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
26603#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26604//CGTS_CU12_SP1_CTRL_REG
26605#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
26606#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26607#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26608#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26609#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26610#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
26611#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26612#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26613#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26614#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26615#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26616#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26617#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26618#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26619#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26620#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26621#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26622#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26623#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26624#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26625//CGTS_CU12_TD_TCP_CTRL_REG
26626#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26627#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26628#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26629#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26630#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26631#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26632#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26633#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26634#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26635#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26636#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26637#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26638#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26639#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26640#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26641#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26642#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26643#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26644#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26645#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26646//CGTS_CU13_SP0_CTRL_REG
26647#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
26648#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26649#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26650#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26651#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26652#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
26653#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26654#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26655#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26656#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26657#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26658#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26659#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26660#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26661#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26662#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26663#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26664#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26665#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26666#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26667//CGTS_CU13_LDS_SQ_CTRL_REG
26668#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26669#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26670#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26671#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26672#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26673#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26674#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26675#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26676#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26677#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26678#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26679#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26680#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26681#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26682#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26683#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26684#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26685#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26686#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26687#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26688//CGTS_CU13_TA_SQC_CTRL_REG
26689#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26690#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26691#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26692#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26693#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26694#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26695#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26696#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26697#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26698#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26699//CGTS_CU13_SP1_CTRL_REG
26700#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
26701#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26702#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26703#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26704#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26705#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
26706#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26707#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26708#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26709#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26710#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26711#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26712#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26713#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26714#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26715#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26716#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26717#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26718#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26719#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26720//CGTS_CU13_TD_TCP_CTRL_REG
26721#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26722#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26723#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26724#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26725#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26726#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26727#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26728#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26729#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26730#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26731#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26732#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26733#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26734#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26735#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26736#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26737#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26738#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26739#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26740#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26741//CGTS_CU14_SP0_CTRL_REG
26742#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
26743#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26744#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26745#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26746#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26747#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
26748#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26749#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26750#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26751#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26752#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26753#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26754#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26755#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26756#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26757#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26758#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26759#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26760#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26761#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26762//CGTS_CU14_LDS_SQ_CTRL_REG
26763#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26764#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26765#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26766#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26767#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26768#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26769#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26770#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26771#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26772#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26773#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26774#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26775#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26776#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26777#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26778#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26779#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26780#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26781#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26782#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26783//CGTS_CU14_TA_SQC_CTRL_REG
26784#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26785#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26786#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26787#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26788#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26789#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26790#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26791#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26792#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26793#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26794//CGTS_CU14_SP1_CTRL_REG
26795#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
26796#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26797#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26798#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26799#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26800#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
26801#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26802#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26803#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26804#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26805#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26806#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26807#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26808#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26809#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26810#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26811#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26812#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26813#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26814#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26815//CGTS_CU14_TD_TCP_CTRL_REG
26816#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26817#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26818#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26819#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26820#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26821#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26822#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26823#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26824#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26825#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26826#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26827#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26828#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26829#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26830#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26831#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26832#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26833#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26834#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26835#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26836//CGTS_CU15_SP0_CTRL_REG
26837#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
26838#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
26839#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
26840#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
26841#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
26842#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
26843#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
26844#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
26845#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
26846#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26847#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL
26848#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L
26849#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L
26850#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L
26851#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26852#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L
26853#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L
26854#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L
26855#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L
26856#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26857//CGTS_CU15_LDS_SQ_CTRL_REG
26858#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
26859#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
26860#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
26861#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
26862#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
26863#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
26864#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
26865#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
26866#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
26867#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26868#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL
26869#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L
26870#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L
26871#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L
26872#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26873#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L
26874#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L
26875#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L
26876#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L
26877#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26878//CGTS_CU15_TA_SQC_CTRL_REG
26879#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0
26880#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
26881#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
26882#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
26883#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
26884#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
26885#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
26886#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
26887#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
26888#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26889#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL
26890#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L
26891#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L
26892#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L
26893#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26894#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L
26895#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L
26896#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L
26897#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L
26898#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26899//CGTS_CU15_SP1_CTRL_REG
26900#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
26901#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
26902#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
26903#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
26904#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
26905#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
26906#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
26907#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
26908#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
26909#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26910#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL
26911#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L
26912#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L
26913#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L
26914#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26915#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L
26916#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L
26917#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L
26918#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L
26919#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26920//CGTS_CU15_TD_TCP_CTRL_REG
26921#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26922#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
26923#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
26924#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
26925#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
26926#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10
26927#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17
26928#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18
26929#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a
26930#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b
26931#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL
26932#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L
26933#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L
26934#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L
26935#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26936#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L
26937#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L
26938#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L
26939#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L
26940#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L
26941//CGTS_CU0_TCPI_CTRL_REG
26942#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0
26943#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
26944#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
26945#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26946#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
26947#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
26948#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
26949#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
26950#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
26951#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
26952#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26953#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
26954//CGTS_CU1_TCPI_CTRL_REG
26955#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0
26956#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
26957#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
26958#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26959#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
26960#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
26961#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
26962#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
26963#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
26964#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
26965#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26966#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
26967//CGTS_CU2_TCPI_CTRL_REG
26968#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0
26969#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
26970#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
26971#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26972#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
26973#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
26974#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
26975#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
26976#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
26977#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
26978#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26979#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
26980//CGTS_CU3_TCPI_CTRL_REG
26981#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0
26982#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
26983#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
26984#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26985#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
26986#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
26987#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
26988#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
26989#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
26990#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
26991#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
26992#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
26993//CGTS_CU4_TCPI_CTRL_REG
26994#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0
26995#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
26996#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
26997#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
26998#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
26999#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27000#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27001#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27002#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27003#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27004#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27005#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27006//CGTS_CU5_TCPI_CTRL_REG
27007#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27008#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27009#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27010#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27011#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27012#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27013#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27014#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27015#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27016#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27017#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27018#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27019//CGTS_CU6_TCPI_CTRL_REG
27020#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27021#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27022#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27023#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27024#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27025#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27026#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27027#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27028#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27029#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27030#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27031#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27032//CGTS_CU7_TCPI_CTRL_REG
27033#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27034#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27035#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27036#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27037#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27038#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27039#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27040#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27041#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27042#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27043#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27044#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27045//CGTS_CU8_TCPI_CTRL_REG
27046#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27047#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27048#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27049#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27050#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27051#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27052#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27053#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27054#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27055#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27056#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27057#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27058//CGTS_CU9_TCPI_CTRL_REG
27059#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27060#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27061#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27062#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27063#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27064#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27065#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27066#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27067#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27068#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27069#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27070#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27071//CGTS_CU10_TCPI_CTRL_REG
27072#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27073#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27074#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27075#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27076#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27077#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27078#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27079#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27080#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27081#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27082#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27083#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27084//CGTS_CU11_TCPI_CTRL_REG
27085#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27086#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27087#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27088#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27089#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27090#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27091#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27092#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27093#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27094#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27095#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27096#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27097//CGTS_CU12_TCPI_CTRL_REG
27098#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27099#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27100#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27101#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27102#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27103#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27104#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27105#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27106#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27107#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27108#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27109#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27110//CGTS_CU13_TCPI_CTRL_REG
27111#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27112#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27113#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27114#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27115#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27116#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27117#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27118#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27119#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27120#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27121#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27122#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27123//CGTS_CU14_TCPI_CTRL_REG
27124#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27125#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27126#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27127#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27128#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27129#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27130#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27131#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27132#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27133#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27134#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27135#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27136//CGTS_CU15_TCPI_CTRL_REG
27137#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0
27138#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7
27139#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8
27140#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa
27141#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb
27142#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc
27143#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL
27144#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27145#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L
27146#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L
27147#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L
27148#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L
27149//CGTT_SPI_PS_CLK_CTRL
27150#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0
27151#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27152#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
27153#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
27154#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
27155#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
27156#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
27157#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
27158#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
27159#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
27160#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
27161#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
27162#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
27163#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
27164#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
27165#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
27166#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27167#define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27168#define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27169#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
27170#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
27171#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
27172#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
27173#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
27174#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
27175#define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
27176#define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
27177#define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
27178#define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
27179#define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
27180#define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
27181#define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
27182#define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
27183#define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27184//CGTT_SPIS_CLK_CTRL
27185#define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0
27186#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27187#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
27188#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
27189#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
27190#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
27191#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
27192#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
27193#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
27194#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
27195#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
27196#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
27197#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
27198#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
27199#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
27200#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
27201#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27202#define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27203#define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27204#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
27205#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
27206#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
27207#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
27208#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
27209#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
27210#define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
27211#define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
27212#define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
27213#define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
27214#define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
27215#define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
27216#define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
27217#define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
27218#define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27219//CGTX_SPI_DEBUG_CLK_CTRL
27220#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0
27221#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6
27222#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7
27223#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT 0x8
27224#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL
27225#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L
27226#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L
27227#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK 0x00000100L
27228//CGTT_SPI_CLK_CTRL
27229#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
27230#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27231#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10
27232#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11
27233#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12
27234#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13
27235#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14
27236#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15
27237#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16
27238#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18
27239#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19
27240#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a
27241#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
27242#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
27243#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
27244#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
27245#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27246#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27247#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27248#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L
27249#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
27250#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
27251#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
27252#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
27253#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
27254#define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
27255#define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L
27256#define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L
27257#define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L
27258#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
27259#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
27260#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
27261#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
27262#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27263//CGTT_PC_CLK_CTRL
27264#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
27265#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27266#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11
27267#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
27268#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
27269#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19
27270#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a
27271#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
27272#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
27273#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
27274#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
27275#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27276#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27277#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27278#define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L
27279#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L
27280#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
27281#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L
27282#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L
27283#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
27284#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
27285#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
27286#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
27287#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27288//CGTT_BCI_CLK_CTRL
27289#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
27290#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27291#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
27292#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27293#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27294#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27295#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27296#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27297#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27298#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27299#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27300#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
27301#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
27302#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
27303#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
27304#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
27305#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
27306#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
27307#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27308#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27309#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27310#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L
27311#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27312#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27313#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27314#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27315#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27316#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27317#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27318#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27319#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
27320#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
27321#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
27322#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
27323#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
27324#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
27325#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
27326#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27327//CGTT_VGT_CLK_CTRL
27328#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
27329#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27330#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
27331#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27332#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27333#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27334#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27335#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27336#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27337#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27338#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18
27339#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
27340#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
27341#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
27342#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
27343#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
27344#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
27345#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27346#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27347#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27348#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
27349#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27350#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27351#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27352#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27353#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27354#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27355#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27356#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L
27357#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
27358#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
27359#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
27360#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
27361#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
27362#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
27363#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27364//CGTT_IA_CLK_CTRL
27365#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
27366#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27367#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27368#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27369#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27370#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27371#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27372#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27373#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27374#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27375#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27376#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
27377#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27378#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27379#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27380#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
27381#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27382#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27383#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27384#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27385#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27386#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27387#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27388#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27389#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27390#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27391#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27392#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27393#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
27394#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27395#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27396#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
27397#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
27398#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27399//CGTT_WD_CLK_CTRL
27400#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
27401#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27402#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf
27403#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27404#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27405#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27406#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27407#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27408#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27409#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27410#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19
27411#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a
27412#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b
27413#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c
27414#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
27415#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
27416#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27417#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27418#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27419#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L
27420#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27421#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27422#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27423#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27424#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27425#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27426#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27427#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L
27428#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L
27429#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L
27430#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L
27431#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
27432#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L
27433#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27434//CGTT_PA_CLK_CTRL
27435#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
27436#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27437#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27438#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27439#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27440#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27441#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27442#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27443#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27444#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27445#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27446#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27447#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27448#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27449#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
27450#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
27451#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
27452#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27453#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27454#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27455#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27456#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27457#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27458#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27459#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27460#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27461#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27462#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
27463#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
27464#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27465#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27466#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
27467#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
27468#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
27469//CGTT_SC_CLK_CTRL0
27470#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0
27471#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
27472#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10
27473#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11
27474#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12
27475#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13
27476#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14
27477#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15
27478#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16
27479#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17
27480#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18
27481#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19
27482#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a
27483#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b
27484#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c
27485#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d
27486#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e
27487#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f
27488#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
27489#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
27490#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L
27491#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L
27492#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L
27493#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L
27494#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L
27495#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L
27496#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L
27497#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L
27498#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L
27499#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L
27500#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L
27501#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L
27502#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L
27503#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L
27504#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L
27505#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L
27506//CGTT_SC_CLK_CTRL1
27507#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0
27508#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
27509#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11
27510#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12
27511#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13
27512#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14
27513#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15
27514#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16
27515#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19
27516#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a
27517#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b
27518#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c
27519#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d
27520#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e
27521#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
27522#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
27523#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L
27524#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L
27525#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L
27526#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L
27527#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L
27528#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L
27529#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L
27530#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L
27531#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L
27532#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L
27533#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L
27534#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L
27535//CGTT_SC_CLK_CTRL2
27536#define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0
27537#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
27538#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b
27539#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c
27540#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d
27541#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e
27542#define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
27543#define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
27544#define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L
27545#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L
27546#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L
27547#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L
27548//CGTT_SQ_CLK_CTRL
27549#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
27550#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27551#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27552#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27553#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27554#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27555#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27556#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27557#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27558#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27559#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
27560#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
27561#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27562#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27563#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27564#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27565#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27566#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27567#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27568#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27569#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27570#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27571#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27572#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
27573#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
27574#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27575//CGTT_SQG_CLK_CTRL
27576#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
27577#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27578#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27579#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27580#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27581#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27582#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27583#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27584#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27585#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27586#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
27587#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
27588#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
27589#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
27590#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27591#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27592#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27593#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27594#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27595#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27596#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27597#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27598#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27599#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27600#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L
27601#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L
27602#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
27603#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
27604//SQ_ALU_CLK_CTRL
27605#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
27606#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
27607#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
27608#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
27609//SQ_TEX_CLK_CTRL
27610#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
27611#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
27612#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
27613#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
27614//SQ_LDS_CLK_CTRL
27615#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
27616#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
27617#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL
27618#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L
27619//SQ_POWER_THROTTLE
27620#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
27621#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
27622#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
27623#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL
27624#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L
27625#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L
27626//SQ_POWER_THROTTLE2
27627#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
27628#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
27629#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
27630#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
27631#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL
27632#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
27633#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
27634#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L
27635//CGTT_SX_CLK_CTRL0
27636#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
27637#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
27638#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
27639#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27640#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27641#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27642#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27643#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27644#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27645#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27646#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27647#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
27648#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
27649#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
27650#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
27651#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
27652#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
27653#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
27654#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
27655#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL
27656#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L
27657#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L
27658#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27659#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27660#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27661#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27662#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27663#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27664#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27665#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27666#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
27667#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
27668#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
27669#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
27670#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
27671#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
27672#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
27673#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
27674//CGTT_SX_CLK_CTRL1
27675#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
27676#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
27677#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
27678#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27679#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27680#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27681#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27682#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27683#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27684#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27685#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27686#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
27687#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
27688#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
27689#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
27690#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
27691#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
27692#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
27693#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL
27694#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L
27695#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L
27696#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27697#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27698#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27699#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27700#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27701#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27702#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27703#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27704#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
27705#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
27706#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
27707#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
27708#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
27709#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
27710#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
27711//CGTT_SX_CLK_CTRL2
27712#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
27713#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
27714#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd
27715#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27716#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27717#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27718#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27719#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27720#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27721#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27722#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27723#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
27724#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
27725#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
27726#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
27727#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
27728#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
27729#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
27730#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL
27731#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L
27732#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L
27733#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27734#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27735#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27736#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27737#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27738#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27739#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27740#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27741#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
27742#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
27743#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
27744#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
27745#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
27746#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
27747#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
27748//CGTT_SX_CLK_CTRL3
27749#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
27750#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
27751#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd
27752#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27753#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27754#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27755#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27756#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27757#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27758#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27759#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27760#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
27761#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
27762#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
27763#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
27764#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
27765#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
27766#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
27767#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL
27768#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L
27769#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L
27770#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27771#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27772#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27773#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27774#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27775#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27776#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27777#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27778#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
27779#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
27780#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
27781#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
27782#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
27783#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
27784#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
27785//CGTT_SX_CLK_CTRL4
27786#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
27787#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
27788#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
27789#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27790#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27791#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27792#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27793#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27794#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27795#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27796#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27797#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
27798#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
27799#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
27800#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
27801#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
27802#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
27803#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
27804#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL
27805#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L
27806#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L
27807#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27808#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27809#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27810#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27811#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27812#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27813#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27814#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27815#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
27816#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
27817#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
27818#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
27819#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
27820#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
27821#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
27822//TD_CGTT_CTRL
27823#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
27824#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27825#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27826#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27827#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27828#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27829#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27830#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27831#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27832#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27833#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27834#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27835#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27836#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27837#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27838#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27839#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
27840#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
27841#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
27842#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27843#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27844#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27845#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27846#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27847#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27848#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27849#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27850#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27851#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27852#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
27853#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
27854#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27855#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27856#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
27857#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
27858#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
27859//TA_CGTT_CTRL
27860#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
27861#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27862#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27863#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27864#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27865#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27866#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27867#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27868#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27869#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27870#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27871#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27872#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27873#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27874#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27875#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27876#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
27877#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
27878#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL
27879#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27880#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27881#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27882#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27883#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27884#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27885#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27886#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27887#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27888#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27889#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
27890#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
27891#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27892#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27893#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
27894#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
27895#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
27896//CGTT_TCPI_CLK_CTRL
27897#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
27898#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27899#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc
27900#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27901#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27902#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27903#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27904#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27905#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27906#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27907#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27908#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27909#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27910#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27911#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27912#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27913#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27914#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
27915#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
27916#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27917#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27918#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L
27919#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27920#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27921#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27922#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27923#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27924#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27925#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27926#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27927#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27928#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
27929#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
27930#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27931#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27932#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
27933#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
27934#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
27935//CGTT_TCI_CLK_CTRL
27936#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
27937#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27938#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27939#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27940#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27941#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27942#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27943#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27944#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27945#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27946#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27947#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27948#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27949#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27950#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27951#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27952#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
27953#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
27954#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27955#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27956#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27957#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27958#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27959#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27960#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27961#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27962#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
27963#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
27964#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
27965#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
27966#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
27967#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
27968#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
27969#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
27970#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
27971#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
27972//CGTT_GDS_CLK_CTRL
27973#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
27974#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
27975#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
27976#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
27977#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
27978#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
27979#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
27980#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
27981#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
27982#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
27983#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
27984#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
27985#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
27986#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
27987#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
27988#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
27989#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
27990#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
27991#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
27992#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
27993#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
27994#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
27995#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
27996#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
27997#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
27998#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
27999#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28000#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28001#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
28002#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28003#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28004#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28005#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28006#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28007#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28008#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28009//DB_CGTT_CLK_CTRL_0
28010#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
28011#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
28012#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
28013#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28014#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28015#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28016#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28017#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28018#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28019#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28020#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28021#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
28022#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
28023#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
28024#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
28025#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
28026#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
28027#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
28028#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
28029#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL
28030#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L
28031#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L
28032#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28033#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28034#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28035#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28036#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28037#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28038#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28039#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28040#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
28041#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
28042#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
28043#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
28044#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
28045#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
28046#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
28047#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
28048//CB_CGTT_SCLK_CTRL
28049#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
28050#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28051#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28052#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28053#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28054#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28055#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28056#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28057#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28058#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28059#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
28060#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
28061#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
28062#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
28063#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
28064#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
28065#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
28066#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
28067#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
28068#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28069#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28070#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28071#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28072#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28073#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28074#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28075#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28076#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28077#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
28078#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28079#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28080#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28081#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28082#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28083#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28084#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28085//TCC_CGTT_SCLK_CTRL
28086#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
28087#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28088#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28089#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28090#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28091#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28092#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28093#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28094#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28095#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28096#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
28097#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
28098#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
28099#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
28100#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
28101#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
28102#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
28103#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
28104#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
28105#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28106#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28107#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28108#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28109#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28110#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28111#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28112#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28113#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28114#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
28115#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28116#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28117#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28118#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28119#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28120#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28121#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28122//TCA_CGTT_SCLK_CTRL
28123#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
28124#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28125#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28126#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28127#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28128#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28129#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28130#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28131#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28132#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28133#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
28134#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
28135#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
28136#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
28137#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
28138#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
28139#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
28140#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
28141#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
28142#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28143#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28144#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28145#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28146#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28147#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28148#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28149#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28150#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28151#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
28152#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28153#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28154#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28155#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28156#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28157#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28158#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28159//CGTT_CP_CLK_CTRL
28160#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
28161#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28162#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
28163#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28164#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28165#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28166#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28167#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28168#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28169#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28170#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28171#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
28172#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28173#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28174#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28175#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28176#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
28177#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28178#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28179#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28180#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28181#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28182#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28183#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28184#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28185#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
28186#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28187#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28188//CGTT_CPF_CLK_CTRL
28189#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
28190#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28191#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
28192#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28193#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28194#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28195#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28196#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28197#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28198#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28199#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28200#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
28201#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28202#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28203#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28204#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28205#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
28206#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28207#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28208#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28209#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28210#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28211#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28212#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28213#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28214#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
28215#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28216#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28217//CGTT_CPC_CLK_CTRL
28218#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
28219#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28220#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
28221#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28222#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28223#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28224#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28225#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28226#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28227#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28228#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28229#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
28230#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28231#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28232#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28233#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28234#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
28235#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28236#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28237#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28238#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28239#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28240#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28241#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28242#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28243#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L
28244#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28245#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28246//CGTT_RLC_CLK_CTRL
28247#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
28248#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28249#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28250#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28251#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28252#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28253#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28254#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28255#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28256#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28257#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28258#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28259#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28260#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28261#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28262#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28263#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28264#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28265#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28266#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28267#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28268#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28269#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28270#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28271//RLC_GFX_RM_CNTL
28272#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0
28273#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1
28274#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L
28275#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL
28276//RMI_CGTT_SCLK_CTRL
28277#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
28278#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28279#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28280#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28281#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28282#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28283#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28284#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28285#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28286#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28287#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
28288#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
28289#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
28290#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
28291#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
28292#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
28293#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
28294#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL
28295#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28296#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28297#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28298#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28299#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28300#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28301#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28302#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28303#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28304#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28305#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28306#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28307#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28308#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28309#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28310#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28311//CGTT_TCPF_CLK_CTRL
28312#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
28313#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28314#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc
28315#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28316#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28317#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28318#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28319#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28320#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28321#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28322#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28323#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
28324#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
28325#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
28326#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
28327#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
28328#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
28329#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
28330#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
28331#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28332#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28333#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L
28334#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28335#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28336#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28337#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28338#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28339#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28340#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28341#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28342#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
28343#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
28344#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
28345#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
28346#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
28347#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
28348#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
28349#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
28350//SE_CAC_CGTT_CLK_CTRL
28351#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
28352#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28353#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28354#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28355#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28356#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28357#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28358#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28359//GC_CAC_CGTT_CLK_CTRL
28360#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
28361#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28362#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28363#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
28364#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28365#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28366#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28367#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
28368//GRBM_CGTT_CLK_CNTL
28369#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
28370#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
28371#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
28372#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
28373#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
28374#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
28375#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
28376#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
28377#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
28378#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
28379#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
28380#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
28381#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
28382#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
28383#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
28384#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
28385#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
28386#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28387#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
28388#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
28389#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
28390#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
28391
28392
28393// addressBlock: gc_ea_pwrdec
28394//GCEA_CGTT_CLK_CTRL
28395#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
28396#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28397#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16
28398#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e
28399#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f
28400#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28401#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28402#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L
28403#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L
28404#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L
28405
28406
28407// addressBlock: gc_utcl2_vmsharedhvdec
28408//MC_VM_FB_SIZE_OFFSET_VF0
28409#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
28410#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
28411#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL
28412#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L
28413//MC_VM_FB_SIZE_OFFSET_VF1
28414#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
28415#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
28416#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL
28417#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L
28418//MC_VM_FB_SIZE_OFFSET_VF2
28419#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
28420#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
28421#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL
28422#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L
28423//MC_VM_FB_SIZE_OFFSET_VF3
28424#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
28425#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
28426#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL
28427#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L
28428//MC_VM_FB_SIZE_OFFSET_VF4
28429#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
28430#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
28431#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL
28432#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L
28433//MC_VM_FB_SIZE_OFFSET_VF5
28434#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
28435#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
28436#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL
28437#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L
28438//MC_VM_FB_SIZE_OFFSET_VF6
28439#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
28440#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
28441#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL
28442#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L
28443//MC_VM_FB_SIZE_OFFSET_VF7
28444#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
28445#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
28446#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL
28447#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L
28448//MC_VM_FB_SIZE_OFFSET_VF8
28449#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
28450#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
28451#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL
28452#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L
28453//MC_VM_FB_SIZE_OFFSET_VF9
28454#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
28455#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
28456#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL
28457#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L
28458//MC_VM_FB_SIZE_OFFSET_VF10
28459#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
28460#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
28461#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL
28462#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L
28463//MC_VM_FB_SIZE_OFFSET_VF11
28464#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
28465#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
28466#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL
28467#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L
28468//MC_VM_FB_SIZE_OFFSET_VF12
28469#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
28470#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
28471#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL
28472#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L
28473//MC_VM_FB_SIZE_OFFSET_VF13
28474#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
28475#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
28476#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL
28477#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L
28478//MC_VM_FB_SIZE_OFFSET_VF14
28479#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
28480#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
28481#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL
28482#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L
28483//MC_VM_FB_SIZE_OFFSET_VF15
28484#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
28485#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
28486#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL
28487#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L
28488//VM_IOMMU_MMIO_CNTRL_1
28489#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8
28490#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L
28491//MC_VM_MARC_BASE_LO_0
28492#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
28493#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L
28494//MC_VM_MARC_BASE_LO_1
28495#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
28496#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L
28497//MC_VM_MARC_BASE_LO_2
28498#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
28499#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L
28500//MC_VM_MARC_BASE_LO_3
28501#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
28502#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L
28503//MC_VM_MARC_BASE_HI_0
28504#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
28505#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL
28506//MC_VM_MARC_BASE_HI_1
28507#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
28508#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL
28509//MC_VM_MARC_BASE_HI_2
28510#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
28511#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL
28512//MC_VM_MARC_BASE_HI_3
28513#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
28514#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL
28515//MC_VM_MARC_RELOC_LO_0
28516#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
28517#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
28518#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
28519#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L
28520#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L
28521#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L
28522//MC_VM_MARC_RELOC_LO_1
28523#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
28524#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
28525#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
28526#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L
28527#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L
28528#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L
28529//MC_VM_MARC_RELOC_LO_2
28530#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
28531#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
28532#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
28533#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L
28534#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L
28535#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L
28536//MC_VM_MARC_RELOC_LO_3
28537#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
28538#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
28539#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
28540#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L
28541#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L
28542#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L
28543//MC_VM_MARC_RELOC_HI_0
28544#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
28545#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL
28546//MC_VM_MARC_RELOC_HI_1
28547#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
28548#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL
28549//MC_VM_MARC_RELOC_HI_2
28550#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
28551#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL
28552//MC_VM_MARC_RELOC_HI_3
28553#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
28554#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL
28555//MC_VM_MARC_LEN_LO_0
28556#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
28557#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L
28558//MC_VM_MARC_LEN_LO_1
28559#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
28560#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L
28561//MC_VM_MARC_LEN_LO_2
28562#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
28563#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L
28564//MC_VM_MARC_LEN_LO_3
28565#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
28566#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L
28567//MC_VM_MARC_LEN_HI_0
28568#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
28569#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL
28570//MC_VM_MARC_LEN_HI_1
28571#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
28572#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL
28573//MC_VM_MARC_LEN_HI_2
28574#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
28575#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL
28576//MC_VM_MARC_LEN_HI_3
28577#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
28578#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL
28579//VM_IOMMU_CONTROL_REGISTER
28580#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0
28581#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L
28582//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
28583#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd
28584#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L
28585//VM_PCIE_ATS_CNTL
28586#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10
28587#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f
28588#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L
28589#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L
28590//VM_PCIE_ATS_CNTL_VF_0
28591#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f
28592#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L
28593//VM_PCIE_ATS_CNTL_VF_1
28594#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f
28595#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L
28596//VM_PCIE_ATS_CNTL_VF_2
28597#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f
28598#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L
28599//VM_PCIE_ATS_CNTL_VF_3
28600#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f
28601#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L
28602//VM_PCIE_ATS_CNTL_VF_4
28603#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f
28604#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L
28605//VM_PCIE_ATS_CNTL_VF_5
28606#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f
28607#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L
28608//VM_PCIE_ATS_CNTL_VF_6
28609#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f
28610#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L
28611//VM_PCIE_ATS_CNTL_VF_7
28612#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f
28613#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L
28614//VM_PCIE_ATS_CNTL_VF_8
28615#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f
28616#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L
28617//VM_PCIE_ATS_CNTL_VF_9
28618#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f
28619#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L
28620//VM_PCIE_ATS_CNTL_VF_10
28621#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f
28622#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L
28623//VM_PCIE_ATS_CNTL_VF_11
28624#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f
28625#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L
28626//VM_PCIE_ATS_CNTL_VF_12
28627#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f
28628#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L
28629//VM_PCIE_ATS_CNTL_VF_13
28630#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f
28631#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L
28632//VM_PCIE_ATS_CNTL_VF_14
28633#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f
28634#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L
28635//VM_PCIE_ATS_CNTL_VF_15
28636#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f
28637#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L
28638//UTCL2_CGTT_CLK_CTRL
28639#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
28640#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
28641#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc
28642#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
28643#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
28644#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
28645#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
28646#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
28647#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L
28648#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
28649#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
28650#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
28651//MC_SHARED_ACTIVE_FCN_ID
28652#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
28653#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
28654#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL
28655#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L
28656//MC_VM_XGMI_GPUIOV_ENABLE
28657#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0
28658#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1
28659#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2
28660#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3
28661#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4
28662#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5
28663#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6
28664#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7
28665#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8
28666#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9
28667#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa
28668#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb
28669#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc
28670#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd
28671#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe
28672#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf
28673#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f
28674#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L
28675#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L
28676#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L
28677#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L
28678#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L
28679#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L
28680#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L
28681#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L
28682#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L
28683#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L
28684#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L
28685#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L
28686#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L
28687#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L
28688#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L
28689#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L
28690#define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L
28691
28692
28693// addressBlock: gc_hypdec
28694//CP_HYP_PFP_UCODE_ADDR
28695#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28696#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
28697//CP_PFP_UCODE_ADDR
28698#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28699#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
28700//CP_HYP_PFP_UCODE_DATA
28701#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28702#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28703//CP_PFP_UCODE_DATA
28704#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28705#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28706//CP_HYP_ME_UCODE_ADDR
28707#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28708#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL
28709//CP_ME_RAM_RADDR
28710#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
28711#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL
28712//CP_ME_RAM_WADDR
28713#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
28714#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL
28715//CP_HYP_ME_UCODE_DATA
28716#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28717#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28718//CP_ME_RAM_DATA
28719#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
28720#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL
28721//CP_CE_UCODE_ADDR
28722#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28723#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
28724//CP_HYP_CE_UCODE_ADDR
28725#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28726#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
28727//CP_CE_UCODE_DATA
28728#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28729#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28730//CP_HYP_CE_UCODE_DATA
28731#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28732#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28733//CP_HYP_MEC1_UCODE_ADDR
28734#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28735#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
28736//CP_MEC_ME1_UCODE_ADDR
28737#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28738#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
28739//CP_HYP_MEC1_UCODE_DATA
28740#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28741#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28742//CP_MEC_ME1_UCODE_DATA
28743#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28744#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28745//CP_HYP_MEC2_UCODE_ADDR
28746#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28747#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
28748//CP_MEC_ME2_UCODE_ADDR
28749#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28750#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL
28751//CP_HYP_MEC2_UCODE_DATA
28752#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28753#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28754//CP_MEC_ME2_UCODE_DATA
28755#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28756#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28757//CP_HYP_PFP_UCODE_CHKSUM
28758#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
28759#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
28760//CP_HYP_CE_UCODE_CHKSUM
28761#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
28762#define CP_HYP_CE_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
28763//CP_HYP_ME_UCODE_CHKSUM
28764#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
28765#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
28766//CP_HYP_MEC_ME1_UCODE_CHKSUM
28767#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
28768#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
28769//CP_HYP_MEC_ME2_UCODE_CHKSUM
28770#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0
28771#define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL
28772//RLC_GPM_UCODE_ADDR
28773#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28774#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe
28775#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL
28776#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L
28777//RLC_GPM_UCODE_DATA
28778#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28779#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28780//GRBM_GFX_INDEX_SR_SELECT
28781#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0
28782#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L
28783//GRBM_GFX_INDEX_SR_DATA
28784#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0
28785#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8
28786#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10
28787#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
28788#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
28789#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
28790#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL
28791#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L
28792#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L
28793#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L
28794#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L
28795#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L
28796//GRBM_GFX_CNTL_SR_SELECT
28797#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0
28798#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L
28799//GRBM_GFX_CNTL_SR_DATA
28800#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0
28801#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2
28802#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4
28803#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8
28804#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L
28805#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL
28806#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L
28807#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L
28808//GRBM_CAM_INDEX
28809#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
28810#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
28811//GRBM_HYP_CAM_INDEX
28812#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
28813#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
28814//GRBM_CAM_DATA
28815#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
28816#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
28817#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
28818#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
28819//GRBM_HYP_CAM_DATA
28820#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
28821#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
28822#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL
28823#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L
28824//RLC_GPU_IOV_VF_ENABLE
28825#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
28826#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
28827#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
28828#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L
28829#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL
28830#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L
28831//RLC_GPU_IOV_CFG_REG6
28832#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
28833#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
28834#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
28835#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
28836#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL
28837#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L
28838#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L
28839#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L
28840//RLC_GPU_IOV_CFG_REG8
28841#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
28842#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
28843//RLC_RLCV_TIMER_INT_0
28844#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0
28845#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL
28846//RLC_RLCV_TIMER_CTRL
28847#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0
28848#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1
28849#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x2
28850#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L
28851#define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L
28852#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFCL
28853//RLC_RLCV_TIMER_STAT
28854#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0
28855#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1
28856#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2
28857#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8
28858#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9
28859#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L
28860#define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L
28861#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL
28862#define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L
28863#define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L
28864//RLC_GPU_IOV_VF_DOORBELL_STATUS
28865#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0
28866#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10
28867#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f
28868#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL
28869#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L
28870#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L
28871//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
28872#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0
28873#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10
28874#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f
28875#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL
28876#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L
28877#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L
28878//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
28879#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0
28880#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10
28881#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f
28882#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL
28883#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L
28884#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L
28885//RLC_GPU_IOV_VF_MASK
28886#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0
28887#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10
28888#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL
28889#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L
28890//RLC_HYP_SEMAPHORE_0
28891#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0
28892#define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5
28893#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL
28894#define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L
28895//RLC_HYP_SEMAPHORE_1
28896#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0
28897#define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5
28898#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL
28899#define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L
28900//RLC_CLK_CNTL
28901#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0
28902#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2
28903#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4
28904#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5
28905#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6
28906#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0x7
28907#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8
28908#define RLC_CLK_CNTL__RESERVED__SHIFT 0x9
28909#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L
28910#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL
28911#define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L
28912#define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L
28913#define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L
28914#define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000080L
28915#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L
28916#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFE00L
28917//RLC_GPU_IOV_SCH_BLOCK
28918#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0
28919#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4
28920#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8
28921#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10
28922#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL
28923#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L
28924#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L
28925#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L
28926//RLC_GPU_IOV_CFG_REG1
28927#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
28928#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
28929#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
28930#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
28931#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
28932#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
28933#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
28934#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL
28935#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L
28936#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L
28937#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L
28938#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L
28939#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L
28940#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L
28941//RLC_GPU_IOV_CFG_REG2
28942#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
28943#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
28944#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL
28945#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L
28946//RLC_GPU_IOV_VM_BUSY_STATUS
28947#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
28948#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
28949//RLC_GPU_IOV_SCH_0
28950#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0
28951#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL
28952//RLC_GPU_IOV_ACTIVE_FCN_ID
28953#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
28954#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
28955#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
28956#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL
28957#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L
28958#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L
28959//RLC_GPU_IOV_SCH_3
28960#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0
28961#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL
28962//RLC_GPU_IOV_SCH_1
28963#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
28964#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL
28965//RLC_GPU_IOV_SCH_2
28966#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
28967#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL
28968//RLC_GPU_IOV_INT_STAT
28969#define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0
28970#define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL
28971//RLC_RLCV_TIMER_INT_1
28972#define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0
28973#define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL
28974//RLC_GPU_IOV_UCODE_ADDR
28975#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
28976#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
28977#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL
28978#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L
28979//RLC_GPU_IOV_UCODE_DATA
28980#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
28981#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL
28982//RLC_GPU_IOV_SCRATCH_ADDR
28983#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
28984#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
28985#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL
28986#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L
28987//RLC_GPU_IOV_SCRATCH_DATA
28988#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
28989#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL
28990//RLC_GPU_IOV_F32_CNTL
28991#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
28992#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
28993#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L
28994#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL
28995//RLC_GPU_IOV_F32_RESET
28996#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
28997#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
28998#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L
28999#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL
29000//RLC_GPU_IOV_SDMA0_STATUS
29001#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
29002#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
29003#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
29004#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
29005#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
29006#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
29007#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L
29008#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL
29009#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L
29010#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L
29011#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L
29012#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L
29013//RLC_GPU_IOV_SDMA1_STATUS
29014#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
29015#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
29016#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
29017#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
29018#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
29019#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
29020#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L
29021#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL
29022#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L
29023#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L
29024#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L
29025#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L
29026//RLC_GPU_IOV_SMU_RESPONSE
29027#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
29028#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL
29029//RLC_GPU_IOV_VIRT_RESET_REQ
29030#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
29031#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
29032#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
29033#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL
29034#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L
29035#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L
29036//RLC_GPU_IOV_RLC_RESPONSE
29037#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
29038#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL
29039//RLC_GPU_IOV_INT_DISABLE
29040#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
29041#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL
29042//RLC_GPU_IOV_INT_FORCE
29043#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
29044#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL
29045//RLC_GPU_IOV_SDMA0_BUSY_STATUS
29046#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
29047#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
29048//RLC_GPU_IOV_SDMA1_BUSY_STATUS
29049#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
29050#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL
29051//RLC_HYP_SEMAPHORE_2
29052#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0
29053#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5
29054#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL
29055#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L
29056//RLC_HYP_SEMAPHORE_3
29057#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0
29058#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5
29059#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL
29060#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L
29061
29062
29063// addressBlock: gccacind
29064//GC_CAC_CNTL
29065#define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
29066#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
29067#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
29068#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
29069#define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
29070#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
29071#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
29072#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
29073//GC_CAC_OVR_SEL
29074#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
29075#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
29076//GC_CAC_OVR_VAL
29077#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
29078#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
29079//GC_CAC_WEIGHT_BCI_0
29080#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0
29081#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10
29082#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL
29083#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L
29084//GC_CAC_WEIGHT_CB_0
29085#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0
29086#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10
29087#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL
29088#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L
29089//GC_CAC_WEIGHT_CB_1
29090#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0
29091#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10
29092#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL
29093#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L
29094//GC_CAC_WEIGHT_CP_0
29095#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0
29096#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10
29097#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL
29098#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L
29099//GC_CAC_WEIGHT_CP_1
29100#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0
29101#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL
29102//GC_CAC_WEIGHT_DB_0
29103#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0
29104#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10
29105#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL
29106#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L
29107//GC_CAC_WEIGHT_DB_1
29108#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0
29109#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10
29110#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL
29111#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L
29112//GC_CAC_WEIGHT_GDS_0
29113#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0
29114#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10
29115#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL
29116#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L
29117//GC_CAC_WEIGHT_GDS_1
29118#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0
29119#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10
29120#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL
29121#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L
29122//GC_CAC_WEIGHT_IA_0
29123#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0
29124#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL
29125//GC_CAC_WEIGHT_LDS_0
29126#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0
29127#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10
29128#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL
29129#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L
29130//GC_CAC_WEIGHT_LDS_1
29131#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0
29132#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10
29133#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL
29134#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L
29135//GC_CAC_WEIGHT_PA_0
29136#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0
29137#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10
29138#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL
29139#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L
29140//GC_CAC_WEIGHT_PC_0
29141#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0
29142#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL
29143//GC_CAC_WEIGHT_SC_0
29144#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0
29145#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL
29146//GC_CAC_WEIGHT_SPI_0
29147#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0
29148#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10
29149#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL
29150#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L
29151//GC_CAC_WEIGHT_SPI_1
29152#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0
29153#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10
29154#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL
29155#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L
29156//GC_CAC_WEIGHT_SPI_2
29157#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0
29158#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10
29159#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL
29160#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L
29161//GC_CAC_WEIGHT_SQ_0
29162#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0
29163#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10
29164#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL
29165#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L
29166//GC_CAC_WEIGHT_SQ_1
29167#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0
29168#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10
29169#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL
29170#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L
29171//GC_CAC_WEIGHT_SQ_2
29172#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0
29173#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10
29174#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL
29175#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L
29176//GC_CAC_WEIGHT_SQ_3
29177#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0
29178#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10
29179#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL
29180#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L
29181//GC_CAC_WEIGHT_SQ_4
29182#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0
29183#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL
29184//GC_CAC_WEIGHT_SX_0
29185#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0
29186#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL
29187//GC_CAC_WEIGHT_SXRB_0
29188#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0
29189#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL
29190//GC_CAC_WEIGHT_TA_0
29191#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0
29192#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL
29193//GC_CAC_WEIGHT_TCC_0
29194#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0
29195#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10
29196#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL
29197#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L
29198//GC_CAC_WEIGHT_TCC_1
29199#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0
29200#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10
29201#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL
29202#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L
29203//GC_CAC_WEIGHT_TCC_2
29204#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0
29205#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL
29206//GC_CAC_WEIGHT_TCP_0
29207#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0
29208#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10
29209#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL
29210#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L
29211//GC_CAC_WEIGHT_TCP_1
29212#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0
29213#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10
29214#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL
29215#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L
29216//GC_CAC_WEIGHT_TCP_2
29217#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0
29218#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL
29219//GC_CAC_WEIGHT_TD_0
29220#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0
29221#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10
29222#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL
29223#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L
29224//GC_CAC_WEIGHT_TD_1
29225#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0
29226#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10
29227#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL
29228#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L
29229//GC_CAC_WEIGHT_TD_2
29230#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0
29231#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10
29232#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL
29233#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L
29234//GC_CAC_WEIGHT_VGT_0
29235#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0
29236#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10
29237#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL
29238#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L
29239//GC_CAC_WEIGHT_VGT_1
29240#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0
29241#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL
29242//GC_CAC_WEIGHT_WD_0
29243#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0
29244#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL
29245//GC_CAC_WEIGHT_CU_0
29246#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0
29247#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL
29248//GC_CAC_ACC_BCI0
29249#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0
29250#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29251//GC_CAC_ACC_CB0
29252#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0
29253#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29254//GC_CAC_ACC_CB1
29255#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0
29256#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29257//GC_CAC_ACC_CB2
29258#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0
29259#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29260//GC_CAC_ACC_CB3
29261#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0
29262#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29263//GC_CAC_ACC_CP0
29264#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0
29265#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29266//GC_CAC_ACC_CP1
29267#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0
29268#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29269//GC_CAC_ACC_CP2
29270#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0
29271#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29272//GC_CAC_ACC_DB0
29273#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0
29274#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29275//GC_CAC_ACC_DB1
29276#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0
29277#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29278//GC_CAC_ACC_DB2
29279#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0
29280#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29281//GC_CAC_ACC_DB3
29282#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0
29283#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29284//GC_CAC_ACC_GDS0
29285#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0
29286#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29287//GC_CAC_ACC_GDS1
29288#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0
29289#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29290//GC_CAC_ACC_GDS2
29291#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0
29292#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29293//GC_CAC_ACC_GDS3
29294#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0
29295#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29296//GC_CAC_ACC_IA0
29297#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0
29298#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29299//GC_CAC_ACC_LDS0
29300#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0
29301#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29302//GC_CAC_ACC_LDS1
29303#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0
29304#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29305//GC_CAC_ACC_LDS2
29306#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0
29307#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29308//GC_CAC_ACC_LDS3
29309#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0
29310#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29311//GC_CAC_ACC_PA0
29312#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0
29313#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29314//GC_CAC_ACC_PA1
29315#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0
29316#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29317//GC_CAC_ACC_PC0
29318#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0
29319#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29320//GC_CAC_ACC_SC0
29321#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0
29322#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29323//GC_CAC_ACC_SPI0
29324#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0
29325#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29326//GC_CAC_ACC_SPI1
29327#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0
29328#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29329//GC_CAC_ACC_SPI2
29330#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0
29331#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29332//GC_CAC_ACC_SPI3
29333#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0
29334#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29335//GC_CAC_ACC_SPI4
29336#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0
29337#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29338//GC_CAC_ACC_SPI5
29339#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0
29340#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29341//GC_CAC_WEIGHT_UTCL2_ATCL2_0
29342#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0
29343#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10
29344#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL
29345#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L
29346//GC_CAC_ACC_EA0
29347#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0
29348#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29349//GC_CAC_ACC_EA1
29350#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0
29351#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29352//GC_CAC_ACC_EA2
29353#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0
29354#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29355//GC_CAC_ACC_EA3
29356#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0
29357#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29358//GC_CAC_ACC_UTCL2_ATCL20
29359#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0
29360#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29361//GC_CAC_OVRD_EA
29362#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0
29363#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6
29364#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL
29365#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L
29366//GC_CAC_OVRD_UTCL2_ATCL2
29367#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0
29368#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5
29369#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL
29370#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L
29371//GC_CAC_WEIGHT_EA_0
29372#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0
29373#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10
29374#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL
29375#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L
29376//GC_CAC_WEIGHT_EA_1
29377#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0
29378#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10
29379#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL
29380#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L
29381//GC_CAC_WEIGHT_RMI_0
29382#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0
29383#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL
29384//GC_CAC_ACC_RMI0
29385#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0
29386#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29387//GC_CAC_OVRD_RMI
29388#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0
29389#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1
29390#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L
29391#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L
29392//GC_CAC_WEIGHT_UTCL2_ATCL2_1
29393#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0
29394#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10
29395#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL
29396#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L
29397//GC_CAC_ACC_UTCL2_ATCL21
29398#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0
29399#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29400//GC_CAC_ACC_UTCL2_ATCL22
29401#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0
29402#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29403//GC_CAC_ACC_UTCL2_ATCL23
29404#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0
29405#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29406//GC_CAC_ACC_EA4
29407#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0
29408#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29409//GC_CAC_ACC_EA5
29410#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0
29411#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29412//GC_CAC_WEIGHT_EA_2
29413#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0
29414#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10
29415#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL
29416#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L
29417//GC_CAC_ACC_SQ0_LOWER
29418#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29419#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29420//GC_CAC_ACC_SQ0_UPPER
29421#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29422#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29423//GC_CAC_ACC_SQ1_LOWER
29424#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29425#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29426//GC_CAC_ACC_SQ1_UPPER
29427#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29428#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29429//GC_CAC_ACC_SQ2_LOWER
29430#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29431#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29432//GC_CAC_ACC_SQ2_UPPER
29433#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29434#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29435//GC_CAC_ACC_SQ3_LOWER
29436#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29437#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29438//GC_CAC_ACC_SQ3_UPPER
29439#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29440#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29441//GC_CAC_ACC_SQ4_LOWER
29442#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29443#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29444//GC_CAC_ACC_SQ4_UPPER
29445#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29446#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29447//GC_CAC_ACC_SQ5_LOWER
29448#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29449#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29450//GC_CAC_ACC_SQ5_UPPER
29451#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29452#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29453//GC_CAC_ACC_SQ6_LOWER
29454#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29455#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29456//GC_CAC_ACC_SQ6_UPPER
29457#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29458#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29459//GC_CAC_ACC_SQ7_LOWER
29460#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29461#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29462//GC_CAC_ACC_SQ7_UPPER
29463#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29464#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29465//GC_CAC_ACC_SQ8_LOWER
29466#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0
29467#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29468//GC_CAC_ACC_SQ8_UPPER
29469#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0
29470#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL
29471//GC_CAC_ACC_SX0
29472#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0
29473#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29474//GC_CAC_ACC_SXRB0
29475#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0
29476#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29477//GC_CAC_ACC_SXRB1
29478#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0
29479#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29480//GC_CAC_ACC_TA0
29481#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0
29482#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29483//GC_CAC_ACC_TCC0
29484#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0
29485#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29486//GC_CAC_ACC_TCC1
29487#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0
29488#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29489//GC_CAC_ACC_TCC2
29490#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0
29491#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29492//GC_CAC_ACC_TCC3
29493#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0
29494#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29495//GC_CAC_ACC_TCC4
29496#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0
29497#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29498//GC_CAC_ACC_TCP0
29499#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0
29500#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29501//GC_CAC_ACC_TCP1
29502#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0
29503#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29504//GC_CAC_ACC_TCP2
29505#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0
29506#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29507//GC_CAC_ACC_TCP3
29508#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0
29509#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29510//GC_CAC_ACC_TCP4
29511#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0
29512#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29513//GC_CAC_ACC_TD0
29514#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0
29515#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29516//GC_CAC_ACC_TD1
29517#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0
29518#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29519//GC_CAC_ACC_TD2
29520#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0
29521#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29522//GC_CAC_ACC_TD3
29523#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0
29524#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29525//GC_CAC_ACC_TD4
29526#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0
29527#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29528//GC_CAC_ACC_TD5
29529#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0
29530#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29531//GC_CAC_ACC_VGT0
29532#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0
29533#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29534//GC_CAC_ACC_VGT1
29535#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0
29536#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29537//GC_CAC_ACC_VGT2
29538#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0
29539#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29540//GC_CAC_ACC_WD0
29541#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0
29542#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29543//GC_CAC_ACC_CU0
29544#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0
29545#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29546//GC_CAC_ACC_CU1
29547#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0
29548#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29549//GC_CAC_ACC_CU2
29550#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0
29551#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29552//GC_CAC_ACC_CU3
29553#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0
29554#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29555//GC_CAC_ACC_CU4
29556#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0
29557#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29558//GC_CAC_OVRD_BCI
29559#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0
29560#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2
29561#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L
29562#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL
29563//GC_CAC_OVRD_CB
29564#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0
29565#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4
29566#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL
29567#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L
29568//GC_CAC_OVRD_CP
29569#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0
29570#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3
29571#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L
29572#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L
29573//GC_CAC_OVRD_DB
29574#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0
29575#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4
29576#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL
29577#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L
29578//GC_CAC_OVRD_GDS
29579#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0
29580#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4
29581#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL
29582#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L
29583//GC_CAC_OVRD_IA
29584#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0
29585#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1
29586#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L
29587#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L
29588//GC_CAC_OVRD_LDS
29589#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0
29590#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4
29591#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL
29592#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L
29593//GC_CAC_OVRD_PA
29594#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0
29595#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2
29596#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L
29597#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL
29598//GC_CAC_OVRD_PC
29599#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0
29600#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1
29601#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L
29602#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L
29603//GC_CAC_OVRD_SC
29604#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0
29605#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1
29606#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L
29607#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L
29608//GC_CAC_OVRD_SPI
29609#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0
29610#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6
29611#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL
29612#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L
29613//GC_CAC_OVRD_CU
29614#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0
29615#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1
29616#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L
29617#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L
29618//GC_CAC_OVRD_SQ
29619#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0
29620#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9
29621#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL
29622#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L
29623//GC_CAC_OVRD_SX
29624#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0
29625#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1
29626#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L
29627#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L
29628//GC_CAC_OVRD_SXRB
29629#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0
29630#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1
29631#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L
29632#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L
29633//GC_CAC_OVRD_TA
29634#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0
29635#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1
29636#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L
29637#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L
29638//GC_CAC_OVRD_TCC
29639#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0
29640#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5
29641#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL
29642#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L
29643//GC_CAC_OVRD_TCP
29644#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0
29645#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5
29646#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL
29647#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L
29648//GC_CAC_OVRD_TD
29649#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0
29650#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6
29651#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL
29652#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L
29653//GC_CAC_OVRD_VGT
29654#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0
29655#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3
29656#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L
29657#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L
29658//GC_CAC_OVRD_WD
29659#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0
29660#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1
29661#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L
29662#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L
29663//GC_CAC_ACC_BCI1
29664#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0
29665#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29666//GC_CAC_WEIGHT_UTCL2_ATCL2_2
29667#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0
29668#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL
29669//GC_CAC_WEIGHT_UTCL2_ROUTER_0
29670#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0
29671#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10
29672#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL
29673#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L
29674//GC_CAC_WEIGHT_UTCL2_ROUTER_1
29675#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0
29676#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10
29677#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL
29678#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L
29679//GC_CAC_WEIGHT_UTCL2_ROUTER_2
29680#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0
29681#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10
29682#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL
29683#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L
29684//GC_CAC_WEIGHT_UTCL2_ROUTER_3
29685#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0
29686#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10
29687#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL
29688#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L
29689//GC_CAC_WEIGHT_UTCL2_ROUTER_4
29690#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0
29691#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10
29692#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL
29693#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L
29694//GC_CAC_WEIGHT_UTCL2_VML2_0
29695#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0
29696#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10
29697#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL
29698#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L
29699//GC_CAC_WEIGHT_UTCL2_VML2_1
29700#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0
29701#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10
29702#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL
29703#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L
29704//GC_CAC_WEIGHT_UTCL2_VML2_2
29705#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0
29706#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL
29707//GC_CAC_ACC_UTCL2_ATCL24
29708#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0
29709#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29710//GC_CAC_ACC_UTCL2_ROUTER0
29711#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0
29712#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29713//GC_CAC_ACC_UTCL2_ROUTER1
29714#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0
29715#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29716//GC_CAC_ACC_UTCL2_ROUTER2
29717#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0
29718#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29719//GC_CAC_ACC_UTCL2_ROUTER3
29720#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0
29721#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29722//GC_CAC_ACC_UTCL2_ROUTER4
29723#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0
29724#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29725//GC_CAC_ACC_UTCL2_ROUTER5
29726#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0
29727#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29728//GC_CAC_ACC_UTCL2_ROUTER6
29729#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0
29730#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29731//GC_CAC_ACC_UTCL2_ROUTER7
29732#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0
29733#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29734//GC_CAC_ACC_UTCL2_ROUTER8
29735#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0
29736#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29737//GC_CAC_ACC_UTCL2_ROUTER9
29738#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0
29739#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29740//GC_CAC_ACC_UTCL2_VML20
29741#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0
29742#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29743//GC_CAC_ACC_UTCL2_VML21
29744#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0
29745#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29746//GC_CAC_ACC_UTCL2_VML22
29747#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0
29748#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29749//GC_CAC_ACC_UTCL2_VML23
29750#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0
29751#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29752//GC_CAC_ACC_UTCL2_VML24
29753#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0
29754#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29755//GC_CAC_OVRD_UTCL2_ROUTER
29756#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0
29757#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa
29758#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL
29759#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L
29760//GC_CAC_OVRD_UTCL2_VML2
29761#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0
29762#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5
29763#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL
29764#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L
29765//GC_CAC_WEIGHT_UTCL2_WALKER_0
29766#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0
29767#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10
29768#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL
29769#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L
29770//GC_CAC_WEIGHT_UTCL2_WALKER_1
29771#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0
29772#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10
29773#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL
29774#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L
29775//GC_CAC_WEIGHT_UTCL2_WALKER_2
29776#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0
29777#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL
29778//GC_CAC_ACC_UTCL2_WALKER0
29779#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0
29780#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29781//GC_CAC_ACC_UTCL2_WALKER1
29782#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0
29783#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29784//GC_CAC_ACC_UTCL2_WALKER2
29785#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0
29786#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29787//GC_CAC_ACC_UTCL2_WALKER3
29788#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0
29789#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29790//GC_CAC_ACC_UTCL2_WALKER4
29791#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0
29792#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29793//GC_CAC_OVRD_UTCL2_WALKER
29794#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0
29795#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5
29796#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL
29797#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L
29798//PCC_STALL_PATTERN_1_2
29799#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0
29800#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10
29801#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL
29802#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L
29803//PCC_STALL_PATTERN_3_4
29804#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0
29805#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10
29806#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL
29807#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L
29808//PCC_STALL_PATTERN_5_6
29809#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0
29810#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10
29811#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL
29812#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L
29813//PCC_STALL_PATTERN_7
29814#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0
29815#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL
29816//PCC_THROT_REINCR_FIRST_PATN_1_8
29817#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT 0x0
29818#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT 0x4
29819#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT 0x8
29820#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT 0xc
29821#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT 0x10
29822#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT 0x14
29823#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT 0x18
29824#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT 0x1c
29825#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK 0x00000007L
29826#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK 0x00000070L
29827#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK 0x00000700L
29828#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK 0x00007000L
29829#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK 0x00070000L
29830#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK 0x00700000L
29831#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK 0x07000000L
29832#define PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK 0x70000000L
29833//PCC_THROT_REINCR_FIRST_PATN_9_16
29834#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT 0x0
29835#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT 0x4
29836#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT 0x8
29837#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT 0xc
29838#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT 0x10
29839#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT 0x14
29840#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT 0x18
29841#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT 0x1c
29842#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK 0x00000007L
29843#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK 0x00000070L
29844#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK 0x00000700L
29845#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK 0x00007000L
29846#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK 0x00070000L
29847#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK 0x00700000L
29848#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK 0x07000000L
29849#define PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK 0x70000000L
29850//PCC_THROT_REINCR_FIRST_PATN_17_20
29851#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT 0x0
29852#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT 0x4
29853#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT 0x8
29854#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT 0xc
29855#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK 0x00000007L
29856#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK 0x00000070L
29857#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK 0x00000700L
29858#define PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK 0x00007000L
29859//PCC_THROT_DECR_FIRST_PATN_1_4
29860#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT 0x0
29861#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT 0x8
29862#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT 0x10
29863#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT 0x18
29864#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK 0x0000001FL
29865#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK 0x00001F00L
29866#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK 0x001F0000L
29867#define PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK 0x1F000000L
29868//PCC_THROT_DECR_FIRST_PATN_5_7
29869#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT 0x0
29870#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT 0x8
29871#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT 0x10
29872#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK 0x0000001FL
29873#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK 0x00001F00L
29874#define PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK 0x001F0000L
29875
29876
29877// addressBlock: secacind
29878//SE_CAC_CNTL
29879#define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0
29880#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1
29881#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11
29882#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17
29883#define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L
29884#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL
29885#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L
29886#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L
29887//SE_CAC_OVR_SEL
29888#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0
29889#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL
29890//SE_CAC_OVR_VAL
29891#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0
29892#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL
29893
29894
29895// addressBlock: sqind
29896//SQ_DEBUG_STS_GLOBAL
29897#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
29898#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
29899#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
29900#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
29901#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
29902#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
29903#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
29904#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
29905#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
29906#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
29907#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
29908#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
29909#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
29910#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
29911#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
29912#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
29913#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
29914#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
29915#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
29916#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
29917//SQ_DEBUG_STS_LOCAL
29918#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L
29919#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000
29920#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L
29921#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004
29922//SQ_WAVE_MODE
29923#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
29924#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
29925#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
29926#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
29927#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
29928#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
29929#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
29930#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17
29931#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18
29932#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19
29933#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a
29934#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
29935#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
29936#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
29937#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL
29938#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L
29939#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L
29940#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L
29941#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L
29942#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x00000800L
29943#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L
29944#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L
29945#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L
29946#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L
29947#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L
29948#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L
29949#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L
29950#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L
29951//SQ_WAVE_STATUS
29952#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
29953#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
29954#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
29955#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
29956#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
29957#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
29958#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
29959#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
29960#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
29961#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
29962#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
29963#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
29964#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
29965#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
29966#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
29967#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
29968#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
29969#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
29970#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
29971#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
29972#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
29973#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17
29974#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
29975#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L
29976#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L
29977#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L
29978#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L
29979#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L
29980#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L
29981#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L
29982#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L
29983#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L
29984#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L
29985#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L
29986#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L
29987#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L
29988#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L
29989#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L
29990#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L
29991#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L
29992#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L
29993#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L
29994#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L
29995#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L
29996#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L
29997#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L
29998//SQ_WAVE_TRAPSTS
29999#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
30000#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
30001#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb
30002#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc
30003#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
30004#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c
30005#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
30006#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL
30007#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L
30008#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L
30009#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L
30010#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L
30011#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L
30012#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L
30013//SQ_WAVE_HW_ID
30014#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
30015#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
30016#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
30017#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
30018#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
30019#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
30020#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
30021#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
30022#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
30023#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
30024#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
30025#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL
30026#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L
30027#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L
30028#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L
30029#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L
30030#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L
30031#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L
30032#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L
30033#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L
30034#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L
30035#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L
30036//SQ_WAVE_GPR_ALLOC
30037#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
30038#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
30039#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
30040#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
30041#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL
30042#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L
30043#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L
30044#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L
30045//SQ_WAVE_LDS_ALLOC
30046#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
30047#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
30048#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL
30049#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L
30050//SQ_WAVE_IB_STS
30051#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
30052#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
30053#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
30054#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
30055#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
30056#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
30057#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16
30058#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL
30059#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L
30060#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L
30061#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L
30062#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L
30063#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L
30064#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L
30065//SQ_WAVE_PC_LO
30066#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
30067#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL
30068//SQ_WAVE_PC_HI
30069#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
30070#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL
30071//SQ_WAVE_INST_DW0
30072#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
30073#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL
30074//SQ_WAVE_INST_DW1
30075#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
30076#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL
30077//SQ_WAVE_IB_DBG0
30078#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
30079#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
30080#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
30081#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
30082#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
30083#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
30084#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
30085#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
30086#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
30087#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
30088#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
30089#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
30090#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f
30091#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L
30092#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L
30093#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L
30094#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L
30095#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L
30096#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L
30097#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L
30098#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L
30099#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L
30100#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L
30101#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L
30102#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L
30103#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L
30104//SQ_WAVE_IB_DBG1
30105#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
30106#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
30107#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
30108#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
30109#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb
30110#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12
30111#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19
30112#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L
30113#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L
30114#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L
30115#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L
30116#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L
30117#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L
30118#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L
30119//SQ_WAVE_FLUSH_IB
30120#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0
30121#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL
30122//SQ_WAVE_TTMP0
30123#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
30124#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL
30125//SQ_WAVE_TTMP1
30126#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
30127#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL
30128//SQ_WAVE_TTMP2
30129#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
30130#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL
30131//SQ_WAVE_TTMP3
30132#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
30133#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL
30134//SQ_WAVE_TTMP4
30135#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
30136#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL
30137//SQ_WAVE_TTMP5
30138#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
30139#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL
30140//SQ_WAVE_TTMP6
30141#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
30142#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL
30143//SQ_WAVE_TTMP7
30144#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
30145#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL
30146//SQ_WAVE_TTMP8
30147#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
30148#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL
30149//SQ_WAVE_TTMP9
30150#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
30151#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL
30152//SQ_WAVE_TTMP10
30153#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
30154#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL
30155//SQ_WAVE_TTMP11
30156#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
30157#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL
30158//SQ_WAVE_TTMP12
30159#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0
30160#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL
30161//SQ_WAVE_TTMP13
30162#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0
30163#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL
30164//SQ_WAVE_TTMP14
30165#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0
30166#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL
30167//SQ_WAVE_TTMP15
30168#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0
30169#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL
30170//SQ_WAVE_M0
30171#define SQ_WAVE_M0__M0__SHIFT 0x0
30172#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL
30173//SQ_WAVE_EXEC_LO
30174#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
30175#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL
30176//SQ_WAVE_EXEC_HI
30177#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
30178#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL
30179//SQ_INTERRUPT_WORD_AUTO_CTXID
30180#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0
30181#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1
30182#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2
30183#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3
30184#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4
30185#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5
30186#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6
30187#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7
30188#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
30189#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18
30190#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a
30191#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L
30192#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L
30193#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L
30194#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L
30195#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L
30196#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L
30197#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L
30198#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L
30199#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L
30200#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L
30201#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L
30202//SQ_INTERRUPT_WORD_AUTO_HI
30203#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8
30204#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa
30205#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L
30206#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L
30207//SQ_INTERRUPT_WORD_AUTO_LO
30208#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0
30209#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1
30210#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
30211#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3
30212#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4
30213#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5
30214#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6
30215#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7
30216#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8
30217#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L
30218#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L
30219#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L
30220#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L
30221#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L
30222#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L
30223#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L
30224#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L
30225#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L
30226//SQ_INTERRUPT_WORD_CMN_CTXID
30227#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18
30228#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a
30229#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L
30230#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L
30231//SQ_INTERRUPT_WORD_CMN_HI
30232#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8
30233#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa
30234#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L
30235#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L
30236//SQ_INTERRUPT_WORD_WAVE_CTXID
30237#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0
30238#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc
30239#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd
30240#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe
30241#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12
30242#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14
30243#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18
30244#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a
30245#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL
30246#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L
30247#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L
30248#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L
30249#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L
30250#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L
30251#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L
30252#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L
30253//SQ_INTERRUPT_WORD_WAVE_HI
30254#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0
30255#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4
30256#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8
30257#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa
30258#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL
30259#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L
30260#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L
30261#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L
30262//SQ_INTERRUPT_WORD_WAVE_LO
30263#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0
30264#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18
30265#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19
30266#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a
30267#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e
30268#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL
30269#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L
30270#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L
30271#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L
30272#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L
30273
30274
30275// addressBlock: didtind
30276//DIDT_SQ_CTRL0
30277#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
30278#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
30279#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
30280#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
30281#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
30282#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
30283#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
30284#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
30285#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
30286#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
30287#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
30288#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
30289#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
30290#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
30291#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
30292#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
30293#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
30294#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
30295#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
30296#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
30297#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
30298#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
30299#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
30300#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
30301#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
30302#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
30303//DIDT_SQ_CTRL2
30304#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
30305#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
30306#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
30307#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
30308#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
30309#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
30310//DIDT_SQ_STALL_CTRL
30311#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
30312#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
30313#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
30314#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
30315#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
30316#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
30317#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
30318#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
30319//DIDT_SQ_TUNING_CTRL
30320#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
30321#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
30322#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
30323#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
30324//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
30325#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
30326#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
30327//DIDT_SQ_CTRL3
30328#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
30329#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
30330#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
30331#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30332#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
30333#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
30334#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
30335#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
30336#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
30337#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
30338#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
30339#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
30340#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
30341#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
30342#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
30343#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30344#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
30345#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
30346#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
30347#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
30348#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
30349#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
30350#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
30351#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
30352//DIDT_SQ_STALL_PATTERN_1_2
30353#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
30354#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
30355#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
30356#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
30357//DIDT_SQ_STALL_PATTERN_3_4
30358#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
30359#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
30360#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
30361#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
30362//DIDT_SQ_STALL_PATTERN_5_6
30363#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
30364#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
30365#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
30366#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
30367//DIDT_SQ_STALL_PATTERN_7
30368#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
30369#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
30370//DIDT_SQ_MPD_SCALE_FACTOR
30371#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
30372#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
30373#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
30374#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
30375#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
30376#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
30377#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
30378#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
30379#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
30380#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
30381#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
30382#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
30383#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
30384#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
30385#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
30386#define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
30387//DIDT_SQ_THROTTLE_CNTL0
30388#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
30389#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
30390#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
30391#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
30392#define DIDT_SQ_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
30393#define DIDT_SQ_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
30394#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
30395#define DIDT_SQ_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
30396//DIDT_SQ_THROTTLE_CNTL1
30397#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
30398#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
30399#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
30400#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
30401#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
30402#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
30403#define DIDT_SQ_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
30404#define DIDT_SQ_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
30405//DIDT_SQ_THROTTLE_CNTL_STATUS
30406#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
30407#define DIDT_SQ_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
30408//DIDT_SQ_WEIGHT0_3
30409#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
30410#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
30411#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
30412#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
30413#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
30414#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
30415#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
30416#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
30417//DIDT_SQ_WEIGHT4_7
30418#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
30419#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
30420#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
30421#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
30422#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
30423#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
30424#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
30425#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
30426//DIDT_SQ_WEIGHT8_11
30427#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
30428#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
30429#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
30430#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
30431#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
30432#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
30433#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
30434#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
30435//DIDT_SQ_EDC_CTRL
30436#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0
30437#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
30438#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
30439#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
30440#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30441#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
30442#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
30443#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
30444#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
30445#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
30446#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
30447#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
30448#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L
30449#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
30450#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
30451#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
30452#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30453#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
30454#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
30455#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
30456#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
30457#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
30458#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
30459#define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
30460//DIDT_SQ_THROTTLE_CTRL
30461#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
30462#define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
30463//DIDT_SQ_EDC_STALL_PATTERN_1_2
30464#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
30465#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
30466#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
30467#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
30468//DIDT_SQ_EDC_STALL_PATTERN_3_4
30469#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
30470#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
30471#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
30472#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
30473//DIDT_SQ_EDC_STALL_PATTERN_5_6
30474#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
30475#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
30476#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
30477#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
30478//DIDT_SQ_EDC_STALL_PATTERN_7
30479#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
30480#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
30481//DIDT_SQ_EDC_STALL_DELAY_1
30482#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0
30483#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x7
30484#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xe
30485#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x15
30486#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000007FL
30487#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00003F80L
30488#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x001FC000L
30489#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x0FE00000L
30490//DIDT_SQ_EDC_STALL_DELAY_2
30491#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0
30492#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000007FL
30493//DIDT_DB_CTRL0
30494#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
30495#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1
30496#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
30497#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
30498#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
30499#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
30500#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
30501#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
30502#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
30503#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
30504#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
30505#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
30506#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
30507#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
30508#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L
30509#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
30510#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
30511#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
30512#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
30513#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
30514#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
30515#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
30516#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
30517#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
30518#define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
30519#define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
30520//DIDT_DB_CTRL2
30521#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
30522#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
30523#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
30524#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
30525#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
30526#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
30527//DIDT_DB_STALL_CTRL
30528#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
30529#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
30530#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
30531#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
30532#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
30533#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
30534#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
30535#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
30536//DIDT_DB_TUNING_CTRL
30537#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
30538#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
30539#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
30540#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
30541//DIDT_DB_STALL_AUTO_RELEASE_CTRL
30542#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
30543#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
30544//DIDT_DB_CTRL3
30545#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
30546#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
30547#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2
30548#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30549#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
30550#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
30551#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
30552#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
30553#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
30554#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
30555#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
30556#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
30557#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
30558#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
30559#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
30560#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30561#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
30562#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
30563#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
30564#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
30565#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
30566#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
30567#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
30568#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
30569//DIDT_DB_STALL_PATTERN_1_2
30570#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
30571#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
30572#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
30573#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
30574//DIDT_DB_STALL_PATTERN_3_4
30575#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
30576#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
30577#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
30578#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
30579//DIDT_DB_STALL_PATTERN_5_6
30580#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
30581#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
30582#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
30583#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
30584//DIDT_DB_STALL_PATTERN_7
30585#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
30586#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
30587//DIDT_DB_MPD_SCALE_FACTOR
30588#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
30589#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
30590#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
30591#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
30592#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
30593#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
30594#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
30595#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
30596#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
30597#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
30598#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
30599#define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
30600#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
30601#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
30602#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
30603#define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
30604//DIDT_DB_THROTTLE_CNTL0
30605#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
30606#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
30607#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
30608#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
30609#define DIDT_DB_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
30610#define DIDT_DB_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
30611#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
30612#define DIDT_DB_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
30613//DIDT_DB_THROTTLE_CNTL1
30614#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
30615#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
30616#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
30617#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
30618#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
30619#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
30620#define DIDT_DB_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
30621#define DIDT_DB_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
30622//DIDT_DB_THROTTLE_CNTL_STATUS
30623#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
30624#define DIDT_DB_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
30625//DIDT_DB_WEIGHT0_3
30626#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
30627#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
30628#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
30629#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
30630#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
30631#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
30632#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
30633#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
30634//DIDT_DB_WEIGHT4_7
30635#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
30636#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
30637#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
30638#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
30639#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
30640#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
30641#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
30642#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
30643//DIDT_DB_WEIGHT8_11
30644#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
30645#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
30646#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
30647#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
30648#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
30649#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
30650#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
30651#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
30652//DIDT_DB_EDC_CTRL
30653#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0
30654#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
30655#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
30656#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
30657#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30658#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
30659#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
30660#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
30661#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
30662#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
30663#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
30664#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
30665#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L
30666#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
30667#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
30668#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
30669#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30670#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
30671#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
30672#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
30673#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
30674#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
30675#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
30676#define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
30677//DIDT_DB_THROTTLE_CTRL
30678#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
30679#define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
30680//DIDT_DB_EDC_STALL_PATTERN_1_2
30681#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
30682#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
30683#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
30684#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
30685//DIDT_DB_EDC_STALL_PATTERN_3_4
30686#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
30687#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
30688#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
30689#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
30690//DIDT_DB_EDC_STALL_PATTERN_5_6
30691#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
30692#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
30693#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
30694#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
30695//DIDT_DB_EDC_STALL_PATTERN_7
30696#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
30697#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
30698//DIDT_DB_EDC_STALL_DELAY_1
30699#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0
30700#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x5
30701#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000001FL
30702#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x000003E0L
30703//DIDT_TD_CTRL0
30704#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
30705#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1
30706#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
30707#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
30708#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
30709#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
30710#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
30711#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
30712#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
30713#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
30714#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
30715#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
30716#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
30717#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
30718#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L
30719#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
30720#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
30721#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
30722#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
30723#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
30724#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
30725#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
30726#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
30727#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
30728#define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
30729#define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
30730//DIDT_TD_CTRL2
30731#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
30732#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
30733#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
30734#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
30735#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
30736#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
30737//DIDT_TD_STALL_CTRL
30738#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
30739#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
30740#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
30741#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
30742#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
30743#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
30744#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
30745#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
30746//DIDT_TD_TUNING_CTRL
30747#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
30748#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
30749#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
30750#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
30751//DIDT_TD_STALL_AUTO_RELEASE_CTRL
30752#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
30753#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
30754//DIDT_TD_CTRL3
30755#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
30756#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
30757#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2
30758#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30759#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
30760#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
30761#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
30762#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
30763#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
30764#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
30765#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
30766#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
30767#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
30768#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
30769#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
30770#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30771#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
30772#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
30773#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
30774#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
30775#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
30776#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
30777#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
30778#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
30779//DIDT_TD_STALL_PATTERN_1_2
30780#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
30781#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
30782#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
30783#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
30784//DIDT_TD_STALL_PATTERN_3_4
30785#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
30786#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
30787#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
30788#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
30789//DIDT_TD_STALL_PATTERN_5_6
30790#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
30791#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
30792#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
30793#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
30794//DIDT_TD_STALL_PATTERN_7
30795#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
30796#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
30797//DIDT_TD_MPD_SCALE_FACTOR
30798#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
30799#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
30800#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
30801#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
30802#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
30803#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
30804#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
30805#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
30806#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
30807#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
30808#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
30809#define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
30810#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
30811#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
30812#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
30813#define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
30814//DIDT_TD_THROTTLE_CNTL0
30815#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
30816#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
30817#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
30818#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
30819#define DIDT_TD_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
30820#define DIDT_TD_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
30821#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
30822#define DIDT_TD_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
30823//DIDT_TD_THROTTLE_CNTL1
30824#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
30825#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
30826#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
30827#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
30828#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
30829#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
30830#define DIDT_TD_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
30831#define DIDT_TD_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
30832//DIDT_TD_THROTTLE_CNTL_STATUS
30833#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
30834#define DIDT_TD_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
30835//DIDT_TD_WEIGHT0_3
30836#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
30837#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
30838#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
30839#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
30840#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
30841#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
30842#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
30843#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
30844//DIDT_TD_WEIGHT4_7
30845#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
30846#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
30847#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
30848#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
30849#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
30850#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
30851#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
30852#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
30853//DIDT_TD_WEIGHT8_11
30854#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
30855#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
30856#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
30857#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
30858#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
30859#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
30860#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
30861#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
30862//DIDT_TD_EDC_CTRL
30863#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0
30864#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
30865#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
30866#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
30867#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30868#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
30869#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
30870#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
30871#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
30872#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
30873#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
30874#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
30875#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L
30876#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
30877#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
30878#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
30879#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30880#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
30881#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
30882#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
30883#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
30884#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
30885#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
30886#define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
30887//DIDT_TD_THROTTLE_CTRL
30888#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
30889#define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
30890//DIDT_TD_EDC_STALL_PATTERN_1_2
30891#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
30892#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
30893#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
30894#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
30895//DIDT_TD_EDC_STALL_PATTERN_3_4
30896#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
30897#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
30898#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
30899#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
30900//DIDT_TD_EDC_STALL_PATTERN_5_6
30901#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
30902#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
30903#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
30904#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
30905//DIDT_TD_EDC_STALL_PATTERN_7
30906#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
30907#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
30908//DIDT_TD_EDC_STALL_DELAY_1
30909#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0
30910#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x7
30911#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xe
30912#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x15
30913#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000007FL
30914#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00003F80L
30915#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x001FC000L
30916#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x0FE00000L
30917//DIDT_TD_EDC_STALL_DELAY_2
30918#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0
30919#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000007FL
30920//DIDT_TCP_CTRL0
30921#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
30922#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1
30923#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
30924#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
30925#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
30926#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
30927#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
30928#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
30929#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
30930#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
30931#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
30932#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
30933#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
30934#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
30935#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L
30936#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
30937#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
30938#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
30939#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
30940#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
30941#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
30942#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
30943#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
30944#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
30945#define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
30946#define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
30947//DIDT_TCP_CTRL2
30948#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
30949#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
30950#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
30951#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
30952#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
30953#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
30954//DIDT_TCP_STALL_CTRL
30955#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
30956#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
30957#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
30958#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
30959#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
30960#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
30961#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
30962#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
30963//DIDT_TCP_TUNING_CTRL
30964#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
30965#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
30966#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
30967#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
30968//DIDT_TCP_STALL_AUTO_RELEASE_CTRL
30969#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
30970#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
30971//DIDT_TCP_CTRL3
30972#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
30973#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
30974#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2
30975#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
30976#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
30977#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
30978#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
30979#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
30980#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
30981#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
30982#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
30983#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
30984#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
30985#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
30986#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
30987#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
30988#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
30989#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
30990#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
30991#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
30992#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
30993#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
30994#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
30995#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
30996//DIDT_TCP_STALL_PATTERN_1_2
30997#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
30998#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
30999#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
31000#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
31001//DIDT_TCP_STALL_PATTERN_3_4
31002#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
31003#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
31004#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL
31005#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L
31006//DIDT_TCP_STALL_PATTERN_5_6
31007#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0
31008#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10
31009#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL
31010#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L
31011//DIDT_TCP_STALL_PATTERN_7
31012#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0
31013#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL
31014//DIDT_TCP_MPD_SCALE_FACTOR
31015#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0
31016#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4
31017#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8
31018#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc
31019#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10
31020#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14
31021#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18
31022#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c
31023#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL
31024#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L
31025#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L
31026#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L
31027#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L
31028#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L
31029#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L
31030#define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L
31031//DIDT_TCP_THROTTLE_CNTL0
31032#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN__SHIFT 0x0
31033#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1
31034#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2
31035#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd
31036#define DIDT_TCP_THROTTLE_CNTL0__DIDT_THROTTLE_CNTL_EN_MASK 0x00000001L
31037#define DIDT_TCP_THROTTLE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L
31038#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL
31039#define DIDT_TCP_THROTTLE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L
31040//DIDT_TCP_THROTTLE_CNTL1
31041#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0
31042#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5
31043#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa
31044#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf
31045#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL
31046#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L
31047#define DIDT_TCP_THROTTLE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L
31048#define DIDT_TCP_THROTTLE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L
31049//DIDT_TCP_THROTTLE_CNTL_STATUS
31050#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE__SHIFT 0x0
31051#define DIDT_TCP_THROTTLE_CNTL_STATUS__DIDT_THROTTLE_CNTL_FSM_STATE_MASK 0x00000003L
31052//DIDT_TCP_WEIGHT0_3
31053#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
31054#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
31055#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
31056#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
31057#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL
31058#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L
31059#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L
31060#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L
31061//DIDT_TCP_WEIGHT4_7
31062#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
31063#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
31064#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
31065#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
31066#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL
31067#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L
31068#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L
31069#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L
31070//DIDT_TCP_WEIGHT8_11
31071#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
31072#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
31073#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
31074#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
31075#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL
31076#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L
31077#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L
31078#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L
31079//DIDT_TCP_EDC_CTRL
31080#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0
31081#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1
31082#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2
31083#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3
31084#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
31085#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9
31086#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11
31087#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12
31088#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13
31089#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15
31090#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16
31091#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17
31092#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L
31093#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L
31094#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L
31095#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L
31096#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
31097#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L
31098#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L
31099#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L
31100#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L
31101#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L
31102#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L
31103#define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L
31104//DIDT_TCP_THROTTLE_CTRL
31105#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1
31106#define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L
31107//DIDT_TCP_EDC_STALL_PATTERN_1_2
31108#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0
31109#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10
31110#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL
31111#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L
31112//DIDT_TCP_EDC_STALL_PATTERN_3_4
31113#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0
31114#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10
31115#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL
31116#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L
31117//DIDT_TCP_EDC_STALL_PATTERN_5_6
31118#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0
31119#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10
31120#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL
31121#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L
31122//DIDT_TCP_EDC_STALL_PATTERN_7
31123#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0
31124#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL
31125//DIDT_TCP_EDC_STALL_DELAY_1
31126#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0
31127#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x7
31128#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xe
31129#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x15
31130#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000007FL
31131#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00003F80L
31132#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x001FC000L
31133#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x0FE00000L
31134//DIDT_TCP_EDC_STALL_DELAY_2
31135#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0
31136#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000007FL
31137//DIDT_SQ_STALL_EVENT_COUNTER
31138#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
31139#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
31140//DIDT_DB_STALL_EVENT_COUNTER
31141#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
31142#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
31143//DIDT_TD_STALL_EVENT_COUNTER
31144#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
31145#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
31146//DIDT_TCP_STALL_EVENT_COUNTER
31147#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
31148#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
31149//DIDT_DBR_STALL_EVENT_COUNTER
31150#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0
31151#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL
31152//DIDT_SQ_CTRL1
31153#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
31154#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
31155#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL
31156#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L
31157//DIDT_SQ_EDC_THRESHOLD
31158#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
31159#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
31160//DIDT_DB_CTRL1
31161#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
31162#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
31163#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL
31164#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L
31165//DIDT_DB_EDC_THRESHOLD
31166#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
31167#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
31168//DIDT_TD_CTRL1
31169#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
31170#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
31171#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL
31172#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L
31173//DIDT_TD_EDC_THRESHOLD
31174#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
31175#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
31176//DIDT_TCP_CTRL1
31177#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
31178#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
31179#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL
31180#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L
31181//DIDT_TCP_EDC_THRESHOLD
31182#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0
31183#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL
31184
31185
31186#endif
31187

source code of linux/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h