1/*
2 *
3 * Copyright (C) 2016 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef GFX_6_0_SH_MASK_H
24#define GFX_6_0_SH_MASK_H
25
26#define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27#define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
36#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
37#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
38#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
39#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
40#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L
41#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
42#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L
43#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x0000001e
44#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
45#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
46#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
47#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
48#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
49#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
50#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
51#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
52#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
53#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
54#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
55#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
56#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
57#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
58#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L
59#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
60#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L
61#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x0000001e
62#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
63#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
64#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
65#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
66#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
67#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
68#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
69#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
70#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
71#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
72#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
73#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
74#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
75#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
76#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L
77#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
78#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L
79#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x0000001e
80#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
81#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
82#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
83#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
84#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
85#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
86#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
87#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
88#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
89#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
90#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
91#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
92#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
93#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
94#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L
95#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
96#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L
97#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x0000001e
98#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
99#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
100#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
101#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
102#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
103#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
104#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
105#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
106#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
107#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
108#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
109#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
110#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
111#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
112#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L
113#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
114#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L
115#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x0000001e
116#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
117#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
118#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
119#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
120#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
121#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
122#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
123#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
124#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
125#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
126#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
127#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
128#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
129#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
130#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L
131#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
132#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L
133#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x0000001e
134#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
135#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
136#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
137#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
138#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
139#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
140#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
141#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
142#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
143#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
144#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
145#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
146#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
147#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
148#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L
149#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
150#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L
151#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x0000001e
152#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
153#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
154#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
155#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
156#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
157#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
158#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
159#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
160#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
161#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
162#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001f00L
163#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x00000008
164#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001fL
165#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x00000000
166#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L
167#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x0000001f
168#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L
169#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x0000001e
170#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L
171#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x0000001d
172#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffffL
173#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x00000000
174#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffffL
175#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x00000000
176#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffffL
177#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x00000000
178#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffffL
179#define CB_BLEND_RED__BLEND_RED__SHIFT 0x00000000
180#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
181#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
182#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000fL
183#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x00000000
184#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
185#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
186#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
187#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
188#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
189#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
190#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
191#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
192#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
193#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
194#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
195#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
196#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
197#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
198#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
199#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
200#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
201#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
202#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
203#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
204#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
205#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
206#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
207#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
208#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
209#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
210#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
211#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
212#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffffL
213#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x00000000
214#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
215#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
216#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
217#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
218#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffffL
219#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x00000000
220#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
221#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
222#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffffL
223#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x00000000
224#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
225#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
226#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L
227#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x00000010
228#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L
229#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0x0000000f
230#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
231#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
232#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
233#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
234#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
235#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
236#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L
237#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0x0000000e
238#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L
239#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0x0000000b
240#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L
241#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x00000000
242#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L
243#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0x0000000d
244#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
245#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
246#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007cL
247#define CB_COLOR0_INFO__FORMAT__SHIFT 0x00000002
248#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L
249#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x00000007
250#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L
251#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x00000008
252#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L
253#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x00000012
254#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L
255#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
256#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
257#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
258#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007ffL
259#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x00000000
260#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003fffffL
261#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x00000000
262#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00ffe000L
263#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0x0000000d
264#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007ffL
265#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x00000000
266#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
267#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
268#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
269#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
270#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
271#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
272#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
273#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
274#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
275#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
276#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
277#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
278#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffffL
279#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x00000000
280#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
281#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
282#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
283#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
284#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffffL
285#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x00000000
286#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
287#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
288#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffffL
289#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x00000000
290#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
291#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
292#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L
293#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x00000010
294#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L
295#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0x0000000f
296#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
297#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
298#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
299#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
300#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
301#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
302#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L
303#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0x0000000e
304#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L
305#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0x0000000b
306#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L
307#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x00000000
308#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L
309#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0x0000000d
310#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
311#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
312#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007cL
313#define CB_COLOR1_INFO__FORMAT__SHIFT 0x00000002
314#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L
315#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x00000007
316#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L
317#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x00000008
318#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L
319#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x00000012
320#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L
321#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
322#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
323#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
324#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007ffL
325#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x00000000
326#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003fffffL
327#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x00000000
328#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00ffe000L
329#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0x0000000d
330#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007ffL
331#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x00000000
332#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
333#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
334#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
335#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
336#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
337#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
338#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
339#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
340#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
341#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
342#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
343#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
344#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffffL
345#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x00000000
346#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
347#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
348#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
349#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
350#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffffL
351#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x00000000
352#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
353#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
354#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffffL
355#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x00000000
356#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
357#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
358#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L
359#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x00000010
360#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L
361#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0x0000000f
362#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
363#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
364#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
366#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
367#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
368#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L
369#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0x0000000e
370#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L
371#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0x0000000b
372#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L
373#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x00000000
374#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L
375#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0x0000000d
376#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
377#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
378#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007cL
379#define CB_COLOR2_INFO__FORMAT__SHIFT 0x00000002
380#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L
381#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x00000007
382#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L
383#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x00000008
384#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L
385#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x00000012
386#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L
387#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
388#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
389#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
390#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007ffL
391#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x00000000
392#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003fffffL
393#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x00000000
394#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00ffe000L
395#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0x0000000d
396#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007ffL
397#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x00000000
398#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
399#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
400#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
401#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
402#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
403#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
404#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
405#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
406#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
407#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
408#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
409#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
410#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffffL
411#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x00000000
412#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
413#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
414#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
415#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
416#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffffL
417#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x00000000
418#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
419#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
420#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffffL
421#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x00000000
422#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
423#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
424#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L
425#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x00000010
426#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L
427#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0x0000000f
428#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
429#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
430#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
431#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
432#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
433#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
434#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L
435#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0x0000000e
436#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L
437#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0x0000000b
438#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L
439#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x00000000
440#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L
441#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0x0000000d
442#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
443#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
444#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007cL
445#define CB_COLOR3_INFO__FORMAT__SHIFT 0x00000002
446#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L
447#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x00000007
448#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L
449#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x00000008
450#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L
451#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x00000012
452#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L
453#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
454#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
455#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
456#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007ffL
457#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x00000000
458#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003fffffL
459#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x00000000
460#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00ffe000L
461#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0x0000000d
462#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007ffL
463#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x00000000
464#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
465#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
466#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
467#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
468#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
469#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
470#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
471#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
472#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
473#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
474#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
475#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
476#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffffL
477#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x00000000
478#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
479#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
480#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
481#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
482#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffffL
483#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x00000000
484#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
485#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
486#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffffL
487#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x00000000
488#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
489#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
490#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L
491#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x00000010
492#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L
493#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0x0000000f
494#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
495#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
496#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
497#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
498#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
499#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
500#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L
501#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0x0000000e
502#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L
503#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0x0000000b
504#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L
505#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x00000000
506#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L
507#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0x0000000d
508#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
509#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
510#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007cL
511#define CB_COLOR4_INFO__FORMAT__SHIFT 0x00000002
512#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L
513#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x00000007
514#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L
515#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x00000008
516#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L
517#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x00000012
518#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L
519#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
520#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
521#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
522#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007ffL
523#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x00000000
524#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003fffffL
525#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x00000000
526#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00ffe000L
527#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0x0000000d
528#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007ffL
529#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x00000000
530#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
531#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
532#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
533#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
534#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
535#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
536#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
537#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
538#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
539#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
540#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
541#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
542#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffffL
543#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x00000000
544#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
545#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
546#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
547#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
548#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffffL
549#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x00000000
550#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
551#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
552#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffffL
553#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x00000000
554#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
555#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
556#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L
557#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x00000010
558#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L
559#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0x0000000f
560#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
561#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
562#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
563#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
564#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
565#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
566#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L
567#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0x0000000e
568#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L
569#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0x0000000b
570#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L
571#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x00000000
572#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L
573#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0x0000000d
574#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
575#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
576#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007cL
577#define CB_COLOR5_INFO__FORMAT__SHIFT 0x00000002
578#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L
579#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x00000007
580#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L
581#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x00000008
582#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L
583#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x00000012
584#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L
585#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
586#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
587#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
588#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007ffL
589#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x00000000
590#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003fffffL
591#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x00000000
592#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00ffe000L
593#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0x0000000d
594#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007ffL
595#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x00000000
596#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
598#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
599#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
600#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
601#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
603#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
604#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
605#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
606#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
607#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
608#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffffL
609#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x00000000
610#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
611#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
612#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
613#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
614#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffffL
615#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x00000000
616#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
617#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
618#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffffL
619#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x00000000
620#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
621#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
622#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L
623#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x00000010
624#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L
625#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0x0000000f
626#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
627#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
628#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
629#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
630#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
631#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
632#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L
633#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0x0000000e
634#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L
635#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0x0000000b
636#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L
637#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x00000000
638#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L
639#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0x0000000d
640#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
641#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
642#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007cL
643#define CB_COLOR6_INFO__FORMAT__SHIFT 0x00000002
644#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L
645#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x00000007
646#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L
647#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x00000008
648#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L
649#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x00000012
650#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L
651#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
652#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
653#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
654#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007ffL
655#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x00000000
656#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003fffffL
657#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x00000000
658#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00ffe000L
659#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0x0000000d
660#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007ffL
661#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x00000000
662#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000c00L
663#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0x0000000a
664#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003e0L
665#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x00000005
666#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L
667#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x00000011
668#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L
669#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0000000f
670#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L
671#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0x0000000c
672#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001fL
673#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x00000000
674#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffffL
675#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x00000000
676#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffffL
677#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x00000000
678#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffffL
679#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x00000000
680#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffffL
681#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x00000000
682#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003fffL
683#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x00000000
684#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffffL
685#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x00000000
686#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003fffffL
687#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x00000000
688#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L
689#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x00000010
690#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L
691#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0x0000000f
692#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L
693#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x00000017
694#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L
695#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x00000014
696#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L
697#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x00000013
698#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L
699#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0x0000000e
700#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L
701#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0x0000000b
702#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L
703#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x00000000
704#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L
705#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0x0000000d
706#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L
707#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x0000001a
708#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007cL
709#define CB_COLOR7_INFO__FORMAT__SHIFT 0x00000002
710#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L
711#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x00000007
712#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L
713#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x00000008
714#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L
715#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x00000012
716#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L
717#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x00000011
718#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000L
719#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x00000014
720#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007ffL
721#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x00000000
722#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003fffffL
723#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x00000000
724#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00ffe000L
725#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0x0000000d
726#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007ffL
727#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x00000000
728#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L
729#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x00000003
730#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L
731#define CB_COLOR_CONTROL__MODE__SHIFT 0x00000004
732#define CB_COLOR_CONTROL__ROP3_MASK 0x00ff0000L
733#define CB_COLOR_CONTROL__ROP3__SHIFT 0x00000010
734#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x00000008L
735#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x00000003
736#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x00000020L
737#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x00000005
738#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x00000010L
739#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x00000004
740#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x00000200L
741#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x00000009
742#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x00000100L
743#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x00000008
744#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x00000080L
745#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x00000007
746#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x00000400L
747#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0x0000000a
748#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x00000040L
749#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x00000006
750#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x00000002L
751#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x00000001
752#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x0007f800L
753#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0x0000000b
754#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x00000001L
755#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x00000000
756#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x00000004L
757#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x00000002
758#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x00000010L
759#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x00000004
760#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x00000008L
761#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x00000003
762#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x00000100L
763#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x00000008
764#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x00000002L
765#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x00000001
766#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x00000004L
767#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x00000002
768#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x00000020L
769#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x00000005
770#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x00000040L
771#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x00000006
772#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x00000080L
773#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x00000007
774#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x00000001L
775#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x00000000
776#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x00000010L
777#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x00000004
778#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x00000040L
779#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x00000006
780#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x00000100L
781#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x00000008
782#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x00000020L
783#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x00000005
784#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x00000008L
785#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x00000003
786#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x00000004L
787#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x00000002
788#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x00000003L
789#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x00000000
790#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x00000080L
791#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x00000007
792#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x00100000L
793#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x00000014
794#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x00400000L
795#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x00000016
796#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x00200000L
797#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x00000015
798#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x000003c0L
799#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x00000006
800#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0x000f0000L
801#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x00000010
802#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x0000003fL
803#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x00000000
804#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0x0000fc00L
805#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0x0000000a
806#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x00000008L
807#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x00000003
808#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x00000004L
809#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x00000002
810#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x00000001L
811#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x00000000
812#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x00000020L
813#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x00000005
814#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x00000002L
815#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x00000001
816#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x00000010L
817#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x00000004
818#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x00000080L
819#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x00000007
820#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x00000040L
821#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x00000006
822#define CB_DEBUG_BUS_18__NOT_USED_MASK 0x00ffffffL
823#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x00000000
824#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001f800L
825#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0000000b
826#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000L
827#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x0000001a
828#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001fL
829#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x00000000
830#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03fe0000L
831#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x00000011
832#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007e0L
833#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x00000005
834#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000ffL
835#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x00000000
836#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff800000L
837#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x00000017
838#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007f8000L
839#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0x0000000f
840#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007f00L
841#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x00000008
842#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
843#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x00000000
844#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
845#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x00000010
846#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000f000L
847#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0x0000000c
848#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000fL
849#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x00000000
850#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
851#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x00000019
852#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
853#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x0000001a
854#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
855#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x00000018
856#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
857#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x00000015
858#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
859#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x0000001b
860#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
861#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x0000001e
862#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
863#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x00000016
864#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
865#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x00000012
866#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
867#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x0000001f
868#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
869#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x00000017
870#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003c0L
871#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x00000006
872#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
873#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x00000014
874#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
875#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x00000013
876#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
877#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x0000001d
878#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
879#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x0000001c
880#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
881#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
882#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
883#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
884#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
885#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
886#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
887#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
888#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001ffL
889#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
890#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007fc00L
891#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
892#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
893#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
894#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
895#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
896#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
897#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
898#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
899#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
900#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
901#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
902#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
903#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
904#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000fL
905#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x00000000
906#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000f0L
907#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x00000004
908#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000f00L
909#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x00000008
910#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000f000L
911#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0x0000000c
912#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000f0000L
913#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x00000010
914#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00f00000L
915#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x00000014
916#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0f000000L
917#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x00000018
918#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000L
919#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x0000001c
920#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000fL
921#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x00000000
922#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000f0L
923#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x00000004
924#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000f00L
925#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x00000008
926#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000f000L
927#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0x0000000c
928#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000f0000L
929#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x00000010
930#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00f00000L
931#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x00000014
932#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0f000000L
933#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x00000018
934#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000L
935#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x0000001c
936#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L
937#define CC_GC_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001
938#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L
939#define CC_GC_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004
940#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L
941#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010
942#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
943#define CC_GC_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003
944#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
945#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
946#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000fL
947#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x00000000
948#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000f0L
949#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x00000004
950#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000f00L
951#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x00000008
952#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000f000L
953#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0x0000000c
954#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000f0000L
955#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x00000010
956#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00f00000L
957#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x00000014
958#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0f000000L
959#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x00000018
960#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000L
961#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x0000001c
962#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
963#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0x0000000c
964#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
965#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x00000014
966#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000f00L
967#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x00000008
968#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000f0000L
969#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x00000010
970#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0x000f0000L
971#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x00000010
972#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0x00f00000L
973#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x00000014
974#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0x0f000000L
975#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x00000018
976#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000L
977#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x0000001c
978#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001f00L
979#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x00000008
980#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001fL
981#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x00000000
982#define CGTS_RD_REG__READ_DATA_MASK 0x00003fffL
983#define CGTS_RD_REG__READ_DATA__SHIFT 0x00000000
984#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L
985#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x00000010
986#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L
987#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x00000016
988#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L
989#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0x0000000c
990#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000ff0L
991#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x00000004
992#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L
993#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x00000017
994#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000L
995#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x00000018
996#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000fL
997#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x00000000
998#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L
999#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x00000015
1000#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L
1001#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x00000014
1002#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000e0000L
1003#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x00000011
1004#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
1005#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
1006#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000L
1007#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x00000010
1008#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
1009#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
1010#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
1011#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
1012#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
1013#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
1014#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
1015#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
1016#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L
1017#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x0000001a
1018#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L
1019#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x00000019
1020#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L
1021#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x00000018
1022#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1023#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1024#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1025#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1026#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1027#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1028#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x00fff000L
1029#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0x0000000c
1030#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1031#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1032#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1033#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1034#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
1035#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
1036#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
1037#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
1038#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1039#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1040#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1041#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1042#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1043#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1044#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1045#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1046#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1047#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1048#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1049#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1050#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1051#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1052#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1053#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1054#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1055#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1056#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1057#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1058#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L
1059#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001d
1060#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
1061#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
1062#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1063#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1064#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1065#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1066#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
1067#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
1068#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1069#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1070#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1071#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1072#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1073#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1074#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1075#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1076#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1077#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1078#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L
1079#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x0000001e
1080#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1081#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1082#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1083#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1084#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L
1085#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0000001f
1086#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1087#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1088#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1089#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1090#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1091#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1092#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1093#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1094#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1095#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1096#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L
1097#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x0000001d
1098#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x02000000L
1099#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x00000019
1100#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L
1101#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x0000001e
1102#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L
1103#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x0000001d
1104#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L
1105#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x0000001c
1106#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L
1107#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x0000001b
1108#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x04000000L
1109#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x0000001a
1110#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
1111#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
1112#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
1113#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
1114#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1115#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1116#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1117#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1118#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1119#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1120#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1121#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1122#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1123#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1124#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
1125#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x0000001e
1126#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L
1127#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x0000001f
1128#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1129#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1130#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1131#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1132#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1133#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1134#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1135#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1136#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1137#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1138#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1139#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1140#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1141#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1142#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1143#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1144#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1145#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1146#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1147#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1148#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L
1149#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x0000001a
1150#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L
1151#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x0000001e
1152#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L
1153#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x0000001d
1154#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L
1155#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x0000001c
1156#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L
1157#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x0000001b
1158#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00fc0000L
1159#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x00000012
1160#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L
1161#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x00000018
1162#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1163#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1164#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1165#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1166#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1167#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1168#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1169#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1170#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1171#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1172#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1173#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1174#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1175#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1176#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1177#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1178#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1179#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1180#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1181#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1182#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1183#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1184#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000ff0L
1185#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x00000004
1186#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000fL
1187#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x00000000
1188#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x00fff000L
1189#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0x0000000c
1190#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L
1191#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x0000001f
1192#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L
1193#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x0000001e
1194#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L
1195#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x0000001d
1196#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L
1197#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x0000001c
1198#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L
1199#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x0000001b
1200#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L
1201#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x0000001a
1202#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L
1203#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x00000019
1204#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L
1205#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x00000018
1206#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000ff0L
1207#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x00000004
1208#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000fL
1209#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x00000000
1210#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x00fff000L
1211#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0x0000000c
1212#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L
1213#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x0000001f
1214#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L
1215#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x0000001e
1216#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L
1217#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x0000001d
1218#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L
1219#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x0000001c
1220#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L
1221#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x0000001b
1222#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L
1223#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x0000001a
1224#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L
1225#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x00000019
1226#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L
1227#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x00000018
1228#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000ff0L
1229#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x00000004
1230#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000fL
1231#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x00000000
1232#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x00fff000L
1233#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0x0000000c
1234#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L
1235#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x0000001f
1236#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L
1237#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x0000001e
1238#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L
1239#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x0000001d
1240#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L
1241#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x0000001c
1242#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L
1243#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x0000001b
1244#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L
1245#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x0000001a
1246#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L
1247#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x00000019
1248#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L
1249#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x00000018
1250#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000ff0L
1251#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x00000004
1252#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000fL
1253#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x00000000
1254#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x00fff000L
1255#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0x0000000c
1256#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L
1257#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x0000001f
1258#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L
1259#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x0000001e
1260#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L
1261#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x0000001d
1262#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L
1263#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x0000001c
1264#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L
1265#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x0000001b
1266#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L
1267#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x0000001a
1268#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L
1269#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x00000019
1270#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L
1271#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x00000018
1272#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000ff0L
1273#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x00000004
1274#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000fL
1275#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x00000000
1276#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x00fff000L
1277#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0x0000000c
1278#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L
1279#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x0000001f
1280#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L
1281#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x0000001e
1282#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L
1283#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x0000001d
1284#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L
1285#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x0000001c
1286#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L
1287#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x0000001b
1288#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L
1289#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x0000001a
1290#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L
1291#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x00000019
1292#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x01000000L
1293#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x00000018
1294#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1295#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1296#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1297#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1298#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1299#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1300#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1301#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1302#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1303#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1304#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1305#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1306#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1307#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1308#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1309#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1310#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1311#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1312#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1313#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1314#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1315#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1316#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1317#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1318#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
1319#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x0000001f
1320#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
1321#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x0000001e
1322#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
1323#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x0000001d
1324#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1325#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1326#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1327#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1328#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
1329#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x0000001a
1330#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
1331#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x00000019
1332#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1333#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1334#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L
1335#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x0000001e
1336#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x04000000L
1337#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x0000001a
1338#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L
1339#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x0000001d
1340#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000ff0L
1341#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x00000004
1342#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000fL
1343#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x00000000
1344#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L
1345#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x00000019
1346#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L
1347#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x0000001f
1348#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
1349#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x0000001c
1350#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
1351#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x0000001b
1352#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
1353#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x00000018
1354#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0x000000ffL
1355#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x00000000
1356#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x08000000L
1357#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x0000001b
1358#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000L
1359#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x0000001c
1360#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x00200000L
1361#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x00000015
1362#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x00400000L
1363#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x00000016
1364#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x00000100L
1365#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x00000008
1366#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x00001000L
1367#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0x0000000c
1368#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x00000800L
1369#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0x0000000b
1370#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x00008000L
1371#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0x0000000f
1372#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x00010000L
1373#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x00000010
1374#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000L
1375#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x0000001d
1376#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x00002000L
1377#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0x0000000d
1378#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x00004000L
1379#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0x0000000e
1380#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x00000600L
1381#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x00000009
1382#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x00020000L
1383#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x00000011
1384#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x00040000L
1385#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x00000012
1386#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000L
1387#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x0000001f
1388#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x00080000L
1389#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x00000013
1390#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x00100000L
1391#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x00000014
1392#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x00800000L
1393#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x00000017
1394#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x01000000L
1395#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x00000018
1396#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x02000000L
1397#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x00000019
1398#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x04000000L
1399#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x0000001a
1400#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000L
1401#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x0000001e
1402#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0x000000ffL
1403#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x00000000
1404#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x00000700L
1405#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x00000008
1406#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000L
1407#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x0000001c
1408#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000L
1409#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x0000001d
1410#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0x000e0000L
1411#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x00000011
1412#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x00100000L
1413#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x00000014
1414#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x0001c000L
1415#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0x0000000e
1416#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x00003800L
1417#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0x0000000b
1418#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000L
1419#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x0000001e
1420#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000L
1421#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x0000001f
1422#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x01000000L
1423#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x00000018
1424#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0x0c000000L
1425#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x0000001a
1426#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x02000000L
1427#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x00000019
1428#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x00800000L
1429#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x00000017
1430#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x00400000L
1431#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x00000016
1432#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x00200000L
1433#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x00000015
1434#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x00000007L
1435#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x00000000
1436#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x04000000L
1437#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x0000001a
1438#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000L
1439#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x0000001c
1440#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x00100000L
1441#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x00000014
1442#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x00200000L
1443#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x00000015
1444#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x08000000L
1445#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x0000001b
1446#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000L
1447#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x0000001d
1448#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x01000000L
1449#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x00000018
1450#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0x000000c0L
1451#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x00000006
1452#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x00400000L
1453#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x00000016
1454#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000L
1455#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x0000001e
1456#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000L
1457#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x0000001f
1458#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x00800000L
1459#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x00000017
1460#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x02000000L
1461#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x00000019
1462#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0x000f0000L
1463#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x00000010
1464#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0x0000f000L
1465#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0x0000000c
1466#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0x00000f00L
1467#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x00000008
1468#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x00000038L
1469#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x00000003
1470#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1471#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1472#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x00800000L
1473#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1474#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1475#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1476#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000L
1477#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1478#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0x000fc000L
1479#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0x0000000e
1480#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000L
1481#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
1482#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1483#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1484#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
1485#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1486#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1487#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1488#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x00700000L
1489#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1490#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000L
1491#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x0000001d
1492#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000L
1493#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1494#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1495#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1496#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1497#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1498#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1499#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1500#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1501#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1502#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1503#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1504#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1505#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1506#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x00800000L
1507#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1508#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1509#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1510#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000L
1511#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1512#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0x000fc000L
1513#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0x0000000e
1514#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000L
1515#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
1516#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1517#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1518#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
1519#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1520#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1521#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1522#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x00700000L
1523#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1524#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000L
1525#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x0000001d
1526#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000L
1527#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1528#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1529#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1530#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1531#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1532#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1533#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1534#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1535#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1536#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1537#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1538#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1539#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1540#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x00800000L
1541#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1542#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1543#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1544#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000L
1545#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1546#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0x000fc000L
1547#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0x0000000e
1548#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000L
1549#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
1550#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1551#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1552#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
1553#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1554#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1555#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1556#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x00700000L
1557#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1558#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000L
1559#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x0000001d
1560#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000L
1561#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1562#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1563#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1564#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1565#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1566#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1567#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1568#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1569#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1570#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1571#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1572#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x00003fffL
1573#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x00000000
1574#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x00800000L
1575#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000017
1576#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x07000000L
1577#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x00000018
1578#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000L
1579#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x0000001c
1580#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0x000fc000L
1581#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0x0000000e
1582#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000L
1583#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
1584#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x08000000L
1585#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x0000001b
1586#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
1587#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1588#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1589#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1590#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x00700000L
1591#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x00000014
1592#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000L
1593#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x0000001d
1594#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000L
1595#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x0000001e
1596#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x000007feL
1597#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x00000001
1598#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1599#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1600#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000L
1601#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x00000017
1602#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x007e0000L
1603#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x00000011
1604#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x0001f800L
1605#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0x0000000b
1606#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x00000080L
1607#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x00000007
1608#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00f00000L
1609#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000014
1610#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x00000008L
1611#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x00000003
1612#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x08000000L
1613#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x0000001b
1614#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000L
1615#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001f
1616#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x00000040L
1617#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x00000006
1618#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0x000f0000L
1619#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000010
1620#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x00000004L
1621#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x00000002
1622#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x04000000L
1623#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x0000001a
1624#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000L
1625#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001e
1626#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x00000020L
1627#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x00000005
1628#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0x0000f000L
1629#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000000c
1630#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x00000002L
1631#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x00000001
1632#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x02000000L
1633#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x00000019
1634#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000L
1635#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001d
1636#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x00000010L
1637#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x00000004
1638#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0x00000f00L
1639#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x00000008
1640#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x00000001L
1641#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x00000000
1642#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x01000000L
1643#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x00000018
1644#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000L
1645#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x0000001c
1646#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0x000000ffL
1647#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x00000000
1648#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x0003e000L
1649#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0x0000000d
1650#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x00001f00L
1651#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x00000008
1652#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0x00c00000L
1653#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x00000016
1654#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0x000c0000L
1655#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x00000012
1656#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x00300000L
1657#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x00000014
1658#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000L
1659#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x0000001e
1660#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1661#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1662#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000L
1663#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x0000001c
1664#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000L
1665#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x0000001d
1666#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x04000000L
1667#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x0000001a
1668#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x08000000L
1669#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x0000001b
1670#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x01000000L
1671#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x00000018
1672#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x02000000L
1673#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x00000019
1674#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x00010000L
1675#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x00000010
1676#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x00003000L
1677#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0x0000000c
1678#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x00008000L
1679#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0x0000000f
1680#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x001e0000L
1681#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x00000011
1682#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x00000020L
1683#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x00000005
1684#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x00000040L
1685#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x00000006
1686#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x00000007L
1687#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x00000000
1688#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000L
1689#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x0000001e
1690#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000L
1691#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x00000018
1692#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000L
1693#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x0000001d
1694#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000L
1695#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x0000001f
1696#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x00800000L
1697#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x00000017
1698#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x00600000L
1699#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x00000015
1700#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x00000008L
1701#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x00000003
1702#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x00000080L
1703#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x00000007
1704#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x00000010L
1705#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x00000004
1706#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0x00000f00L
1707#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x00000008
1708#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x00004000L
1709#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0x0000000e
1710#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0x00e00000L
1711#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x00000015
1712#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x00080000L
1713#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x00000013
1714#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000L
1715#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x00000018
1716#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000L
1717#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x0000001e
1718#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x00100000L
1719#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x00000014
1720#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x0003f000L
1721#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0x0000000c
1722#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0x00000fc0L
1723#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x00000006
1724#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x0000003fL
1725#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x00000000
1726#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x00040000L
1727#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x00000012
1728#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000L
1729#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x0000001f
1730#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000L
1731#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x0000001a
1732#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x03e00000L
1733#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x00000015
1734#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x001f0000L
1735#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x00000010
1736#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000L
1737#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x0000001f
1738#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0x0000ffffL
1739#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x00000000
1740#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1741#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1742#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000L
1743#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1744#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x00001f00L
1745#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x00000008
1746#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000L
1747#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1748#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x07f00000L
1749#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x00000014
1750#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000L
1751#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x0000001d
1752#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x00080000L
1753#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x00000013
1754#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x00040000L
1755#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x00000012
1756#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000L
1757#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x0000001e
1758#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x0000007fL
1759#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x00000000
1760#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x00000080L
1761#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x00000007
1762#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x0003e000L
1763#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0x0000000d
1764#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1765#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1766#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000L
1767#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1768#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x00001f00L
1769#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x00000008
1770#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000L
1771#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1772#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x07f00000L
1773#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x00000014
1774#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000L
1775#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x0000001d
1776#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x00080000L
1777#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x00000013
1778#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x00040000L
1779#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x00000012
1780#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000L
1781#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x0000001e
1782#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x0000007fL
1783#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x00000000
1784#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x00000080L
1785#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x00000007
1786#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x0003e000L
1787#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0x0000000d
1788#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1789#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1790#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000L
1791#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1792#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x00001f00L
1793#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x00000008
1794#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000L
1795#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1796#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x07f00000L
1797#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x00000014
1798#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000L
1799#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x0000001d
1800#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x00080000L
1801#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x00000013
1802#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x00040000L
1803#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x00000012
1804#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000L
1805#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x0000001e
1806#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x0000007fL
1807#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x00000000
1808#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x00000080L
1809#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x00000007
1810#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x0003e000L
1811#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0x0000000d
1812#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x08000000L
1813#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x0000001b
1814#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000L
1815#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x0000001c
1816#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x00001f00L
1817#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x00000008
1818#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000L
1819#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x0000001f
1820#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x07f00000L
1821#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x00000014
1822#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000L
1823#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x0000001d
1824#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x00080000L
1825#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x00000013
1826#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x00040000L
1827#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x00000012
1828#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000L
1829#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x0000001e
1830#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x0000007fL
1831#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x00000000
1832#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x00000080L
1833#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x00000007
1834#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x0003e000L
1835#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0x0000000d
1836#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffffL
1837#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x00000000
1838#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffffL
1839#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x00000000
1840#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffffL
1841#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x00000000
1842#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffffL
1843#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x00000000
1844#define COMPUTE_DIM_X__SIZE_MASK 0xffffffffL
1845#define COMPUTE_DIM_X__SIZE__SHIFT 0x00000000
1846#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffffL
1847#define COMPUTE_DIM_Y__SIZE__SHIFT 0x00000000
1848#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffffL
1849#define COMPUTE_DIM_Z__SIZE__SHIFT 0x00000000
1850#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L
1851#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x00000000
1852#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x00001000L
1853#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0x0000000c
1854#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x00000380L
1855#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x00000007
1856#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L
1857#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x00000002
1858#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L
1859#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x00000003
1860#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L
1861#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x00000004
1862#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L
1863#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x00000006
1864#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L
1865#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x00000001
1866#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L
1867#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0x0000000e
1868#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L
1869#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0x0000000a
1870#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L
1871#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x00000005
1872#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L
1873#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0x0000000b
1874#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000ffffL
1875#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x00000000
1876#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1877#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1878#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000ffffL
1879#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x00000000
1880#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1881#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1882#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000ffffL
1883#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x00000000
1884#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000L
1885#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x00000010
1886#define COMPUTE_PGM_HI__DATA_MASK 0x000000ffL
1887#define COMPUTE_PGM_HI__DATA__SHIFT 0x00000000
1888#define COMPUTE_PGM_HI__INST_ATC_MASK 0x00000100L
1889#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x00000008
1890#define COMPUTE_PGM_LO__DATA_MASK 0xffffffffL
1891#define COMPUTE_PGM_LO__DATA__SHIFT 0x00000000
1892#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L
1893#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x00000018
1894#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L
1895#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x00000019
1896#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L
1897#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x00000016
1898#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L
1899#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x00000015
1900#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000ff000L
1901#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0x0000000c
1902#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L
1903#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x00000017
1904#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000c00L
1905#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0x0000000a
1906#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L
1907#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x00000014
1908#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003c0L
1909#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x00000006
1910#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003fL
1911#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x00000000
1912#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000L
1913#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L
1914#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0x0000000d
1915#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x00000018
1916#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00ff8000L
1917#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0x0000000f
1918#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L
1919#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x00000000
1920#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L
1921#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x00000007
1922#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L
1923#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x00000008
1924#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L
1925#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x00000009
1926#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L
1927#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0x0000000a
1928#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L
1929#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0x0000000b
1930#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L
1931#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x00000006
1932#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003eL
1933#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x00000001
1934#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L
1935#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x00000018
1936#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L
1937#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x00000017
1938#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003f0000L
1939#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x00000010
1940#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L
1941#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x00000016
1942#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000f000L
1943#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0x0000000c
1944#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x0000003fL
1945#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x00000000
1946#define COMPUTE_START_X__START_MASK 0xffffffffL
1947#define COMPUTE_START_X__START__SHIFT 0x00000000
1948#define COMPUTE_START_Y__START_MASK 0xffffffffL
1949#define COMPUTE_START_Y__START__SHIFT 0x00000000
1950#define COMPUTE_START_Z__START_MASK 0xffffffffL
1951#define COMPUTE_START_Z__START__SHIFT 0x00000000
1952#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000ffffL
1953#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x00000000
1954#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000L
1955#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x00000010
1956#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000ffffL
1957#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x00000000
1958#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000L
1959#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x00000010
1960#define COMPUTE_TBA_HI__DATA_MASK 0x000000ffL
1961#define COMPUTE_TBA_HI__DATA__SHIFT 0x00000000
1962#define COMPUTE_TBA_LO__DATA_MASK 0xffffffffL
1963#define COMPUTE_TBA_LO__DATA__SHIFT 0x00000000
1964#define COMPUTE_TMA_HI__DATA_MASK 0x000000ffL
1965#define COMPUTE_TMA_HI__DATA__SHIFT 0x00000000
1966#define COMPUTE_TMA_LO__DATA_MASK 0xffffffffL
1967#define COMPUTE_TMA_LO__DATA__SHIFT 0x00000000
1968#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01fff000L
1969#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0x0000000c
1970#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000fffL
1971#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x00000000
1972#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffffL
1973#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x00000000
1974#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffffL
1975#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x00000000
1976#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffffL
1977#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x00000000
1978#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffffL
1979#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x00000000
1980#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffffL
1981#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x00000000
1982#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffffL
1983#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x00000000
1984#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffffL
1985#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x00000000
1986#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffffL
1987#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x00000000
1988#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffffL
1989#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x00000000
1990#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffffL
1991#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x00000000
1992#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffffL
1993#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x00000000
1994#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffffL
1995#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x00000000
1996#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffffL
1997#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x00000000
1998#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffffL
1999#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x00000000
2000#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffffL
2001#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x00000000
2002#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffffL
2003#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x00000000
2004#define COMPUTE_VMID__DATA_MASK 0x0000000fL
2005#define COMPUTE_VMID__DATA__SHIFT 0x00000000
2006#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000L
2007#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x0000001d
2008#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L
2009#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x00000010
2010#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x000000ffL
2011#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x00000000
2012#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffcL
2013#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x00000002
2014#define CP_APPEND_DATA__DATA_MASK 0xffffffffL
2015#define CP_APPEND_DATA__DATA__SHIFT 0x00000000
2016#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffffL
2017#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x00000000
2018#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffffL
2019#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x00000000
2020#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffffL
2021#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x00000000
2022#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffffL
2023#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x00000000
2024#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
2025#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x00000016
2026#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
2027#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x00000006
2028#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
2029#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x00000012
2030#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
2031#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0x0000000f
2032#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
2033#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x00000011
2034#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
2035#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x00000008
2036#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
2037#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x00000007
2038#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
2039#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x00000014
2040#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
2041#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x00000015
2042#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
2043#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0x0000000a
2044#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
2045#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x00000009
2046#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
2047#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x00000000
2048#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
2049#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0x0000000c
2050#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
2051#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0x0000000d
2052#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
2053#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0x0000000e
2054#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
2055#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x00000013
2056#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffffL
2057#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x00000000
2058#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
2059#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
2060#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
2061#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
2062#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
2063#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
2064#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
2065#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
2066#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
2067#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
2068#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
2069#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
2070#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x000000ffL
2071#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x00000000
2072#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0L
2073#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x00000005
2074#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000fffL
2075#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x00000000
2076#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07ff0000L
2077#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x00000010
2078#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007ffL
2079#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x00000000
2080#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007ffL
2081#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x00000000
2082#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003ffL
2083#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x00000000
2084#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03ff0000L
2085#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x00000010
2086#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003ffL
2087#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x00000000
2088#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03ff0000L
2089#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x00000010
2090#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003ffL
2091#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x00000000
2092#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03ff0000L
2093#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x00000010
2094#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
2095#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
2096#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
2097#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
2098#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffffL
2099#define CP_CMD_DATA__CMD_DATA__SHIFT 0x00000000
2100#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007ffL
2101#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x00000000
2102#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
2103#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0x0000000c
2104#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00030000L
2105#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x00000010
2106#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0ff00000L
2107#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x00000014
2108#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000ffL
2109#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x00000000
2110#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
2111#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x0000001c
2112#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
2113#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x00000008
2114#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffffL
2115#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x00000000
2116#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000ffL
2117#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x00000000
2118#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L
2119#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x00000006
2120#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L
2121#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x00000007
2122#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L
2123#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x00000008
2124#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L
2125#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x00000009
2126#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L
2127#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0x0000000a
2128#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L
2129#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0x0000000b
2130#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L
2131#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0x0000000c
2132#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L
2133#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0x0000000d
2134#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L
2135#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x00000019
2136#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L
2137#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x0000001a
2138#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L
2139#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0x0000000e
2140#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L
2141#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x00000000
2142#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L
2143#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x00000001
2144#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L
2145#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x00000013
2146#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L
2147#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x00000015
2148#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L
2149#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x0000001d
2150#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L
2151#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x0000001b
2152#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L
2153#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x0000001c
2154#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L
2155#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x00000017
2156#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L
2157#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x00000016
2158#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L
2159#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0x0000000f
2160#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x00010000L
2161#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x00000010
2162#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L
2163#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x00000012
2164#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffffL
2165#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x00000000
2166#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000ffL
2167#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x00000000
2168#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003fL
2169#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x00000000
2170#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000ffL
2171#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x00000000
2172#define CP_COHER_STATUS__MEID_MASK 0x03000000L
2173#define CP_COHER_STATUS__MEID__SHIFT 0x00000018
2174#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000L
2175#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x0000001e
2176#define CP_COHER_STATUS__STATUS_MASK 0x80000000L
2177#define CP_COHER_STATUS__STATUS__SHIFT 0x0000001f
2178#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0x0000000fL
2179#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x00000000
2180#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x00003f00L
2181#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x00000008
2182#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0x0000000fL
2183#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x00000000
2184#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000f0000L
2185#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x00000010
2186#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L
2187#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x00000004
2188#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000L
2189#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x0000001e
2190#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L
2191#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x0000001c
2192#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L
2193#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x0000001d
2194#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x001fffffL
2195#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x00000000
2196#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L
2197#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x0000001d
2198#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L
2199#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x0000001b
2200#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x00200000L
2201#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x00000015
2202#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x03000000L
2203#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x00000018
2204#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L
2205#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x0000001e
2206#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L
2207#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x0000001c
2208#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L
2209#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x0000001a
2210#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0x00c00000L
2211#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x00000016
2212#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffffL
2213#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x00000000
2214#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
2215#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
2216#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
2217#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
2218#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
2219#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
2220#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x001fffffL
2221#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x00000000
2222#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L
2223#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x0000001d
2224#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L
2225#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x0000001b
2226#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x00200000L
2227#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x00000015
2228#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x03000000L
2229#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x00000018
2230#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L
2231#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x0000001e
2232#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L
2233#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x0000001c
2234#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L
2235#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x0000001a
2236#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0x00c00000L
2237#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x00000016
2238#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffffL
2239#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x00000000
2240#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x000000ffL
2241#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x00000000
2242#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x000000ffL
2243#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x00000000
2244#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffffL
2245#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x00000000
2246#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03ffffffL
2247#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x00000000
2248#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L
2249#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x0000001c
2250#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L
2251#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x00000000
2252#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0x000000f0L
2253#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x00000004
2254#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x00000003L
2255#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x00000000
2256#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0x000000f0L
2257#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x00000004
2258#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x00003c00L
2259#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0x0000000a
2260#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0x000f0000L
2261#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x00000010
2262#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x00000003L
2263#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x00000000
2264#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0x000000f0L
2265#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x00000004
2266#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x00003c00L
2267#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0x0000000a
2268#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0x000f0000L
2269#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x00000010
2270#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x00000003L
2271#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x00000000
2272#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0x000000f0L
2273#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x00000004
2274#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x00003c00L
2275#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0x0000000a
2276#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0x000f0000L
2277#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x00000010
2278#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x00003c00L
2279#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0x0000000a
2280#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000f0000L
2281#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x00000010
2282#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000ffffL
2283#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x00000000
2284#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffcL
2285#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x00000002
2286#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x00000003L
2287#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x00000000
2288#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0x0000ffffL
2289#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x00000000
2290#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000L
2291#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x0000001d
2292#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L
2293#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x00000010
2294#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
2295#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x00000018
2296#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffffL
2297#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x00000000
2298#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffffL
2299#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x00000000
2300#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffffL
2301#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x00000000
2302#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffffL
2303#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x00000000
2304#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffffL
2305#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x00000000
2306#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffffL
2307#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x00000000
2308#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffffL
2309#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x00000000
2310#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffffL
2311#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x00000000
2312#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003f00L
2313#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x00000008
2314#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003fL
2315#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003f0000L
2316#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x00000010
2317#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x00000000
2318#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x000000ffL
2319#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x00000000
2320#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffcL
2321#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x00000002
2322#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000fffffL
2323#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x00000000
2324#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000fffffL
2325#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x00000000
2326#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000fffffL
2327#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x00000000
2328#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000fffffL
2329#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x00000000
2330#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x000000ffL
2331#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x00000000
2332#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffcL
2333#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x00000002
2334#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000fffffL
2335#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x00000000
2336#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000fffffL
2337#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x00000000
2338#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000fffffL
2339#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x00000000
2340#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000fffffL
2341#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x00000000
2342#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2343#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2344#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2345#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2346#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2347#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2348#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L
2349#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2350#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L
2351#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2352#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L
2353#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2354#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2355#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2356#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2357#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2358#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2359#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2360#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2361#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2362#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2363#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2364#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2365#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2366#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2367#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2368#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L
2369#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2370#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L
2371#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2372#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L
2373#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2374#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2375#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2376#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2377#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2378#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2379#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2380#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2381#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2382#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2383#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2384#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2385#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2386#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2387#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2388#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2389#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2390#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2391#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2392#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L
2393#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2394#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L
2395#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2396#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L
2397#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2398#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2399#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2400#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2401#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2402#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2403#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2404#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2405#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2406#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2407#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2408#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2409#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2410#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L
2411#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x00000013
2412#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L
2413#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x00000014
2414#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L
2415#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0x0000000e
2416#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L
2417#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x0000001f
2418#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L
2419#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x0000001e
2420#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L
2421#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x0000001d
2422#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L
2423#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x00000018
2424#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L
2425#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016
2426#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L
2427#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x00000017
2428#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L
2429#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x0000001b
2430#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2431#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2432#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2433#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2434#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L
2435#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x0000001a
2436#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L
2437#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x00000011
2438#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
2439#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x00000013
2440#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
2441#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x00000014
2442#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
2443#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0x0000000e
2444#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
2445#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x0000001f
2446#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
2447#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x0000001e
2448#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
2449#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x0000001d
2450#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
2451#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x00000018
2452#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
2453#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x00000016
2454#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
2455#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x00000017
2456#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
2457#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x0000001b
2458#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
2459#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x0000001a
2460#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
2461#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x00000011
2462#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2463#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2464#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2465#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2466#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2467#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2468#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L
2469#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x0000001f
2470#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L
2471#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x0000001e
2472#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L
2473#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x0000001d
2474#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2475#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2476#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2477#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2478#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L
2479#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x00000017
2480#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2481#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2482#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2483#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2484#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2485#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2486#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2487#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2488#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L
2489#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x0000001f
2490#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L
2491#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x0000001e
2492#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L
2493#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x0000001d
2494#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2495#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2496#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2497#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2498#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L
2499#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x00000017
2500#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2501#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2502#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L
2503#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2504#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2505#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2506#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2507#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2508#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2509#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2510#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2511#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2512#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L
2513#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x0000001f
2514#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L
2515#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x0000001e
2516#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L
2517#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x0000001d
2518#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2519#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2520#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2521#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2522#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L
2523#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x00000017
2524#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2525#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2526#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L
2527#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2528#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2529#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2530#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L
2531#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x00000013
2532#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L
2533#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x00000014
2534#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L
2535#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0x0000000e
2536#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L
2537#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x0000001f
2538#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L
2539#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x0000001e
2540#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L
2541#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x0000001d
2542#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L
2543#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x00000018
2544#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L
2545#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x00000016
2546#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L
2547#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x00000017
2548#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L
2549#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x0000001b
2550#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L
2551#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2552#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2553#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2554#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L
2555#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x0000001a
2556#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L
2557#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x00000011
2558#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x0000001fL
2559#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x00000000
2560#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
2561#define CP_ME_CNTL__CE_HALT__SHIFT 0x00000018
2562#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
2563#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x00000004
2564#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
2565#define CP_ME_CNTL__CE_STEP__SHIFT 0x00000019
2566#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
2567#define CP_ME_CNTL__ME_HALT__SHIFT 0x0000001c
2568#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
2569#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x00000008
2570#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
2571#define CP_ME_CNTL__ME_STEP__SHIFT 0x0000001d
2572#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
2573#define CP_ME_CNTL__PFP_HALT__SHIFT 0x0000001a
2574#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
2575#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x00000006
2576#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
2577#define CP_ME_CNTL__PFP_STEP__SHIFT 0x0000001b
2578#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffffL
2579#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x00000000
2580#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x000000ffL
2581#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x00000000
2582#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffcL
2583#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x00000002
2584#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x00000003L
2585#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x00000000
2586#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x000000ffL
2587#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x00000000
2588#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffcL
2589#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x00000002
2590#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x00000003L
2591#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x00000000
2592#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffffL
2593#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x00000000
2594#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffffL
2595#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x00000000
2596#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L
2597#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x00000001
2598#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L
2599#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x00000000
2600#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00ff0000L
2601#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x00000010
2602#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000ff00L
2603#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x00000008
2604#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000L
2605#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018
2606#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x000000fcL
2607#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002
2608#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x00000001L
2609#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x00000000
2610#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003ffL
2611#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x00000000
2612#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003ffL
2613#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x00000000
2614#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03ff0000L
2615#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x00000010
2616#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000ffL
2617#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x00000000
2618#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000ff00L
2619#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x00000008
2620#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffffL
2621#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x00000000
2622#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00000fffL
2623#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x00000000
2624#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00000fffL
2625#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x00000000
2626#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffffL
2627#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x00000000
2628#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffffL
2629#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x00000000
2630#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffffL
2631#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x00000000
2632#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffffL
2633#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x00000000
2634#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffffL
2635#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x00000000
2636#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffffL
2637#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x00000000
2638#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffffL
2639#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x00000000
2640#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffffL
2641#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x00000000
2642#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffffL
2643#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x00000000
2644#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffffL
2645#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x00000000
2646#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffffL
2647#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x00000000
2648#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffffL
2649#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x00000000
2650#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffffL
2651#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x00000000
2652#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffffL
2653#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x00000000
2654#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffffL
2655#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x00000000
2656#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffffL
2657#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x00000000
2658#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffffL
2659#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x00000000
2660#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffffL
2661#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x00000000
2662#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffffL
2663#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x00000000
2664#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffffL
2665#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x00000000
2666#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
2667#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
2668#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
2669#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
2670#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
2671#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
2672#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000f0L
2673#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x00000004
2674#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
2675#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x0000001f
2676#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffffL
2677#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x00000000
2678#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x00000001L
2679#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x00000000
2680#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L
2681#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x00000001
2682#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L
2683#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x00000000
2684#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L
2685#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x00000018
2686#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L
2687#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x00000010
2688#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L
2689#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0x0000000f
2690#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00000fffL
2691#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x00000000
2692#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffffL
2693#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x00000000
2694#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffffffffL
2695#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x00000000
2696#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffcL
2697#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x00000002
2698#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x00000003L
2699#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x00000000
2700#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x00000001L
2701#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x00000000
2702#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003fL
2703#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x00000000
2704#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003f00L
2705#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x00000008
2706#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
2707#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
2708#define CP_RB0_BASE__RB_BASE_MASK 0xffffffffL
2709#define CP_RB0_BASE__RB_BASE__SHIFT 0x00000000
2710#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L
2711#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x00000010
2712#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L
2713#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x00000018
2714#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2715#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2716#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2717#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2718#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003f00L
2719#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x00000008
2720#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003fL
2721#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x00000000
2722#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2723#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2724#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2725#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2726#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L
2727#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2728#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2729#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2730#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2731#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2732#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2733#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2734#define CP_RB0_RPTR__RB_RPTR_MASK 0x000fffffL
2735#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x00000000
2736#define CP_RB0_WPTR__RB_WPTR_MASK 0x000fffffL
2737#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x00000000
2738#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000ffL
2739#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x00000000
2740#define CP_RB1_BASE__RB_BASE_MASK 0xffffffffL
2741#define CP_RB1_BASE__RB_BASE__SHIFT 0x00000000
2742#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L
2743#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x00000018
2744#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2745#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2746#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2747#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2748#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003f00L
2749#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x00000008
2750#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003fL
2751#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x00000000
2752#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2753#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2754#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2755#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2756#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L
2757#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2758#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2759#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2760#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2761#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2762#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2763#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2764#define CP_RB1_RPTR__RB_RPTR_MASK 0x000fffffL
2765#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x00000000
2766#define CP_RB1_WPTR__RB_WPTR_MASK 0x000fffffL
2767#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x00000000
2768#define CP_RB2_BASE__RB_BASE_MASK 0xffffffffL
2769#define CP_RB2_BASE__RB_BASE__SHIFT 0x00000000
2770#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L
2771#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x00000018
2772#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2773#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2774#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2775#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2776#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003f00L
2777#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x00000008
2778#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003fL
2779#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x00000000
2780#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2781#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2782#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2783#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2784#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L
2785#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2786#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2787#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2788#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2789#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2790#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2791#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2792#define CP_RB2_RPTR__RB_RPTR_MASK 0x000fffffL
2793#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x00000000
2794#define CP_RB2_WPTR__RB_WPTR_MASK 0x000fffffL
2795#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x00000000
2796#define CP_RB_BASE__RB_BASE_MASK 0xffffffffL
2797#define CP_RB_BASE__RB_BASE__SHIFT 0x00000000
2798#define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L
2799#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x00000010
2800#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L
2801#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x00000018
2802#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L
2803#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x00000014
2804#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00c00000L
2805#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x00000016
2806#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003f00L
2807#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x00000008
2808#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003fL
2809#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x00000000
2810#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L
2811#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x0000001b
2812#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L
2813#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x0000001f
2814#define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L
2815#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x0000001a
2816#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000fffffL
2817#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x00000000
2818#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x000000ffL
2819#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x00000000
2820#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffcL
2821#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x00000002
2822#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x00000003L
2823#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x00000000
2824#define CP_RB_RPTR__RB_RPTR_MASK 0x000fffffL
2825#define CP_RB_RPTR__RB_RPTR__SHIFT 0x00000000
2826#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000fffffL
2827#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x00000000
2828#define CP_RB_VMID__RB0_VMID_MASK 0x0000000fL
2829#define CP_RB_VMID__RB0_VMID__SHIFT 0x00000000
2830#define CP_RB_VMID__RB1_VMID_MASK 0x00000f00L
2831#define CP_RB_VMID__RB1_VMID__SHIFT 0x00000008
2832#define CP_RB_VMID__RB2_VMID_MASK 0x000f0000L
2833#define CP_RB_VMID__RB2_VMID__SHIFT 0x00000010
2834#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000L
2835#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x0000001c
2836#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0fffffffL
2837#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x00000000
2838#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0x000000ffL
2839#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x00000000
2840#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x000000ffL
2841#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x00000000
2842#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffcL
2843#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x00000002
2844#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffcL
2845#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x00000002
2846#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000L
2847#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010
2848#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000ffffL
2849#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x00000000
2850#define CP_RB_WPTR__RB_WPTR_MASK 0x000fffffL
2851#define CP_RB_WPTR__RB_WPTR__SHIFT 0x00000000
2852#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L
2853#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x00000000
2854#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L
2855#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x00000000
2856#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L
2857#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x00000000
2858#define CP_RINGID__RINGID_MASK 0x00000003L
2859#define CP_RINGID__RINGID__SHIFT 0x00000000
2860#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000ffL
2861#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x00000000
2862#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000ff00L
2863#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x00000008
2864#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00ff0000L
2865#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x00000010
2866#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000L
2867#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x00000018
2868#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00ff0000L
2869#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x00000010
2870#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000L
2871#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x00000018
2872#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000ffL
2873#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x00000000
2874#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000ff00L
2875#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x00000008
2876#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007ffL
2877#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x00000000
2878#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000ff00L
2879#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x00000008
2880#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00ff0000L
2881#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x00000010
2882#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000ffL
2883#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x00000000
2884#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000L
2885#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x00000018
2886#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07ff0000L
2887#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x00000010
2888#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007ffL
2889#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000
2890#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL
2891#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x00000000
2892#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03ff0000L
2893#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x00000010
2894#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003ffL
2895#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x00000000
2896#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03ff0000L
2897#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x00000010
2898#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003ffL
2899#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x00000000
2900#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03ff0000L
2901#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x00000010
2902#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffffL
2903#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x00000000
2904#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffffL
2905#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x00000000
2906#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffffL
2907#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x00000000
2908#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffffL
2909#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x00000000
2910#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffffL
2911#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x00000000
2912#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000ffL
2913#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x00000000
2914#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffffL
2915#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x00000000
2916#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL
2917#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000
2918#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
2919#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018
2920#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L
2921#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d
2922#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
2923#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014
2924#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
2925#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010
2926#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L
2927#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003
2928#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
2929#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000
2930#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
2931#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0x0000000a
2932#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
2933#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0x0000000b
2934#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
2935#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x0000000d
2936#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
2937#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x0000000c
2938#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x00004000L
2939#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0x0000000e
2940#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
2941#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0x0000000f
2942#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x00010000L
2943#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x00000010
2944#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x00020000L
2945#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x00000011
2946#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
2947#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x00000000
2948#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
2949#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x00000004
2950#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
2951#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x00000002
2952#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x10000000L
2953#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x0000001c
2954#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
2955#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x0000001c
2956#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
2957#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x0000001b
2958#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
2959#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x0000001a
2960#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
2961#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x00000017
2962#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
2963#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x00000018
2964#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
2965#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x00000019
2966#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
2967#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x0000001c
2968#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
2969#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x00000019
2970#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
2971#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x0000001a
2972#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
2973#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x0000001d
2974#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
2975#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x0000001b
2976#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
2977#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x00000015
2978#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
2979#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x00000016
2980#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
2981#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0x0000000b
2982#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
2983#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000010
2984#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
2985#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0x0000000c
2986#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
2987#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0x0000000d
2988#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
2989#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0x0000000e
2990#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
2991#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x00000012
2992#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
2993#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0x0000000f
2994#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
2995#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0x0000000a
2996#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
2997#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x00000009
2998#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x00000040L
2999#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x00000006
3000#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
3001#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x00000005
3002#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
3003#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x00000014
3004#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
3005#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x00000013
3006#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
3007#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000
3008#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
3009#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x00000001
3010#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000080L
3011#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000007
3012#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
3013#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x00000002
3014#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
3015#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x00000004
3016#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
3017#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x00000008
3018#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
3019#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x00000018
3020#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
3021#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x00000011
3022#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
3023#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x00000017
3024#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
3025#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x0000001f
3026#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
3027#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x0000001e
3028#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
3029#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x00000000
3030#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
3031#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000006
3032#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x00000100L
3033#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x00000008
3034#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
3035#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x00000004
3036#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
3037#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x00000001
3038#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
3039#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x00000003
3040#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
3041#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x00000005
3042#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
3043#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x00000007
3044#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
3045#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0x0000000a
3046#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
3047#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0x0000000b
3048#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
3049#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x00000002
3050#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
3051#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0x0000000c
3052#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
3053#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0x0000000d
3054#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
3055#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0x0000000e
3056#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
3057#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0x0000000f
3058#define CP_STAT__CE_BUSY_MASK 0x04000000L
3059#define CP_STAT__CE_BUSY__SHIFT 0x0000001a
3060#define CP_STAT__CP_BUSY_MASK 0x80000000L
3061#define CP_STAT__CP_BUSY__SHIFT 0x0000001f
3062#define CP_STAT__CPC_CPG_BUSY_MASK 0x02000000L
3063#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x00000019
3064#define CP_STAT__DC_BUSY_MASK 0x00002000L
3065#define CP_STAT__DC_BUSY__SHIFT 0x0000000d
3066#define CP_STAT__DMA_BUSY_MASK 0x00400000L
3067#define CP_STAT__DMA_BUSY__SHIFT 0x00000016
3068#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
3069#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x00000014
3070#define CP_STAT__ME_BUSY_MASK 0x00020000L
3071#define CP_STAT__ME_BUSY__SHIFT 0x00000011
3072#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
3073#define CP_STAT__MEQ_BUSY__SHIFT 0x00000010
3074#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x00000080L
3075#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x00000007
3076#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x00000100L
3077#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x00000008
3078#define CP_STAT__PFP_BUSY_MASK 0x00008000L
3079#define CP_STAT__PFP_BUSY__SHIFT 0x0000000f
3080#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
3081#define CP_STAT__QUERY_BUSY__SHIFT 0x00000012
3082#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
3083#define CP_STAT__RCIU_BUSY__SHIFT 0x00000017
3084#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
3085#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x0000001d
3086#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
3087#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x0000001e
3088#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
3089#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x0000001c
3090#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
3091#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0x0000000a
3092#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
3093#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0x0000000b
3094#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
3095#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x00000009
3096#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
3097#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0x0000000c
3098#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
3099#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x00000018
3100#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
3101#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x00000013
3102#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
3103#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x00000015
3104#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
3105#define CP_STAT__TCIU_BUSY__SHIFT 0x0000001b
3106#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x000000ffL
3107#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x00000000
3108#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffcL
3109#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x00000002
3110#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000fffffL
3111#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x00000000
3112#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001ffL
3113#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x00000000
3114#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003ffL
3115#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x00000000
3116#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000ffL
3117#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x00000000
3118#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000ff00L
3119#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x00000008
3120#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00ff0000L
3121#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x00000010
3122#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffffffffL
3123#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x00000000
3124#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffcL
3125#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x00000002
3126#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x00000003L
3127#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x00000000
3128#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L
3129#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x00000000
3130#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffffL
3131#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x00000000
3132#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffffL
3133#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x00000000
3134#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffffL
3135#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x00000000
3136#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffffL
3137#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x00000000
3138#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffffL
3139#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x00000000
3140#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffffL
3141#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x00000000
3142#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffffL
3143#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x00000000
3144#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffffL
3145#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x00000000
3146#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffffL
3147#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x00000000
3148#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffffL
3149#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x00000000
3150#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffffL
3151#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x00000000
3152#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffffL
3153#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x00000000
3154#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffffL
3155#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x00000000
3156#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffffL
3157#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x00000000
3158#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffffL
3159#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x00000000
3160#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffffL
3161#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x00000000
3162#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000ffffL
3163#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x00000000
3164#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000L
3165#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x00000010
3166#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000ffffL
3167#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x00000000
3168#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000L
3169#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x00000010
3170#define CP_VMID__VMID_MASK 0x0000000fL
3171#define CP_VMID__VMID__SHIFT 0x00000000
3172#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffffL
3173#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x00000000
3174#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x000000ffL
3175#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x00000000
3176#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L
3177#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018
3178#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000L
3179#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x0000001d
3180#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L
3181#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x00000014
3182#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L
3183#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010
3184#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8L
3185#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x00000003
3186#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L
3187#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x00000000
3188#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
3189#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x00000000
3190#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L
3191#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x00000000
3192#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L
3193#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x00000008
3194#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000c00L
3195#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0x0000000a
3196#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L
3197#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0x0000000c
3198#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000c000L
3199#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0x0000000e
3200#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L
3201#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x00000010
3202#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000ff0L
3203#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x00000004
3204#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000fL
3205#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x00000000
3206#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x00fff000L
3207#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x0000000c
3208#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L
3209#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0000001f
3210#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L
3211#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x0000001e
3212#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L
3213#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x0000001d
3214#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L
3215#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x0000001c
3216#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L
3217#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x0000001b
3218#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L
3219#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x0000001a
3220#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L
3221#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x00000019
3222#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L
3223#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x00000018
3224#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00f00000L
3225#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x00000014
3226#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L
3227#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x00000001
3228#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L
3229#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x00000004
3230#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000f0000L
3231#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x00000010
3232#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0f000000L
3233#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x00000018
3234#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000L
3235#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x0000001c
3236#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L
3237#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0x0000000c
3238#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000f00L
3239#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x00000008
3240#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L
3241#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x00000000
3242#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001c00L
3243#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0x0000000a
3244#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000L
3245#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x00000018
3246#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003e0L
3247#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x00000005
3248#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001fL
3249#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x00000000
3250#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
3251#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x00000000
3252#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003e00L
3253#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x00000009
3254#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
3255#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x00000012
3256#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L
3257#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x00000010
3258#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
3259#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x00000011
3260#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x00000100L
3261#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x00000008
3262#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x00000020L
3263#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x00000080L
3264#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x00000007
3265#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x00000005
3266#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
3267#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x0000001d
3268#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
3269#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x00000013
3270#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x80000000L
3271#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x0000001f
3272#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
3273#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x00000002
3274#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
3275#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x00000001
3276#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
3277#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0x0000000e
3278#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
3279#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x0000001f
3280#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
3281#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x00000004
3282#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
3283#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x00000003
3284#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x00000040L
3285#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x00000006
3286#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
3287#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x0000001c
3288#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
3289#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0x0000000f
3290#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00020000L
3291#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x00000011
3292#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xfc000000L
3293#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x0000001a
3294#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
3295#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x00000019
3296#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
3297#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x00000018
3298#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
3299#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x00000004
3300#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00200000L
3301#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x00000015
3302#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00004000L
3303#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0x0000000e
3304#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00010000L
3305#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0x00000010
3306#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00008000L
3307#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0x0000000f
3308#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00080000L
3309#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x00000013
3310#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00002000L
3311#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0x0000000d
3312#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
3313#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x0000001b
3314#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
3315#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x00000017
3316#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000800L
3317#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0x0000000b
3318#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000400L
3319#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x0000000a
3320#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
3321#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x00000007
3322#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00100000L
3323#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x00000014
3324#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
3325#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x00000003
3326#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
3327#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x00000008
3328#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
3329#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x0000001d
3330#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
3331#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x0000001c
3332#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
3333#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x0000001a
3334#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00001000L
3335#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0x0000000c
3336#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00400000L
3337#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x00000016
3338#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00800000L
3339#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x00000017
3340#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
3341#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x00000005
3342#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
3343#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x00000006
3344#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
3345#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x00000002
3346#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00040000L
3347#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x00000012
3348#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffffc0L
3349#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x00000006
3350#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000020L
3351#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x00000005
3352#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
3353#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x00000001
3354#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
3355#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x00000000
3356#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
3357#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x00000002
3358#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
3359#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x00000001
3360#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
3361#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0x0000000f
3362#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
3363#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0x0000000e
3364#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
3365#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x00000006
3366#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
3367#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x00000013
3368#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000c00L
3369#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0x0000000a
3370#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
3371#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0x0000000c
3372#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
3373#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x00000008
3374#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
3375#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x00000007
3376#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
3377#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x00000010
3378#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
3379#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x00000000
3380#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0f000000L
3381#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x00000018
3382#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
3383#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x00000012
3384#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
3385#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x0000001e
3386#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
3387#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x0000001f
3388#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
3389#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x00000011
3390#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
3391#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x00000017
3392#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
3393#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x00000003
3394#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
3395#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x00000002
3396#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
3397#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x0000001d
3398#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
3399#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x00000004
3400#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
3401#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x00000015
3402#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
3403#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x0000001c
3404#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
3405#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x00000016
3406#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffffL
3407#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x00000000
3408#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffffL
3409#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x00000000
3410#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffffL
3411#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x00000000
3412#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L
3413#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x00000007
3414#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L
3415#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x00000003
3416#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L
3417#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x0000001f
3418#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L
3419#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x0000001e
3420#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L
3421#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x00000000
3422#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L
3423#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x00000014
3424#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L
3425#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x00000008
3426#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L
3427#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x00000001
3428#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L
3429#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x00000004
3430#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L
3431#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x00000002
3432#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0x0000000fL
3433#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x00000000
3434#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0x000000f0L
3435#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x00000004
3436#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x00018000L
3437#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0x0000000f
3438#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x00006000L
3439#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0x0000000d
3440#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x00060000L
3441#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x00000011
3442#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x00180000L
3443#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x00000013
3444#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x00001f00L
3445#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x00000008
3446#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x003ff800L
3447#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0x0000000b
3448#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x000007ffL
3449#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x00000000
3450#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x003fffffL
3451#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x00000000
3452#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00ffe000L
3453#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x0000000d
3454#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007ffL
3455#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x00000000
3456#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L
3457#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x00000019
3458#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L
3459#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x00000018
3460#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L
3461#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x00000015
3462#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L
3463#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0x0000000c
3464#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L
3465#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x0000001b
3466#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L
3467#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x00000010
3468#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L
3469#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x00000011
3470#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L
3471#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x00000012
3472#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L
3473#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x00000013
3474#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L
3475#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x00000008
3476#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L
3477#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x00000000
3478#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L
3479#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x00000018
3480#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L
3481#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x00000004
3482#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L
3483#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x00000014
3484#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000L
3485#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x00000015
3486#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000fc00L
3487#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x0000000a
3488#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x0000001fL
3489#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x00000000
3490#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x000003e0L
3491#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x00000005
3492#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001f0000L
3493#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x00000010
3494#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000ffL
3495#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x00000000
3496#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007f00L
3497#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x00000008
3498#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01ff8000L
3499#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x0000000f
3500#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000L
3501#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x00000019
3502#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007fL
3503#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x00000000
3504#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x01e00000L
3505#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x00000015
3506#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003f80L
3507#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x00000007
3508#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x001fc000L
3509#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x0000000e
3510#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000L
3511#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x00000019
3512#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffffL
3513#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x00000000
3514#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L
3515#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x00000010
3516#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L
3517#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x00000001
3518#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L
3519#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x00000002
3520#define DB_HTILE_SURFACE__LINEAR_MASK 0x00000001L
3521#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x00000000
3522#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000fc00L
3523#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0x0000000a
3524#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003f0L
3525#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x00000004
3526#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L
3527#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x00000003
3528#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3529#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3530#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3531#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3532#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000L
3533#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x0000001c
3534#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0f000000L
3535#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x00000018
3536#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003ffL
3537#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x00000000
3538#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000ffc00L
3539#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a
3540#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00f00000L
3541#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x00000014
3542#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0f000000L
3543#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x00000018
3544#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000L
3545#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x0000001c
3546#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000ffc00L
3547#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a
3548#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000ffL
3549#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
3550#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3551#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3552#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3553#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3554#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000L
3555#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x0000001c
3556#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0f000000L
3557#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x00000018
3558#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003ffL
3559#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x00000000
3560#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000ffc00L
3561#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a
3562#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00f00000L
3563#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014
3564#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0f000000L
3565#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x00000018
3566#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000L
3567#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x0000001c
3568#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000ffc00L
3569#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0x0000000a
3570#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000ffL
3571#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
3572#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3573#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3574#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3575#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3576#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00f00000L
3577#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x00000014
3578#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0f000000L
3579#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x00000018
3580#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000L
3581#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x0000001c
3582#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000ffc00L
3583#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0x0000000a
3584#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000ffL
3585#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x00000000
3586#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffffL
3587#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x00000000
3588#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffffL
3589#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x00000000
3590#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00f00000L
3591#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x00000014
3592#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0f000000L
3593#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x00000018
3594#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000L
3595#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x0000001c
3596#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000ffc00L
3597#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0x0000000a
3598#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000ffL
3599#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x00000000
3600#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00ff0000L
3601#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x00000010
3602#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000L
3603#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x00000018
3604#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000ffL
3605#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x00000000
3606#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000ff00L
3607#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x00000008
3608#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffffL
3609#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x00000000
3610#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffffL
3611#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x00000000
3612#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffffL
3613#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x00000000
3614#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffffL
3615#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x00000000
3616#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffffL
3617#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x00000000
3618#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffffL
3619#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x00000000
3620#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffffL
3621#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x00000000
3622#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffffL
3623#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x00000000
3624#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffffL
3625#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x00000000
3626#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffffL
3627#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x00000000
3628#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffffL
3629#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x00000000
3630#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffffL
3631#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x00000000
3632#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffffL
3633#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x00000000
3634#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffffL
3635#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x00000000
3636#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffffL
3637#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x00000000
3638#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffffL
3639#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x00000000
3640#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L
3641#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x00000007
3642#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000f00L
3643#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x00000008
3644#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L
3645#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x00000000
3646#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L
3647#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x00000006
3648#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L
3649#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x00000002
3650#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L
3651#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x00000004
3652#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L
3653#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x00000001
3654#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L
3655#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x00000005
3656#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L
3657#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x00000003
3658#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L
3659#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x00000008
3660#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L
3661#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x0000000a
3662#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L
3663#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x00000007
3664#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L
3665#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x00000017
3666#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L
3667#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x00000009
3668#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L
3669#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000006
3670#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L
3671#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x00000005
3672#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001c0000L
3673#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x00000012
3674#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L
3675#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0x0000000f
3676#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L
3677#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0x0000000c
3678#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L
3679#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x00000000
3680#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001cL
3681#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x00000002
3682#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L
3683#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x00000016
3684#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L
3685#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x00000015
3686#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L
3687#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0x0000000b
3688#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L
3689#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x00000012
3690#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L
3691#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x0000001a
3692#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L
3693#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x00000010
3694#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L
3695#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x00000008
3696#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L
3697#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x00000007
3698#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L
3699#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0x0000000a
3700#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L
3701#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x0000000d
3702#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000cL
3703#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x00000002
3704#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L
3705#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x00000004
3706#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L
3707#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x00000000
3708#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L
3709#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0x0000000f
3710#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L
3711#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x00000006
3712#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L
3713#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x0000001c
3714#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L
3715#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0x0000000c
3716#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L
3717#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x0000001e
3718#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L
3719#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x0000001b
3720#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L
3721#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x00000013
3722#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L
3723#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0x0000000b
3724#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L
3725#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x0000001d
3726#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L
3727#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x00000011
3728#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03e00000L
3729#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x00000015
3730#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L
3731#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x00000009
3732#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L
3733#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x0000001f
3734#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L
3735#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0x0000000b
3736#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L
3737#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x0000000d
3738#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L
3739#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x00000007
3740#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L
3741#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0x0000000c
3742#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L
3743#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x00000009
3744#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L
3745#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0x0000000a
3746#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L
3747#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x00000006
3748#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L
3749#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x00000008
3750#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L
3751#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x00000002
3752#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L
3753#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x00000001
3754#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L
3755#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x00000000
3756#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L
3757#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x00000004
3758#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L
3759#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x00000000
3760#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000ff000L
3761#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0x0000000c
3762#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000ff0L
3763#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x00000004
3764#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L
3765#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x00000018
3766#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L
3767#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x00000000
3768#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000ff000L
3769#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0x0000000c
3770#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000ff0L
3771#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x00000004
3772#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L
3773#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x00000018
3774#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000ffL
3775#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x00000000
3776#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000f000L
3777#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0x0000000c
3778#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000fL
3779#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x00000000
3780#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00f00000L
3781#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x00000014
3782#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000f00L
3783#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x00000008
3784#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000f0000L
3785#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x00000010
3786#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000f0L
3787#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x00000004
3788#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
3789#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b
3790#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L
3791#define DB_STENCIL_INFO__FORMAT__SHIFT 0x00000000
3792#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x00700000L
3793#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x00000014
3794#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0x0000e000L
3795#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0x0000000d
3796#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L
3797#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x0000001d
3798#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffffL
3799#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x00000000
3800#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000ff00L
3801#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x00000008
3802#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000L
3803#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x00000018
3804#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000ffL
3805#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x00000000
3806#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00ff0000L
3807#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x00000010
3808#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000ff00L
3809#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x00000008
3810#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000L
3811#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x00000018
3812#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000ffL
3813#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x00000000
3814#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00ff0000L
3815#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x00000010
3816#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffffL
3817#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x00000000
3818#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
3819#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x00000010
3820#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000c0000L
3821#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x00000012
3822#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
3823#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x00000000
3824#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000cL
3825#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x00000002
3826#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
3827#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x00000004
3828#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000c0L
3829#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x00000006
3830#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
3831#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x00000008
3832#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000c00L
3833#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0x0000000a
3834#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
3835#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0x0000000c
3836#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000c000L
3837#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0x0000000e
3838#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
3839#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x0000001e
3840#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
3841#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x0000001f
3842#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x07f00000L
3843#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x00000014
3844#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007e0L
3845#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x00000005
3846#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001fL
3847#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x00000000
3848#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000f8000L
3849#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x0000000f
3850#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x08000000L
3851#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x0000001b
3852#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
3853#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0x0000000b
3854#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000L
3855#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x0000001c
3856#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000L
3857#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x0000001d
3858#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L
3859#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x0000001b
3860#define DB_Z_INFO__FORMAT_MASK 0x00000003L
3861#define DB_Z_INFO__FORMAT__SHIFT 0x00000000
3862#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000cL
3863#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x00000002
3864#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L
3865#define DB_Z_INFO__READ_SIZE__SHIFT 0x0000001c
3866#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x00700000L
3867#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x00000014
3868#define DB_Z_INFO__TILE_SPLIT_MASK 0x0000e000L
3869#define DB_Z_INFO__TILE_SPLIT__SHIFT 0x0000000d
3870#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L
3871#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x0000001d
3872#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L
3873#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x0000001f
3874#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffffL
3875#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x00000000
3876#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffffL
3877#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x00000000
3878#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffffL
3879#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x00000000
3880#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffffL
3881#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x00000000
3882#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffffL
3883#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x00000000
3884#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x0003ffffL
3885#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x00000000
3886#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
3887#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
3888#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
3889#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
3890#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
3891#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
3892#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
3893#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
3894#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
3895#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
3896#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
3897#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
3898#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
3899#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
3900#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
3901#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
3902#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
3903#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
3904#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffffL
3905#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x00000000
3906#define GB_EDC_MODE__BYPASS_MASK 0x80000000L
3907#define GB_EDC_MODE__BYPASS__SHIFT 0x0000001f
3908#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L
3909#define GB_EDC_MODE__DED_MODE__SHIFT 0x00000014
3910#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00010000L
3911#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x00000010
3912#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L
3913#define GB_EDC_MODE__PROP_FED__SHIFT 0x0000001d
3914#define GB_GPU_ID__GPU_ID_MASK 0x0000000fL
3915#define GB_GPU_ID__GPU_ID__SHIFT 0x00000000
3916#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003cL
3917#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x00000002
3918#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3919#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3920#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007c0L
3921#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x00000006
3922#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
3923#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x00000019
3924#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
3925#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0x0000000b
3926#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003cL
3927#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x00000002
3928#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3929#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3930#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007c0L
3931#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x00000006
3932#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
3933#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x00000019
3934#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
3935#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0x0000000b
3936#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003cL
3937#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x00000002
3938#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3939#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3940#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007c0L
3941#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x00000006
3942#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
3943#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x00000019
3944#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
3945#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0x0000000b
3946#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003cL
3947#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x00000002
3948#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3949#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3950#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007c0L
3951#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x00000006
3952#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
3953#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x00000019
3954#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
3955#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0x0000000b
3956#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003cL
3957#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x00000002
3958#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3959#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3960#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007c0L
3961#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x00000006
3962#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
3963#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x00000019
3964#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
3965#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0x0000000b
3966#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003cL
3967#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x00000002
3968#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3969#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3970#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007c0L
3971#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x00000006
3972#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
3973#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x00000019
3974#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
3975#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0x0000000b
3976#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003cL
3977#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x00000002
3978#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3979#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3980#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007c0L
3981#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x00000006
3982#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
3983#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x00000019
3984#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
3985#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0x0000000b
3986#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003cL
3987#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x00000002
3988#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3989#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
3990#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007c0L
3991#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x00000006
3992#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
3993#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x00000019
3994#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
3995#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0x0000000b
3996#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003cL
3997#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x00000002
3998#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
3999#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4000#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007c0L
4001#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x00000006
4002#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
4003#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x00000019
4004#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
4005#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0x0000000b
4006#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003cL
4007#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x00000002
4008#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4009#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4010#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007c0L
4011#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x00000006
4012#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
4013#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x00000019
4014#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
4015#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0x0000000b
4016#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003cL
4017#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x00000002
4018#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4019#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4020#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007c0L
4021#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x00000006
4022#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
4023#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x00000019
4024#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
4025#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0x0000000b
4026#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003cL
4027#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x00000002
4028#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4029#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4030#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007c0L
4031#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x00000006
4032#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
4033#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x00000019
4034#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
4035#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0x0000000b
4036#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003cL
4037#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x00000002
4038#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4039#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4040#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007c0L
4041#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x00000006
4042#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
4043#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x00000019
4044#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
4045#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0x0000000b
4046#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003cL
4047#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x00000002
4048#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4049#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4050#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007c0L
4051#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x00000006
4052#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
4053#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x00000019
4054#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
4055#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0x0000000b
4056#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003cL
4057#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x00000002
4058#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4059#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4060#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007c0L
4061#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x00000006
4062#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
4063#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x00000019
4064#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
4065#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0x0000000b
4066#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003cL
4067#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x00000002
4068#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4069#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4070#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007c0L
4071#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x00000006
4072#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
4073#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x00000019
4074#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
4075#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0x0000000b
4076#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003cL
4077#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x00000002
4078#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4079#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4080#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007c0L
4081#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x00000006
4082#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
4083#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x00000019
4084#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
4085#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0x0000000b
4086#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003cL
4087#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x00000002
4088#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4089#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4090#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007c0L
4091#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x00000006
4092#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
4093#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x00000019
4094#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
4095#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0x0000000b
4096#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003cL
4097#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x00000002
4098#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4099#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4100#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007c0L
4101#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x00000006
4102#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
4103#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x00000019
4104#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
4105#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0x0000000b
4106#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003cL
4107#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x00000002
4108#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4109#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4110#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007c0L
4111#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x00000006
4112#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
4113#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x00000019
4114#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
4115#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0x0000000b
4116#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003cL
4117#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x00000002
4118#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4119#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4120#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007c0L
4121#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x00000006
4122#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
4123#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x00000019
4124#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
4125#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0x0000000b
4126#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003cL
4127#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x00000002
4128#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4129#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4130#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007c0L
4131#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x00000006
4132#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
4133#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x00000019
4134#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
4135#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0x0000000b
4136#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003cL
4137#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x00000002
4138#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4139#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4140#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007c0L
4141#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x00000006
4142#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
4143#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x00000019
4144#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
4145#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0x0000000b
4146#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003cL
4147#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x00000002
4148#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4149#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4150#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007c0L
4151#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x00000006
4152#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
4153#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x00000019
4154#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
4155#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0x0000000b
4156#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003cL
4157#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x00000002
4158#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4159#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4160#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007c0L
4161#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x00000006
4162#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
4163#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x00000019
4164#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
4165#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0x0000000b
4166#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003cL
4167#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x00000002
4168#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4169#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4170#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007c0L
4171#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x00000006
4172#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
4173#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x00000019
4174#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
4175#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0x0000000b
4176#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003cL
4177#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x00000002
4178#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4179#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4180#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007c0L
4181#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x00000006
4182#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
4183#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x00000019
4184#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
4185#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0x0000000b
4186#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003cL
4187#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x00000002
4188#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4189#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4190#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007c0L
4191#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x00000006
4192#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
4193#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x00000019
4194#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
4195#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0x0000000b
4196#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003cL
4197#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x00000002
4198#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4199#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4200#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007c0L
4201#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x00000006
4202#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
4203#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x00000019
4204#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
4205#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0x0000000b
4206#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003cL
4207#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x00000002
4208#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4209#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4210#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007c0L
4211#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x00000006
4212#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
4213#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x00000019
4214#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
4215#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0x0000000b
4216#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003cL
4217#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x00000002
4218#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4219#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4220#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007c0L
4221#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x00000006
4222#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
4223#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x00000019
4224#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
4225#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0x0000000b
4226#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003cL
4227#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x00000002
4228#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01c00000L
4229#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x00000016
4230#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007c0L
4231#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x00000006
4232#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
4233#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x00000019
4234#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
4235#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0x0000000b
4236#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
4237#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
4238#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK 0x00000006L
4239#define GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT 0x00000001
4240#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK 0x00000010L
4241#define GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT 0x00000004
4242#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000L
4243#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x00000010
4244#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
4245#define GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x00000003
4246#define GDS_ATOM_BASE__BASE_MASK 0x0000ffffL
4247#define GDS_ATOM_BASE__BASE__SHIFT 0x00000000
4248#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000L
4249#define GDS_ATOM_BASE__UNUSED__SHIFT 0x00000010
4250#define GDS_ATOM_CNTL__AINC_MASK 0x0000003fL
4251#define GDS_ATOM_CNTL__AINC__SHIFT 0x00000000
4252#define GDS_ATOM_CNTL__DMODE_MASK 0x00000100L
4253#define GDS_ATOM_CNTL__DMODE__SHIFT 0x00000008
4254#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000c0L
4255#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x00000006
4256#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffe00L
4257#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0x00000009
4258#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L
4259#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x00000000
4260#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffeL
4261#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x00000001
4262#define GDS_ATOM_DST__DST_MASK 0xffffffffL
4263#define GDS_ATOM_DST__DST__SHIFT 0x00000000
4264#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000ffL
4265#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x00000000
4266#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00L
4267#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x00000008
4268#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000ffL
4269#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x00000000
4270#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00L
4271#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x00000008
4272#define GDS_ATOM_OP__OP_MASK 0x000000ffL
4273#define GDS_ATOM_OP__OP__SHIFT 0x00000000
4274#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00L
4275#define GDS_ATOM_OP__UNUSED__SHIFT 0x00000008
4276#define GDS_ATOM_READ0__DATA_MASK 0xffffffffL
4277#define GDS_ATOM_READ0__DATA__SHIFT 0x00000000
4278#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffffL
4279#define GDS_ATOM_READ0_U__DATA__SHIFT 0x00000000
4280#define GDS_ATOM_READ1__DATA_MASK 0xffffffffL
4281#define GDS_ATOM_READ1__DATA__SHIFT 0x00000000
4282#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffffL
4283#define GDS_ATOM_READ1_U__DATA__SHIFT 0x00000000
4284#define GDS_ATOM_SIZE__SIZE_MASK 0x0000ffffL
4285#define GDS_ATOM_SIZE__SIZE__SHIFT 0x00000000
4286#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000L
4287#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x00000010
4288#define GDS_ATOM_SRC0__DATA_MASK 0xffffffffL
4289#define GDS_ATOM_SRC0__DATA__SHIFT 0x00000000
4290#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffffL
4291#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x00000000
4292#define GDS_ATOM_SRC1__DATA_MASK 0xffffffffL
4293#define GDS_ATOM_SRC1__DATA__SHIFT 0x00000000
4294#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffffL
4295#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x00000000
4296#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
4297#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x00000004
4298#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
4299#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x00000003
4300#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
4301#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x00000006
4302#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
4303#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x00000005
4304#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
4305#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x00000000
4306#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
4307#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x00000001
4308#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
4309#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x00000002
4310#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
4311#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x00000001
4312#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
4313#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x00000003
4314#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
4315#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005
4316#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
4317#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x00000007
4318#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x0000001fL
4319#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x00000000
4320#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0L
4321#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x00000005
4322#define GDS_DEBUG_DATA__DATA_MASK 0xffffffffL
4323#define GDS_DEBUG_DATA__DATA__SHIFT 0x00000000
4324#define GDS_DEBUG_REG0__buff_write_MASK 0x00020000L
4325#define GDS_DEBUG_REG0__buff_write__SHIFT 0x00000011
4326#define GDS_DEBUG_REG0__cstate_MASK 0x0001e000L
4327#define GDS_DEBUG_REG0__cstate__SHIFT 0x0000000d
4328#define GDS_DEBUG_REG0__flush_request_MASK 0x00040000L
4329#define GDS_DEBUG_REG0__flush_request__SHIFT 0x00000012
4330#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x00001000L
4331#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0x0000000c
4332#define GDS_DEBUG_REG0__spare1_MASK 0x00000001L
4333#define GDS_DEBUG_REG0__spare1__SHIFT 0x00000000
4334#define GDS_DEBUG_REG0__spare_MASK 0xff000000L
4335#define GDS_DEBUG_REG0__spare__SHIFT 0x00000018
4336#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x00100000L
4337#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x00000014
4338#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x00200000L
4339#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x00000015
4340#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x00080000L
4341#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x00000013
4342#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x00000040L
4343#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x00000006
4344#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0x00000f80L
4345#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x00000007
4346#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x00200000L
4347#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x00000015
4348#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x00100000L
4349#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x00000014
4350#define GDS_DEBUG_REG1__awaiting_data_MASK 0x00080000L
4351#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x00000013
4352#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x00800000L
4353#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x00000017
4354#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x00400000L
4355#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x00000016
4356#define GDS_DEBUG_REG1__data_ready_MASK 0x00040000L
4357#define GDS_DEBUG_REG1__data_ready__SHIFT 0x00000012
4358#define GDS_DEBUG_REG1__pixel_addr_MASK 0x0001fffcL
4359#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x00000002
4360#define GDS_DEBUG_REG1__pixel_vld_MASK 0x00020000L
4361#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x00000011
4362#define GDS_DEBUG_REG1__spare_MASK 0xff000000L
4363#define GDS_DEBUG_REG1__spare__SHIFT 0x00000018
4364#define GDS_DEBUG_REG1__tag_hit_MASK 0x00000001L
4365#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x00000000
4366#define GDS_DEBUG_REG1__tag_miss_MASK 0x00000002L
4367#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x00000001
4368#define GDS_DEBUG_REG2__app_sel_MASK 0x000000f0L
4369#define GDS_DEBUG_REG2__app_sel__SHIFT 0x00000004
4370#define GDS_DEBUG_REG2__cmd_write_MASK 0x00000008L
4371#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x00000003
4372#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x00000002L
4373#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x00000001
4374#define GDS_DEBUG_REG2__ds_full_MASK 0x00000001L
4375#define GDS_DEBUG_REG2__ds_full__SHIFT 0x00000000
4376#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x00000004L
4377#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x00000002
4378#define GDS_DEBUG_REG2__req_MASK 0x007fff00L
4379#define GDS_DEBUG_REG2__req__SHIFT 0x00000008
4380#define GDS_DEBUG_REG2__spare_MASK 0xff000000L
4381#define GDS_DEBUG_REG2__spare__SHIFT 0x00000018
4382#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x00007800L
4383#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0x0000000b
4384#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x000007ffL
4385#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x00000000
4386#define GDS_DEBUG_REG3__spare_MASK 0xff000000L
4387#define GDS_DEBUG_REG3__spare__SHIFT 0x00000018
4388#define GDS_DEBUG_REG4__cmd_write_MASK 0x00020000L
4389#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x00000011
4390#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x00010000L
4391#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x00000010
4392#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x00002000L
4393#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0x0000000d
4394#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x00008000L
4395#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0x0000000f
4396#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x00001000L
4397#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0x0000000c
4398#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x00004000L
4399#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0x0000000e
4400#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x00000400L
4401#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0x0000000a
4402#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x00000800L
4403#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0x0000000b
4404#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x00000200L
4405#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x00000009
4406#define GDS_DEBUG_REG4__cur_reso_MASK 0x000001f8L
4407#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x00000003
4408#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x00080000L
4409#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x00000013
4410#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x00040000L
4411#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x00000012
4412#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x00200000L
4413#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x00000015
4414#define GDS_DEBUG_REG4__gws_busy_MASK 0x00000001L
4415#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x00000000
4416#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x00000004L
4417#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x00000002
4418#define GDS_DEBUG_REG4__gws_req_MASK 0x00000002L
4419#define GDS_DEBUG_REG4__gws_req__SHIFT 0x00000001
4420#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x00400000L
4421#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x00000016
4422#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x00800000L
4423#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x00000017
4424#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x00100000L
4425#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x00000014
4426#define GDS_DEBUG_REG4__spare_MASK 0xff000000L
4427#define GDS_DEBUG_REG4__spare__SHIFT 0x00000018
4428#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x00000004L
4429#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x00000002
4430#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x00000008L
4431#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x00000003
4432#define GDS_DEBUG_REG5__dec_error_MASK 0x00000002L
4433#define GDS_DEBUG_REG5__dec_error__SHIFT 0x00000001
4434#define GDS_DEBUG_REG5__error_ds_address_MASK 0x003fff00L
4435#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x00000008<