1/*
2 * GFX_7_2 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_7_2_SH_MASK_H
25#define GFX_7_2_SH_MASK_H
26
27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
37#define CB_COLOR_CONTROL__MODE_MASK 0x70
38#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
39#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
40#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
41#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
42#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
43#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
44#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
45#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
46#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
47#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
48#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
49#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
50#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
51#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
52#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
53#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
54#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
55#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
56#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
57#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
58#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
59#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
60#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
61#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
62#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
63#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
64#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
65#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
66#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
67#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
68#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
69#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
70#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
71#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
72#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
73#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
74#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
75#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
76#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
77#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
78#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
79#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
80#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
81#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
82#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
83#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
84#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
85#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
86#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
87#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
88#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
89#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
90#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
91#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
92#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
93#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
94#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
95#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
96#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
97#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
98#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
99#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
100#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
101#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
102#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
103#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
104#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
105#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
106#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
107#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
108#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
109#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
110#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
111#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
112#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
113#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
114#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
115#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
116#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
117#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
118#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
119#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
120#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
121#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
122#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
123#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
124#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
125#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
126#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
127#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
128#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
129#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
130#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
131#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
132#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
133#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
134#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
135#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
136#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
137#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
138#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
139#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
140#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
141#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
142#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
143#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
144#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
145#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
146#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
147#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
148#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
149#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
150#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
151#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
152#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
153#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
154#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
155#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
156#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
157#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
158#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
159#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
160#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
161#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
162#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
163#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
164#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
165#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
166#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
167#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
168#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
169#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
170#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
171#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
172#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
173#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
174#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
175#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
176#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
177#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
178#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
179#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
180#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
181#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
182#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
183#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
184#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
185#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
186#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
187#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
188#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
189#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
190#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
191#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
192#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
193#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
194#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
195#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
196#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
197#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
198#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
199#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
200#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
201#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
202#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
203#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
204#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
205#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
206#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
207#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
208#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
209#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
210#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
211#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
212#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
213#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
214#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
215#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
216#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
217#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
218#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
219#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
220#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
221#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
222#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
223#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
224#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
225#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
226#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
227#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
228#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
229#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
230#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
231#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
232#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
233#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
234#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
235#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
236#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
237#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
238#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
239#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
240#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
241#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
242#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
243#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
244#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
245#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
246#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
247#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
248#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
249#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
250#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
251#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
252#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
253#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
254#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
255#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
256#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
257#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
258#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
259#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
260#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
261#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
262#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
263#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
264#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
265#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
266#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
267#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
268#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
269#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
270#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
271#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
272#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
273#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
274#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
275#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
276#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
277#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
278#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
279#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
280#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
281#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
282#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
283#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
284#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
285#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
286#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
287#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
288#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
289#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
290#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
291#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
292#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
293#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
294#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
295#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
296#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
297#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
298#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
299#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
300#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
301#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
302#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
303#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
304#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
305#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
306#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
307#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
308#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
309#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
310#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
311#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
312#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
313#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
314#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
315#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
316#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
317#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
318#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
319#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
320#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
321#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
322#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
323#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
324#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
325#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
326#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
327#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
328#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
329#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
330#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
331#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
332#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
333#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
334#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
335#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
336#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
337#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
338#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
339#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
340#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
341#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
342#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
343#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
344#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
345#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
346#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
347#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
348#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
349#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
350#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
351#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
352#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
353#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
354#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
355#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
356#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
357#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
358#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
359#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
360#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
361#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
362#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
363#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
364#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
366#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
367#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
368#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
369#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
370#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
371#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
372#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
373#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
374#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
375#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
376#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
377#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
378#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
379#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
380#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
381#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
382#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
383#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
384#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
385#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
386#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
387#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
388#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
389#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
390#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
391#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
392#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
393#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
394#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
395#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
396#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
397#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
398#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
399#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
400#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
401#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
402#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
403#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
404#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
405#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
406#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
407#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
408#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
409#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
410#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
411#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
412#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
413#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
414#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
415#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
416#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
417#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
418#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
419#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
420#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
421#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
422#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
423#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
424#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
425#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
426#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
427#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
428#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
429#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
430#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
431#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
432#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
433#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
434#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
435#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
436#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
437#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
438#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
439#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
440#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
441#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
442#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
443#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
444#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
445#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
446#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
447#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
448#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
449#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
450#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
451#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
452#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
453#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
454#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
455#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
456#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
457#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
458#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
459#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
460#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
461#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
462#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
463#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
464#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
465#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
466#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
467#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
468#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
469#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
470#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
471#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
472#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
473#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
474#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
475#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
476#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
477#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
478#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
479#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
480#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
481#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
482#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
483#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
484#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
485#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
486#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
487#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
488#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
489#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
490#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
491#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
492#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
493#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
494#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
495#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
496#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
497#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
498#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
499#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
500#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
501#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
502#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
503#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
504#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
505#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
506#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
507#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
508#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
509#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
510#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
511#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
512#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
513#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
514#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
515#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
516#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
517#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
518#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
519#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
520#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
521#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
522#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
523#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
524#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
525#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
526#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
527#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
528#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
529#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
530#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
531#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
532#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
533#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
534#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
535#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
536#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
537#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
538#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
539#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
540#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
541#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
542#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
543#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
544#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
545#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
546#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
547#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
548#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
549#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
550#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
551#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
552#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
553#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
554#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
555#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
556#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
557#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
558#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
559#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
560#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
561#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
562#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
563#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
564#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
565#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
566#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
567#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
568#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
569#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
570#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
571#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
572#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
573#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
574#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
575#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
576#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
577#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
578#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
579#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
580#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
581#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
582#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
583#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
584#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
585#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
586#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
587#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
588#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
589#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
590#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
591#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
592#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
593#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
594#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
595#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
596#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
598#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
599#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
600#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
601#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
603#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
604#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
605#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
606#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
607#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
608#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
609#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
610#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
611#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
612#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
613#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
614#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
615#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
616#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
617#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
618#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
619#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
620#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
621#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
622#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
623#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
624#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
625#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
626#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
627#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
628#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
629#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
630#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
631#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
632#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
633#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
634#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
635#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
636#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
637#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
638#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
639#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
640#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
641#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
642#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
643#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
644#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
645#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
646#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
647#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
648#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
649#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
650#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
651#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
652#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
653#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
654#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
655#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
656#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
657#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
658#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
659#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
660#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
661#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
662#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
663#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
664#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
665#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
666#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
667#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
668#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
669#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
670#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
671#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
672#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
673#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
674#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
675#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
676#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
677#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
678#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
679#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
680#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
681#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
682#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
683#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
684#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
685#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
686#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
687#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
688#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
689#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
690#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
691#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
692#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
693#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
694#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
695#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
696#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
697#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
698#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
699#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
700#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
701#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
702#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
703#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
704#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
705#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
706#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
707#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
708#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
709#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
710#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
711#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
712#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
713#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
714#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
715#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
716#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
717#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
718#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
719#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
720#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
721#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
722#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
723#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
724#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
725#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
726#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
727#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
728#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
729#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
730#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
731#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
732#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
733#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
734#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
735#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
736#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
737#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
738#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
739#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
740#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
741#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
742#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
743#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
744#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
745#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
746#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
747#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
748#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
749#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
750#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
751#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
752#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
753#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
754#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
755#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
756#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
757#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
758#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
759#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
760#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
761#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
762#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
763#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
764#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
765#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
766#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
767#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
768#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
769#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
770#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
771#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
772#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
773#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
774#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
775#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
776#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
777#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
778#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
779#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
780#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
781#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
782#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
783#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
784#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
785#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
786#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
787#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
788#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
789#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
790#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
791#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
792#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
793#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
794#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
795#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
796#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
797#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000
798#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18
799#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
800#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
801#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
802#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
803#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
804#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
805#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
806#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
807#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
808#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
809#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
810#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
811#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
812#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
813#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
814#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
815#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
816#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
817#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
818#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
819#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
820#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
821#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
822#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
823#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
824#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
825#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
826#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
827#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
828#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
829#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
830#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
831#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
832#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
833#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
834#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
835#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
836#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
837#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
838#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
839#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
840#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
841#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
842#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
843#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
844#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
845#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
846#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
847#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
848#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
849#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
850#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
851#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
852#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
853#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
854#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
855#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
856#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
857#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
858#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
859#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
860#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
861#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
862#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
863#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
864#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
865#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
866#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
867#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
868#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
869#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
870#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
871#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
872#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
873#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
874#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
875#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
876#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
877#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
878#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
879#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
880#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
881#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
882#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
883#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
884#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
885#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
886#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
887#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
888#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
889#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
890#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
891#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1
892#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0
893#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2
894#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1
895#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4
896#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2
897#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8
898#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3
899#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10
900#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4
901#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20
902#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5
903#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40
904#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6
905#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80
906#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7
907#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100
908#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8
909#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200
910#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9
911#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400
912#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa
913#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800
914#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb
915#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1
916#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0
917#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2
918#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1
919#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4
920#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2
921#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8
922#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3
923#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10
924#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4
925#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20
926#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5
927#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40
928#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6
929#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80
930#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7
931#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100
932#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8
933#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3
934#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0
935#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4
936#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2
937#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8
938#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3
939#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10
940#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4
941#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20
942#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5
943#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40
944#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6
945#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80
946#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7
947#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100
948#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8
949#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f
950#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0
951#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0
952#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6
953#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00
954#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa
955#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000
956#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10
957#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
958#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
959#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
960#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
961#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
962#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
963#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1
964#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0
965#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2
966#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1
967#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4
968#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2
969#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8
970#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3
971#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10
972#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4
973#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20
974#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5
975#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40
976#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6
977#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80
978#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7
979#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff
980#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0
981#define CP_DFY_CNTL__POLICY_MASK 0x300
982#define CP_DFY_CNTL__POLICY__SHIFT 0x8
983#define CP_DFY_CNTL__VOL_MASK 0x400
984#define CP_DFY_CNTL__VOL__SHIFT 0xa
985#define CP_DFY_CNTL__ATC_MASK 0x800
986#define CP_DFY_CNTL__ATC__SHIFT 0xb
987#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
988#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
989#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000
990#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
991#define CP_DFY_STAT__BUSY_MASK 0x80000000
992#define CP_DFY_STAT__BUSY__SHIFT 0x1f
993#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
994#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
995#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
996#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
997#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
998#define CP_DFY_DATA_0__DATA__SHIFT 0x0
999#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
1000#define CP_DFY_DATA_1__DATA__SHIFT 0x0
1001#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
1002#define CP_DFY_DATA_2__DATA__SHIFT 0x0
1003#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
1004#define CP_DFY_DATA_3__DATA__SHIFT 0x0
1005#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
1006#define CP_DFY_DATA_4__DATA__SHIFT 0x0
1007#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
1008#define CP_DFY_DATA_5__DATA__SHIFT 0x0
1009#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
1010#define CP_DFY_DATA_6__DATA__SHIFT 0x0
1011#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
1012#define CP_DFY_DATA_7__DATA__SHIFT 0x0
1013#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
1014#define CP_DFY_DATA_8__DATA__SHIFT 0x0
1015#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
1016#define CP_DFY_DATA_9__DATA__SHIFT 0x0
1017#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
1018#define CP_DFY_DATA_10__DATA__SHIFT 0x0
1019#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
1020#define CP_DFY_DATA_11__DATA__SHIFT 0x0
1021#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
1022#define CP_DFY_DATA_12__DATA__SHIFT 0x0
1023#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
1024#define CP_DFY_DATA_13__DATA__SHIFT 0x0
1025#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
1026#define CP_DFY_DATA_14__DATA__SHIFT 0x0
1027#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
1028#define CP_DFY_DATA_15__DATA__SHIFT 0x0
1029#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
1030#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
1031#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
1032#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
1033#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
1034#define CP_RB_BASE__RB_BASE__SHIFT 0x0
1035#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
1036#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
1037#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
1038#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
1039#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
1040#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
1041#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
1042#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
1043#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
1044#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
1045#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000
1046#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
1047#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
1048#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1049#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1050#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1051#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000
1052#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
1053#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000
1054#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
1055#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
1056#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1057#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1058#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1059#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
1060#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1061#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
1062#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1063#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000
1064#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
1065#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
1066#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1067#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1068#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1069#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000
1070#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
1071#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000
1072#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
1073#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
1074#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1075#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1076#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1077#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
1078#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
1079#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
1080#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
1081#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
1082#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1083#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1084#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1085#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000
1086#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
1087#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000
1088#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
1089#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
1090#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1091#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1092#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1093#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
1094#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
1095#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
1096#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
1097#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
1098#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1099#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1100#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1101#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000
1102#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
1103#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000
1104#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
1105#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
1106#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1107#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1108#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1109#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
1110#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
1111#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1112#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1113#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1114#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1115#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1116#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1117#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1118#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1119#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1120#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1121#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1122#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1123#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1124#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1125#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1126#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1127#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1128#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1129#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1130#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1131#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1132#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1133#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1134#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1135#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
1136#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
1137#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
1138#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
1139#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
1140#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
1141#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
1142#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
1143#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc
1144#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2
1145#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff
1146#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0
1147#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1148#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1149#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1150#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1151#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1152#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1153#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1154#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1155#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1156#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1157#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1158#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1159#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1160#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1161#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1162#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1163#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1164#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1165#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1166#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1167#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1168#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1169#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1170#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1171#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1172#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1173#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1174#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1175#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1176#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1177#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1178#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1179#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1180#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1181#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
1182#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
1183#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1184#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1185#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1186#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1187#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1188#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1189#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
1190#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
1191#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
1192#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
1193#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
1194#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
1195#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1196#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1197#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1198#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1199#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1200#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1201#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1202#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1203#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1204#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1205#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
1206#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
1207#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1208#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1209#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1210#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1211#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1212#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1213#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
1214#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
1215#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
1216#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
1217#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
1218#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
1219#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1220#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1221#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1222#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1223#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1224#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1225#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1226#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1227#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1228#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1229#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
1230#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
1231#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1232#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1233#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1234#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1235#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1236#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1237#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
1238#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
1239#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
1240#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
1241#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
1242#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
1243#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1244#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1245#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1246#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1247#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
1248#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
1249#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
1250#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1251#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
1252#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
1253#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
1254#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
1255#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1256#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1257#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
1258#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
1259#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1260#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1261#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
1262#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
1263#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
1264#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
1265#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
1266#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
1267#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1268#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1269#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1270#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1271#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000
1272#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13
1273#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
1274#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1275#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
1276#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
1277#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
1278#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
1279#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1280#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1281#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
1282#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
1283#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1284#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1285#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
1286#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
1287#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
1288#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
1289#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
1290#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
1291#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1292#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1293#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1294#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1295#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
1296#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
1297#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
1298#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1299#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
1300#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
1301#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
1302#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
1303#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1304#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1305#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
1306#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
1307#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1308#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1309#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
1310#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
1311#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
1312#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
1313#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
1314#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
1315#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1316#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1317#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1318#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1319#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
1320#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
1321#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
1322#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1323#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
1324#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
1325#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
1326#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
1327#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1328#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1329#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
1330#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
1331#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1332#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1333#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
1334#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
1335#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
1336#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
1337#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
1338#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
1339#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
1340#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
1341#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1342#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1343#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1344#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1345#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1346#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1347#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1348#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1349#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1350#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1351#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1352#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1353#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1354#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1355#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1356#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1357#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
1358#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
1359#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1360#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1361#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
1362#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
1363#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1364#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1365#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
1366#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
1367#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1368#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1369#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
1370#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
1371#define CP_RB_VMID__RB0_VMID_MASK 0xf
1372#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
1373#define CP_RB_VMID__RB1_VMID_MASK 0xf00
1374#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
1375#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
1376#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
1377#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
1378#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
1379#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
1380#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
1381#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1382#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1383#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1384#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1385#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff
1386#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
1387#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff
1388#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
1389#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
1390#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
1391#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
1392#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
1393#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1394#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1395#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1396#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1397#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1398#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1399#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
1400#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
1401#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1402#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1403#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1404#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1405#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1406#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1407#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
1408#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
1409#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1410#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1411#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1412#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1413#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1414#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1415#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1416#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1417#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1418#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1419#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1420#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1421#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1422#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1423#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1424#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1425#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1426#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1427#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1428#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1429#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1430#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1431#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1432#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1433#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1
1434#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0
1435#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
1436#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
1437#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
1438#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
1439#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc
1440#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
1441#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
1442#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
1443#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
1444#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
1445#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
1446#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
1447#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
1448#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
1449#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0
1450#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4
1451#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00
1452#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa
1453#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
1454#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
1455#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3
1456#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0
1457#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0
1458#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4
1459#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00
1460#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa
1461#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000
1462#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10
1463#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3
1464#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0
1465#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0
1466#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4
1467#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00
1468#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa
1469#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000
1470#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10
1471#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3
1472#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0
1473#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0
1474#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4
1475#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00
1476#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa
1477#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000
1478#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10
1479#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1
1480#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
1481#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
1482#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
1483#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
1484#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
1485#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
1486#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
1487#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
1488#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
1489#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1490#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1491#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1492#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1493#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1494#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1495#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1496#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1497#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1498#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1499#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1500#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1501#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1502#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1503#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1504#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1505#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1506#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1507#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1508#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1509#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1510#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1511#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1512#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1513#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1514#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1515#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1516#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1517#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1518#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1519#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1520#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1521#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1522#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1523#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1524#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1525#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1526#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1527#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1528#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1529#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1530#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1531#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1532#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1533#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1534#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1535#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1536#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1537#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1538#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1539#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1540#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1541#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1542#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1543#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1544#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1545#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1546#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1547#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1548#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1549#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1550#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1551#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1552#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1553#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1554#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1555#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1556#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1557#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1558#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1559#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1560#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1561#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1562#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1563#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1564#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1565#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1566#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1567#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1568#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1569#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1570#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1571#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1572#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1573#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1574#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1575#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1576#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1577#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1578#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1579#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1580#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1581#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1582#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1583#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1584#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1585#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1586#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1587#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1588#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1589#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1590#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1591#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1592#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1593#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1594#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1595#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1596#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1597#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1598#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1599#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1600#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1601#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1602#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1603#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1604#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1605#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1606#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1607#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1608#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1609#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1610#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1611#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1612#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1613#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1614#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1615#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1616#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1617#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1618#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1619#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1620#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1621#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1622#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1623#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1624#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1625#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1626#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1627#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1628#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1629#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1630#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1631#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1632#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1633#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1634#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1635#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1636#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1637#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1638#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1639#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1640#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1641#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1642#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1643#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1644#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1645#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1646#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1647#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1648#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1649#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1650#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1651#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1652#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1653#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1654#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1655#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1656#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1657#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1658#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1659#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1660#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1661#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1662#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1663#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1664#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1665#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1666#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1667#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1668#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1669#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1670#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1671#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1672#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1673#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1674#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1675#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1676#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1677#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1678#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1679#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1680#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1681#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1682#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1683#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1684#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1685#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1686#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1687#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1688#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1689#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1690#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1691#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1692#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1693#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1694#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1695#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1696#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1697#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1698#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1699#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1700#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1701#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1702#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1703#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1704#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1705#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1706#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1707#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1708#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1709#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1710#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1711#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1712#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1713#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1714#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1715#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1716#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1717#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1718#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1719#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1720#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1721#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1722#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1723#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1724#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1725#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1726#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1727#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1728#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1729#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1730#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1731#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1732#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1733#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1734#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1735#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1736#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1737#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1738#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1739#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1740#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1741#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1742#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1743#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1744#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1745#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1746#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1747#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1748#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1749#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1750#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1751#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1752#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1753#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1754#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1755#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1756#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1757#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1758#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1759#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1760#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1761#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1762#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1763#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1764#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1765#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1766#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1767#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1768#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1769#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1770#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1771#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1772#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1773#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1774#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1775#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1776#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1777#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1778#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1779#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1780#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1781#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1782#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1783#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1784#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1785#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1786#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1787#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1788#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1789#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1790#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1791#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1792#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1793#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1794#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1795#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1796#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1797#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1798#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1799#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1800#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1801#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1802#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1803#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1804#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1805#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1806#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1807#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1808#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1809#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1810#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1811#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1812#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1813#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1814#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1815#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1816#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1817#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1818#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1819#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1820#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1821#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1822#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1823#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1824#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1825#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1826#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1827#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1828#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1829#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1830#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1831#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1832#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1833#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1834#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1835#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1836#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1837#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1838#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1839#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1840#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1841#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1842#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1843#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1844#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1845#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1846#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1847#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1848#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1849#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
1850#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
1851#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
1852#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
1853#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
1854#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
1855#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
1856#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
1857#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
1858#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
1859#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
1860#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
1861#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
1862#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
1863#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
1864#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
1865#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
1866#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
1867#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
1868#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
1869#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
1870#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
1871#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
1872#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
1873#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
1874#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
1875#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
1876#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
1877#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
1878#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
1879#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
1880#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
1881#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
1882#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
1883#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
1884#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
1885#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
1886#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
1887#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
1888#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
1889#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1890#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1891#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1892#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1893#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1894#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1895#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1896#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1897#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1898#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1899#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1900#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1901#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1902#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1903#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
1904#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
1905#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1906#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1907#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1908#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1909#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1910#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1911#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1912#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1913#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1914#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1915#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1916#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1917#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1918#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1919#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
1920#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
1921#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1922#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1923#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1924#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1925#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1926#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1927#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff
1928#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1929#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff
1930#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1931#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1932#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1933#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1934#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1935#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1936#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1937#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff
1938#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1939#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff
1940#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1941#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
1942#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
1943#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
1944#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
1945#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
1946#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
1947#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
1948#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
1949#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
1950#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
1951#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
1952#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
1953#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
1954#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
1955#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
1956#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
1957#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
1958#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
1959#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
1960#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
1961#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
1962#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
1963#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
1964#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
1965#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
1966#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
1967#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
1968#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
1969#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
1970#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
1971#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
1972#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
1973#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000
1974#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10
1975#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff
1976#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
1977#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
1978#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
1979#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
1980#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
1981#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
1982#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
1983#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
1984#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
1985#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
1986#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
1987#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
1988#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
1989#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
1990#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
1991#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
1992#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
1993#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
1994#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
1995#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
1996#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
1997#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100
1998#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8
1999#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200
2000#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9
2001#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
2002#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
2003#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
2004#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
2005#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
2006#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
2007#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
2008#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
2009#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
2010#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
2011#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
2012#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
2013#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
2014#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
2015#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
2016#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
2017#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
2018#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
2019#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
2020#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
2021#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
2022#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
2023#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
2024#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
2025#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
2026#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
2027#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
2028#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
2029#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
2030#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
2031#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
2032#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
2033#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
2034#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
2035#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
2036#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
2037#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
2038#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
2039#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
2040#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
2041#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
2042#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
2043#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
2044#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
2045#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
2046#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
2047#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
2048#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
2049#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
2050#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
2051#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
2052#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
2053#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
2054#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
2055#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
2056#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
2057#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
2058#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
2059#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
2060#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
2061#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
2062#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
2063#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
2064#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
2065#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
2066#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
2067#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
2068#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
2069#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1
2070#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0
2071#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2
2072#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1
2073#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
2074#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
2075#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
2076#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
2077#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
2078#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
2079#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
2080#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
2081#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
2082#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
2083#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
2084#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
2085#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800
2086#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb
2087#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000
2088#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc
2089#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
2090#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
2091#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
2092#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
2093#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
2094#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
2095#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
2096#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
2097#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000
2098#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13
2099#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000
2100#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14
2101#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
2102#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
2103#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
2104#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
2105#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
2106#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
2107#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4
2108#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2
2109#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8
2110#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3
2111#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
2112#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
2113#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
2114#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
2115#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
2116#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
2117#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
2118#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
2119#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
2120#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
2121#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
2122#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
2123#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
2124#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
2125#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
2126#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
2127#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
2128#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
2129#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
2130#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
2131#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
2132#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
2133#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
2134#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
2135#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
2136#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
2137#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
2138#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
2139#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2140#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2141#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
2142#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
2143#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
2144#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
2145#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
2146#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
2147#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
2148#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
2149#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
2150#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
2151#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
2152#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
2153#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
2154#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
2155#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
2156#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
2157#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
2158#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
2159#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
2160#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
2161#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
2162#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
2163#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
2164#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
2165#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
2166#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
2167#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
2168#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
2169#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
2170#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
2171#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
2172#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
2173#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
2174#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
2175#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
2176#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
2177#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
2178#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
2179#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
2180#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
2181#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
2182#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
2183#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
2184#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
2185#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
2186#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
2187#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
2188#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
2189#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
2190#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
2191#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
2192#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
2193#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
2194#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
2195#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
2196#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
2197#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
2198#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
2199#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
2200#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
2201#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
2202#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
2203#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
2204#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
2205#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
2206#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
2207#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
2208#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
2209#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10
2210#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4
2211#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
2212#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
2213#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
2214#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
2215#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f
2216#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0
2217#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
2218#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
2219#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
2220#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
2221#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
2222#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
2223#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
2224#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
2225#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
2226#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
2227#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
2228#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
2229#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2230#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2231#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2232#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2233#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
2234#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2235#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2236#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2237#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2238#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2239#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2240#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2241#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2242#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2243#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2244#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2245#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2246#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2247#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2248#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2249#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2250#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2251#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2252#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2253#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2254#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2255#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2256#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2257#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2258#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2259#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2260#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2261#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2262#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2263#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2264#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2265#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2266#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2267#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2268#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2269#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2270#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2271#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2272#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2273#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2274#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2275#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2276#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2277#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2278#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2279#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2280#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2281#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2282#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2283#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2284#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2285#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2286#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2287#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2288#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2289#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2290#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2291#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2292#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2293#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2294#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2295#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2296#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2297#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
2298#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
2299#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
2300#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
2301#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
2302#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
2303#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
2304#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
2305#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
2306#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
2307#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
2308#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
2309#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
2310#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
2311#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
2312#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
2313#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
2314#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
2315#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
2316#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
2317#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
2318#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
2319#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
2320#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
2321#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
2322#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
2323#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
2324#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
2325#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
2326#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
2327#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
2328#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
2329#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
2330#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
2331#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
2332#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
2333#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000
2334#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14
2335#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
2336#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
2337#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
2338#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
2339#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2340#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2341#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
2342#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
2343#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
2344#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
2345#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2346#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2347#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
2348#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
2349#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
2350#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
2351#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000
2352#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
2353#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000
2354#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
2355#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
2356#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
2357#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
2358#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
2359#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
2360#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
2361#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
2362#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
2363#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3
2364#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0
2365#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
2366#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
2367#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
2368#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
2369#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
2370#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
2371#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
2372#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
2373#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
2374#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
2375#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
2376#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
2377#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3
2378#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0
2379#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
2380#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
2381#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
2382#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
2383#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
2384#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
2385#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
2386#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
2387#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
2388#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
2389#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
2390#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
2391#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
2392#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
2393#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
2394#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
2395#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
2396#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
2397#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
2398#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
2399#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
2400#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
2401#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
2402#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
2403#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
2404#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
2405#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
2406#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
2407#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
2408#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
2409#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
2410#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
2411#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
2412#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
2413#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
2414#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
2415#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3
2416#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0
2417#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
2418#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
2419#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
2420#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
2421#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
2422#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
2423#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
2424#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
2425#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
2426#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
2427#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
2428#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
2429#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
2430#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
2431#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
2432#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
2433#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
2434#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
2435#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
2436#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
2437#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
2438#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
2439#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
2440#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
2441#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
2442#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
2443#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
2444#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
2445#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
2446#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
2447#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
2448#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
2449#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
2450#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
2451#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
2452#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
2453#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
2454#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
2455#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
2456#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
2457#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
2458#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
2459#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
2460#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
2461#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
2462#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
2463#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
2464#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
2465#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
2466#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
2467#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
2468#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
2469#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
2470#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
2471#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
2472#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
2473#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
2474#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
2475#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
2476#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
2477#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
2478#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
2479#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
2480#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
2481#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
2482#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
2483#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
2484#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
2485#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
2486#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
2487#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
2488#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
2489#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
2490#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
2491#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
2492#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
2493#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2494#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2495#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2496#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2497#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2498#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2499#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2500#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2501#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2502#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2503#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2504#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2505#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
2506#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
2507#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
2508#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
2509#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
2510#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
2511#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
2512#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
2513#define CP_APPEND_DATA__DATA_MASK 0xffffffff
2514#define CP_APPEND_DATA__DATA__SHIFT 0x0
2515#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
2516#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
2517#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
2518#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
2519#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2520#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2521#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2522#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2523#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2524#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2525#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2526#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2527#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2528#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2529#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2530#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2531#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2532#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2533#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2534#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2535#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2536#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2537#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2538#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2539#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2540#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2541#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2542#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2543#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
2544#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
2545#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
2546#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
2547#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
2548#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
2549#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
2550#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
2551#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
2552#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
2553#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
2554#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
2555#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
2556#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
2557#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
2558#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
2559#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
2560#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
2561#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
2562#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
2563#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
2564#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
2565#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
2566#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
2567#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
2568#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
2569#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
2570#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
2571#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
2572#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
2573#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
2574#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
2575#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
2576#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
2577#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
2578#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
2579#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
2580#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
2581#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
2582#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
2583#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
2584#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
2585#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
2586#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
2587#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
2588#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
2589#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
2590#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
2591#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
2592#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
2593#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
2594#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
2595#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
2596#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
2597#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
2598#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
2599#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
2600#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
2601#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
2602#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
2603#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
2604#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
2605#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
2606#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
2607#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
2608#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
2609#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
2610#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
2611#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
2612#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
2613#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
2614#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
2615#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
2616#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
2617#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000
2618#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10
2619#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
2620#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
2621#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
2622#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
2623#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
2624#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
2625#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
2626#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
2627#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
2628#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
2629#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
2630#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
2631#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
2632#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
2633#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
2634#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
2635#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
2636#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
2637#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
2638#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
2639#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
2640#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
2641#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
2642#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
2643#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
2644#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
2645#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
2646#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
2647#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
2648#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
2649#define CP_COHER_STATUS__MEID_MASK 0x3000000
2650#define CP_COHER_STATUS__MEID__SHIFT 0x18
2651#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
2652#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
2653#define CP_COHER_STATUS__STATUS_MASK 0x80000000
2654#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
2655#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
2656#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
2657#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
2658#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
2659#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
2660#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
2661#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
2662#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
2663#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
2664#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
2665#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
2666#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
2667#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
2668#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
2669#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
2670#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
2671#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
2672#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
2673#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
2674#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
2675#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
2676#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
2677#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
2678#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
2679#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
2680#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
2681#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
2682#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
2683#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000
2684#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf
2685#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
2686#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
2687#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
2688#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
2689#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
2690#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
2691#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000
2692#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b
2693#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
2694#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
2695#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
2696#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
2697#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
2698#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
2699#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
2700#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
2701#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
2702#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
2703#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
2704#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
2705#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
2706#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
2707#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
2708#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
2709#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
2710#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
2711#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
2712#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
2713#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
2714#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
2715#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
2716#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
2717#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
2718#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
2719#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
2720#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
2721#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
2722#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
2723#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
2724#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
2725#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000
2726#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf
2727#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
2728#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
2729#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
2730#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
2731#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
2732#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
2733#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000
2734#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b
2735#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
2736#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
2737#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
2738#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
2739#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
2740#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
2741#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
2742#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
2743#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
2744#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
2745#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
2746#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
2747#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
2748#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
2749#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
2750#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
2751#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
2752#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
2753#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
2754#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
2755#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
2756#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
2757#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
2758#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
2759#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
2760#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
2761#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
2762#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
2763#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
2764#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
2765#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
2766#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
2767#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
2768#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
2769#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
2770#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
2771#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
2772#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
2773#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
2774#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
2775#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000
2776#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf
2777#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
2778#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
2779#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
2780#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
2781#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
2782#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2783#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2784#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2785#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
2786#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
2787#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
2788#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
2789#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
2790#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
2791#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
2792#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
2793#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
2794#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
2795#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
2796#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
2797#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
2798#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
2799#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
2800#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
2801#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
2802#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
2803#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
2804#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
2805#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
2806#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
2807#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
2808#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
2809#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
2810#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
2811#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
2812#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
2813#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
2814#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
2815#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
2816#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
2817#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
2818#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
2819#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000
2820#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe
2821#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
2822#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
2823#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000
2824#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10
2825#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000
2826#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11
2827#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
2828#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
2829#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
2830#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
2831#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
2832#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
2833#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
2834#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
2835#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
2836#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
2837#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
2838#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
2839#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
2840#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
2841#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
2842#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
2843#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
2844#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
2845#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
2846#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
2847#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
2848#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
2849#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
2850#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
2851#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40
2852#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6
2853#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80
2854#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7
2855#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
2856#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
2857#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
2858#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
2859#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
2860#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
2861#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
2862#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
2863#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
2864#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
2865#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
2866#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
2867#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
2868#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
2869#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
2870#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
2871#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
2872#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
2873#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
2874#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
2875#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
2876#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
2877#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
2878#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
2879#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
2880#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
2881#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
2882#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
2883#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
2884#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
2885#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
2886#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
2887#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
2888#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
2889#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
2890#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
2891#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
2892#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
2893#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
2894#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
2895#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
2896#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
2897#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
2898#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
2899#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
2900#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
2901#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
2902#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
2903#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
2904#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
2905#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
2906#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
2907#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
2908#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
2909#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
2910#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
2911#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
2912#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
2913#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
2914#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
2915#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
2916#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
2917#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
2918#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
2919#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100
2920#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8
2921#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
2922#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
2923#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
2924#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
2925#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
2926#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
2927#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
2928#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
2929#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
2930#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
2931#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
2932#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
2933#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2934#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2935#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
2936#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
2937#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
2938#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
2939#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
2940#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
2941#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
2942#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
2943#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
2944#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
2945#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
2946#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
2947#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
2948#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
2949#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
2950#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
2951#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
2952#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
2953#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
2954#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
2955#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
2956#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
2957#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
2958#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
2959#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
2960#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
2961#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
2962#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
2963#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
2964#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
2965#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80
2966#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7
2967#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100
2968#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8
2969#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
2970#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
2971#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
2972#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
2973#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
2974#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
2975#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
2976#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
2977#define CP_STAT__DC_BUSY_MASK 0x2000
2978#define CP_STAT__DC_BUSY__SHIFT 0xd
2979#define CP_STAT__PFP_BUSY_MASK 0x8000
2980#define CP_STAT__PFP_BUSY__SHIFT 0xf
2981#define CP_STAT__MEQ_BUSY_MASK 0x10000
2982#define CP_STAT__MEQ_BUSY__SHIFT 0x10
2983#define CP_STAT__ME_BUSY_MASK 0x20000
2984#define CP_STAT__ME_BUSY__SHIFT 0x11
2985#define CP_STAT__QUERY_BUSY_MASK 0x40000
2986#define CP_STAT__QUERY_BUSY__SHIFT 0x12
2987#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
2988#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
2989#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
2990#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
2991#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
2992#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
2993#define CP_STAT__DMA_BUSY_MASK 0x400000
2994#define CP_STAT__DMA_BUSY__SHIFT 0x16
2995#define CP_STAT__RCIU_BUSY_MASK 0x800000
2996#define CP_STAT__RCIU_BUSY__SHIFT 0x17
2997#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
2998#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
2999#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
3000#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
3001#define CP_STAT__CE_BUSY_MASK 0x4000000
3002#define CP_STAT__CE_BUSY__SHIFT 0x1a
3003#define CP_STAT__TCIU_BUSY_MASK 0x8000000
3004#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
3005#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
3006#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
3007#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
3008#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
3009#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
3010#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
3011#define CP_STAT__CP_BUSY_MASK 0x80000000
3012#define CP_STAT__CP_BUSY__SHIFT 0x1f
3013#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
3014#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
3015#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
3016#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
3017#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
3018#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
3019#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
3020#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
3021#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
3022#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
3023#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
3024#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
3025#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f
3026#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0
3027#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f
3028#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0
3029#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000
3030#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10
3031#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff
3032#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0
3033#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
3034#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
3035#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00
3036#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
3037#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
3038#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
3039#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
3040#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
3041#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
3042#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
3043#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
3044#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
3045#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
3046#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
3047#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
3048#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
3049#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
3050#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
3051#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
3052#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
3053#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
3054#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
3055#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
3056#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
3057#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
3058#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
3059#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
3060#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
3061#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
3062#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
3063#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
3064#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
3065#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1
3066#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0
3067#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
3068#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
3069#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
3070#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
3071#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
3072#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
3073#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
3074#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
3075#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
3076#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
3077#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
3078#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
3079#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
3080#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
3081#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
3082#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
3083#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
3084#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
3085#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
3086#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
3087#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
3088#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
3089#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3090#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3091#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3092#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3093#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3094#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3095#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3096#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3097#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3098#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3099#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3100#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3101#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3102#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3103#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3104#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3105#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3106#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3107#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3108#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3109#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3110#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3111#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3112#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3113#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
3114#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
3115#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
3116#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
3117#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
3118#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
3119#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
3120#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
3121#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
3122#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
3123#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
3124#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
3125#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
3126#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
3127#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
3128#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
3129#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
3130#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
3131#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
3132#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
3133#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
3134#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
3135#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
3136#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
3137#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
3138#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
3139#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
3140#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
3141#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
3142#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
3143#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
3144#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
3145#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
3146#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
3147#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
3148#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
3149#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
3150#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
3151#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
3152#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
3153#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
3154#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
3155#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
3156#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
3157#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
3158#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
3159#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
3160#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
3161#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
3162#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
3163#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
3164#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
3165#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
3166#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
3167#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
3168#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
3169#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000
3170#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
3171#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
3172#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
3173#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
3174#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
3175#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
3176#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
3177#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
3178#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
3179#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
3180#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
3181#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
3182#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
3183#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
3184#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
3185#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
3186#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
3187#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
3188#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
3189#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
3190#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
3191#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
3192#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
3193#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
3194#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
3195#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
3196#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
3197#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
3198#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
3199#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
3200#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
3201#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
3202#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
3203#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
3204#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
3205#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
3206#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
3207#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
3208#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
3209#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
3210#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
3211#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
3212#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
3213#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
3214#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
3215#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
3216#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
3217#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
3218#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
3219#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
3220#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
3221#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
3222#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
3223#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
3224#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
3225#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
3226#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
3227#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
3228#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
3229#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
3230#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
3231#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
3232#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
3233#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
3234#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
3235#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
3236#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
3237#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
3238#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
3239#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
3240#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
3241#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
3242#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
3243#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
3244#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
3245#define CP_RINGID__RINGID_MASK 0x3
3246#define CP_RINGID__RINGID__SHIFT 0x0
3247#define CP_PIPEID__PIPE_ID_MASK 0x3
3248#define CP_PIPEID__PIPE_ID__SHIFT 0x0
3249#define CP_VMID__VMID_MASK 0xf
3250#define CP_VMID__VMID__SHIFT 0x0
3251#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
3252#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
3253#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
3254#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
3255#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
3256#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
3257#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
3258#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
3259#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
3260#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3261#define CP_HPD_EOP_VMID__VMID_MASK 0xf
3262#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0
3263#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
3264#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
3265#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
3266#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
3267#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00
3268#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9
3269#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
3270#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
3271#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
3272#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
3273#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
3274#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
3275#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000
3276#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
3277#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000
3278#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
3279#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000
3280#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a
3281#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000
3282#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c
3283#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
3284#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
3285#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
3286#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
3287#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
3288#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3289#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
3290#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
3291#define CP_HQD_VMID__VMID_MASK 0xf
3292#define CP_HQD_VMID__VMID__SHIFT 0x0
3293#define CP_HQD_VMID__IB_VMID_MASK 0xf00
3294#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
3295#define CP_HQD_VMID__VQID_MASK 0x3ff0000
3296#define CP_HQD_VMID__VQID__SHIFT 0x10
3297#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
3298#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
3299#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
3300#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
3301#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
3302#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
3303#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
3304#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
3305#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
3306#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
3307#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
3308#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
3309#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
3310#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
3311#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
3312#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
3313#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
3314#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
3315#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
3316#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
3317#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
3318#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3319#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
3320#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
3321#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
3322#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
3323#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
3324#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
3325#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
3326#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
3327#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
3328#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
3329#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
3330#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
3331#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
3332#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
3333#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
3334#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
3335#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
3336#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
3337#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
3338#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
3339#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
3340#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
3341#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
3342#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
3343#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000
3344#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10
3345#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
3346#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
3347#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
3348#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
3349#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000
3350#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
3351#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000
3352#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a
3353#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
3354#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
3355#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
3356#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
3357#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
3358#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
3359#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
3360#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
3361#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
3362#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
3363#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
3364#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
3365#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
3366#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
3367#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
3368#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3369#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
3370#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
3371#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
3372#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
3373#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
3374#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
3375#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000
3376#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
3377#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000
3378#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a
3379#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
3380#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
3381#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
3382#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
3383#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
3384#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
3385#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
3386#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
3387#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
3388#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
3389#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
3390#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
3391#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000
3392#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
3393#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000
3394#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a
3395#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
3396#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
3397#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
3398#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
3399#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
3400#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
3401#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
3402#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
3403#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3
3404#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
3405#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
3406#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
3407#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
3408#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
3409#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
3410#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
3411#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
3412#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
3413#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
3414#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
3415#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3
3416#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
3417#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
3418#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
3419#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
3420#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
3421#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
3422#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
3423#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
3424#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
3425#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3
3426#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0
3427#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc
3428#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2
3429#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30
3430#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4
3431#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40
3432#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6
3433#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80
3434#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7
3435#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100
3436#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8
3437#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200
3438#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9
3439#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400
3440#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa
3441#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800
3442#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb
3443#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
3444#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
3445#define CP_MQD_CONTROL__VMID_MASK 0xf
3446#define CP_MQD_CONTROL__VMID__SHIFT 0x0
3447#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
3448#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
3449#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000
3450#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
3451#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000
3452#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a
3453#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
3454#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
3455#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
3456#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
3457#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
3458#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
3459#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
3460#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
3461#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
3462#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
3463#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
3464#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
3465#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
3466#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
3467#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
3468#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
3469#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
3470#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
3471#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
3472#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
3473#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
3474#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
3475#define DB_Z_INFO__FORMAT_MASK 0x3
3476#define DB_Z_INFO__FORMAT__SHIFT 0x0
3477#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
3478#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
3479#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
3480#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
3481#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
3482#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
3483#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
3484#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
3485#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
3486#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
3487#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
3488#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
3489#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
3490#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
3491#define DB_STENCIL_INFO__FORMAT_MASK 0x1
3492#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
3493#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
3494#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
3495#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
3496#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
3497#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
3498#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
3499#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
3500#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
3501#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
3502#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
3503#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
3504#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
3505#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
3506#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
3507#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
3508#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
3509#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
3510#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
3511#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
3512#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
3513#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
3514#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
3515#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
3516#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
3517#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
3518#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
3519#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
3520#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
3521#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
3522#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
3523#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
3524#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
3525#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
3526#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
3527#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
3528#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
3529#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
3530#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
3531#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
3532#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
3533#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
3534#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
3535#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
3536#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
3537#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
3538#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
3539#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
3540#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
3541#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
3542#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
3543#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
3544#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
3545#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
3546#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
3547#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
3548#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
3549#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
3550#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
3551#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
3552#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
3553#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
3554#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
3555#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
3556#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
3557#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
3558#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
3559#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
3560#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
3561#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
3562#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
3563#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
3564#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
3565#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
3566#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
3567#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
3568#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
3569#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
3570#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
3571#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
3572#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
3573#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
3574#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
3575#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
3576#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
3577#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
3578#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
3579#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
3580#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
3581#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
3582#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
3583#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
3584#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
3585#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
3586#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
3587#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
3588#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
3589#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
3590#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
3591#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
3592#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
3593#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
3594#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
3595#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
3596#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
3597#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
3598#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
3599#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
3600#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
3601#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
3602#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
3603#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
3604#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
3605#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
3606#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
3607#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
3608#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
3609#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
3610#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
3611#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
3612#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
3613#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
3614#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
3615#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
3616#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
3617#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
3618#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
3619#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
3620#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
3621#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
3622#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
3623#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
3624#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
3625#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
3626#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
3627#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
3628#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
3629#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
3630#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
3631#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
3632#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
3633#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
3634#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
3635#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
3636#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
3637#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
3638#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
3639#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
3640#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
3641#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
3642#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
3643#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
3644#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
3645#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
3646#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
3647#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
3648#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
3649#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
3650#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
3651#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
3652#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
3653#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
3654#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
3655#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
3656#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
3657#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
3658#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
3659#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
3660#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
3661#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
3662#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
3663#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
3664#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
3665#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
3666#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
3667#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
3668#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
3669#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
3670#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
3671#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
3672#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
3673#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
3674#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
3675#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
3676#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
3677#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
3678#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
3679#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
3680#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
3681#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
3682#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
3683#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
3684#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
3685#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
3686#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
3687#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
3688#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
3689#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
3690#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
3691#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
3692#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
3693#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
3694#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
3695#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
3696#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
3697#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
3698#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
3699#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
3700#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
3701#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
3702#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
3703#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
3704#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
3705#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
3706#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
3707#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
3708#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
3709#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
3710#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
3711#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
3712#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
3713#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
3714#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
3715#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
3716#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
3717#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
3718#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
3719#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
3720#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
3721#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
3722#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
3723#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
3724#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
3725#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
3726#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
3727#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
3728#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
3729#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
3730#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
3731#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
3732#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
3733#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
3734#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
3735#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
3736#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
3737#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
3738#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
3739#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
3740#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
3741#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
3742#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
3743#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
3744#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
3745#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
3746#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
3747#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
3748#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
3749#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
3750#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
3751#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
3752#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
3753#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
3754#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
3755#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
3756#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
3757#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
3758#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
3759#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
3760#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
3761#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
3762#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
3763#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
3764#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
3765#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
3766#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
3767#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
3768#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
3769#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
3770#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
3771#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
3772#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
3773#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
3774#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
3775#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
3776#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
3777#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
3778#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
3779#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
3780#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
3781#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
3782#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
3783#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
3784#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
3785#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
3786#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3787#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
3788#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3789#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
3790#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
3791#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
3792#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
3793#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
3794#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
3795#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
3796#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
3797#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
3798#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
3799#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
3800#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
3801#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
3802#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
3803#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
3804#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
3805#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
3806#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
3807#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
3808#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
3809#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
3810#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
3811#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
3812#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
3813#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
3814#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
3815#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
3816#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
3817#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
3818#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
3819#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
3820#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
3821#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
3822#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
3823#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
3824#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
3825#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
3826#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3827#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
3828#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
3829#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
3830#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
3831#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
3832#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
3833#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
3834#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
3835#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
3836#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
3837#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
3838#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
3839#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
3840#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
3841#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
3842#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
3843#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
3844#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
3845#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
3846#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
3847#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
3848#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
3849#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
3850#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
3851#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
3852#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
3853#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
3854#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
3855#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
3856#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
3857#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
3858#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
3859#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
3860#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
3861#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
3862#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
3863#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
3864#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
3865#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
3866#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
3867#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
3868#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
3869#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
3870#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
3871#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
3872#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
3873#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
3874#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
3875#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
3876#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
3877#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
3878#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
3879#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
3880#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
3881#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
3882#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
3883#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
3884#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
3885#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
3886#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
3887#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
3888#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
3889#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
3890#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
3891#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
3892#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
3893#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
3894#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
3895#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
3896#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
3897#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
3898#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
3899#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
3900#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
3901#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
3902#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
3903#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
3904#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
3905#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
3906#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
3907#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
3908#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
3909#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
3910#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
3911#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
3912#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
3913#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
3914#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
3915#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
3916#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
3917#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
3918#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
3919#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
3920#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
3921#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
3922#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
3923#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
3924#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
3925#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
3926#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
3927#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
3928#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
3929#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
3930#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
3931#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
3932#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
3933#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
3934#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
3935#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
3936#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
3937#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
3938#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
3939#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
3940#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
3941#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
3942#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
3943#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
3944#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
3945#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
3946#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
3947#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
3948#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
3949#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
3950#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
3951#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
3952#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
3953#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
3954#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
3955#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
3956#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
3957#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
3958#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
3959#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
3960#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
3961#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
3962#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
3963#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
3964#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
3965#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
3966#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
3967#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
3968#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
3969#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
3970#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
3971#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
3972#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
3973#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
3974#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
3975#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
3976#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
3977#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
3978#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
3979#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
3980#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
3981#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
3982#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
3983#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
3984#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
3985#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
3986#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
3987#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
3988#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
3989#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
3990#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
3991#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
3992#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
3993#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
3994#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
3995#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
3996#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
3997#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
3998#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
3999#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000
4000#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e
4001#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
4002#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
4003#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
4004#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
4005#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
4006#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
4007#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
4008#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
4009#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
4010#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
4011#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
4012#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
4013#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
4014#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
4015#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
4016#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4017#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
4018#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
4019#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
4020#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
4021#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
4022#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
4023#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
4024#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
4025#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
4026#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
4027#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
4028#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
4029#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
4030#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
4031#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
4032#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
4033#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
4034#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
4035#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
4036#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
4037#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
4038#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
4039#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
4040#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
4041#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
4042#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
4043#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
4044#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
4045#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
4046#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
4047#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
4048#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
4049#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
4050#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4051#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
4052#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
4053#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
4054#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
4055#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
4056#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
4057#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
4058#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
4059#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
4060#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
4061#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
4062#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
4063#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
4064#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
4065#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
4066#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
4067#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
4068#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
4069#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
4070#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
4071#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
4072#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
4073#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
4074#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4075#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
4076#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
4077#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
4078#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
4079#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
4080#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
4081#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
4082#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
4083#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
4084#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
4085#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
4086#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
4087#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
4088#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
4089#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
4090#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
4091#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
4092#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
4093#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
4094#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
4095#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
4096#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
4097#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
4098#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
4099#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
4100#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
4101#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
4102#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
4103#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
4104#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
4105#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
4106#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
4107#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
4108#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
4109#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
4110#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
4111#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
4112#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
4113#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
4114#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
4115#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
4116#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
4117#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
4118#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
4119#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
4120#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
4121#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
4122#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
4123#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
4124#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
4125#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
4126#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
4127#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
4128#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
4129#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
4130#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
4131#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
4132#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
4133#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
4134#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
4135#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
4136#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
4137#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
4138#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
4139#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
4140#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
4141#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
4142#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
4143#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
4144#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
4145#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
4146#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
4147#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
4148#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
4149#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
4150#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
4151#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
4152#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
4153#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
4154#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
4155#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
4156#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
4157#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
4158#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
4159#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
4160#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
4161#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
4162#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
4163#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4164#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4165#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4166#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4167#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4168#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4169#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4170#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4171#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4172#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4173#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4174#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4175#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4176#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4177#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4178#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4179#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4180#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4181#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4182#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4183#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
4184#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
4185#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
4186#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
4187#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
4188#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
4189#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
4190#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
4191#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
4192#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
4193#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
4194#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
4195#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
4196#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
4197#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
4198#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
4199#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
4200#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
4201#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
4202#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
4203#define GB_GPU_ID__GPU_ID_MASK 0xf
4204#define GB_GPU_ID__GPU_ID__SHIFT 0x0
4205#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
4206#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
4207#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
4208#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
4209#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
4210#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
4211#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
4212#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
4213#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
4214#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
4215#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
4216#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
4217#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
4218#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
4219#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
4220#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
4221#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
4222#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
4223#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
4224#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
4225#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
4226#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
4227#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4228#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
4229#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
4230#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
4231#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
4232#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
4233#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
4234#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
4235#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
4236#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
4237#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4238#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
4239#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
4240#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
4241#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
4242#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
4243#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
4244#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
4245#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
4246#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
4247#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4248#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
4249#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
4250#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
4251#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
4252#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
4253#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
4254#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
4255#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
4256#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
4257#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4258#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
4259#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
4260#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
4261#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
4262#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
4263#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
4264#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
4265#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
4266#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
4267#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4268#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
4269#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
4270#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
4271#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
4272#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
4273#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
4274#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
4275#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
4276#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
4277#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4278#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
4279#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
4280#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
4281#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
4282#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
4283#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
4284#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
4285#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
4286#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
4287#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4288#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
4289#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
4290#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
4291#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
4292#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
4293#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
4294#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
4295#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
4296#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
4297#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4298#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
4299#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
4300#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
4301#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
4302#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
4303#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
4304#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
4305#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
4306#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
4307#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4308#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
4309#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
4310#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
4311#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
4312#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
4313#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
4314#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
4315#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
4316#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
4317#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4318#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
4319#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
4320#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
4321#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
4322#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
4323#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
4324#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
4325#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
4326#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
4327#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4328#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
4329#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
4330#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
4331#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
4332#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
4333#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
4334#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
4335#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
4336#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
4337#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4338#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
4339#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
4340#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
4341#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
4342#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
4343#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
4344#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
4345#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
4346#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
4347#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4348#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
4349#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
4350#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
4351#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
4352#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
4353#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
4354#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
4355#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
4356#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
4357#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4358#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
4359#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
4360#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
4361#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
4362#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
4363#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
4364#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
4365#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
4366#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
4367#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4368#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
4369#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
4370#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
4371#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
4372#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
4373#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
4374#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
4375#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
4376#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
4377#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4378#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
4379#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
4380#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
4381#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
4382#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
4383#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
4384#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
4385#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
4386#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
4387#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4388#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
4389#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
4390#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
4391#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
4392#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
4393#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
4394#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
4395#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
4396#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
4397#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4398#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
4399#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
4400#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
4401#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
4402#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
4403#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
4404#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
4405#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
4406#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
4407#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4408#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
4409#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
4410#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
4411#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
4412#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
4413#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
4414#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
4415#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
4416#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
4417#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4418#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
4419#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
4420#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
4421#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
4422#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
4423#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
4424#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
4425#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
4426#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
4427#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4428#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
4429#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
4430#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
4431#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
4432#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
4433#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
4434#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
4435#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
4436#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
4437#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4438#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
4439#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
4440#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
4441#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
4442#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
4443#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
4444#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
4445#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
4446#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
4447#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4448#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
4449#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
4450#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
4451#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
4452#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
4453#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
4454#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
4455#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
4456#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
4457#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4458#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
4459#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
4460#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
4461#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
4462#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
4463#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
4464#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
4465#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
4466#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
4467#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4468#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
4469#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
4470#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
4471#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
4472#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
4473#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
4474#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
4475#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
4476#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
4477#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4478#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
4479#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
4480#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
4481#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
4482#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
4483#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
4484#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
4485#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
4486#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
4487#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4488#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
4489#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
4490#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
4491#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
4492#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
4493#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
4494#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
4495#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
4496#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
4497#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4498#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
4499#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
4500#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
4501#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
4502#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
4503#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
4504#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
4505#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
4506#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
4507#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4508#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
4509#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
4510#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
4511#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
4512#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
4513#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
4514#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
4515#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
4516#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
4517#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4518#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
4519#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
4520#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
4521#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
4522#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
4523#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
4524#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
4525#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
4526#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
4527#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4528#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
4529#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
4530#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
4531#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
4532#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
4533#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
4534#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
4535#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
4536#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
4537#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4538#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
4539#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
4540#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
4541#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
4542#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
4543#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
4544#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
4545#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
4546#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
4547#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
4548#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
4549#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
4550#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
4551#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
4552#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
4553#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
4554#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
4555#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
4556#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
4557#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
4558#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
4559#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
4560#define