1/*
2 * GFX_8_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_8_0_SH_MASK_H
25#define GFX_8_0_SH_MASK_H
26
27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
37#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
38#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
39#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
40#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
41#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
42#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
43#define CB_COLOR_CONTROL__MODE_MASK 0x70
44#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
45#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
46#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
47#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
48#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
49#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
50#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
51#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
52#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
53#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
54#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
55#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
56#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
57#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
58#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
59#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
60#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
61#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
62#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
63#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
64#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
65#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
66#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
67#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
68#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
69#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
70#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
71#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
72#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
73#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
74#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
75#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
76#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
77#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
78#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
79#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
80#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
81#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
82#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
83#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
84#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
85#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
86#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
87#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
88#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
89#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
90#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
91#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
92#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
93#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
94#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
95#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
96#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
97#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
98#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
99#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
100#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
101#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
102#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
103#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
104#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
105#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
106#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
107#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
108#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
109#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
110#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
111#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
112#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
113#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
114#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
115#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
116#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
117#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
118#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
119#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
120#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
121#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
122#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
123#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
124#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
125#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
126#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
127#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
128#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
129#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
130#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
131#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
132#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
133#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
134#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
135#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
136#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
137#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
138#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
139#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
140#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
141#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
142#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
143#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
144#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
145#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
146#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
147#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
148#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
149#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
150#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
151#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
152#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
153#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
154#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
155#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
156#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
157#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
158#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
159#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
160#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
161#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
162#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
163#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
164#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
165#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
166#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
167#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
168#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
169#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
170#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
171#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
172#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
173#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
174#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
175#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
176#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
177#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
178#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
179#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
180#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
181#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
182#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
183#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
184#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
185#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
186#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
187#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
188#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
189#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
190#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
191#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
192#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
193#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
194#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
195#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
196#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
197#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
198#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
199#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
200#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
201#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
202#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
203#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
204#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
205#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
206#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
207#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
208#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
209#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
210#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
211#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
212#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
213#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
214#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
215#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
216#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
217#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
218#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
219#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
220#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
221#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
222#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
223#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
224#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
225#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
226#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
227#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
228#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
229#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
230#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
231#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
232#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
233#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
234#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
235#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
236#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
237#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
238#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
239#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
240#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
241#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
242#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
243#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
244#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
245#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
246#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
247#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
248#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
249#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
250#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
251#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
252#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
253#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
254#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
255#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
256#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
257#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
258#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
259#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
260#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
261#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
262#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
263#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
264#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
265#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
266#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
267#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
268#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
269#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
270#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
271#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
272#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
273#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
274#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
275#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
276#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
277#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
278#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
279#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
280#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
281#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
282#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
283#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
284#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
285#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
286#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
287#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
288#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
289#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
290#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
291#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
292#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
293#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
294#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
295#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
296#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
297#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
298#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
299#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
300#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
301#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
302#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
303#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
304#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
305#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
306#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
307#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
308#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
309#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
310#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
311#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
312#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
313#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
314#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
315#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
316#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
317#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
318#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
319#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
320#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
321#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
322#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
323#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
324#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
325#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
326#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
327#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
328#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
329#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
330#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
331#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
332#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
333#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
334#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
335#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
336#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
337#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
338#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
339#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
340#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
341#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
342#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
343#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
344#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
345#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
346#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
347#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
348#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
349#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
350#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
351#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
352#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
353#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
354#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
355#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
356#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
357#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
358#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
359#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
360#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
361#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
362#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
363#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
364#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
365#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
366#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
367#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
368#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
369#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
370#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
371#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
372#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
373#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
374#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
375#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
376#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
377#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
378#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
379#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
380#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
381#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
382#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
383#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
384#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
385#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
386#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
387#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
388#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
389#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
390#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
391#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
392#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
393#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
394#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
395#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
396#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
397#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
398#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
399#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
400#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
401#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
402#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
403#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
404#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
405#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
406#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
407#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
408#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
409#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
410#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
411#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
412#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
413#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
414#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
415#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
416#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
417#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
418#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
419#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
420#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
421#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
422#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
423#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
424#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
425#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
426#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
427#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
428#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
429#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
430#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
431#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
432#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
433#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
434#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
435#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
436#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
437#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
438#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
439#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
440#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
441#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
442#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
443#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
444#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
445#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
446#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
447#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
448#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
449#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
450#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
451#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
452#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
453#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
454#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
455#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
456#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
457#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
458#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
459#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
460#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
461#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
462#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
463#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
464#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
465#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
466#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
467#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
468#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
469#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
470#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
471#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
472#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
473#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
474#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
475#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
476#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
477#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
478#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
479#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
480#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
481#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
482#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
483#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
484#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
485#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
486#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
487#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
488#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
489#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
490#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
491#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
492#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
493#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
494#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
495#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
496#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
497#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
498#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
499#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
500#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
501#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
502#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
503#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
504#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
505#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
506#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
507#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
508#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
509#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
510#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
511#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
512#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
513#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
514#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
515#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
516#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
517#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
518#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
519#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
520#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
521#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
522#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
523#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
524#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
525#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
526#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
527#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
528#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
529#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
530#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
531#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
532#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
533#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
534#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
535#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
536#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
537#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
538#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
539#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
540#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
541#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
542#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
543#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
544#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
545#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
546#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
547#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
548#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
549#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
550#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
551#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
552#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
553#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
554#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
555#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
556#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
557#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
558#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
559#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
560#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
561#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
562#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
563#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
564#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
565#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
566#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
567#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
568#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
569#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
570#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
571#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
572#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
573#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
574#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
575#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
576#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
577#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
578#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
579#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
580#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
581#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
582#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
583#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
584#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
585#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
586#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
587#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
588#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
589#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
590#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
591#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
592#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
593#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
594#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
595#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
596#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
597#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
598#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
599#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
600#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
601#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
602#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
603#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
604#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
605#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
606#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
607#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
608#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
609#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
610#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
611#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
612#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
613#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
614#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
615#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
616#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
617#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
618#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
619#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
620#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
621#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
622#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
623#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
624#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
625#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
626#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
627#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
628#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
629#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
630#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
631#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
632#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
633#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
634#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
635#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
636#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
637#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
638#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
639#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
640#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
641#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
642#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
643#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
644#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
645#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
646#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
647#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
648#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
649#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
650#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
651#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
652#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
653#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
654#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
655#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
656#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
657#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
658#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
659#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
660#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
661#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
662#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
663#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
664#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
665#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
666#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
667#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
668#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
669#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
670#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
671#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
672#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
673#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
674#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
675#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
676#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
677#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
678#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
679#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
680#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
681#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
682#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
683#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
684#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
685#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
686#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
687#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
688#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
689#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
690#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
691#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
692#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
693#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
694#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
695#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
696#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
697#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
698#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
699#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
700#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
701#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
702#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
703#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
704#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
705#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
706#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
707#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
708#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
709#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
710#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
711#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
712#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
713#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
714#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
715#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
716#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
717#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
718#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
719#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
720#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
721#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
722#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
723#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
724#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
725#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
726#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
727#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
728#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
729#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
730#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
731#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
732#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
733#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
734#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
735#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
736#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
737#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
738#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
739#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
740#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
741#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
742#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
743#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
744#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
745#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
746#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
747#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
748#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
749#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
750#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
751#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
752#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
753#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
754#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
755#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
756#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
757#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
758#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
759#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
760#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
761#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
762#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
763#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
764#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
765#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
766#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
767#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
768#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
769#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
770#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
771#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
772#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
773#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
774#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
775#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
776#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
777#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
778#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
779#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
780#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
781#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
782#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
783#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
784#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
785#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
786#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
787#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
788#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
789#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
790#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
791#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
792#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
793#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
794#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
795#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
796#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
797#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
798#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
799#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
800#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
801#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
802#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
803#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
804#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
805#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
806#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
807#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
808#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
809#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
810#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
811#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
812#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
813#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
814#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
815#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
816#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
817#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
818#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
819#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
820#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
821#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
822#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
823#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
824#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
825#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
826#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
827#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
828#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
829#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
830#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
831#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
832#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
833#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
834#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
835#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
836#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
837#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
838#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
839#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
840#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
841#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
842#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
843#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
844#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
845#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
846#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
847#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
848#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
849#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
850#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
851#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
852#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
853#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
854#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
855#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
856#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
857#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
858#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
859#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
860#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
861#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
862#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
863#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
864#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
865#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
866#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
867#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
868#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
869#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
870#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
871#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
872#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
873#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
874#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
875#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
876#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
877#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
878#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
879#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
880#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
881#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
882#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
883#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
884#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
885#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
886#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
887#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
888#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
889#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
890#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
891#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
892#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
893#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
894#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
895#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
896#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
897#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
898#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
899#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
900#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
901#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
902#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
903#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
904#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
905#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
906#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
907#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
908#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
909#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
910#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
911#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
912#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
913#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
914#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
915#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
916#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
917#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
918#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
919#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
920#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
921#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
922#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
923#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
924#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
925#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
926#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
927#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
928#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
929#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
930#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
931#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
932#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
933#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
934#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
935#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
936#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
937#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
938#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
939#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
940#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
941#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
942#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
943#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
944#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
945#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
946#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
947#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
948#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
949#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
950#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
951#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
952#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
953#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
954#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
955#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
956#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
957#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
958#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
959#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
960#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
961#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
962#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
963#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
964#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
965#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
966#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
967#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
968#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
969#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
970#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
971#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
972#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
973#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
974#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
975#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
976#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
977#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
978#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
979#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
980#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
981#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
982#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
983#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
984#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
985#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
986#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
987#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
988#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
989#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
990#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
991#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
992#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
993#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
994#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
995#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
996#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
997#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
998#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
999#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
1000#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
1001#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
1002#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
1003#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
1004#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
1005#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
1006#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
1007#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
1008#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
1009#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
1010#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
1011#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
1012#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
1013#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
1014#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
1015#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
1016#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
1017#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
1018#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
1019#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
1020#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
1021#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
1022#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
1023#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
1024#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
1025#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
1026#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
1027#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
1028#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
1029#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
1030#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
1031#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
1032#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
1033#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
1034#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
1035#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
1036#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
1037#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
1038#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
1039#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
1040#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
1041#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
1042#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
1043#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
1044#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
1045#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
1046#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
1047#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
1048#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
1049#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
1050#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
1051#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
1052#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
1053#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
1054#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
1055#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
1056#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
1057#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1058#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
1059#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
1060#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
1061#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
1062#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
1063#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
1064#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
1065#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
1066#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
1067#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
1068#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
1069#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
1070#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
1071#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
1072#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
1073#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
1074#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
1075#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
1076#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
1077#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
1078#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
1079#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
1080#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
1081#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
1082#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
1083#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
1084#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
1085#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
1086#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
1087#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
1088#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
1089#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
1090#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
1091#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
1092#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
1093#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
1094#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
1095#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
1096#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
1097#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
1098#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
1099#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
1100#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
1101#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
1102#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
1103#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
1104#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
1105#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
1106#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
1107#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
1108#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
1109#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
1110#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
1111#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
1112#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
1113#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
1114#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
1115#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
1116#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
1117#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
1118#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
1119#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1120#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1121#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
1122#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1123#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
1124#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1125#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
1126#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1127#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
1128#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1129#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
1130#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1131#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
1132#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1133#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
1134#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1135#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
1136#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1137#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
1138#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
1139#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
1140#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
1141#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
1142#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
1143#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
1144#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
1145#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
1146#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
1147#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
1148#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
1149#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
1150#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
1151#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
1152#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
1153#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
1154#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
1155#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
1156#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
1157#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
1158#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
1159#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
1160#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
1161#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
1162#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
1163#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
1164#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
1165#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
1166#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
1167#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
1168#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
1169#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
1170#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
1171#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
1172#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
1173#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
1174#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
1175#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
1176#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
1177#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
1178#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
1179#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
1180#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
1181#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
1182#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
1183#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
1184#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
1185#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
1186#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
1187#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
1188#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
1189#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
1190#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
1191#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
1192#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
1193#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
1194#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
1195#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
1196#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
1197#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
1198#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
1199#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
1200#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
1201#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
1202#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
1203#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
1204#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
1205#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
1206#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
1207#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
1208#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
1209#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
1210#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
1211#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
1212#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
1213#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
1214#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
1215#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
1216#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
1217#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
1218#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
1219#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
1220#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
1221#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
1222#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
1223#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
1224#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
1225#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
1226#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
1227#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
1228#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
1229#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
1230#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
1231#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
1232#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
1233#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
1234#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
1235#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
1236#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
1237#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
1238#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
1239#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
1240#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
1241#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
1242#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
1243#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
1244#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
1245#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
1246#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
1247#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
1248#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
1249#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
1250#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
1251#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
1252#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
1253#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
1254#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
1255#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
1256#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
1257#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
1258#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
1259#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
1260#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
1261#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
1262#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
1263#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
1264#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
1265#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
1266#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
1267#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
1268#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
1269#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
1270#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
1271#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
1272#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
1273#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
1274#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
1275#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
1276#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
1277#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
1278#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
1279#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
1280#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
1281#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
1282#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
1283#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
1284#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
1285#define CP_DFY_CNTL__POLICY_MASK 0x1
1286#define CP_DFY_CNTL__POLICY__SHIFT 0x0
1287#define CP_DFY_CNTL__MTYPE_MASK 0xc
1288#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
1289#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
1290#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
1291#define CP_DFY_CNTL__MODE_MASK 0x60000000
1292#define CP_DFY_CNTL__MODE__SHIFT 0x1d
1293#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
1294#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
1295#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
1296#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
1297#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
1298#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
1299#define CP_DFY_STAT__BUSY_MASK 0x80000000
1300#define CP_DFY_STAT__BUSY__SHIFT 0x1f
1301#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
1302#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
1303#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
1304#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
1305#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
1306#define CP_DFY_DATA_0__DATA__SHIFT 0x0
1307#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
1308#define CP_DFY_DATA_1__DATA__SHIFT 0x0
1309#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
1310#define CP_DFY_DATA_2__DATA__SHIFT 0x0
1311#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
1312#define CP_DFY_DATA_3__DATA__SHIFT 0x0
1313#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
1314#define CP_DFY_DATA_4__DATA__SHIFT 0x0
1315#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
1316#define CP_DFY_DATA_5__DATA__SHIFT 0x0
1317#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
1318#define CP_DFY_DATA_6__DATA__SHIFT 0x0
1319#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
1320#define CP_DFY_DATA_7__DATA__SHIFT 0x0
1321#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
1322#define CP_DFY_DATA_8__DATA__SHIFT 0x0
1323#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
1324#define CP_DFY_DATA_9__DATA__SHIFT 0x0
1325#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
1326#define CP_DFY_DATA_10__DATA__SHIFT 0x0
1327#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
1328#define CP_DFY_DATA_11__DATA__SHIFT 0x0
1329#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
1330#define CP_DFY_DATA_12__DATA__SHIFT 0x0
1331#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
1332#define CP_DFY_DATA_13__DATA__SHIFT 0x0
1333#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
1334#define CP_DFY_DATA_14__DATA__SHIFT 0x0
1335#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
1336#define CP_DFY_DATA_15__DATA__SHIFT 0x0
1337#define CP_DFY_CMD__OFFSET_MASK 0x1ff
1338#define CP_DFY_CMD__OFFSET__SHIFT 0x0
1339#define CP_DFY_CMD__SIZE_MASK 0xffff0000
1340#define CP_DFY_CMD__SIZE__SHIFT 0x10
1341#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
1342#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
1343#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
1344#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
1345#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
1346#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
1347#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
1348#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
1349#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
1350#define CP_RB_BASE__RB_BASE__SHIFT 0x0
1351#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
1352#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
1353#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
1354#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
1355#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
1356#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
1357#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
1358#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
1359#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
1360#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
1361#define CP_RB0_CNTL__MTYPE_MASK 0x18000
1362#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
1363#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
1364#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
1365#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
1366#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1367#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1368#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1369#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
1370#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
1371#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
1372#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1373#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1374#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1375#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
1376#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1377#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
1378#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1379#define CP_RB_CNTL__MTYPE_MASK 0x18000
1380#define CP_RB_CNTL__MTYPE__SHIFT 0xf
1381#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
1382#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
1383#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
1384#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1385#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1386#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1387#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
1388#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
1389#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
1390#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1391#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1392#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1393#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
1394#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
1395#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
1396#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
1397#define CP_RB1_CNTL__MTYPE_MASK 0x18000
1398#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
1399#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
1400#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1401#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1402#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1403#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
1404#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
1405#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
1406#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1407#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1408#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1409#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
1410#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
1411#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
1412#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
1413#define CP_RB2_CNTL__MTYPE_MASK 0x18000
1414#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
1415#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
1416#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1417#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1418#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1419#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
1420#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
1421#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
1422#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1423#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1424#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1425#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
1426#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
1427#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1428#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1429#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1430#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1431#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1432#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1433#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1434#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1435#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1436#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1437#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1438#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1439#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1440#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1441#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1442#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1443#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1444#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1445#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1446#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1447#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1448#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1449#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1450#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1451#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
1452#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
1453#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
1454#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
1455#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
1456#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
1457#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
1458#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
1459#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
1460#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
1461#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
1462#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
1463#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1464#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1465#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1466#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1467#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1468#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1469#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
1470#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1471#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1472#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1473#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1474#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1475#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
1476#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1477#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1478#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1479#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1480#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1481#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1482#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1483#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1484#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1485#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1486#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1487#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1488#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1489#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1490#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1491#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1492#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1493#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1494#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1495#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1496#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1497#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1498#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1499#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
1500#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1501#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1502#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1503#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1504#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1505#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
1506#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1507#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1508#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1509#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
1510#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
1511#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1512#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1513#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1514#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1515#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1516#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1517#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
1518#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
1519#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
1520#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
1521#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
1522#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
1523#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1524#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1525#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1526#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1527#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1528#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1529#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
1530#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1531#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1532#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1533#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1534#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1535#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
1536#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1537#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1538#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1539#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
1540#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
1541#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1542#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1543#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1544#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1545#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1546#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1547#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
1548#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
1549#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
1550#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
1551#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
1552#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
1553#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1554#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1555#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1556#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1557#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1558#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1559#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
1560#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1561#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1562#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1563#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1564#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1565#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
1566#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1567#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1568#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1569#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
1570#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
1571#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1572#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1573#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1574#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1575#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1576#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1577#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
1578#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
1579#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
1580#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
1581#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
1582#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
1583#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1584#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1585#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1586#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1587#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1588#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1589#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
1590#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
1591#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
1592#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
1593#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
1594#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1595#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
1596#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
1597#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
1598#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
1599#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
1600#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
1601#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1602#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1603#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
1604#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
1605#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1606#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1607#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
1608#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
1609#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
1610#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
1611#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
1612#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
1613#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1614#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1615#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1616#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1617#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1618#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1619#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
1620#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
1621#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
1622#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
1623#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
1624#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1625#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
1626#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
1627#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
1628#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
1629#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
1630#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
1631#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1632#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1633#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
1634#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
1635#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1636#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1637#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
1638#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
1639#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
1640#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
1641#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
1642#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
1643#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1644#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1645#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1646#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1647#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1648#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1649#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
1650#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
1651#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
1652#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
1653#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
1654#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1655#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
1656#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
1657#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
1658#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
1659#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
1660#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
1661#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1662#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1663#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
1664#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
1665#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1666#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1667#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
1668#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
1669#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
1670#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
1671#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
1672#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
1673#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1674#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1675#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1676#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1677#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1678#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1679#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
1680#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
1681#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
1682#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
1683#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
1684#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1685#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
1686#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
1687#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
1688#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
1689#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
1690#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
1691#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1692#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1693#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
1694#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
1695#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1696#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1697#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
1698#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
1699#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
1700#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
1701#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
1702#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
1703#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
1704#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
1705#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1706#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1707#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1708#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1709#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1710#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1711#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1712#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1713#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1714#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1715#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1716#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1717#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1718#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1719#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1720#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1721#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
1722#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
1723#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1724#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1725#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
1726#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
1727#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1728#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1729#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
1730#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
1731#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1732#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1733#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
1734#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
1735#define CP_RB_VMID__RB0_VMID_MASK 0xf
1736#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
1737#define CP_RB_VMID__RB1_VMID_MASK 0xf00
1738#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
1739#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
1740#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
1741#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
1742#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
1743#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
1744#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
1745#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
1746#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
1747#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
1748#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
1749#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
1750#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
1751#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
1752#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
1753#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
1754#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
1755#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
1756#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
1757#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
1758#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
1759#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1760#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1761#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1762#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1763#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
1764#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
1765#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
1766#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
1767#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
1768#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
1769#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
1770#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
1771#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1772#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1773#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1774#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1775#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1776#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1777#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1778#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1779#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
1780#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
1781#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1782#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1783#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1784#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1785#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1786#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1787#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1788#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1789#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
1790#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
1791#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1792#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1793#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1794#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1795#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1796#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1797#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1798#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1799#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1800#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1801#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1802#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1803#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
1804#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1805#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1806#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1807#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
1808#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1809#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1810#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1811#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1812#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1813#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1814#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1815#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1816#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1817#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
1818#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
1819#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
1820#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
1821#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
1822#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
1823#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
1824#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
1825#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
1826#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
1827#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
1828#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
1829#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
1830#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
1831#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
1832#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
1833#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
1834#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
1835#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
1836#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
1837#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
1838#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
1839#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
1840#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
1841#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
1842#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
1843#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
1844#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
1845#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
1846#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
1847#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
1848#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
1849#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
1850#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
1851#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
1852#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
1853#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
1854#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
1855#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
1856#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
1857#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
1858#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
1859#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
1860#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
1861#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
1862#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
1863#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
1864#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
1865#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
1866#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
1867#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
1868#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
1869#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
1870#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
1871#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
1872#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
1873#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
1874#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
1875#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
1876#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
1877#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
1878#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
1879#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
1880#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
1881#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
1882#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
1883#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
1884#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
1885#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
1886#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
1887#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
1888#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
1889#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
1890#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
1891#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
1892#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
1893#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
1894#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
1895#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
1896#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
1897#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
1898#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
1899#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
1900#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
1901#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
1902#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
1903#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
1904#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
1905#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
1906#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
1907#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
1908#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
1909#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
1910#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
1911#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
1912#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
1913#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
1914#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
1915#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
1916#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
1917#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
1918#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
1919#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1920#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1921#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1922#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1923#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1924#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1925#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1926#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1927#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1928#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1929#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1930#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1931#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1932#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1933#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1934#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1935#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1936#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1937#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1938#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1939#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1940#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1941#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1942#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1943#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1944#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1945#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1946#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1947#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1948#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1949#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1950#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1951#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1952#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1953#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1954#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1955#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1956#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1957#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1958#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1959#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1960#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1961#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1962#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1963#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1964#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1965#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1966#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1967#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1968#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1969#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1970#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1971#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1972#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1973#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1974#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1975#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1976#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1977#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1978#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1979#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1980#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1981#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1982#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1983#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1984#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1985#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1986#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1987#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1988#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1989#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1990#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1991#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1992#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1993#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1994#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1995#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1996#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1997#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1998#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1999#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2000#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2001#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2002#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2003#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2004#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2005#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2006#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2007#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2008#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2009#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2010#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2011#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2012#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2013#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2014#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2015#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2016#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2017#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2018#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2019#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2020#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2021#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2022#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2023#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2024#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2025#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2026#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2027#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2028#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2029#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2030#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2031#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2032#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2033#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2034#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2035#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2036#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2037#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2038#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2039#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2040#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2041#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2042#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2043#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2044#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2045#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2046#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2047#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2048#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2049#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2050#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2051#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2052#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2053#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2054#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2055#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2056#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2057#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2058#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2059#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2060#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2061#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2062#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2063#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2064#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2065#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2066#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2067#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2068#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2069#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2070#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2071#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2072#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2073#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2074#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2075#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2076#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2077#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2078#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2079#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2080#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2081#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2082#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2083#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2084#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2085#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2086#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2087#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2088#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2089#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2090#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2091#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2092#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2093#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2094#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2095#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2096#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2097#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2098#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2099#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2100#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2101#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2102#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2103#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2104#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2105#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2106#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2107#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2108#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2109#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2110#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2111#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2112#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2113#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2114#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2115#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2116#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2117#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2118#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2119#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2120#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2121#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2122#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2123#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2124#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2125#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2126#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2127#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2128#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2129#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2130#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2131#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2132#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2133#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2134#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2135#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2136#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2137#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2138#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2139#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2140#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2141#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2142#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2143#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2144#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2145#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2146#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2147#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2148#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2149#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2150#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2151#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2152#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2153#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2154#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2155#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2156#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2157#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2158#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2159#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2160#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2161#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2162#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2163#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2164#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2165#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2166#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2167#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2168#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2169#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2170#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2171#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2172#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2173#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2174#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2175#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2176#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2177#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2178#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2179#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2180#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2181#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2182#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2183#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2184#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2185#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2186#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2187#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2188#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2189#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2190#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2191#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2192#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2193#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2194#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2195#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2196#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2197#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2198#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2199#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2200#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2201#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2202#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2203#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2204#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2205#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2206#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2207#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2208#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2209#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2210#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2211#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2212#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2213#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2214#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2215#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2216#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2217#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2218#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2219#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2220#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2221#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2222#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2223#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2224#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2225#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2226#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2227#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2228#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2229#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2230#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2231#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2232#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2233#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2234#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2235#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2236#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2237#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2238#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2239#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2240#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2241#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2242#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2243#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2244#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2245#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2246#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2247#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2248#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2249#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2250#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2251#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2252#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2253#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2254#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2255#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2256#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2257#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2258#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2259#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2260#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2261#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2262#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2263#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2264#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2265#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2266#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2267#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2268#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2269#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2270#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2271#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2272#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2273#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2274#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2275#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2276#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2277#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2278#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2279#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2280#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2281#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2282#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2283#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2284#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2285#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2286#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2287#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2288#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2289#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2290#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2291#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2292#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2293#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2294#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2295#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2296#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2297#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2298#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2299#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2300#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2301#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2302#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2303#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2304#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2305#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2306#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2307#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2308#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2309#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2310#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2311#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2312#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2313#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2314#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2315#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2316#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2317#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2318#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2319#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2320#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2321#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2322#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2323#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2324#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2325#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2326#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2327#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2328#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2329#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2330#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2331#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2332#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2333#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2334#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2335#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2336#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2337#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2338#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2339#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2340#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2341#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2342#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2343#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2344#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2345#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2346#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2347#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2348#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2349#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2350#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2351#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2352#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2353#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2354#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2355#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2356#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2357#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2358#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2359#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2360#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2361#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2362#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2363#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2364#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2365#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2366#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2367#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2368#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2369#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2370#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2371#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2372#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2373#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2374#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2375#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2376#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2377#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2378#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2379#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2380#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2381#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2382#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2383#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2384#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2385#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2386#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2387#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2388#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2389#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2390#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2391#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2392#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2393#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2394#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2395#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2396#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2397#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2398#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2399#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2400#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2401#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2402#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2403#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2404#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2405#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2406#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2407#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2408#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2409#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2410#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2411#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2412#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2413#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2414#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2415#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2416#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2417#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2418#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2419#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2420#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2421#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2422#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2423#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2424#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2425#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2426#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2427#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2428#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2429#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2430#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2431#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
2432#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2433#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
2434#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2435#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
2436#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2437#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
2438#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2439#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
2440#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2441#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
2442#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2443#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
2444#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2445#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
2446#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2447#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
2448#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2449#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
2450#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2451#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
2452#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
2453#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
2454#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
2455#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
2456#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
2457#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
2458#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
2459#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
2460#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
2461#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
2462#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
2463#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
2464#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
2465#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
2466#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
2467#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
2468#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
2469#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
2470#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
2471#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
2472#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
2473#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
2474#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
2475#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
2476#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
2477#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
2478#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
2479#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
2480#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
2481#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
2482#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
2483#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
2484#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
2485#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
2486#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
2487#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
2488#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
2489#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
2490#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
2491#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
2492#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
2493#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
2494#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
2495#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
2496#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
2497#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
2498#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
2499#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
2500#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
2501#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
2502#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
2503#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
2504#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
2505#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
2506#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
2507#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
2508#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
2509#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
2510#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
2511#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
2512#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
2513#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
2514#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
2515#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
2516#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
2517#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
2518#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
2519#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
2520#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
2521#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
2522#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
2523#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
2524#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
2525#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
2526#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
2527#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
2528#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
2529#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
2530#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
2531#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
2532#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
2533#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
2534#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
2535#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
2536#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
2537#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
2538#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
2539#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
2540#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
2541#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
2542#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
2543#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
2544#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
2545#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
2546#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
2547#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
2548#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
2549#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
2550#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
2551#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
2552#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
2553#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
2554#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
2555#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
2556#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
2557#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
2558#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
2559#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
2560#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
2561#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
2562#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
2563#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
2564#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
2565#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
2566#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
2567#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
2568#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
2569#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
2570#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
2571#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
2572#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
2573#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
2574#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
2575#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
2576#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
2577#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
2578#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
2579#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
2580#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
2581#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
2582#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
2583#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
2584#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
2585#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
2586#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
2587#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
2588#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
2589#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
2590#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
2591#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
2592#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
2593#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
2594#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
2595#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
2596#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
2597#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
2598#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
2599#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
2600#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
2601#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
2602#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
2603#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
2604#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
2605#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
2606#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
2607#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
2608#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
2609#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
2610#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
2611#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
2612#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
2613#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
2614#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
2615#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
2616#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
2617#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
2618#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
2619#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
2620#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
2621#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
2622#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
2623#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
2624#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
2625#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
2626#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
2627#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
2628#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
2629#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
2630#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
2631#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
2632#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
2633#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
2634#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
2635#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
2636#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
2637#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
2638#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
2639#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
2640#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
2641#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
2642#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
2643#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
2644#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
2645#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
2646#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
2647#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
2648#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
2649#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
2650#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
2651#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
2652#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
2653#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
2654#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
2655#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
2656#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
2657#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
2658#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
2659#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
2660#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
2661#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
2662#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
2663#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
2664#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
2665#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
2666#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
2667#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
2668#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
2669#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
2670#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
2671#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2672#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2673#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
2674#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
2675#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
2676#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
2677#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
2678#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
2679#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
2680#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
2681#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
2682#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
2683#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
2684#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
2685#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
2686#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
2687#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
2688#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
2689#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
2690#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
2691#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
2692#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
2693#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
2694#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
2695#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
2696#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
2697#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
2698#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
2699#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
2700#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
2701#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
2702#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
2703#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
2704#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
2705#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
2706#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
2707#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
2708#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
2709#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
2710#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
2711#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
2712#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
2713#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
2714#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
2715#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
2716#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
2717#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
2718#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
2719#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
2720#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
2721#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
2722#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
2723#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
2724#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
2725#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
2726#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
2727#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
2728#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
2729#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
2730#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
2731#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
2732#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
2733#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
2734#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
2735#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
2736#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
2737#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
2738#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
2739#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
2740#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
2741#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
2742#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
2743#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
2744#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
2745#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
2746#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
2747#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
2748#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
2749#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
2750#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
2751#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
2752#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
2753#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
2754#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
2755#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
2756#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
2757#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
2758#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
2759#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
2760#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
2761#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
2762#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
2763#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
2764#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
2765#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
2766#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
2767#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
2768#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
2769#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
2770#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
2771#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
2772#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
2773#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
2774#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
2775#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2776#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2777#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2778#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2779#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
2780#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2781#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2782#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2783#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2784#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2785#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2786#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2787#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2788#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2789#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2790#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2791#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2792#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2793#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2794#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2795#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2796#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2797#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2798#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2799#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2800#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2801#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2802#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2803#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2804#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2805#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2806#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2807#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2808#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2809#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2810#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2811#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2812#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2813#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2814#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2815#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2816#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2817#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2818#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2819#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2820#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2821#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2822#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2823#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2824#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2825#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2826#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2827#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2828#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2829#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2830#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2831#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2832#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2833#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2834#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2835#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2836#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2837#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2838#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2839#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2840#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2841#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2842#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2843#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
2844#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
2845#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
2846#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
2847#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
2848#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
2849#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
2850#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
2851#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
2852#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
2853#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
2854#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
2855#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
2856#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
2857#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
2858#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
2859#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
2860#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
2861#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
2862#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
2863#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
2864#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
2865#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
2866#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
2867#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
2868#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
2869#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
2870#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
2871#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
2872#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
2873#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
2874#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
2875#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
2876#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
2877#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
2878#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
2879#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
2880#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
2881#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
2882#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
2883#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
2884#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
2885#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
2886#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
2887#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2888#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2889#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
2890#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
2891#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
2892#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
2893#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2894#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2895#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
2896#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
2897#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
2898#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
2899#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
2900#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
2901#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
2902#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
2903#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
2904#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
2905#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
2906#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
2907#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
2908#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
2909#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
2910#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
2911#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
2912#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
2913#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
2914#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
2915#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
2916#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
2917#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
2918#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
2919#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
2920#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
2921#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
2922#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
2923#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
2924#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
2925#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
2926#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
2927#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
2928#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
2929#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
2930#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
2931#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
2932#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
2933#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
2934#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
2935#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
2936#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
2937#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
2938#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
2939#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
2940#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
2941#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
2942#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
2943#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
2944#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
2945#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
2946#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
2947#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
2948#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
2949#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
2950#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
2951#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
2952#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
2953#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
2954#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
2955#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
2956#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
2957#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
2958#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
2959#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
2960#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
2961#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
2962#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
2963#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
2964#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
2965#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
2966#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
2967#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
2968#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
2969#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
2970#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
2971#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
2972#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
2973#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
2974#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
2975#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
2976#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
2977#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
2978#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
2979#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
2980#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
2981#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
2982#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
2983#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
2984#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
2985#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
2986#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
2987#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
2988#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
2989#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
2990#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
2991#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
2992#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
2993#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
2994#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
2995#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
2996#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
2997#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
2998#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
2999#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
3000#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
3001#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
3002#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
3003#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
3004#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
3005#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
3006#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
3007#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
3008#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
3009#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
3010#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
3011#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
3012#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
3013#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
3014#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
3015#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
3016#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
3017#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
3018#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
3019#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
3020#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
3021#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
3022#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
3023#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
3024#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
3025#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
3026#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
3027#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
3028#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
3029#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
3030#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
3031#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
3032#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
3033#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
3034#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
3035#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
3036#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
3037#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
3038#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
3039#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
3040#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
3041#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
3042#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
3043#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
3044#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
3045#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3046#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3047#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3048#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3049#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3050#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3051#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3052#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3053#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3054#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3055#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3056#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3057#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
3058#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
3059#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
3060#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
3061#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
3062#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
3063#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
3064#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
3065#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
3066#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
3067#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
3068#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
3069#define CP_APPEND_DATA__DATA_MASK 0xffffffff
3070#define CP_APPEND_DATA__DATA__SHIFT 0x0
3071#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
3072#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
3073#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
3074#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
3075#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3076#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3077#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3078#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3079#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3080#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3081#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3082#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3083#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3084#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3085#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3086#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3087#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3088#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3089#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3090#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3091#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3092#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3093#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3094#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3095#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3096#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3097#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3098#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3099#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
3100#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
3101#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
3102#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
3103#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
3104#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
3105#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
3106#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
3107#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
3108#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
3109#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
3110#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
3111#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
3112#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
3113#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
3114#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
3115#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
3116#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
3117#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
3118#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
3119#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
3120#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
3121#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
3122#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
3123#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
3124#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
3125#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3126#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3127#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3128#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3129#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3130#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3131#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3132#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3133#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3134#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3135#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3136#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3137#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3138#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3139#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3140#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3141#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3142#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3143#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3144#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3145#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3146#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3147#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3148#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3149#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3150#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3151#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3152#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3153#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
3154#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
3155#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
3156#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
3157#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
3158#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
3159#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
3160#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
3161#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
3162#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
3163#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
3164#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
3165#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
3166#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
3167#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
3168#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
3169#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
3170#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
3171#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
3172#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
3173#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
3174#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
3175#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
3176#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
3177#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
3178#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
3179#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
3180#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
3181#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
3182#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
3183#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
3184#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
3185#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
3186#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
3187#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
3188#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
3189#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
3190#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
3191#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
3192#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
3193#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
3194#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
3195#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
3196#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
3197#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
3198#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
3199#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
3200#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
3201#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
3202#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
3203#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
3204#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
3205#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
3206#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
3207#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
3208#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
3209#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
3210#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
3211#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
3212#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
3213#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
3214#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
3215#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
3216#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
3217#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
3218#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
3219#define CP_COHER_STATUS__MEID_MASK 0x3000000
3220#define CP_COHER_STATUS__MEID__SHIFT 0x18
3221#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
3222#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
3223#define CP_COHER_STATUS__STATUS_MASK 0x80000000
3224#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
3225#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
3226#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
3227#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
3228#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
3229#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
3230#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
3231#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
3232#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
3233#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
3234#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
3235#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
3236#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
3237#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
3238#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
3239#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
3240#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
3241#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3242#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3243#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3244#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3245#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
3246#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
3247#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3248#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3249#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
3250#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
3251#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
3252#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
3253#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3254#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3255#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
3256#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
3257#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
3258#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
3259#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
3260#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
3261#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3262#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3263#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
3264#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
3265#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
3266#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
3267#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
3268#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
3269#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
3270#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
3271#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
3272#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
3273#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
3274#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
3275#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
3276#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
3277#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
3278#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
3279#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
3280#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
3281#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
3282#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
3283#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3284#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3285#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3286#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3287#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
3288#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
3289#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3290#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3291#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
3292#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
3293#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
3294#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
3295#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3296#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3297#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
3298#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
3299#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
3300#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
3301#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
3302#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
3303#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3304#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3305#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
3306#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
3307#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
3308#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
3309#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
3310#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
3311#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
3312#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
3313#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
3314#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
3315#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
3316#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
3317#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
3318#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
3319#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
3320#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
3321#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
3322#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
3323#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
3324#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
3325#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
3326#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
3327#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
3328#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
3329#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
3330#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
3331#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
3332#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
3333#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
3334#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
3335#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
3336#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
3337#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
3338#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
3339#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
3340#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
3341#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
3342#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
3343#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
3344#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
3345#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
3346#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
3347#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
3348#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
3349#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
3350#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
3351#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
3352#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
3353#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3354#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3355#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3356#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3357#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3358#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3359#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
3360#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
3361#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
3362#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
3363#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
3364#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
3365#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
3366#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
3367#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3368#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3369#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3370#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3371#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
3372#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
3373#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3374#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3375#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
3376#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
3377#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
3378#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
3379#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
3380#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
3381#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3382#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3383#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3384#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3385#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3386#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3387#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3388#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3389#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3390#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
3391#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3392#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3393#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3394#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
3395#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3396#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3397#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3398#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
3399#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3400#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3401#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
3402#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
3403#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
3404#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
3405#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
3406#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
3407#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
3408#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
3409#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
3410#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
3411#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
3412#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
3413#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
3414#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
3415#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
3416#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
3417#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
3418#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
3419#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
3420#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
3421#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
3422#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
3423#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
3424#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
3425#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
3426#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
3427#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
3428#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
3429#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
3430#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
3431#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
3432#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
3433#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
3434#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
3435#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
3436#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
3437#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
3438#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
3439#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
3440#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
3441#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
3442#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
3443#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
3444#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
3445#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
3446#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
3447#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
3448#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
3449#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
3450#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
3451#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
3452#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
3453#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
3454#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
3455#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
3456#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
3457#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
3458#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
3459#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
3460#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
3461#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
3462#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
3463#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
3464#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
3465#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
3466#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
3467#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
3468#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
3469#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
3470#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
3471#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
3472#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
3473#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
3474#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
3475#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
3476#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
3477#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
3478#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
3479#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
3480#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
3481#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
3482#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
3483#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
3484#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
3485#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
3486#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
3487#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
3488#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
3489#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
3490#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
3491#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
3492#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
3493#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
3494#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
3495#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
3496#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
3497#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
3498#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
3499#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
3500#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
3501#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
3502#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
3503#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
3504#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
3505#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
3506#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
3507#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
3508#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
3509#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
3510#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
3511#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
3512#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
3513#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
3514#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
3515#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
3516#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
3517#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
3518#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
3519#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
3520#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
3521#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
3522#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
3523#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
3524#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
3525#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
3526#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
3527#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
3528#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
3529#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
3530#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
3531#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
3532#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
3533#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
3534#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
3535#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
3536#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
3537#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
3538#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
3539#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
3540#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
3541#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
3542#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
3543#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
3544#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
3545#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
3546#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
3547#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
3548#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
3549#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
3550#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
3551#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
3552#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
3553#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
3554#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
3555#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
3556#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
3557#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
3558#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
3559#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
3560#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
3561#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
3562#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
3563#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
3564#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
3565#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
3566#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
3567#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
3568#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
3569#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
3570#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
3571#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
3572#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
3573#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
3574#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
3575#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
3576#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
3577#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
3578#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
3579#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
3580#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
3581#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
3582#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
3583#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
3584#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
3585#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
3586#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
3587#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
3588#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
3589#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
3590#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
3591#define CP_STAT__DC_BUSY_MASK 0x2000
3592#define CP_STAT__DC_BUSY__SHIFT 0xd
3593#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
3594#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
3595#define CP_STAT__PFP_BUSY_MASK 0x8000
3596#define CP_STAT__PFP_BUSY__SHIFT 0xf
3597#define CP_STAT__MEQ_BUSY_MASK 0x10000
3598#define CP_STAT__MEQ_BUSY__SHIFT 0x10
3599#define CP_STAT__ME_BUSY_MASK 0x20000
3600#define CP_STAT__ME_BUSY__SHIFT 0x11
3601#define CP_STAT__QUERY_BUSY_MASK 0x40000
3602#define CP_STAT__QUERY_BUSY__SHIFT 0x12
3603#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
3604#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
3605#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
3606#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
3607#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
3608#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
3609#define CP_STAT__DMA_BUSY_MASK 0x400000
3610#define CP_STAT__DMA_BUSY__SHIFT 0x16
3611#define CP_STAT__RCIU_BUSY_MASK 0x800000
3612#define CP_STAT__RCIU_BUSY__SHIFT 0x17
3613#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
3614#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
3615#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
3616#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
3617#define CP_STAT__CE_BUSY_MASK 0x4000000
3618#define CP_STAT__CE_BUSY__SHIFT 0x1a
3619#define CP_STAT__TCIU_BUSY_MASK 0x8000000
3620#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
3621#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
3622#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
3623#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
3624#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
3625#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
3626#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
3627#define CP_STAT__CP_BUSY_MASK 0x80000000
3628#define CP_STAT__CP_BUSY__SHIFT 0x1f
3629#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
3630#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
3631#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
3632#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
3633#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
3634#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
3635#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
3636#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
3637#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
3638#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
3639#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
3640#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
3641#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
3642#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
3643#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
3644#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
3645#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
3646#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
3647#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
3648#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
3649#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
3650#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
3651#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
3652#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
3653#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
3654#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
3655#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
3656#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
3657#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
3658#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
3659#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
3660#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
3661#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
3662#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
3663#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
3664#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
3665#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
3666#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
3667#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
3668#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
3669#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
3670#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
3671#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
3672#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
3673#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
3674#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
3675#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
3676#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
3677#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
3678#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
3679#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
3680#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
3681#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
3682#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
3683#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
3684#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
3685#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
3686#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
3687#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
3688#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
3689#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
3690#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
3691#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
3692#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
3693#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
3694#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
3695#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
3696#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
3697#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
3698#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
3699#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
3700#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
3701#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
3702#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
3703#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3704#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3705#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3706#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3707#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3708#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3709#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3710#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3711#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3712#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3713#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3714#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3715#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3716#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3717#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3718#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3719#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3720#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3721#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3722#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3723#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3724#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3725#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3726#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3727#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
3728#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
3729#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
3730#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
3731#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
3732#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
3733#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
3734#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
3735#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
3736#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
3737#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
3738#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
3739#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
3740#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
3741#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
3742#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
3743#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
3744#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
3745#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
3746#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
3747#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
3748#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
3749#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
3750#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
3751#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
3752#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
3753#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
3754#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
3755#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
3756#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
3757#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
3758#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
3759#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
3760#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
3761#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
3762#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
3763#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
3764#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
3765#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
3766#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
3767#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
3768#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
3769#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
3770#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
3771#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
3772#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
3773#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
3774#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
3775#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
3776#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
3777#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
3778#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
3779#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
3780#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
3781#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
3782#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
3783#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
3784#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
3785#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
3786#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
3787#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
3788#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
3789#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
3790#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
3791#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
3792#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
3793#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
3794#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
3795#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
3796#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
3797#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
3798#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
3799#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
3800#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
3801#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
3802#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
3803#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
3804#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
3805#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
3806#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
3807#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
3808#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
3809#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
3810#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
3811#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
3812#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
3813#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
3814#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
3815#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
3816#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
3817#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
3818#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
3819#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
3820#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
3821#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
3822#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
3823#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
3824#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
3825#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
3826#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
3827#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
3828#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
3829#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
3830#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
3831#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
3832#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
3833#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
3834#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
3835#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
3836#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
3837#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
3838#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
3839#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
3840#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
3841#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
3842#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
3843#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
3844#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
3845#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
3846#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
3847#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
3848#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
3849#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
3850#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
3851#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
3852#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
3853#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
3854#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
3855#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
3856#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
3857#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
3858#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
3859#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
3860#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
3861#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
3862#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
3863#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
3864#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
3865#define CP_RINGID__RINGID_MASK 0x3
3866#define CP_RINGID__RINGID__SHIFT 0x0
3867#define CP_PIPEID__PIPE_ID_MASK 0x3
3868#define CP_PIPEID__PIPE_ID__SHIFT 0x0
3869#define CP_VMID__VMID_MASK 0xf
3870#define CP_VMID__VMID__SHIFT 0x0
3871#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
3872#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
3873#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
3874#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
3875#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
3876#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
3877#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
3878#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
3879#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
3880#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
3881#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
3882#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
3883#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
3884#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
3885#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
3886#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3887#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
3888#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
3889#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
3890#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
3891#define CP_HQD_VMID__VMID_MASK 0xf
3892#define CP_HQD_VMID__VMID__SHIFT 0x0
3893#define CP_HQD_VMID__IB_VMID_MASK 0xf00
3894#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
3895#define CP_HQD_VMID__VQID_MASK 0x3ff0000
3896#define CP_HQD_VMID__VQID__SHIFT 0x10
3897#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
3898#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
3899#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
3900#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
3901#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
3902#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
3903#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
3904#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
3905#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
3906#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
3907#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
3908#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
3909#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
3910#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
3911#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
3912#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
3913#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
3914#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
3915#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
3916#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
3917#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
3918#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
3919#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
3920#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
3921#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
3922#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
3923#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
3924#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
3925#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
3926#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3927#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
3928#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
3929#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
3930#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
3931#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
3932#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
3933#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
3934#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
3935#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
3936#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
3937#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
3938#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
3939#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
3940#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
3941#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
3942#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
3943#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
3944#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
3945#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
3946#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
3947#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
3948#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
3949#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
3950#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
3951#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
3952#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
3953#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
3954#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
3955#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
3956#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
3957#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
3958#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
3959#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
3960#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
3961#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
3962#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
3963#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
3964#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
3965#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
3966#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
3967#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
3968#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
3969#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
3970#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
3971#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
3972#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
3973#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
3974#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
3975#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
3976#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
3977#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
3978#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
3979#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
3980#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
3981#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
3982#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
3983#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
3984#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3985#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
3986#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
3987#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
3988#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
3989#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
3990#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
3991#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
3992#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
3993#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
3994#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
3995#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
3996#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
3997#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
3998#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
3999#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
4000#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
4001#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
4002#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
4003#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
4004#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
4005#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
4006#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
4007#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
4008#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
4009#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
4010#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
4011#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
4012#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
4013#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
4014#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
4015#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
4016#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
4017#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
4018#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
4019#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
4020#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
4021#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
4022#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
4023#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
4024#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
4025#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
4026#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
4027#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
4028#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
4029#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
4030#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
4031#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
4032#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
4033#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
4034#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
4035#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4036#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4037#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4038#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4039#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
4040#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
4041#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
4042#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
4043#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
4044#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
4045#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
4046#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
4047#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
4048#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
4049#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
4050#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
4051#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
4052#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
4053#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
4054#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
4055#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
4056#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
4057#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
4058#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
4059#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
4060#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
4061#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
4062#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
4063#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
4064#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
4065#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
4066#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
4067#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
4068#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
4069#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
4070#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
4071#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
4072#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
4073#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
4074#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
4075#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
4076#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
4077#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
4078#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
4079#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
4080#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
4081#define CP_MQD_CONTROL__VMID_MASK 0xf
4082#define CP_MQD_CONTROL__VMID__SHIFT 0x0
4083#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
4084#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
4085#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
4086#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
4087#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
4088#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
4089#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
4090#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
4091#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
4092#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
4093#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
4094#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
4095#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
4096#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
4097#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
4098#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
4099#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
4100#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
4101#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
4102#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
4103#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
4104#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
4105#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
4106#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
4107#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
4108#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
4109#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
4110#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
4111#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
4112#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
4113#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
4114#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
4115#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
4116#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
4117#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
4118#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
4119#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
4120#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
4121#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
4122#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
4123#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
4124#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
4125#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
4126#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
4127#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
4128#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
4129#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
4130#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
4131#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
4132#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
4133#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
4134#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
4135#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
4136#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
4137#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
4138#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
4139#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
4140#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
4141#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
4142#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
4143#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
4144#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
4145#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
4146#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
4147#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
4148#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
4149#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
4150#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
4151#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
4152#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
4153#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
4154#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
4155#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
4156#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
4157#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
4158#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
4159#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
4160#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
4161#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
4162#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
4163#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
4164#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
4165#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
4166#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
4167#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
4168#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
4169#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
4170#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
4171#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
4172#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
4173#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
4174#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
4175#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
4176#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
4177#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
4178#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
4179#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
4180#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
4181#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
4182#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
4183#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
4184#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
4185#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
4186#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
4187#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
4188#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
4189#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
4190#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
4191#define DB_Z_INFO__FORMAT_MASK 0x3
4192#define DB_Z_INFO__FORMAT__SHIFT 0x0
4193#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
4194#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
4195#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
4196#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
4197#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
4198#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
4199#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
4200#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
4201#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4202#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4203#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
4204#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
4205#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
4206#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
4207#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4208#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4209#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
4210#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
4211#define DB_STENCIL_INFO__FORMAT_MASK 0x1
4212#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
4213#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
4214#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
4215#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
4216#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
4217#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4218#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4219#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
4220#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
4221#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4222#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4223#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
4224#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
4225#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
4226#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
4227#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
4228#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
4229#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
4230#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
4231#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
4232#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
4233#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
4234#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
4235#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
4236#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
4237#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
4238#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
4239#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
4240#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
4241#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
4242#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
4243#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
4244#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
4245#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
4246#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
4247#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
4248#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
4249#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
4250#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
4251#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
4252#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
4253#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
4254#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
4255#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
4256#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
4257#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
4258#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
4259#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
4260#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
4261#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
4262#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
4263#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
4264#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
4265#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
4266#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
4267#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
4268#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
4269#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
4270#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
4271#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
4272#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
4273#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
4274#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
4275#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
4276#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
4277#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
4278#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
4279#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
4280#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
4281#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
4282#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
4283#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
4284#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
4285#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
4286#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
4287#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
4288#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
4289#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
4290#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
4291#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
4292#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
4293#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
4294#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
4295#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
4296#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
4297#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
4298#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
4299#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
4300#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
4301#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
4302#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
4303#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
4304#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
4305#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
4306#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
4307#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
4308#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
4309#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
4310#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
4311#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
4312#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
4313#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
4314#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
4315#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
4316#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
4317#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
4318#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
4319#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
4320#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
4321#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
4322#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
4323#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
4324#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
4325#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
4326#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
4327#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
4328#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
4329#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
4330#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
4331#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
4332#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
4333#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
4334#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
4335#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
4336#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
4337#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
4338#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
4339#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
4340#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
4341#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
4342#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
4343#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
4344#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
4345#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
4346#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
4347#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
4348#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
4349#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
4350#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
4351#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
4352#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
4353#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
4354#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
4355#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
4356#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
4357#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
4358#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
4359#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
4360#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
4361#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
4362#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
4363#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
4364#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
4365#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
4366#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
4367#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
4368#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
4369#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
4370#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
4371#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
4372#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
4373#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
4374#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
4375#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
4376#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
4377#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
4378#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
4379#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
4380#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
4381#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
4382#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
4383#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
4384#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
4385#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
4386#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
4387#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
4388#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
4389#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
4390#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
4391#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
4392#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
4393#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
4394#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
4395#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
4396#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
4397#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
4398#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
4399#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
4400#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
4401#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
4402#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
4403#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
4404#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
4405#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
4406#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
4407#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
4408#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
4409#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
4410#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
4411#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
4412#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
4413#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
4414#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
4415#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
4416#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
4417#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
4418#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
4419#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
4420#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
4421#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
4422#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
4423#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
4424#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
4425#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
4426#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
4427#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
4428#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
4429#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
4430#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
4431#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
4432#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
4433#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
4434#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
4435#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
4436#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
4437#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
4438#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
4439#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
4440#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
4441#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
4442#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
4443#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
4444#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
4445#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
4446#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
4447#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
4448#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
4449#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
4450#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
4451#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
4452#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
4453#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
4454#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
4455#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
4456#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
4457#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
4458#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
4459#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
4460#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
4461#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
4462#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
4463#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
4464#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
4465#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
4466#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
4467#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
4468#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
4469#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
4470#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
4471#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
4472#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
4473#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
4474#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
4475#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
4476#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
4477#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
4478#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
4479#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
4480#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
4481#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
4482#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
4483#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
4484#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
4485#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
4486#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
4487#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
4488#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
4489#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
4490#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
4491#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
4492#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
4493#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
4494#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
4495#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
4496#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
4497#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
4498#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0