| 1 | /* |
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| 2 | * GMC_7_0 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef GMC_7_0_D_H |
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| 25 | #define GMC_7_0_D_H |
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| 26 | |
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| 27 | #define mmMC_CONFIG 0x800 |
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| 28 | #define mmMC_ARB_AGE_CNTL 0x9bf |
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| 29 | #define mmMC_ARB_RET_CREDITS2 0x9c0 |
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| 30 | #define mmMC_ARB_FED_CNTL 0x9c1 |
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| 31 | #define mmMC_ARB_GECC2_STATUS 0x9c2 |
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| 32 | #define mmMC_ARB_GECC2_MISC 0x9c3 |
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| 33 | #define mmMC_ARB_GECC2_DEBUG 0x9c4 |
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| 34 | #define mmMC_ARB_GECC2_DEBUG2 0x9c5 |
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| 35 | #define mmMC_ARB_GECC2 0x9c9 |
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| 36 | #define mmMC_ARB_GECC2_CLI 0x9ca |
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| 37 | #define mmMC_ARB_ADDR_SWIZ0 0x9cb |
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| 38 | #define mmMC_ARB_ADDR_SWIZ1 0x9cc |
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| 39 | #define mmMC_ARB_MISC3 0x9cd |
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| 40 | #define mmMC_ARB_WCDR_2 0x9ce |
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| 41 | #define mmMC_ARB_RTT_DATA 0x9cf |
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| 42 | #define mmMC_ARB_RTT_CNTL0 0x9d0 |
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| 43 | #define mmMC_ARB_RTT_CNTL1 0x9d1 |
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| 44 | #define mmMC_ARB_RTT_CNTL2 0x9d2 |
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| 45 | #define mmMC_ARB_RTT_DEBUG 0x9d3 |
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| 46 | #define mmMC_ARB_CAC_CNTL 0x9d4 |
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| 47 | #define mmMC_ARB_MISC2 0x9d5 |
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| 48 | #define mmMC_ARB_MISC 0x9d6 |
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| 49 | #define mmMC_ARB_BANKMAP 0x9d7 |
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| 50 | #define mmMC_ARB_RAMCFG 0x9d8 |
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| 51 | #define mmMC_ARB_POP 0x9d9 |
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| 52 | #define mmMC_ARB_MINCLKS 0x9da |
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| 53 | #define mmMC_ARB_SQM_CNTL 0x9db |
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| 54 | #define mmMC_ARB_ADDR_HASH 0x9dc |
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| 55 | #define mmMC_ARB_DRAM_TIMING 0x9dd |
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| 56 | #define mmMC_ARB_DRAM_TIMING2 0x9de |
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| 57 | #define mmMC_ARB_WTM_CNTL_RD 0x9df |
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| 58 | #define mmMC_ARB_WTM_CNTL_WR 0x9e0 |
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| 59 | #define mmMC_ARB_WTM_GRPWT_RD 0x9e1 |
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| 60 | #define mmMC_ARB_WTM_GRPWT_WR 0x9e2 |
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| 61 | #define mmMC_ARB_TM_CNTL_RD 0x9e3 |
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| 62 | #define mmMC_ARB_TM_CNTL_WR 0x9e4 |
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| 63 | #define mmMC_ARB_LAZY0_RD 0x9e5 |
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| 64 | #define mmMC_ARB_LAZY0_WR 0x9e6 |
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| 65 | #define mmMC_ARB_LAZY1_RD 0x9e7 |
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| 66 | #define mmMC_ARB_LAZY1_WR 0x9e8 |
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| 67 | #define mmMC_ARB_AGE_RD 0x9e9 |
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| 68 | #define mmMC_ARB_AGE_WR 0x9ea |
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| 69 | #define mmMC_ARB_RFSH_CNTL 0x9eb |
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| 70 | #define mmMC_ARB_RFSH_RATE 0x9ec |
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| 71 | #define mmMC_ARB_PM_CNTL 0x9ed |
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| 72 | #define mmMC_ARB_GDEC_RD_CNTL 0x9ee |
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| 73 | #define mmMC_ARB_GDEC_WR_CNTL 0x9ef |
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| 74 | #define mmMC_ARB_LM_RD 0x9f0 |
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| 75 | #define mmMC_ARB_LM_WR 0x9f1 |
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| 76 | #define mmMC_ARB_REMREQ 0x9f2 |
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| 77 | #define mmMC_ARB_REPLAY 0x9f3 |
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| 78 | #define mmMC_ARB_RET_CREDITS_RD 0x9f4 |
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| 79 | #define mmMC_ARB_RET_CREDITS_WR 0x9f5 |
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| 80 | #define mmMC_ARB_MAX_LAT_CID 0x9f6 |
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| 81 | #define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 |
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| 82 | #define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 |
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| 83 | #define mmMC_ARB_SSM 0x9f9 |
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| 84 | #define mmMC_ARB_CG 0x9fa |
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| 85 | #define mmMC_ARB_WCDR 0x9fb |
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| 86 | #define mmMC_ARB_DRAM_TIMING_1 0x9fc |
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| 87 | #define mmMC_ARB_BUSY_STATUS 0x9fd |
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| 88 | #define mmMC_ARB_DRAM_TIMING2_1 0x9ff |
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| 89 | #define mmMC_ARB_BURST_TIME 0xa02 |
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| 90 | #define mmMC_CITF_XTRA_ENABLE 0x96d |
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| 91 | #define mmCC_MC_MAX_CHANNEL 0x96e |
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| 92 | #define mmMC_CG_CONFIG 0x96f |
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| 93 | #define mmMC_CITF_CNTL 0x970 |
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| 94 | #define mmMC_CITF_CREDITS_VM 0x971 |
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| 95 | #define mmMC_CITF_CREDITS_ARB_RD 0x972 |
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| 96 | #define mmMC_CITF_CREDITS_ARB_WR 0x973 |
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| 97 | #define mmMC_CITF_DAGB_CNTL 0x974 |
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| 98 | #define mmMC_CITF_INT_CREDITS 0x975 |
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| 99 | #define mmMC_CITF_RET_MODE 0x976 |
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| 100 | #define mmMC_CITF_DAGB_DLY 0x977 |
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| 101 | #define mmMC_RD_GRP_EXT 0x978 |
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| 102 | #define mmMC_WR_GRP_EXT 0x979 |
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| 103 | #define mmMC_CITF_REMREQ 0x97a |
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| 104 | #define mmMC_WR_TC0 0x97b |
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| 105 | #define mmMC_WR_TC1 0x97c |
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| 106 | #define mmMC_CITF_INT_CREDITS_WR 0x97d |
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| 107 | #define mmMC_CITF_WTM_RD_CNTL 0x97f |
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| 108 | #define mmMC_CITF_WTM_WR_CNTL 0x980 |
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| 109 | #define mmMC_RD_CB 0x981 |
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| 110 | #define mmMC_RD_DB 0x982 |
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| 111 | #define mmMC_RD_TC0 0x983 |
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| 112 | #define mmMC_RD_TC1 0x984 |
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| 113 | #define mmMC_RD_HUB 0x985 |
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| 114 | #define mmMC_WR_CB 0x986 |
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| 115 | #define mmMC_WR_DB 0x987 |
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| 116 | #define mmMC_WR_HUB 0x988 |
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| 117 | #define mmMC_CITF_CREDITS_XBAR 0x989 |
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| 118 | #define mmMC_RD_GRP_LCL 0x98a |
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| 119 | #define mmMC_WR_GRP_LCL 0x98b |
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| 120 | #define mmMC_CITF_PERF_MON_CNTL2 0x98e |
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| 121 | #define mmMC_CITF_PERF_MON_RSLT2 0x991 |
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| 122 | #define mmMC_CITF_MISC_RD_CG 0x992 |
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| 123 | #define mmMC_CITF_MISC_WR_CG 0x993 |
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| 124 | #define mmMC_CITF_MISC_VM_CG 0x994 |
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| 125 | #define mmMC_HUB_MISC_POWER 0x82d |
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| 126 | #define mmMC_HUB_MISC_HUB_CG 0x82e |
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| 127 | #define mmMC_HUB_MISC_VM_CG 0x82f |
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| 128 | #define mmMC_HUB_MISC_SIP_CG 0x830 |
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| 129 | #define mmMC_HUB_MISC_DBG 0x831 |
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| 130 | #define mmMC_HUB_MISC_STATUS 0x832 |
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| 131 | #define mmMC_HUB_MISC_OVERRIDE 0x833 |
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| 132 | #define mmMC_HUB_MISC_FRAMING 0x834 |
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| 133 | #define mmMC_HUB_WDP_CNTL 0x835 |
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| 134 | #define mmMC_HUB_WDP_ERR 0x836 |
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| 135 | #define mmMC_HUB_WDP_BP 0x837 |
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| 136 | #define mmMC_HUB_WDP_STATUS 0x838 |
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| 137 | #define mmMC_HUB_RDREQ_STATUS 0x839 |
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| 138 | #define mmMC_HUB_WRRET_STATUS 0x83a |
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| 139 | #define mmMC_HUB_RDREQ_CNTL 0x83b |
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| 140 | #define mmMC_HUB_WRRET_CNTL 0x83c |
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| 141 | #define mmMC_HUB_RDREQ_WTM_CNTL 0x83d |
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| 142 | #define mmMC_HUB_WDP_WTM_CNTL 0x83e |
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| 143 | #define mmMC_HUB_WDP_CREDITS 0x83f |
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| 144 | #define mmMC_HUB_WDP_MGPU2 0x840 |
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| 145 | #define mmMC_HUB_WDP_GBL0 0x841 |
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| 146 | #define mmMC_HUB_WDP_GBL1 0x842 |
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| 147 | #define mmMC_HUB_WDP_MGPU 0x843 |
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| 148 | #define mmMC_HUB_RDREQ_CREDITS 0x844 |
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| 149 | #define mmMC_HUB_RDREQ_CREDITS2 0x845 |
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| 150 | #define mmMC_HUB_SHARED_DAGB_DLY 0x846 |
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| 151 | #define mmMC_HUB_MISC_IDLE_STATUS 0x847 |
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| 152 | #define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 |
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| 153 | #define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 |
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| 154 | #define mmMC_HUB_WDP_SH2 0x84d |
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| 155 | #define mmMC_HUB_WDP_SH3 0x84e |
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| 156 | #define mmMC_HUB_RDREQ_IA0 0x84f |
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| 157 | #define mmMC_HUB_RDREQ_IA1 0x850 |
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| 158 | #define mmMC_HUB_RDREQ_MCDW 0x851 |
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| 159 | #define mmMC_HUB_RDREQ_MCDX 0x852 |
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| 160 | #define mmMC_HUB_RDREQ_MCDY 0x853 |
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| 161 | #define mmMC_HUB_RDREQ_MCDZ 0x854 |
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| 162 | #define mmMC_HUB_RDREQ_SIP 0x855 |
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| 163 | #define mmMC_HUB_RDREQ_GBL0 0x856 |
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| 164 | #define mmMC_HUB_RDREQ_GBL1 0x857 |
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| 165 | #define mmMC_HUB_RDREQ_SMU 0x858 |
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| 166 | #define mmMC_HUB_RDREQ_CPG 0x859 |
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| 167 | #define mmMC_HUB_RDREQ_SDMA0 0x85a |
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| 168 | #define mmMC_HUB_RDREQ_HDP 0x85b |
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| 169 | #define mmMC_HUB_RDREQ_SDMA1 0x85c |
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| 170 | #define mmMC_HUB_RDREQ_RLC 0x85d |
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| 171 | #define mmMC_HUB_RDREQ_SEM 0x85e |
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| 172 | #define mmMC_HUB_RDREQ_VCE 0x85f |
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| 173 | #define mmMC_HUB_RDREQ_UMC 0x860 |
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| 174 | #define mmMC_HUB_RDREQ_UVD 0x861 |
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| 175 | #define mmMC_HUB_RDREQ_IA 0x862 |
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| 176 | #define mmMC_HUB_RDREQ_DMIF 0x863 |
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| 177 | #define mmMC_HUB_RDREQ_MCIF 0x864 |
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| 178 | #define mmMC_HUB_RDREQ_VMC 0x865 |
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| 179 | #define mmMC_HUB_RDREQ_VCEU 0x866 |
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| 180 | #define mmMC_HUB_WDP_MCDW 0x867 |
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| 181 | #define mmMC_HUB_WDP_MCDX 0x868 |
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| 182 | #define mmMC_HUB_WDP_MCDY 0x869 |
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| 183 | #define mmMC_HUB_WDP_MCDZ 0x86a |
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| 184 | #define mmMC_HUB_WDP_SIP 0x86b |
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| 185 | #define mmMC_HUB_WDP_CPG 0x86c |
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| 186 | #define mmMC_HUB_WDP_SDMA1 0x86d |
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| 187 | #define mmMC_HUB_WDP_SH0 0x86e |
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| 188 | #define mmMC_HUB_WDP_MCIF 0x86f |
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| 189 | #define mmMC_HUB_WDP_VCE 0x870 |
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| 190 | #define mmMC_HUB_WDP_XDP 0x871 |
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| 191 | #define mmMC_HUB_WDP_IH 0x872 |
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| 192 | #define mmMC_HUB_WDP_RLC 0x873 |
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| 193 | #define mmMC_HUB_WDP_SEM 0x874 |
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| 194 | #define mmMC_HUB_WDP_SMU 0x875 |
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| 195 | #define mmMC_HUB_WDP_SH1 0x876 |
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| 196 | #define mmMC_HUB_WDP_UMC 0x877 |
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| 197 | #define mmMC_HUB_WDP_UVD 0x878 |
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| 198 | #define mmMC_HUB_WDP_HDP 0x879 |
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| 199 | #define mmMC_HUB_WDP_SDMA0 0x87a |
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| 200 | #define mmMC_HUB_WRRET_MCDW 0x87b |
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| 201 | #define mmMC_HUB_WRRET_MCDX 0x87c |
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| 202 | #define mmMC_HUB_WRRET_MCDY 0x87d |
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| 203 | #define mmMC_HUB_WRRET_MCDZ 0x87e |
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| 204 | #define mmMC_HUB_WDP_VCEU 0x87f |
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| 205 | #define mmMC_HUB_WDP_XDMAM 0x880 |
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| 206 | #define mmMC_HUB_WDP_XDMA 0x881 |
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| 207 | #define mmMC_HUB_RDREQ_XDMAM 0x882 |
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| 208 | #define mmMC_HUB_RDREQ_ACPG 0x883 |
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| 209 | #define mmMC_HUB_RDREQ_ACPO 0x884 |
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| 210 | #define mmMC_HUB_RDREQ_SAM 0x885 |
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| 211 | #define mmMC_HUB_WDP_ACPG 0x886 |
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| 212 | #define mmMC_HUB_WDP_ACPO 0x887 |
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| 213 | #define mmMC_HUB_WDP_SAM 0x888 |
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| 214 | #define mmMC_HUB_RDREQ_CPC 0x889 |
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| 215 | #define mmMC_HUB_RDREQ_CPF 0x88a |
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| 216 | #define mmMC_HUB_WDP_CPC 0x88b |
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| 217 | #define mmMC_HUB_WDP_CPF 0x88c |
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| 218 | #define mmMC_RPB_CONF 0x94d |
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| 219 | #define mmMC_RPB_IF_CONF 0x94e |
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| 220 | #define mmMC_RPB_DBG1 0x94f |
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| 221 | #define mmMC_RPB_EFF_CNTL 0x950 |
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| 222 | #define mmMC_RPB_ARB_CNTL 0x951 |
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| 223 | #define mmMC_RPB_BIF_CNTL 0x952 |
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| 224 | #define mmMC_RPB_WR_SWITCH_CNTL 0x953 |
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| 225 | #define mmMC_RPB_WR_COMBINE_CNTL 0x954 |
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| 226 | #define mmMC_RPB_RD_SWITCH_CNTL 0x955 |
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| 227 | #define mmMC_RPB_CID_QUEUE_WR 0x956 |
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| 228 | #define mmMC_RPB_CID_QUEUE_RD 0x957 |
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| 229 | #define mmMC_RPB_PERF_COUNTER_CNTL 0x958 |
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| 230 | #define mmMC_RPB_PERF_COUNTER_STATUS 0x959 |
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| 231 | #define mmMC_RPB_CID_QUEUE_EX 0x95a |
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| 232 | #define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b |
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| 233 | #define mmMC_SHARED_CHMAP 0x801 |
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| 234 | #define mmMC_SHARED_CHREMAP 0x802 |
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| 235 | #define mmMC_RD_GRP_GFX 0x803 |
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| 236 | #define mmMC_WR_GRP_GFX 0x804 |
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| 237 | #define mmMC_RD_GRP_SYS 0x805 |
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| 238 | #define mmMC_WR_GRP_SYS 0x806 |
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| 239 | #define mmMC_RD_GRP_OTH 0x807 |
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| 240 | #define mmMC_WR_GRP_OTH 0x808 |
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| 241 | #define mmMC_VM_FB_LOCATION 0x809 |
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| 242 | #define mmMC_VM_AGP_TOP 0x80a |
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| 243 | #define mmMC_VM_AGP_BOT 0x80b |
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| 244 | #define mmMC_VM_AGP_BASE 0x80c |
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| 245 | #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d |
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| 246 | #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e |
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| 247 | #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f |
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| 248 | #define mmMC_VM_DC_WRITE_CNTL 0x810 |
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| 249 | #define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 |
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| 250 | #define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 |
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| 251 | #define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 |
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| 252 | #define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 |
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| 253 | #define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 |
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| 254 | #define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 |
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| 255 | #define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 |
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| 256 | #define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 |
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| 257 | #define mmMC_VM_MX_L1_TLB_CNTL 0x819 |
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| 258 | #define mmMC_VM_FB_OFFSET 0x81a |
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| 259 | #define mmMC_VM_STEERING 0x81b |
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| 260 | #define mmMC_CONFIG_MCD 0x828 |
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| 261 | #define mmMC_CG_CONFIG_MCD 0x829 |
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| 262 | #define mmMC_MEM_POWER_LS 0x82a |
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| 263 | #define mmMC_SHARED_BLACKOUT_CNTL 0x82b |
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| 264 | #define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 |
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| 265 | #define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 |
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| 266 | #define mmMC_VM_MB_L1_TLB0_STATUS 0x895 |
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| 267 | #define mmMC_VM_MB_L1_TLB1_STATUS 0x896 |
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| 268 | #define mmMC_VM_MB_L1_TLB2_STATUS 0x897 |
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| 269 | #define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 |
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| 270 | #define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 |
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| 271 | #define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 |
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| 272 | #define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 |
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| 273 | #define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 |
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| 274 | #define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a |
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| 275 | #define mmMC_VM_MD_L1_TLB0_STATUS 0x99b |
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| 276 | #define mmMC_VM_MD_L1_TLB1_STATUS 0x99c |
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| 277 | #define mmMC_VM_MD_L1_TLB2_STATUS 0x99d |
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| 278 | #define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 |
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| 279 | #define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 |
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| 280 | #define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 |
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| 281 | #define mmMC_XPB_RTR_SRC_APRTR0 0x8cd |
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| 282 | #define mmMC_XPB_RTR_SRC_APRTR1 0x8ce |
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| 283 | #define mmMC_XPB_RTR_SRC_APRTR2 0x8cf |
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| 284 | #define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 |
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| 285 | #define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 |
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| 286 | #define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 |
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| 287 | #define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 |
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| 288 | #define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 |
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| 289 | #define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 |
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| 290 | #define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 |
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| 291 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 |
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| 292 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 |
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| 293 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 |
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| 294 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da |
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| 295 | #define mmMC_XPB_RTR_DEST_MAP0 0x8db |
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| 296 | #define mmMC_XPB_RTR_DEST_MAP1 0x8dc |
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| 297 | #define mmMC_XPB_RTR_DEST_MAP2 0x8dd |
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| 298 | #define mmMC_XPB_RTR_DEST_MAP3 0x8de |
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| 299 | #define mmMC_XPB_RTR_DEST_MAP4 0x8df |
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| 300 | #define mmMC_XPB_RTR_DEST_MAP5 0x8e0 |
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| 301 | #define mmMC_XPB_RTR_DEST_MAP6 0x8e1 |
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| 302 | #define mmMC_XPB_RTR_DEST_MAP7 0x8e2 |
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| 303 | #define mmMC_XPB_RTR_DEST_MAP8 0x8e3 |
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| 304 | #define mmMC_XPB_RTR_DEST_MAP9 0x8e4 |
|---|
| 305 | #define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 |
|---|
| 306 | #define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 |
|---|
| 307 | #define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 |
|---|
| 308 | #define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 |
|---|
| 309 | #define mmMC_XPB_CLG_CFG0 0x8e9 |
|---|
| 310 | #define mmMC_XPB_CLG_CFG1 0x8ea |
|---|
| 311 | #define mmMC_XPB_CLG_CFG2 0x8eb |
|---|
| 312 | #define mmMC_XPB_CLG_CFG3 0x8ec |
|---|
| 313 | #define mmMC_XPB_CLG_CFG4 0x8ed |
|---|
| 314 | #define mmMC_XPB_CLG_CFG5 0x8ee |
|---|
| 315 | #define mmMC_XPB_CLG_CFG6 0x8ef |
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| 316 | #define mmMC_XPB_CLG_CFG7 0x8f0 |
|---|
| 317 | #define mmMC_XPB_CLG_CFG8 0x8f1 |
|---|
| 318 | #define mmMC_XPB_CLG_CFG9 0x8f2 |
|---|
| 319 | #define mmMC_XPB_CLG_CFG10 0x8f3 |
|---|
| 320 | #define mmMC_XPB_CLG_CFG11 0x8f4 |
|---|
| 321 | #define mmMC_XPB_CLG_CFG12 0x8f5 |
|---|
| 322 | #define mmMC_XPB_CLG_CFG13 0x8f6 |
|---|
| 323 | #define mmMC_XPB_CLG_CFG14 0x8f7 |
|---|
| 324 | #define mmMC_XPB_CLG_CFG15 0x8f8 |
|---|
| 325 | #define mmMC_XPB_CLG_CFG16 0x8f9 |
|---|
| 326 | #define mmMC_XPB_CLG_CFG17 0x8fa |
|---|
| 327 | #define mmMC_XPB_CLG_CFG18 0x8fb |
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| 328 | #define mmMC_XPB_CLG_CFG19 0x8fc |
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| 329 | #define 0x8fd |
|---|
| 330 | #define mmMC_XPB_LB_ADDR 0x8fe |
|---|
| 331 | #define mmMC_XPB_UNC_THRESH_HST 0x8ff |
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| 332 | #define mmMC_XPB_UNC_THRESH_SID 0x900 |
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| 333 | #define mmMC_XPB_WCB_STS 0x901 |
|---|
| 334 | #define mmMC_XPB_WCB_CFG 0x902 |
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| 335 | #define mmMC_XPB_P2P_BAR_CFG 0x903 |
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| 336 | #define mmMC_XPB_P2P_BAR0 0x904 |
|---|
| 337 | #define mmMC_XPB_P2P_BAR1 0x905 |
|---|
| 338 | #define mmMC_XPB_P2P_BAR2 0x906 |
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| 339 | #define mmMC_XPB_P2P_BAR3 0x907 |
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| 340 | #define mmMC_XPB_P2P_BAR4 0x908 |
|---|
| 341 | #define mmMC_XPB_P2P_BAR5 0x909 |
|---|
| 342 | #define mmMC_XPB_P2P_BAR6 0x90a |
|---|
| 343 | #define mmMC_XPB_P2P_BAR7 0x90b |
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| 344 | #define mmMC_XPB_P2P_BAR_SETUP 0x90c |
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| 345 | #define mmMC_XPB_P2P_BAR_DEBUG 0x90d |
|---|
| 346 | #define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e |
|---|
| 347 | #define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f |
|---|
| 348 | #define mmMC_XPB_PEER_SYS_BAR0 0x910 |
|---|
| 349 | #define mmMC_XPB_PEER_SYS_BAR1 0x911 |
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| 350 | #define mmMC_XPB_PEER_SYS_BAR2 0x912 |
|---|
| 351 | #define mmMC_XPB_PEER_SYS_BAR3 0x913 |
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| 352 | #define mmMC_XPB_PEER_SYS_BAR4 0x914 |
|---|
| 353 | #define mmMC_XPB_PEER_SYS_BAR5 0x915 |
|---|
| 354 | #define mmMC_XPB_PEER_SYS_BAR6 0x916 |
|---|
| 355 | #define mmMC_XPB_PEER_SYS_BAR7 0x917 |
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| 356 | #define mmMC_XPB_PEER_SYS_BAR8 0x918 |
|---|
| 357 | #define mmMC_XPB_PEER_SYS_BAR9 0x919 |
|---|
| 358 | #define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a |
|---|
| 359 | #define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b |
|---|
| 360 | #define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c |
|---|
| 361 | #define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d |
|---|
| 362 | #define mmMC_XPB_CLK_GAT 0x91e |
|---|
| 363 | #define mmMC_XPB_INTF_CFG 0x91f |
|---|
| 364 | #define mmMC_XPB_INTF_STS 0x920 |
|---|
| 365 | #define mmMC_XPB_PIPE_STS 0x921 |
|---|
| 366 | #define mmMC_XPB_SUB_CTRL 0x922 |
|---|
| 367 | #define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 |
|---|
| 368 | #define mmMC_XPB_PERF_KNOBS 0x924 |
|---|
| 369 | #define mmMC_XPB_STICKY 0x925 |
|---|
| 370 | #define mmMC_XPB_STICKY_W1C 0x926 |
|---|
| 371 | #define mmMC_XPB_MISC_CFG 0x927 |
|---|
| 372 | #define mmMC_XPB_CLG_CFG20 0x928 |
|---|
| 373 | #define mmMC_XPB_CLG_CFG21 0x929 |
|---|
| 374 | #define mmMC_XPB_CLG_CFG22 0x92a |
|---|
| 375 | #define mmMC_XPB_CLG_CFG23 0x92b |
|---|
| 376 | #define mmMC_XPB_CLG_CFG24 0x92c |
|---|
| 377 | #define mmMC_XPB_CLG_CFG25 0x92d |
|---|
| 378 | #define mmMC_XPB_CLG_CFG26 0x92e |
|---|
| 379 | #define mmMC_XPB_CLG_CFG27 0x92f |
|---|
| 380 | #define mmMC_XPB_CLG_CFG28 0x930 |
|---|
| 381 | #define mmMC_XPB_CLG_CFG29 0x931 |
|---|
| 382 | #define mmMC_XPB_CLG_CFG30 0x932 |
|---|
| 383 | #define mmMC_XPB_CLG_CFG31 0x933 |
|---|
| 384 | #define mmMC_XPB_INTF_CFG2 0x934 |
|---|
| 385 | #define 0x935 |
|---|
| 386 | #define mmMC_XPB_CLG_CFG32 0x936 |
|---|
| 387 | #define mmMC_XPB_CLG_CFG33 0x937 |
|---|
| 388 | #define mmMC_XPB_CLG_CFG34 0x938 |
|---|
| 389 | #define mmMC_XPB_CLG_CFG35 0x939 |
|---|
| 390 | #define mmMC_XPB_CLG_CFG36 0x93a |
|---|
| 391 | #define mmMC_XBAR_ADDR_DEC 0xc80 |
|---|
| 392 | #define mmMC_XBAR_REMOTE 0xc81 |
|---|
| 393 | #define mmMC_XBAR_WRREQ_CREDIT 0xc82 |
|---|
| 394 | #define mmMC_XBAR_RDREQ_CREDIT 0xc83 |
|---|
| 395 | #define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 |
|---|
| 396 | #define mmMC_XBAR_WRRET_CREDIT1 0xc85 |
|---|
| 397 | #define mmMC_XBAR_WRRET_CREDIT2 0xc86 |
|---|
| 398 | #define mmMC_XBAR_RDRET_CREDIT1 0xc87 |
|---|
| 399 | #define mmMC_XBAR_RDRET_CREDIT2 0xc88 |
|---|
| 400 | #define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 |
|---|
| 401 | #define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a |
|---|
| 402 | #define mmMC_XBAR_CHTRIREMAP 0xc8b |
|---|
| 403 | #define mmMC_XBAR_TWOCHAN 0xc8c |
|---|
| 404 | #define mmMC_XBAR_ARB 0xc8d |
|---|
| 405 | #define mmMC_XBAR_ARB_MAX_BURST 0xc8e |
|---|
| 406 | #define mmMC_XBAR_PERF_MON_CNTL0 0xc8f |
|---|
| 407 | #define mmMC_XBAR_PERF_MON_CNTL1 0xc90 |
|---|
| 408 | #define mmMC_XBAR_PERF_MON_CNTL2 0xc91 |
|---|
| 409 | #define mmMC_XBAR_PERF_MON_RSLT0 0xc92 |
|---|
| 410 | #define mmMC_XBAR_PERF_MON_RSLT1 0xc93 |
|---|
| 411 | #define mmMC_XBAR_PERF_MON_RSLT2 0xc94 |
|---|
| 412 | #define mmMC_XBAR_PERF_MON_RSLT3 0xc95 |
|---|
| 413 | #define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96 |
|---|
| 414 | #define mmMC_XBAR_SPARE0 0xc97 |
|---|
| 415 | #define mmMC_XBAR_SPARE1 0xc98 |
|---|
| 416 | #define mmMC_CITF_PERFCOUNTER_LO 0x7a0 |
|---|
| 417 | #define mmMC_HUB_PERFCOUNTER_LO 0x7a1 |
|---|
| 418 | #define mmMC_RPB_PERFCOUNTER_LO 0x7a2 |
|---|
| 419 | #define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 |
|---|
| 420 | #define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 |
|---|
| 421 | #define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 |
|---|
| 422 | #define mmMC_ARB_PERFCOUNTER_LO 0x7a6 |
|---|
| 423 | #define mmATC_PERFCOUNTER_LO 0x7a7 |
|---|
| 424 | #define mmMC_CITF_PERFCOUNTER_HI 0x7a8 |
|---|
| 425 | #define mmMC_HUB_PERFCOUNTER_HI 0x7a9 |
|---|
| 426 | #define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa |
|---|
| 427 | #define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab |
|---|
| 428 | #define mmMC_RPB_PERFCOUNTER_HI 0x7ac |
|---|
| 429 | #define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad |
|---|
| 430 | #define mmMC_ARB_PERFCOUNTER_HI 0x7ae |
|---|
| 431 | #define mmATC_PERFCOUNTER_HI 0x7af |
|---|
| 432 | #define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 |
|---|
| 433 | #define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 |
|---|
| 434 | #define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 |
|---|
| 435 | #define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 |
|---|
| 436 | #define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 |
|---|
| 437 | #define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 |
|---|
| 438 | #define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 |
|---|
| 439 | #define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 |
|---|
| 440 | #define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 |
|---|
| 441 | #define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 |
|---|
| 442 | #define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba |
|---|
| 443 | #define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb |
|---|
| 444 | #define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc |
|---|
| 445 | #define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd |
|---|
| 446 | #define mmMC_ARB_PERFCOUNTER2_CFG 0x7be |
|---|
| 447 | #define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf |
|---|
| 448 | #define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 |
|---|
| 449 | #define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 |
|---|
| 450 | #define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 |
|---|
| 451 | #define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 |
|---|
| 452 | #define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 |
|---|
| 453 | #define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 |
|---|
| 454 | #define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 |
|---|
| 455 | #define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 |
|---|
| 456 | #define mmATC_PERFCOUNTER0_CFG 0x7c8 |
|---|
| 457 | #define mmATC_PERFCOUNTER1_CFG 0x7c9 |
|---|
| 458 | #define mmATC_PERFCOUNTER2_CFG 0x7ca |
|---|
| 459 | #define mmATC_PERFCOUNTER3_CFG 0x7cb |
|---|
| 460 | #define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc |
|---|
| 461 | #define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd |
|---|
| 462 | #define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce |
|---|
| 463 | #define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf |
|---|
| 464 | #define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 |
|---|
| 465 | #define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 |
|---|
| 466 | #define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 |
|---|
| 467 | #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 |
|---|
| 468 | #define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 |
|---|
| 469 | #define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 |
|---|
| 470 | #define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 |
|---|
| 471 | #define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 |
|---|
| 472 | #define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 |
|---|
| 473 | #define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 |
|---|
| 474 | #define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da |
|---|
| 475 | #define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db |
|---|
| 476 | #define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 |
|---|
| 477 | #define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 |
|---|
| 478 | #define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 |
|---|
| 479 | #define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 |
|---|
| 480 | #define mmATC_VM_APERTURE0_CNTL 0xcc4 |
|---|
| 481 | #define mmATC_VM_APERTURE1_CNTL 0xcc5 |
|---|
| 482 | #define mmATC_VM_APERTURE0_CNTL2 0xcc6 |
|---|
| 483 | #define mmATC_VM_APERTURE1_CNTL2 0xcc7 |
|---|
| 484 | #define mmATC_ATS_CNTL 0xcc9 |
|---|
| 485 | #define mmATC_ATS_DEBUG 0xcca |
|---|
| 486 | #define mmATC_ATS_FAULT_DEBUG 0xccb |
|---|
| 487 | #define mmATC_ATS_STATUS 0xccc |
|---|
| 488 | #define mmATC_ATS_FAULT_CNTL 0xccd |
|---|
| 489 | #define mmATC_ATS_FAULT_STATUS_INFO 0xcce |
|---|
| 490 | #define mmATC_ATS_FAULT_STATUS_ADDR 0xccf |
|---|
| 491 | #define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 |
|---|
| 492 | #define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 |
|---|
| 493 | #define mmATC_MISC_CG 0xcd4 |
|---|
| 494 | #define mmATC_L2_CNTL 0xcd5 |
|---|
| 495 | #define mmATC_L2_CNTL2 0xcd6 |
|---|
| 496 | #define mmATC_L2_DEBUG 0xcd7 |
|---|
| 497 | #define mmATC_L2_DEBUG2 0xcd8 |
|---|
| 498 | #define mmATC_L1_CNTL 0xcdc |
|---|
| 499 | #define mmATC_L1_ADDRESS_OFFSET 0xcdd |
|---|
| 500 | #define mmATC_L1RD_DEBUG_TLB 0xcde |
|---|
| 501 | #define mmATC_L1WR_DEBUG_TLB 0xcdf |
|---|
| 502 | #define mmATC_L1RD_STATUS 0xce0 |
|---|
| 503 | #define mmATC_L1WR_STATUS 0xce1 |
|---|
| 504 | #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 |
|---|
| 505 | #define mmATC_VMID0_PASID_MAPPING 0xce7 |
|---|
| 506 | #define mmATC_VMID1_PASID_MAPPING 0xce8 |
|---|
| 507 | #define mmATC_VMID2_PASID_MAPPING 0xce9 |
|---|
| 508 | #define mmATC_VMID3_PASID_MAPPING 0xcea |
|---|
| 509 | #define mmATC_VMID4_PASID_MAPPING 0xceb |
|---|
| 510 | #define mmATC_VMID5_PASID_MAPPING 0xcec |
|---|
| 511 | #define mmATC_VMID6_PASID_MAPPING 0xced |
|---|
| 512 | #define mmATC_VMID7_PASID_MAPPING 0xcee |
|---|
| 513 | #define mmATC_VMID8_PASID_MAPPING 0xcef |
|---|
| 514 | #define mmATC_VMID9_PASID_MAPPING 0xcf0 |
|---|
| 515 | #define mmATC_VMID10_PASID_MAPPING 0xcf1 |
|---|
| 516 | #define mmATC_VMID11_PASID_MAPPING 0xcf2 |
|---|
| 517 | #define mmATC_VMID12_PASID_MAPPING 0xcf3 |
|---|
| 518 | #define mmATC_VMID13_PASID_MAPPING 0xcf4 |
|---|
| 519 | #define mmATC_VMID14_PASID_MAPPING 0xcf5 |
|---|
| 520 | #define mmATC_VMID15_PASID_MAPPING 0xcf6 |
|---|
| 521 | #define mmGMCON_RENG_RAM_INDEX 0xd40 |
|---|
| 522 | #define mmGMCON_RENG_RAM_DATA 0xd41 |
|---|
| 523 | #define mmGMCON_RENG_EXECUTE 0xd42 |
|---|
| 524 | #define mmGMCON_MISC 0xd43 |
|---|
| 525 | #define mmGMCON_MISC2 0xd44 |
|---|
| 526 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 |
|---|
| 527 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 |
|---|
| 528 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 |
|---|
| 529 | #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 |
|---|
| 530 | #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 |
|---|
| 531 | #define mmGMCON_PERF_MON_CNTL0 0xd4a |
|---|
| 532 | #define mmGMCON_PERF_MON_CNTL1 0xd4b |
|---|
| 533 | #define mmGMCON_PERF_MON_RSLT0 0xd4c |
|---|
| 534 | #define mmGMCON_PERF_MON_RSLT1 0xd4d |
|---|
| 535 | #define mmGMCON_PGFSM_CONFIG 0xd4e |
|---|
| 536 | #define mmGMCON_PGFSM_WRITE 0xd4f |
|---|
| 537 | #define mmGMCON_PGFSM_READ 0xd50 |
|---|
| 538 | #define mmGMCON_MISC3 0xd51 |
|---|
| 539 | #define mmGMCON_MASK 0xd52 |
|---|
| 540 | #define mmGMCON_DEBUG 0xd5f |
|---|
| 541 | #define mmVM_L2_CNTL 0x500 |
|---|
| 542 | #define mmVM_L2_CNTL2 0x501 |
|---|
| 543 | #define mmVM_L2_CNTL3 0x502 |
|---|
| 544 | #define mmVM_L2_STATUS 0x503 |
|---|
| 545 | #define mmVM_CONTEXT0_CNTL 0x504 |
|---|
| 546 | #define mmVM_CONTEXT1_CNTL 0x505 |
|---|
| 547 | #define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 |
|---|
| 548 | #define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 |
|---|
| 549 | #define mmVM_CONTEXT0_CNTL2 0x50c |
|---|
| 550 | #define mmVM_CONTEXT1_CNTL2 0x50d |
|---|
| 551 | #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e |
|---|
| 552 | #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f |
|---|
| 553 | #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 |
|---|
| 554 | #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 |
|---|
| 555 | #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 |
|---|
| 556 | #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 |
|---|
| 557 | #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 |
|---|
| 558 | #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 |
|---|
| 559 | #define mmVM_INVALIDATE_REQUEST 0x51e |
|---|
| 560 | #define mmVM_INVALIDATE_RESPONSE 0x51f |
|---|
| 561 | #define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c |
|---|
| 562 | #define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d |
|---|
| 563 | #define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e |
|---|
| 564 | #define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f |
|---|
| 565 | #define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 |
|---|
| 566 | #define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 |
|---|
| 567 | #define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 |
|---|
| 568 | #define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 |
|---|
| 569 | #define mmVM_PRT_CNTL 0x534 |
|---|
| 570 | #define mmVM_CONTEXTS_DISABLE 0x535 |
|---|
| 571 | #define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 |
|---|
| 572 | #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 |
|---|
| 573 | #define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 |
|---|
| 574 | #define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 |
|---|
| 575 | #define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e |
|---|
| 576 | #define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f |
|---|
| 577 | #define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 |
|---|
| 578 | #define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 |
|---|
| 579 | #define mmVM_FAULT_CLIENT_ID 0x54e |
|---|
| 580 | #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f |
|---|
| 581 | #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 |
|---|
| 582 | #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 |
|---|
| 583 | #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 |
|---|
| 584 | #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 |
|---|
| 585 | #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 |
|---|
| 586 | #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 |
|---|
| 587 | #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 |
|---|
| 588 | #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 |
|---|
| 589 | #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 |
|---|
| 590 | #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f |
|---|
| 591 | #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 |
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| 592 | #define mmVM_DEBUG 0x56f |
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| 593 | #define mmVM_L2_CG 0x570 |
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| 594 | #define mmVM_L2_BANK_SELECT_MASKA 0x572 |
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| 595 | #define mmVM_L2_BANK_SELECT_MASKB 0x573 |
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| 596 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 |
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| 597 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 |
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| 598 | #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 |
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| 599 | #define mmMC_ARB_HARSH_EN_RD 0xdc0 |
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| 600 | #define mmMC_ARB_HARSH_EN_WR 0xdc1 |
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| 601 | #define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 |
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| 602 | #define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 |
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| 603 | #define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 |
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| 604 | #define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 |
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| 605 | #define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 |
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| 606 | #define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 |
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| 607 | #define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 |
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| 608 | #define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 |
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| 609 | #define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca |
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| 610 | #define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb |
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| 611 | #define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc |
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| 612 | #define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd |
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| 613 | #define mmMC_ARB_HARSH_BWCNT0_RD 0xdce |
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| 614 | #define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf |
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| 615 | #define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 |
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| 616 | #define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 |
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| 617 | #define mmMC_ARB_HARSH_SAT0_RD 0xdd2 |
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| 618 | #define mmMC_ARB_HARSH_SAT0_WR 0xdd3 |
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| 619 | #define mmMC_ARB_HARSH_SAT1_RD 0xdd4 |
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| 620 | #define mmMC_ARB_HARSH_SAT1_WR 0xdd5 |
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| 621 | #define mmMC_ARB_HARSH_CTL_RD 0xdd6 |
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| 622 | #define mmMC_ARB_HARSH_CTL_WR 0xdd7 |
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| 623 | #define mmMC_FUS_DRAM0_CS0_BASE 0xa05 |
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| 624 | #define mmMC_FUS_DRAM1_CS0_BASE 0xa06 |
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| 625 | #define mmMC_FUS_DRAM0_CS1_BASE 0xa07 |
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| 626 | #define mmMC_FUS_DRAM1_CS1_BASE 0xa08 |
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| 627 | #define mmMC_FUS_DRAM0_CS2_BASE 0xa09 |
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| 628 | #define mmMC_FUS_DRAM1_CS2_BASE 0xa0a |
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| 629 | #define mmMC_FUS_DRAM0_CS3_BASE 0xa0b |
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| 630 | #define mmMC_FUS_DRAM1_CS3_BASE 0xa0c |
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| 631 | #define mmMC_FUS_DRAM0_CS01_MASK 0xa0d |
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| 632 | #define mmMC_FUS_DRAM1_CS01_MASK 0xa0e |
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| 633 | #define mmMC_FUS_DRAM0_CS23_MASK 0xa0f |
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| 634 | #define mmMC_FUS_DRAM1_CS23_MASK 0xa10 |
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| 635 | #define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 |
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| 636 | #define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 |
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| 637 | #define mmMC_FUS_DRAM0_CTL_BASE 0xa13 |
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| 638 | #define mmMC_FUS_DRAM1_CTL_BASE 0xa14 |
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| 639 | #define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 |
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| 640 | #define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 |
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| 641 | #define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 |
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| 642 | #define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 |
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| 643 | #define mmMC_FUS_DRAM_MODE 0xa19 |
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| 644 | #define mmMC_FUS_DRAM_APER_BASE 0xa1a |
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| 645 | #define mmMC_FUS_DRAM_APER_TOP 0xa1b |
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| 646 | #define mmMC_FUS_DRAM_C6SAVE_APER_BASE 0xa1c |
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| 647 | #define mmMC_FUS_DRAM_C6SAVE_APER_TOP 0xa1d |
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| 648 | #define mmMC_FUS_DRAM_APER_DEF 0xa1e |
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| 649 | #define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f |
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| 650 | #define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 |
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| 651 | #define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 |
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| 652 | #define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 |
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| 653 | #define mmMC_CG_DATAPORT 0xa32 |
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| 654 | #define mmCHUB_ATC_L1_DEBUG_TLB 0x8c00 |
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| 655 | #define mmCHUB_ATC_L1_STATUS 0x8c01 |
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| 656 | |
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| 657 | #endif /* GMC_7_0_D_H */ |
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| 658 | |
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