1/*
2 * GMC_7_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GMC_7_1_D_H
25#define GMC_7_1_D_H
26
27#define mmMC_CONFIG 0x800
28#define mmMC_ARB_AGE_CNTL 0x9bf
29#define mmMC_ARB_RET_CREDITS2 0x9c0
30#define mmMC_ARB_FED_CNTL 0x9c1
31#define mmMC_ARB_GECC2_STATUS 0x9c2
32#define mmMC_ARB_GECC2_MISC 0x9c3
33#define mmMC_ARB_GECC2_DEBUG 0x9c4
34#define mmMC_ARB_GECC2_DEBUG2 0x9c5
35#define mmMC_ARB_PERF_CID 0x9c6
36#define mmMC_ARB_GECC2 0x9c9
37#define mmMC_ARB_GECC2_CLI 0x9ca
38#define mmMC_ARB_ADDR_SWIZ0 0x9cb
39#define mmMC_ARB_ADDR_SWIZ1 0x9cc
40#define mmMC_ARB_MISC3 0x9cd
41#define mmMC_ARB_WCDR_2 0x9ce
42#define mmMC_ARB_RTT_DATA 0x9cf
43#define mmMC_ARB_RTT_CNTL0 0x9d0
44#define mmMC_ARB_RTT_CNTL1 0x9d1
45#define mmMC_ARB_RTT_CNTL2 0x9d2
46#define mmMC_ARB_RTT_DEBUG 0x9d3
47#define mmMC_ARB_CAC_CNTL 0x9d4
48#define mmMC_ARB_MISC2 0x9d5
49#define mmMC_ARB_MISC 0x9d6
50#define mmMC_ARB_BANKMAP 0x9d7
51#define mmMC_ARB_RAMCFG 0x9d8
52#define mmMC_ARB_POP 0x9d9
53#define mmMC_ARB_MINCLKS 0x9da
54#define mmMC_ARB_SQM_CNTL 0x9db
55#define mmMC_ARB_ADDR_HASH 0x9dc
56#define mmMC_ARB_DRAM_TIMING 0x9dd
57#define mmMC_ARB_DRAM_TIMING2 0x9de
58#define mmMC_ARB_WTM_CNTL_RD 0x9df
59#define mmMC_ARB_WTM_CNTL_WR 0x9e0
60#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
61#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
62#define mmMC_ARB_TM_CNTL_RD 0x9e3
63#define mmMC_ARB_TM_CNTL_WR 0x9e4
64#define mmMC_ARB_LAZY0_RD 0x9e5
65#define mmMC_ARB_LAZY0_WR 0x9e6
66#define mmMC_ARB_LAZY1_RD 0x9e7
67#define mmMC_ARB_LAZY1_WR 0x9e8
68#define mmMC_ARB_AGE_RD 0x9e9
69#define mmMC_ARB_AGE_WR 0x9ea
70#define mmMC_ARB_RFSH_CNTL 0x9eb
71#define mmMC_ARB_RFSH_RATE 0x9ec
72#define mmMC_ARB_PM_CNTL 0x9ed
73#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
74#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
75#define mmMC_ARB_LM_RD 0x9f0
76#define mmMC_ARB_LM_WR 0x9f1
77#define mmMC_ARB_REMREQ 0x9f2
78#define mmMC_ARB_REPLAY 0x9f3
79#define mmMC_ARB_RET_CREDITS_RD 0x9f4
80#define mmMC_ARB_RET_CREDITS_WR 0x9f5
81#define mmMC_ARB_MAX_LAT_CID 0x9f6
82#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
83#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
84#define mmMC_ARB_SSM 0x9f9
85#define mmMC_ARB_CG 0x9fa
86#define mmMC_ARB_WCDR 0x9fb
87#define mmMC_ARB_DRAM_TIMING_1 0x9fc
88#define mmMC_ARB_BUSY_STATUS 0x9fd
89#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
90#define mmMC_ARB_BURST_TIME 0xa02
91#define mmMC_CITF_XTRA_ENABLE 0x96d
92#define mmCC_MC_MAX_CHANNEL 0x96e
93#define mmMC_CG_CONFIG 0x96f
94#define mmMC_CITF_CNTL 0x970
95#define mmMC_CITF_CREDITS_VM 0x971
96#define mmMC_CITF_CREDITS_ARB_RD 0x972
97#define mmMC_CITF_CREDITS_ARB_WR 0x973
98#define mmMC_CITF_DAGB_CNTL 0x974
99#define mmMC_CITF_INT_CREDITS 0x975
100#define mmMC_CITF_RET_MODE 0x976
101#define mmMC_CITF_DAGB_DLY 0x977
102#define mmMC_RD_GRP_EXT 0x978
103#define mmMC_WR_GRP_EXT 0x979
104#define mmMC_CITF_REMREQ 0x97a
105#define mmMC_WR_TC0 0x97b
106#define mmMC_WR_TC1 0x97c
107#define mmMC_CITF_INT_CREDITS_WR 0x97d
108#define mmMC_CITF_WTM_RD_CNTL 0x97f
109#define mmMC_CITF_WTM_WR_CNTL 0x980
110#define mmMC_RD_CB 0x981
111#define mmMC_RD_DB 0x982
112#define mmMC_RD_TC0 0x983
113#define mmMC_RD_TC1 0x984
114#define mmMC_RD_HUB 0x985
115#define mmMC_WR_CB 0x986
116#define mmMC_WR_DB 0x987
117#define mmMC_WR_HUB 0x988
118#define mmMC_CITF_CREDITS_XBAR 0x989
119#define mmMC_RD_GRP_LCL 0x98a
120#define mmMC_WR_GRP_LCL 0x98b
121#define mmMC_CITF_PERF_MON_CNTL2 0x98e
122#define mmMC_CITF_PERF_MON_RSLT2 0x991
123#define mmMC_CITF_MISC_RD_CG 0x992
124#define mmMC_CITF_MISC_WR_CG 0x993
125#define mmMC_CITF_MISC_VM_CG 0x994
126#define mmMC_HUB_MISC_POWER 0x82d
127#define mmMC_HUB_MISC_HUB_CG 0x82e
128#define mmMC_HUB_MISC_VM_CG 0x82f
129#define mmMC_HUB_MISC_SIP_CG 0x830
130#define mmMC_HUB_MISC_STATUS 0x832
131#define mmMC_HUB_MISC_OVERRIDE 0x833
132#define mmMC_HUB_MISC_FRAMING 0x834
133#define mmMC_HUB_WDP_CNTL 0x835
134#define mmMC_HUB_WDP_ERR 0x836
135#define mmMC_HUB_WDP_BP 0x837
136#define mmMC_HUB_WDP_STATUS 0x838
137#define mmMC_HUB_RDREQ_STATUS 0x839
138#define mmMC_HUB_WRRET_STATUS 0x83a
139#define mmMC_HUB_RDREQ_CNTL 0x83b
140#define mmMC_HUB_WRRET_CNTL 0x83c
141#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
142#define mmMC_HUB_WDP_WTM_CNTL 0x83e
143#define mmMC_HUB_WDP_CREDITS 0x83f
144#define mmMC_HUB_WDP_CREDITS2 0x840
145#define mmMC_HUB_WDP_GBL0 0x841
146#define mmMC_HUB_WDP_GBL1 0x842
147#define mmMC_HUB_RDREQ_CREDITS 0x844
148#define mmMC_HUB_RDREQ_CREDITS2 0x845
149#define mmMC_HUB_SHARED_DAGB_DLY 0x846
150#define mmMC_HUB_MISC_IDLE_STATUS 0x847
151#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
152#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
153#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
154#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
155#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
156#define mmMC_HUB_WDP_SH2 0x84d
157#define mmMC_HUB_WDP_SH3 0x84e
158#define mmMC_HUB_RDREQ_IA0 0x84f
159#define mmMC_HUB_RDREQ_IA1 0x850
160#define mmMC_HUB_RDREQ_MCDW 0x851
161#define mmMC_HUB_RDREQ_MCDX 0x852
162#define mmMC_HUB_RDREQ_MCDY 0x853
163#define mmMC_HUB_RDREQ_MCDZ 0x854
164#define mmMC_HUB_RDREQ_SIP 0x855
165#define mmMC_HUB_RDREQ_GBL0 0x856
166#define mmMC_HUB_RDREQ_GBL1 0x857
167#define mmMC_HUB_RDREQ_SMU 0x858
168#define mmMC_HUB_RDREQ_CPG 0x859
169#define mmMC_HUB_RDREQ_SDMA0 0x85a
170#define mmMC_HUB_RDREQ_HDP 0x85b
171#define mmMC_HUB_RDREQ_SDMA1 0x85c
172#define mmMC_HUB_RDREQ_RLC 0x85d
173#define mmMC_HUB_RDREQ_SEM 0x85e
174#define mmMC_HUB_RDREQ_VCE 0x85f
175#define mmMC_HUB_RDREQ_UMC 0x860
176#define mmMC_HUB_RDREQ_UVD 0x861
177#define mmMC_HUB_RDREQ_IA 0x862
178#define mmMC_HUB_RDREQ_DMIF 0x863
179#define mmMC_HUB_RDREQ_MCIF 0x864
180#define mmMC_HUB_RDREQ_VMC 0x865
181#define mmMC_HUB_RDREQ_VCEU 0x866
182#define mmMC_HUB_WDP_MCDW 0x867
183#define mmMC_HUB_WDP_MCDX 0x868
184#define mmMC_HUB_WDP_MCDY 0x869
185#define mmMC_HUB_WDP_MCDZ 0x86a
186#define mmMC_HUB_WDP_SIP 0x86b
187#define mmMC_HUB_WDP_CPG 0x86c
188#define mmMC_HUB_WDP_SDMA1 0x86d
189#define mmMC_HUB_WDP_SH0 0x86e
190#define mmMC_HUB_WDP_MCIF 0x86f
191#define mmMC_HUB_WDP_VCE 0x870
192#define mmMC_HUB_WDP_XDP 0x871
193#define mmMC_HUB_WDP_IH 0x872
194#define mmMC_HUB_WDP_RLC 0x873
195#define mmMC_HUB_WDP_SEM 0x874
196#define mmMC_HUB_WDP_SMU 0x875
197#define mmMC_HUB_WDP_SH1 0x876
198#define mmMC_HUB_WDP_UMC 0x877
199#define mmMC_HUB_WDP_UVD 0x878
200#define mmMC_HUB_WDP_HDP 0x879
201#define mmMC_HUB_WDP_SDMA0 0x87a
202#define mmMC_HUB_WRRET_MCDW 0x87b
203#define mmMC_HUB_WRRET_MCDX 0x87c
204#define mmMC_HUB_WRRET_MCDY 0x87d
205#define mmMC_HUB_WRRET_MCDZ 0x87e
206#define mmMC_HUB_WDP_VCEU 0x87f
207#define mmMC_HUB_WDP_XDMAM 0x880
208#define mmMC_HUB_WDP_XDMA 0x881
209#define mmMC_HUB_RDREQ_XDMAM 0x882
210#define mmMC_HUB_RDREQ_ACPG 0x883
211#define mmMC_HUB_RDREQ_ACPO 0x884
212#define mmMC_HUB_RDREQ_SAM 0x885
213#define mmMC_HUB_WDP_ACPG 0x886
214#define mmMC_HUB_WDP_ACPO 0x887
215#define mmMC_HUB_WDP_SAM 0x888
216#define mmMC_HUB_RDREQ_CPC 0x889
217#define mmMC_HUB_RDREQ_CPF 0x88a
218#define mmMC_HUB_WDP_CPC 0x88b
219#define mmMC_HUB_WDP_CPF 0x88c
220#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
221#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
222#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
223#define mmMC_HUB_WDP_ISP_SPM 0xde3
224#define mmMC_HUB_WDP_ISP_MPS 0xde4
225#define mmMC_HUB_WDP_ISP_MPM 0xde5
226#define mmMC_HUB_WDP_ISP_CCPU 0xde6
227#define mmMC_HUB_RDREQ_MCDS 0xde7
228#define mmMC_HUB_RDREQ_MCDT 0xde8
229#define mmMC_HUB_RDREQ_MCDU 0xde9
230#define mmMC_HUB_RDREQ_MCDV 0xdea
231#define mmMC_HUB_WDP_MCDS 0xdeb
232#define mmMC_HUB_WDP_MCDT 0xdec
233#define mmMC_HUB_WDP_MCDU 0xded
234#define mmMC_HUB_WDP_MCDV 0xdee
235#define mmMC_HUB_WRRET_MCDS 0xdef
236#define mmMC_HUB_WRRET_MCDT 0xdf0
237#define mmMC_HUB_WRRET_MCDU 0xdf1
238#define mmMC_HUB_WRRET_MCDV 0xdf2
239#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
240#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
241#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
242#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
243#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
244#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
245#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
246#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
247#define mmMC_HUB_WDP_BP2 0xdfb
248#define mmMC_RPB_CONF 0x94d
249#define mmMC_RPB_IF_CONF 0x94e
250#define mmMC_RPB_DBG1 0x94f
251#define mmMC_RPB_EFF_CNTL 0x950
252#define mmMC_RPB_ARB_CNTL 0x951
253#define mmMC_RPB_BIF_CNTL 0x952
254#define mmMC_RPB_WR_SWITCH_CNTL 0x953
255#define mmMC_RPB_WR_COMBINE_CNTL 0x954
256#define mmMC_RPB_RD_SWITCH_CNTL 0x955
257#define mmMC_RPB_CID_QUEUE_WR 0x956
258#define mmMC_RPB_CID_QUEUE_RD 0x957
259#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
260#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
261#define mmMC_RPB_CID_QUEUE_EX 0x95a
262#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
263#define mmMC_RPB_TCI_CNTL 0x95c
264#define mmMC_SHARED_CHMAP 0x801
265#define mmMC_SHARED_CHREMAP 0x802
266#define mmMC_RD_GRP_GFX 0x803
267#define mmMC_WR_GRP_GFX 0x804
268#define mmMC_RD_GRP_SYS 0x805
269#define mmMC_WR_GRP_SYS 0x806
270#define mmMC_RD_GRP_OTH 0x807
271#define mmMC_WR_GRP_OTH 0x808
272#define mmMC_VM_FB_LOCATION 0x809
273#define mmMC_VM_AGP_TOP 0x80a
274#define mmMC_VM_AGP_BOT 0x80b
275#define mmMC_VM_AGP_BASE 0x80c
276#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
277#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
278#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
279#define mmMC_VM_DC_WRITE_CNTL 0x810
280#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
281#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
282#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
283#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
284#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
285#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
286#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
287#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
288#define mmMC_VM_MX_L1_TLB_CNTL 0x819
289#define mmMC_VM_FB_OFFSET 0x81a
290#define mmMC_VM_STEERING 0x81b
291#define mmMC_SHARED_CHREMAP2 0x81c
292#define mmMC_CONFIG_MCD 0x828
293#define mmMC_CG_CONFIG_MCD 0x829
294#define mmMC_MEM_POWER_LS 0x82a
295#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
296#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
297#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
298#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
299#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
300#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
301#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
302#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
303#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
304#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
305#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
306#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
307#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
308#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
309#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
310#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
311#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
312#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
313#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
314#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
315#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
316#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
317#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
318#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
319#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
320#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
321#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
322#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
323#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
324#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
325#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
326#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
327#define mmMC_XPB_RTR_DEST_MAP0 0x8db
328#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
329#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
330#define mmMC_XPB_RTR_DEST_MAP3 0x8de
331#define mmMC_XPB_RTR_DEST_MAP4 0x8df
332#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
333#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
334#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
335#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
336#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
337#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
338#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
339#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
340#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
341#define mmMC_XPB_CLG_CFG0 0x8e9
342#define mmMC_XPB_CLG_CFG1 0x8ea
343#define mmMC_XPB_CLG_CFG2 0x8eb
344#define mmMC_XPB_CLG_CFG3 0x8ec
345#define mmMC_XPB_CLG_CFG4 0x8ed
346#define mmMC_XPB_CLG_CFG5 0x8ee
347#define mmMC_XPB_CLG_CFG6 0x8ef
348#define mmMC_XPB_CLG_CFG7 0x8f0
349#define mmMC_XPB_CLG_CFG8 0x8f1
350#define mmMC_XPB_CLG_CFG9 0x8f2
351#define mmMC_XPB_CLG_CFG10 0x8f3
352#define mmMC_XPB_CLG_CFG11 0x8f4
353#define mmMC_XPB_CLG_CFG12 0x8f5
354#define mmMC_XPB_CLG_CFG13 0x8f6
355#define mmMC_XPB_CLG_CFG14 0x8f7
356#define mmMC_XPB_CLG_CFG15 0x8f8
357#define mmMC_XPB_CLG_CFG16 0x8f9
358#define mmMC_XPB_CLG_CFG17 0x8fa
359#define mmMC_XPB_CLG_CFG18 0x8fb
360#define mmMC_XPB_CLG_CFG19 0x8fc
361#define mmMC_XPB_CLG_EXTRA 0x8fd
362#define mmMC_XPB_LB_ADDR 0x8fe
363#define mmMC_XPB_UNC_THRESH_HST 0x8ff
364#define mmMC_XPB_UNC_THRESH_SID 0x900
365#define mmMC_XPB_WCB_STS 0x901
366#define mmMC_XPB_WCB_CFG 0x902
367#define mmMC_XPB_P2P_BAR_CFG 0x903
368#define mmMC_XPB_P2P_BAR0 0x904
369#define mmMC_XPB_P2P_BAR1 0x905
370#define mmMC_XPB_P2P_BAR2 0x906
371#define mmMC_XPB_P2P_BAR3 0x907
372#define mmMC_XPB_P2P_BAR4 0x908
373#define mmMC_XPB_P2P_BAR5 0x909
374#define mmMC_XPB_P2P_BAR6 0x90a
375#define mmMC_XPB_P2P_BAR7 0x90b
376#define mmMC_XPB_P2P_BAR_SETUP 0x90c
377#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
378#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
379#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
380#define mmMC_XPB_PEER_SYS_BAR0 0x910
381#define mmMC_XPB_PEER_SYS_BAR1 0x911
382#define mmMC_XPB_PEER_SYS_BAR2 0x912
383#define mmMC_XPB_PEER_SYS_BAR3 0x913
384#define mmMC_XPB_PEER_SYS_BAR4 0x914
385#define mmMC_XPB_PEER_SYS_BAR5 0x915
386#define mmMC_XPB_PEER_SYS_BAR6 0x916
387#define mmMC_XPB_PEER_SYS_BAR7 0x917
388#define mmMC_XPB_PEER_SYS_BAR8 0x918
389#define mmMC_XPB_PEER_SYS_BAR9 0x919
390#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
391#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
392#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
393#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
394#define mmMC_XPB_CLK_GAT 0x91e
395#define mmMC_XPB_INTF_CFG 0x91f
396#define mmMC_XPB_INTF_STS 0x920
397#define mmMC_XPB_PIPE_STS 0x921
398#define mmMC_XPB_SUB_CTRL 0x922
399#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
400#define mmMC_XPB_PERF_KNOBS 0x924
401#define mmMC_XPB_STICKY 0x925
402#define mmMC_XPB_STICKY_W1C 0x926
403#define mmMC_XPB_MISC_CFG 0x927
404#define mmMC_XPB_CLG_CFG20 0x928
405#define mmMC_XPB_CLG_CFG21 0x929
406#define mmMC_XPB_CLG_CFG22 0x92a
407#define mmMC_XPB_CLG_CFG23 0x92b
408#define mmMC_XPB_CLG_CFG24 0x92c
409#define mmMC_XPB_CLG_CFG25 0x92d
410#define mmMC_XPB_CLG_CFG26 0x92e
411#define mmMC_XPB_CLG_CFG27 0x92f
412#define mmMC_XPB_CLG_CFG28 0x930
413#define mmMC_XPB_CLG_CFG29 0x931
414#define mmMC_XPB_CLG_CFG30 0x932
415#define mmMC_XPB_CLG_CFG31 0x933
416#define mmMC_XPB_INTF_CFG2 0x934
417#define mmMC_XPB_CLG_EXTRA_RD 0x935
418#define mmMC_XPB_CLG_CFG32 0x936
419#define mmMC_XPB_CLG_CFG33 0x937
420#define mmMC_XPB_CLG_CFG34 0x938
421#define mmMC_XPB_CLG_CFG35 0x939
422#define mmMC_XPB_CLG_CFG36 0x93a
423#define mmMC_XBAR_ADDR_DEC 0xc80
424#define mmMC_XBAR_REMOTE 0xc81
425#define mmMC_XBAR_WRREQ_CREDIT 0xc82
426#define mmMC_XBAR_RDREQ_CREDIT 0xc83
427#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
428#define mmMC_XBAR_WRRET_CREDIT1 0xc85
429#define mmMC_XBAR_WRRET_CREDIT2 0xc86
430#define mmMC_XBAR_RDRET_CREDIT1 0xc87
431#define mmMC_XBAR_RDRET_CREDIT2 0xc88
432#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
433#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
434#define mmMC_XBAR_CHTRIREMAP 0xc8b
435#define mmMC_XBAR_TWOCHAN 0xc8c
436#define mmMC_XBAR_ARB 0xc8d
437#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
438#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f
439#define mmMC_XBAR_PERF_MON_CNTL1 0xc90
440#define mmMC_XBAR_PERF_MON_CNTL2 0xc91
441#define mmMC_XBAR_PERF_MON_RSLT0 0xc92
442#define mmMC_XBAR_PERF_MON_RSLT1 0xc93
443#define mmMC_XBAR_PERF_MON_RSLT2 0xc94
444#define mmMC_XBAR_PERF_MON_RSLT3 0xc95
445#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96
446#define mmMC_XBAR_SPARE0 0xc97
447#define mmMC_XBAR_SPARE1 0xc98
448#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
449#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
450#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
451#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
452#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
453#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
454#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
455#define mmATC_PERFCOUNTER_LO 0x7a7
456#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
457#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
458#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
459#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
460#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
461#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
462#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
463#define mmATC_PERFCOUNTER_HI 0x7af
464#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
465#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
466#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
467#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
468#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
469#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
470#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
471#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
472#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
473#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
474#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
475#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
476#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
477#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
478#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
479#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
480#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
481#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
482#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
483#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
484#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
485#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
486#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
487#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
488#define mmATC_PERFCOUNTER0_CFG 0x7c8
489#define mmATC_PERFCOUNTER1_CFG 0x7c9
490#define mmATC_PERFCOUNTER2_CFG 0x7ca
491#define mmATC_PERFCOUNTER3_CFG 0x7cb
492#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
493#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
494#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
495#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
496#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
497#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
498#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
499#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
500#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
501#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
502#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
503#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
504#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
505#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
506#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
507#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db
508#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
509#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
510#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
511#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
512#define mmATC_VM_APERTURE0_CNTL 0xcc4
513#define mmATC_VM_APERTURE1_CNTL 0xcc5
514#define mmATC_VM_APERTURE0_CNTL2 0xcc6
515#define mmATC_VM_APERTURE1_CNTL2 0xcc7
516#define mmATC_ATS_CNTL 0xcc9
517#define mmATC_ATS_DEBUG 0xcca
518#define mmATC_ATS_FAULT_DEBUG 0xccb
519#define mmATC_ATS_STATUS 0xccc
520#define mmATC_ATS_FAULT_CNTL 0xccd
521#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
522#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
523#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
524#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
525#define mmATC_MISC_CG 0xcd4
526#define mmATC_L2_CNTL 0xcd5
527#define mmATC_L2_CNTL2 0xcd6
528#define mmATC_L2_DEBUG 0xcd7
529#define mmATC_L2_DEBUG2 0xcd8
530#define mmATC_L1_CNTL 0xcdc
531#define mmATC_L1_ADDRESS_OFFSET 0xcdd
532#define mmATC_L1RD_DEBUG_TLB 0xcde
533#define mmATC_L1WR_DEBUG_TLB 0xcdf
534#define mmATC_L1RD_STATUS 0xce0
535#define mmATC_L1WR_STATUS 0xce1
536#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
537#define mmATC_VMID0_PASID_MAPPING 0xce7
538#define mmATC_VMID1_PASID_MAPPING 0xce8
539#define mmATC_VMID2_PASID_MAPPING 0xce9
540#define mmATC_VMID3_PASID_MAPPING 0xcea
541#define mmATC_VMID4_PASID_MAPPING 0xceb
542#define mmATC_VMID5_PASID_MAPPING 0xcec
543#define mmATC_VMID6_PASID_MAPPING 0xced
544#define mmATC_VMID7_PASID_MAPPING 0xcee
545#define mmATC_VMID8_PASID_MAPPING 0xcef
546#define mmATC_VMID9_PASID_MAPPING 0xcf0
547#define mmATC_VMID10_PASID_MAPPING 0xcf1
548#define mmATC_VMID11_PASID_MAPPING 0xcf2
549#define mmATC_VMID12_PASID_MAPPING 0xcf3
550#define mmATC_VMID13_PASID_MAPPING 0xcf4
551#define mmATC_VMID14_PASID_MAPPING 0xcf5
552#define mmATC_VMID15_PASID_MAPPING 0xcf6
553#define mmGMCON_RENG_RAM_INDEX 0xd40
554#define mmGMCON_RENG_RAM_DATA 0xd41
555#define mmGMCON_RENG_EXECUTE 0xd42
556#define mmGMCON_MISC 0xd43
557#define mmGMCON_MISC2 0xd44
558#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
559#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
560#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
561#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
562#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
563#define mmGMCON_PERF_MON_CNTL0 0xd4a
564#define mmGMCON_PERF_MON_CNTL1 0xd4b
565#define mmGMCON_PERF_MON_RSLT0 0xd4c
566#define mmGMCON_PERF_MON_RSLT1 0xd4d
567#define mmGMCON_PGFSM_CONFIG 0xd4e
568#define mmGMCON_PGFSM_WRITE 0xd4f
569#define mmGMCON_PGFSM_READ 0xd50
570#define mmGMCON_MISC3 0xd51
571#define mmGMCON_MASK 0xd52
572#define mmGMCON_LPT_TARGET 0xd53
573#define mmGMCON_DEBUG 0xd5f
574#define mmVM_L2_CNTL 0x500
575#define mmVM_L2_CNTL2 0x501
576#define mmVM_L2_CNTL3 0x502
577#define mmVM_L2_STATUS 0x503
578#define mmVM_CONTEXT0_CNTL 0x504
579#define mmVM_CONTEXT1_CNTL 0x505
580#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
581#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
582#define mmVM_CONTEXT0_CNTL2 0x50c
583#define mmVM_CONTEXT1_CNTL2 0x50d
584#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
585#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
586#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
587#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
588#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
589#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
590#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
591#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
592#define mmVM_INVALIDATE_REQUEST 0x51e
593#define mmVM_INVALIDATE_RESPONSE 0x51f
594#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
595#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
596#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
597#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
598#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
599#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
600#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
601#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
602#define mmVM_PRT_CNTL 0x534
603#define mmVM_CONTEXTS_DISABLE 0x535
604#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
605#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
606#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
607#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
608#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
609#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
610#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
611#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
612#define mmVM_FAULT_CLIENT_ID 0x54e
613#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
614#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
615#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
616#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
617#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
618#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
619#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
620#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
621#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
622#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
623#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
624#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
625#define mmVM_DEBUG 0x56f
626#define mmVM_L2_CG 0x570
627#define mmVM_L2_BANK_SELECT_MASKA 0x572
628#define mmVM_L2_BANK_SELECT_MASKB 0x573
629#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
630#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
631#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
632#define mmMC_SEQ_CNTL 0xa25
633#define mmMC_SEQ_CNTL_2 0xad4
634#define mmMC_SEQ_DRAM 0xa26
635#define mmMC_SEQ_DRAM_2 0xa27
636#define mmMC_SEQ_RAS_TIMING 0xa28
637#define mmMC_SEQ_CAS_TIMING 0xa29
638#define mmMC_SEQ_MISC_TIMING 0xa2a
639#define mmMC_SEQ_MISC_TIMING2 0xa2b
640#define mmMC_SEQ_PMG_TIMING 0xa2c
641#define mmMC_SEQ_RD_CTL_D0 0xa2d
642#define mmMC_SEQ_RD_CTL_D1 0xa2e
643#define mmMC_SEQ_WR_CTL_D0 0xa2f
644#define mmMC_SEQ_WR_CTL_D1 0xa30
645#define mmMC_SEQ_WR_CTL_2 0xad5
646#define mmMC_SEQ_CMD 0xa31
647#define mmMC_PMG_CMD_EMRS 0xa83
648#define mmMC_PMG_CMD_MRS 0xaab
649#define mmMC_PMG_CMD_MRS1 0xad1
650#define mmMC_PMG_CMD_MRS2 0xad7
651#define mmMC_PMG_CFG 0xa84
652#define mmMC_PMG_AUTO_CMD 0xa34
653#define mmMC_PMG_AUTO_CFG 0xa35
654#define mmMC_IMP_CNTL 0xa36
655#define mmMC_IMP_DEBUG 0xa37
656#define mmMC_IMP_STATUS 0xa38
657#define mmMC_IMP_DQ_STATUS 0xabc
658#define mmMC_SEQ_WCDR_CTRL 0xa39
659#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a
660#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b
661#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe
662#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff
663#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c
664#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d
665#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e
666#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f
667#define mmMC_SEQ_TRAIN_TIMING 0xa40
668#define mmMC_TRAIN_EDCCDR_R_D0 0xa41
669#define mmMC_TRAIN_EDCCDR_R_D1 0xa42
670#define mmMC_TRAIN_PRBSERR_0_D0 0xa43
671#define mmMC_TRAIN_PRBSERR_1_D0 0xa44
672#define mmMC_TRAIN_PRBSERR_2_D0 0xafb
673#define mmMC_TRAIN_EDC_STATUS_D0 0xa45
674#define mmMC_TRAIN_PRBSERR_0_D1 0xa46
675#define mmMC_TRAIN_PRBSERR_1_D1 0xa47
676#define mmMC_TRAIN_PRBSERR_2_D1 0xafc
677#define mmMC_TRAIN_EDC_STATUS_D1 0xa48
678#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49
679#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a
680#define mmMC_IO_TXCNTL_APHY_D0 0xa4b
681#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c
682#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf
683#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d
684#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0
685#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e
686#define mmMC_IO_APHY_STR_CNTL_D0 0xa97
687#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f
688#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50
689#define mmMC_IO_TXCNTL_APHY_D1 0xa51
690#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52
691#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1
692#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53
693#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2
694#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54
695#define mmMC_IO_APHY_STR_CNTL_D1 0xa98
696#define mmMC_IO_CDRCNTL_D0 0xa55
697#define mmMC_IO_CDRCNTL1_D0 0xadd
698#define mmMC_IO_CDRCNTL2_D0 0xae4
699#define mmMC_IO_CDRCNTL_D1 0xa56
700#define mmMC_IO_CDRCNTL1_D1 0xade
701#define mmMC_IO_CDRCNTL2_D1 0xae5
702#define mmMC_SEQ_FIFO_CTL 0xa57
703#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58
704#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59
705#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a
706#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b
707#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c
708#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d
709#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e
710#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60
711#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61
712#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62
713#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63
714#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64
715#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65
716#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66
717#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67
718#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68
719#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69
720#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a
721#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b
722#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c
723#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d
724#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e
725#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f
726#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70
727#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71
728#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72
729#define mmMC_IO_PAD_CNTL 0xa73
730#define mmMC_IO_PAD_CNTL_D0 0xa74
731#define mmMC_IO_PAD_CNTL_D1 0xa75
732#define mmMC_NPL_STATUS 0xa76
733#define mmMC_BIST_CMD_CNTL 0xa8e
734#define mmMC_BIST_CNTL 0xa05
735#define mmMC_BIST_AUTO_CNTL 0xa06
736#define mmMC_BIST_DIR_CNTL 0xa07
737#define mmMC_BIST_SADDR 0xa08
738#define mmMC_BIST_EADDR 0xa09
739#define mmMC_BIST_CMP_CNTL 0xa8d
740#define mmMC_BIST_CMP_CNTL_2 0xab6
741#define mmMC_BIST_DATA_WORD0 0xa0a
742#define mmMC_BIST_DATA_WORD1 0xa0b
743#define mmMC_BIST_DATA_WORD2 0xa0c
744#define mmMC_BIST_DATA_WORD3 0xa0d
745#define mmMC_BIST_DATA_WORD4 0xa0e
746#define mmMC_BIST_DATA_WORD5 0xa0f
747#define mmMC_BIST_DATA_WORD6 0xa10
748#define mmMC_BIST_DATA_WORD7 0xa11
749#define mmMC_BIST_DATA_MASK 0xa12
750#define mmMC_BIST_MISMATCH_ADDR 0xa13
751#define mmMC_BIST_RDATA_WORD0 0xa14
752#define mmMC_BIST_RDATA_WORD1 0xa15
753#define mmMC_BIST_RDATA_WORD2 0xa16
754#define mmMC_BIST_RDATA_WORD3 0xa17
755#define mmMC_BIST_RDATA_WORD4 0xa18
756#define mmMC_BIST_RDATA_WORD5 0xa19
757#define mmMC_BIST_RDATA_WORD6 0xa1a
758#define mmMC_BIST_RDATA_WORD7 0xa1b
759#define mmMC_BIST_RDATA_MASK 0xa1c
760#define mmMC_BIST_RDATA_EDC 0xa1d
761#define mmMC_SEQ_PERF_CNTL 0xa77
762#define mmMC_SEQ_PERF_CNTL_1 0xafd
763#define mmMC_SEQ_PERF_SEQ_CTL 0xa78
764#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79
765#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a
766#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b
767#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c
768#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9
769#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada
770#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb
771#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc
772#define mmMC_SEQ_STATUS_M 0xa7d
773#define mmMC_SEQ_STATUS_S 0xa20
774#define mmMC_CG_DATAPORT 0xa21
775#define mmMC_SEQ_VENDOR_ID_I0 0xa7e
776#define mmMC_SEQ_VENDOR_ID_I1 0xa7f
777#define mmMC_SEQ_MISC0 0xa80
778#define mmMC_SEQ_MISC1 0xa81
779#define mmMC_SEQ_RESERVE_0_S 0xa1e
780#define mmMC_SEQ_RESERVE_1_S 0xa1f
781#define mmMC_SEQ_RESERVE_M 0xa82
782#define mmMC_SEQ_IO_RESERVE_D0 0xab7
783#define mmMC_SEQ_IO_RESERVE_D1 0xab8
784#define mmMC_SEQ_SUP_CNTL 0xa32
785#define mmMC_SEQ_SUP_PGM 0xa33
786#define mmMC_SEQ_SUP_GP0_STAT 0xa8f
787#define mmMC_SEQ_SUP_GP1_STAT 0xa90
788#define mmMC_SEQ_SUP_GP2_STAT 0xa85
789#define mmMC_SEQ_SUP_GP3_STAT 0xa86
790#define mmMC_SEQ_SUP_IR_STAT 0xa87
791#define mmMC_SEQ_SUP_DEC_STAT 0xa88
792#define mmMC_SEQ_SUP_PGM_STAT 0xa89
793#define mmMC_SEQ_SUP_R_PGM 0xa8a
794#define mmMC_SEQ_MISC3 0xa8b
795#define mmMC_SEQ_MISC4 0xa8c
796#define mmMC_SEQ_MISC5 0xa95
797#define mmMC_SEQ_MISC6 0xa96
798#define mmMC_SEQ_MISC7 0xa99
799#define mmMC_SEQ_MISC8 0xa5f
800#define mmMC_SEQ_MISC9 0xae7
801#define mmMC_SEQ_CG 0xa9a
802#define mmMC_SEQ_BYTE_REMAP_D0 0xa93
803#define mmMC_SEQ_BYTE_REMAP_D1 0xa94
804#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3
805#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4
806#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5
807#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6
808#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7
809#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8
810#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9
811#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa
812#define mmMC_SEQ_RAS_TIMING_LP 0xa9b
813#define mmMC_SEQ_CAS_TIMING_LP 0xa9c
814#define mmMC_SEQ_MISC_TIMING_LP 0xa9d
815#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e
816#define mmMC_SEQ_RD_CTL_D0_LP 0xac7
817#define mmMC_SEQ_RD_CTL_D1_LP 0xac8
818#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f
819#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0
820#define mmMC_SEQ_WR_CTL_2_LP 0xad6
821#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1
822#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2
823#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2
824#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8
825#define mmMC_SEQ_PMG_TIMING_LP 0xad3
826#define mmMC_SEQ_IO_RWORD0 0xaac
827#define mmMC_SEQ_IO_RWORD1 0xaad
828#define mmMC_SEQ_IO_RWORD2 0xaae
829#define mmMC_SEQ_IO_RWORD3 0xaaf
830#define mmMC_SEQ_IO_RWORD4 0xab0
831#define mmMC_SEQ_IO_RWORD5 0xab1
832#define mmMC_SEQ_IO_RWORD6 0xab2
833#define mmMC_SEQ_IO_RWORD7 0xab3
834#define mmMC_SEQ_IO_RDBI 0xab4
835#define mmMC_SEQ_IO_REDC 0xab5
836#define mmMC_SEQ_TCG_CNTL 0xabd
837#define mmMC_SEQ_TSM_CTRL 0xabe
838#define mmMC_SEQ_TSM_GCNT 0xabf
839#define mmMC_SEQ_TSM_OCNT 0xac0
840#define mmMC_SEQ_TSM_NCNT 0xac1
841#define mmMC_SEQ_TSM_BCNT 0xac2
842#define mmMC_SEQ_TSM_FLAG 0xac3
843#define mmMC_SEQ_TSM_UPDATE 0xac4
844#define mmMC_SEQ_TSM_EDC 0xac5
845#define mmMC_SEQ_TSM_DBI 0xac6
846#define mmMC_SEQ_TSM_WCDR 0xae3
847#define mmMC_SEQ_TSM_MISC 0xae6
848#define mmMC_SEQ_TIMER_WR 0xac9
849#define mmMC_SEQ_TIMER_RD 0xaca
850#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb
851#define mmMC_PHY_TIMING_D0 0xacc
852#define mmMC_PHY_TIMING_D1 0xacd
853#define mmMC_PHY_TIMING_2 0xace
854#define mmMC_SEQ_MPLL_OVERRIDE 0xa22
855#define mmMCLK_PWRMGT_CNTL 0xae8
856#define mmDLL_CNTL 0xae9
857#define mmMPLL_SEQ_UCODE_1 0xaea
858#define mmMPLL_SEQ_UCODE_2 0xaeb
859#define mmMPLL_CNTL_MODE 0xaec
860#define mmMPLL_FUNC_CNTL 0xaed
861#define mmMPLL_FUNC_CNTL_1 0xaee
862#define mmMPLL_FUNC_CNTL_2 0xaef
863#define mmMPLL_AD_FUNC_CNTL 0xaf0
864#define mmMPLL_DQ_FUNC_CNTL 0xaf1
865#define mmMPLL_TIME 0xaf2
866#define mmMPLL_SS1 0xaf3
867#define mmMPLL_SS2 0xaf4
868#define mmMPLL_CONTROL 0xaf5
869#define mmMPLL_AD_STATUS 0xaf6
870#define mmMPLL_DQ_0_0_STATUS 0xaf7
871#define mmMPLL_DQ_0_1_STATUS 0xaf8
872#define mmMPLL_DQ_1_0_STATUS 0xaf9
873#define mmMPLL_DQ_1_1_STATUS 0xafa
874#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9
875#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba
876#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb
877#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf
878#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0
879#define ixMC_TSM_DEBUG_GCNT 0x0
880#define ixMC_TSM_DEBUG_FLAG 0x1
881#define ixMC_TSM_DEBUG_MISC 0x2
882#define ixMC_TSM_DEBUG_BCNT0 0x3
883#define ixMC_TSM_DEBUG_BCNT1 0x4
884#define ixMC_TSM_DEBUG_BCNT2 0x5
885#define ixMC_TSM_DEBUG_BCNT3 0x6
886#define ixMC_TSM_DEBUG_BCNT4 0x7
887#define ixMC_TSM_DEBUG_BCNT5 0x8
888#define ixMC_TSM_DEBUG_BCNT6 0x9
889#define ixMC_TSM_DEBUG_BCNT7 0xa
890#define ixMC_TSM_DEBUG_BCNT8 0xb
891#define ixMC_TSM_DEBUG_BCNT9 0xc
892#define ixMC_TSM_DEBUG_BCNT10 0xd
893#define ixMC_TSM_DEBUG_ST01 0x10
894#define ixMC_TSM_DEBUG_ST23 0x11
895#define ixMC_TSM_DEBUG_ST45 0x12
896#define ixMC_TSM_DEBUG_BKPT 0x13
897#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91
898#define mmMC_SEQ_IO_DEBUG_DATA 0xa92
899#define ixMC_IO_DEBUG_UP_0 0x0
900#define ixMC_IO_DEBUG_UP_1 0x1
901#define ixMC_IO_DEBUG_UP_2 0x2
902#define ixMC_IO_DEBUG_UP_3 0x3
903#define ixMC_IO_DEBUG_UP_4 0x4
904#define ixMC_IO_DEBUG_UP_5 0x5
905#define ixMC_IO_DEBUG_UP_6 0x6
906#define ixMC_IO_DEBUG_UP_7 0x7
907#define ixMC_IO_DEBUG_UP_8 0x8
908#define ixMC_IO_DEBUG_UP_9 0x9
909#define ixMC_IO_DEBUG_UP_10 0xa
910#define ixMC_IO_DEBUG_UP_11 0xb
911#define ixMC_IO_DEBUG_UP_12 0xc
912#define ixMC_IO_DEBUG_UP_13 0xd
913#define ixMC_IO_DEBUG_UP_14 0xe
914#define ixMC_IO_DEBUG_UP_15 0xf
915#define ixMC_IO_DEBUG_UP_16 0x10
916#define ixMC_IO_DEBUG_UP_17 0x11
917#define ixMC_IO_DEBUG_UP_18 0x12
918#define ixMC_IO_DEBUG_UP_19 0x13
919#define ixMC_IO_DEBUG_UP_20 0x14
920#define ixMC_IO_DEBUG_UP_21 0x15
921#define ixMC_IO_DEBUG_UP_22 0x16
922#define ixMC_IO_DEBUG_UP_23 0x17
923#define ixMC_IO_DEBUG_UP_24 0x18
924#define ixMC_IO_DEBUG_UP_25 0x19
925#define ixMC_IO_DEBUG_UP_26 0x1a
926#define ixMC_IO_DEBUG_UP_27 0x1b
927#define ixMC_IO_DEBUG_UP_28 0x1c
928#define ixMC_IO_DEBUG_UP_29 0x1d
929#define ixMC_IO_DEBUG_UP_30 0x1e
930#define ixMC_IO_DEBUG_UP_31 0x1f
931#define ixMC_IO_DEBUG_UP_32 0x20
932#define ixMC_IO_DEBUG_UP_33 0x21
933#define ixMC_IO_DEBUG_UP_34 0x22
934#define ixMC_IO_DEBUG_UP_35 0x23
935#define ixMC_IO_DEBUG_UP_36 0x24
936#define ixMC_IO_DEBUG_UP_37 0x25
937#define ixMC_IO_DEBUG_UP_38 0x26
938#define ixMC_IO_DEBUG_UP_39 0x27
939#define ixMC_IO_DEBUG_UP_40 0x28
940#define ixMC_IO_DEBUG_UP_41 0x29
941#define ixMC_IO_DEBUG_UP_42 0x2a
942#define ixMC_IO_DEBUG_UP_43 0x2b
943#define ixMC_IO_DEBUG_UP_44 0x2c
944#define ixMC_IO_DEBUG_UP_45 0x2d
945#define ixMC_IO_DEBUG_UP_46 0x2e
946#define ixMC_IO_DEBUG_UP_47 0x2f
947#define ixMC_IO_DEBUG_UP_48 0x30
948#define ixMC_IO_DEBUG_UP_49 0x31
949#define ixMC_IO_DEBUG_UP_50 0x32
950#define ixMC_IO_DEBUG_UP_51 0x33
951#define ixMC_IO_DEBUG_UP_52 0x34
952#define ixMC_IO_DEBUG_UP_53 0x35
953#define ixMC_IO_DEBUG_UP_54 0x36
954#define ixMC_IO_DEBUG_UP_55 0x37
955#define ixMC_IO_DEBUG_UP_56 0x38
956#define ixMC_IO_DEBUG_UP_57 0x39
957#define ixMC_IO_DEBUG_UP_58 0x3a
958#define ixMC_IO_DEBUG_UP_59 0x3b
959#define ixMC_IO_DEBUG_UP_60 0x3c
960#define ixMC_IO_DEBUG_UP_61 0x3d
961#define ixMC_IO_DEBUG_UP_62 0x3e
962#define ixMC_IO_DEBUG_UP_63 0x3f
963#define ixMC_IO_DEBUG_UP_64 0x40
964#define ixMC_IO_DEBUG_UP_65 0x41
965#define ixMC_IO_DEBUG_UP_66 0x42
966#define ixMC_IO_DEBUG_UP_67 0x43
967#define ixMC_IO_DEBUG_UP_68 0x44
968#define ixMC_IO_DEBUG_UP_69 0x45
969#define ixMC_IO_DEBUG_UP_70 0x46
970#define ixMC_IO_DEBUG_UP_71 0x47
971#define ixMC_IO_DEBUG_UP_72 0x48
972#define ixMC_IO_DEBUG_UP_73 0x49
973#define ixMC_IO_DEBUG_UP_74 0x4a
974#define ixMC_IO_DEBUG_UP_75 0x4b
975#define ixMC_IO_DEBUG_UP_76 0x4c
976#define ixMC_IO_DEBUG_UP_77 0x4d
977#define ixMC_IO_DEBUG_UP_78 0x4e
978#define ixMC_IO_DEBUG_UP_79 0x4f
979#define ixMC_IO_DEBUG_UP_80 0x50
980#define ixMC_IO_DEBUG_UP_81 0x51
981#define ixMC_IO_DEBUG_UP_82 0x52
982#define ixMC_IO_DEBUG_UP_83 0x53
983#define ixMC_IO_DEBUG_UP_84 0x54
984#define ixMC_IO_DEBUG_UP_85 0x55
985#define ixMC_IO_DEBUG_UP_86 0x56
986#define ixMC_IO_DEBUG_UP_87 0x57
987#define ixMC_IO_DEBUG_UP_88 0x58
988#define ixMC_IO_DEBUG_UP_89 0x59
989#define ixMC_IO_DEBUG_UP_90 0x5a
990#define ixMC_IO_DEBUG_UP_91 0x5b
991#define ixMC_IO_DEBUG_UP_92 0x5c
992#define ixMC_IO_DEBUG_UP_93 0x5d
993#define ixMC_IO_DEBUG_UP_94 0x5e
994#define ixMC_IO_DEBUG_UP_95 0x5f
995#define ixMC_IO_DEBUG_UP_96 0x60
996#define ixMC_IO_DEBUG_UP_97 0x61
997#define ixMC_IO_DEBUG_UP_98 0x62
998#define ixMC_IO_DEBUG_UP_99 0x63
999#define ixMC_IO_DEBUG_UP_100 0x64
1000#define ixMC_IO_DEBUG_UP_101 0x65
1001#define ixMC_IO_DEBUG_UP_102 0x66
1002#define ixMC_IO_DEBUG_UP_103 0x67
1003#define ixMC_IO_DEBUG_UP_104 0x68
1004#define ixMC_IO_DEBUG_UP_105 0x69
1005#define ixMC_IO_DEBUG_UP_106 0x6a
1006#define ixMC_IO_DEBUG_UP_107 0x6b
1007#define ixMC_IO_DEBUG_UP_108 0x6c
1008#define ixMC_IO_DEBUG_UP_109 0x6d
1009#define ixMC_IO_DEBUG_UP_110 0x6e
1010#define ixMC_IO_DEBUG_UP_111 0x6f
1011#define ixMC_IO_DEBUG_UP_112 0x70
1012#define ixMC_IO_DEBUG_UP_113 0x71
1013#define ixMC_IO_DEBUG_UP_114 0x72
1014#define ixMC_IO_DEBUG_UP_115 0x73
1015#define ixMC_IO_DEBUG_UP_116 0x74
1016#define ixMC_IO_DEBUG_UP_117 0x75
1017#define ixMC_IO_DEBUG_UP_118 0x76
1018#define ixMC_IO_DEBUG_UP_119 0x77
1019#define ixMC_IO_DEBUG_UP_120 0x78
1020#define ixMC_IO_DEBUG_UP_121 0x79
1021#define ixMC_IO_DEBUG_UP_122 0x7a
1022#define ixMC_IO_DEBUG_UP_123 0x7b
1023#define ixMC_IO_DEBUG_UP_124 0x7c
1024#define ixMC_IO_DEBUG_UP_125 0x7d
1025#define ixMC_IO_DEBUG_UP_126 0x7e
1026#define ixMC_IO_DEBUG_UP_127 0x7f
1027#define ixMC_IO_DEBUG_UP_128 0x80
1028#define ixMC_IO_DEBUG_UP_129 0x81
1029#define ixMC_IO_DEBUG_UP_130 0x82
1030#define ixMC_IO_DEBUG_UP_131 0x83
1031#define ixMC_IO_DEBUG_UP_132 0x84
1032#define ixMC_IO_DEBUG_UP_133 0x85
1033#define ixMC_IO_DEBUG_UP_134 0x86
1034#define ixMC_IO_DEBUG_UP_135 0x87
1035#define ixMC_IO_DEBUG_UP_136 0x88
1036#define ixMC_IO_DEBUG_UP_137 0x89
1037#define ixMC_IO_DEBUG_UP_138 0x8a
1038#define ixMC_IO_DEBUG_UP_139 0x8b
1039#define ixMC_IO_DEBUG_UP_140 0x8c
1040#define ixMC_IO_DEBUG_UP_141 0x8d
1041#define ixMC_IO_DEBUG_UP_142 0x8e
1042#define ixMC_IO_DEBUG_UP_143 0x8f
1043#define ixMC_IO_DEBUG_UP_144 0x90
1044#define ixMC_IO_DEBUG_UP_145 0x91
1045#define ixMC_IO_DEBUG_UP_146 0x92
1046#define ixMC_IO_DEBUG_UP_147 0x93
1047#define ixMC_IO_DEBUG_UP_148 0x94
1048#define ixMC_IO_DEBUG_UP_149 0x95
1049#define ixMC_IO_DEBUG_UP_150 0x96
1050#define ixMC_IO_DEBUG_UP_151 0x97
1051#define ixMC_IO_DEBUG_UP_152 0x98
1052#define ixMC_IO_DEBUG_UP_153 0x99
1053#define ixMC_IO_DEBUG_UP_154 0x9a
1054#define ixMC_IO_DEBUG_UP_155 0x9b
1055#define ixMC_IO_DEBUG_UP_156 0x9c
1056#define ixMC_IO_DEBUG_UP_157 0x9d
1057#define ixMC_IO_DEBUG_UP_158 0x9e
1058#define ixMC_IO_DEBUG_UP_159 0x9f
1059#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0
1060#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1
1061#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2
1062#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3
1063#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4
1064#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5
1065#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6
1066#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7
1067#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8
1068#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9
1069#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa
1070#define ixMC_IO_DEBUG_CK_MISC_D0 0xab
1071#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac
1072#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad
1073#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae
1074#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf
1075#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0
1076#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1
1077#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2
1078#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3
1079#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4
1080#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5
1081#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6
1082#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7
1083#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8
1084#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9
1085#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba
1086#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb
1087#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc
1088#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd
1089#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe
1090#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf
1091#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0
1092#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1
1093#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2
1094#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3
1095#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4
1096#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5
1097#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6
1098#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7
1099#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8
1100#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9
1101#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca
1102#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb
1103#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc
1104#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd
1105#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce
1106#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf
1107#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0
1108#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1
1109#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2
1110#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3
1111#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4
1112#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5
1113#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6
1114#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7
1115#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8
1116#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9
1117#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda
1118#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb
1119#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc
1120#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd
1121#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde
1122#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf
1123#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0
1124#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1
1125#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2
1126#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3
1127#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4
1128#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5
1129#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6
1130#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7
1131#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8
1132#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9
1133#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea
1134#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb
1135#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec
1136#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed
1137#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee
1138#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef
1139#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0
1140#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1
1141#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2
1142#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3
1143#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4
1144#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5
1145#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6
1146#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7
1147#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8
1148#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9
1149#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa
1150#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb
1151#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc
1152#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd
1153#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe
1154#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff
1155#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100
1156#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101
1157#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102
1158#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103
1159#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104
1160#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
1161#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106
1162#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107
1163#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108
1164#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109
1165#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a
1166#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b
1167#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c
1168#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d
1169#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e
1170#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f
1171#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110
1172#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
1173#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
1174#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113
1175#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114
1176#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
1177#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116
1178#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
1179#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118
1180#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119
1181#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a
1182#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b
1183#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c
1184#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d
1185#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e
1186#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f
1187#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120
1188#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121
1189#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
1190#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123
1191#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124
1192#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
1193#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
1194#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127
1195#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128
1196#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129
1197#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a
1198#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b
1199#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c
1200#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d
1201#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e
1202#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f
1203#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130
1204#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
1205#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
1206#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
1207#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134
1208#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
1209#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
1210#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137
1211#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138
1212#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139
1213#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a
1214#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b
1215#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c
1216#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d
1217#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e
1218#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f
1219#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140
1220#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
1221#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142
1222#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143
1223#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144
1224#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
1225#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146
1226#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147
1227#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148
1228#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149
1229#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a
1230#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b
1231#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c
1232#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d
1233#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e
1234#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f
1235#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150
1236#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151
1237#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152
1238#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153
1239#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154
1240#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155
1241#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156
1242#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157
1243#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158
1244#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159
1245#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a
1246#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b
1247#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c
1248#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d
1249#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e
1250#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f
1251#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160
1252#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161
1253#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162
1254#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163
1255#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164
1256#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165
1257#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166
1258#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167
1259#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168
1260#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169
1261#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a
1262#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b
1263#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c
1264#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d
1265#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e
1266#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f
1267#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170
1268#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171
1269#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172
1270#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173
1271#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174
1272#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175
1273#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176
1274#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177
1275#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178
1276#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179
1277#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a
1278#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b
1279#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c
1280#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d
1281#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e
1282#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f
1283#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180
1284#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181
1285#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182
1286#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183
1287#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184
1288#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185
1289#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186
1290#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187
1291#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188
1292#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189
1293#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a
1294#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b
1295#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c
1296#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d
1297#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e
1298#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f
1299#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190
1300#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191
1301#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192
1302#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193
1303#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194
1304#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195
1305#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196
1306#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197
1307#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198
1308#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199
1309#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a
1310#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b
1311#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c
1312#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d
1313#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e
1314#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f
1315#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0
1316#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1
1317#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2
1318#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3
1319#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4
1320#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5
1321#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6
1322#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7
1323#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8
1324#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9
1325#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa
1326#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab
1327#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac
1328#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad
1329#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae
1330#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af
1331#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0
1332#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1
1333#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2
1334#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3
1335#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4
1336#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5
1337#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6
1338#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7
1339#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8
1340#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9
1341#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba
1342#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb
1343#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc
1344#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd
1345#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be
1346#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf
1347#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0
1348#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1
1349#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2
1350#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3
1351#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4
1352#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5
1353#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6
1354#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7
1355#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8
1356#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9
1357#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca
1358#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb
1359#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc
1360#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd
1361#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce
1362#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf
1363#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0
1364#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1
1365#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2
1366#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3
1367#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4
1368#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5
1369#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6
1370#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7
1371#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8
1372#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9
1373#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da
1374#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db
1375#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc
1376#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd
1377#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de
1378#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df
1379#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0
1380#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1
1381#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2
1382#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3
1383#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4
1384#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5
1385#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6
1386#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7
1387#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8
1388#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9
1389#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea
1390#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb
1391#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec
1392#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0
1393#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1
1394#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2
1395#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3
1396#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4
1397#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5
1398#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6
1399#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7
1400#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8
1401#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9
1402#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa
1403#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb
1404#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc
1405#define mmMC_SEQ_CNTL_3 0xd80
1406#define mmMC_SEQ_G5PDX_CTRL 0xd81
1407#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82
1408#define mmMC_SEQ_G5PDX_CMD0 0xd83
1409#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84
1410#define mmMC_SEQ_G5PDX_CMD1 0xd85
1411#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86
1412#define mmMC_SEQ_SREG_READ 0xd87
1413#define mmMC_SEQ_SREG_STATUS 0xd88
1414#define mmMC_SEQ_PHYREG_BCAST 0xd89
1415#define mmMC_SEQ_PMG_DVS_CTL 0xd8a
1416#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b
1417#define mmMC_SEQ_PMG_DVS_CMD 0xd8c
1418#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d
1419#define mmMC_SEQ_DLL_STBY 0xd8e
1420#define mmMC_SEQ_DLL_STBY_LP 0xd8f
1421#define mmMC_DLB_MISCCTRL0 0xd90
1422#define mmMC_DLB_MISCCTRL1 0xd91
1423#define mmMC_DLB_MISCCTRL2 0xd92
1424#define mmMC_DLB_CONFIG0 0xd93
1425#define mmMC_DLB_CONFIG1 0xd94
1426#define mmMC_DLB_SETUP 0xd95
1427#define mmMC_DLB_SETUPSWEEP 0xd96
1428#define mmMC_DLB_SETUPFIFO 0xd97
1429#define mmMC_DLB_WRITE_MASK 0xd98
1430#define mmMC_DLB_STATUS 0xd99
1431#define mmMC_DLB_STATUS_MISC0 0xd9a
1432#define mmMC_DLB_STATUS_MISC1 0xd9b
1433#define mmMC_DLB_STATUS_MISC2 0xd9c
1434#define mmMC_DLB_STATUS_MISC3 0xd9d
1435#define mmMC_DLB_STATUS_MISC4 0xd9e
1436#define mmMC_DLB_STATUS_MISC5 0xd9f
1437#define mmMC_DLB_STATUS_MISC6 0xda0
1438#define mmMC_DLB_STATUS_MISC7 0xda1
1439#define mmMC_ARB_HARSH_EN_RD 0xdc0
1440#define mmMC_ARB_HARSH_EN_WR 0xdc1
1441#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
1442#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
1443#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
1444#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
1445#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
1446#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
1447#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
1448#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
1449#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
1450#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
1451#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
1452#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
1453#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
1454#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
1455#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
1456#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
1457#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
1458#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
1459#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
1460#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
1461#define mmMC_ARB_HARSH_CTL_RD 0xdd6
1462#define mmMC_ARB_HARSH_CTL_WR 0xdd7
1463
1464#endif /* GMC_7_1_D_H */
1465