1/*
2 * GMC_7_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GMC_7_1_SH_MASK_H
25#define GMC_7_1_SH_MASK_H
26
27#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
37#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
38#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
39#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
40#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
41#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
42#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
43#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
44#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
45#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
46#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
47#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
48#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
49#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
50#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
51#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
52#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
53#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
54#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
55#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
56#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
57#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
58#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
59#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
60#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
61#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
62#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
63#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
64#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
65#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
66#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
67#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
68#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
69#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
70#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
71#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
72#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
73#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
74#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
75#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
76#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
77#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
78#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
79#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
80#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
81#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
82#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
83#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
84#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
85#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
86#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
87#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
88#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
89#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
90#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
91#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
92#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
93#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
94#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
95#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
96#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
97#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
98#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
99#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
100#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
101#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
102#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
103#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
104#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
105#define MC_ARB_FED_CNTL__MODE_MASK 0x3
106#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
107#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
108#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
109#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
110#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
111#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
112#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
113#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
114#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
115#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
116#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
117#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
118#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
119#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
120#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
121#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
122#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
123#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
124#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
125#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
126#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
127#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
128#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
129#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
130#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
131#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
132#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
133#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
134#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
135#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
136#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
137#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
138#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
139#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
140#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
141#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
142#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
143#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
144#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
145#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
146#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
147#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
148#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
149#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
150#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
151#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
152#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
153#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
154#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
155#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
156#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
157#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
158#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
159#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
160#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
161#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
162#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
163#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
164#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
165#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
166#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
167#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
168#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
169#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
170#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
171#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
172#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
173#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
174#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
175#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
176#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
177#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
178#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
179#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
180#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
181#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
182#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
183#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
184#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
185#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
186#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
187#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
188#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
189#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
190#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
191#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
192#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
193#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
194#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
195#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
196#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
197#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
198#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
199#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
200#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
201#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
202#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
203#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
204#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
205#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
206#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
207#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
208#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
209#define MC_ARB_PERF_CID__CH0_MASK 0xff
210#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
211#define MC_ARB_PERF_CID__CH1_MASK 0xff00
212#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
213#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
214#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
215#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
216#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
217#define MC_ARB_GECC2__ENABLE_MASK 0x1
218#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
219#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
220#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
221#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
222#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
223#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
224#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
225#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
226#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
227#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
228#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
229#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
230#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
231#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
232#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
233#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
234#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
235#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
236#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
237#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
238#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
239#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
240#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
241#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
242#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
243#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
244#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
245#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
246#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
247#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
248#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
249#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
250#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
251#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
252#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
253#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
254#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
255#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
256#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
257#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
258#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
259#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
260#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
261#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
262#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
263#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
264#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
265#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
266#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
267#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
268#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
269#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
270#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
271#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
272#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
273#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
274#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
275#define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8
276#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3
277#define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
278#define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
279#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
280#define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
281#define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
282#define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
283#define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
284#define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
285#define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
286#define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
287#define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
288#define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
289#define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
290#define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
291#define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
292#define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
293#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
294#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
295#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
296#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
297#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
298#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
299#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
300#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
301#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
302#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
303#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
304#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
305#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
306#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
307#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
308#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
309#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
310#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
311#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
312#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
313#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
314#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
315#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
316#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
317#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
318#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
319#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
320#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
321#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
322#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
323#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
324#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
325#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
326#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
327#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
328#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
329#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
330#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
331#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
332#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
333#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
334#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
335#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
336#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
337#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
338#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
339#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
340#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
341#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
342#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
343#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
344#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
345#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
346#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
347#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
348#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
349#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
350#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
351#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
352#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
353#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
354#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
355#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
356#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
357#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
358#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
359#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
360#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
361#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
362#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
363#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
364#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
365#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
366#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
367#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
368#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
369#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
370#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
371#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
372#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
373#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
374#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
375#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
376#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
377#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
378#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
379#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
380#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
381#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
382#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
383#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
384#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
385#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
386#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
387#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
388#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
389#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
390#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
391#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
392#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
393#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
394#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
395#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
396#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
397#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
398#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
399#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
400#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
401#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
402#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
403#define MC_ARB_MISC2__GECC_MASK 0x40000
404#define MC_ARB_MISC2__GECC__SHIFT 0x12
405#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
406#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
407#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
408#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
409#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
410#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
411#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
412#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
413#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
414#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
415#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
416#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
417#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
418#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
419#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
420#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
421#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
422#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
423#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
424#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
425#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
426#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
427#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
428#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
429#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
430#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
431#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
432#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
433#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
434#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
435#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
436#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
437#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
438#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
439#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
440#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
441#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
442#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
443#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
444#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
445#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
446#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
447#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
448#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
449#define MC_ARB_BANKMAP__BANK0_MASK 0xf
450#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
451#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
452#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
453#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
454#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
455#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
456#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
457#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
458#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
459#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
460#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
461#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
462#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
463#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
464#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
465#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
466#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
467#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
468#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
469#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
470#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
471#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
472#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
473#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
474#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
475#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
476#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
477#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
478#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
479#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
480#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
481#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
482#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
483#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
484#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
485#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
486#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
487#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
488#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
489#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
490#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
491#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
492#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
493#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
494#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
495#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
496#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
497#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
498#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
499#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
500#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
501#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
502#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
503#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
504#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
505#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
506#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
507#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
508#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
509#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
510#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
511#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
512#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
513#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
514#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
515#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
516#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
517#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
518#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
519#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
520#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
521#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
522#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
523#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
524#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
525#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
526#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
527#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
528#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
529#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
530#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
531#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
532#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
533#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
534#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
535#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
536#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
537#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
538#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
539#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
540#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
541#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
542#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
543#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
544#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
545#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
546#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
547#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
548#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
549#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
550#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
551#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
552#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
553#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
554#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
555#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
556#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
557#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
558#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
559#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
560#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
561#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
562#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
563#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
564#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
565#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
566#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
567#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
568#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
569#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
570#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
571#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
572#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
573#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
574#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
575#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
576#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
577#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
578#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
579#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
580#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
581#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
582#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
583#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
584#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
585#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
586#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
587#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
588#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
589#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
590#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
591#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
592#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
593#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
594#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
595#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
596#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
597#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
598#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
599#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
600#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
601#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
602#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
603#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
604#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
605#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
606#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
607#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
608#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
609#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
610#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
611#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
612#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
613#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
614#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
615#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
616#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
617#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
618#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
619#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
620#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
621#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
622#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
623#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
624#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
625#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
626#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
627#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
628#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
629#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
630#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
631#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
632#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
633#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
634#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
635#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
636#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
637#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
638#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
639#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
640#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
641#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
642#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
643#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
644#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
645#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
646#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
647#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
648#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
649#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
650#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
651#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
652#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
653#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
654#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
655#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
656#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
657#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
658#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
659#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
660#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
661#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
662#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
663#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
664#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
665#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
666#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
667#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
668#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
669#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
670#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
671#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
672#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
673#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
674#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
675#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
676#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
677#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
678#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
679#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
680#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
681#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
682#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
683#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
684#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
685#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
686#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
687#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
688#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
689#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
690#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
691#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
692#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
693#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
694#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
695#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
696#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
697#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
698#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
699#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
700#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
701#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
702#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
703#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
704#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
705#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
706#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
707#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
708#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
709#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
710#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
711#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
712#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
713#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
714#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
715#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
716#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
717#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
718#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
719#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
720#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
721#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
722#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
723#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
724#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
725#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
726#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
727#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
728#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
729#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
730#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
731#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
732#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
733#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
734#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
735#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
736#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
737#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
738#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
739#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
740#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
741#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
742#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
743#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
744#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
745#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
746#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
747#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
748#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
749#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
750#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
751#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
752#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
753#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
754#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
755#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
756#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
757#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
758#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
759#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
760#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
761#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
762#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
763#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
764#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
765#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
766#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
767#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
768#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
769#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
770#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
771#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
772#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
773#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
774#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
775#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
776#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
777#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
778#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
779#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
780#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
781#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
782#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
783#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
784#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
785#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
786#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
787#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
788#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
789#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
790#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
791#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
792#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
793#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
794#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
795#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
796#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
797#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
798#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
799#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
800#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
801#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
802#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
803#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
804#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
805#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
806#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
807#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
808#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
809#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
810#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
811#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
812#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
813#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
814#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
815#define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
816#define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
817#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
818#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
819#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
820#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
821#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
822#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
823#define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
824#define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
825#define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
826#define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
827#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
828#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
829#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
830#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
831#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
832#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
833#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
834#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
835#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
836#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
837#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
838#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
839#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
840#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
841#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
842#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
843#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
844#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
845#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
846#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
847#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
848#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
849#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
850#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
851#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
852#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
853#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
854#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
855#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
856#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
857#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
858#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
859#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
860#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
861#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
862#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
863#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
864#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
865#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
866#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
867#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
868#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
869#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
870#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
871#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
872#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
873#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
874#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
875#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
876#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
877#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
878#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
879#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
880#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
881#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
882#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
883#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
884#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
885#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
886#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
887#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
888#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
889#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
890#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
891#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
892#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
893#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
894#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
895#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
896#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
897#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
898#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
899#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
900#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
901#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
902#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
903#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
904#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
905#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
906#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
907#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
908#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
909#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
910#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
911#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
912#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
913#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
914#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
915#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
916#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
917#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
918#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
919#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
920#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
921#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
922#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
923#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
924#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
925#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
926#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
927#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
928#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
929#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
930#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
931#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
932#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
933#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
934#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
935#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
936#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
937#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
938#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
939#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
940#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
941#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
942#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
943#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
944#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
945#define MC_ARB_SSM__FORMAT_MASK 0x1f
946#define MC_ARB_SSM__FORMAT__SHIFT 0x0
947#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
948#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
949#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
950#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
951#define MC_ARB_CG__RSV_0_MASK 0xff0000
952#define MC_ARB_CG__RSV_0__SHIFT 0x10
953#define MC_ARB_CG__RSV_1_MASK 0xff000000
954#define MC_ARB_CG__RSV_1__SHIFT 0x18
955#define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
956#define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
957#define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
958#define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
959#define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
960#define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
961#define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
962#define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
963#define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
964#define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
965#define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
966#define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
967#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
968#define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
969#define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
970#define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
971#define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
972#define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
973#define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
974#define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
975#define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
976#define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
977#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
978#define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
979#define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
980#define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
981#define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
982#define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
983#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
984#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
985#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
986#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
987#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
988#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
989#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
990#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
991#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
992#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
993#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
994#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
995#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
996#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
997#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
998#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
999#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
1000#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
1001#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
1002#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
1003#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
1004#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
1005#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
1006#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
1007#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
1008#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
1009#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
1010#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
1011#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
1012#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
1013#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
1014#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
1015#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
1016#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
1017#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
1018#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
1019#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
1020#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
1021#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
1022#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
1023#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
1024#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
1025#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
1026#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
1027#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
1028#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
1029#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
1030#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
1031#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
1032#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
1033#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
1034#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
1035#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
1036#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
1037#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
1038#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
1039#define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
1040#define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
1041#define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
1042#define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
1043#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
1044#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
1045#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
1046#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
1047#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
1048#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
1049#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
1050#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1051#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
1052#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
1053#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
1054#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
1055#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
1056#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
1057#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
1058#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
1059#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
1060#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
1061#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
1062#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
1063#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
1064#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
1065#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
1066#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
1067#define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
1068#define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
1069#define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
1070#define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
1071#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
1072#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
1073#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
1074#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
1075#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
1076#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
1077#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
1078#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
1079#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
1080#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
1081#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
1082#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
1083#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
1084#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
1085#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
1086#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
1087#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
1088#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
1089#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
1090#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
1091#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
1092#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
1093#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
1094#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
1095#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
1096#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
1097#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
1098#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
1099#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
1100#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
1101#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
1102#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
1103#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
1104#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
1105#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
1106#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
1107#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
1108#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
1109#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
1110#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
1111#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
1112#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
1113#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
1114#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
1115#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
1116#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
1117#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
1118#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
1119#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
1120#define MC_CG_CONFIG__INDEX__SHIFT 0x6
1121#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
1122#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
1123#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
1124#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
1125#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
1126#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
1127#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
1128#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
1129#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
1130#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
1131#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
1132#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
1133#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
1134#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
1135#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
1136#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
1137#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
1138#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
1139#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
1140#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
1141#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
1142#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
1143#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
1144#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
1145#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
1146#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
1147#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
1148#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
1149#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
1150#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
1151#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
1152#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
1153#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
1154#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
1155#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
1156#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
1157#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
1158#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
1159#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
1160#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
1161#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
1162#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
1163#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
1164#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
1165#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
1166#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
1167#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
1168#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
1169#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
1170#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
1171#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
1172#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
1173#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
1174#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
1175#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
1176#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
1177#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
1178#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
1179#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
1180#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
1181#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
1182#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
1183#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
1184#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
1185#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
1186#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
1187#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
1188#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
1189#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
1190#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
1191#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
1192#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
1193#define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
1194#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
1195#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
1196#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
1197#define MC_RD_GRP_EXT__TC0_MASK 0xf0
1198#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
1199#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
1200#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
1201#define MC_WR_GRP_EXT__TC0_MASK 0xf0
1202#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
1203#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
1204#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
1205#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
1206#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
1207#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
1208#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
1209#define MC_WR_TC0__ENABLE_MASK 0x1
1210#define MC_WR_TC0__ENABLE__SHIFT 0x0
1211#define MC_WR_TC0__PRESCALE_MASK 0x6
1212#define MC_WR_TC0__PRESCALE__SHIFT 0x1
1213#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
1214#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1215#define MC_WR_TC0__STALL_MODE_MASK 0x30
1216#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
1217#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
1218#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
1219#define MC_WR_TC0__MAX_BURST_MASK 0x780
1220#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
1221#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
1222#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
1223#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1224#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1225#define MC_WR_TC1__ENABLE_MASK 0x1
1226#define MC_WR_TC1__ENABLE__SHIFT 0x0
1227#define MC_WR_TC1__PRESCALE_MASK 0x6
1228#define MC_WR_TC1__PRESCALE__SHIFT 0x1
1229#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
1230#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1231#define MC_WR_TC1__STALL_MODE_MASK 0x30
1232#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
1233#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
1234#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
1235#define MC_WR_TC1__MAX_BURST_MASK 0x780
1236#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
1237#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
1238#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
1239#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1240#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1241#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
1242#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
1243#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
1244#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
1245#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
1246#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1247#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
1248#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1249#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1250#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1251#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
1252#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1253#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
1254#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1255#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
1256#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1257#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1258#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1259#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1260#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1261#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
1262#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
1263#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
1264#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
1265#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
1266#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1267#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
1268#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1269#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1270#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1271#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
1272#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1273#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
1274#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1275#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
1276#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1277#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1278#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1279#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1280#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1281#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
1282#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
1283#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
1284#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
1285#define MC_RD_CB__ENABLE_MASK 0x1
1286#define MC_RD_CB__ENABLE__SHIFT 0x0
1287#define MC_RD_CB__PRESCALE_MASK 0x6
1288#define MC_RD_CB__PRESCALE__SHIFT 0x1
1289#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
1290#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1291#define MC_RD_CB__STALL_MODE_MASK 0x30
1292#define MC_RD_CB__STALL_MODE__SHIFT 0x4
1293#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
1294#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
1295#define MC_RD_CB__MAX_BURST_MASK 0x780
1296#define MC_RD_CB__MAX_BURST__SHIFT 0x7
1297#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
1298#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
1299#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1300#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1301#define MC_RD_DB__ENABLE_MASK 0x1
1302#define MC_RD_DB__ENABLE__SHIFT 0x0
1303#define MC_RD_DB__PRESCALE_MASK 0x6
1304#define MC_RD_DB__PRESCALE__SHIFT 0x1
1305#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
1306#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1307#define MC_RD_DB__STALL_MODE_MASK 0x30
1308#define MC_RD_DB__STALL_MODE__SHIFT 0x4
1309#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
1310#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
1311#define MC_RD_DB__MAX_BURST_MASK 0x780
1312#define MC_RD_DB__MAX_BURST__SHIFT 0x7
1313#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
1314#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
1315#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1316#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1317#define MC_RD_TC0__ENABLE_MASK 0x1
1318#define MC_RD_TC0__ENABLE__SHIFT 0x0
1319#define MC_RD_TC0__PRESCALE_MASK 0x6
1320#define MC_RD_TC0__PRESCALE__SHIFT 0x1
1321#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
1322#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1323#define MC_RD_TC0__STALL_MODE_MASK 0x30
1324#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
1325#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
1326#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
1327#define MC_RD_TC0__MAX_BURST_MASK 0x780
1328#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
1329#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
1330#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
1331#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1332#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1333#define MC_RD_TC1__ENABLE_MASK 0x1
1334#define MC_RD_TC1__ENABLE__SHIFT 0x0
1335#define MC_RD_TC1__PRESCALE_MASK 0x6
1336#define MC_RD_TC1__PRESCALE__SHIFT 0x1
1337#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
1338#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1339#define MC_RD_TC1__STALL_MODE_MASK 0x30
1340#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
1341#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
1342#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
1343#define MC_RD_TC1__MAX_BURST_MASK 0x780
1344#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
1345#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
1346#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
1347#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1348#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1349#define MC_RD_HUB__ENABLE_MASK 0x1
1350#define MC_RD_HUB__ENABLE__SHIFT 0x0
1351#define MC_RD_HUB__PRESCALE_MASK 0x6
1352#define MC_RD_HUB__PRESCALE__SHIFT 0x1
1353#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
1354#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1355#define MC_RD_HUB__STALL_MODE_MASK 0x30
1356#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
1357#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
1358#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
1359#define MC_RD_HUB__MAX_BURST_MASK 0x780
1360#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
1361#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
1362#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
1363#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1364#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1365#define MC_WR_CB__ENABLE_MASK 0x1
1366#define MC_WR_CB__ENABLE__SHIFT 0x0
1367#define MC_WR_CB__PRESCALE_MASK 0x6
1368#define MC_WR_CB__PRESCALE__SHIFT 0x1
1369#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
1370#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1371#define MC_WR_CB__STALL_MODE_MASK 0x30
1372#define MC_WR_CB__STALL_MODE__SHIFT 0x4
1373#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
1374#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
1375#define MC_WR_CB__MAX_BURST_MASK 0x780
1376#define MC_WR_CB__MAX_BURST__SHIFT 0x7
1377#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
1378#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
1379#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1380#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1381#define MC_WR_DB__ENABLE_MASK 0x1
1382#define MC_WR_DB__ENABLE__SHIFT 0x0
1383#define MC_WR_DB__PRESCALE_MASK 0x6
1384#define MC_WR_DB__PRESCALE__SHIFT 0x1
1385#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
1386#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1387#define MC_WR_DB__STALL_MODE_MASK 0x30
1388#define MC_WR_DB__STALL_MODE__SHIFT 0x4
1389#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
1390#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
1391#define MC_WR_DB__MAX_BURST_MASK 0x780
1392#define MC_WR_DB__MAX_BURST__SHIFT 0x7
1393#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
1394#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
1395#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1396#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1397#define MC_WR_HUB__ENABLE_MASK 0x1
1398#define MC_WR_HUB__ENABLE__SHIFT 0x0
1399#define MC_WR_HUB__PRESCALE_MASK 0x6
1400#define MC_WR_HUB__PRESCALE__SHIFT 0x1
1401#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
1402#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1403#define MC_WR_HUB__STALL_MODE_MASK 0x30
1404#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
1405#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
1406#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
1407#define MC_WR_HUB__MAX_BURST_MASK 0x780
1408#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
1409#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
1410#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
1411#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1412#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1413#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
1414#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
1415#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
1416#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
1417#define MC_RD_GRP_LCL__CB0_MASK 0xf000
1418#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
1419#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
1420#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
1421#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
1422#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
1423#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
1424#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
1425#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
1426#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
1427#define MC_WR_GRP_LCL__CB0_MASK 0xf
1428#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
1429#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
1430#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
1431#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
1432#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
1433#define MC_WR_GRP_LCL__DB0_MASK 0xf000
1434#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
1435#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
1436#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
1437#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
1438#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
1439#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
1440#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
1441#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
1442#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
1443#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
1444#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
1445#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
1446#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
1447#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
1448#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
1449#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
1450#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
1451#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
1452#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
1453#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
1454#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
1455#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
1456#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
1457#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
1458#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
1459#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
1460#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
1461#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
1462#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
1463#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
1464#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
1465#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
1466#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
1467#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
1468#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
1469#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
1470#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
1471#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
1472#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
1473#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
1474#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
1475#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
1476#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
1477#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
1478#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
1479#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
1480#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
1481#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
1482#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
1483#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
1484#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
1485#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
1486#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
1487#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
1488#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
1489#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
1490#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
1491#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
1492#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
1493#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
1494#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
1495#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
1496#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
1497#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1498#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1499#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
1500#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
1501#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
1502#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
1503#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
1504#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
1505#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
1506#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
1507#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
1508#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
1509#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
1510#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
1511#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
1512#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
1513#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
1514#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
1515#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
1516#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
1517#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
1518#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
1519#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
1520#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
1521#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1522#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1523#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
1524#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
1525#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
1526#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
1527#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
1528#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
1529#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
1530#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
1531#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
1532#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
1533#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
1534#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
1535#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
1536#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
1537#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
1538#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
1539#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
1540#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
1541#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
1542#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
1543#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
1544#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
1545#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
1546#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
1547#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
1548#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
1549#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
1550#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
1551#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
1552#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
1553#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
1554#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
1555#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
1556#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
1557#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
1558#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
1559#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
1560#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
1561#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
1562#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
1563#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
1564#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
1565#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
1566#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
1567#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
1568#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
1569#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
1570#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
1571#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1572#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1573#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
1574#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
1575#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
1576#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
1577#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
1578#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
1579#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
1580#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
1581#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
1582#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
1583#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
1584#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
1585#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
1586#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
1587#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
1588#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
1589#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
1590#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
1591#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
1592#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
1593#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
1594#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
1595#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
1596#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
1597#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
1598#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
1599#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
1600#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
1601#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
1602#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
1603#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
1604#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
1605#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
1606#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
1607#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
1608#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1609#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
1610#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1611#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
1612#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1613#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1614#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1615#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
1616#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1617#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
1618#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1619#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
1620#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1621#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
1622#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1623#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
1624#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
1625#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
1626#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
1627#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
1628#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
1629#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
1630#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
1631#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
1632#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
1633#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
1634#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
1635#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
1636#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
1637#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
1638#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
1639#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
1640#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
1641#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
1642#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
1643#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
1644#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
1645#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
1646#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
1647#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
1648#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
1649#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
1650#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
1651#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
1652#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
1653#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
1654#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1655#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
1656#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1657#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
1658#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1659#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1660#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1661#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
1662#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1663#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
1664#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1665#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
1666#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1667#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
1668#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1669#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
1670#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
1671#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
1672#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
1673#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
1674#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
1675#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
1676#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
1677#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
1678#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
1679#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
1680#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
1681#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
1682#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
1683#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
1684#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
1685#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
1686#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
1687#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
1688#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
1689#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
1690#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
1691#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
1692#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
1693#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
1694#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
1695#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
1696#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
1697#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
1698#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
1699#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
1700#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
1701#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
1702#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
1703#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
1704#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
1705#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1706#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1707#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
1708#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
1709#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
1710#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
1711#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
1712#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
1713#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
1714#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
1715#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
1716#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
1717#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
1718#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
1719#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
1720#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
1721#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
1722#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
1723#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
1724#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
1725#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
1726#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
1727#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
1728#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
1729#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
1730#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
1731#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
1732#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
1733#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
1734#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
1735#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
1736#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
1737#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
1738#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
1739#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
1740#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
1741#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
1742#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
1743#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
1744#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
1745#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
1746#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
1747#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
1748#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
1749#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1750#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1751#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1752#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1753#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1754#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1755#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1756#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1757#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1758#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1759#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1760#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1761#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1762#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1763#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1764#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1765#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1766#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1767#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1768#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1769#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1770#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1771#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1772#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1773#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1774#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1775#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1776#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1777#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1778#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1779#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1780#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1781#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
1782#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
1783#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
1784#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
1785#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
1786#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
1787#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
1788#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
1789#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
1790#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
1791#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
1792#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
1793#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
1794#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
1795#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
1796#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
1797#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
1798#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
1799#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
1800#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
1801#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
1802#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
1803#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
1804#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
1805#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
1806#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
1807#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
1808#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
1809#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
1810#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
1811#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
1812#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
1813#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
1814#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
1815#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
1816#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
1817#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
1818#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
1819#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
1820#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
1821#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
1822#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
1823#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
1824#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
1825#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
1826#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
1827#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
1828#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
1829#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
1830#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
1831#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
1832#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
1833#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
1834#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
1835#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
1836#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
1837#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
1838#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
1839#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
1840#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
1841#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
1842#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
1843#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
1844#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
1845#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
1846#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
1847#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
1848#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
1849#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
1850#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
1851#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
1852#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
1853#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
1854#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
1855#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
1856#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
1857#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
1858#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
1859#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
1860#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
1861#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
1862#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
1863#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
1864#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
1865#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
1866#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
1867#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
1868#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
1869#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
1870#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
1871#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
1872#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
1873#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
1874#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
1875#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
1876#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
1877#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
1878#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
1879#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
1880#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
1881#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
1882#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
1883#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
1884#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
1885#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
1886#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
1887#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
1888#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
1889#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
1890#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
1891#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x40000000
1892#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e
1893#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x80000000
1894#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f
1895#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
1896#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
1897#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
1898#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
1899#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
1900#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
1901#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
1902#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
1903#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
1904#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
1905#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
1906#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
1907#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
1908#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
1909#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
1910#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
1911#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
1912#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
1913#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
1914#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
1915#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
1916#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
1917#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
1918#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
1919#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
1920#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
1921#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
1922#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
1923#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
1924#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
1925#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
1926#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
1927#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
1928#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
1929#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
1930#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
1931#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
1932#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
1933#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
1934#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
1935#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
1936#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
1937#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
1938#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
1939#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
1940#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
1941#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
1942#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
1943#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
1944#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
1945#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1946#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1947#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
1948#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
1949#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
1950#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
1951#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
1952#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
1953#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
1954#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
1955#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
1956#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
1957#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
1958#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
1959#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
1960#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
1961#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
1962#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
1963#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1964#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1965#define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
1966#define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
1967#define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
1968#define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
1969#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
1970#define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
1971#define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
1972#define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
1973#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
1974#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
1975#define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
1976#define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
1977#define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
1978#define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
1979#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
1980#define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
1981#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1982#define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1983#define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
1984#define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
1985#define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
1986#define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
1987#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
1988#define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
1989#define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
1990#define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
1991#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
1992#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
1993#define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
1994#define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
1995#define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
1996#define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
1997#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
1998#define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
1999#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2000#define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2001#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
2002#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
2003#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2004#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2005#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
2006#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
2007#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
2008#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
2009#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
2010#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
2011#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
2012#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
2013#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
2014#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
2015#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
2016#define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
2017#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
2018#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
2019#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2020#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2021#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
2022#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
2023#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
2024#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
2025#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
2026#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
2027#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
2028#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
2029#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
2030#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
2031#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
2032#define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
2033#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
2034#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
2035#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2036#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2037#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
2038#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
2039#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
2040#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
2041#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
2042#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
2043#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
2044#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
2045#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
2046#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
2047#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
2048#define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
2049#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
2050#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
2051#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2052#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2053#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
2054#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
2055#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
2056#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
2057#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
2058#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
2059#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
2060#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
2061#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
2062#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
2063#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
2064#define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
2065#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
2066#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
2067#define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
2068#define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
2069#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
2070#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
2071#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
2072#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
2073#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
2074#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
2075#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
2076#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
2077#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
2078#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
2079#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
2080#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
2081#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
2082#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
2083#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
2084#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2085#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
2086#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
2087#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
2088#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
2089#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
2090#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
2091#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
2092#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
2093#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2094#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2095#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2096#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2097#define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
2098#define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
2099#define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
2100#define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
2101#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
2102#define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
2103#define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
2104#define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
2105#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
2106#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
2107#define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
2108#define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
2109#define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
2110#define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
2111#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
2112#define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2113#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2114#define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2115#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
2116#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
2117#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
2118#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
2119#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2120#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2121#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
2122#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
2123#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
2124#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2125#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
2126#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
2127#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
2128#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
2129#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2130#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2131#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2132#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2133#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
2134#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
2135#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
2136#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
2137#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
2138#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2139#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
2140#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
2141#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
2142#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
2143#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
2144#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
2145#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
2146#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
2147#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2148#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2149#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2150#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2151#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
2152#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
2153#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
2154#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
2155#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2156#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2157#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
2158#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
2159#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
2160#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2161#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
2162#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
2163#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
2164#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
2165#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2166#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2167#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2168#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2169#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
2170#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
2171#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
2172#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
2173#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
2174#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2175#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
2176#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
2177#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
2178#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
2179#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
2180#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
2181#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
2182#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
2183#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2184#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2185#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2186#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2187#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
2188#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
2189#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
2190#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
2191#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
2192#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2193#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
2194#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
2195#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
2196#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
2197#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
2198#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
2199#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
2200#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
2201#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2202#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2203#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2204#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2205#define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
2206#define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
2207#define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
2208#define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
2209#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
2210#define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2211#define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
2212#define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
2213#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
2214#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
2215#define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
2216#define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
2217#define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
2218#define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
2219#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2220#define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2221#define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x10000
2222#define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x10
2223#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2224#define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2225#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
2226#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
2227#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
2228#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
2229#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
2230#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2231#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
2232#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
2233#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
2234#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
2235#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
2236#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
2237#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
2238#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
2239#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2240#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2241#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
2242#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
2243#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2244#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2245#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
2246#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
2247#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
2248#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
2249#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
2250#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2251#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
2252#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
2253#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
2254#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
2255#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
2256#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
2257#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
2258#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
2259#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2260#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2261#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
2262#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
2263#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2264#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2265#define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
2266#define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
2267#define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
2268#define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
2269#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
2270#define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
2271#define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
2272#define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
2273#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
2274#define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
2275#define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
2276#define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
2277#define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
2278#define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
2279#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
2280#define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
2281#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2282#define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2283#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
2284#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
2285#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
2286#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
2287#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
2288#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
2289#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
2290#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
2291#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
2292#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
2293#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
2294#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
2295#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
2296#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
2297#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
2298#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2299#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2300#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2301#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
2302#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
2303#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
2304#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
2305#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2306#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2307#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
2308#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
2309#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
2310#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
2311#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
2312#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
2313#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
2314#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
2315#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2316#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2317#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2318#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2319#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
2320#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
2321#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
2322#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
2323#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
2324#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
2325#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
2326#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
2327#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
2328#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
2329#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
2330#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
2331#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
2332#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
2333#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
2334#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2335#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2336#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2337#define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
2338#define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
2339#define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
2340#define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
2341#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2342#define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2343#define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
2344#define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
2345#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
2346#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
2347#define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
2348#define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
2349#define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
2350#define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
2351#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2352#define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2353#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2354#define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2355#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
2356#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
2357#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2358#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2359#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
2360#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
2361#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
2362#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
2363#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
2364#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
2365#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
2366#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
2367#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
2368#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
2369#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
2370#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
2371#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
2372#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
2373#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2374#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2375#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
2376#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
2377#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
2378#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
2379#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
2380#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
2381#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
2382#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
2383#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
2384#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
2385#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
2386#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
2387#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
2388#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
2389#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2390#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2391#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
2392#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
2393#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
2394#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
2395#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
2396#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
2397#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
2398#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
2399#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
2400#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
2401#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
2402#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
2403#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
2404#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
2405#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2406#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2407#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
2408#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
2409#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
2410#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
2411#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
2412#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
2413#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
2414#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
2415#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
2416#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
2417#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
2418#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
2419#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
2420#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
2421#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
2422#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
2423#define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
2424#define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
2425#define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
2426#define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
2427#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
2428#define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
2429#define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
2430#define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
2431#define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
2432#define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
2433#define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
2434#define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
2435#define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
2436#define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
2437#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
2438#define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2439#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2440#define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2441#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
2442#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
2443#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
2444#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
2445#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2446#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2447#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
2448#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
2449#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
2450#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2451#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
2452#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
2453#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
2454#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
2455#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2456#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2457#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2458#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2459#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
2460#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
2461#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
2462#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
2463#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
2464#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
2465#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
2466#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
2467#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
2468#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
2469#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
2470#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
2471#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
2472#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
2473#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
2474#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
2475#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2476#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2477#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
2478#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
2479#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
2480#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
2481#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2482#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2483#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
2484#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
2485#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
2486#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
2487#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
2488#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
2489#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
2490#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
2491#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2492#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2493#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2494#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2495#define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
2496#define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
2497#define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
2498#define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
2499#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
2500#define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2501#define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
2502#define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
2503#define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
2504#define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
2505#define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
2506#define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
2507#define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
2508#define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
2509#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2510#define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2511#define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x10000
2512#define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x10
2513#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2514#define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2515#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
2516#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
2517#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
2518#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
2519#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
2520#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
2521#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
2522#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
2523#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
2524#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
2525#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
2526#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
2527#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
2528#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
2529#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
2530#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2531#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2532#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2533#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
2534#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
2535#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
2536#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
2537#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
2538#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
2539#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
2540#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
2541#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
2542#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
2543#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
2544#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
2545#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
2546#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
2547#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
2548#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
2549#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2550#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2551#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
2552#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
2553#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
2554#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
2555#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
2556#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2557#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
2558#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
2559#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
2560#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
2561#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
2562#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
2563#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
2564#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
2565#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2566#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2567#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2568#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2569#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
2570#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
2571#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
2572#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
2573#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
2574#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2575#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
2576#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
2577#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
2578#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
2579#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
2580#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
2581#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
2582#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
2583#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2584#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2585#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2586#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2587#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
2588#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
2589#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
2590#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
2591#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
2592#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2593#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
2594#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
2595#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
2596#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
2597#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
2598#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
2599#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
2600#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
2601#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2602#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2603#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2604#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2605#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
2606#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
2607#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
2608#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
2609#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
2610#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
2611#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
2612#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
2613#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
2614#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
2615#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
2616#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
2617#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
2618#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
2619#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
2620#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
2621#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2622#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2623#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
2624#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
2625#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
2626#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
2627#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
2628#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2629#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
2630#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
2631#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
2632#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
2633#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
2634#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
2635#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
2636#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
2637#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2638#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2639#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2640#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2641#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
2642#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
2643#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
2644#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
2645#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
2646#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2647#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
2648#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
2649#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
2650#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
2651#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
2652#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
2653#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
2654#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
2655#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2656#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2657#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
2658#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
2659#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2660#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2661#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
2662#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
2663#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
2664#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
2665#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
2666#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2667#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
2668#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
2669#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
2670#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
2671#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
2672#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
2673#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
2674#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
2675#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2676#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2677#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2678#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2679#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
2680#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
2681#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
2682#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
2683#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2684#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2685#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
2686#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
2687#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
2688#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2689#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
2690#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
2691#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
2692#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
2693#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2694#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2695#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2696#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2697#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
2698#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
2699#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
2700#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
2701#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
2702#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
2703#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
2704#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
2705#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
2706#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
2707#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
2708#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
2709#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
2710#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
2711#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
2712#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
2713#define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
2714#define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
2715#define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
2716#define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
2717#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2718#define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2719#define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
2720#define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
2721#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
2722#define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
2723#define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
2724#define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
2725#define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
2726#define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
2727#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2728#define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2729#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2730#define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2731#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
2732#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
2733#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
2734#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
2735#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2736#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2737#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
2738#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
2739#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
2740#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2741#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
2742#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
2743#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
2744#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
2745#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2746#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2747#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2748#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2749#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
2750#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
2751#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
2752#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
2753#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
2754#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
2755#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
2756#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
2757#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
2758#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
2759#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
2760#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
2761#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
2762#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
2763#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
2764#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
2765#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2766#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2767#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
2768#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
2769#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
2770#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
2771#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2772#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2773#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
2774#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
2775#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
2776#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2777#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
2778#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
2779#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
2780#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
2781#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2782#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2783#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2784#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2785#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
2786#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
2787#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
2788#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
2789#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2790#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2791#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
2792#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
2793#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
2794#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
2795#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
2796#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
2797#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
2798#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
2799#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2800#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2801#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2802#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2803#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
2804#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2805#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2806#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2807#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2808#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
2809#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
2810#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
2811#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
2812#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
2813#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2814#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2815#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
2816#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
2817#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
2818#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
2819#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
2820#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
2821#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
2822#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
2823#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2824#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2825#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2826#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2827#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
2828#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2829#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2830#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2831#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2832#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
2833#define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
2834#define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
2835#define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
2836#define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
2837#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
2838#define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2839#define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
2840#define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
2841#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
2842#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
2843#define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
2844#define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
2845#define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
2846#define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
2847#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2848#define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2849#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2850#define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2851#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
2852#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
2853#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
2854#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
2855#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2856#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2857#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
2858#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
2859#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
2860#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
2861#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
2862#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
2863#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
2864#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
2865#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2866#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2867#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2868#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2869#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
2870#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2871#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2872#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2873#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2874#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
2875#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
2876#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
2877#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
2878#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
2879#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2880#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2881#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
2882#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
2883#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
2884#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
2885#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
2886#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
2887#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
2888#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
2889#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2890#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2891#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2892#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2893#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
2894#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2895#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2896#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2897#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2898#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
2899#define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
2900#define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
2901#define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
2902#define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
2903#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
2904#define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2905#define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
2906#define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
2907#define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
2908#define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
2909#define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
2910#define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
2911#define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
2912#define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
2913#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2914#define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2915#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2916#define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2917#define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
2918#define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
2919#define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
2920#define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
2921#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
2922#define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2923#define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
2924#define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
2925#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
2926#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
2927#define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
2928#define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
2929#define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
2930#define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
2931#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2932#define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2933#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2934#define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2935#define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
2936#define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
2937#define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
2938#define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
2939#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
2940#define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2941#define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
2942#define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
2943#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
2944#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
2945#define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
2946#define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
2947#define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
2948#define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
2949#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2950#define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2951#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2952#define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2953#define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
2954#define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
2955#define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
2956#define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
2957#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
2958#define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2959#define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
2960#define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
2961#define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
2962#define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
2963#define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
2964#define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
2965#define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
2966#define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
2967#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2968#define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2969#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2970#define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2971#define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
2972#define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
2973#define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
2974#define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
2975#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
2976#define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2977#define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
2978#define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
2979#define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
2980#define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
2981#define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
2982#define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
2983#define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
2984#define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
2985#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2986#define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2987#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2988#define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2989#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
2990#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
2991#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
2992#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
2993#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
2994#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
2995#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
2996#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
2997#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
2998#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
2999#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
3000#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
3001#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
3002#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3003#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3004#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3005#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3006#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3007#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3008#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3009#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3010#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3011#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3012#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3013#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
3014#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
3015#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
3016#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
3017#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3018#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3019#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
3020#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
3021#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3022#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3023#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
3024#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
3025#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
3026#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3027#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3028#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3029#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3030#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3031#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3032#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3033#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3034#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3035#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3036#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3037#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
3038#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
3039#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
3040#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
3041#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3042#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3043#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
3044#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
3045#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3046#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3047#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
3048#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
3049#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3050#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3051#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3052#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3053#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3054#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3055#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3056#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3057#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3058#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3059#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3060#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3061#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
3062#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
3063#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
3064#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
3065#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3066#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3067#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
3068#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
3069#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3070#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3071#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
3072#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
3073#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
3074#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3075#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3076#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3077#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3078#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3079#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3080#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3081#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3082#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3083#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3084#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3085#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
3086#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
3087#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
3088#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
3089#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
3090#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
3091#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
3092#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
3093#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
3094#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
3095#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
3096#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
3097#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
3098#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
3099#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
3100#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
3101#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3102#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3103#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
3104#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
3105#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
3106#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
3107#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
3108#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
3109#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
3110#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
3111#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
3112#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
3113#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3114#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3115#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
3116#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
3117#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3118#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3119#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
3120#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
3121#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
3122#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3123#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3124#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3125#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3126#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3127#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3128#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3129#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3130#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3131#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3132#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3133#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
3134#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
3135#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
3136#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
3137#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3138#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3139#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
3140#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
3141#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3142#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3143#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
3144#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
3145#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3146#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3147#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3148#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3149#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3150#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3151#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3152#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3153#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3154#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3155#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3156#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3157#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
3158#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
3159#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3160#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3161#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
3162#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
3163#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
3164#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
3165#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
3166#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
3167#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
3168#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
3169#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
3170#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
3171#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
3172#define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
3173#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
3174#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
3175#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3176#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3177#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
3178#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
3179#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
3180#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
3181#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
3182#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
3183#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
3184#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
3185#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
3186#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
3187#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
3188#define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
3189#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
3190#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
3191#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3192#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3193#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
3194#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
3195#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
3196#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
3197#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
3198#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
3199#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
3200#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
3201#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
3202#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
3203#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
3204#define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
3205#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
3206#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
3207#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3208#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3209#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
3210#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
3211#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
3212#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
3213#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
3214#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
3215#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
3216#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
3217#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
3218#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
3219#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
3220#define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
3221#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
3222#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
3223#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3224#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3225#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
3226#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
3227#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
3228#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
3229#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
3230#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
3231#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
3232#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
3233#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
3234#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
3235#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
3236#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
3237#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
3238#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
3239#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3240#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3241#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
3242#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
3243#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
3244#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
3245#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
3246#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
3247#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
3248#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
3249#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
3250#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
3251#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
3252#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
3253#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
3254#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
3255#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3256#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3257#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
3258#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
3259#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
3260#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
3261#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
3262#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
3263#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
3264#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
3265#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
3266#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
3267#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
3268#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
3269#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
3270#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
3271#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3272#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3273#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
3274#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
3275#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
3276#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
3277#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
3278#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
3279#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
3280#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
3281#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
3282#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
3283#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
3284#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
3285#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
3286#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
3287#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
3288#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
3289#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
3290#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
3291#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
3292#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
3293#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
3294#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
3295#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
3296#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
3297#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
3298#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
3299#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
3300#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
3301#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
3302#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
3303#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3304#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3305#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
3306#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
3307#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3308#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3309#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
3310#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
3311#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3312#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3313#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
3314#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
3315#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3316#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3317#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
3318#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
3319#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3320#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3321#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
3322#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
3323#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3324#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3325#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
3326#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
3327#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3328#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3329#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
3330#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
3331#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3332#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3333#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
3334#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
3335#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
3336#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
3337#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
3338#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
3339#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
3340#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
3341#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
3342#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
3343#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
3344#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
3345#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
3346#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
3347#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
3348#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
3349#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
3350#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
3351#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
3352#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
3353#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
3354#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
3355#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
3356#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
3357#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
3358#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
3359#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
3360#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
3361#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
3362#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
3363#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
3364#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
3365#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3366#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3367#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3368#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3369#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3370#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3371#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3372#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3373#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
3374#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
3375#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
3376#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
3377#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
3378#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
3379#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
3380#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
3381#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3382#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3383#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3384#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3385#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3386#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3387#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3388#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3389#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
3390#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
3391#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
3392#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
3393#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
3394#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
3395#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
3396#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
3397#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
3398#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
3399#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
3400#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
3401#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
3402#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
3403#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
3404#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
3405#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
3406#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
3407#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
3408#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
3409#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
3410#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
3411#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
3412#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
3413#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
3414#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
3415#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
3416#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
3417#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
3418#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
3419#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
3420#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
3421#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
3422#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
3423#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
3424#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
3425#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
3426#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
3427#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
3428#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
3429#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
3430#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
3431#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
3432#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
3433#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
3434#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
3435#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
3436#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
3437#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
3438#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
3439#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
3440#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
3441#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
3442#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
3443#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
3444#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
3445#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
3446#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
3447#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
3448#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
3449#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
3450#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
3451#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
3452#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
3453#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
3454#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
3455#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
3456#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
3457#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
3458#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
3459#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
3460#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
3461#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
3462#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
3463#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
3464#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
3465#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
3466#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
3467#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
3468#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
3469#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
3470#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
3471#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
3472#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
3473#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
3474#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
3475#define MC_RD_GRP_GFX__CP_MASK 0xf
3476#define MC_RD_GRP_GFX__CP__SHIFT 0x0
3477#define MC_RD_GRP_GFX__SH_MASK 0xf0
3478#define MC_RD_GRP_GFX__SH__SHIFT 0x4
3479#define MC_RD_GRP_GFX__IA_MASK 0xf00
3480#define MC_RD_GRP_GFX__IA__SHIFT 0x8
3481#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
3482#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
3483#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
3484#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
3485#define MC_RD_GRP_GFX__ISP_MASK 0xf00000
3486#define MC_RD_GRP_GFX__ISP__SHIFT 0x14
3487#define MC_RD_GRP_GFX__XDMAM_MASK 0xf000000
3488#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x18
3489#define MC_WR_GRP_GFX__CP_MASK 0xf
3490#define MC_WR_GRP_GFX__CP__SHIFT 0x0
3491#define MC_WR_GRP_GFX__SH_MASK 0xf0
3492#define MC_WR_GRP_GFX__SH__SHIFT 0x4
3493#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
3494#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
3495#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
3496#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
3497#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
3498#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
3499#define MC_WR_GRP_GFX__XDMA_MASK 0xf00000
3500#define MC_WR_GRP_GFX__XDMA__SHIFT 0x14
3501#define MC_WR_GRP_GFX__XDMAM_MASK 0xf000000
3502#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x18
3503#define MC_RD_GRP_SYS__RLC_MASK 0xf
3504#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
3505#define MC_RD_GRP_SYS__VMC_MASK 0xf0
3506#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
3507#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
3508#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
3509#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
3510#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
3511#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
3512#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
3513#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
3514#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
3515#define MC_RD_GRP_SYS__VCE_MASK 0xf000000
3516#define MC_RD_GRP_SYS__VCE__SHIFT 0x18
3517#define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
3518#define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
3519#define MC_WR_GRP_SYS__IH_MASK 0xf
3520#define MC_WR_GRP_SYS__IH__SHIFT 0x0
3521#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
3522#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
3523#define MC_WR_GRP_SYS__RLC_MASK 0xf00
3524#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
3525#define MC_WR_GRP_SYS__SAM_MASK 0xf000
3526#define MC_WR_GRP_SYS__SAM__SHIFT 0xc
3527#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
3528#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
3529#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
3530#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
3531#define MC_WR_GRP_SYS__VCE_MASK 0xf000000
3532#define MC_WR_GRP_SYS__VCE__SHIFT 0x18
3533#define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
3534#define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
3535#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
3536#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
3537#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
3538#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
3539#define MC_RD_GRP_OTH__HDP_MASK 0xf00
3540#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
3541#define MC_RD_GRP_OTH__SEM_MASK 0xf000
3542#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
3543#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
3544#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
3545#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
3546#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
3547#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
3548#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
3549#define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
3550#define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
3551#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
3552#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
3553#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
3554#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
3555#define MC_WR_GRP_OTH__HDP_MASK 0xf00
3556#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
3557#define MC_WR_GRP_OTH__SEM_MASK 0xf000
3558#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
3559#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
3560#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
3561#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
3562#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
3563#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
3564#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
3565#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
3566#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
3567#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
3568#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
3569#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
3570#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
3571#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
3572#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
3573#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
3574#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
3575#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
3576#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
3577#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3578#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3579#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3580#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3581#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
3582#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
3583#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
3584#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
3585#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
3586#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
3587#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
3588#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
3589#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
3590#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
3591#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
3592#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
3593#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
3594#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
3595#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3596#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3597#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3598#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3599#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3600#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3601#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3602#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3603#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3604#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3605#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3606#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3607#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3608#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3609#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3610#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3611#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
3612#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
3613#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
3614#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
3615#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
3616#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
3617#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
3618#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
3619#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
3620#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
3621#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
3622#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
3623#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
3624#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
3625#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
3626#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
3627#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
3628#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
3629#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
3630#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
3631#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
3632#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
3633#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
3634#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
3635#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
3636#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
3637#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
3638#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
3639#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
3640#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
3641#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
3642#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
3643#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3644#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3645#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3646#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3647#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3648#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3649#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3650#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3651#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3652#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3653#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3654#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3655#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
3656#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
3657#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
3658#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
3659#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3660#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3661#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
3662#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
3663#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
3664#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
3665#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
3666#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
3667#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
3668#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
3669#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3670#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3671#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3672#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3673#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3674#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3675#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3676#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3677#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3678#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3679#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3680#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3681#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
3682#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
3683#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
3684#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
3685#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3686#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3687#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
3688#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
3689#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
3690#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
3691#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
3692#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
3693#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
3694#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
3695#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
3696#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
3697#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3698#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3699#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3700#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3701#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3702#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3703#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3704#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3705#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3706#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3707#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3708#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3709#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3710#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3711#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3712#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3713#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3714#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3715#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3716#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3717#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3718#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3719#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3720#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3721#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
3722#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3723#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
3724#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3725#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
3726#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3727#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3728#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3729#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3730#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3731#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3732#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3733#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3734#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3735#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3736#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3737#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3738#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3739#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3740#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3741#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
3742#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3743#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3744#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3745#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3746#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3747#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3748#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3749#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3750#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3751#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3752#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3753#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3754#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3755#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3756#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3757#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3758#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3759#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3760#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3761#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3762#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3763#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3764#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3765#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3766#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3767#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3768#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3769#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3770#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3771#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3772#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3773#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3774#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3775#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3776#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3777#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3778#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3779#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
3780#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3781#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
3782#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3783#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
3784#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3785#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3786#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3787#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3788#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3789#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3790#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3791#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3792#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3793#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3794#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3795#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3796#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3797#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3798#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3799#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
3800#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3801#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3802#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3803#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3804#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3805#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3806#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3807#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3808#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3809#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
3810#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
3811#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
3812#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
3813#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
3814#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
3815#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
3816#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
3817#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
3818#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
3819#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
3820#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
3821#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3822#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3823#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3824#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3825#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3826#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3827#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3828#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3829#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
3830#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
3831#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3832#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3833#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3834#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3835#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3836#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3837#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3838#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3839#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3840#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3841#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
3842#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
3843#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3844#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3845#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3846#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3847#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3848#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3849#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3850#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3851#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3852#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3853#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
3854#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
3855#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3856#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3857#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3858#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3859#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3860#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3861#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3862#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3863#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3864#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3865#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
3866#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
3867#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3868#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3869#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3870#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3871#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3872#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3873#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3874#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3875#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3876#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3877#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
3878#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
3879#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
3880#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
3881#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
3882#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
3883#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
3884#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
3885#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
3886#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
3887#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
3888#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
3889#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
3890#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
3891#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
3892#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
3893#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
3894#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
3895#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
3896#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
3897#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
3898#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
3899#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
3900#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
3901#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
3902#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
3903#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
3904#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
3905#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
3906#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
3907#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
3908#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
3909#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
3910#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
3911#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
3912#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
3913#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
3914#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
3915#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
3916#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
3917#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
3918#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
3919#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
3920#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
3921#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
3922#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
3923#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
3924#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
3925#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
3926#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
3927#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
3928#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
3929#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
3930#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
3931#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
3932#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
3933#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
3934#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
3935#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
3936#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
3937#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
3938#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
3939#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
3940#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
3941#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
3942#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
3943#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
3944#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
3945#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
3946#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
3947#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
3948#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
3949#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
3950#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
3951#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3952#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3953#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3954#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3955#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3956#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3957#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3958#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3959#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3960#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3961#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
3962#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
3963#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3964#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3965#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3966#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3967#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3968#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3969#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3970#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3971#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3972#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3973#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
3974#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
3975#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3976#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3977#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3978#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3979#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3980#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3981#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3982#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3983#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3984#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3985#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
3986#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
3987#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3988#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3989#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3990#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3991#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3992#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3993#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3994#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3995#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3996#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3997#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
3998#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
3999#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
4000#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
4001#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
4002#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
4003#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
4004#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
4005#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
4006#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
4007#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
4008#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
4009#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
4010#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
4011#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
4012#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
4013#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
4014#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
4015#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
4016#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
4017#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
4018#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
4019#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
4020#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
4021#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
4022#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
4023#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
4024#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
4025#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
4026#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
4027#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
4028#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
4029#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
4030#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
4031#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
4032#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
4033#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
4034#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
4035#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
4036#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
4037#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
4038#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
4039#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
4040#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
4041#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
4042#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
4043#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
4044#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
4045#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
4046#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
4047#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
4048#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
4049#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
4050#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
4051#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
4052#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
4053#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
4054#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
4055#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
4056#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
4057#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
4058#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
4059#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
4060#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
4061#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
4062#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
4063#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
4064#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
4065#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
4066#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
4067#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
4068#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
4069#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
4070#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
4071#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
4072#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
4073#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
4074#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
4075#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
4076#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
4077#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
4078#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
4079#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
4080#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
4081#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
4082#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
4083#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
4084#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
4085#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
4086#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
4087#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
4088#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
4089#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
4090#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
4091#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
4092#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
4093#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
4094#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
4095#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
4096#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
4097#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
4098#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
4099#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
4100#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
4101#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
4102#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
4103#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
4104#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
4105#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
4106#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
4107#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
4108#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
4109#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
4110#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
4111#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
4112#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
4113#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
4114#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
4115#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
4116#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
4117#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
4118#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
4119#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
4120#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
4121#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
4122#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
4123#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
4124#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
4125#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
4126#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
4127#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
4128#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
4129#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
4130#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
4131#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
4132#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
4133#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
4134#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
4135#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
4136#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
4137#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
4138#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
4139#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
4140#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
4141#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
4142#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
4143#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
4144#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
4145#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
4146#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
4147#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
4148#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
4149#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
4150#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
4151#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
4152#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
4153#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
4154#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
4155#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
4156#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
4157#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
4158#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
4159#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
4160#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
4161#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
4162#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
4163#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
4164#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
4165#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
4166#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
4167#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
4168#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
4169#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
4170#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
4171#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
4172#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
4173#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
4174#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
4175#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
4176#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
4177#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
4178#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
4179#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
4180#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
4181#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
4182#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
4183#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
4184#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
4185#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
4186#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
4187#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
4188#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
4189#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
4190#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
4191#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
4192#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
4193#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
4194#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
4195#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
4196#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
4197#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
4198#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
4199#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
4200#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
4201#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
4202#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
4203#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
4204#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
4205#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
4206#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
4207#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
4208#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
4209#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
4210#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
4211#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
4212#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
4213#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
4214#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
4215#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
4216#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
4217#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
4218#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
4219#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
4220#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
4221#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
4222#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
4223#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
4224#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
4225#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
4226#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
4227#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
4228#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
4229#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
4230#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
4231#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
4232#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
4233#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
4234#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
4235#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
4236#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
4237#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
4238#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
4239#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
4240#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
4241#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
4242#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
4243#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
4244#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
4245#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
4246#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
4247#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
4248#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
4249#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
4250#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
4251#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
4252#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
4253#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
4254#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
4255#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
4256#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
4257#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
4258#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
4259#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
4260#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
4261#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
4262#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
4263#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
4264#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
4265#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
4266#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
4267#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
4268#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
4269#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
4270#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
4271#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
4272#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
4273#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
4274#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
4275#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
4276#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
4277#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
4278#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
4279#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
4280#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
4281#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
4282#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
4283#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
4284#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
4285#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
4286#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
4287#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
4288#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
4289#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
4290#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
4291#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
4292#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
4293#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
4294#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
4295#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
4296#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
4297#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
4298#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
4299#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
4300#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
4301#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
4302#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
4303#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
4304#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
4305#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
4306#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
4307#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
4308#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
4309#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
4310#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
4311#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
4312#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
4313#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
4314#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
4315#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
4316#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
4317#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
4318#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
4319#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
4320#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
4321#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
4322#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
4323#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
4324#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
4325#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
4326#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
4327#define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
4328#define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
4329#define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
4330#define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
4331#define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
4332#define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
4333#define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
4334#define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
4335#define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
4336#define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
4337#define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
4338#define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
4339#define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
4340#define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
4341#define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
4342#define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
4343#define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
4344#define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
4345#define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
4346#define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
4347#define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
4348#define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
4349#define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
4350#define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
4351#define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
4352#define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
4353#define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
4354#define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
4355#define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
4356#define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
4357#define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
4358#define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
4359#define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
4360#define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
4361#define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
4362#define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
4363#define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
4364#define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
4365#define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
4366#define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
4367#define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
4368#define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
4369#define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
4370#define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
4371#define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
4372#define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
4373#define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
4374#define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
4375#define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
4376#define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
4377#define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
4378#define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
4379#define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
4380#define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
4381#define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
4382#define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
4383#define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
4384#define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
4385#define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
4386#define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
4387#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
4388#define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
4389#define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
4390#define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
4391#define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
4392#define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
4393#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
4394#define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
4395#define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
4396#define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
4397#define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
4398#define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
4399#define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
4400#define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
4401#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
4402#define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
4403#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
4404#define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
4405#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
4406#define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
4407#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
4408#define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
4409#define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
4410#define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
4411#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
4412#define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
4413#define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
4414#define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
4415#define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4416#define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4417#define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4418#define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4419#define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
4420#define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
4421#define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4422#define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4423#define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4424#define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4425#define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
4426#define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
4427#define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4428#define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4429#define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4430#define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4431#define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
4432#define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
4433#define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4434#define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4435#define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4436#define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4437#define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
4438#define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
4439#define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
4440#define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
4441#define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
4442#define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
4443#define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
4444#define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
4445#define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
4446#define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
4447#define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
4448#define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
4449#define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
4450#define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
4451#define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
4452#define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
4453#define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
4454#define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
4455#define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
4456#define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
4457#define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
4458#define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
4459#define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
4460#define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
4461#define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
4462#define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
4463#define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
4464#define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
4465#define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
4466#define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
4467#define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
4468#define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
4469#define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
4470#define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
4471#define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
4472#define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
4473#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
4474#define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
4475#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4476#define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4477#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4478#define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4479#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
4480#define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
4481#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4482#define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4483#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4484#define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4485#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
4486#define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
4487#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4488#define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4489#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4490#define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4491#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
4492#define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
4493#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4494#define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4495#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4496#define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4497#define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
4498#define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
4499#define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
4500#define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
4501#define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
4502#define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
4503#define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
4504#define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
4505#define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
4506#define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
4507#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
4508#define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
4509#define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
4510#define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
4511#define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
4512#define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
4513#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
4514#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
4515#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
4516#define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
4517#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
4518#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
4519#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
4520#define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
4521#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
4522#define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
4523#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
4524#define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
4525#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
4526#define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
4527#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
4528#define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
4529#define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
4530#define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
4531#define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
4532#define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
4533#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
4534#define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
4535#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
4536#define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
4537#define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
4538#define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
4539#define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
4540#define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
4541#define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
4542#define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
4543#define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
4544#define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
4545#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
4546#define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
4547#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
4548#define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
4549#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
4550#define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
4551#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
4552#define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
4553#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
4554#define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
4555#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
4556#define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
4557#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
4558#define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
4559#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
4560#define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
4561#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
4562#define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
4563#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
4564#define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
4565#define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
4566#define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
4567#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
4568#define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
4569#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
4570#define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
4571#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
4572#define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
4573#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
4574#define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
4575#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
4576#define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
4577#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
4578#define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
4579#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
4580#define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
4581#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
4582#define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
4583#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
4584#define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
4585#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
4586#define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
4587#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
4588#define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
4589#define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
4590#define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
4591#define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
4592#define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
4593#define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
4594#define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
4595#define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
4596#define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
4597#define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
4598#define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
4599#define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
4600#define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
4601#define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
4602#define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
4603#define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
4604#define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
4605#define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
4606#define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
4607#define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
4608#define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
4609#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
4610#define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
4611#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
4612#define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
4613#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
4614#define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
4615#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
4616#define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
4617#define MC_XPB_STICKY__BITS_MASK 0xffffffff
4618#define MC_XPB_STICKY__BITS__SHIFT 0x0
4619#define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
4620#define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
4621#define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
4622#define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
4623#define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
4624#define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
4625#define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
4626#define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
4627#define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
4628#define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
4629#define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
4630#define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
4631#define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
4632#define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
4633#define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
4634#define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
4635#define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
4636#define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
4637#define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
4638#define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
4639#define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
4640#define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
4641#define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
4642#define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
4643#define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
4644#define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
4645#define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
4646#define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
4647#define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
4648#define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
4649#define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
4650#define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
4651#define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
4652#define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
4653#define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
4654#define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
4655#define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
4656#define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
4657#define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
4658#define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
4659#define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
4660#define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
4661#define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
4662#define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
4663#define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
4664#define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
4665#define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
4666#define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
4667#define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
4668#define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
4669#define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
4670#define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
4671#define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
4672#define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
4673#define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
4674#define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
4675#define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
4676#define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
4677#define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
4678#define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
4679#define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
4680#define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
4681#define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
4682#define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
4683#define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
4684#define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
4685#define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
4686#define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
4687#define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
4688#define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
4689#define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
4690#define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
4691#define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
4692#define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
4693#define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
4694#define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
4695#define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
4696#define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
4697#define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
4698#define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
4699#define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
4700#define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
4701#define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
4702#define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
4703#define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
4704#define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
4705#define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
4706#define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
4707#define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
4708#define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
4709#define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
4710#define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
4711#define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
4712#define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
4713#define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
4714#define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
4715#define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
4716#define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
4717#define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
4718#define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
4719#define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
4720#define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
4721#define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
4722#define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
4723#define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
4724#define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
4725#define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
4726#define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
4727#define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
4728#define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
4729#define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
4730#define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
4731#define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
4732#define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
4733#define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
4734#define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
4735#define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
4736#define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
4737#define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
4738#define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
4739#define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
4740#define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
4741#define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
4742#define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
4743#define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
4744#define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
4745#define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
4746#define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
4747#define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
4748#define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
4749#define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
4750#define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
4751#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
4752#define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
4753#define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
4754#define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
4755#define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
4756#define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
4757#define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
4758#define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
4759#define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
4760#define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
4761#define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
4762#define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
4763#define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
4764#define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
4765#define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
4766#define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
4767#define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
4768#define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
4769#define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
4770#define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
4771#define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
4772#define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
4773#define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
4774#define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
4775#define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
4776#define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
4777#define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
4778#define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
4779#define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
4780#define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
4781#define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
4782#define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
4783#define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
4784#define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
4785#define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
4786#define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
4787#define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
4788#define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
4789#define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
4790#define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
4791#define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
4792#define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
4793#define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
4794#define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
4795#define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
4796#define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
4797#define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
4798#define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
4799#define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
4800#define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
4801#define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
4802#define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
4803#define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
4804#define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
4805#define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
4806#define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
4807#define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
4808#define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
4809#define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
4810#define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
4811#define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
4812#define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
4813#define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
4814#define