1/*
2 * GMC_8_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GMC_8_1_D_H
25#define GMC_8_1_D_H
26
27#define mmMC_CONFIG 0x800
28#define mmMC_ARB_ATOMIC 0x9be
29#define mmMC_ARB_AGE_CNTL 0x9bf
30#define mmMC_ARB_RET_CREDITS2 0x9c0
31#define mmMC_ARB_FED_CNTL 0x9c1
32#define mmMC_ARB_GECC2_STATUS 0x9c2
33#define mmMC_ARB_GECC2_MISC 0x9c3
34#define mmMC_ARB_GECC2_DEBUG 0x9c4
35#define mmMC_ARB_GECC2_DEBUG2 0x9c5
36#define mmMC_ARB_PERF_CID 0x9c6
37#define mmMC_ARB_SNOOP 0x9c7
38#define mmMC_ARB_GRUB 0x9c8
39#define mmMC_ARB_GECC2 0x9c9
40#define mmMC_ARB_GECC2_CLI 0x9ca
41#define mmMC_ARB_ADDR_SWIZ0 0x9cb
42#define mmMC_ARB_ADDR_SWIZ1 0x9cc
43#define mmMC_ARB_MISC3 0x9cd
44#define mmMC_ARB_GRUB_PROMOTE 0x9ce
45#define mmMC_ARB_RTT_DATA 0x9cf
46#define mmMC_ARB_RTT_CNTL0 0x9d0
47#define mmMC_ARB_RTT_CNTL1 0x9d1
48#define mmMC_ARB_RTT_CNTL2 0x9d2
49#define mmMC_ARB_RTT_DEBUG 0x9d3
50#define mmMC_ARB_CAC_CNTL 0x9d4
51#define mmMC_ARB_MISC2 0x9d5
52#define mmMC_ARB_MISC 0x9d6
53#define mmMC_ARB_BANKMAP 0x9d7
54#define mmMC_ARB_RAMCFG 0x9d8
55#define mmMC_ARB_POP 0x9d9
56#define mmMC_ARB_MINCLKS 0x9da
57#define mmMC_ARB_SQM_CNTL 0x9db
58#define mmMC_ARB_ADDR_HASH 0x9dc
59#define mmMC_ARB_DRAM_TIMING 0x9dd
60#define mmMC_ARB_DRAM_TIMING2 0x9de
61#define mmMC_ARB_WTM_CNTL_RD 0x9df
62#define mmMC_ARB_WTM_CNTL_WR 0x9e0
63#define mmMC_ARB_WTM_GRPWT_RD 0x9e1
64#define mmMC_ARB_WTM_GRPWT_WR 0x9e2
65#define mmMC_ARB_TM_CNTL_RD 0x9e3
66#define mmMC_ARB_TM_CNTL_WR 0x9e4
67#define mmMC_ARB_LAZY0_RD 0x9e5
68#define mmMC_ARB_LAZY0_WR 0x9e6
69#define mmMC_ARB_LAZY1_RD 0x9e7
70#define mmMC_ARB_LAZY1_WR 0x9e8
71#define mmMC_ARB_AGE_RD 0x9e9
72#define mmMC_ARB_AGE_WR 0x9ea
73#define mmMC_ARB_RFSH_CNTL 0x9eb
74#define mmMC_ARB_RFSH_RATE 0x9ec
75#define mmMC_ARB_PM_CNTL 0x9ed
76#define mmMC_ARB_GDEC_RD_CNTL 0x9ee
77#define mmMC_ARB_GDEC_WR_CNTL 0x9ef
78#define mmMC_ARB_LM_RD 0x9f0
79#define mmMC_ARB_LM_WR 0x9f1
80#define mmMC_ARB_REMREQ 0x9f2
81#define mmMC_ARB_REPLAY 0x9f3
82#define mmMC_ARB_RET_CREDITS_RD 0x9f4
83#define mmMC_ARB_RET_CREDITS_WR 0x9f5
84#define mmMC_ARB_MAX_LAT_CID 0x9f6
85#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7
86#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8
87#define mmMC_ARB_GRUB_REALTIME_RD 0x9f9
88#define mmMC_ARB_CG 0x9fa
89#define mmMC_ARB_GRUB_REALTIME_WR 0x9fb
90#define mmMC_ARB_DRAM_TIMING_1 0x9fc
91#define mmMC_ARB_BUSY_STATUS 0x9fd
92#define mmMC_ARB_DRAM_TIMING2_1 0x9ff
93#define mmMC_ARB_GRUB2 0xa01
94#define mmMC_ARB_BURST_TIME 0xa02
95#define mmMC_CITF_XTRA_ENABLE 0x96d
96#define mmCC_MC_MAX_CHANNEL 0x96e
97#define mmMC_CG_CONFIG 0x96f
98#define mmMC_CITF_CNTL 0x970
99#define mmMC_CITF_CREDITS_VM 0x971
100#define mmMC_CITF_CREDITS_ARB_RD 0x972
101#define mmMC_CITF_CREDITS_ARB_WR 0x973
102#define mmMC_CITF_DAGB_CNTL 0x974
103#define mmMC_CITF_INT_CREDITS 0x975
104#define mmMC_CITF_RET_MODE 0x976
105#define mmMC_CITF_DAGB_DLY 0x977
106#define mmMC_RD_GRP_EXT 0x978
107#define mmMC_WR_GRP_EXT 0x979
108#define mmMC_CITF_REMREQ 0x97a
109#define mmMC_WR_TC0 0x97b
110#define mmMC_WR_TC1 0x97c
111#define mmMC_CITF_INT_CREDITS_WR 0x97d
112#define mmMC_CITF_CREDITS_ARB_RD2 0x97e
113#define mmMC_CITF_WTM_RD_CNTL 0x97f
114#define mmMC_CITF_WTM_WR_CNTL 0x980
115#define mmMC_RD_CB 0x981
116#define mmMC_RD_DB 0x982
117#define mmMC_RD_TC0 0x983
118#define mmMC_RD_TC1 0x984
119#define mmMC_RD_HUB 0x985
120#define mmMC_WR_CB 0x986
121#define mmMC_WR_DB 0x987
122#define mmMC_WR_HUB 0x988
123#define mmMC_CITF_CREDITS_XBAR 0x989
124#define mmMC_RD_GRP_LCL 0x98a
125#define mmMC_WR_GRP_LCL 0x98b
126#define mmMC_CITF_PERF_MON_CNTL2 0x98e
127#define mmMC_CITF_PERF_MON_RSLT2 0x991
128#define mmMC_CITF_MISC_RD_CG 0x992
129#define mmMC_CITF_MISC_WR_CG 0x993
130#define mmMC_CITF_MISC_VM_CG 0x994
131#define mmMC_HUB_MISC_POWER 0x82d
132#define mmMC_HUB_MISC_HUB_CG 0x82e
133#define mmMC_HUB_MISC_VM_CG 0x82f
134#define mmMC_HUB_MISC_SIP_CG 0x830
135#define mmMC_HUB_MISC_STATUS 0x832
136#define mmMC_HUB_MISC_OVERRIDE 0x833
137#define mmMC_HUB_MISC_FRAMING 0x834
138#define mmMC_HUB_WDP_CNTL 0x835
139#define mmMC_HUB_WDP_ERR 0x836
140#define mmMC_HUB_WDP_BP 0x837
141#define mmMC_HUB_WDP_STATUS 0x838
142#define mmMC_HUB_RDREQ_STATUS 0x839
143#define mmMC_HUB_WRRET_STATUS 0x83a
144#define mmMC_HUB_RDREQ_CNTL 0x83b
145#define mmMC_HUB_WRRET_CNTL 0x83c
146#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d
147#define mmMC_HUB_WDP_WTM_CNTL 0x83e
148#define mmMC_HUB_WDP_CREDITS 0x83f
149#define mmMC_HUB_WDP_CREDITS2 0x840
150#define mmMC_HUB_WDP_GBL0 0x841
151#define mmMC_HUB_WDP_GBL1 0x842
152#define mmMC_HUB_WDP_CREDITS3 0x843
153#define mmMC_HUB_RDREQ_CREDITS 0x844
154#define mmMC_HUB_RDREQ_CREDITS2 0x845
155#define mmMC_HUB_SHARED_DAGB_DLY 0x846
156#define mmMC_HUB_MISC_IDLE_STATUS 0x847
157#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848
158#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849
159#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a
160#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b
161#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c
162#define mmMC_HUB_WDP_SH2 0x84d
163#define mmMC_HUB_WDP_SH3 0x84e
164#define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f
165#define mmMC_HUB_WDP_VIN0 0x850
166#define mmMC_HUB_RDREQ_MCDW 0x851
167#define mmMC_HUB_RDREQ_MCDX 0x852
168#define mmMC_HUB_RDREQ_MCDY 0x853
169#define mmMC_HUB_RDREQ_MCDZ 0x854
170#define mmMC_HUB_RDREQ_SIP 0x855
171#define mmMC_HUB_RDREQ_GBL0 0x856
172#define mmMC_HUB_RDREQ_GBL1 0x857
173#define mmMC_HUB_RDREQ_SMU 0x858
174#define mmMC_HUB_RDREQ_SDMA0 0x859
175#define mmMC_HUB_RDREQ_HDP 0x85a
176#define mmMC_HUB_RDREQ_SDMA1 0x85b
177#define mmMC_HUB_RDREQ_RLC 0x85c
178#define mmMC_HUB_RDREQ_SEM 0x85d
179#define mmMC_HUB_RDREQ_VCE0 0x85e
180#define mmMC_HUB_RDREQ_UMC 0x85f
181#define mmMC_HUB_RDREQ_UVD 0x860
182#define mmMC_HUB_RDREQ_TLS 0x861
183#define mmMC_HUB_RDREQ_DMIF 0x862
184#define mmMC_HUB_RDREQ_MCIF 0x863
185#define mmMC_HUB_RDREQ_VMC 0x864
186#define mmMC_HUB_RDREQ_VCEU0 0x865
187#define mmMC_HUB_WDP_MCDW 0x866
188#define mmMC_HUB_WDP_MCDX 0x867
189#define mmMC_HUB_WDP_MCDY 0x868
190#define mmMC_HUB_WDP_MCDZ 0x869
191#define mmMC_HUB_WDP_SIP 0x86a
192#define mmMC_HUB_WDP_SDMA1 0x86b
193#define mmMC_HUB_WDP_SH0 0x86c
194#define mmMC_HUB_WDP_MCIF 0x86d
195#define mmMC_HUB_WDP_VCE0 0x86e
196#define mmMC_HUB_WDP_XDP 0x86f
197#define mmMC_HUB_WDP_IH 0x870
198#define mmMC_HUB_WDP_RLC 0x871
199#define mmMC_HUB_WDP_SEM 0x872
200#define mmMC_HUB_WDP_SMU 0x873
201#define mmMC_HUB_WDP_SH1 0x874
202#define mmMC_HUB_WDP_UMC 0x875
203#define mmMC_HUB_WDP_UVD 0x876
204#define mmMC_HUB_WDP_HDP 0x877
205#define mmMC_HUB_WDP_SDMA0 0x878
206#define mmMC_HUB_WRRET_MCDW 0x879
207#define mmMC_HUB_WRRET_MCDX 0x87a
208#define mmMC_HUB_WRRET_MCDY 0x87b
209#define mmMC_HUB_WRRET_MCDZ 0x87c
210#define mmMC_HUB_WDP_VCEU0 0x87d
211#define mmMC_HUB_WDP_XDMAM 0x87e
212#define mmMC_HUB_WDP_XDMA 0x87f
213#define mmMC_HUB_RDREQ_XDMAM 0x880
214#define mmMC_HUB_RDREQ_ACPG 0x881
215#define mmMC_HUB_RDREQ_ACPO 0x882
216#define mmMC_HUB_RDREQ_SAMMSP 0x883
217#define mmMC_HUB_RDREQ_VP8 0x884
218#define mmMC_HUB_RDREQ_VP8U 0x885
219#define mmMC_HUB_WDP_ACPG 0x886
220#define mmMC_HUB_WDP_ACPO 0x887
221#define mmMC_HUB_WDP_SAMMSP 0x888
222#define mmMC_HUB_WDP_VP8 0x889
223#define mmMC_HUB_WDP_VP8U 0x88a
224#define mmMC_HUB_RDREQ_ISP_SPM 0xde0
225#define mmMC_HUB_RDREQ_ISP_MPM 0xde1
226#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2
227#define mmMC_HUB_WDP_ISP_SPM 0xde3
228#define mmMC_HUB_WDP_ISP_MPS 0xde4
229#define mmMC_HUB_WDP_ISP_MPM 0xde5
230#define mmMC_HUB_WDP_ISP_CCPU 0xde6
231#define mmMC_HUB_RDREQ_MCDS 0xde7
232#define mmMC_HUB_RDREQ_MCDT 0xde8
233#define mmMC_HUB_RDREQ_MCDU 0xde9
234#define mmMC_HUB_RDREQ_MCDV 0xdea
235#define mmMC_HUB_WDP_MCDS 0xdeb
236#define mmMC_HUB_WDP_MCDT 0xdec
237#define mmMC_HUB_WDP_MCDU 0xded
238#define mmMC_HUB_WDP_MCDV 0xdee
239#define mmMC_HUB_WRRET_MCDS 0xdef
240#define mmMC_HUB_WRRET_MCDT 0xdf0
241#define mmMC_HUB_WRRET_MCDU 0xdf1
242#define mmMC_HUB_WRRET_MCDV 0xdf2
243#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3
244#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4
245#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5
246#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6
247#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7
248#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8
249#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9
250#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa
251#define mmMC_HUB_WDP_BP2 0xdfb
252#define mmMC_HUB_RDREQ_VCE1 0xdfc
253#define mmMC_HUB_RDREQ_VCEU1 0xdfd
254#define mmMC_HUB_WDP_VCE1 0xdfe
255#define mmMC_HUB_WDP_VCEU1 0xdff
256#define mmMC_RPB_CONF 0x94d
257#define mmMC_RPB_IF_CONF 0x94e
258#define mmMC_RPB_DBG1 0x94f
259#define mmMC_RPB_EFF_CNTL 0x950
260#define mmMC_RPB_ARB_CNTL 0x951
261#define mmMC_RPB_BIF_CNTL 0x952
262#define mmMC_RPB_WR_SWITCH_CNTL 0x953
263#define mmMC_RPB_WR_COMBINE_CNTL 0x954
264#define mmMC_RPB_RD_SWITCH_CNTL 0x955
265#define mmMC_RPB_CID_QUEUE_WR 0x956
266#define mmMC_RPB_CID_QUEUE_RD 0x957
267#define mmMC_RPB_PERF_COUNTER_CNTL 0x958
268#define mmMC_RPB_PERF_COUNTER_STATUS 0x959
269#define mmMC_RPB_CID_QUEUE_EX 0x95a
270#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b
271#define mmMC_RPB_TCI_CNTL 0x95c
272#define mmMC_RPB_TCI_CNTL2 0x95d
273#define mmMC_SHARED_CHMAP 0x801
274#define mmMC_SHARED_CHREMAP 0x802
275#define mmMC_RD_GRP_GFX 0x803
276#define mmMC_WR_GRP_GFX 0x804
277#define mmMC_RD_GRP_SYS 0x805
278#define mmMC_WR_GRP_SYS 0x806
279#define mmMC_RD_GRP_OTH 0x807
280#define mmMC_WR_GRP_OTH 0x808
281#define mmMC_VM_FB_LOCATION 0x809
282#define mmMC_VM_AGP_TOP 0x80a
283#define mmMC_VM_AGP_BOT 0x80b
284#define mmMC_VM_AGP_BASE 0x80c
285#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d
286#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e
287#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f
288#define mmMC_VM_DC_WRITE_CNTL 0x810
289#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811
290#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812
291#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813
292#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814
293#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815
294#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816
295#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817
296#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818
297#define mmMC_VM_MX_L1_TLB_CNTL 0x819
298#define mmMC_VM_FB_OFFSET 0x81a
299#define mmMC_VM_STEERING 0x81b
300#define mmMC_SHARED_CHREMAP2 0x81c
301#define mmMC_SHARED_VF_ENABLE 0x81d
302#define mmMC_SHARED_VIRT_RESET_REQ 0x81e
303#define mmMC_SHARED_ACTIVE_FCN_ID 0x81f
304#define mmMC_CONFIG_MCD 0x828
305#define mmMC_CG_CONFIG_MCD 0x829
306#define mmMC_MEM_POWER_LS 0x82a
307#define mmMC_SHARED_BLACKOUT_CNTL 0x82b
308#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891
309#define mmMC_VM_MB_L1_TLB1_DEBUG 0x892
310#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893
311#define mmMC_VM_MB_L1_TLB0_STATUS 0x895
312#define mmMC_VM_MB_L1_TLB1_STATUS 0x896
313#define mmMC_VM_MB_L1_TLB2_STATUS 0x897
314#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1
315#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5
316#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6
317#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998
318#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999
319#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a
320#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b
321#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c
322#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d
323#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4
324#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7
325#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8
326#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd
327#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce
328#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf
329#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0
330#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1
331#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2
332#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3
333#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4
334#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5
335#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6
336#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7
337#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8
338#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9
339#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da
340#define mmMC_XPB_RTR_DEST_MAP0 0x8db
341#define mmMC_XPB_RTR_DEST_MAP1 0x8dc
342#define mmMC_XPB_RTR_DEST_MAP2 0x8dd
343#define mmMC_XPB_RTR_DEST_MAP3 0x8de
344#define mmMC_XPB_RTR_DEST_MAP4 0x8df
345#define mmMC_XPB_RTR_DEST_MAP5 0x8e0
346#define mmMC_XPB_RTR_DEST_MAP6 0x8e1
347#define mmMC_XPB_RTR_DEST_MAP7 0x8e2
348#define mmMC_XPB_RTR_DEST_MAP8 0x8e3
349#define mmMC_XPB_RTR_DEST_MAP9 0x8e4
350#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5
351#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6
352#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7
353#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8
354#define mmMC_XPB_CLG_CFG0 0x8e9
355#define mmMC_XPB_CLG_CFG1 0x8ea
356#define mmMC_XPB_CLG_CFG2 0x8eb
357#define mmMC_XPB_CLG_CFG3 0x8ec
358#define mmMC_XPB_CLG_CFG4 0x8ed
359#define mmMC_XPB_CLG_CFG5 0x8ee
360#define mmMC_XPB_CLG_CFG6 0x8ef
361#define mmMC_XPB_CLG_CFG7 0x8f0
362#define mmMC_XPB_CLG_CFG8 0x8f1
363#define mmMC_XPB_CLG_CFG9 0x8f2
364#define mmMC_XPB_CLG_CFG10 0x8f3
365#define mmMC_XPB_CLG_CFG11 0x8f4
366#define mmMC_XPB_CLG_CFG12 0x8f5
367#define mmMC_XPB_CLG_CFG13 0x8f6
368#define mmMC_XPB_CLG_CFG14 0x8f7
369#define mmMC_XPB_CLG_CFG15 0x8f8
370#define mmMC_XPB_CLG_CFG16 0x8f9
371#define mmMC_XPB_CLG_CFG17 0x8fa
372#define mmMC_XPB_CLG_CFG18 0x8fb
373#define mmMC_XPB_CLG_CFG19 0x8fc
374#define mmMC_XPB_CLG_EXTRA 0x8fd
375#define mmMC_XPB_LB_ADDR 0x8fe
376#define mmMC_XPB_UNC_THRESH_HST 0x8ff
377#define mmMC_XPB_UNC_THRESH_SID 0x900
378#define mmMC_XPB_WCB_STS 0x901
379#define mmMC_XPB_WCB_CFG 0x902
380#define mmMC_XPB_P2P_BAR_CFG 0x903
381#define mmMC_XPB_P2P_BAR0 0x904
382#define mmMC_XPB_P2P_BAR1 0x905
383#define mmMC_XPB_P2P_BAR2 0x906
384#define mmMC_XPB_P2P_BAR3 0x907
385#define mmMC_XPB_P2P_BAR4 0x908
386#define mmMC_XPB_P2P_BAR5 0x909
387#define mmMC_XPB_P2P_BAR6 0x90a
388#define mmMC_XPB_P2P_BAR7 0x90b
389#define mmMC_XPB_P2P_BAR_SETUP 0x90c
390#define mmMC_XPB_P2P_BAR_DEBUG 0x90d
391#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e
392#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f
393#define mmMC_XPB_PEER_SYS_BAR0 0x910
394#define mmMC_XPB_PEER_SYS_BAR1 0x911
395#define mmMC_XPB_PEER_SYS_BAR2 0x912
396#define mmMC_XPB_PEER_SYS_BAR3 0x913
397#define mmMC_XPB_PEER_SYS_BAR4 0x914
398#define mmMC_XPB_PEER_SYS_BAR5 0x915
399#define mmMC_XPB_PEER_SYS_BAR6 0x916
400#define mmMC_XPB_PEER_SYS_BAR7 0x917
401#define mmMC_XPB_PEER_SYS_BAR8 0x918
402#define mmMC_XPB_PEER_SYS_BAR9 0x919
403#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a
404#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b
405#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c
406#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d
407#define mmMC_XPB_CLK_GAT 0x91e
408#define mmMC_XPB_INTF_CFG 0x91f
409#define mmMC_XPB_INTF_STS 0x920
410#define mmMC_XPB_PIPE_STS 0x921
411#define mmMC_XPB_SUB_CTRL 0x922
412#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923
413#define mmMC_XPB_PERF_KNOBS 0x924
414#define mmMC_XPB_STICKY 0x925
415#define mmMC_XPB_STICKY_W1C 0x926
416#define mmMC_XPB_MISC_CFG 0x927
417#define mmMC_XPB_CLG_CFG20 0x928
418#define mmMC_XPB_CLG_CFG21 0x929
419#define mmMC_XPB_CLG_CFG22 0x92a
420#define mmMC_XPB_CLG_CFG23 0x92b
421#define mmMC_XPB_CLG_CFG24 0x92c
422#define mmMC_XPB_CLG_CFG25 0x92d
423#define mmMC_XPB_CLG_CFG26 0x92e
424#define mmMC_XPB_CLG_CFG27 0x92f
425#define mmMC_XPB_CLG_CFG28 0x930
426#define mmMC_XPB_CLG_CFG29 0x931
427#define mmMC_XPB_CLG_CFG30 0x932
428#define mmMC_XPB_CLG_CFG31 0x933
429#define mmMC_XPB_INTF_CFG2 0x934
430#define mmMC_XPB_CLG_EXTRA_RD 0x935
431#define mmMC_XPB_CLG_CFG32 0x936
432#define mmMC_XPB_CLG_CFG33 0x937
433#define mmMC_XPB_CLG_CFG34 0x938
434#define mmMC_XPB_CLG_CFG35 0x939
435#define mmMC_XPB_CLG_CFG36 0x93a
436#define mmMC_XBAR_ADDR_DEC 0xc80
437#define mmMC_XBAR_REMOTE 0xc81
438#define mmMC_XBAR_WRREQ_CREDIT 0xc82
439#define mmMC_XBAR_RDREQ_CREDIT 0xc83
440#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84
441#define mmMC_XBAR_WRRET_CREDIT1 0xc85
442#define mmMC_XBAR_WRRET_CREDIT2 0xc86
443#define mmMC_XBAR_RDRET_CREDIT1 0xc87
444#define mmMC_XBAR_RDRET_CREDIT2 0xc88
445#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89
446#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a
447#define mmMC_XBAR_CHTRIREMAP 0xc8b
448#define mmMC_XBAR_TWOCHAN 0xc8c
449#define mmMC_XBAR_ARB 0xc8d
450#define mmMC_XBAR_ARB_MAX_BURST 0xc8e
451#define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f
452#define mmMC_XBAR_FIFO_MON_CNTL1 0xc90
453#define mmMC_XBAR_FIFO_MON_CNTL2 0xc91
454#define mmMC_XBAR_FIFO_MON_RSLT0 0xc92
455#define mmMC_XBAR_FIFO_MON_RSLT1 0xc93
456#define mmMC_XBAR_FIFO_MON_RSLT2 0xc94
457#define mmMC_XBAR_FIFO_MON_RSLT3 0xc95
458#define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96
459#define mmMC_XBAR_SPARE0 0xc97
460#define mmMC_XBAR_SPARE1 0xc98
461#define mmMC_CITF_PERFCOUNTER_LO 0x7a0
462#define mmMC_HUB_PERFCOUNTER_LO 0x7a1
463#define mmMC_RPB_PERFCOUNTER_LO 0x7a2
464#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3
465#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4
466#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5
467#define mmMC_ARB_PERFCOUNTER_LO 0x7a6
468#define mmATC_PERFCOUNTER_LO 0x7a7
469#define mmMC_CITF_PERFCOUNTER_HI 0x7a8
470#define mmMC_HUB_PERFCOUNTER_HI 0x7a9
471#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa
472#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab
473#define mmMC_RPB_PERFCOUNTER_HI 0x7ac
474#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad
475#define mmMC_ARB_PERFCOUNTER_HI 0x7ae
476#define mmATC_PERFCOUNTER_HI 0x7af
477#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0
478#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1
479#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2
480#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3
481#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4
482#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5
483#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6
484#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7
485#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8
486#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9
487#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba
488#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb
489#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc
490#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd
491#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be
492#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf
493#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0
494#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1
495#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2
496#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3
497#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4
498#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5
499#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6
500#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7
501#define mmATC_PERFCOUNTER0_CFG 0x7c8
502#define mmATC_PERFCOUNTER1_CFG 0x7c9
503#define mmATC_PERFCOUNTER2_CFG 0x7ca
504#define mmATC_PERFCOUNTER3_CFG 0x7cb
505#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc
506#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd
507#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce
508#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf
509#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0
510#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1
511#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2
512#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3
513#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4
514#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5
515#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6
516#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7
517#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8
518#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9
519#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da
520#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0
521#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1
522#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2
523#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3
524#define mmATC_VM_APERTURE0_CNTL 0xcc4
525#define mmATC_VM_APERTURE1_CNTL 0xcc5
526#define mmATC_VM_APERTURE0_CNTL2 0xcc6
527#define mmATC_VM_APERTURE1_CNTL2 0xcc7
528#define mmATC_ATS_CNTL 0xcc9
529#define mmATC_ATS_DEBUG 0xcca
530#define mmATC_ATS_FAULT_DEBUG 0xccb
531#define mmATC_ATS_STATUS 0xccc
532#define mmATC_ATS_FAULT_CNTL 0xccd
533#define mmATC_ATS_FAULT_STATUS_INFO 0xcce
534#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf
535#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0
536#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1
537#define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2
538#define mmATC_MISC_CG 0xcd4
539#define mmATC_L2_CNTL 0xcd5
540#define mmATC_L2_CNTL2 0xcd6
541#define mmATC_L2_DEBUG 0xcd7
542#define mmATC_L2_DEBUG2 0xcd8
543#define mmATC_L2_CACHE_DATA0 0xcd9
544#define mmATC_L2_CACHE_DATA1 0xcda
545#define mmATC_L2_CACHE_DATA2 0xcdb
546#define mmATC_L1_CNTL 0xcdc
547#define mmATC_L1_ADDRESS_OFFSET 0xcdd
548#define mmATC_L1RD_DEBUG_TLB 0xcde
549#define mmATC_L1WR_DEBUG_TLB 0xcdf
550#define mmATC_L1RD_STATUS 0xce0
551#define mmATC_L1WR_STATUS 0xce1
552#define mmATC_L1RD_DEBUG2_TLB 0xce2
553#define mmATC_L1WR_DEBUG2_TLB 0xce3
554#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6
555#define mmATC_VMID0_PASID_MAPPING 0xce7
556#define mmATC_VMID1_PASID_MAPPING 0xce8
557#define mmATC_VMID2_PASID_MAPPING 0xce9
558#define mmATC_VMID3_PASID_MAPPING 0xcea
559#define mmATC_VMID4_PASID_MAPPING 0xceb
560#define mmATC_VMID5_PASID_MAPPING 0xcec
561#define mmATC_VMID6_PASID_MAPPING 0xced
562#define mmATC_VMID7_PASID_MAPPING 0xcee
563#define mmATC_VMID8_PASID_MAPPING 0xcef
564#define mmATC_VMID9_PASID_MAPPING 0xcf0
565#define mmATC_VMID10_PASID_MAPPING 0xcf1
566#define mmATC_VMID11_PASID_MAPPING 0xcf2
567#define mmATC_VMID12_PASID_MAPPING 0xcf3
568#define mmATC_VMID13_PASID_MAPPING 0xcf4
569#define mmATC_VMID14_PASID_MAPPING 0xcf5
570#define mmATC_VMID15_PASID_MAPPING 0xcf6
571#define mmATC_ATS_VMID_STATUS 0xd07
572#define mmATC_ATS_SMU_STATUS 0xd08
573#define mmATC_L2_CNTL3 0xd09
574#define mmATC_L2_STATUS 0xd0a
575#define mmATC_L2_STATUS2 0xd0b
576#define mmGMCON_RENG_RAM_INDEX 0xd40
577#define mmGMCON_RENG_RAM_DATA 0xd41
578#define mmGMCON_RENG_EXECUTE 0xd42
579#define mmGMCON_MISC 0xd43
580#define mmGMCON_MISC2 0xd44
581#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45
582#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46
583#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47
584#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48
585#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49
586#define mmGMCON_PERF_MON_CNTL0 0xd4a
587#define mmGMCON_PERF_MON_CNTL1 0xd4b
588#define mmGMCON_PERF_MON_RSLT0 0xd4c
589#define mmGMCON_PERF_MON_RSLT1 0xd4d
590#define mmGMCON_PGFSM_CONFIG 0xd4e
591#define mmGMCON_PGFSM_WRITE 0xd4f
592#define mmGMCON_PGFSM_READ 0xd50
593#define mmGMCON_MISC3 0xd51
594#define mmGMCON_MASK 0xd52
595#define mmGMCON_LPT_TARGET 0xd53
596#define mmGMCON_DEBUG 0xd5f
597#define mmVM_L2_CNTL 0x500
598#define mmVM_L2_CNTL2 0x501
599#define mmVM_L2_CNTL3 0x502
600#define mmVM_L2_STATUS 0x503
601#define mmVM_CONTEXT0_CNTL 0x504
602#define mmVM_CONTEXT1_CNTL 0x505
603#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506
604#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507
605#define mmVM_CONTEXT0_CNTL2 0x50c
606#define mmVM_CONTEXT1_CNTL2 0x50d
607#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e
608#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f
609#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510
610#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511
611#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512
612#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
613#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
614#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
615#define mmVM_INVALIDATE_REQUEST 0x51e
616#define mmVM_INVALIDATE_RESPONSE 0x51f
617#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
618#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
619#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
620#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f
621#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530
622#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531
623#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532
624#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533
625#define mmVM_PRT_CNTL 0x534
626#define mmVM_CONTEXTS_DISABLE 0x535
627#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536
628#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537
629#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538
630#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539
631#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e
632#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f
633#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546
634#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547
635#define mmVM_FAULT_CLIENT_ID 0x54e
636#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
637#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550
638#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551
639#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552
640#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553
641#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554
642#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555
643#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
644#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
645#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
646#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
647#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
648#define mmVM_DEBUG 0x56f
649#define mmVM_L2_CG 0x570
650#define mmVM_L2_BANK_SELECT_MASKA 0x572
651#define mmVM_L2_BANK_SELECT_MASKB 0x573
652#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575
653#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576
654#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577
655#define mmVM_L2_CNTL4 0x578
656#define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579
657#define mmVM_L2_BANK_SELECT_RESERVED_CID2 0x57a
658#define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980
659#define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981
660#define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982
661#define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983
662#define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984
663#define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985
664#define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986
665#define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987
666#define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988
667#define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989
668#define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a
669#define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b
670#define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c
671#define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d
672#define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e
673#define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f
674#define mmMC_VM_NB_MMIOBASE 0xf990
675#define mmMC_VM_NB_MMIOLIMIT 0xf991
676#define mmMC_VM_NB_PCI_CTRL 0xf992
677#define mmMC_VM_NB_PCI_ARB 0xf993
678#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994
679#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995
680#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996
681#define mmMC_VM_NB_TOP_OF_DRAM3 0xf997
682#define mmMC_VM_MARC_BASE_LO_0 0xf998
683#define mmMC_VM_MARC_BASE_LO_1 0xf99e
684#define mmMC_VM_MARC_BASE_LO_2 0xf9a4
685#define mmMC_VM_MARC_BASE_LO_3 0xf9aa
686#define mmMC_VM_MARC_BASE_HI_0 0xf999
687#define mmMC_VM_MARC_BASE_HI_1 0xf99f
688#define mmMC_VM_MARC_BASE_HI_2 0xf9a5
689#define mmMC_VM_MARC_BASE_HI_3 0xf9ab
690#define mmMC_VM_MARC_RELOC_LO_0 0xf99a
691#define mmMC_VM_MARC_RELOC_LO_1 0xf9a0
692#define mmMC_VM_MARC_RELOC_LO_2 0xf9a6
693#define mmMC_VM_MARC_RELOC_LO_3 0xf9ac
694#define mmMC_VM_MARC_RELOC_HI_0 0xf99b
695#define mmMC_VM_MARC_RELOC_HI_1 0xf9a1
696#define mmMC_VM_MARC_RELOC_HI_2 0xf9a7
697#define mmMC_VM_MARC_RELOC_HI_3 0xf9ad
698#define mmMC_VM_MARC_LEN_LO_0 0xf99c
699#define mmMC_VM_MARC_LEN_LO_1 0xf9a2
700#define mmMC_VM_MARC_LEN_LO_2 0xf9a8
701#define mmMC_VM_MARC_LEN_LO_3 0xf9ae
702#define mmMC_VM_MARC_LEN_HI_0 0xf99d
703#define mmMC_VM_MARC_LEN_HI_1 0xf9a3
704#define mmMC_VM_MARC_LEN_HI_2 0xf9a9
705#define mmMC_VM_MARC_LEN_HI_3 0xf9af
706#define mmMC_VM_MARC_CNTL 0xf9b0
707#define mmMC_VM_MB_L1_TLS0_CNTL0 0xf9b1
708#define mmMC_VM_MB_L1_TLS0_CNTL1 0xf9b4
709#define mmMC_VM_MB_L1_TLS0_CNTL2 0xf9b7
710#define mmMC_VM_MB_L1_TLS0_CNTL3 0xf9ba
711#define mmMC_VM_MB_L1_TLS0_CNTL4 0xf9bd
712#define mmMC_VM_MB_L1_TLS0_CNTL5 0xf9c0
713#define mmMC_VM_MB_L1_TLS0_CNTL6 0xf9c3
714#define mmMC_VM_MB_L1_TLS0_CNTL7 0xf9c6
715#define mmMC_VM_MB_L1_TLS0_CNTL8 0xf9c9
716#define mmMC_VM_MB_L1_TLS0_START_ADDR0 0xf9b2
717#define mmMC_VM_MB_L1_TLS0_START_ADDR1 0xf9b5
718#define mmMC_VM_MB_L1_TLS0_START_ADDR2 0xf9b8
719#define mmMC_VM_MB_L1_TLS0_START_ADDR3 0xf9bb
720#define mmMC_VM_MB_L1_TLS0_START_ADDR4 0xf9be
721#define mmMC_VM_MB_L1_TLS0_START_ADDR5 0xf9c1
722#define mmMC_VM_MB_L1_TLS0_START_ADDR6 0xf9c4
723#define mmMC_VM_MB_L1_TLS0_START_ADDR7 0xf9c7
724#define mmMC_VM_MB_L1_TLS0_START_ADDR8 0xf9ca
725#define mmMC_VM_MB_L1_TLS0_END_ADDR0 0xf9b3
726#define mmMC_VM_MB_L1_TLS0_END_ADDR1 0xf9b6
727#define mmMC_VM_MB_L1_TLS0_END_ADDR2 0xf9b9
728#define mmMC_VM_MB_L1_TLS0_END_ADDR3 0xf9bc
729#define mmMC_VM_MB_L1_TLS0_END_ADDR4 0xf9bf
730#define mmMC_VM_MB_L1_TLS0_END_ADDR5 0xf9c2
731#define mmMC_VM_MB_L1_TLS0_END_ADDR6 0xf9c5
732#define mmMC_VM_MB_L1_TLS0_END_ADDR7 0xf9c8
733#define mmMC_VM_MB_L1_TLS0_END_ADDR8 0xf9cb
734#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS 0xf9cc
735#define mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR 0xf9cd
736#define mmMC_SEQ_CNTL 0xa25
737#define mmMC_SEQ_CNTL_2 0xad4
738#define mmMC_SEQ_DRAM 0xa26
739#define mmMC_SEQ_DRAM_2 0xa27
740#define mmMC_SEQ_RAS_TIMING 0xa28
741#define mmMC_SEQ_CAS_TIMING 0xa29
742#define mmMC_SEQ_MISC_TIMING 0xa2a
743#define mmMC_SEQ_MISC_TIMING2 0xa2b
744#define mmMC_SEQ_PMG_TIMING 0xa2c
745#define mmMC_SEQ_RD_CTL_D0 0xa2d
746#define mmMC_SEQ_RD_CTL_D1 0xa2e
747#define mmMC_SEQ_WR_CTL_D0 0xa2f
748#define mmMC_SEQ_WR_CTL_D1 0xa30
749#define mmMC_SEQ_WR_CTL_2 0xad5
750#define mmMC_SEQ_CMD 0xa31
751#define mmMC_PMG_CMD_EMRS 0xa83
752#define mmMC_PMG_CMD_MRS 0xaab
753#define mmMC_PMG_CMD_MRS1 0xad1
754#define mmMC_PMG_CMD_MRS2 0xad7
755#define mmMC_PMG_CFG 0xa84
756#define mmMC_PMG_AUTO_CMD 0xa34
757#define mmMC_PMG_AUTO_CFG 0xa35
758#define mmMC_IMP_CNTL 0xa36
759#define mmMC_IMP_DEBUG 0xa37
760#define mmMC_IMP_STATUS 0xa38
761#define mmMC_IMP_DQ_STATUS 0xabc
762#define mmMC_SEQ_WCDR_CTRL 0xa39
763#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a
764#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b
765#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe
766#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff
767#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c
768#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d
769#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e
770#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f
771#define mmMC_SEQ_TRAIN_TIMING 0xa40
772#define mmMC_TRAIN_EDCCDR_R_D0 0xa41
773#define mmMC_TRAIN_EDCCDR_R_D1 0xa42
774#define mmMC_TRAIN_PRBSERR_0_D0 0xa43
775#define mmMC_TRAIN_PRBSERR_1_D0 0xa44
776#define mmMC_TRAIN_PRBSERR_2_D0 0xafb
777#define mmMC_TRAIN_EDC_STATUS_D0 0xa45
778#define mmMC_TRAIN_PRBSERR_0_D1 0xa46
779#define mmMC_TRAIN_PRBSERR_1_D1 0xa47
780#define mmMC_TRAIN_PRBSERR_2_D1 0xafc
781#define mmMC_TRAIN_EDC_STATUS_D1 0xa48
782#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49
783#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a
784#define mmMC_IO_TXCNTL_APHY_D0 0xa4b
785#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c
786#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf
787#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d
788#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0
789#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e
790#define mmMC_IO_APHY_STR_CNTL_D0 0xa97
791#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f
792#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50
793#define mmMC_IO_TXCNTL_APHY_D1 0xa51
794#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52
795#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1
796#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53
797#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2
798#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54
799#define mmMC_IO_APHY_STR_CNTL_D1 0xa98
800#define mmMC_IO_CDRCNTL_D0 0xa55
801#define mmMC_IO_CDRCNTL1_D0 0xadd
802#define mmMC_IO_CDRCNTL2_D0 0xae4
803#define mmMC_IO_CDRCNTL_D1 0xa56
804#define mmMC_IO_CDRCNTL1_D1 0xade
805#define mmMC_IO_CDRCNTL2_D1 0xae5
806#define mmMC_SEQ_FIFO_CTL 0xa57
807#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58
808#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59
809#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a
810#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b
811#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c
812#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d
813#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e
814#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60
815#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61
816#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62
817#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63
818#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64
819#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65
820#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66
821#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67
822#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68
823#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69
824#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a
825#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b
826#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c
827#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d
828#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e
829#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f
830#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70
831#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71
832#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72
833#define mmMC_IO_PAD_CNTL 0xa73
834#define mmMC_IO_PAD_CNTL_D0 0xa74
835#define mmMC_IO_PAD_CNTL_D1 0xa75
836#define mmMC_NPL_STATUS 0xa76
837#define mmMC_BIST_CMD_CNTL 0xa8e
838#define mmMC_BIST_CNTL 0xa05
839#define mmMC_BIST_AUTO_CNTL 0xa06
840#define mmMC_BIST_DIR_CNTL 0xa07
841#define mmMC_BIST_SADDR 0xa08
842#define mmMC_BIST_EADDR 0xa09
843#define mmMC_BIST_CMP_CNTL 0xa8d
844#define mmMC_BIST_CMP_CNTL_2 0xab6
845#define mmMC_BIST_DATA_WORD0 0xa0a
846#define mmMC_BIST_DATA_WORD1 0xa0b
847#define mmMC_BIST_DATA_WORD2 0xa0c
848#define mmMC_BIST_DATA_WORD3 0xa0d
849#define mmMC_BIST_DATA_WORD4 0xa0e
850#define mmMC_BIST_DATA_WORD5 0xa0f
851#define mmMC_BIST_DATA_WORD6 0xa10
852#define mmMC_BIST_DATA_WORD7 0xa11
853#define mmMC_BIST_DATA_MASK 0xa12
854#define mmMC_BIST_MISMATCH_ADDR 0xa13
855#define mmMC_BIST_RDATA_WORD0 0xa14
856#define mmMC_BIST_RDATA_WORD1 0xa15
857#define mmMC_BIST_RDATA_WORD2 0xa16
858#define mmMC_BIST_RDATA_WORD3 0xa17
859#define mmMC_BIST_RDATA_WORD4 0xa18
860#define mmMC_BIST_RDATA_WORD5 0xa19
861#define mmMC_BIST_RDATA_WORD6 0xa1a
862#define mmMC_BIST_RDATA_WORD7 0xa1b
863#define mmMC_BIST_RDATA_MASK 0xa1c
864#define mmMC_BIST_RDATA_EDC 0xa1d
865#define mmMC_SEQ_PERF_CNTL 0xa77
866#define mmMC_SEQ_PERF_CNTL_1 0xafd
867#define mmMC_SEQ_PERF_SEQ_CTL 0xa78
868#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79
869#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a
870#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b
871#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c
872#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9
873#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada
874#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb
875#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc
876#define mmMC_SEQ_STATUS_M 0xa7d
877#define mmMC_SEQ_STATUS_S 0xa20
878#define mmMC_CG_DATAPORT 0xa21
879#define mmMC_SEQ_VENDOR_ID_I0 0xa7e
880#define mmMC_SEQ_VENDOR_ID_I1 0xa7f
881#define mmMC_SEQ_MISC0 0xa80
882#define mmMC_SEQ_MISC1 0xa81
883#define mmMC_SEQ_RESERVE_0_S 0xa1e
884#define mmMC_SEQ_RESERVE_1_S 0xa1f
885#define mmMC_SEQ_RESERVE_M 0xa82
886#define mmMC_SEQ_IO_RESERVE_D0 0xab7
887#define mmMC_SEQ_IO_RESERVE_D1 0xab8
888#define mmMC_SEQ_SUP_CNTL 0xa32
889#define mmMC_SEQ_SUP_PGM 0xa33
890#define mmMC_SEQ_SUP_GP0_STAT 0xa8f
891#define mmMC_SEQ_SUP_GP1_STAT 0xa90
892#define mmMC_SEQ_SUP_GP2_STAT 0xa85
893#define mmMC_SEQ_SUP_GP3_STAT 0xa86
894#define mmMC_SEQ_SUP_IR_STAT 0xa87
895#define mmMC_SEQ_SUP_DEC_STAT 0xa88
896#define mmMC_SEQ_SUP_PGM_STAT 0xa89
897#define mmMC_SEQ_SUP_R_PGM 0xa8a
898#define mmMC_SEQ_MISC3 0xa8b
899#define mmMC_SEQ_MISC4 0xa8c
900#define mmMC_SEQ_MISC5 0xa95
901#define mmMC_SEQ_MISC6 0xa96
902#define mmMC_SEQ_MISC7 0xa99
903#define mmMC_SEQ_MISC8 0xa5f
904#define mmMC_SEQ_MISC9 0xae7
905#define mmMC_SEQ_CG 0xa9a
906#define mmMC_SEQ_BYTE_REMAP_D0 0xa93
907#define mmMC_SEQ_BYTE_REMAP_D1 0xa94
908#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3
909#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4
910#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5
911#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6
912#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7
913#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8
914#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9
915#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa
916#define mmMC_SEQ_RAS_TIMING_LP 0xa9b
917#define mmMC_SEQ_CAS_TIMING_LP 0xa9c
918#define mmMC_SEQ_MISC_TIMING_LP 0xa9d
919#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e
920#define mmMC_SEQ_RD_CTL_D0_LP 0xac7
921#define mmMC_SEQ_RD_CTL_D1_LP 0xac8
922#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f
923#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0
924#define mmMC_SEQ_WR_CTL_2_LP 0xad6
925#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1
926#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2
927#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2
928#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8
929#define mmMC_SEQ_PMG_TIMING_LP 0xad3
930#define mmMC_SEQ_IO_RWORD0 0xaac
931#define mmMC_SEQ_IO_RWORD1 0xaad
932#define mmMC_SEQ_IO_RWORD2 0xaae
933#define mmMC_SEQ_IO_RWORD3 0xaaf
934#define mmMC_SEQ_IO_RWORD4 0xab0
935#define mmMC_SEQ_IO_RWORD5 0xab1
936#define mmMC_SEQ_IO_RWORD6 0xab2
937#define mmMC_SEQ_IO_RWORD7 0xab3
938#define mmMC_SEQ_IO_RDBI 0xab4
939#define mmMC_SEQ_IO_REDC 0xab5
940#define mmMC_SEQ_TCG_CNTL 0xabd
941#define mmMC_SEQ_TSM_CTRL 0xabe
942#define mmMC_SEQ_TSM_GCNT 0xabf
943#define mmMC_SEQ_TSM_OCNT 0xac0
944#define mmMC_SEQ_TSM_NCNT 0xac1
945#define mmMC_SEQ_TSM_BCNT 0xac2
946#define mmMC_SEQ_TSM_FLAG 0xac3
947#define mmMC_SEQ_TSM_UPDATE 0xac4
948#define mmMC_SEQ_TSM_EDC 0xac5
949#define mmMC_SEQ_TSM_DBI 0xac6
950#define mmMC_SEQ_TSM_WCDR 0xae3
951#define mmMC_SEQ_TSM_MISC 0xae6
952#define mmMC_SEQ_TIMER_WR 0xac9
953#define mmMC_SEQ_TIMER_RD 0xaca
954#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb
955#define mmMC_PHY_TIMING_D0 0xacc
956#define mmMC_PHY_TIMING_D1 0xacd
957#define mmMC_PHY_TIMING_2 0xace
958#define mmMC_SEQ_MPLL_OVERRIDE 0xa22
959#define mmMCLK_PWRMGT_CNTL 0xae8
960#define mmDLL_CNTL 0xae9
961#define mmMPLL_SEQ_UCODE_1 0xaea
962#define mmMPLL_SEQ_UCODE_2 0xaeb
963#define mmMPLL_CNTL_MODE 0xaec
964#define mmMPLL_FUNC_CNTL 0xaed
965#define mmMPLL_FUNC_CNTL_1 0xaee
966#define mmMPLL_FUNC_CNTL_2 0xaef
967#define mmMPLL_AD_FUNC_CNTL 0xaf0
968#define mmMPLL_DQ_FUNC_CNTL 0xaf1
969#define mmMPLL_TIME 0xaf2
970#define mmMPLL_SS1 0xaf3
971#define mmMPLL_SS2 0xaf4
972#define mmMPLL_CONTROL 0xaf5
973#define mmMPLL_AD_STATUS 0xaf6
974#define mmMPLL_DQ_0_0_STATUS 0xaf7
975#define mmMPLL_DQ_0_1_STATUS 0xaf8
976#define mmMPLL_DQ_1_0_STATUS 0xaf9
977#define mmMPLL_DQ_1_1_STATUS 0xafa
978#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9
979#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba
980#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb
981#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf
982#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0
983#define ixMC_TSM_DEBUG_GCNT 0x0
984#define ixMC_TSM_DEBUG_FLAG 0x1
985#define ixMC_TSM_DEBUG_MISC 0x2
986#define ixMC_TSM_DEBUG_BCNT0 0x3
987#define ixMC_TSM_DEBUG_BCNT1 0x4
988#define ixMC_TSM_DEBUG_BCNT2 0x5
989#define ixMC_TSM_DEBUG_BCNT3 0x6
990#define ixMC_TSM_DEBUG_BCNT4 0x7
991#define ixMC_TSM_DEBUG_BCNT5 0x8
992#define ixMC_TSM_DEBUG_BCNT6 0x9
993#define ixMC_TSM_DEBUG_BCNT7 0xa
994#define ixMC_TSM_DEBUG_BCNT8 0xb
995#define ixMC_TSM_DEBUG_BCNT9 0xc
996#define ixMC_TSM_DEBUG_BCNT10 0xd
997#define ixMC_TSM_DEBUG_ST01 0x10
998#define ixMC_TSM_DEBUG_ST23 0x11
999#define ixMC_TSM_DEBUG_ST45 0x12
1000#define ixMC_TSM_DEBUG_BKPT 0x13
1001#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91
1002#define mmMC_SEQ_IO_DEBUG_DATA 0xa92
1003#define ixMC_IO_DEBUG_UP_0 0x0
1004#define ixMC_IO_DEBUG_UP_1 0x1
1005#define ixMC_IO_DEBUG_UP_2 0x2
1006#define ixMC_IO_DEBUG_UP_3 0x3
1007#define ixMC_IO_DEBUG_UP_4 0x4
1008#define ixMC_IO_DEBUG_UP_5 0x5
1009#define ixMC_IO_DEBUG_UP_6 0x6
1010#define ixMC_IO_DEBUG_UP_7 0x7
1011#define ixMC_IO_DEBUG_UP_8 0x8
1012#define ixMC_IO_DEBUG_UP_9 0x9
1013#define ixMC_IO_DEBUG_UP_10 0xa
1014#define ixMC_IO_DEBUG_UP_11 0xb
1015#define ixMC_IO_DEBUG_UP_12 0xc
1016#define ixMC_IO_DEBUG_UP_13 0xd
1017#define ixMC_IO_DEBUG_UP_14 0xe
1018#define ixMC_IO_DEBUG_UP_15 0xf
1019#define ixMC_IO_DEBUG_UP_16 0x10
1020#define ixMC_IO_DEBUG_UP_17 0x11
1021#define ixMC_IO_DEBUG_UP_18 0x12
1022#define ixMC_IO_DEBUG_UP_19 0x13
1023#define ixMC_IO_DEBUG_UP_20 0x14
1024#define ixMC_IO_DEBUG_UP_21 0x15
1025#define ixMC_IO_DEBUG_UP_22 0x16
1026#define ixMC_IO_DEBUG_UP_23 0x17
1027#define ixMC_IO_DEBUG_UP_24 0x18
1028#define ixMC_IO_DEBUG_UP_25 0x19
1029#define ixMC_IO_DEBUG_UP_26 0x1a
1030#define ixMC_IO_DEBUG_UP_27 0x1b
1031#define ixMC_IO_DEBUG_UP_28 0x1c
1032#define ixMC_IO_DEBUG_UP_29 0x1d
1033#define ixMC_IO_DEBUG_UP_30 0x1e
1034#define ixMC_IO_DEBUG_UP_31 0x1f
1035#define ixMC_IO_DEBUG_UP_32 0x20
1036#define ixMC_IO_DEBUG_UP_33 0x21
1037#define ixMC_IO_DEBUG_UP_34 0x22
1038#define ixMC_IO_DEBUG_UP_35 0x23
1039#define ixMC_IO_DEBUG_UP_36 0x24
1040#define ixMC_IO_DEBUG_UP_37 0x25
1041#define ixMC_IO_DEBUG_UP_38 0x26
1042#define ixMC_IO_DEBUG_UP_39 0x27
1043#define ixMC_IO_DEBUG_UP_40 0x28
1044#define ixMC_IO_DEBUG_UP_41 0x29
1045#define ixMC_IO_DEBUG_UP_42 0x2a
1046#define ixMC_IO_DEBUG_UP_43 0x2b
1047#define ixMC_IO_DEBUG_UP_44 0x2c
1048#define ixMC_IO_DEBUG_UP_45 0x2d
1049#define ixMC_IO_DEBUG_UP_46 0x2e
1050#define ixMC_IO_DEBUG_UP_47 0x2f
1051#define ixMC_IO_DEBUG_UP_48 0x30
1052#define ixMC_IO_DEBUG_UP_49 0x31
1053#define ixMC_IO_DEBUG_UP_50 0x32
1054#define ixMC_IO_DEBUG_UP_51 0x33
1055#define ixMC_IO_DEBUG_UP_52 0x34
1056#define ixMC_IO_DEBUG_UP_53 0x35
1057#define ixMC_IO_DEBUG_UP_54 0x36
1058#define ixMC_IO_DEBUG_UP_55 0x37
1059#define ixMC_IO_DEBUG_UP_56 0x38
1060#define ixMC_IO_DEBUG_UP_57 0x39
1061#define ixMC_IO_DEBUG_UP_58 0x3a
1062#define ixMC_IO_DEBUG_UP_59 0x3b
1063#define ixMC_IO_DEBUG_UP_60 0x3c
1064#define ixMC_IO_DEBUG_UP_61 0x3d
1065#define ixMC_IO_DEBUG_UP_62 0x3e
1066#define ixMC_IO_DEBUG_UP_63 0x3f
1067#define ixMC_IO_DEBUG_UP_64 0x40
1068#define ixMC_IO_DEBUG_UP_65 0x41
1069#define ixMC_IO_DEBUG_UP_66 0x42
1070#define ixMC_IO_DEBUG_UP_67 0x43
1071#define ixMC_IO_DEBUG_UP_68 0x44
1072#define ixMC_IO_DEBUG_UP_69 0x45
1073#define ixMC_IO_DEBUG_UP_70 0x46
1074#define ixMC_IO_DEBUG_UP_71 0x47
1075#define ixMC_IO_DEBUG_UP_72 0x48
1076#define ixMC_IO_DEBUG_UP_73 0x49
1077#define ixMC_IO_DEBUG_UP_74 0x4a
1078#define ixMC_IO_DEBUG_UP_75 0x4b
1079#define ixMC_IO_DEBUG_UP_76 0x4c
1080#define ixMC_IO_DEBUG_UP_77 0x4d
1081#define ixMC_IO_DEBUG_UP_78 0x4e
1082#define ixMC_IO_DEBUG_UP_79 0x4f
1083#define ixMC_IO_DEBUG_UP_80 0x50
1084#define ixMC_IO_DEBUG_UP_81 0x51
1085#define ixMC_IO_DEBUG_UP_82 0x52
1086#define ixMC_IO_DEBUG_UP_83 0x53
1087#define ixMC_IO_DEBUG_UP_84 0x54
1088#define ixMC_IO_DEBUG_UP_85 0x55
1089#define ixMC_IO_DEBUG_UP_86 0x56
1090#define ixMC_IO_DEBUG_UP_87 0x57
1091#define ixMC_IO_DEBUG_UP_88 0x58
1092#define ixMC_IO_DEBUG_UP_89 0x59
1093#define ixMC_IO_DEBUG_UP_90 0x5a
1094#define ixMC_IO_DEBUG_UP_91 0x5b
1095#define ixMC_IO_DEBUG_UP_92 0x5c
1096#define ixMC_IO_DEBUG_UP_93 0x5d
1097#define ixMC_IO_DEBUG_UP_94 0x5e
1098#define ixMC_IO_DEBUG_UP_95 0x5f
1099#define ixMC_IO_DEBUG_UP_96 0x60
1100#define ixMC_IO_DEBUG_UP_97 0x61
1101#define ixMC_IO_DEBUG_UP_98 0x62
1102#define ixMC_IO_DEBUG_UP_99 0x63
1103#define ixMC_IO_DEBUG_UP_100 0x64
1104#define ixMC_IO_DEBUG_UP_101 0x65
1105#define ixMC_IO_DEBUG_UP_102 0x66
1106#define ixMC_IO_DEBUG_UP_103 0x67
1107#define ixMC_IO_DEBUG_UP_104 0x68
1108#define ixMC_IO_DEBUG_UP_105 0x69
1109#define ixMC_IO_DEBUG_UP_106 0x6a
1110#define ixMC_IO_DEBUG_UP_107 0x6b
1111#define ixMC_IO_DEBUG_UP_108 0x6c
1112#define ixMC_IO_DEBUG_UP_109 0x6d
1113#define ixMC_IO_DEBUG_UP_110 0x6e
1114#define ixMC_IO_DEBUG_UP_111 0x6f
1115#define ixMC_IO_DEBUG_UP_112 0x70
1116#define ixMC_IO_DEBUG_UP_113 0x71
1117#define ixMC_IO_DEBUG_UP_114 0x72
1118#define ixMC_IO_DEBUG_UP_115 0x73
1119#define ixMC_IO_DEBUG_UP_116 0x74
1120#define ixMC_IO_DEBUG_UP_117 0x75
1121#define ixMC_IO_DEBUG_UP_118 0x76
1122#define ixMC_IO_DEBUG_UP_119 0x77
1123#define ixMC_IO_DEBUG_UP_120 0x78
1124#define ixMC_IO_DEBUG_UP_121 0x79
1125#define ixMC_IO_DEBUG_UP_122 0x7a
1126#define ixMC_IO_DEBUG_UP_123 0x7b
1127#define ixMC_IO_DEBUG_UP_124 0x7c
1128#define ixMC_IO_DEBUG_UP_125 0x7d
1129#define ixMC_IO_DEBUG_UP_126 0x7e
1130#define ixMC_IO_DEBUG_UP_127 0x7f
1131#define ixMC_IO_DEBUG_UP_128 0x80
1132#define ixMC_IO_DEBUG_UP_129 0x81
1133#define ixMC_IO_DEBUG_UP_130 0x82
1134#define ixMC_IO_DEBUG_UP_131 0x83
1135#define ixMC_IO_DEBUG_UP_132 0x84
1136#define ixMC_IO_DEBUG_UP_133 0x85
1137#define ixMC_IO_DEBUG_UP_134 0x86
1138#define ixMC_IO_DEBUG_UP_135 0x87
1139#define ixMC_IO_DEBUG_UP_136 0x88
1140#define ixMC_IO_DEBUG_UP_137 0x89
1141#define ixMC_IO_DEBUG_UP_138 0x8a
1142#define ixMC_IO_DEBUG_UP_139 0x8b
1143#define ixMC_IO_DEBUG_UP_140 0x8c
1144#define ixMC_IO_DEBUG_UP_141 0x8d
1145#define ixMC_IO_DEBUG_UP_142 0x8e
1146#define ixMC_IO_DEBUG_UP_143 0x8f
1147#define ixMC_IO_DEBUG_UP_144 0x90
1148#define ixMC_IO_DEBUG_UP_145 0x91
1149#define ixMC_IO_DEBUG_UP_146 0x92
1150#define ixMC_IO_DEBUG_UP_147 0x93
1151#define ixMC_IO_DEBUG_UP_148 0x94
1152#define ixMC_IO_DEBUG_UP_149 0x95
1153#define ixMC_IO_DEBUG_UP_150 0x96
1154#define ixMC_IO_DEBUG_UP_151 0x97
1155#define ixMC_IO_DEBUG_UP_152 0x98
1156#define ixMC_IO_DEBUG_UP_153 0x99
1157#define ixMC_IO_DEBUG_UP_154 0x9a
1158#define ixMC_IO_DEBUG_UP_155 0x9b
1159#define ixMC_IO_DEBUG_UP_156 0x9c
1160#define ixMC_IO_DEBUG_UP_157 0x9d
1161#define ixMC_IO_DEBUG_UP_158 0x9e
1162#define ixMC_IO_DEBUG_UP_159 0x9f
1163#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0
1164#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1
1165#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2
1166#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3
1167#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4
1168#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5
1169#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6
1170#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7
1171#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8
1172#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9
1173#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa
1174#define ixMC_IO_DEBUG_CK_MISC_D0 0xab
1175#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac
1176#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad
1177#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae
1178#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf
1179#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0
1180#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1
1181#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2
1182#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3
1183#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4
1184#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5
1185#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6
1186#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7
1187#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8
1188#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9
1189#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba
1190#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb
1191#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc
1192#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd
1193#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe
1194#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf
1195#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0
1196#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1
1197#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2
1198#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3
1199#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4
1200#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5
1201#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6
1202#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7
1203#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8
1204#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9
1205#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca
1206#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb
1207#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc
1208#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd
1209#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce
1210#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf
1211#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0
1212#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1
1213#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2
1214#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3
1215#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4
1216#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5
1217#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6
1218#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7
1219#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8
1220#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9
1221#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda
1222#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb
1223#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc
1224#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd
1225#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde
1226#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf
1227#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0
1228#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1
1229#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2
1230#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3
1231#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4
1232#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5
1233#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6
1234#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7
1235#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8
1236#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9
1237#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea
1238#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb
1239#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec
1240#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed
1241#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee
1242#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef
1243#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0
1244#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1
1245#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2
1246#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3
1247#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4
1248#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5
1249#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6
1250#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7
1251#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8
1252#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9
1253#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa
1254#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb
1255#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc
1256#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd
1257#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe
1258#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff
1259#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100
1260#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101
1261#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102
1262#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103
1263#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104
1264#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105
1265#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106
1266#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107
1267#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108
1268#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109
1269#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a
1270#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b
1271#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c
1272#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d
1273#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e
1274#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f
1275#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110
1276#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111
1277#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112
1278#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113
1279#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114
1280#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115
1281#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116
1282#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
1283#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118
1284#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119
1285#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a
1286#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b
1287#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c
1288#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d
1289#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e
1290#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f
1291#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120
1292#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121
1293#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122
1294#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123
1295#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124
1296#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
1297#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
1298#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127
1299#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128
1300#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129
1301#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a
1302#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b
1303#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c
1304#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d
1305#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e
1306#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f
1307#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130
1308#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131
1309#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132
1310#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133
1311#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134
1312#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135
1313#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136
1314#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137
1315#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138
1316#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139
1317#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a
1318#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b
1319#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c
1320#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d
1321#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e
1322#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f
1323#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140
1324#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141
1325#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142
1326#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143
1327#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144
1328#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145
1329#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146
1330#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147
1331#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148
1332#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149
1333#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a
1334#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b
1335#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c
1336#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d
1337#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e
1338#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f
1339#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150
1340#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151
1341#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152
1342#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153
1343#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154
1344#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155
1345#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156
1346#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157
1347#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158
1348#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159
1349#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a
1350#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b
1351#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c
1352#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d
1353#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e
1354#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f
1355#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160
1356#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161
1357#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162
1358#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163
1359#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164
1360#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165
1361#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166
1362#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167
1363#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168
1364#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169
1365#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a
1366#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b
1367#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c
1368#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d
1369#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e
1370#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f
1371#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170
1372#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171
1373#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172
1374#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173
1375#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174
1376#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175
1377#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176
1378#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177
1379#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178
1380#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179
1381#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a
1382#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b
1383#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c
1384#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d
1385#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e
1386#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f
1387#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180
1388#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181
1389#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182
1390#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183
1391#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184
1392#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185
1393#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186
1394#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187
1395#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188
1396#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189
1397#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a
1398#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b
1399#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c
1400#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d
1401#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e
1402#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f
1403#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190
1404#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191
1405#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192
1406#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193
1407#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194
1408#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195
1409#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196
1410#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197
1411#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198
1412#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199
1413#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a
1414#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b
1415#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c
1416#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d
1417#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e
1418#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f
1419#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0
1420#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1
1421#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2
1422#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3
1423#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4
1424#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5
1425#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6
1426#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7
1427#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8
1428#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9
1429#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa
1430#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab
1431#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac
1432#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad
1433#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae
1434#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af
1435#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0
1436#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1
1437#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2
1438#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3
1439#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4
1440#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5
1441#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6
1442#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7
1443#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8
1444#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9
1445#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba
1446#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb
1447#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc
1448#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd
1449#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be
1450#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf
1451#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0
1452#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1
1453#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2
1454#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3
1455#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4
1456#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5
1457#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6
1458#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7
1459#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8
1460#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9
1461#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca
1462#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb
1463#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc
1464#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd
1465#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce
1466#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf
1467#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0
1468#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1
1469#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2
1470#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3
1471#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4
1472#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5
1473#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6
1474#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7
1475#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8
1476#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9
1477#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da
1478#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db
1479#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc
1480#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd
1481#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de
1482#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df
1483#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0
1484#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1
1485#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2
1486#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3
1487#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4
1488#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5
1489#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6
1490#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7
1491#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8
1492#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9
1493#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea
1494#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb
1495#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec
1496#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0
1497#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1
1498#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2
1499#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3
1500#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4
1501#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5
1502#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6
1503#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7
1504#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8
1505#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9
1506#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa
1507#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb
1508#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc
1509#define mmMC_SEQ_CNTL_3 0xd80
1510#define mmMC_SEQ_G5PDX_CTRL 0xd81
1511#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82
1512#define mmMC_SEQ_G5PDX_CMD0 0xd83
1513#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84
1514#define mmMC_SEQ_G5PDX_CMD1 0xd85
1515#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86
1516#define mmMC_SEQ_SREG_READ 0xd87
1517#define mmMC_SEQ_SREG_STATUS 0xd88
1518#define mmMC_SEQ_PHYREG_BCAST 0xd89
1519#define mmMC_SEQ_PMG_DVS_CTL 0xd8a
1520#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b
1521#define mmMC_SEQ_PMG_DVS_CMD 0xd8c
1522#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d
1523#define mmMC_SEQ_DLL_STBY 0xd8e
1524#define mmMC_SEQ_DLL_STBY_LP 0xd8f
1525#define mmMC_DLB_MISCCTRL0 0xd90
1526#define mmMC_DLB_MISCCTRL1 0xd91
1527#define mmMC_DLB_MISCCTRL2 0xd92
1528#define mmMC_DLB_CONFIG0 0xd93
1529#define mmMC_DLB_CONFIG1 0xd94
1530#define mmMC_DLB_SETUP 0xd95
1531#define mmMC_DLB_SETUPSWEEP 0xd96
1532#define mmMC_DLB_SETUPFIFO 0xd97
1533#define mmMC_DLB_WRITE_MASK 0xd98
1534#define mmMC_DLB_STATUS 0xd99
1535#define mmMC_DLB_STATUS_MISC0 0xd9a
1536#define mmMC_DLB_STATUS_MISC1 0xd9b
1537#define mmMC_DLB_STATUS_MISC2 0xd9c
1538#define mmMC_DLB_STATUS_MISC3 0xd9d
1539#define mmMC_DLB_STATUS_MISC4 0xd9e
1540#define mmMC_DLB_STATUS_MISC5 0xd9f
1541#define mmMC_DLB_STATUS_MISC6 0xda0
1542#define mmMC_DLB_STATUS_MISC7 0xda1
1543#define mmMC_ARB_HARSH_EN_RD 0xdc0
1544#define mmMC_ARB_HARSH_EN_WR 0xdc1
1545#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2
1546#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3
1547#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4
1548#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5
1549#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6
1550#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7
1551#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8
1552#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9
1553#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca
1554#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb
1555#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc
1556#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd
1557#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce
1558#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf
1559#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0
1560#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1
1561#define mmMC_ARB_HARSH_SAT0_RD 0xdd2
1562#define mmMC_ARB_HARSH_SAT0_WR 0xdd3
1563#define mmMC_ARB_HARSH_SAT1_RD 0xdd4
1564#define mmMC_ARB_HARSH_SAT1_WR 0xdd5
1565#define mmMC_ARB_HARSH_CTL_RD 0xdd6
1566#define mmMC_ARB_HARSH_CTL_WR 0xdd7
1567#define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8
1568#define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9
1569#define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda
1570#define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb
1571#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78
1572#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78
1573#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8
1574#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8
1575#define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
1576#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79
1577#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9
1578#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9
1579#define mmMCIF_WB_BUFMGR_STATUS 0x5e7a
1580#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a
1581#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba
1582#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa
1583#define mmMCIF_WB_BUF_PITCH 0x5e7b
1584#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b
1585#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb
1586#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb
1587#define mmMCIF_WB_BUF_1_STATUS 0x5e7c
1588#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c
1589#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc
1590#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc
1591#define mmMCIF_WB_BUF_1_STATUS2 0x5e7d
1592#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d
1593#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd
1594#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd
1595#define mmMCIF_WB_BUF_2_STATUS 0x5e7e
1596#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e
1597#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe
1598#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe
1599#define mmMCIF_WB_BUF_2_STATUS2 0x5e7f
1600#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f
1601#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf
1602#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff
1603#define mmMCIF_WB_BUF_3_STATUS 0x5e80
1604#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80
1605#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0
1606#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00
1607#define mmMCIF_WB_BUF_3_STATUS2 0x5e81
1608#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81
1609#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1
1610#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01
1611#define mmMCIF_WB_BUF_4_STATUS 0x5e82
1612#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82
1613#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2
1614#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02
1615#define mmMCIF_WB_BUF_4_STATUS2 0x5e83
1616#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83
1617#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3
1618#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03
1619#define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84
1620#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84
1621#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4
1622#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04
1623#define mmMCIF_WB_URGENCY_WATERMARK 0x5e85
1624#define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85
1625#define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5
1626#define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05
1627#define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86
1628#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86
1629#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6
1630#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06
1631#define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87
1632#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87
1633#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7
1634#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07
1635#define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88
1636#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88
1637#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8
1638#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08
1639#define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
1640#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89
1641#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9
1642#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09
1643#define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a
1644#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a
1645#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca
1646#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a
1647#define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
1648#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b
1649#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb
1650#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b
1651#define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c
1652#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c
1653#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc
1654#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c
1655#define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
1656#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d
1657#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd
1658#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d
1659#define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e
1660#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e
1661#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece
1662#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e
1663#define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
1664#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f
1665#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf
1666#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f
1667#define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90
1668#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90
1669#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0
1670#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10
1671#define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
1672#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91
1673#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1
1674#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11
1675#define mmMCIF_WB_BUF_3_ADDR_C 0x5e92
1676#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92
1677#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2
1678#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12
1679#define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
1680#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93
1681#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3
1682#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13
1683#define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94
1684#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94
1685#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4
1686#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14
1687#define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
1688#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95
1689#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5
1690#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15
1691#define mmMCIF_WB_BUF_4_ADDR_C 0x5e96
1692#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96
1693#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6
1694#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16
1695#define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
1696#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97
1697#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7
1698#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17
1699#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
1700#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98
1701#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8
1702#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18
1703#define mmMCIF_WB_HVVMID_CONTROL 0x5e99
1704#define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99
1705#define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9
1706#define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19
1707
1708#endif /* GMC_8_1_D_H */
1709