1/*
2 * GMC_8_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GMC_8_1_SH_MASK_H
25#define GMC_8_1_SH_MASK_H
26
27#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
37#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
38#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
39#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
40#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
41#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
42#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
43#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
44#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
45#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
46#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
47#define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
48#define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
49#define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
50#define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
51#define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
52#define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
53#define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
54#define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
55#define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
56#define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
57#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
58#define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
59#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
60#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
61#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
62#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
63#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
64#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
65#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
66#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
67#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
68#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
69#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
70#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
71#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
72#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
73#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
74#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
75#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
76#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
77#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
78#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
79#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
80#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
81#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
82#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
83#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
84#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
85#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
86#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
87#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
88#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
89#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
90#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
91#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
92#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
93#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
94#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
95#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
96#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
97#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
98#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
99#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
100#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
101#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
102#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
103#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
104#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
105#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
106#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
107#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
108#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
109#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
110#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
111#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
112#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
113#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
114#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
115#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
116#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
117#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
118#define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
119#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
120#define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
121#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
122#define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
123#define MC_ARB_FED_CNTL__MODE_MASK 0x3
124#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
125#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
126#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
127#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
128#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
129#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
130#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
131#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
132#define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
133#define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
134#define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
135#define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
136#define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
137#define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
138#define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
139#define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
140#define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
141#define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
142#define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
143#define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
144#define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
145#define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
146#define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
147#define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
148#define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
149#define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
150#define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
151#define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
152#define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
153#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
154#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
155#define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
156#define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
157#define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
158#define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
159#define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
160#define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
161#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
162#define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
163#define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
164#define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
165#define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
166#define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
167#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
168#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
169#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
170#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
171#define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
172#define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
173#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
174#define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
175#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
176#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
177#define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
178#define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
179#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
180#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
181#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
182#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
183#define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
184#define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
185#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
186#define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
187#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
188#define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
189#define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
190#define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
191#define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
192#define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
193#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
194#define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
195#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
196#define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
197#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
198#define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
199#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
200#define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
201#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
202#define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
203#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
204#define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
205#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
206#define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
207#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
208#define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
209#define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
210#define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
211#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
212#define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
213#define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
214#define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
215#define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
216#define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
217#define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
218#define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
219#define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
220#define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
221#define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
222#define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
223#define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
224#define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
225#define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
226#define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
227#define MC_ARB_PERF_CID__CH0_MASK 0xff
228#define MC_ARB_PERF_CID__CH0__SHIFT 0x0
229#define MC_ARB_PERF_CID__CH1_MASK 0xff00
230#define MC_ARB_PERF_CID__CH1__SHIFT 0x8
231#define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
232#define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
233#define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
234#define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
235#define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
236#define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
237#define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
238#define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
239#define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
240#define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
241#define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
242#define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
243#define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
244#define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
245#define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
246#define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
247#define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
248#define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
249#define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
250#define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
251#define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
252#define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
253#define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
254#define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
255#define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
256#define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
257#define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
258#define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
259#define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
260#define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
261#define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
262#define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
263#define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
264#define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
265#define MC_ARB_GECC2__ENABLE_MASK 0x1
266#define MC_ARB_GECC2__ENABLE__SHIFT 0x0
267#define MC_ARB_GECC2__ECC_MODE_MASK 0x6
268#define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
269#define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
270#define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
271#define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
272#define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
273#define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
274#define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
275#define MC_ARB_GECC2__READ_ERR_MASK 0x3800
276#define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
277#define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
278#define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
279#define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
280#define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
281#define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
282#define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
283#define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
284#define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
285#define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
286#define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
287#define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
288#define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
289#define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
290#define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
291#define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
292#define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
293#define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
294#define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
295#define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
296#define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
297#define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
298#define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
299#define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
300#define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
301#define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
302#define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
303#define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
304#define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
305#define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
306#define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
307#define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
308#define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
309#define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
310#define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
311#define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
312#define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
313#define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
314#define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
315#define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
316#define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
317#define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
318#define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
319#define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
320#define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
321#define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
322#define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
323#define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
324#define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
325#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
326#define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
327#define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
328#define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
329#define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
330#define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
331#define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
332#define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
333#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
334#define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
335#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
336#define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
337#define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
338#define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
339#define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
340#define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
341#define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
342#define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
343#define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
344#define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
345#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
346#define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
347#define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
348#define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
349#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
350#define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
351#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
352#define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
353#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
354#define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
355#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
356#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
357#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
358#define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
359#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
360#define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
361#define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
362#define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
363#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
364#define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
365#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
366#define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
367#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
368#define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
369#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
370#define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
371#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
372#define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
373#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
374#define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
375#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
376#define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
377#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
378#define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
379#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
380#define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
381#define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
382#define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
383#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
384#define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
385#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
386#define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
387#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
388#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
389#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
390#define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
391#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
392#define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
393#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
394#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
395#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
396#define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
397#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
398#define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
399#define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
400#define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
401#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
402#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
403#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
404#define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
405#define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
406#define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
407#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
408#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
409#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
410#define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
411#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
412#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
413#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
414#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
415#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
416#define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
417#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
418#define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
419#define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
420#define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
421#define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
422#define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
423#define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
424#define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
425#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
426#define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
427#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
428#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
429#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
430#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
431#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
432#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
433#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
434#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
435#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
436#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
437#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
438#define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
439#define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
440#define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
441#define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
442#define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
443#define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
444#define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
445#define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
446#define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
447#define MC_ARB_MISC2__GECC_MASK 0x40000
448#define MC_ARB_MISC2__GECC__SHIFT 0x12
449#define MC_ARB_MISC2__GECC_RST_MASK 0x80000
450#define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
451#define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
452#define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
453#define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
454#define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
455#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
456#define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
457#define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
458#define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
459#define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
460#define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
461#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
462#define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
463#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
464#define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
465#define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
466#define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
467#define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
468#define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
469#define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
470#define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
471#define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
472#define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
473#define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
474#define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
475#define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
476#define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
477#define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
478#define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
479#define MC_ARB_MISC__CALI_RATES_MASK 0x600000
480#define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
481#define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
482#define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
483#define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
484#define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
485#define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
486#define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
487#define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
488#define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
489#define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
490#define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
491#define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
492#define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
493#define MC_ARB_BANKMAP__BANK0_MASK 0xf
494#define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
495#define MC_ARB_BANKMAP__BANK1_MASK 0xf0
496#define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
497#define MC_ARB_BANKMAP__BANK2_MASK 0xf00
498#define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
499#define MC_ARB_BANKMAP__BANK3_MASK 0xf000
500#define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
501#define MC_ARB_BANKMAP__RANK_MASK 0xf0000
502#define MC_ARB_BANKMAP__RANK__SHIFT 0x10
503#define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
504#define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
505#define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
506#define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
507#define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
508#define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
509#define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
510#define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
511#define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
512#define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
513#define MC_ARB_RAMCFG__RSV_1_MASK 0x200
514#define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
515#define MC_ARB_RAMCFG__RSV_2_MASK 0x400
516#define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
517#define MC_ARB_RAMCFG__RSV_3_MASK 0x800
518#define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
519#define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
520#define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
521#define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
522#define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
523#define MC_ARB_POP__ENABLE_ARB_MASK 0x1
524#define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
525#define MC_ARB_POP__SPEC_OPEN_MASK 0x2
526#define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
527#define MC_ARB_POP__POP_DEPTH_MASK 0x3c
528#define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
529#define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
530#define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
531#define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
532#define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
533#define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
534#define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
535#define MC_ARB_POP__QUICK_STOP_MASK 0x20000
536#define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
537#define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
538#define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
539#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
540#define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
541#define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
542#define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
543#define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
544#define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
545#define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
546#define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
547#define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
548#define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
549#define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
550#define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
551#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
552#define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
553#define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
554#define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
555#define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
556#define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
557#define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
558#define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
559#define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
560#define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
561#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
562#define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
563#define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
564#define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
565#define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
566#define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
567#define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
568#define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
569#define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
570#define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
571#define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
572#define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
573#define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
574#define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
575#define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
576#define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
577#define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
578#define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
579#define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
580#define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
581#define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
582#define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
583#define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
584#define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
585#define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
586#define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
587#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
588#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
589#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
590#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
591#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
592#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
593#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
594#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
595#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
596#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
597#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
598#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
599#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
600#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
601#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
602#define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
603#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
604#define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
605#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
606#define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
607#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
608#define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
609#define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
610#define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
611#define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
612#define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
613#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
614#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
615#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
616#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
617#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
618#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
619#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
620#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
621#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
622#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
623#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
624#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
625#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
626#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
627#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
628#define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
629#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
630#define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
631#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
632#define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
633#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
634#define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
635#define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
636#define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
637#define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
638#define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
639#define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
640#define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
641#define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
642#define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
643#define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
644#define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
645#define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
646#define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
647#define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
648#define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
649#define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
650#define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
651#define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
652#define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
653#define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
654#define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
655#define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
656#define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
657#define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
658#define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
659#define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
660#define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
661#define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
662#define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
663#define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
664#define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
665#define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
666#define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
667#define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
668#define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
669#define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
670#define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
671#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
672#define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
673#define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
674#define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
675#define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
676#define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
677#define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
678#define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
679#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
680#define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
681#define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
682#define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
683#define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
684#define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
685#define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
686#define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
687#define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
688#define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
689#define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
690#define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
691#define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
692#define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
693#define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
694#define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
695#define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
696#define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
697#define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
698#define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
699#define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
700#define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
701#define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
702#define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
703#define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
704#define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
705#define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
706#define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
707#define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
708#define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
709#define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
710#define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
711#define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
712#define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
713#define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
714#define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
715#define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
716#define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
717#define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
718#define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
719#define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
720#define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
721#define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
722#define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
723#define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
724#define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
725#define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
726#define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
727#define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
728#define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
729#define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
730#define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
731#define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
732#define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
733#define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
734#define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
735#define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
736#define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
737#define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
738#define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
739#define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
740#define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
741#define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
742#define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
743#define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
744#define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
745#define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
746#define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
747#define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
748#define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
749#define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
750#define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
751#define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
752#define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
753#define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
754#define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
755#define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
756#define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
757#define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
758#define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
759#define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
760#define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
761#define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
762#define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
763#define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
764#define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
765#define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
766#define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
767#define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
768#define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
769#define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
770#define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
771#define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
772#define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
773#define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
774#define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
775#define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
776#define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
777#define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
778#define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
779#define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
780#define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
781#define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
782#define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
783#define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
784#define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
785#define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
786#define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
787#define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
788#define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
789#define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
790#define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
791#define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
792#define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
793#define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
794#define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
795#define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
796#define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
797#define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
798#define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
799#define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
800#define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
801#define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
802#define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
803#define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
804#define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
805#define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
806#define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
807#define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
808#define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
809#define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
810#define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
811#define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
812#define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
813#define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
814#define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
815#define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
816#define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
817#define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
818#define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
819#define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
820#define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
821#define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
822#define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
823#define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
824#define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
825#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
826#define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
827#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
828#define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
829#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000
830#define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11
831#define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
832#define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
833#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
834#define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
835#define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
836#define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
837#define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
838#define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
839#define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
840#define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
841#define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
842#define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
843#define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
844#define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
845#define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
846#define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
847#define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
848#define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
849#define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
850#define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
851#define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
852#define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
853#define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
854#define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
855#define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
856#define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
857#define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
858#define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
859#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
860#define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
861#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
862#define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
863#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
864#define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
865#define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
866#define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
867#define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
868#define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
869#define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
870#define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
871#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
872#define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
873#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
874#define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
875#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
876#define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
877#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
878#define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
879#define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
880#define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
881#define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
882#define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
883#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
884#define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
885#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
886#define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
887#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
888#define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
889#define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
890#define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
891#define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
892#define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
893#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
894#define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
895#define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
896#define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
897#define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
898#define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
899#define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
900#define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
901#define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
902#define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
903#define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
904#define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
905#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
906#define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
907#define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
908#define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
909#define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
910#define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
911#define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
912#define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
913#define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
914#define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
915#define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
916#define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
917#define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
918#define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
919#define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
920#define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
921#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
922#define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
923#define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
924#define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
925#define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
926#define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
927#define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
928#define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
929#define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
930#define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
931#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
932#define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
933#define MC_ARB_REMREQ__RD_WATER_MASK 0xff
934#define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
935#define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
936#define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
937#define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
938#define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
939#define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
940#define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
941#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
942#define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
943#define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
944#define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
945#define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
946#define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
947#define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
948#define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
949#define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
950#define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
951#define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
952#define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
953#define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
954#define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
955#define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
956#define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
957#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
958#define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
959#define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
960#define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
961#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
962#define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
963#define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
964#define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
965#define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
966#define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
967#define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
968#define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
969#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
970#define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
971#define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
972#define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
973#define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
974#define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
975#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
976#define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
977#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
978#define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
979#define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
980#define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
981#define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
982#define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
983#define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
984#define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
985#define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
986#define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
987#define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
988#define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
989#define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
990#define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
991#define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
992#define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
993#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
994#define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
995#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
996#define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
997#define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
998#define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
999#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
1000#define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
1001#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
1002#define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
1003#define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
1004#define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
1005#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
1006#define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
1007#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
1008#define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
1009#define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
1010#define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
1011#define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
1012#define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
1013#define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
1014#define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
1015#define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
1016#define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
1017#define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
1018#define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
1019#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
1020#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
1021#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
1022#define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
1023#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
1024#define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
1025#define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
1026#define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
1027#define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
1028#define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
1029#define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
1030#define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
1031#define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
1032#define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
1033#define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
1034#define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
1035#define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
1036#define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
1037#define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
1038#define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
1039#define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
1040#define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
1041#define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
1042#define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
1043#define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
1044#define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
1045#define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
1046#define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
1047#define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
1048#define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
1049#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
1050#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
1051#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
1052#define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
1053#define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
1054#define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
1055#define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
1056#define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
1057#define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
1058#define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
1059#define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
1060#define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
1061#define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
1062#define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
1063#define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
1064#define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
1065#define MC_ARB_CG__RSV_0_MASK 0xff0000
1066#define MC_ARB_CG__RSV_0__SHIFT 0x10
1067#define MC_ARB_CG__RSV_1_MASK 0xff000000
1068#define MC_ARB_CG__RSV_1__SHIFT 0x18
1069#define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
1070#define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
1071#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
1072#define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
1073#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
1074#define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
1075#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
1076#define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
1077#define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
1078#define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
1079#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
1080#define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
1081#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
1082#define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
1083#define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
1084#define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
1085#define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
1086#define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
1087#define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
1088#define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
1089#define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
1090#define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
1091#define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
1092#define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
1093#define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
1094#define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
1095#define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
1096#define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
1097#define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
1098#define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
1099#define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
1100#define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
1101#define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
1102#define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
1103#define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
1104#define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
1105#define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
1106#define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
1107#define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
1108#define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
1109#define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
1110#define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
1111#define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
1112#define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
1113#define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
1114#define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
1115#define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
1116#define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
1117#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
1118#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
1119#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
1120#define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
1121#define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
1122#define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
1123#define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
1124#define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
1125#define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
1126#define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
1127#define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
1128#define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
1129#define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
1130#define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
1131#define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
1132#define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
1133#define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
1134#define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
1135#define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
1136#define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
1137#define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
1138#define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
1139#define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
1140#define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
1141#define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
1142#define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
1143#define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
1144#define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
1145#define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
1146#define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
1147#define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
1148#define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
1149#define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
1150#define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
1151#define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
1152#define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
1153#define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
1154#define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
1155#define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
1156#define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
1157#define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
1158#define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
1159#define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
1160#define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
1161#define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
1162#define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
1163#define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
1164#define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
1165#define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
1166#define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
1167#define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
1168#define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
1169#define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
1170#define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
1171#define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
1172#define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
1173#define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
1174#define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
1175#define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
1176#define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
1177#define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
1178#define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
1179#define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
1180#define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
1181#define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
1182#define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
1183#define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
1184#define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
1185#define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
1186#define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
1187#define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
1188#define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
1189#define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
1190#define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
1191#define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
1192#define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
1193#define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
1194#define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
1195#define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
1196#define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
1197#define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
1198#define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
1199#define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
1200#define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1201#define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
1202#define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
1203#define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
1204#define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
1205#define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
1206#define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
1207#define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
1208#define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
1209#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
1210#define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
1211#define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
1212#define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
1213#define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
1214#define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
1215#define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
1216#define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
1217#define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
1218#define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
1219#define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
1220#define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
1221#define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
1222#define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
1223#define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
1224#define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
1225#define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
1226#define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
1227#define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
1228#define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
1229#define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
1230#define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
1231#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
1232#define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
1233#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
1234#define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
1235#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
1236#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
1237#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
1238#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
1239#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
1240#define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
1241#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
1242#define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
1243#define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
1244#define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
1245#define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
1246#define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
1247#define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00
1248#define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa
1249#define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000
1250#define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf
1251#define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000
1252#define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14
1253#define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000
1254#define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19
1255#define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
1256#define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
1257#define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
1258#define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
1259#define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
1260#define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
1261#define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
1262#define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
1263#define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
1264#define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
1265#define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
1266#define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
1267#define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
1268#define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
1269#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
1270#define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
1271#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
1272#define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
1273#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
1274#define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
1275#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
1276#define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
1277#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
1278#define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
1279#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
1280#define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
1281#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
1282#define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
1283#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
1284#define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
1285#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
1286#define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
1287#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
1288#define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
1289#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
1290#define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
1291#define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
1292#define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
1293#define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
1294#define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
1295#define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
1296#define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
1297#define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
1298#define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
1299#define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
1300#define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
1301#define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
1302#define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
1303#define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
1304#define MC_CG_CONFIG__INDEX__SHIFT 0x6
1305#define MC_CITF_CNTL__IGNOREPM_MASK 0x4
1306#define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
1307#define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
1308#define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
1309#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
1310#define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
1311#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
1312#define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
1313#define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
1314#define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
1315#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
1316#define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
1317#define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
1318#define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
1319#define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
1320#define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
1321#define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
1322#define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
1323#define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
1324#define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
1325#define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
1326#define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
1327#define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
1328#define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
1329#define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
1330#define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
1331#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
1332#define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
1333#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
1334#define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
1335#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
1336#define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
1337#define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
1338#define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
1339#define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
1340#define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
1341#define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
1342#define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
1343#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
1344#define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
1345#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
1346#define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
1347#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
1348#define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
1349#define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
1350#define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
1351#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
1352#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
1353#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
1354#define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
1355#define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
1356#define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
1357#define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
1358#define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
1359#define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
1360#define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
1361#define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
1362#define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
1363#define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
1364#define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
1365#define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
1366#define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
1367#define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
1368#define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
1369#define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
1370#define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
1371#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
1372#define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
1373#define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
1374#define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
1375#define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
1376#define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
1377#define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
1378#define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
1379#define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
1380#define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
1381#define MC_RD_GRP_EXT__TC0_MASK 0xf0
1382#define MC_RD_GRP_EXT__TC0__SHIFT 0x4
1383#define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
1384#define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
1385#define MC_WR_GRP_EXT__TC0_MASK 0xf0
1386#define MC_WR_GRP_EXT__TC0__SHIFT 0x4
1387#define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
1388#define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
1389#define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
1390#define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
1391#define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
1392#define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
1393#define MC_WR_TC0__ENABLE_MASK 0x1
1394#define MC_WR_TC0__ENABLE__SHIFT 0x0
1395#define MC_WR_TC0__PRESCALE_MASK 0x6
1396#define MC_WR_TC0__PRESCALE__SHIFT 0x1
1397#define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
1398#define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1399#define MC_WR_TC0__STALL_MODE_MASK 0x30
1400#define MC_WR_TC0__STALL_MODE__SHIFT 0x4
1401#define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
1402#define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
1403#define MC_WR_TC0__MAX_BURST_MASK 0x780
1404#define MC_WR_TC0__MAX_BURST__SHIFT 0x7
1405#define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
1406#define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
1407#define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1408#define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1409#define MC_WR_TC1__ENABLE_MASK 0x1
1410#define MC_WR_TC1__ENABLE__SHIFT 0x0
1411#define MC_WR_TC1__PRESCALE_MASK 0x6
1412#define MC_WR_TC1__PRESCALE__SHIFT 0x1
1413#define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
1414#define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1415#define MC_WR_TC1__STALL_MODE_MASK 0x30
1416#define MC_WR_TC1__STALL_MODE__SHIFT 0x4
1417#define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
1418#define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
1419#define MC_WR_TC1__MAX_BURST_MASK 0x780
1420#define MC_WR_TC1__MAX_BURST__SHIFT 0x7
1421#define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
1422#define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
1423#define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1424#define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1425#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
1426#define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
1427#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
1428#define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
1429#define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
1430#define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
1431#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
1432#define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1433#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
1434#define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1435#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1436#define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1437#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
1438#define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1439#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
1440#define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1441#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
1442#define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1443#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1444#define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1445#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1446#define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1447#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
1448#define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
1449#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
1450#define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
1451#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
1452#define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1453#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
1454#define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1455#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1456#define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1457#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
1458#define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1459#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
1460#define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1461#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
1462#define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1463#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1464#define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1465#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1466#define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1467#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
1468#define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
1469#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
1470#define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
1471#define MC_RD_CB__ENABLE_MASK 0x1
1472#define MC_RD_CB__ENABLE__SHIFT 0x0
1473#define MC_RD_CB__PRESCALE_MASK 0x6
1474#define MC_RD_CB__PRESCALE__SHIFT 0x1
1475#define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
1476#define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1477#define MC_RD_CB__STALL_MODE_MASK 0x30
1478#define MC_RD_CB__STALL_MODE__SHIFT 0x4
1479#define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
1480#define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
1481#define MC_RD_CB__MAX_BURST_MASK 0x780
1482#define MC_RD_CB__MAX_BURST__SHIFT 0x7
1483#define MC_RD_CB__LAZY_TIMER_MASK 0x7800
1484#define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
1485#define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1486#define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1487#define MC_RD_DB__ENABLE_MASK 0x1
1488#define MC_RD_DB__ENABLE__SHIFT 0x0
1489#define MC_RD_DB__PRESCALE_MASK 0x6
1490#define MC_RD_DB__PRESCALE__SHIFT 0x1
1491#define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
1492#define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1493#define MC_RD_DB__STALL_MODE_MASK 0x30
1494#define MC_RD_DB__STALL_MODE__SHIFT 0x4
1495#define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
1496#define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
1497#define MC_RD_DB__MAX_BURST_MASK 0x780
1498#define MC_RD_DB__MAX_BURST__SHIFT 0x7
1499#define MC_RD_DB__LAZY_TIMER_MASK 0x7800
1500#define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
1501#define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1502#define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1503#define MC_RD_TC0__ENABLE_MASK 0x1
1504#define MC_RD_TC0__ENABLE__SHIFT 0x0
1505#define MC_RD_TC0__PRESCALE_MASK 0x6
1506#define MC_RD_TC0__PRESCALE__SHIFT 0x1
1507#define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
1508#define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1509#define MC_RD_TC0__STALL_MODE_MASK 0x30
1510#define MC_RD_TC0__STALL_MODE__SHIFT 0x4
1511#define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
1512#define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
1513#define MC_RD_TC0__MAX_BURST_MASK 0x780
1514#define MC_RD_TC0__MAX_BURST__SHIFT 0x7
1515#define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
1516#define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
1517#define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1518#define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1519#define MC_RD_TC1__ENABLE_MASK 0x1
1520#define MC_RD_TC1__ENABLE__SHIFT 0x0
1521#define MC_RD_TC1__PRESCALE_MASK 0x6
1522#define MC_RD_TC1__PRESCALE__SHIFT 0x1
1523#define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
1524#define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1525#define MC_RD_TC1__STALL_MODE_MASK 0x30
1526#define MC_RD_TC1__STALL_MODE__SHIFT 0x4
1527#define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
1528#define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
1529#define MC_RD_TC1__MAX_BURST_MASK 0x780
1530#define MC_RD_TC1__MAX_BURST__SHIFT 0x7
1531#define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
1532#define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
1533#define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1534#define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1535#define MC_RD_HUB__ENABLE_MASK 0x1
1536#define MC_RD_HUB__ENABLE__SHIFT 0x0
1537#define MC_RD_HUB__PRESCALE_MASK 0x6
1538#define MC_RD_HUB__PRESCALE__SHIFT 0x1
1539#define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
1540#define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1541#define MC_RD_HUB__STALL_MODE_MASK 0x30
1542#define MC_RD_HUB__STALL_MODE__SHIFT 0x4
1543#define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
1544#define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
1545#define MC_RD_HUB__MAX_BURST_MASK 0x780
1546#define MC_RD_HUB__MAX_BURST__SHIFT 0x7
1547#define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
1548#define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
1549#define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1550#define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1551#define MC_WR_CB__ENABLE_MASK 0x1
1552#define MC_WR_CB__ENABLE__SHIFT 0x0
1553#define MC_WR_CB__PRESCALE_MASK 0x6
1554#define MC_WR_CB__PRESCALE__SHIFT 0x1
1555#define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
1556#define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1557#define MC_WR_CB__STALL_MODE_MASK 0x30
1558#define MC_WR_CB__STALL_MODE__SHIFT 0x4
1559#define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
1560#define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
1561#define MC_WR_CB__MAX_BURST_MASK 0x780
1562#define MC_WR_CB__MAX_BURST__SHIFT 0x7
1563#define MC_WR_CB__LAZY_TIMER_MASK 0x7800
1564#define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
1565#define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1566#define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1567#define MC_WR_DB__ENABLE_MASK 0x1
1568#define MC_WR_DB__ENABLE__SHIFT 0x0
1569#define MC_WR_DB__PRESCALE_MASK 0x6
1570#define MC_WR_DB__PRESCALE__SHIFT 0x1
1571#define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
1572#define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1573#define MC_WR_DB__STALL_MODE_MASK 0x30
1574#define MC_WR_DB__STALL_MODE__SHIFT 0x4
1575#define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
1576#define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
1577#define MC_WR_DB__MAX_BURST_MASK 0x780
1578#define MC_WR_DB__MAX_BURST__SHIFT 0x7
1579#define MC_WR_DB__LAZY_TIMER_MASK 0x7800
1580#define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
1581#define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1582#define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1583#define MC_WR_HUB__ENABLE_MASK 0x1
1584#define MC_WR_HUB__ENABLE__SHIFT 0x0
1585#define MC_WR_HUB__PRESCALE_MASK 0x6
1586#define MC_WR_HUB__PRESCALE__SHIFT 0x1
1587#define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
1588#define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1589#define MC_WR_HUB__STALL_MODE_MASK 0x30
1590#define MC_WR_HUB__STALL_MODE__SHIFT 0x4
1591#define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
1592#define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
1593#define MC_WR_HUB__MAX_BURST_MASK 0x780
1594#define MC_WR_HUB__MAX_BURST__SHIFT 0x7
1595#define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
1596#define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
1597#define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1598#define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1599#define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
1600#define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
1601#define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
1602#define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
1603#define MC_RD_GRP_LCL__CB0_MASK 0xf000
1604#define MC_RD_GRP_LCL__CB0__SHIFT 0xc
1605#define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
1606#define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
1607#define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
1608#define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
1609#define MC_RD_GRP_LCL__DB0_MASK 0xf000000
1610#define MC_RD_GRP_LCL__DB0__SHIFT 0x18
1611#define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
1612#define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
1613#define MC_WR_GRP_LCL__CB0_MASK 0xf
1614#define MC_WR_GRP_LCL__CB0__SHIFT 0x0
1615#define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
1616#define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
1617#define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
1618#define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
1619#define MC_WR_GRP_LCL__DB0_MASK 0xf000
1620#define MC_WR_GRP_LCL__DB0__SHIFT 0xc
1621#define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
1622#define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
1623#define MC_WR_GRP_LCL__SX0_MASK 0xf00000
1624#define MC_WR_GRP_LCL__SX0__SHIFT 0x14
1625#define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
1626#define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
1627#define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
1628#define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
1629#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
1630#define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
1631#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
1632#define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
1633#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
1634#define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
1635#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
1636#define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
1637#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
1638#define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
1639#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
1640#define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
1641#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
1642#define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
1643#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
1644#define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
1645#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
1646#define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
1647#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
1648#define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
1649#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
1650#define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
1651#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
1652#define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
1653#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
1654#define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
1655#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
1656#define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
1657#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
1658#define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
1659#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
1660#define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
1661#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
1662#define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
1663#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
1664#define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
1665#define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
1666#define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
1667#define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
1668#define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
1669#define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
1670#define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
1671#define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
1672#define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
1673#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
1674#define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
1675#define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
1676#define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
1677#define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
1678#define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
1679#define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
1680#define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
1681#define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
1682#define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
1683#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
1684#define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
1685#define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
1686#define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
1687#define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
1688#define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
1689#define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
1690#define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
1691#define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
1692#define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
1693#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1694#define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1695#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
1696#define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
1697#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
1698#define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
1699#define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
1700#define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
1701#define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
1702#define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
1703#define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
1704#define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
1705#define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
1706#define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
1707#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
1708#define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
1709#define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
1710#define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
1711#define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
1712#define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
1713#define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
1714#define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
1715#define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
1716#define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
1717#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1718#define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1719#define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
1720#define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
1721#define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
1722#define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
1723#define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
1724#define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
1725#define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
1726#define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
1727#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
1728#define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
1729#define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
1730#define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
1731#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
1732#define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
1733#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
1734#define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
1735#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
1736#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
1737#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
1738#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
1739#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
1740#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
1741#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
1742#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
1743#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
1744#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
1745#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
1746#define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
1747#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
1748#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
1749#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
1750#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
1751#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
1752#define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
1753#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
1754#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
1755#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
1756#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
1757#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
1758#define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
1759#define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
1760#define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
1761#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
1762#define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
1763#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
1764#define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
1765#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
1766#define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
1767#define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
1768#define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
1769#define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
1770#define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
1771#define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
1772#define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
1773#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
1774#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
1775#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
1776#define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
1777#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
1778#define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
1779#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1780#define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1781#define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
1782#define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
1783#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
1784#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
1785#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
1786#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
1787#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
1788#define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
1789#define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
1790#define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
1791#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
1792#define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
1793#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
1794#define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
1795#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
1796#define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
1797#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
1798#define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
1799#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
1800#define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
1801#define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
1802#define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
1803#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
1804#define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
1805#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
1806#define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
1807#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
1808#define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
1809#define MC_HUB_WDP_BP__ENABLE_MASK 0x1
1810#define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
1811#define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
1812#define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
1813#define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
1814#define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
1815#define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
1816#define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
1817#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
1818#define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1819#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
1820#define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1821#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
1822#define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1823#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1824#define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1825#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
1826#define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1827#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
1828#define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1829#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
1830#define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1831#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
1832#define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1833#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
1834#define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
1835#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
1836#define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
1837#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
1838#define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
1839#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
1840#define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
1841#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
1842#define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
1843#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
1844#define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
1845#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
1846#define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
1847#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
1848#define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
1849#define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
1850#define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
1851#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
1852#define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
1853#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
1854#define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
1855#define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
1856#define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
1857#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
1858#define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
1859#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
1860#define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
1861#define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
1862#define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
1863#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
1864#define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1865#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
1866#define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1867#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
1868#define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1869#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1870#define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1871#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
1872#define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1873#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
1874#define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1875#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
1876#define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1877#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
1878#define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1879#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
1880#define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
1881#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
1882#define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
1883#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
1884#define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
1885#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
1886#define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
1887#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
1888#define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
1889#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
1890#define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
1891#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
1892#define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
1893#define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
1894#define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
1895#define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
1896#define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
1897#define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
1898#define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
1899#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
1900#define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
1901#define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
1902#define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
1903#define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
1904#define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
1905#define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
1906#define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
1907#define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
1908#define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
1909#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
1910#define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
1911#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
1912#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
1913#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
1914#define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
1915#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1916#define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1917#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
1918#define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
1919#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
1920#define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
1921#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
1922#define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
1923#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
1924#define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
1925#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
1926#define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
1927#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
1928#define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
1929#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
1930#define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
1931#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
1932#define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
1933#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
1934#define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
1935#define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
1936#define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
1937#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
1938#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
1939#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
1940#define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
1941#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
1942#define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
1943#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
1944#define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
1945#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
1946#define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
1947#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
1948#define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
1949#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
1950#define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
1951#define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
1952#define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
1953#define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
1954#define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
1955#define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
1956#define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
1957#define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
1958#define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
1959#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
1960#define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
1961#define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
1962#define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
1963#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1964#define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1965#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1966#define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1967#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1968#define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1969#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1970#define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1971#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1972#define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1973#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1974#define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1975#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1976#define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1977#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1978#define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1979#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1980#define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1981#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1982#define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1983#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1984#define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1985#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1986#define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1987#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1988#define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1989#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1990#define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1991#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1992#define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1993#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1994#define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1995#define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
1996#define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
1997#define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
1998#define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
1999#define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
2000#define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
2001#define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
2002#define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
2003#define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
2004#define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
2005#define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
2006#define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
2007#define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
2008#define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
2009#define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000
2010#define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18
2011#define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
2012#define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
2013#define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
2014#define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
2015#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
2016#define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
2017#define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
2018#define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
2019#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
2020#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
2021#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000
2022#define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19
2023#define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
2024#define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
2025#define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
2026#define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
2027#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
2028#define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
2029#define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
2030#define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
2031#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
2032#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
2033#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000
2034#define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19
2035#define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff
2036#define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0
2037#define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00
2038#define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8
2039#define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
2040#define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
2041#define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
2042#define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
2043#define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
2044#define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
2045#define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
2046#define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
2047#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
2048#define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
2049#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
2050#define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
2051#define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
2052#define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
2053#define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
2054#define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
2055#define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
2056#define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
2057#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
2058#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
2059#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
2060#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
2061#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
2062#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
2063#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
2064#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
2065#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
2066#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
2067#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
2068#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
2069#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
2070#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
2071#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
2072#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
2073#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
2074#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
2075#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
2076#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
2077#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
2078#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
2079#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
2080#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
2081#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
2082#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
2083#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
2084#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
2085#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
2086#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
2087#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
2088#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
2089#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
2090#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
2091#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
2092#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
2093#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
2094#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
2095#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
2096#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
2097#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
2098#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
2099#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
2100#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
2101#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
2102#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
2103#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
2104#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
2105#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
2106#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
2107#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
2108#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
2109#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
2110#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
2111#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
2112#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
2113#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
2114#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
2115#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
2116#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
2117#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
2118#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
2119#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
2120#define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
2121#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
2122#define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
2123#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
2124#define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
2125#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
2126#define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
2127#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
2128#define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
2129#define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
2130#define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
2131#define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
2132#define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
2133#define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
2134#define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
2135#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
2136#define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
2137#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
2138#define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
2139#define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
2140#define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
2141#define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
2142#define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
2143#define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
2144#define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
2145#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
2146#define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
2147#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
2148#define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
2149#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
2150#define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
2151#define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
2152#define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
2153#define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
2154#define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
2155#define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
2156#define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
2157#define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
2158#define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
2159#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
2160#define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
2161#define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
2162#define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
2163#define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
2164#define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
2165#define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
2166#define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
2167#define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
2168#define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
2169#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
2170#define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
2171#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2172#define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2173#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2174#define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2175#define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
2176#define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
2177#define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
2178#define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
2179#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
2180#define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
2181#define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
2182#define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
2183#define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
2184#define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
2185#define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
2186#define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
2187#define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
2188#define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
2189#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
2190#define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
2191#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2192#define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2193#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2194#define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2195#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
2196#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
2197#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
2198#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
2199#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
2200#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
2201#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
2202#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
2203#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
2204#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
2205#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
2206#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
2207#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
2208#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
2209#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
2210#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
2211#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
2212#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
2213#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
2214#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
2215#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
2216#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
2217#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
2218#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
2219#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
2220#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
2221#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
2222#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
2223#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
2224#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
2225#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
2226#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
2227#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000
2228#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10
2229#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000
2230#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11
2231#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000
2232#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12
2233#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000
2234#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13
2235#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000
2236#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14
2237#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000
2238#define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15
2239#define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1
2240#define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0
2241#define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6
2242#define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1
2243#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8
2244#define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3
2245#define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30
2246#define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4
2247#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40
2248#define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6
2249#define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780
2250#define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7
2251#define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800
2252#define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb
2253#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000
2254#define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf
2255#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2256#define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2257#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2258#define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2259#define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
2260#define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
2261#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2262#define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2263#define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
2264#define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
2265#define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
2266#define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
2267#define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
2268#define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
2269#define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
2270#define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
2271#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
2272#define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
2273#define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
2274#define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
2275#define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
2276#define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
2277#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2278#define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2279#define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
2280#define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
2281#define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
2282#define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
2283#define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
2284#define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
2285#define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
2286#define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
2287#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
2288#define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
2289#define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
2290#define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
2291#define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
2292#define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
2293#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2294#define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2295#define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
2296#define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
2297#define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
2298#define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
2299#define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
2300#define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
2301#define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
2302#define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
2303#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
2304#define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
2305#define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
2306#define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
2307#define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
2308#define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
2309#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2310#define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2311#define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
2312#define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
2313#define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
2314#define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
2315#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
2316#define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
2317#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
2318#define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
2319#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
2320#define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
2321#define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
2322#define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
2323#define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
2324#define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
2325#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
2326#define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
2327#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
2328#define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
2329#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
2330#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
2331#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
2332#define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
2333#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
2334#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
2335#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
2336#define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
2337#define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
2338#define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
2339#define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
2340#define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
2341#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
2342#define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2343#define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
2344#define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
2345#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
2346#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
2347#define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
2348#define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
2349#define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
2350#define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
2351#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2352#define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2353#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2354#define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2355#define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
2356#define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
2357#define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
2358#define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
2359#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2360#define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2361#define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
2362#define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
2363#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
2364#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2365#define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
2366#define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
2367#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
2368#define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
2369#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2370#define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2371#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2372#define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2373#define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
2374#define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
2375#define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
2376#define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
2377#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
2378#define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2379#define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
2380#define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
2381#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
2382#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
2383#define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
2384#define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
2385#define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
2386#define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
2387#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2388#define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2389#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2390#define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2391#define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
2392#define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
2393#define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
2394#define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
2395#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2396#define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2397#define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
2398#define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
2399#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
2400#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2401#define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
2402#define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
2403#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
2404#define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
2405#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2406#define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2407#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2408#define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2409#define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
2410#define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
2411#define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
2412#define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
2413#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
2414#define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2415#define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
2416#define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
2417#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
2418#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
2419#define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
2420#define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
2421#define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
2422#define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
2423#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2424#define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2425#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2426#define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2427#define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
2428#define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
2429#define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
2430#define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
2431#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
2432#define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2433#define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
2434#define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
2435#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
2436#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
2437#define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
2438#define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
2439#define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
2440#define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
2441#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2442#define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2443#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2444#define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2445#define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
2446#define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
2447#define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
2448#define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
2449#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
2450#define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
2451#define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
2452#define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
2453#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
2454#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
2455#define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
2456#define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
2457#define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
2458#define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
2459#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
2460#define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
2461#define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
2462#define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
2463#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2464#define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2465#define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
2466#define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
2467#define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
2468#define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
2469#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
2470#define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2471#define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
2472#define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
2473#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
2474#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
2475#define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
2476#define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
2477#define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
2478#define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
2479#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2480#define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2481#define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
2482#define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
2483#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2484#define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2485#define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
2486#define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
2487#define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
2488#define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
2489#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
2490#define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2491#define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
2492#define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
2493#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
2494#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
2495#define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
2496#define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
2497#define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
2498#define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
2499#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2500#define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2501#define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
2502#define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
2503#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2504#define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2505#define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1
2506#define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0
2507#define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6
2508#define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1
2509#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8
2510#define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3
2511#define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30
2512#define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4
2513#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40
2514#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6
2515#define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780
2516#define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7
2517#define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800
2518#define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb
2519#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000
2520#define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf
2521#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2522#define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2523#define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
2524#define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
2525#define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
2526#define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
2527#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
2528#define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
2529#define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
2530#define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
2531#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
2532#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
2533#define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
2534#define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
2535#define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
2536#define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
2537#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
2538#define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2539#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2540#define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2541#define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
2542#define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
2543#define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
2544#define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
2545#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2546#define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2547#define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
2548#define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
2549#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
2550#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
2551#define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
2552#define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
2553#define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
2554#define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
2555#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2556#define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2557#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2558#define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2559#define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
2560#define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
2561#define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
2562#define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
2563#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
2564#define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
2565#define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
2566#define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
2567#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
2568#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
2569#define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
2570#define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
2571#define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
2572#define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
2573#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
2574#define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2575#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2576#define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2577#define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
2578#define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
2579#define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
2580#define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
2581#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
2582#define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
2583#define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
2584#define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
2585#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
2586#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
2587#define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
2588#define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
2589#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
2590#define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
2591#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
2592#define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
2593#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2594#define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2595#define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
2596#define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
2597#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2598#define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2599#define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
2600#define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
2601#define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
2602#define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
2603#define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
2604#define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
2605#define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
2606#define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
2607#define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
2608#define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
2609#define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
2610#define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
2611#define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
2612#define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
2613#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2614#define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2615#define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
2616#define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
2617#define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
2618#define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
2619#define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
2620#define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
2621#define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
2622#define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
2623#define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
2624#define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
2625#define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
2626#define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
2627#define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
2628#define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
2629#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2630#define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2631#define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
2632#define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
2633#define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
2634#define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
2635#define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
2636#define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
2637#define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
2638#define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
2639#define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
2640#define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
2641#define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
2642#define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
2643#define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
2644#define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
2645#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2646#define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2647#define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
2648#define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
2649#define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
2650#define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
2651#define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
2652#define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
2653#define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
2654#define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
2655#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
2656#define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
2657#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
2658#define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
2659#define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
2660#define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
2661#define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
2662#define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
2663#define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
2664#define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
2665#define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
2666#define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
2667#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2668#define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2669#define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
2670#define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
2671#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
2672#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2673#define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
2674#define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
2675#define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
2676#define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
2677#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2678#define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2679#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2680#define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2681#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2682#define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2683#define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
2684#define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
2685#define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
2686#define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
2687#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
2688#define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
2689#define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
2690#define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
2691#define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
2692#define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
2693#define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
2694#define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
2695#define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
2696#define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
2697#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
2698#define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
2699#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2700#define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2701#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2702#define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2703#define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
2704#define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
2705#define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
2706#define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
2707#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2708#define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2709#define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
2710#define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
2711#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
2712#define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
2713#define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
2714#define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
2715#define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
2716#define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
2717#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2718#define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2719#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2720#define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2721#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2722#define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2723#define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
2724#define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
2725#define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
2726#define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
2727#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
2728#define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
2729#define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
2730#define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
2731#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
2732#define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
2733#define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
2734#define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
2735#define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
2736#define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
2737#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
2738#define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
2739#define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
2740#define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
2741#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2742#define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2743#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
2744#define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
2745#define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
2746#define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
2747#define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
2748#define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
2749#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
2750#define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
2751#define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
2752#define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
2753#define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
2754#define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
2755#define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
2756#define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
2757#define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
2758#define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
2759#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
2760#define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2761#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2762#define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2763#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2764#define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2765#define MC_HUB_WDP_IH__ENABLE_MASK 0x1
2766#define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
2767#define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
2768#define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
2769#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
2770#define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
2771#define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
2772#define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
2773#define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
2774#define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
2775#define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
2776#define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
2777#define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
2778#define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
2779#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
2780#define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
2781#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2782#define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2783#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2784#define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2785#define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
2786#define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
2787#define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
2788#define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
2789#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
2790#define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2791#define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
2792#define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
2793#define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
2794#define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
2795#define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
2796#define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
2797#define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
2798#define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
2799#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2800#define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2801#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2802#define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2803#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2804#define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2805#define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
2806#define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
2807#define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
2808#define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
2809#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
2810#define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2811#define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
2812#define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
2813#define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
2814#define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
2815#define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
2816#define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
2817#define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
2818#define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
2819#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2820#define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2821#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2822#define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2823#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2824#define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2825#define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
2826#define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
2827#define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
2828#define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
2829#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
2830#define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2831#define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
2832#define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
2833#define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
2834#define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
2835#define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
2836#define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
2837#define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
2838#define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
2839#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2840#define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2841#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2842#define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2843#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2844#define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2845#define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
2846#define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
2847#define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
2848#define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
2849#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
2850#define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
2851#define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
2852#define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
2853#define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
2854#define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
2855#define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
2856#define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
2857#define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
2858#define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
2859#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
2860#define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
2861#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2862#define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2863#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2864#define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2865#define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
2866#define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
2867#define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
2868#define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
2869#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
2870#define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2871#define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
2872#define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
2873#define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
2874#define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
2875#define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
2876#define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
2877#define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
2878#define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
2879#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2880#define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2881#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2882#define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2883#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2884#define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2885#define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
2886#define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
2887#define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
2888#define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
2889#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
2890#define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2891#define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
2892#define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
2893#define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
2894#define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
2895#define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
2896#define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
2897#define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
2898#define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
2899#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2900#define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2901#define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
2902#define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
2903#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2904#define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2905#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
2906#define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
2907#define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
2908#define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
2909#define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
2910#define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
2911#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
2912#define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2913#define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
2914#define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
2915#define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
2916#define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
2917#define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
2918#define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
2919#define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
2920#define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
2921#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2922#define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2923#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2924#define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2925#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2926#define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2927#define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
2928#define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
2929#define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
2930#define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
2931#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2932#define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2933#define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
2934#define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
2935#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
2936#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2937#define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
2938#define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
2939#define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
2940#define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
2941#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2942#define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2943#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2944#define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2945#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2946#define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2947#define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
2948#define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
2949#define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
2950#define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
2951#define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
2952#define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
2953#define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
2954#define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
2955#define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
2956#define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
2957#define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
2958#define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
2959#define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
2960#define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
2961#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
2962#define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
2963#define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
2964#define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
2965#define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
2966#define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
2967#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
2968#define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
2969#define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
2970#define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
2971#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
2972#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
2973#define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
2974#define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
2975#define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
2976#define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
2977#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
2978#define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
2979#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2980#define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2981#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2982#define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2983#define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
2984#define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
2985#define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
2986#define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
2987#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2988#define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2989#define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
2990#define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
2991#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
2992#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2993#define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
2994#define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
2995#define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
2996#define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
2997#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2998#define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2999#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3000#define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3001#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3002#define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3003#define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
3004#define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
3005#define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
3006#define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
3007#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
3008#define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
3009#define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
3010#define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
3011#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
3012#define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
3013#define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
3014#define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
3015#define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
3016#define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
3017#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
3018#define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
3019#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3020#define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3021#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3022#define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3023#define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
3024#define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
3025#define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
3026#define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
3027#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
3028#define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
3029#define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
3030#define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
3031#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
3032#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
3033#define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
3034#define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
3035#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
3036#define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
3037#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
3038#define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
3039#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3040#define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3041#define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
3042#define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
3043#define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
3044#define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
3045#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
3046#define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
3047#define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
3048#define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
3049#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
3050#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
3051#define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
3052#define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
3053#define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
3054#define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
3055#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
3056#define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
3057#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3058#define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3059#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
3060#define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
3061#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
3062#define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
3063#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
3064#define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
3065#define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
3066#define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
3067#define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
3068#define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
3069#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
3070#define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
3071#define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
3072#define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
3073#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
3074#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
3075#define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
3076#define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
3077#define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
3078#define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
3079#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
3080#define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
3081#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3082#define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3083#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
3084#define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
3085#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
3086#define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
3087#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
3088#define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
3089#define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
3090#define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
3091#define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
3092#define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
3093#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
3094#define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
3095#define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
3096#define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
3097#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
3098#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
3099#define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
3100#define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
3101#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
3102#define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
3103#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
3104#define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
3105#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3106#define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3107#define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
3108#define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
3109#define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
3110#define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
3111#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
3112#define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
3113#define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
3114#define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
3115#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
3116#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
3117#define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
3118#define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
3119#define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
3120#define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
3121#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
3122#define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
3123#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3124#define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3125#define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
3126#define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
3127#define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
3128#define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
3129#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
3130#define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
3131#define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
3132#define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
3133#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
3134#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
3135#define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
3136#define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
3137#define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
3138#define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
3139#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
3140#define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
3141#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3142#define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3143#define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
3144#define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
3145#define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
3146#define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
3147#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
3148#define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
3149#define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
3150#define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
3151#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
3152#define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
3153#define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
3154#define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
3155#define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
3156#define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
3157#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
3158#define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
3159#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3160#define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3161#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3162#define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3163#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000
3164#define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12
3165#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000
3166#define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13
3167#define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000
3168#define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14
3169#define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
3170#define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
3171#define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
3172#define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
3173#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
3174#define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
3175#define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
3176#define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
3177#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
3178#define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
3179#define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
3180#define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
3181#define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
3182#define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
3183#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
3184#define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
3185#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3186#define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3187#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3188#define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3189#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000
3190#define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12
3191#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000
3192#define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13
3193#define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000
3194#define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14
3195#define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
3196#define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
3197#define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
3198#define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
3199#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
3200#define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
3201#define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
3202#define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
3203#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
3204#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
3205#define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
3206#define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
3207#define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
3208#define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
3209#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
3210#define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
3211#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3212#define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3213#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3214#define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3215#define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
3216#define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
3217#define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
3218#define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
3219#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
3220#define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
3221#define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
3222#define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
3223#define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
3224#define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
3225#define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
3226#define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
3227#define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
3228#define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
3229#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
3230#define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
3231#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3232#define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3233#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3234#define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3235#define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
3236#define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
3237#define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
3238#define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
3239#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
3240#define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
3241#define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
3242#define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
3243#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
3244#define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
3245#define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
3246#define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
3247#define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
3248#define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
3249#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
3250#define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
3251#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3252#define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3253#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3254#define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3255#define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
3256#define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
3257#define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
3258#define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
3259#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3260#define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3261#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
3262#define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
3263#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3264#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3265#define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
3266#define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
3267#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
3268#define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3269#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3270#define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3271#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3272#define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3273#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3274#define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3275#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3276#define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3277#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3278#define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3279#define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
3280#define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
3281#define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
3282#define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
3283#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3284#define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3285#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
3286#define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
3287#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3288#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3289#define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
3290#define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
3291#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
3292#define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3293#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3294#define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3295#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3296#define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3297#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3298#define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3299#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3300#define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3301#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3302#define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3303#define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
3304#define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
3305#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
3306#define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
3307#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3308#define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3309#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
3310#define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
3311#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3312#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3313#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
3314#define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
3315#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3316#define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3317#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3318#define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3319#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3320#define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3321#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3322#define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3323#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3324#define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3325#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3326#define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3327#define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
3328#define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
3329#define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
3330#define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
3331#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3332#define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3333#define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
3334#define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
3335#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3336#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3337#define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
3338#define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
3339#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
3340#define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3341#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3342#define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3343#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3344#define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3345#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3346#define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3347#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x40000
3348#define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x12
3349#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x80000
3350#define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x13
3351#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x3f00000
3352#define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x14
3353#define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
3354#define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
3355#define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
3356#define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
3357#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
3358#define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
3359#define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
3360#define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
3361#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
3362#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
3363#define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
3364#define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
3365#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
3366#define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
3367#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
3368#define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
3369#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3370#define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3371#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3372#define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3373#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x40000
3374#define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x12
3375#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x80000
3376#define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x13
3377#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x3f00000
3378#define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x14
3379#define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
3380#define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
3381#define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
3382#define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
3383#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3384#define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3385#define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
3386#define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
3387#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3388#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3389#define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
3390#define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
3391#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
3392#define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3393#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3394#define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3395#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3396#define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3397#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3398#define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3399#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x40000
3400#define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x12
3401#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x80000
3402#define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x13
3403#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x3f00000
3404#define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x14
3405#define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
3406#define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
3407#define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
3408#define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
3409#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3410#define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3411#define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
3412#define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
3413#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3414#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3415#define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
3416#define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
3417#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3418#define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3419#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3420#define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3421#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3422#define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3423#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3424#define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3425#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x40000
3426#define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x12
3427#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x80000
3428#define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x13
3429#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x3f00000
3430#define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x14
3431#define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
3432#define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
3433#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3434#define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3435#define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
3436#define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
3437#define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
3438#define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
3439#define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
3440#define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
3441#define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
3442#define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
3443#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
3444#define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
3445#define MC_HUB_RDREQ_MCDS__MED_CREDITS_MASK 0xfe000000
3446#define MC_HUB_RDREQ_MCDS__MED_CREDITS__SHIFT 0x19
3447#define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
3448#define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
3449#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3450#define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3451#define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
3452#define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
3453#define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
3454#define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
3455#define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
3456#define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
3457#define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
3458#define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
3459#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
3460#define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
3461#define MC_HUB_RDREQ_MCDT__MED_CREDITS_MASK 0xfe000000
3462#define MC_HUB_RDREQ_MCDT__MED_CREDITS__SHIFT 0x19
3463#define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
3464#define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
3465#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3466#define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3467#define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
3468#define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
3469#define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
3470#define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
3471#define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
3472#define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
3473#define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
3474#define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
3475#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
3476#define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
3477#define MC_HUB_RDREQ_MCDU__MED_CREDITS_MASK 0xfe000000
3478#define MC_HUB_RDREQ_MCDU__MED_CREDITS__SHIFT 0x19
3479#define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
3480#define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
3481#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3482#define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3483#define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
3484#define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
3485#define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
3486#define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
3487#define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
3488#define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
3489#define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
3490#define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
3491#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
3492#define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
3493#define MC_HUB_RDREQ_MCDV__MED_CREDITS_MASK 0xfe000000
3494#define MC_HUB_RDREQ_MCDV__MED_CREDITS__SHIFT 0x19
3495#define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
3496#define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
3497#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3498#define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3499#define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
3500#define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
3501#define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
3502#define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
3503#define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
3504#define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
3505#define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
3506#define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
3507#define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
3508#define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
3509#define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
3510#define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
3511#define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
3512#define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
3513#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3514#define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3515#define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
3516#define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
3517#define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
3518#define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
3519#define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
3520#define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
3521#define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
3522#define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
3523#define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
3524#define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
3525#define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
3526#define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
3527#define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
3528#define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
3529#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3530#define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3531#define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
3532#define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
3533#define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
3534#define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
3535#define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
3536#define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
3537#define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
3538#define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
3539#define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
3540#define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
3541#define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
3542#define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
3543#define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
3544#define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
3545#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3546#define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3547#define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
3548#define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
3549#define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
3550#define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
3551#define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
3552#define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
3553#define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
3554#define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
3555#define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
3556#define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
3557#define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
3558#define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
3559#define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
3560#define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
3561#define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
3562#define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
3563#define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
3564#define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
3565#define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
3566#define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
3567#define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
3568#define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
3569#define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
3570#define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
3571#define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
3572#define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
3573#define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
3574#define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
3575#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
3576#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
3577#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3578#define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3579#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_MASK 0x1fc000
3580#define MC_HUB_WDP_CREDITS_MCDW__WR_URG__SHIFT 0xe
3581#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3582#define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3583#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
3584#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
3585#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3586#define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3587#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_MASK 0x1fc000
3588#define MC_HUB_WDP_CREDITS_MCDX__WR_URG__SHIFT 0xe
3589#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3590#define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3591#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
3592#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
3593#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3594#define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3595#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_MASK 0x1fc000
3596#define MC_HUB_WDP_CREDITS_MCDY__WR_URG__SHIFT 0xe
3597#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3598#define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3599#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
3600#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
3601#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3602#define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3603#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_MASK 0x1fc000
3604#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG__SHIFT 0xe
3605#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3606#define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3607#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
3608#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
3609#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3610#define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3611#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_MASK 0x1fc000
3612#define MC_HUB_WDP_CREDITS_MCDS__WR_URG__SHIFT 0xe
3613#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3614#define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3615#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
3616#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
3617#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3618#define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3619#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_MASK 0x1fc000
3620#define MC_HUB_WDP_CREDITS_MCDT__WR_URG__SHIFT 0xe
3621#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3622#define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3623#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
3624#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
3625#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3626#define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3627#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_MASK 0x1fc000
3628#define MC_HUB_WDP_CREDITS_MCDU__WR_URG__SHIFT 0xe
3629#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3630#define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3631#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
3632#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
3633#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3634#define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3635#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_MASK 0x1fc000
3636#define MC_HUB_WDP_CREDITS_MCDV__WR_URG__SHIFT 0xe
3637#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3638#define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3639#define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
3640#define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
3641#define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
3642#define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
3643#define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
3644#define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
3645#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
3646#define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
3647#define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
3648#define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
3649#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
3650#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
3651#define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
3652#define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
3653#define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
3654#define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
3655#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
3656#define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
3657#define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
3658#define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
3659#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3660#define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3661#define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
3662#define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
3663#define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
3664#define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
3665#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
3666#define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
3667#define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
3668#define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
3669#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
3670#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
3671#define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
3672#define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
3673#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
3674#define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
3675#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
3676#define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
3677#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3678#define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3679#define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
3680#define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
3681#define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
3682#define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
3683#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
3684#define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
3685#define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
3686#define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
3687#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
3688#define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
3689#define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
3690#define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
3691#define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
3692#define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
3693#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
3694#define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
3695#define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
3696#define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
3697#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3698#define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3699#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
3700#define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
3701#define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
3702#define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
3703#define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
3704#define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
3705#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
3706#define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
3707#define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
3708#define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
3709#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
3710#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
3711#define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
3712#define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
3713#define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
3714#define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
3715#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
3716#define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
3717#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3718#define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3719#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3720#define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3721#define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
3722#define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
3723#define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
3724#define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
3725#define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
3726#define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
3727#define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
3728#define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
3729#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
3730#define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
3731#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
3732#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
3733#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
3734#define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
3735#define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
3736#define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
3737#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
3738#define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
3739#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
3740#define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
3741#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
3742#define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
3743#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
3744#define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
3745#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
3746#define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
3747#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
3748#define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
3749#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
3750#define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
3751#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3752#define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3753#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3754#define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3755#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3756#define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3757#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3758#define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3759#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
3760#define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
3761#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
3762#define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
3763#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
3764#define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
3765#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
3766#define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
3767#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3768#define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3769#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3770#define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3771#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3772#define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3773#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3774#define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3775#define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
3776#define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
3777#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
3778#define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
3779#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
3780#define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
3781#define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
3782#define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
3783#define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
3784#define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
3785#define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
3786#define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
3787#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
3788#define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
3789#define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
3790#define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
3791#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
3792#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
3793#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
3794#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
3795#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
3796#define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
3797#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
3798#define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
3799#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
3800#define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
3801#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
3802#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
3803#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
3804#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
3805#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
3806#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
3807#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
3808#define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
3809#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
3810#define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
3811#define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
3812#define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
3813#define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
3814#define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
3815#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
3816#define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
3817#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
3818#define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
3819#define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
3820#define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
3821#define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
3822#define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
3823#define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
3824#define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
3825#define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
3826#define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
3827#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
3828#define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
3829#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
3830#define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
3831#define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
3832#define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
3833#define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
3834#define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
3835#define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
3836#define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
3837#define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
3838#define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
3839#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
3840#define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
3841#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
3842#define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
3843#define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
3844#define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
3845#define MC_SHARED_CHMAP__CHAN0_MASK 0xf
3846#define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
3847#define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
3848#define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
3849#define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
3850#define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
3851#define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
3852#define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
3853#define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
3854#define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
3855#define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
3856#define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
3857#define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
3858#define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
3859#define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
3860#define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
3861#define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
3862#define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
3863#define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
3864#define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
3865#define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
3866#define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
3867#define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
3868#define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
3869#define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
3870#define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
3871#define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
3872#define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
3873#define MC_RD_GRP_GFX__CP_MASK 0xf
3874#define MC_RD_GRP_GFX__CP__SHIFT 0x0
3875#define MC_RD_GRP_GFX__SH_MASK 0xf0
3876#define MC_RD_GRP_GFX__SH__SHIFT 0x4
3877#define MC_RD_GRP_GFX__TLS_MASK 0xf00
3878#define MC_RD_GRP_GFX__TLS__SHIFT 0x8
3879#define MC_RD_GRP_GFX__ACPG_MASK 0xf000
3880#define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
3881#define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
3882#define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
3883#define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
3884#define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
3885#define MC_RD_GRP_GFX__ISP_MASK 0xf000000
3886#define MC_RD_GRP_GFX__ISP__SHIFT 0x18
3887#define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
3888#define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
3889#define MC_WR_GRP_GFX__VIN0_MASK 0xf
3890#define MC_WR_GRP_GFX__VIN0__SHIFT 0x0
3891#define MC_WR_GRP_GFX__SH_MASK 0xf0
3892#define MC_WR_GRP_GFX__SH__SHIFT 0x4
3893#define MC_WR_GRP_GFX__ACPG_MASK 0xf00
3894#define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
3895#define MC_WR_GRP_GFX__ACPO_MASK 0xf000
3896#define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
3897#define MC_WR_GRP_GFX__ISP_MASK 0xf0000
3898#define MC_WR_GRP_GFX__ISP__SHIFT 0x10
3899#define MC_WR_GRP_GFX__VP8_MASK 0xf00000
3900#define MC_WR_GRP_GFX__VP8__SHIFT 0x14
3901#define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
3902#define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
3903#define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
3904#define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
3905#define MC_RD_GRP_SYS__RLC_MASK 0xf
3906#define MC_RD_GRP_SYS__RLC__SHIFT 0x0
3907#define MC_RD_GRP_SYS__VMC_MASK 0xf0
3908#define MC_RD_GRP_SYS__VMC__SHIFT 0x4
3909#define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
3910#define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
3911#define MC_RD_GRP_SYS__DMIF_MASK 0xf000
3912#define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
3913#define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
3914#define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
3915#define MC_RD_GRP_SYS__SMU_MASK 0xf00000
3916#define MC_RD_GRP_SYS__SMU__SHIFT 0x14
3917#define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
3918#define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
3919#define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
3920#define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
3921#define MC_WR_GRP_SYS__IH_MASK 0xf
3922#define MC_WR_GRP_SYS__IH__SHIFT 0x0
3923#define MC_WR_GRP_SYS__MCIF_MASK 0xf0
3924#define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
3925#define MC_WR_GRP_SYS__RLC_MASK 0xf00
3926#define MC_WR_GRP_SYS__RLC__SHIFT 0x8
3927#define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
3928#define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
3929#define MC_WR_GRP_SYS__SMU_MASK 0xf0000
3930#define MC_WR_GRP_SYS__SMU__SHIFT 0x10
3931#define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
3932#define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
3933#define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
3934#define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
3935#define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
3936#define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
3937#define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
3938#define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
3939#define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
3940#define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
3941#define MC_RD_GRP_OTH__HDP_MASK 0xf00
3942#define MC_RD_GRP_OTH__HDP__SHIFT 0x8
3943#define MC_RD_GRP_OTH__SEM_MASK 0xf000
3944#define MC_RD_GRP_OTH__SEM__SHIFT 0xc
3945#define MC_RD_GRP_OTH__UMC_MASK 0xf0000
3946#define MC_RD_GRP_OTH__UMC__SHIFT 0x10
3947#define MC_RD_GRP_OTH__UVD_MASK 0xf00000
3948#define MC_RD_GRP_OTH__UVD__SHIFT 0x14
3949#define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
3950#define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
3951#define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
3952#define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
3953#define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
3954#define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
3955#define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
3956#define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
3957#define MC_WR_GRP_OTH__HDP_MASK 0xf00
3958#define MC_WR_GRP_OTH__HDP__SHIFT 0x8
3959#define MC_WR_GRP_OTH__SEM_MASK 0xf000
3960#define MC_WR_GRP_OTH__SEM__SHIFT 0xc
3961#define MC_WR_GRP_OTH__UMC_MASK 0xf0000
3962#define MC_WR_GRP_OTH__UMC__SHIFT 0x10
3963#define MC_WR_GRP_OTH__UVD_MASK 0xf00000
3964#define MC_WR_GRP_OTH__UVD__SHIFT 0x14
3965#define MC_WR_GRP_OTH__XDP_MASK 0xf000000
3966#define MC_WR_GRP_OTH__XDP__SHIFT 0x18
3967#define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
3968#define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
3969#define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
3970#define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
3971#define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
3972#define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
3973#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
3974#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
3975#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
3976#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
3977#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
3978#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
3979#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3980#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3981#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3982#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3983#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
3984#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
3985#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
3986#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
3987#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
3988#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
3989#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
3990#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
3991#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
3992#define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
3993#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
3994#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
3995#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
3996#define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
3997#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3998#define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3999#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4000#define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4001#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4002#define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4003#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4004#define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4005#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4006#define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4007#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4008#define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4009#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4010#define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4011#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4012#define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4013#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
4014#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
4015#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
4016#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
4017#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
4018#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
4019#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
4020#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
4021#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
4022#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
4023#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
4024#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
4025#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
4026#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
4027#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
4028#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
4029#define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
4030#define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
4031#define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
4032#define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
4033#define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
4034#define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
4035#define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
4036#define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
4037#define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
4038#define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
4039#define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
4040#define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
4041#define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
4042#define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
4043#define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
4044#define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
4045#define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
4046#define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
4047#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
4048#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
4049#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
4050#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
4051#define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
4052#define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
4053#define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
4054#define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
4055#define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
4056#define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
4057#define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
4058#define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
4059#define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
4060#define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
4061#define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
4062#define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
4063#define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
4064#define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
4065#define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
4066#define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
4067#define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
4068#define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
4069#define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
4070#define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
4071#define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
4072#define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
4073#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
4074#define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
4075#define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
4076#define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
4077#define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
4078#define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
4079#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
4080#define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
4081#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
4082#define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
4083#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
4084#define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
4085#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
4086#define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
4087#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
4088#define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
4089#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
4090#define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
4091#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
4092#define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
4093#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
4094#define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
4095#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
4096#define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
4097#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
4098#define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
4099#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
4100#define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
4101#define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
4102#define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
4103#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
4104#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
4105#define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
4106#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
4107#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
4108#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
4109#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
4110#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
4111#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
4112#define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
4113#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
4114#define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
4115#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
4116#define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
4117#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4118#define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4119#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4120#define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4121#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4122#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4123#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4124#define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4125#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4126#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4127#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4128#define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4129#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4130#define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4131#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4132#define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4133#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4134#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4135#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4136#define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4137#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4138#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4139#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4140#define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4141#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4142#define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4143#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4144#define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4145#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4146#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4147#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4148#define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4149#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4150#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4151#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4152#define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4153#define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
4154#define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
4155#define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
4156#define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
4157#define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
4158#define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
4159#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
4160#define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
4161#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4162#define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4163#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4164#define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4165#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4166#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4167#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4168#define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4169#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4170#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4171#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4172#define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4173#define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
4174#define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
4175#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4176#define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4177#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4178#define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4179#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4180#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4181#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4182#define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4183#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4184#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4185#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4186#define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4187#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4188#define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4189#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4190#define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4191#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4192#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4193#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4194#define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4195#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4196#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4197#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4198#define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4199#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4200#define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4201#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4202#define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4203#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4204#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4205#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4206#define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4207#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4208#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4209#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4210#define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4211#define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
4212#define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
4213#define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
4214#define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
4215#define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
4216#define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
4217#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
4218#define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
4219#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4220#define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4221#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4222#define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4223#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4224#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4225#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4226#define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4227#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4228#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4229#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4230#define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4231#define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
4232#define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
4233#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
4234#define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
4235#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
4236#define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
4237#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
4238#define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
4239#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
4240#define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
4241#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
4242#define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
4243#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
4244#define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
4245#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
4246#define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
4247#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
4248#define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
4249#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
4250#define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
4251#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
4252#define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
4253#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
4254#define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
4255#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
4256#define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
4257#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
4258#define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
4259#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
4260#define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
4261#define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
4262#define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
4263#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
4264#define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
4265#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
4266#define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
4267#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
4268#define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
4269#define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
4270#define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
4271#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
4272#define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
4273#define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
4274#define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
4275#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
4276#define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
4277#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
4278#define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
4279#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
4280#define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
4281#define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
4282#define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
4283#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
4284#define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
4285#define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
4286#define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
4287#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
4288#define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
4289#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
4290#define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
4291#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
4292#define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
4293#define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
4294#define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
4295#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
4296#define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
4297#define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
4298#define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
4299#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
4300#define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
4301#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
4302#define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
4303#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
4304#define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
4305#define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
4306#define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
4307#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
4308#define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
4309#define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
4310#define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
4311#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
4312#define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
4313#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
4314#define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
4315#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
4316#define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
4317#define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
4318#define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
4319#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
4320#define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
4321#define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
4322#define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
4323#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
4324#define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
4325#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
4326#define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
4327#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
4328#define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
4329#define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
4330#define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
4331#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
4332#define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
4333#define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
4334#define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
4335#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
4336#define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
4337#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
4338#define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
4339#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
4340#define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
4341#define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
4342#define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
4343#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
4344#define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
4345#define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
4346#define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
4347#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
4348#define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
4349#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
4350#define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
4351#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
4352#define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
4353#define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
4354#define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
4355#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
4356#define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
4357#define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
4358#define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
4359#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
4360#define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
4361#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
4362#define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
4363#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
4364#define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
4365#define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
4366#define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
4367#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
4368#define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
4369#define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
4370#define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
4371#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
4372#define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
4373#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
4374#define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
4375#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
4376#define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
4377#define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
4378#define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
4379#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
4380#define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
4381#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
4382#define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
4383#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
4384#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
4385#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
4386#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
4387#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
4388#define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
4389#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
4390#define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
4391#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
4392#define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
4393#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
4394#define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
4395#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
4396#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
4397#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
4398#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
4399#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
4400#define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
4401#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
4402#define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
4403#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
4404#define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
4405#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
4406#define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
4407#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
4408#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
4409#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
4410#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
4411#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
4412#define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
4413#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
4414#define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
4415#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
4416#define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
4417#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
4418#define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
4419#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
4420#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
4421#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
4422#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
4423#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
4424#define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
4425#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
4426#define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
4427#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
4428#define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
4429#define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
4430#define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
4431#define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
4432#define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
4433#define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
4434#define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
4435#define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
4436#define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
4437#define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
4438#define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
4439#define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
4440#define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
4441#define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
4442#define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
4443#define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
4444#define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
4445#define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
4446#define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
4447#define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
4448#define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
4449#define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
4450#define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
4451#define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
4452#define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
4453#define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
4454#define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
4455#define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
4456#define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
4457#define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
4458#define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
4459#define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
4460#define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
4461#define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
4462#define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
4463#define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
4464#define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
4465#define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
4466#define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
4467#define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
4468#define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
4469#define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
4470#define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
4471#define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
4472#define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
4473#define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
4474#define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
4475#define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
4476#define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
4477#define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
4478#define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
4479#define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
4480#define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
4481#define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
4482#define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
4483#define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
4484#define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
4485#define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
4486#define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
4487#define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
4488#define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
4489#define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
4490#define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
4491#define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
4492#define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
4493#define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
4494#define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
4495#define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
4496#define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
4497#define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
4498#define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
4499#define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
4500#define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
4501#define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
4502#define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
4503#define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
4504#define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
4505#define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
4506#define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
4507#define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
4508#define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
4509#define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
4510#define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
4511#define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
4512#define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
4513#define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
4514#define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
4515#define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
4516#define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
4517#define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
4518#define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
4519#define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
4520#define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
4521#define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
4522#define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
4523#define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
4524#define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
4525#define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
4526#define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
4527#define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
4528#define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
4529#define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
4530#define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
4531#define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
4532#define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
4533#define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
4534#define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
4535#define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
4536#define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
4537#define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
4538#define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
4539#define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
4540#define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
4541#define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
4542#define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
4543#define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
4544#define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
4545#define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
4546#define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
4547#define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
4548#define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
4549#define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
4550#define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
4551#define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
4552#define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
4553#define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
4554#define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
4555#define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
4556#define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
4557#define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
4558#define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
4559#define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
4560#define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
4561#define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
4562#define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
4563#define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
4564#define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
4565#define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
4566#define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
4567#define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
4568#define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
4569#define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
4570#define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
4571#define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
4572#define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
4573#define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
4574#define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
4575#define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
4576#define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
4577#define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
4578#define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
4579#define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
4580#define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
4581#define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
4582#define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
4583#define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
4584#define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
4585#define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
4586#define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
4587#define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
4588#define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
4589#define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
4590#define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
4591#define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
4592#define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
4593#define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
4594#define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
4595#define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
4596#define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
4597#define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
4598#define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
4599#define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
4600#define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
4601#define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
4602#define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
4603#define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
4604#define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
4605#define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
4606#define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
4607#define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
4608#define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
4609#define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
4610#define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
4611#define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
4612#define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
4613#define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
4614#define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
4615#define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
4616#define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
4617#define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
4618#define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
4619#define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
4620#define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
4621#define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
4622#define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
4623#define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
4624#define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
4625#define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
4626#define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
4627#define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
4628#define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
4629#define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
4630#define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
4631#define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
4632#define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
4633#define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
4634#define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
4635#define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
4636#define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
4637#define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
4638#define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
4639#define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
4640#define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
4641#define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
4642#define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
4643#define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
4644#define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
4645#define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
4646#define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
4647#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
4648#define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
4649#define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
4650#define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
4651#define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
4652#define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
4653#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
4654#define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
4655#define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
4656#define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
4657#define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
4658#define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
4659#define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
4660#define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
4661#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
4662#define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
4663#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
4664#define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
4665#define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
4666#define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
4667#define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
4668#define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
4669#define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
4670#define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
4671#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
4672#define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
4673#define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
4674#define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
4675#define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
4676#define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
4677#define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
4678#define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
4679#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
4680#define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
4681#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
4682#define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
4683#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
4684#define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
4685#define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
4686#define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
4687#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
4688#define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
4689#define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
4690#define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
4691#define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
4692#define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
4693#define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
4694#define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
4695#define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
4696#define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
4697#define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
4698#define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
4699#define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
4700#define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
4701#define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
4702#define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
4703#define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
4704#define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
4705#define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
4706#define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
4707#define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
4708#define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
4709#define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
4710#define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
4711#define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
4712#define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
4713#define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
4714#define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
4715#define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
4716#define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
4717#define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
4718#define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
4719#define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
4720#define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
4721#define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
4722#define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
4723#define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
4724#define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
4725#define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
4726#define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
4727#define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
4728#define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
4729#define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
4730#define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
4731#define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
4732#define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
4733#define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
4734#define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
4735#define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
4736#define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
4737#define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
4738#define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
4739#define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
4740#define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
4741#define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
4742#define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
4743#define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
4744#define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
4745#define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
4746#define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
4747#define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
4748#define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
4749#define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
4750#define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
4751#define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
4752#define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
4753#define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
4754#define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
4755#define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
4756#define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
4757#define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
4758#define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
4759#define