| 1 | /* |
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| 2 | * GMC_8_2 Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef GMC_8_2_D_H |
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| 25 | #define GMC_8_2_D_H |
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| 26 | |
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| 27 | #define mmMC_CONFIG 0x800 |
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| 28 | #define mmMC_ARB_ATOMIC 0x9be |
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| 29 | #define mmMC_ARB_AGE_CNTL 0x9bf |
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| 30 | #define mmMC_ARB_RET_CREDITS2 0x9c0 |
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| 31 | #define mmMC_ARB_FED_CNTL 0x9c1 |
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| 32 | #define mmMC_ARB_GECC2_STATUS 0x9c2 |
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| 33 | #define mmMC_ARB_GECC2_MISC 0x9c3 |
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| 34 | #define mmMC_ARB_GECC2_DEBUG 0x9c4 |
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| 35 | #define mmMC_ARB_GECC2_DEBUG2 0x9c5 |
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| 36 | #define mmMC_ARB_PERF_CID 0x9c6 |
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| 37 | #define mmMC_ARB_SNOOP 0x9c7 |
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| 38 | #define mmMC_ARB_GRUB 0x9c8 |
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| 39 | #define mmMC_ARB_GECC2 0x9c9 |
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| 40 | #define mmMC_ARB_GECC2_CLI 0x9ca |
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| 41 | #define mmMC_ARB_ADDR_SWIZ0 0x9cb |
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| 42 | #define mmMC_ARB_ADDR_SWIZ1 0x9cc |
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| 43 | #define mmMC_ARB_MISC3 0x9cd |
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| 44 | #define mmMC_ARB_GRUB_PROMOTE 0x9ce |
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| 45 | #define mmMC_ARB_RTT_DATA 0x9cf |
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| 46 | #define mmMC_ARB_RTT_CNTL0 0x9d0 |
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| 47 | #define mmMC_ARB_RTT_CNTL1 0x9d1 |
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| 48 | #define mmMC_ARB_RTT_CNTL2 0x9d2 |
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| 49 | #define mmMC_ARB_RTT_DEBUG 0x9d3 |
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| 50 | #define mmMC_ARB_CAC_CNTL 0x9d4 |
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| 51 | #define mmMC_ARB_MISC2 0x9d5 |
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| 52 | #define mmMC_ARB_MISC 0x9d6 |
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| 53 | #define mmMC_ARB_BANKMAP 0x9d7 |
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| 54 | #define mmMC_ARB_RAMCFG 0x9d8 |
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| 55 | #define mmMC_ARB_POP 0x9d9 |
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| 56 | #define mmMC_ARB_MINCLKS 0x9da |
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| 57 | #define mmMC_ARB_SQM_CNTL 0x9db |
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| 58 | #define mmMC_ARB_ADDR_HASH 0x9dc |
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| 59 | #define mmMC_ARB_DRAM_TIMING 0x9dd |
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| 60 | #define mmMC_ARB_DRAM_TIMING2 0x9de |
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| 61 | #define mmMC_ARB_WTM_CNTL_RD 0x9df |
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| 62 | #define mmMC_ARB_WTM_CNTL_WR 0x9e0 |
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| 63 | #define mmMC_ARB_WTM_GRPWT_RD 0x9e1 |
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| 64 | #define mmMC_ARB_WTM_GRPWT_WR 0x9e2 |
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| 65 | #define mmMC_ARB_TM_CNTL_RD 0x9e3 |
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| 66 | #define mmMC_ARB_TM_CNTL_WR 0x9e4 |
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| 67 | #define mmMC_ARB_LAZY0_RD 0x9e5 |
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| 68 | #define mmMC_ARB_LAZY0_WR 0x9e6 |
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| 69 | #define mmMC_ARB_LAZY1_RD 0x9e7 |
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| 70 | #define mmMC_ARB_LAZY1_WR 0x9e8 |
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| 71 | #define mmMC_ARB_AGE_RD 0x9e9 |
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| 72 | #define mmMC_ARB_AGE_WR 0x9ea |
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| 73 | #define mmMC_ARB_RFSH_CNTL 0x9eb |
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| 74 | #define mmMC_ARB_RFSH_RATE 0x9ec |
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| 75 | #define mmMC_ARB_PM_CNTL 0x9ed |
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| 76 | #define mmMC_ARB_GDEC_RD_CNTL 0x9ee |
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| 77 | #define mmMC_ARB_GDEC_WR_CNTL 0x9ef |
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| 78 | #define mmMC_ARB_LM_RD 0x9f0 |
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| 79 | #define mmMC_ARB_LM_WR 0x9f1 |
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| 80 | #define mmMC_ARB_REMREQ 0x9f2 |
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| 81 | #define mmMC_ARB_REPLAY 0x9f3 |
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| 82 | #define mmMC_ARB_RET_CREDITS_RD 0x9f4 |
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| 83 | #define mmMC_ARB_RET_CREDITS_WR 0x9f5 |
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| 84 | #define mmMC_ARB_MAX_LAT_CID 0x9f6 |
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| 85 | #define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 |
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| 86 | #define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 |
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| 87 | #define mmMC_ARB_GRUB_REALTIME_RD 0x9f9 |
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| 88 | #define mmMC_ARB_CG 0x9fa |
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| 89 | #define mmMC_ARB_GRUB_REALTIME_WR 0x9fb |
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| 90 | #define mmMC_ARB_DRAM_TIMING_1 0x9fc |
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| 91 | #define mmMC_ARB_BUSY_STATUS 0x9fd |
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| 92 | #define mmMC_ARB_DRAM_TIMING2_1 0x9ff |
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| 93 | #define mmMC_ARB_GRUB2 0xa01 |
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| 94 | #define mmMC_ARB_BURST_TIME 0xa02 |
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| 95 | #define mmMC_CITF_XTRA_ENABLE 0x96d |
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| 96 | #define mmCC_MC_MAX_CHANNEL 0x96e |
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| 97 | #define mmMC_CG_CONFIG 0x96f |
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| 98 | #define mmMC_CITF_CNTL 0x970 |
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| 99 | #define mmMC_CITF_CREDITS_VM 0x971 |
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| 100 | #define mmMC_CITF_CREDITS_ARB_RD 0x972 |
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| 101 | #define mmMC_CITF_CREDITS_ARB_WR 0x973 |
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| 102 | #define mmMC_CITF_DAGB_CNTL 0x974 |
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| 103 | #define mmMC_CITF_INT_CREDITS 0x975 |
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| 104 | #define mmMC_CITF_RET_MODE 0x976 |
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| 105 | #define mmMC_CITF_DAGB_DLY 0x977 |
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| 106 | #define mmMC_RD_GRP_EXT 0x978 |
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| 107 | #define mmMC_WR_GRP_EXT 0x979 |
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| 108 | #define mmMC_CITF_REMREQ 0x97a |
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| 109 | #define mmMC_WR_TC0 0x97b |
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| 110 | #define mmMC_WR_TC1 0x97c |
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| 111 | #define mmMC_CITF_INT_CREDITS_WR 0x97d |
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| 112 | #define mmMC_CITF_CREDITS_ARB_RD2 0x97e |
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| 113 | #define mmMC_CITF_WTM_RD_CNTL 0x97f |
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| 114 | #define mmMC_CITF_WTM_WR_CNTL 0x980 |
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| 115 | #define mmMC_RD_CB 0x981 |
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| 116 | #define mmMC_RD_DB 0x982 |
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| 117 | #define mmMC_RD_TC0 0x983 |
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| 118 | #define mmMC_RD_TC1 0x984 |
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| 119 | #define mmMC_RD_HUB 0x985 |
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| 120 | #define mmMC_WR_CB 0x986 |
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| 121 | #define mmMC_WR_DB 0x987 |
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| 122 | #define mmMC_WR_HUB 0x988 |
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| 123 | #define mmMC_CITF_CREDITS_XBAR 0x989 |
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| 124 | #define mmMC_RD_GRP_LCL 0x98a |
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| 125 | #define mmMC_WR_GRP_LCL 0x98b |
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| 126 | #define mmMC_CITF_PERF_MON_CNTL2 0x98e |
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| 127 | #define mmMC_CITF_PERF_MON_RSLT2 0x991 |
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| 128 | #define mmMC_CITF_MISC_RD_CG 0x992 |
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| 129 | #define mmMC_CITF_MISC_WR_CG 0x993 |
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| 130 | #define mmMC_CITF_MISC_VM_CG 0x994 |
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| 131 | #define mmMC_HUB_MISC_POWER 0x82d |
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| 132 | #define mmMC_HUB_MISC_HUB_CG 0x82e |
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| 133 | #define mmMC_HUB_MISC_VM_CG 0x82f |
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| 134 | #define mmMC_HUB_MISC_SIP_CG 0x830 |
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| 135 | #define mmMC_HUB_MISC_STATUS 0x832 |
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| 136 | #define mmMC_HUB_MISC_OVERRIDE 0x833 |
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| 137 | #define mmMC_HUB_MISC_FRAMING 0x834 |
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| 138 | #define mmMC_HUB_WDP_CNTL 0x835 |
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| 139 | #define mmMC_HUB_WDP_ERR 0x836 |
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| 140 | #define mmMC_HUB_WDP_BP 0x837 |
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| 141 | #define mmMC_HUB_WDP_STATUS 0x838 |
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| 142 | #define mmMC_HUB_RDREQ_STATUS 0x839 |
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| 143 | #define mmMC_HUB_WRRET_STATUS 0x83a |
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| 144 | #define mmMC_HUB_RDREQ_CNTL 0x83b |
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| 145 | #define mmMC_HUB_WRRET_CNTL 0x83c |
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| 146 | #define mmMC_HUB_RDREQ_WTM_CNTL 0x83d |
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| 147 | #define mmMC_HUB_WDP_WTM_CNTL 0x83e |
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| 148 | #define mmMC_HUB_WDP_CREDITS 0x83f |
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| 149 | #define mmMC_HUB_WDP_CREDITS2 0x840 |
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| 150 | #define mmMC_HUB_WDP_GBL0 0x841 |
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| 151 | #define mmMC_HUB_WDP_GBL1 0x842 |
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| 152 | #define mmMC_HUB_RDREQ_CREDITS 0x844 |
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| 153 | #define mmMC_HUB_RDREQ_CREDITS2 0x845 |
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| 154 | #define mmMC_HUB_SHARED_DAGB_DLY 0x846 |
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| 155 | #define mmMC_HUB_MISC_IDLE_STATUS 0x847 |
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| 156 | #define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 |
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| 157 | #define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 |
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| 158 | #define mmMC_HUB_WDP_BYPASS_GBL0 0x84a |
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| 159 | #define mmMC_HUB_WDP_BYPASS_GBL1 0x84b |
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| 160 | #define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c |
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| 161 | #define mmMC_HUB_WDP_SH2 0x84d |
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| 162 | #define mmMC_HUB_WDP_SH3 0x84e |
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| 163 | #define mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0x84f |
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| 164 | #define mmMC_HUB_RDREQ_MCDW 0x851 |
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| 165 | #define mmMC_HUB_RDREQ_MCDX 0x852 |
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| 166 | #define mmMC_HUB_RDREQ_MCDY 0x853 |
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| 167 | #define mmMC_HUB_RDREQ_MCDZ 0x854 |
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| 168 | #define mmMC_HUB_RDREQ_SIP 0x855 |
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| 169 | #define mmMC_HUB_RDREQ_GBL0 0x856 |
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| 170 | #define mmMC_HUB_RDREQ_GBL1 0x857 |
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| 171 | #define mmMC_HUB_RDREQ_SMU 0x858 |
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| 172 | #define mmMC_HUB_RDREQ_SDMA0 0x859 |
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| 173 | #define mmMC_HUB_RDREQ_HDP 0x85a |
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| 174 | #define mmMC_HUB_RDREQ_SDMA1 0x85b |
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| 175 | #define mmMC_HUB_RDREQ_RLC 0x85c |
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| 176 | #define mmMC_HUB_RDREQ_SEM 0x85d |
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| 177 | #define mmMC_HUB_RDREQ_VCE0 0x85e |
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| 178 | #define mmMC_HUB_RDREQ_UMC 0x85f |
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| 179 | #define mmMC_HUB_RDREQ_UVD 0x860 |
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| 180 | #define mmMC_HUB_RDREQ_DMIF 0x862 |
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| 181 | #define mmMC_HUB_RDREQ_MCIF 0x863 |
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| 182 | #define mmMC_HUB_RDREQ_VMC 0x864 |
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| 183 | #define mmMC_HUB_RDREQ_VCEU0 0x865 |
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| 184 | #define mmMC_HUB_WDP_MCDW 0x866 |
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| 185 | #define mmMC_HUB_WDP_MCDX 0x867 |
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| 186 | #define mmMC_HUB_WDP_MCDY 0x868 |
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| 187 | #define mmMC_HUB_WDP_MCDZ 0x869 |
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| 188 | #define mmMC_HUB_WDP_SIP 0x86a |
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| 189 | #define mmMC_HUB_WDP_SDMA1 0x86b |
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| 190 | #define mmMC_HUB_WDP_SH0 0x86c |
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| 191 | #define mmMC_HUB_WDP_MCIF 0x86d |
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| 192 | #define mmMC_HUB_WDP_VCE0 0x86e |
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| 193 | #define mmMC_HUB_WDP_XDP 0x86f |
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| 194 | #define mmMC_HUB_WDP_IH 0x870 |
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| 195 | #define mmMC_HUB_WDP_RLC 0x871 |
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| 196 | #define mmMC_HUB_WDP_SEM 0x872 |
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| 197 | #define mmMC_HUB_WDP_SMU 0x873 |
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| 198 | #define mmMC_HUB_WDP_SH1 0x874 |
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| 199 | #define mmMC_HUB_WDP_UMC 0x875 |
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| 200 | #define mmMC_HUB_WDP_UVD 0x876 |
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| 201 | #define mmMC_HUB_WDP_HDP 0x877 |
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| 202 | #define mmMC_HUB_WDP_SDMA0 0x878 |
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| 203 | #define mmMC_HUB_WRRET_MCDW 0x879 |
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| 204 | #define mmMC_HUB_WRRET_MCDX 0x87a |
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| 205 | #define mmMC_HUB_WRRET_MCDY 0x87b |
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| 206 | #define mmMC_HUB_WRRET_MCDZ 0x87c |
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| 207 | #define mmMC_HUB_WDP_VCEU0 0x87d |
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| 208 | #define mmMC_HUB_WDP_XDMAM 0x87e |
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| 209 | #define mmMC_HUB_WDP_XDMA 0x87f |
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| 210 | #define mmMC_HUB_RDREQ_XDMAM 0x880 |
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| 211 | #define mmMC_HUB_RDREQ_ACPG 0x881 |
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| 212 | #define mmMC_HUB_RDREQ_ACPO 0x882 |
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| 213 | #define mmMC_HUB_RDREQ_SAMMSP 0x883 |
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| 214 | #define mmMC_HUB_RDREQ_VP8 0x884 |
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| 215 | #define mmMC_HUB_RDREQ_VP8U 0x885 |
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| 216 | #define mmMC_HUB_WDP_ACPG 0x886 |
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| 217 | #define mmMC_HUB_WDP_ACPO 0x887 |
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| 218 | #define mmMC_HUB_WDP_SAMMSP 0x888 |
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| 219 | #define mmMC_HUB_WDP_VP8 0x889 |
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| 220 | #define mmMC_HUB_WDP_VP8U 0x88a |
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| 221 | #define mmMC_HUB_RDREQ_ISP_SPM 0xde0 |
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| 222 | #define mmMC_HUB_RDREQ_ISP_MPM 0xde1 |
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| 223 | #define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 |
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| 224 | #define mmMC_HUB_WDP_ISP_SPM 0xde3 |
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| 225 | #define mmMC_HUB_WDP_ISP_MPS 0xde4 |
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| 226 | #define mmMC_HUB_WDP_ISP_MPM 0xde5 |
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| 227 | #define mmMC_HUB_WDP_ISP_CCPU 0xde6 |
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| 228 | #define mmMC_HUB_RDREQ_MCDS 0xde7 |
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| 229 | #define mmMC_HUB_RDREQ_MCDT 0xde8 |
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| 230 | #define mmMC_HUB_RDREQ_MCDU 0xde9 |
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| 231 | #define mmMC_HUB_RDREQ_MCDV 0xdea |
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| 232 | #define mmMC_HUB_WDP_MCDS 0xdeb |
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| 233 | #define mmMC_HUB_WDP_MCDT 0xdec |
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| 234 | #define mmMC_HUB_WDP_MCDU 0xded |
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| 235 | #define mmMC_HUB_WDP_MCDV 0xdee |
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| 236 | #define mmMC_HUB_WRRET_MCDS 0xdef |
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| 237 | #define mmMC_HUB_WRRET_MCDT 0xdf0 |
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| 238 | #define mmMC_HUB_WRRET_MCDU 0xdf1 |
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| 239 | #define mmMC_HUB_WRRET_MCDV 0xdf2 |
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| 240 | #define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 |
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| 241 | #define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 |
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| 242 | #define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 |
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| 243 | #define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 |
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| 244 | #define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 |
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| 245 | #define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 |
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| 246 | #define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 |
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| 247 | #define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa |
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| 248 | #define mmMC_HUB_WDP_BP2 0xdfb |
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| 249 | #define mmMC_HUB_RDREQ_VCE1 0xdfc |
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| 250 | #define mmMC_HUB_RDREQ_VCEU1 0xdfd |
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| 251 | #define mmMC_HUB_WDP_VCE1 0xdfe |
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| 252 | #define mmMC_HUB_WDP_VCEU1 0xdff |
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| 253 | #define mmMC_RPB_CONF 0x94d |
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| 254 | #define mmMC_RPB_IF_CONF 0x94e |
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| 255 | #define mmMC_RPB_DBG1 0x94f |
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| 256 | #define mmMC_RPB_EFF_CNTL 0x950 |
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| 257 | #define mmMC_RPB_ARB_CNTL 0x951 |
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| 258 | #define mmMC_RPB_BIF_CNTL 0x952 |
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| 259 | #define mmMC_RPB_WR_SWITCH_CNTL 0x953 |
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| 260 | #define mmMC_RPB_WR_COMBINE_CNTL 0x954 |
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| 261 | #define mmMC_RPB_RD_SWITCH_CNTL 0x955 |
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| 262 | #define mmMC_RPB_CID_QUEUE_WR 0x956 |
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| 263 | #define mmMC_RPB_CID_QUEUE_RD 0x957 |
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| 264 | #define mmMC_RPB_PERF_COUNTER_CNTL 0x958 |
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| 265 | #define mmMC_RPB_PERF_COUNTER_STATUS 0x959 |
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| 266 | #define mmMC_RPB_CID_QUEUE_EX 0x95a |
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| 267 | #define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b |
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| 268 | #define mmMC_RPB_TCI_CNTL 0x95c |
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| 269 | #define mmMC_RPB_TCI_CNTL2 0x95d |
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| 270 | #define mmMC_SHARED_CHMAP 0x801 |
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| 271 | #define mmMC_SHARED_CHREMAP 0x802 |
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| 272 | #define mmMC_RD_GRP_GFX 0x803 |
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| 273 | #define mmMC_WR_GRP_GFX 0x804 |
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| 274 | #define mmMC_RD_GRP_SYS 0x805 |
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| 275 | #define mmMC_WR_GRP_SYS 0x806 |
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| 276 | #define mmMC_RD_GRP_OTH 0x807 |
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| 277 | #define mmMC_WR_GRP_OTH 0x808 |
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| 278 | #define mmMC_VM_FB_LOCATION 0x809 |
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| 279 | #define mmMC_VM_AGP_TOP 0x80a |
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| 280 | #define mmMC_VM_AGP_BOT 0x80b |
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| 281 | #define mmMC_VM_AGP_BASE 0x80c |
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| 282 | #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d |
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| 283 | #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e |
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| 284 | #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f |
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| 285 | #define mmMC_VM_DC_WRITE_CNTL 0x810 |
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| 286 | #define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 |
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| 287 | #define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 |
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| 288 | #define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 |
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| 289 | #define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 |
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| 290 | #define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 |
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| 291 | #define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 |
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| 292 | #define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 |
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| 293 | #define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 |
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| 294 | #define mmMC_VM_MX_L1_TLB_CNTL 0x819 |
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| 295 | #define mmMC_VM_FB_OFFSET 0x81a |
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| 296 | #define mmMC_VM_STEERING 0x81b |
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| 297 | #define mmMC_SHARED_CHREMAP2 0x81c |
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| 298 | #define mmMC_SHARED_VF_ENABLE 0x81d |
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| 299 | #define mmMC_SHARED_VIRT_RESET_REQ 0x81e |
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| 300 | #define mmMC_SHARED_ACTIVE_FCN_ID 0x81f |
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| 301 | #define mmMC_CONFIG_MCD 0x828 |
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| 302 | #define mmMC_CG_CONFIG_MCD 0x829 |
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| 303 | #define mmMC_MEM_POWER_LS 0x82a |
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| 304 | #define mmMC_SHARED_BLACKOUT_CNTL 0x82b |
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| 305 | #define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 |
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| 306 | #define mmMC_VM_MB_L1_TLB1_DEBUG 0x892 |
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| 307 | #define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 |
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| 308 | #define mmMC_VM_MB_L1_TLB0_STATUS 0x895 |
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| 309 | #define mmMC_VM_MB_L1_TLB1_STATUS 0x896 |
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| 310 | #define mmMC_VM_MB_L1_TLB2_STATUS 0x897 |
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| 311 | #define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 |
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| 312 | #define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 |
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| 313 | #define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 |
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| 314 | #define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 |
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| 315 | #define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 |
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| 316 | #define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a |
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| 317 | #define mmMC_VM_MD_L1_TLB0_STATUS 0x99b |
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| 318 | #define mmMC_VM_MD_L1_TLB1_STATUS 0x99c |
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| 319 | #define mmMC_VM_MD_L1_TLB2_STATUS 0x99d |
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| 320 | #define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 |
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| 321 | #define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 |
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| 322 | #define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 |
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| 323 | #define mmMC_XPB_RTR_SRC_APRTR0 0x8cd |
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| 324 | #define mmMC_XPB_RTR_SRC_APRTR1 0x8ce |
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| 325 | #define mmMC_XPB_RTR_SRC_APRTR2 0x8cf |
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| 326 | #define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 |
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| 327 | #define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 |
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| 328 | #define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 |
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| 329 | #define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 |
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| 330 | #define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 |
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| 331 | #define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 |
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| 332 | #define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 |
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| 333 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 |
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| 334 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 |
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| 335 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 |
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| 336 | #define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da |
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| 337 | #define mmMC_XPB_RTR_DEST_MAP0 0x8db |
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| 338 | #define mmMC_XPB_RTR_DEST_MAP1 0x8dc |
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| 339 | #define mmMC_XPB_RTR_DEST_MAP2 0x8dd |
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| 340 | #define mmMC_XPB_RTR_DEST_MAP3 0x8de |
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| 341 | #define mmMC_XPB_RTR_DEST_MAP4 0x8df |
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| 342 | #define mmMC_XPB_RTR_DEST_MAP5 0x8e0 |
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| 343 | #define mmMC_XPB_RTR_DEST_MAP6 0x8e1 |
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| 344 | #define mmMC_XPB_RTR_DEST_MAP7 0x8e2 |
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| 345 | #define mmMC_XPB_RTR_DEST_MAP8 0x8e3 |
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| 346 | #define mmMC_XPB_RTR_DEST_MAP9 0x8e4 |
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| 347 | #define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 |
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| 348 | #define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 |
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| 349 | #define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 |
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| 350 | #define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 |
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| 351 | #define mmMC_XPB_CLG_CFG0 0x8e9 |
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| 352 | #define mmMC_XPB_CLG_CFG1 0x8ea |
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| 353 | #define mmMC_XPB_CLG_CFG2 0x8eb |
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| 354 | #define mmMC_XPB_CLG_CFG3 0x8ec |
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| 355 | #define mmMC_XPB_CLG_CFG4 0x8ed |
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| 356 | #define mmMC_XPB_CLG_CFG5 0x8ee |
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| 357 | #define mmMC_XPB_CLG_CFG6 0x8ef |
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| 358 | #define mmMC_XPB_CLG_CFG7 0x8f0 |
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| 359 | #define mmMC_XPB_CLG_CFG8 0x8f1 |
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| 360 | #define mmMC_XPB_CLG_CFG9 0x8f2 |
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| 361 | #define mmMC_XPB_CLG_CFG10 0x8f3 |
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| 362 | #define mmMC_XPB_CLG_CFG11 0x8f4 |
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| 363 | #define mmMC_XPB_CLG_CFG12 0x8f5 |
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| 364 | #define mmMC_XPB_CLG_CFG13 0x8f6 |
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| 365 | #define mmMC_XPB_CLG_CFG14 0x8f7 |
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| 366 | #define mmMC_XPB_CLG_CFG15 0x8f8 |
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| 367 | #define mmMC_XPB_CLG_CFG16 0x8f9 |
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| 368 | #define mmMC_XPB_CLG_CFG17 0x8fa |
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| 369 | #define mmMC_XPB_CLG_CFG18 0x8fb |
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| 370 | #define mmMC_XPB_CLG_CFG19 0x8fc |
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| 371 | #define 0x8fd |
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| 372 | #define mmMC_XPB_LB_ADDR 0x8fe |
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| 373 | #define mmMC_XPB_UNC_THRESH_HST 0x8ff |
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| 374 | #define mmMC_XPB_UNC_THRESH_SID 0x900 |
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| 375 | #define mmMC_XPB_WCB_STS 0x901 |
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| 376 | #define mmMC_XPB_WCB_CFG 0x902 |
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| 377 | #define mmMC_XPB_P2P_BAR_CFG 0x903 |
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| 378 | #define mmMC_XPB_P2P_BAR0 0x904 |
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| 379 | #define mmMC_XPB_P2P_BAR1 0x905 |
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| 380 | #define mmMC_XPB_P2P_BAR2 0x906 |
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| 381 | #define mmMC_XPB_P2P_BAR3 0x907 |
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| 382 | #define mmMC_XPB_P2P_BAR4 0x908 |
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| 383 | #define mmMC_XPB_P2P_BAR5 0x909 |
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| 384 | #define mmMC_XPB_P2P_BAR6 0x90a |
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| 385 | #define mmMC_XPB_P2P_BAR7 0x90b |
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| 386 | #define mmMC_XPB_P2P_BAR_SETUP 0x90c |
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| 387 | #define mmMC_XPB_P2P_BAR_DEBUG 0x90d |
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| 388 | #define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e |
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| 389 | #define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f |
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| 390 | #define mmMC_XPB_PEER_SYS_BAR0 0x910 |
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| 391 | #define mmMC_XPB_PEER_SYS_BAR1 0x911 |
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| 392 | #define mmMC_XPB_PEER_SYS_BAR2 0x912 |
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| 393 | #define mmMC_XPB_PEER_SYS_BAR3 0x913 |
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| 394 | #define mmMC_XPB_PEER_SYS_BAR4 0x914 |
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| 395 | #define mmMC_XPB_PEER_SYS_BAR5 0x915 |
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| 396 | #define mmMC_XPB_PEER_SYS_BAR6 0x916 |
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| 397 | #define mmMC_XPB_PEER_SYS_BAR7 0x917 |
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| 398 | #define mmMC_XPB_PEER_SYS_BAR8 0x918 |
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| 399 | #define mmMC_XPB_PEER_SYS_BAR9 0x919 |
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| 400 | #define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a |
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| 401 | #define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b |
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| 402 | #define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c |
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| 403 | #define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d |
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| 404 | #define mmMC_XPB_CLK_GAT 0x91e |
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| 405 | #define mmMC_XPB_INTF_CFG 0x91f |
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| 406 | #define mmMC_XPB_INTF_STS 0x920 |
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| 407 | #define mmMC_XPB_PIPE_STS 0x921 |
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| 408 | #define mmMC_XPB_SUB_CTRL 0x922 |
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| 409 | #define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 |
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| 410 | #define mmMC_XPB_PERF_KNOBS 0x924 |
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| 411 | #define mmMC_XPB_STICKY 0x925 |
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| 412 | #define mmMC_XPB_STICKY_W1C 0x926 |
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| 413 | #define mmMC_XPB_MISC_CFG 0x927 |
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| 414 | #define mmMC_XPB_CLG_CFG20 0x928 |
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| 415 | #define mmMC_XPB_CLG_CFG21 0x929 |
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| 416 | #define mmMC_XPB_CLG_CFG22 0x92a |
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| 417 | #define mmMC_XPB_CLG_CFG23 0x92b |
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| 418 | #define mmMC_XPB_CLG_CFG24 0x92c |
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| 419 | #define mmMC_XPB_CLG_CFG25 0x92d |
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| 420 | #define mmMC_XPB_CLG_CFG26 0x92e |
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| 421 | #define mmMC_XPB_CLG_CFG27 0x92f |
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| 422 | #define mmMC_XPB_CLG_CFG28 0x930 |
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| 423 | #define mmMC_XPB_CLG_CFG29 0x931 |
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| 424 | #define mmMC_XPB_CLG_CFG30 0x932 |
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| 425 | #define mmMC_XPB_CLG_CFG31 0x933 |
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| 426 | #define mmMC_XPB_INTF_CFG2 0x934 |
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| 427 | #define 0x935 |
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| 428 | #define mmMC_XPB_CLG_CFG32 0x936 |
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| 429 | #define mmMC_XPB_CLG_CFG33 0x937 |
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| 430 | #define mmMC_XPB_CLG_CFG34 0x938 |
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| 431 | #define mmMC_XPB_CLG_CFG35 0x939 |
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| 432 | #define mmMC_XPB_CLG_CFG36 0x93a |
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| 433 | #define mmMC_XBAR_ADDR_DEC 0xc80 |
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| 434 | #define mmMC_XBAR_REMOTE 0xc81 |
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| 435 | #define mmMC_XBAR_WRREQ_CREDIT 0xc82 |
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| 436 | #define mmMC_XBAR_RDREQ_CREDIT 0xc83 |
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| 437 | #define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 |
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| 438 | #define mmMC_XBAR_WRRET_CREDIT1 0xc85 |
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| 439 | #define mmMC_XBAR_WRRET_CREDIT2 0xc86 |
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| 440 | #define mmMC_XBAR_RDRET_CREDIT1 0xc87 |
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| 441 | #define mmMC_XBAR_RDRET_CREDIT2 0xc88 |
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| 442 | #define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 |
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| 443 | #define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a |
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| 444 | #define mmMC_XBAR_CHTRIREMAP 0xc8b |
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| 445 | #define mmMC_XBAR_TWOCHAN 0xc8c |
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| 446 | #define mmMC_XBAR_ARB 0xc8d |
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| 447 | #define mmMC_XBAR_ARB_MAX_BURST 0xc8e |
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| 448 | #define mmMC_XBAR_FIFO_MON_CNTL0 0xc8f |
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| 449 | #define mmMC_XBAR_FIFO_MON_CNTL1 0xc90 |
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| 450 | #define mmMC_XBAR_FIFO_MON_CNTL2 0xc91 |
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| 451 | #define mmMC_XBAR_FIFO_MON_RSLT0 0xc92 |
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| 452 | #define mmMC_XBAR_FIFO_MON_RSLT1 0xc93 |
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| 453 | #define mmMC_XBAR_FIFO_MON_RSLT2 0xc94 |
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| 454 | #define mmMC_XBAR_FIFO_MON_RSLT3 0xc95 |
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| 455 | #define mmMC_XBAR_FIFO_MON_MAX_THSH 0xc96 |
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| 456 | #define mmMC_XBAR_SPARE0 0xc97 |
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| 457 | #define mmMC_XBAR_SPARE1 0xc98 |
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| 458 | #define mmMC_CITF_PERFCOUNTER_LO 0x7a0 |
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| 459 | #define mmMC_HUB_PERFCOUNTER_LO 0x7a1 |
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| 460 | #define mmMC_RPB_PERFCOUNTER_LO 0x7a2 |
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| 461 | #define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 |
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| 462 | #define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 |
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| 463 | #define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 |
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| 464 | #define mmMC_ARB_PERFCOUNTER_LO 0x7a6 |
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| 465 | #define mmATC_PERFCOUNTER_LO 0x7a7 |
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| 466 | #define mmMC_CITF_PERFCOUNTER_HI 0x7a8 |
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| 467 | #define mmMC_HUB_PERFCOUNTER_HI 0x7a9 |
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| 468 | #define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa |
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| 469 | #define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab |
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| 470 | #define mmMC_RPB_PERFCOUNTER_HI 0x7ac |
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| 471 | #define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad |
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| 472 | #define mmMC_ARB_PERFCOUNTER_HI 0x7ae |
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| 473 | #define mmATC_PERFCOUNTER_HI 0x7af |
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| 474 | #define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 |
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| 475 | #define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 |
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| 476 | #define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 |
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| 477 | #define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 |
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| 478 | #define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 |
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| 479 | #define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 |
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| 480 | #define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 |
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| 481 | #define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 |
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| 482 | #define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 |
|---|
| 483 | #define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 |
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| 484 | #define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba |
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| 485 | #define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb |
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| 486 | #define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc |
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| 487 | #define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd |
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| 488 | #define mmMC_ARB_PERFCOUNTER2_CFG 0x7be |
|---|
| 489 | #define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf |
|---|
| 490 | #define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 |
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| 491 | #define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 |
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| 492 | #define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 |
|---|
| 493 | #define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 |
|---|
| 494 | #define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 |
|---|
| 495 | #define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 |
|---|
| 496 | #define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 |
|---|
| 497 | #define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 |
|---|
| 498 | #define mmATC_PERFCOUNTER0_CFG 0x7c8 |
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| 499 | #define mmATC_PERFCOUNTER1_CFG 0x7c9 |
|---|
| 500 | #define mmATC_PERFCOUNTER2_CFG 0x7ca |
|---|
| 501 | #define mmATC_PERFCOUNTER3_CFG 0x7cb |
|---|
| 502 | #define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc |
|---|
| 503 | #define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd |
|---|
| 504 | #define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce |
|---|
| 505 | #define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf |
|---|
| 506 | #define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 |
|---|
| 507 | #define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 |
|---|
| 508 | #define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 |
|---|
| 509 | #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 |
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| 510 | #define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 |
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| 511 | #define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 |
|---|
| 512 | #define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 |
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| 513 | #define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 |
|---|
| 514 | #define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 |
|---|
| 515 | #define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 |
|---|
| 516 | #define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da |
|---|
| 517 | #define mmMC_GRUB_PERFCOUNTER_LO 0x7e4 |
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| 518 | #define mmMC_GRUB_PERFCOUNTER_HI 0x7e5 |
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| 519 | #define mmMC_GRUB_PERFCOUNTER0_CFG 0x7e6 |
|---|
| 520 | #define mmMC_GRUB_PERFCOUNTER1_CFG 0x7e7 |
|---|
| 521 | #define mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0x7e8 |
|---|
| 522 | #define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 |
|---|
| 523 | #define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 |
|---|
| 524 | #define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 |
|---|
| 525 | #define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 |
|---|
| 526 | #define mmATC_VM_APERTURE0_CNTL 0xcc4 |
|---|
| 527 | #define mmATC_VM_APERTURE1_CNTL 0xcc5 |
|---|
| 528 | #define mmATC_VM_APERTURE0_CNTL2 0xcc6 |
|---|
| 529 | #define mmATC_VM_APERTURE1_CNTL2 0xcc7 |
|---|
| 530 | #define mmATC_ATS_CNTL 0xcc9 |
|---|
| 531 | #define mmATC_ATS_DEBUG 0xcca |
|---|
| 532 | #define mmATC_ATS_FAULT_DEBUG 0xccb |
|---|
| 533 | #define mmATC_ATS_STATUS 0xccc |
|---|
| 534 | #define mmATC_ATS_FAULT_CNTL 0xccd |
|---|
| 535 | #define mmATC_ATS_FAULT_STATUS_INFO 0xcce |
|---|
| 536 | #define mmATC_ATS_FAULT_STATUS_ADDR 0xccf |
|---|
| 537 | #define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 |
|---|
| 538 | #define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 |
|---|
| 539 | #define mmATC_ATS_FAULT_STATUS_INFO2 0xcd2 |
|---|
| 540 | #define mmATC_MISC_CG 0xcd4 |
|---|
| 541 | #define mmATC_L2_CNTL 0xcd5 |
|---|
| 542 | #define mmATC_L2_CNTL2 0xcd6 |
|---|
| 543 | #define mmATC_L2_DEBUG 0xcd7 |
|---|
| 544 | #define mmATC_L2_DEBUG2 0xcd8 |
|---|
| 545 | #define mmATC_L2_CACHE_DATA0 0xcd9 |
|---|
| 546 | #define mmATC_L2_CACHE_DATA1 0xcda |
|---|
| 547 | #define mmATC_L2_CACHE_DATA2 0xcdb |
|---|
| 548 | #define mmATC_L1_CNTL 0xcdc |
|---|
| 549 | #define mmATC_L1_ADDRESS_OFFSET 0xcdd |
|---|
| 550 | #define mmATC_L1RD_DEBUG_TLB 0xcde |
|---|
| 551 | #define mmATC_L1WR_DEBUG_TLB 0xcdf |
|---|
| 552 | #define mmATC_L1RD_STATUS 0xce0 |
|---|
| 553 | #define mmATC_L1WR_STATUS 0xce1 |
|---|
| 554 | #define mmATC_L1RD_DEBUG2_TLB 0xce2 |
|---|
| 555 | #define mmATC_L1WR_DEBUG2_TLB 0xce3 |
|---|
| 556 | #define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 |
|---|
| 557 | #define mmATC_VMID0_PASID_MAPPING 0xce7 |
|---|
| 558 | #define mmATC_VMID1_PASID_MAPPING 0xce8 |
|---|
| 559 | #define mmATC_VMID2_PASID_MAPPING 0xce9 |
|---|
| 560 | #define mmATC_VMID3_PASID_MAPPING 0xcea |
|---|
| 561 | #define mmATC_VMID4_PASID_MAPPING 0xceb |
|---|
| 562 | #define mmATC_VMID5_PASID_MAPPING 0xcec |
|---|
| 563 | #define mmATC_VMID6_PASID_MAPPING 0xced |
|---|
| 564 | #define mmATC_VMID7_PASID_MAPPING 0xcee |
|---|
| 565 | #define mmATC_VMID8_PASID_MAPPING 0xcef |
|---|
| 566 | #define mmATC_VMID9_PASID_MAPPING 0xcf0 |
|---|
| 567 | #define mmATC_VMID10_PASID_MAPPING 0xcf1 |
|---|
| 568 | #define mmATC_VMID11_PASID_MAPPING 0xcf2 |
|---|
| 569 | #define mmATC_VMID12_PASID_MAPPING 0xcf3 |
|---|
| 570 | #define mmATC_VMID13_PASID_MAPPING 0xcf4 |
|---|
| 571 | #define mmATC_VMID14_PASID_MAPPING 0xcf5 |
|---|
| 572 | #define mmATC_VMID15_PASID_MAPPING 0xcf6 |
|---|
| 573 | #define mmATC_ATS_VMID_STATUS 0xd07 |
|---|
| 574 | #define mmATC_ATS_SMU_STATUS 0xd08 |
|---|
| 575 | #define mmATC_L2_CNTL3 0xd09 |
|---|
| 576 | #define mmATC_L2_STATUS 0xd0a |
|---|
| 577 | #define mmATC_L2_STATUS2 0xd0b |
|---|
| 578 | #define mmGMCON_RENG_RAM_INDEX 0xd40 |
|---|
| 579 | #define mmGMCON_RENG_RAM_DATA 0xd41 |
|---|
| 580 | #define mmGMCON_RENG_EXECUTE 0xd42 |
|---|
| 581 | #define mmGMCON_MISC 0xd43 |
|---|
| 582 | #define mmGMCON_MISC2 0xd44 |
|---|
| 583 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 |
|---|
| 584 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 |
|---|
| 585 | #define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 |
|---|
| 586 | #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 |
|---|
| 587 | #define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 |
|---|
| 588 | #define mmGMCON_PERF_MON_CNTL0 0xd4a |
|---|
| 589 | #define mmGMCON_PERF_MON_CNTL1 0xd4b |
|---|
| 590 | #define mmGMCON_PERF_MON_RSLT0 0xd4c |
|---|
| 591 | #define mmGMCON_PERF_MON_RSLT1 0xd4d |
|---|
| 592 | #define mmGMCON_PGFSM_CONFIG 0xd4e |
|---|
| 593 | #define mmGMCON_PGFSM_WRITE 0xd4f |
|---|
| 594 | #define mmGMCON_PGFSM_READ 0xd50 |
|---|
| 595 | #define mmGMCON_MISC3 0xd51 |
|---|
| 596 | #define mmGMCON_MASK 0xd52 |
|---|
| 597 | #define mmGMCON_LPT_TARGET 0xd53 |
|---|
| 598 | #define mmGMCON_DEBUG 0xd5f |
|---|
| 599 | #define mmVM_L2_CNTL 0x500 |
|---|
| 600 | #define mmVM_L2_CNTL2 0x501 |
|---|
| 601 | #define mmVM_L2_CNTL3 0x502 |
|---|
| 602 | #define mmVM_L2_STATUS 0x503 |
|---|
| 603 | #define mmVM_CONTEXT0_CNTL 0x504 |
|---|
| 604 | #define mmVM_CONTEXT1_CNTL 0x505 |
|---|
| 605 | #define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 |
|---|
| 606 | #define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 |
|---|
| 607 | #define mmVM_CONTEXT0_CNTL2 0x50c |
|---|
| 608 | #define mmVM_CONTEXT1_CNTL2 0x50d |
|---|
| 609 | #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e |
|---|
| 610 | #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f |
|---|
| 611 | #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 |
|---|
| 612 | #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 |
|---|
| 613 | #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 |
|---|
| 614 | #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 |
|---|
| 615 | #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 |
|---|
| 616 | #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 |
|---|
| 617 | #define mmVM_INVALIDATE_REQUEST 0x51e |
|---|
| 618 | #define mmVM_INVALIDATE_RESPONSE 0x51f |
|---|
| 619 | #define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c |
|---|
| 620 | #define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d |
|---|
| 621 | #define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e |
|---|
| 622 | #define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f |
|---|
| 623 | #define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 |
|---|
| 624 | #define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 |
|---|
| 625 | #define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 |
|---|
| 626 | #define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 |
|---|
| 627 | #define mmVM_PRT_CNTL 0x534 |
|---|
| 628 | #define mmVM_CONTEXTS_DISABLE 0x535 |
|---|
| 629 | #define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 |
|---|
| 630 | #define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 |
|---|
| 631 | #define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 |
|---|
| 632 | #define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 |
|---|
| 633 | #define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e |
|---|
| 634 | #define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f |
|---|
| 635 | #define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 |
|---|
| 636 | #define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 |
|---|
| 637 | #define mmVM_FAULT_CLIENT_ID 0x54e |
|---|
| 638 | #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f |
|---|
| 639 | #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 |
|---|
| 640 | #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 |
|---|
| 641 | #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 |
|---|
| 642 | #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 |
|---|
| 643 | #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 |
|---|
| 644 | #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 |
|---|
| 645 | #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 |
|---|
| 646 | #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 |
|---|
| 647 | #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 |
|---|
| 648 | #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f |
|---|
| 649 | #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 |
|---|
| 650 | #define mmVM_DEBUG 0x56f |
|---|
| 651 | #define mmVM_L2_CG 0x570 |
|---|
| 652 | #define mmVM_L2_BANK_SELECT_MASKA 0x572 |
|---|
| 653 | #define mmVM_L2_BANK_SELECT_MASKB 0x573 |
|---|
| 654 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 |
|---|
| 655 | #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 |
|---|
| 656 | #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 |
|---|
| 657 | #define mmVM_L2_CNTL4 0x578 |
|---|
| 658 | #define mmVM_L2_BANK_SELECT_RESERVED_CID 0x579 |
|---|
| 659 | #define mmMC_VM_FB_SIZE_OFFSET_VF0 0xf980 |
|---|
| 660 | #define mmMC_VM_FB_SIZE_OFFSET_VF1 0xf981 |
|---|
| 661 | #define mmMC_VM_FB_SIZE_OFFSET_VF2 0xf982 |
|---|
| 662 | #define mmMC_VM_FB_SIZE_OFFSET_VF3 0xf983 |
|---|
| 663 | #define mmMC_VM_FB_SIZE_OFFSET_VF4 0xf984 |
|---|
| 664 | #define mmMC_VM_FB_SIZE_OFFSET_VF5 0xf985 |
|---|
| 665 | #define mmMC_VM_FB_SIZE_OFFSET_VF6 0xf986 |
|---|
| 666 | #define mmMC_VM_FB_SIZE_OFFSET_VF7 0xf987 |
|---|
| 667 | #define mmMC_VM_FB_SIZE_OFFSET_VF8 0xf988 |
|---|
| 668 | #define mmMC_VM_FB_SIZE_OFFSET_VF9 0xf989 |
|---|
| 669 | #define mmMC_VM_FB_SIZE_OFFSET_VF10 0xf98a |
|---|
| 670 | #define mmMC_VM_FB_SIZE_OFFSET_VF11 0xf98b |
|---|
| 671 | #define mmMC_VM_FB_SIZE_OFFSET_VF12 0xf98c |
|---|
| 672 | #define mmMC_VM_FB_SIZE_OFFSET_VF13 0xf98d |
|---|
| 673 | #define mmMC_VM_FB_SIZE_OFFSET_VF14 0xf98e |
|---|
| 674 | #define mmMC_VM_FB_SIZE_OFFSET_VF15 0xf98f |
|---|
| 675 | #define mmMC_VM_NB_MMIOBASE 0xf990 |
|---|
| 676 | #define mmMC_VM_NB_MMIOLIMIT 0xf991 |
|---|
| 677 | #define mmMC_VM_NB_PCI_CTRL 0xf992 |
|---|
| 678 | #define mmMC_VM_NB_PCI_ARB 0xf993 |
|---|
| 679 | #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0xf994 |
|---|
| 680 | #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0xf995 |
|---|
| 681 | #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0xf996 |
|---|
| 682 | #define mmMC_VM_NB_TOP_OF_DRAM3 0xf997 |
|---|
| 683 | #define mmMC_VM_MARC_BASE_LO_0 0xf998 |
|---|
| 684 | #define mmMC_VM_MARC_BASE_LO_1 0xf99e |
|---|
| 685 | #define mmMC_VM_MARC_BASE_LO_2 0xf9a4 |
|---|
| 686 | #define mmMC_VM_MARC_BASE_LO_3 0xf9aa |
|---|
| 687 | #define mmMC_VM_MARC_BASE_HI_0 0xf999 |
|---|
| 688 | #define mmMC_VM_MARC_BASE_HI_1 0xf99f |
|---|
| 689 | #define mmMC_VM_MARC_BASE_HI_2 0xf9a5 |
|---|
| 690 | #define mmMC_VM_MARC_BASE_HI_3 0xf9ab |
|---|
| 691 | #define mmMC_VM_MARC_RELOC_LO_0 0xf99a |
|---|
| 692 | #define mmMC_VM_MARC_RELOC_LO_1 0xf9a0 |
|---|
| 693 | #define mmMC_VM_MARC_RELOC_LO_2 0xf9a6 |
|---|
| 694 | #define mmMC_VM_MARC_RELOC_LO_3 0xf9ac |
|---|
| 695 | #define mmMC_VM_MARC_RELOC_HI_0 0xf99b |
|---|
| 696 | #define mmMC_VM_MARC_RELOC_HI_1 0xf9a1 |
|---|
| 697 | #define mmMC_VM_MARC_RELOC_HI_2 0xf9a7 |
|---|
| 698 | #define mmMC_VM_MARC_RELOC_HI_3 0xf9ad |
|---|
| 699 | #define mmMC_VM_MARC_LEN_LO_0 0xf99c |
|---|
| 700 | #define mmMC_VM_MARC_LEN_LO_1 0xf9a2 |
|---|
| 701 | #define mmMC_VM_MARC_LEN_LO_2 0xf9a8 |
|---|
| 702 | #define mmMC_VM_MARC_LEN_LO_3 0xf9ae |
|---|
| 703 | #define mmMC_VM_MARC_LEN_HI_0 0xf99d |
|---|
| 704 | #define mmMC_VM_MARC_LEN_HI_1 0xf9a3 |
|---|
| 705 | #define mmMC_VM_MARC_LEN_HI_2 0xf9a9 |
|---|
| 706 | #define mmMC_VM_MARC_LEN_HI_3 0xf9af |
|---|
| 707 | #define mmMC_VM_MARC_CNTL 0xf9b0 |
|---|
| 708 | #define mmMC_ARB_HARSH_EN_RD 0xdc0 |
|---|
| 709 | #define mmMC_ARB_HARSH_EN_WR 0xdc1 |
|---|
| 710 | #define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 |
|---|
| 711 | #define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 |
|---|
| 712 | #define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 |
|---|
| 713 | #define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 |
|---|
| 714 | #define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 |
|---|
| 715 | #define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 |
|---|
| 716 | #define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 |
|---|
| 717 | #define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 |
|---|
| 718 | #define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca |
|---|
| 719 | #define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb |
|---|
| 720 | #define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc |
|---|
| 721 | #define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd |
|---|
| 722 | #define mmMC_ARB_HARSH_BWCNT0_RD 0xdce |
|---|
| 723 | #define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf |
|---|
| 724 | #define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 |
|---|
| 725 | #define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 |
|---|
| 726 | #define mmMC_ARB_HARSH_SAT0_RD 0xdd2 |
|---|
| 727 | #define mmMC_ARB_HARSH_SAT0_WR 0xdd3 |
|---|
| 728 | #define mmMC_ARB_HARSH_SAT1_RD 0xdd4 |
|---|
| 729 | #define mmMC_ARB_HARSH_SAT1_WR 0xdd5 |
|---|
| 730 | #define mmMC_ARB_HARSH_CTL_RD 0xdd6 |
|---|
| 731 | #define mmMC_ARB_HARSH_CTL_WR 0xdd7 |
|---|
| 732 | #define mmMC_ARB_GRUB_PRIORITY1_RD 0xdd8 |
|---|
| 733 | #define mmMC_ARB_GRUB_PRIORITY1_WR 0xdd9 |
|---|
| 734 | #define mmMC_ARB_GRUB_PRIORITY2_RD 0xdda |
|---|
| 735 | #define mmMC_ARB_GRUB_PRIORITY2_WR 0xddb |
|---|
| 736 | #define mmMC_FUS_DRAM0_CS0_BASE 0xa05 |
|---|
| 737 | #define mmMC_FUS_DRAM1_CS0_BASE 0xa06 |
|---|
| 738 | #define mmMC_FUS_DRAM0_CS1_BASE 0xa07 |
|---|
| 739 | #define mmMC_FUS_DRAM1_CS1_BASE 0xa08 |
|---|
| 740 | #define mmMC_FUS_DRAM0_CS2_BASE 0xa09 |
|---|
| 741 | #define mmMC_FUS_DRAM1_CS2_BASE 0xa0a |
|---|
| 742 | #define mmMC_FUS_DRAM0_CS3_BASE 0xa0b |
|---|
| 743 | #define mmMC_FUS_DRAM1_CS3_BASE 0xa0c |
|---|
| 744 | #define mmMC_FUS_DRAM0_CS01_MASK 0xa0d |
|---|
| 745 | #define mmMC_FUS_DRAM1_CS01_MASK 0xa0e |
|---|
| 746 | #define mmMC_FUS_DRAM0_CS23_MASK 0xa0f |
|---|
| 747 | #define mmMC_FUS_DRAM1_CS23_MASK 0xa10 |
|---|
| 748 | #define mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0xa11 |
|---|
| 749 | #define mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0xa12 |
|---|
| 750 | #define mmMC_FUS_DRAM0_CTL_BASE 0xa13 |
|---|
| 751 | #define mmMC_FUS_DRAM1_CTL_BASE 0xa14 |
|---|
| 752 | #define mmMC_FUS_DRAM0_CTL_LIMIT 0xa15 |
|---|
| 753 | #define mmMC_FUS_DRAM1_CTL_LIMIT 0xa16 |
|---|
| 754 | #define mmMC_FUS_DRAM_CTL_HIGH_01 0xa17 |
|---|
| 755 | #define mmMC_FUS_DRAM_CTL_HIGH_23 0xa18 |
|---|
| 756 | #define mmMC_FUS_DRAM_MODE 0xa19 |
|---|
| 757 | #define mmMC_FUS_DRAM_APER_BASE 0xa1a |
|---|
| 758 | #define mmMC_FUS_DRAM_APER_TOP 0xa1b |
|---|
| 759 | #define mmMC_FUS_DRAM_APER_DEF 0xa1e |
|---|
| 760 | #define mmMC_FUS_ARB_GARLIC_ISOC_PRI 0xa1f |
|---|
| 761 | #define mmMC_FUS_ARB_GARLIC_CNTL 0xa20 |
|---|
| 762 | #define mmMC_FUS_ARB_GARLIC_WR_PRI 0xa21 |
|---|
| 763 | #define mmMC_FUS_ARB_GARLIC_WR_PRI2 0xa22 |
|---|
| 764 | #define mmMC_CG_DATAPORT 0xa32 |
|---|
| 765 | #define mmMC_GRUB_PROBE_MAP 0xa33 |
|---|
| 766 | #define mmMC_GRUB_POST_PROBE_DELAY 0xa34 |
|---|
| 767 | #define mmMC_GRUB_PROBE_CREDITS 0xa35 |
|---|
| 768 | #define mmMC_GRUB_FEATURES 0xa36 |
|---|
| 769 | #define mmMC_GRUB_TX_CREDITS 0xa37 |
|---|
| 770 | #define mmMC_GRUB_TCB_INDEX 0xa38 |
|---|
| 771 | #define mmMC_GRUB_TCB_DATA_LO 0xa39 |
|---|
| 772 | #define mmMC_GRUB_TCB_DATA_HI 0xa3a |
|---|
| 773 | #define mmMCIF_WB_BUFMGR_SW_CONTROL 0x5e78 |
|---|
| 774 | #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x5e78 |
|---|
| 775 | #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x5eb8 |
|---|
| 776 | #define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x5ef8 |
|---|
| 777 | #define mmMCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 |
|---|
| 778 | #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x5e79 |
|---|
| 779 | #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x5eb9 |
|---|
| 780 | #define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x5ef9 |
|---|
| 781 | #define mmMCIF_WB_BUFMGR_STATUS 0x5e7a |
|---|
| 782 | #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x5e7a |
|---|
| 783 | #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x5eba |
|---|
| 784 | #define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x5efa |
|---|
| 785 | #define mmMCIF_WB_BUF_PITCH 0x5e7b |
|---|
| 786 | #define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x5e7b |
|---|
| 787 | #define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x5ebb |
|---|
| 788 | #define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x5efb |
|---|
| 789 | #define mmMCIF_WB_BUF_1_STATUS 0x5e7c |
|---|
| 790 | #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x5e7c |
|---|
| 791 | #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x5ebc |
|---|
| 792 | #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x5efc |
|---|
| 793 | #define mmMCIF_WB_BUF_1_STATUS2 0x5e7d |
|---|
| 794 | #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x5e7d |
|---|
| 795 | #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x5ebd |
|---|
| 796 | #define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x5efd |
|---|
| 797 | #define mmMCIF_WB_BUF_2_STATUS 0x5e7e |
|---|
| 798 | #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x5e7e |
|---|
| 799 | #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x5ebe |
|---|
| 800 | #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x5efe |
|---|
| 801 | #define mmMCIF_WB_BUF_2_STATUS2 0x5e7f |
|---|
| 802 | #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x5e7f |
|---|
| 803 | #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x5ebf |
|---|
| 804 | #define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x5eff |
|---|
| 805 | #define mmMCIF_WB_BUF_3_STATUS 0x5e80 |
|---|
| 806 | #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x5e80 |
|---|
| 807 | #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x5ec0 |
|---|
| 808 | #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x5f00 |
|---|
| 809 | #define mmMCIF_WB_BUF_3_STATUS2 0x5e81 |
|---|
| 810 | #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x5e81 |
|---|
| 811 | #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x5ec1 |
|---|
| 812 | #define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x5f01 |
|---|
| 813 | #define mmMCIF_WB_BUF_4_STATUS 0x5e82 |
|---|
| 814 | #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x5e82 |
|---|
| 815 | #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x5ec2 |
|---|
| 816 | #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x5f02 |
|---|
| 817 | #define mmMCIF_WB_BUF_4_STATUS2 0x5e83 |
|---|
| 818 | #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x5e83 |
|---|
| 819 | #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x5ec3 |
|---|
| 820 | #define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x5f03 |
|---|
| 821 | #define mmMCIF_WB_ARBITRATION_CONTROL 0x5e84 |
|---|
| 822 | #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x5e84 |
|---|
| 823 | #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x5ec4 |
|---|
| 824 | #define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x5f04 |
|---|
| 825 | #define mmMCIF_WB_URGENCY_WATERMARK 0x5e85 |
|---|
| 826 | #define mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0x5e85 |
|---|
| 827 | #define mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0x5ec5 |
|---|
| 828 | #define mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0x5f05 |
|---|
| 829 | #define mmMCIF_WB_TEST_DEBUG_INDEX 0x5e86 |
|---|
| 830 | #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x5e86 |
|---|
| 831 | #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x5ec6 |
|---|
| 832 | #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x5f06 |
|---|
| 833 | #define mmMCIF_WB_TEST_DEBUG_DATA 0x5e87 |
|---|
| 834 | #define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x5e87 |
|---|
| 835 | #define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x5ec7 |
|---|
| 836 | #define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x5f07 |
|---|
| 837 | #define mmMCIF_WB_BUF_1_ADDR_Y 0x5e88 |
|---|
| 838 | #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x5e88 |
|---|
| 839 | #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x5ec8 |
|---|
| 840 | #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x5f08 |
|---|
| 841 | #define mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 |
|---|
| 842 | #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5e89 |
|---|
| 843 | #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5ec9 |
|---|
| 844 | #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x5f09 |
|---|
| 845 | #define mmMCIF_WB_BUF_1_ADDR_C 0x5e8a |
|---|
| 846 | #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x5e8a |
|---|
| 847 | #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x5eca |
|---|
| 848 | #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x5f0a |
|---|
| 849 | #define mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b |
|---|
| 850 | #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5e8b |
|---|
| 851 | #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5ecb |
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| 852 | #define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x5f0b |
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| 853 | #define mmMCIF_WB_BUF_2_ADDR_Y 0x5e8c |
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| 854 | #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x5e8c |
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| 855 | #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x5ecc |
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| 856 | #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x5f0c |
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| 857 | #define mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d |
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| 858 | #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5e8d |
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| 859 | #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5ecd |
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| 860 | #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x5f0d |
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| 861 | #define mmMCIF_WB_BUF_2_ADDR_C 0x5e8e |
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| 862 | #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x5e8e |
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| 863 | #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x5ece |
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| 864 | #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x5f0e |
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| 865 | #define mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f |
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| 866 | #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5e8f |
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| 867 | #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5ecf |
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| 868 | #define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x5f0f |
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| 869 | #define mmMCIF_WB_BUF_3_ADDR_Y 0x5e90 |
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| 870 | #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x5e90 |
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| 871 | #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x5ed0 |
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| 872 | #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x5f10 |
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| 873 | #define mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 |
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| 874 | #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5e91 |
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| 875 | #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5ed1 |
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| 876 | #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x5f11 |
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| 877 | #define mmMCIF_WB_BUF_3_ADDR_C 0x5e92 |
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| 878 | #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x5e92 |
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| 879 | #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x5ed2 |
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| 880 | #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x5f12 |
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| 881 | #define mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 |
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| 882 | #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5e93 |
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| 883 | #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5ed3 |
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| 884 | #define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x5f13 |
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| 885 | #define mmMCIF_WB_BUF_4_ADDR_Y 0x5e94 |
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| 886 | #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x5e94 |
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| 887 | #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x5ed4 |
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| 888 | #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x5f14 |
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| 889 | #define mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 |
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| 890 | #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5e95 |
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| 891 | #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5ed5 |
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| 892 | #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x5f15 |
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| 893 | #define mmMCIF_WB_BUF_4_ADDR_C 0x5e96 |
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| 894 | #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x5e96 |
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| 895 | #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x5ed6 |
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| 896 | #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x5f16 |
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| 897 | #define mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 |
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| 898 | #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5e97 |
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| 899 | #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5ed7 |
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| 900 | #define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x5f17 |
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| 901 | #define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 |
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| 902 | #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x5e98 |
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| 903 | #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x5ed8 |
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| 904 | #define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x5f18 |
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| 905 | #define mmMCIF_WB_HVVMID_CONTROL 0x5e99 |
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| 906 | #define mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0x5e99 |
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| 907 | #define mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0x5ed9 |
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| 908 | #define mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0x5f19 |
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| 909 | |
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| 910 | #endif /* GMC_8_2_D_H */ |
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| 911 | |
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