1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _mmhub_1_0_SH_MASK_HEADER
22#define _mmhub_1_0_SH_MASK_HEADER
23
24
25// addressBlock: mmhub_dagbdec
26//DAGB0_RDCLI0
27#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0
28#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4
30#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8
31#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd
33#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
34#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16
35#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a
37#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L
38#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
39#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L
40#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L
41#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
42#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L
43#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
44#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L
45#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
46#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L
47//DAGB0_RDCLI1
48#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0
49#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
50#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4
51#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8
52#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
53#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd
54#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
55#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16
56#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
57#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a
58#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L
59#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
60#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L
61#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L
62#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
63#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L
64#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
65#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L
66#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
67#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L
68//DAGB0_RDCLI2
69#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0
70#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
71#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4
72#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8
73#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
74#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd
75#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
76#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16
77#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
78#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a
79#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L
80#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
81#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L
82#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L
83#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
84#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L
85#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
86#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L
87#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
88#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L
89//DAGB0_RDCLI3
90#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0
91#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
92#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4
93#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8
94#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
95#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd
96#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
97#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16
98#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
99#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a
100#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L
101#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
102#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L
103#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L
104#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
105#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L
106#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
107#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L
108#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
109#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L
110//DAGB0_RDCLI4
111#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0
112#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
113#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4
114#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8
115#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
116#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd
117#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
118#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16
119#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
120#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a
121#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L
122#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
123#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L
124#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L
125#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
126#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L
127#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
128#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L
129#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
130#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L
131//DAGB0_RDCLI5
132#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0
133#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
134#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4
135#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8
136#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
137#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd
138#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
139#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16
140#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
141#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a
142#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L
143#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
144#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L
145#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L
146#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
147#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L
148#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
149#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L
150#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
151#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L
152//DAGB0_RDCLI6
153#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0
154#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
155#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4
156#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8
157#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
158#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd
159#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
160#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16
161#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
162#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a
163#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L
164#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
165#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L
166#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L
167#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
168#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L
169#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
170#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L
171#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
172#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L
173//DAGB0_RDCLI7
174#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0
175#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
176#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4
177#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8
178#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
179#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd
180#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
181#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16
182#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
183#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a
184#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L
185#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
186#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L
187#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L
188#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
189#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L
190#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
191#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L
192#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
193#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L
194//DAGB0_RDCLI8
195#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0
196#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
197#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4
198#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8
199#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
200#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd
201#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
202#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16
203#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
204#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a
205#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L
206#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
207#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L
208#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L
209#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
210#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L
211#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
212#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L
213#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
214#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L
215//DAGB0_RDCLI9
216#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0
217#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
218#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4
219#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8
220#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
221#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd
222#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
223#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16
224#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
225#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a
226#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L
227#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
228#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L
229#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L
230#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
231#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L
232#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
233#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L
234#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
235#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L
236//DAGB0_RDCLI10
237#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0
238#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
239#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4
240#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8
241#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
242#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd
243#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
244#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16
245#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
246#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a
247#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L
248#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
249#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L
250#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L
251#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
252#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L
253#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
254#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L
255#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
256#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L
257//DAGB0_RDCLI11
258#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0
259#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
260#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4
261#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8
262#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
263#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd
264#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
265#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16
266#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
267#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a
268#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L
269#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
270#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L
271#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L
272#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
273#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L
274#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
275#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L
276#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
277#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L
278//DAGB0_RDCLI12
279#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0
280#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
281#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4
282#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8
283#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
284#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd
285#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
286#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16
287#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
288#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a
289#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L
290#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
291#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L
292#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L
293#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
294#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L
295#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
296#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L
297#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
298#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L
299//DAGB0_RDCLI13
300#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0
301#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
302#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4
303#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8
304#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
305#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd
306#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
307#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16
308#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
309#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a
310#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L
311#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
312#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L
313#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L
314#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
315#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L
316#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
317#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L
318#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
319#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L
320//DAGB0_RDCLI14
321#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0
322#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
323#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4
324#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8
325#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
326#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd
327#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
328#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16
329#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
330#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a
331#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L
332#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
333#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L
334#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L
335#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
336#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L
337#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
338#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L
339#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
340#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L
341//DAGB0_RDCLI15
342#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0
343#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
344#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4
345#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8
346#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
347#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd
348#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
349#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16
350#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
351#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a
352#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L
353#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
354#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L
355#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L
356#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
357#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L
358#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
359#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L
360#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
361#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L
362//DAGB0_RD_CNTL
363#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0
364#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
365#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
366#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
367#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11
368#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
369#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
370#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
371#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
372#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
373#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
374#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
375#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
376#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
377//DAGB0_RD_GMI_CNTL
378#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
379#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6
380#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
381#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
382#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
383#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
384#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
385#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
386//DAGB0_RD_ADDR_DAGB
387#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
388#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
389#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
390#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
391#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
392#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
393#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
394#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
395//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
396#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
397#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
398#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
399#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
400#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
401#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
402#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
403#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
404#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
405#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
406#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
407#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
408#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
409#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
410#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
411#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
412//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
413#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
414#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
415#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
416#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
417#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
418#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
419#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
420#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
421#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
422#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
423#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
424#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
425#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
426#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
427#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
428#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
429//DAGB0_RD_CGTT_CLK_CTRL
430#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
431#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
432#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
433#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
434#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
435#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
436#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
437#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
438#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
439#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
440#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
441#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
442#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
443#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
444#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
445#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
446//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
447#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
448#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
449#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
450#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
451#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
452#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
453#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
454#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
455#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
456#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
457#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
458#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
459#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
460#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
461#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
462#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
463//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
464#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
465#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
466#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
467#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
468#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
469#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
470#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
471#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
472#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
473#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
474#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
475#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
476#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
477#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
478#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
479#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
480//DAGB0_RD_ADDR_DAGB_MAX_BURST0
481#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
482#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
483#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
484#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
485#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
486#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
487#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
488#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
489#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
490#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
491#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
492#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
493#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
494#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
495#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
496#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
497//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
498#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
499#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
500#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
501#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
502#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
503#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
504#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
505#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
506#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
507#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
508#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
509#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
510#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
511#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
512#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
513#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
514//DAGB0_RD_ADDR_DAGB_MAX_BURST1
515#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
516#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
517#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
518#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
519#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
520#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
521#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
522#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
523#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
524#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
525#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
526#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
527#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
528#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
529#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
530#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
531//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
532#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
533#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
534#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
535#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
536#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
537#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
538#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
539#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
540#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
541#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
542#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
543#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
544#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
545#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
546#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
547#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
548//DAGB0_RD_VC0_CNTL
549#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
550#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
551#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
552#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
553#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
554#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
555#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
556#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
557#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
558#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
559#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
560#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
561#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
562#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
563#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
564#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
565//DAGB0_RD_VC1_CNTL
566#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
567#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
568#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
569#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
570#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
571#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
572#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
573#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
574#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
575#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
576#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
577#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
578#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
579#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
580#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
581#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
582//DAGB0_RD_VC2_CNTL
583#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
584#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
585#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
586#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
587#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
588#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
589#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
590#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
591#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
592#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
593#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
594#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
595#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
596#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
597#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
598#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
599//DAGB0_RD_VC3_CNTL
600#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
601#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
602#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
603#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
604#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
605#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
606#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
607#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
608#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
609#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
610#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
611#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
612#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
613#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
614#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
615#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
616//DAGB0_RD_VC4_CNTL
617#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
618#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
619#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
620#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
621#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
622#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
623#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
624#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
625#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
626#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
627#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
628#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
629#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
630#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
631#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
632#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
633//DAGB0_RD_VC5_CNTL
634#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
635#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
636#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
637#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
638#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
639#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
640#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
641#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
642#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
643#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
644#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
645#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
646#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
647#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
648#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
649#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
650//DAGB0_RD_VC6_CNTL
651#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
652#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
653#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
654#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
655#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
656#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
657#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
658#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
659#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
660#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
661#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
662#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
663#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
664#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
665#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
666#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
667//DAGB0_RD_VC7_CNTL
668#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
669#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
670#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
671#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
672#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
673#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
674#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
675#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
676#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
677#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
678#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
679#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
680#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
681#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
682#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
683#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
684//DAGB0_RD_CNTL_MISC
685#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
686#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
687#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
688#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
689#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
690#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
691#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
692#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
693#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
694#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
695#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
696#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
697//DAGB0_RD_TLB_CREDIT
698#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0
699#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5
700#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
701#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf
702#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14
703#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19
704#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
705#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
706#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
707#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
708#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
709#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
710//DAGB0_RDCLI_ASK_PENDING
711#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
712#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
713//DAGB0_RDCLI_GO_PENDING
714#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
715#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
716//DAGB0_RDCLI_GBLSEND_PENDING
717#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
718#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
719//DAGB0_RDCLI_TLB_PENDING
720#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
721#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
722//DAGB0_RDCLI_OARB_PENDING
723#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
724#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
725//DAGB0_RDCLI_OSD_PENDING
726#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
727#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
728//DAGB0_WRCLI0
729#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0
730#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
731#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4
732#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8
733#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
734#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd
735#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
736#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16
737#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
738#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a
739#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L
740#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
741#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L
742#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L
743#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
744#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L
745#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
746#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L
747#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
748#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L
749//DAGB0_WRCLI1
750#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0
751#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
752#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4
753#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8
754#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
755#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd
756#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
757#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16
758#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
759#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a
760#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L
761#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
762#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L
763#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L
764#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
765#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L
766#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
767#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L
768#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
769#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L
770//DAGB0_WRCLI2
771#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0
772#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
773#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4
774#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8
775#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
776#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd
777#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
778#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16
779#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
780#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a
781#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L
782#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
783#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L
784#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L
785#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
786#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L
787#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
788#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L
789#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
790#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L
791//DAGB0_WRCLI3
792#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0
793#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
794#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4
795#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8
796#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
797#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd
798#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
799#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16
800#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
801#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a
802#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L
803#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
804#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L
805#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L
806#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
807#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L
808#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
809#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L
810#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
811#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L
812//DAGB0_WRCLI4
813#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0
814#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
815#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4
816#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8
817#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
818#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd
819#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
820#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16
821#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
822#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a
823#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L
824#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
825#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L
826#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L
827#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
828#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L
829#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
830#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L
831#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
832#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L
833//DAGB0_WRCLI5
834#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0
835#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
836#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4
837#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8
838#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
839#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd
840#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
841#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16
842#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
843#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a
844#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L
845#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
846#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L
847#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L
848#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
849#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L
850#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
851#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L
852#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
853#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L
854//DAGB0_WRCLI6
855#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0
856#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
857#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4
858#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8
859#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
860#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd
861#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
862#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16
863#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
864#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a
865#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L
866#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
867#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L
868#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L
869#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
870#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L
871#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
872#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L
873#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
874#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L
875//DAGB0_WRCLI7
876#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0
877#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
878#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4
879#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8
880#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
881#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd
882#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
883#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16
884#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
885#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a
886#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L
887#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
888#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L
889#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L
890#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
891#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L
892#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
893#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L
894#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
895#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L
896//DAGB0_WRCLI8
897#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0
898#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
899#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4
900#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8
901#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
902#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd
903#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
904#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16
905#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
906#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a
907#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L
908#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
909#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L
910#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L
911#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
912#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L
913#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
914#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L
915#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
916#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L
917//DAGB0_WRCLI9
918#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0
919#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
920#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4
921#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8
922#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
923#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd
924#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
925#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16
926#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
927#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a
928#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L
929#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
930#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L
931#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L
932#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
933#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L
934#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
935#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L
936#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
937#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L
938//DAGB0_WRCLI10
939#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0
940#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
941#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4
942#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8
943#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
944#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd
945#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
946#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16
947#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
948#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a
949#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L
950#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
951#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L
952#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L
953#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
954#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L
955#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
956#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L
957#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
958#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L
959//DAGB0_WRCLI11
960#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0
961#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
962#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4
963#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8
964#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
965#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd
966#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
967#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16
968#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
969#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a
970#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L
971#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
972#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L
973#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L
974#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
975#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L
976#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
977#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L
978#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
979#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L
980//DAGB0_WRCLI12
981#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0
982#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
983#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4
984#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8
985#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
986#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd
987#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
988#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16
989#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
990#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a
991#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L
992#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
993#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L
994#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L
995#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
996#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L
997#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
998#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L
999#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
1000#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L
1001//DAGB0_WRCLI13
1002#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0
1003#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
1004#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4
1005#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8
1006#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
1007#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd
1008#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
1009#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16
1010#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
1011#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a
1012#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L
1013#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
1014#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L
1015#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L
1016#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
1017#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L
1018#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
1019#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L
1020#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
1021#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L
1022//DAGB0_WRCLI14
1023#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0
1024#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
1025#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4
1026#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8
1027#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
1028#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd
1029#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
1030#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16
1031#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
1032#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a
1033#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L
1034#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
1035#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L
1036#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L
1037#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
1038#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L
1039#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
1040#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L
1041#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
1042#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L
1043//DAGB0_WRCLI15
1044#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0
1045#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
1046#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4
1047#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8
1048#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
1049#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd
1050#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
1051#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16
1052#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
1053#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a
1054#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L
1055#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
1056#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L
1057#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L
1058#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
1059#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L
1060#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
1061#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L
1062#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
1063#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L
1064//DAGB0_WR_CNTL
1065#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0
1066#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
1067#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
1068#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
1069#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11
1070#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
1071#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
1072#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
1073#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
1074#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
1075#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
1076#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
1077#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
1078#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
1079//DAGB0_WR_GMI_CNTL
1080#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
1081#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6
1082#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
1083#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
1084#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
1085#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
1086#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
1087#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
1088//DAGB0_WR_ADDR_DAGB
1089#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
1090#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
1091#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
1092#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
1093#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
1094#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
1095#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
1096#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
1097//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
1098#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
1099#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
1100#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
1101#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
1102#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
1103#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
1104#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
1105#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
1106#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
1107#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
1108#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
1109#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
1110#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
1111#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
1112#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
1113#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
1114//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
1115#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
1116#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
1117#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
1118#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
1119#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
1120#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
1121#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
1122#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
1123#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
1124#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
1125#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
1126#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
1127#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
1128#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
1129#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
1130#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
1131//DAGB0_WR_CGTT_CLK_CTRL
1132#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1133#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1134#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1135#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1136#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1137#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1138#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1139#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1140#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1141#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1142#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1143#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1144#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1145#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1146#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1147#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1148//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
1149#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1150#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1151#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1152#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1153#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1154#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1155#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1156#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1157#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1158#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1159#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1160#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1161#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1162#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1163#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1164#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1165//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
1166#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
1167#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1168#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
1169#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
1170#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
1171#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
1172#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
1173#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
1174#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
1175#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
1176#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
1177#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
1178#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
1179#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
1180#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
1181#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
1182//DAGB0_WR_ADDR_DAGB_MAX_BURST0
1183#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
1184#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
1185#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
1186#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
1187#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
1188#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
1189#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
1190#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
1191#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
1192#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
1193#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
1194#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
1195#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
1196#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
1197#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
1198#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
1199//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
1200#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
1201#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
1202#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
1203#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
1204#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
1205#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
1206#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
1207#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
1208#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
1209#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
1210#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
1211#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
1212#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
1213#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
1214#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
1215#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
1216//DAGB0_WR_ADDR_DAGB_MAX_BURST1
1217#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
1218#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
1219#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
1220#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
1221#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
1222#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
1223#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
1224#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
1225#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
1226#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
1227#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
1228#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
1229#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
1230#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
1231#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
1232#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
1233//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
1234#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
1235#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
1236#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
1237#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
1238#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
1239#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
1240#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
1241#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
1242#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
1243#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
1244#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
1245#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
1246#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
1247#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
1248#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
1249#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
1250//DAGB0_WR_DATA_DAGB
1251#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
1252#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
1253#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
1254#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
1255#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
1256#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
1257#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
1258#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
1259//DAGB0_WR_DATA_DAGB_MAX_BURST0
1260#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
1261#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
1262#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
1263#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
1264#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
1265#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
1266#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
1267#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
1268#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
1269#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
1270#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
1271#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
1272#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
1273#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
1274#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
1275#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
1276//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
1277#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
1278#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
1279#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
1280#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
1281#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
1282#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
1283#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
1284#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
1285#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
1286#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
1287#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
1288#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
1289#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
1290#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
1291#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
1292#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
1293//DAGB0_WR_DATA_DAGB_MAX_BURST1
1294#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
1295#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
1296#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
1297#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
1298#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
1299#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
1300#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
1301#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
1302#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
1303#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
1304#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
1305#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
1306#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
1307#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
1308#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
1309#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
1310//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
1311#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
1312#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
1313#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
1314#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
1315#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
1316#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
1317#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
1318#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
1319#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
1320#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
1321#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
1322#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
1323#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
1324#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
1325#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
1326#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
1327//DAGB0_WR_VC0_CNTL
1328#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
1329#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
1330#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1331#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
1332#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1333#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
1334#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1335#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
1336#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
1337#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
1338#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1339#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
1340#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1341#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
1342#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1343#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
1344//DAGB0_WR_VC1_CNTL
1345#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
1346#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
1347#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1348#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
1349#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1350#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
1351#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1352#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
1353#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
1354#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
1355#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1356#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
1357#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1358#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
1359#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1360#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
1361//DAGB0_WR_VC2_CNTL
1362#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
1363#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
1364#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1365#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
1366#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1367#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
1368#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1369#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
1370#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
1371#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
1372#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1373#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
1374#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1375#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
1376#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1377#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
1378//DAGB0_WR_VC3_CNTL
1379#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
1380#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
1381#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1382#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
1383#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1384#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
1385#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1386#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
1387#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
1388#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
1389#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1390#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
1391#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1392#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
1393#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1394#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
1395//DAGB0_WR_VC4_CNTL
1396#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
1397#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
1398#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1399#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
1400#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1401#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
1402#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1403#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
1404#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
1405#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
1406#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1407#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
1408#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1409#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
1410#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1411#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
1412//DAGB0_WR_VC5_CNTL
1413#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
1414#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
1415#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1416#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
1417#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1418#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
1419#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1420#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
1421#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
1422#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
1423#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1424#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
1425#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1426#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
1427#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1428#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
1429//DAGB0_WR_VC6_CNTL
1430#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
1431#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
1432#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1433#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
1434#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1435#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
1436#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1437#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
1438#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
1439#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
1440#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1441#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
1442#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1443#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
1444#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1445#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
1446//DAGB0_WR_VC7_CNTL
1447#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
1448#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
1449#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
1450#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
1451#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
1452#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
1453#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
1454#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
1455#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
1456#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
1457#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
1458#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
1459#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
1460#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
1461#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
1462#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
1463//DAGB0_WR_CNTL_MISC
1464#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
1465#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
1466#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
1467#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
1468#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
1469#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
1470#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
1471#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
1472#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
1473#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
1474#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
1475#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
1476//DAGB0_WR_TLB_CREDIT
1477#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0
1478#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5
1479#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
1480#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf
1481#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14
1482#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19
1483#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
1484#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
1485#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
1486#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
1487#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
1488#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
1489//DAGB0_WR_DATA_CREDIT
1490#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
1491#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
1492#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
1493#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
1494#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
1495#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
1496#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
1497#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
1498//DAGB0_WR_MISC_CREDIT
1499#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
1500#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
1501#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
1502#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
1503#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
1504#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
1505#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
1506#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
1507//DAGB0_WRCLI_ASK_PENDING
1508#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
1509#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
1510//DAGB0_WRCLI_GO_PENDING
1511#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
1512#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
1513//DAGB0_WRCLI_GBLSEND_PENDING
1514#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
1515#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
1516//DAGB0_WRCLI_TLB_PENDING
1517#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
1518#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
1519//DAGB0_WRCLI_OARB_PENDING
1520#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
1521#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
1522//DAGB0_WRCLI_OSD_PENDING
1523#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
1524#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
1525//DAGB0_WRCLI_DBUS_ASK_PENDING
1526#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
1527#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
1528//DAGB0_WRCLI_DBUS_GO_PENDING
1529#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
1530#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
1531//DAGB0_DAGB_DLY
1532#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0
1533#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8
1534#define DAGB0_DAGB_DLY__POS__SHIFT 0x10
1535#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL
1536#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L
1537#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L
1538//DAGB0_CNTL_MISC
1539#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
1540#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
1541#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
1542#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
1543#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
1544#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
1545#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
1546#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
1547#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
1548#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
1549#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
1550#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
1551#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
1552#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
1553#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
1554#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
1555#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
1556#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
1557#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
1558#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
1559//DAGB0_CNTL_MISC2
1560#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
1561#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
1562#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
1563#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
1564#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
1565#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
1566#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
1567#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
1568#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
1569#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
1570#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
1571#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
1572#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
1573#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
1574#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
1575#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
1576#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
1577#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
1578#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
1579#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
1580#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
1581#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
1582//DAGB0_FIFO_EMPTY
1583#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0
1584#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
1585//DAGB0_FIFO_FULL
1586#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0
1587#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL
1588//DAGB0_WR_CREDITS_FULL
1589#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0
1590#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
1591//DAGB0_RD_CREDITS_FULL
1592#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0
1593#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
1594//DAGB0_PERFCOUNTER_LO
1595#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
1596#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
1597//DAGB0_PERFCOUNTER_HI
1598#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
1599#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
1600#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
1601#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
1602//DAGB0_PERFCOUNTER0_CFG
1603#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
1604#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
1605#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
1606#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
1607#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
1608#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
1609#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
1610#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
1611#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
1612#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
1613//DAGB0_PERFCOUNTER1_CFG
1614#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
1615#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
1616#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
1617#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
1618#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
1619#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
1620#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
1621#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
1622#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
1623#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
1624//DAGB0_PERFCOUNTER2_CFG
1625#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
1626#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
1627#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
1628#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
1629#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
1630#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
1631#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
1632#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
1633#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
1634#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
1635//DAGB0_PERFCOUNTER_RSLT_CNTL
1636#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
1637#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
1638#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
1639#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
1640#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
1641#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
1642#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
1643#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
1644#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
1645#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
1646#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
1647#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
1648//DAGB0_RESERVE0
1649#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0
1650#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
1651//DAGB0_RESERVE1
1652#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0
1653#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
1654//DAGB0_RESERVE2
1655#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0
1656#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
1657//DAGB0_RESERVE3
1658#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0
1659#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
1660//DAGB0_RESERVE4
1661#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0
1662#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
1663//DAGB0_RESERVE5
1664#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0
1665#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
1666//DAGB0_RESERVE6
1667#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0
1668#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
1669//DAGB0_RESERVE7
1670#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0
1671#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
1672//DAGB0_RESERVE8
1673#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0
1674#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
1675//DAGB0_RESERVE9
1676#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0
1677#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
1678//DAGB0_RESERVE10
1679#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0
1680#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
1681//DAGB0_RESERVE11
1682#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0
1683#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
1684//DAGB0_RESERVE12
1685#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0
1686#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
1687//DAGB0_RESERVE13
1688#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0
1689#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
1690//DAGB0_RESERVE14
1691#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0
1692#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
1693//DAGB0_RESERVE15
1694#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0
1695#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
1696//DAGB0_RESERVE16
1697#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0
1698#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
1699//DAGB0_RESERVE17
1700#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0
1701#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
1702//DAGB1_RDCLI0
1703#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0
1704#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
1705#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4
1706#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8
1707#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
1708#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd
1709#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15
1710#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16
1711#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
1712#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a
1713#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L
1714#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
1715#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L
1716#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L
1717#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L
1718#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L
1719#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L
1720#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L
1721#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
1722#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L
1723//DAGB1_RDCLI1
1724#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0
1725#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
1726#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4
1727#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8
1728#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc
1729#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd
1730#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15
1731#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16
1732#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
1733#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a
1734#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L
1735#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
1736#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L
1737#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L
1738#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L
1739#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L
1740#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L
1741#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L
1742#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
1743#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L
1744//DAGB1_RDCLI2
1745#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0
1746#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
1747#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4
1748#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8
1749#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc
1750#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd
1751#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15
1752#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16
1753#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
1754#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a
1755#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L
1756#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
1757#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L
1758#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L
1759#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L
1760#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L
1761#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L
1762#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L
1763#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
1764#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L
1765//DAGB1_RDCLI3
1766#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0
1767#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
1768#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4
1769#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8
1770#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc
1771#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd
1772#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15
1773#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16
1774#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
1775#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a
1776#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L
1777#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
1778#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L
1779#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L
1780#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L
1781#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L
1782#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L
1783#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L
1784#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
1785#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L
1786//DAGB1_RDCLI4
1787#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0
1788#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
1789#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4
1790#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8
1791#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc
1792#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd
1793#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15
1794#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16
1795#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
1796#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a
1797#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L
1798#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
1799#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L
1800#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L
1801#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L
1802#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L
1803#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L
1804#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L
1805#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
1806#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L
1807//DAGB1_RDCLI5
1808#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0
1809#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
1810#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4
1811#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8
1812#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc
1813#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd
1814#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15
1815#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16
1816#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
1817#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a
1818#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L
1819#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
1820#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L
1821#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L
1822#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L
1823#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L
1824#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L
1825#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L
1826#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
1827#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L
1828//DAGB1_RDCLI6
1829#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0
1830#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
1831#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4
1832#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8
1833#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc
1834#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd
1835#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15
1836#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16
1837#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
1838#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a
1839#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L
1840#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
1841#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L
1842#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L
1843#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L
1844#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L
1845#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L
1846#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L
1847#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
1848#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L
1849//DAGB1_RDCLI7
1850#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0
1851#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
1852#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4
1853#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8
1854#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc
1855#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd
1856#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15
1857#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16
1858#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
1859#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a
1860#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L
1861#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
1862#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L
1863#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L
1864#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L
1865#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L
1866#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L
1867#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L
1868#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
1869#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L
1870//DAGB1_RDCLI8
1871#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0
1872#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
1873#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4
1874#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8
1875#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc
1876#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd
1877#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15
1878#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16
1879#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
1880#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a
1881#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L
1882#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
1883#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L
1884#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L
1885#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L
1886#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L
1887#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L
1888#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L
1889#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
1890#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L
1891//DAGB1_RDCLI9
1892#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0
1893#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
1894#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4
1895#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8
1896#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc
1897#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd
1898#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15
1899#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16
1900#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
1901#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a
1902#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L
1903#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
1904#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L
1905#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L
1906#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L
1907#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L
1908#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L
1909#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L
1910#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
1911#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L
1912//DAGB1_RDCLI10
1913#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0
1914#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
1915#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4
1916#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8
1917#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc
1918#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd
1919#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15
1920#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16
1921#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
1922#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a
1923#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L
1924#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
1925#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L
1926#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L
1927#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L
1928#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L
1929#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L
1930#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L
1931#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
1932#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L
1933//DAGB1_RDCLI11
1934#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0
1935#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
1936#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4
1937#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8
1938#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc
1939#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd
1940#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15
1941#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16
1942#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
1943#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a
1944#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L
1945#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
1946#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L
1947#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L
1948#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L
1949#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L
1950#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L
1951#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L
1952#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
1953#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L
1954//DAGB1_RDCLI12
1955#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0
1956#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
1957#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4
1958#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8
1959#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc
1960#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd
1961#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15
1962#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16
1963#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
1964#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a
1965#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L
1966#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
1967#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L
1968#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L
1969#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L
1970#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L
1971#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L
1972#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L
1973#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
1974#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L
1975//DAGB1_RDCLI13
1976#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0
1977#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
1978#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4
1979#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8
1980#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc
1981#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd
1982#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15
1983#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16
1984#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
1985#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a
1986#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L
1987#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
1988#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L
1989#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L
1990#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L
1991#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L
1992#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L
1993#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L
1994#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
1995#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L
1996//DAGB1_RDCLI14
1997#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0
1998#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
1999#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4
2000#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8
2001#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc
2002#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd
2003#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15
2004#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16
2005#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
2006#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a
2007#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L
2008#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
2009#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L
2010#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L
2011#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L
2012#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L
2013#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L
2014#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L
2015#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
2016#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L
2017//DAGB1_RDCLI15
2018#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0
2019#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
2020#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4
2021#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8
2022#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc
2023#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd
2024#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15
2025#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16
2026#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
2027#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a
2028#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L
2029#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
2030#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L
2031#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L
2032#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L
2033#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L
2034#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L
2035#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L
2036#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
2037#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L
2038//DAGB1_RD_CNTL
2039#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0
2040#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
2041#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
2042#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
2043#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11
2044#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
2045#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17
2046#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL
2047#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
2048#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
2049#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
2050#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L
2051#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
2052#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L
2053//DAGB1_RD_GMI_CNTL
2054#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0
2055#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6
2056#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9
2057#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
2058#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
2059#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L
2060#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
2061#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
2062//DAGB1_RD_ADDR_DAGB
2063#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
2064#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
2065#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
2066#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7
2067#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
2068#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
2069#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
2070#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
2071//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
2072#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
2073#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
2074#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
2075#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
2076#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
2077#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
2078#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
2079#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
2080#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
2081#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
2082#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
2083#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
2084#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
2085#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
2086#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
2087#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
2088//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
2089#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
2090#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
2091#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
2092#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
2093#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
2094#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
2095#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
2096#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
2097#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
2098#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
2099#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
2100#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
2101#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
2102#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
2103#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
2104#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
2105//DAGB1_RD_CGTT_CLK_CTRL
2106#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2107#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2108#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2109#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2110#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2111#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2112#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2113#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2114#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2115#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2116#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2117#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2118#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2119#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2120#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2121#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2122//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
2123#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2124#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2125#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2126#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2127#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2128#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2129#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2130#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2131#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2132#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2133#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2134#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2135#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2136#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2137#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2138#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2139//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
2140#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2141#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2142#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2143#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2144#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2145#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2146#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2147#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2148#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2149#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2150#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2151#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2152#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2153#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2154#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2155#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2156//DAGB1_RD_ADDR_DAGB_MAX_BURST0
2157#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
2158#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
2159#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
2160#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
2161#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
2162#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
2163#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
2164#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
2165#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
2166#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
2167#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
2168#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
2169#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
2170#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
2171#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
2172#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
2173//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
2174#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
2175#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
2176#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
2177#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
2178#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
2179#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
2180#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
2181#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
2182#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
2183#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
2184#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
2185#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
2186#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
2187#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
2188#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
2189#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
2190//DAGB1_RD_ADDR_DAGB_MAX_BURST1
2191#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
2192#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
2193#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
2194#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
2195#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
2196#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
2197#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
2198#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
2199#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
2200#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
2201#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
2202#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
2203#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
2204#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
2205#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
2206#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
2207//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
2208#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
2209#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
2210#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
2211#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
2212#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
2213#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
2214#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
2215#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
2216#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
2217#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
2218#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
2219#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
2220#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
2221#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
2222#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
2223#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
2224//DAGB1_RD_VC0_CNTL
2225#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
2226#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5
2227#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2228#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc
2229#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2230#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15
2231#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2232#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19
2233#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
2234#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
2235#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2236#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L
2237#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2238#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L
2239#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2240#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
2241//DAGB1_RD_VC1_CNTL
2242#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
2243#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5
2244#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2245#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc
2246#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2247#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15
2248#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2249#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19
2250#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
2251#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
2252#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2253#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L
2254#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2255#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L
2256#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2257#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
2258//DAGB1_RD_VC2_CNTL
2259#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
2260#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5
2261#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2262#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc
2263#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2264#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15
2265#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2266#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19
2267#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
2268#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
2269#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2270#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L
2271#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2272#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L
2273#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2274#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
2275//DAGB1_RD_VC3_CNTL
2276#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
2277#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5
2278#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2279#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc
2280#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2281#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15
2282#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2283#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19
2284#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
2285#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
2286#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2287#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L
2288#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2289#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L
2290#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2291#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
2292//DAGB1_RD_VC4_CNTL
2293#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
2294#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5
2295#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2296#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc
2297#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2298#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15
2299#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2300#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19
2301#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
2302#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
2303#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2304#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L
2305#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2306#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L
2307#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2308#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
2309//DAGB1_RD_VC5_CNTL
2310#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
2311#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5
2312#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2313#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc
2314#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2315#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15
2316#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2317#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19
2318#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
2319#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
2320#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2321#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L
2322#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2323#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L
2324#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2325#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
2326//DAGB1_RD_VC6_CNTL
2327#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
2328#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5
2329#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2330#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc
2331#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2332#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15
2333#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2334#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19
2335#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
2336#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
2337#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2338#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L
2339#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2340#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L
2341#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2342#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
2343//DAGB1_RD_VC7_CNTL
2344#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
2345#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5
2346#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
2347#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc
2348#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
2349#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15
2350#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
2351#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19
2352#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
2353#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
2354#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
2355#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L
2356#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
2357#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L
2358#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
2359#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
2360//DAGB1_RD_CNTL_MISC
2361#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
2362#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
2363#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
2364#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
2365#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
2366#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15
2367#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
2368#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
2369#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
2370#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
2371#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
2372#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
2373//DAGB1_RD_TLB_CREDIT
2374#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0
2375#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5
2376#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
2377#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf
2378#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14
2379#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19
2380#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL
2381#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L
2382#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L
2383#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L
2384#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L
2385#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L
2386//DAGB1_RDCLI_ASK_PENDING
2387#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0
2388#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
2389//DAGB1_RDCLI_GO_PENDING
2390#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0
2391#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
2392//DAGB1_RDCLI_GBLSEND_PENDING
2393#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
2394#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
2395//DAGB1_RDCLI_TLB_PENDING
2396#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0
2397#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
2398//DAGB1_RDCLI_OARB_PENDING
2399#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0
2400#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
2401//DAGB1_RDCLI_OSD_PENDING
2402#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0
2403#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
2404//DAGB1_WRCLI0
2405#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0
2406#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
2407#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4
2408#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8
2409#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc
2410#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd
2411#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15
2412#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16
2413#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
2414#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a
2415#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L
2416#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L
2417#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L
2418#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L
2419#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L
2420#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L
2421#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L
2422#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L
2423#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L
2424#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L
2425//DAGB1_WRCLI1
2426#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0
2427#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3
2428#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4
2429#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8
2430#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc
2431#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd
2432#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15
2433#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16
2434#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19
2435#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a
2436#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L
2437#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L
2438#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L
2439#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L
2440#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L
2441#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L
2442#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L
2443#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L
2444#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L
2445#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L
2446//DAGB1_WRCLI2
2447#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0
2448#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3
2449#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4
2450#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8
2451#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc
2452#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd
2453#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15
2454#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16
2455#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19
2456#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a
2457#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L
2458#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L
2459#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L
2460#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L
2461#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L
2462#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L
2463#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L
2464#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L
2465#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L
2466#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L
2467//DAGB1_WRCLI3
2468#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0
2469#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3
2470#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4
2471#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8
2472#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc
2473#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd
2474#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15
2475#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16
2476#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19
2477#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a
2478#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L
2479#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L
2480#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L
2481#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L
2482#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L
2483#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L
2484#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L
2485#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L
2486#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L
2487#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L
2488//DAGB1_WRCLI4
2489#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0
2490#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3
2491#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4
2492#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8
2493#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc
2494#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd
2495#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15
2496#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16
2497#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19
2498#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a
2499#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L
2500#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L
2501#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L
2502#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L
2503#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L
2504#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L
2505#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L
2506#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L
2507#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L
2508#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L
2509//DAGB1_WRCLI5
2510#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0
2511#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3
2512#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4
2513#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8
2514#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc
2515#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd
2516#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15
2517#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16
2518#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19
2519#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a
2520#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L
2521#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L
2522#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L
2523#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L
2524#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L
2525#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L
2526#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L
2527#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L
2528#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L
2529#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L
2530//DAGB1_WRCLI6
2531#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0
2532#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3
2533#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4
2534#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8
2535#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc
2536#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd
2537#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15
2538#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16
2539#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19
2540#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a
2541#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L
2542#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L
2543#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L
2544#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L
2545#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L
2546#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L
2547#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L
2548#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L
2549#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L
2550#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L
2551//DAGB1_WRCLI7
2552#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0
2553#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3
2554#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4
2555#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8
2556#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc
2557#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd
2558#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15
2559#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16
2560#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19
2561#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a
2562#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L
2563#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L
2564#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L
2565#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L
2566#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L
2567#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L
2568#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L
2569#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L
2570#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L
2571#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L
2572//DAGB1_WRCLI8
2573#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0
2574#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3
2575#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4
2576#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8
2577#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc
2578#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd
2579#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15
2580#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16
2581#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19
2582#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a
2583#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L
2584#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L
2585#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L
2586#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L
2587#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L
2588#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L
2589#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L
2590#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L
2591#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L
2592#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L
2593//DAGB1_WRCLI9
2594#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0
2595#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3
2596#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4
2597#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8
2598#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc
2599#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd
2600#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15
2601#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16
2602#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19
2603#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a
2604#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L
2605#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L
2606#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L
2607#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L
2608#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L
2609#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L
2610#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L
2611#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L
2612#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L
2613#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L
2614//DAGB1_WRCLI10
2615#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0
2616#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3
2617#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4
2618#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8
2619#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc
2620#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd
2621#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15
2622#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16
2623#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19
2624#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a
2625#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L
2626#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L
2627#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L
2628#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L
2629#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L
2630#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L
2631#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L
2632#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L
2633#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L
2634#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L
2635//DAGB1_WRCLI11
2636#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0
2637#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3
2638#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4
2639#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8
2640#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc
2641#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd
2642#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15
2643#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16
2644#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19
2645#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a
2646#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L
2647#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L
2648#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L
2649#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L
2650#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L
2651#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L
2652#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L
2653#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L
2654#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L
2655#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L
2656//DAGB1_WRCLI12
2657#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0
2658#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3
2659#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4
2660#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8
2661#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc
2662#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd
2663#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15
2664#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16
2665#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19
2666#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a
2667#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L
2668#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L
2669#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L
2670#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L
2671#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L
2672#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L
2673#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L
2674#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L
2675#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L
2676#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L
2677//DAGB1_WRCLI13
2678#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0
2679#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3
2680#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4
2681#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8
2682#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc
2683#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd
2684#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15
2685#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16
2686#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19
2687#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a
2688#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L
2689#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L
2690#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L
2691#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L
2692#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L
2693#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L
2694#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L
2695#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L
2696#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L
2697#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L
2698//DAGB1_WRCLI14
2699#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0
2700#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3
2701#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4
2702#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8
2703#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc
2704#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd
2705#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15
2706#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16
2707#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19
2708#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a
2709#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L
2710#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L
2711#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L
2712#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L
2713#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L
2714#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L
2715#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L
2716#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L
2717#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L
2718#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L
2719//DAGB1_WRCLI15
2720#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0
2721#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3
2722#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4
2723#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8
2724#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc
2725#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd
2726#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15
2727#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16
2728#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19
2729#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a
2730#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L
2731#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L
2732#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L
2733#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L
2734#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L
2735#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L
2736#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L
2737#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L
2738#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L
2739#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L
2740//DAGB1_WR_CNTL
2741#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0
2742#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4
2743#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
2744#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10
2745#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11
2746#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14
2747#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17
2748#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL
2749#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L
2750#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L
2751#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L
2752#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L
2753#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L
2754#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L
2755//DAGB1_WR_GMI_CNTL
2756#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0
2757#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6
2758#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9
2759#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd
2760#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL
2761#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L
2762#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L
2763#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L
2764//DAGB1_WR_ADDR_DAGB
2765#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0
2766#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
2767#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
2768#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7
2769#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L
2770#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
2771#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
2772#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L
2773//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
2774#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0
2775#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4
2776#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8
2777#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc
2778#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10
2779#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14
2780#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18
2781#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c
2782#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL
2783#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L
2784#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L
2785#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L
2786#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L
2787#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L
2788#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L
2789#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L
2790//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
2791#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0
2792#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4
2793#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8
2794#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc
2795#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10
2796#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14
2797#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18
2798#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c
2799#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL
2800#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L
2801#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L
2802#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L
2803#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L
2804#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L
2805#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L
2806#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L
2807//DAGB1_WR_CGTT_CLK_CTRL
2808#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2809#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2810#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2811#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2812#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2813#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2814#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2815#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2816#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2817#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2818#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2819#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2820#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2821#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2822#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2823#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2824//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
2825#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2826#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2827#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2828#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2829#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2830#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2831#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2832#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2833#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2834#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2835#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2836#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2837#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2838#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2839#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2840#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2841//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
2842#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
2843#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
2844#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16
2845#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b
2846#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c
2847#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d
2848#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e
2849#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f
2850#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
2851#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
2852#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L
2853#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L
2854#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L
2855#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L
2856#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L
2857#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L
2858//DAGB1_WR_ADDR_DAGB_MAX_BURST0
2859#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
2860#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
2861#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
2862#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
2863#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
2864#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
2865#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
2866#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
2867#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
2868#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
2869#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
2870#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
2871#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
2872#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
2873#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
2874#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
2875//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
2876#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
2877#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
2878#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
2879#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
2880#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
2881#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
2882#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
2883#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
2884#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
2885#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
2886#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
2887#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
2888#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
2889#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
2890#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
2891#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
2892//DAGB1_WR_ADDR_DAGB_MAX_BURST1
2893#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
2894#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
2895#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
2896#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
2897#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
2898#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
2899#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
2900#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
2901#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
2902#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
2903#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
2904#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
2905#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
2906#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
2907#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
2908#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
2909//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
2910#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
2911#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
2912#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
2913#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
2914#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
2915#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
2916#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
2917#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
2918#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
2919#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
2920#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
2921#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
2922#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
2923#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
2924#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
2925#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
2926//DAGB1_WR_DATA_DAGB
2927#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0
2928#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3
2929#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6
2930#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7
2931#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L
2932#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L
2933#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L
2934#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L
2935//DAGB1_WR_DATA_DAGB_MAX_BURST0
2936#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0
2937#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4
2938#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8
2939#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc
2940#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10
2941#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14
2942#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18
2943#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c
2944#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL
2945#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L
2946#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L
2947#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L
2948#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L
2949#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L
2950#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L
2951#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L
2952//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
2953#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0
2954#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4
2955#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8
2956#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc
2957#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10
2958#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14
2959#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18
2960#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c
2961#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL
2962#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L
2963#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L
2964#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L
2965#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L
2966#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L
2967#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L
2968#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L
2969//DAGB1_WR_DATA_DAGB_MAX_BURST1
2970#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0
2971#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4
2972#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8
2973#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc
2974#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10
2975#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14
2976#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18
2977#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c
2978#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL
2979#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L
2980#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L
2981#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L
2982#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L
2983#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L
2984#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L
2985#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L
2986//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
2987#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0
2988#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4
2989#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8
2990#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc
2991#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10
2992#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14
2993#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18
2994#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c
2995#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL
2996#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L
2997#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L
2998#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L
2999#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L
3000#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L
3001#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L
3002#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L
3003//DAGB1_WR_VC0_CNTL
3004#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0
3005#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5
3006#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3007#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc
3008#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3009#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15
3010#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3011#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19
3012#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL
3013#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L
3014#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3015#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L
3016#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3017#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L
3018#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3019#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L
3020//DAGB1_WR_VC1_CNTL
3021#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0
3022#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5
3023#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3024#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc
3025#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3026#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15
3027#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3028#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19
3029#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL
3030#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L
3031#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3032#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L
3033#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3034#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L
3035#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3036#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L
3037//DAGB1_WR_VC2_CNTL
3038#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0
3039#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5
3040#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3041#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc
3042#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3043#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15
3044#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3045#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19
3046#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL
3047#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L
3048#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3049#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L
3050#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3051#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L
3052#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3053#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L
3054//DAGB1_WR_VC3_CNTL
3055#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0
3056#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5
3057#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3058#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc
3059#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3060#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15
3061#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3062#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19
3063#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL
3064#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L
3065#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3066#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L
3067#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3068#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L
3069#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3070#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L
3071//DAGB1_WR_VC4_CNTL
3072#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0
3073#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5
3074#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3075#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc
3076#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3077#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15
3078#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3079#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19
3080#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL
3081#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L
3082#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3083#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L
3084#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3085#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L
3086#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3087#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L
3088//DAGB1_WR_VC5_CNTL
3089#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0
3090#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5
3091#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3092#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc
3093#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3094#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15
3095#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3096#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19
3097#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL
3098#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L
3099#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3100#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L
3101#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3102#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L
3103#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3104#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L
3105//DAGB1_WR_VC6_CNTL
3106#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0
3107#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5
3108#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3109#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc
3110#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3111#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15
3112#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3113#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19
3114#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL
3115#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L
3116#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3117#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L
3118#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3119#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L
3120#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3121#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L
3122//DAGB1_WR_VC7_CNTL
3123#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0
3124#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5
3125#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb
3126#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc
3127#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14
3128#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15
3129#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18
3130#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19
3131#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL
3132#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L
3133#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L
3134#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L
3135#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L
3136#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L
3137#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L
3138#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L
3139//DAGB1_WR_CNTL_MISC
3140#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0
3141#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6
3142#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd
3143#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13
3144#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14
3145#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15
3146#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL
3147#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L
3148#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L
3149#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L
3150#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L
3151#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L
3152//DAGB1_WR_TLB_CREDIT
3153#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0
3154#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5
3155#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
3156#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf
3157#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14
3158#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19
3159#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL
3160#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L
3161#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L
3162#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L
3163#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L
3164#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L
3165//DAGB1_WR_DATA_CREDIT
3166#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0
3167#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8
3168#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10
3169#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18
3170#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL
3171#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L
3172#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L
3173#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L
3174//DAGB1_WR_MISC_CREDIT
3175#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0
3176#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6
3177#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9
3178#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10
3179#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL
3180#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L
3181#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L
3182#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L
3183//DAGB1_WRCLI_ASK_PENDING
3184#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0
3185#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
3186//DAGB1_WRCLI_GO_PENDING
3187#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0
3188#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
3189//DAGB1_WRCLI_GBLSEND_PENDING
3190#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0
3191#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL
3192//DAGB1_WRCLI_TLB_PENDING
3193#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0
3194#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL
3195//DAGB1_WRCLI_OARB_PENDING
3196#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0
3197#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL
3198//DAGB1_WRCLI_OSD_PENDING
3199#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0
3200#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL
3201//DAGB1_WRCLI_DBUS_ASK_PENDING
3202#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0
3203#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL
3204//DAGB1_WRCLI_DBUS_GO_PENDING
3205#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0
3206#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL
3207//DAGB1_DAGB_DLY
3208#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0
3209#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8
3210#define DAGB1_DAGB_DLY__POS__SHIFT 0x10
3211#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL
3212#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L
3213#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L
3214//DAGB1_CNTL_MISC
3215#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0
3216#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3
3217#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6
3218#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9
3219#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc
3220#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf
3221#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12
3222#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15
3223#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18
3224#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e
3225#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L
3226#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L
3227#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L
3228#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L
3229#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L
3230#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L
3231#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L
3232#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L
3233#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L
3234#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L
3235//DAGB1_CNTL_MISC2
3236#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0
3237#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1
3238#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2
3239#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3
3240#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4
3241#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5
3242#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6
3243#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7
3244#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8
3245#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9
3246#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
3247#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L
3248#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L
3249#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L
3250#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L
3251#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L
3252#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L
3253#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L
3254#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L
3255#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L
3256#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L
3257#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L
3258//DAGB1_FIFO_EMPTY
3259#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0
3260#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL
3261//DAGB1_FIFO_FULL
3262#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0
3263#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL
3264//DAGB1_WR_CREDITS_FULL
3265#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0
3266#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL
3267//DAGB1_RD_CREDITS_FULL
3268#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0
3269#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL
3270//DAGB1_PERFCOUNTER_LO
3271#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
3272#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL
3273//DAGB1_PERFCOUNTER_HI
3274#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
3275#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
3276#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL
3277#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L
3278//DAGB1_PERFCOUNTER0_CFG
3279#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
3280#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
3281#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
3282#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
3283#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
3284#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL
3285#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L
3286#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L
3287#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L
3288#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L
3289//DAGB1_PERFCOUNTER1_CFG
3290#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
3291#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
3292#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
3293#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
3294#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
3295#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL
3296#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L
3297#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L
3298#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L
3299#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L
3300//DAGB1_PERFCOUNTER2_CFG
3301#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
3302#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
3303#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
3304#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
3305#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
3306#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL
3307#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L
3308#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L
3309#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L
3310#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L
3311//DAGB1_PERFCOUNTER_RSLT_CNTL
3312#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
3313#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
3314#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
3315#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
3316#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
3317#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
3318#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL
3319#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L
3320#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L
3321#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L
3322#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L
3323#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L
3324//DAGB1_RESERVE0
3325#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0
3326#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL
3327//DAGB1_RESERVE1
3328#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0
3329#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL
3330//DAGB1_RESERVE2
3331#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0
3332#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL
3333//DAGB1_RESERVE3
3334#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0
3335#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL
3336//DAGB1_RESERVE4
3337#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0
3338#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL
3339//DAGB1_RESERVE5
3340#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0
3341#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL
3342//DAGB1_RESERVE6
3343#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0
3344#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL
3345//DAGB1_RESERVE7
3346#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0
3347#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL
3348//DAGB1_RESERVE8
3349#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0
3350#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL
3351//DAGB1_RESERVE9
3352#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0
3353#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL
3354//DAGB1_RESERVE10
3355#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0
3356#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL
3357//DAGB1_RESERVE11
3358#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0
3359#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL
3360//DAGB1_RESERVE12
3361#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0
3362#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL
3363//DAGB1_RESERVE13
3364#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0
3365#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL
3366//DAGB1_RESERVE14
3367#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0
3368#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL
3369//DAGB1_RESERVE15
3370#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0
3371#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL
3372//DAGB1_RESERVE16
3373#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0
3374#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL
3375//DAGB1_RESERVE17
3376#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0
3377#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL
3378
3379
3380// addressBlock: mmhub_ea_mmeadec
3381//MMEA0_DRAM_RD_CLI2GRP_MAP0
3382#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
3383#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
3384#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
3385#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
3386#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
3387#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
3388#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
3389#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
3390#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
3391#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
3392#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
3393#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
3394#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
3395#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
3396#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
3397#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
3398#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
3399#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
3400#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
3401#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
3402#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
3403#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
3404#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
3405#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
3406#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
3407#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
3408#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
3409#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
3410#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
3411#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
3412#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
3413#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
3414//MMEA0_DRAM_RD_CLI2GRP_MAP1
3415#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
3416#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
3417#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
3418#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
3419#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
3420#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
3421#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
3422#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
3423#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
3424#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
3425#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
3426#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
3427#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
3428#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
3429#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
3430#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
3431#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
3432#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
3433#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
3434#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
3435#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
3436#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
3437#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
3438#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
3439#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
3440#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
3441#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
3442#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
3443#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
3444#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
3445#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
3446#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
3447//MMEA0_DRAM_WR_CLI2GRP_MAP0
3448#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0
3449#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2
3450#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4
3451#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6
3452#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8
3453#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa
3454#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc
3455#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe
3456#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10
3457#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12
3458#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14
3459#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16
3460#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18
3461#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a
3462#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c
3463#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e
3464#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L
3465#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL
3466#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L
3467#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L
3468#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L
3469#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L
3470#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L
3471#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L
3472#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L
3473#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L
3474#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L
3475#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L
3476#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L
3477#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L
3478#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L
3479#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L
3480//MMEA0_DRAM_WR_CLI2GRP_MAP1
3481#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0
3482#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2
3483#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4
3484#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6
3485#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8
3486#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa
3487#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc
3488#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe
3489#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10
3490#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12
3491#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14
3492#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16
3493#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18
3494#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a
3495#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c
3496#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e
3497#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L
3498#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL
3499#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L
3500#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L
3501#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L
3502#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L
3503#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L
3504#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L
3505#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L
3506#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L
3507#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L
3508#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L
3509#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L
3510#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L
3511#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L
3512#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L
3513//MMEA0_DRAM_RD_GRP2VC_MAP
3514#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
3515#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
3516#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
3517#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
3518#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
3519#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
3520#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
3521#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
3522//MMEA0_DRAM_WR_GRP2VC_MAP
3523#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0
3524#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3
3525#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6
3526#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9
3527#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L
3528#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L
3529#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L
3530#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L
3531//MMEA0_DRAM_RD_LAZY
3532#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0
3533#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3
3534#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6
3535#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9
3536#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L
3537#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L
3538#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L
3539#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L
3540//MMEA0_DRAM_WR_LAZY
3541#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0
3542#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3
3543#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6
3544#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9
3545#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L
3546#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L
3547#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L
3548#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L
3549//MMEA0_DRAM_RD_CAM_CNTL
3550#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
3551#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
3552#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
3553#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
3554#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
3555#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
3556#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
3557#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
3558#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
3559#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
3560#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
3561#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
3562#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
3563#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
3564#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
3565#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
3566//MMEA0_DRAM_WR_CAM_CNTL
3567#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0
3568#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4
3569#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8
3570#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc
3571#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10
3572#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13
3573#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16
3574#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19
3575#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL
3576#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L
3577#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L
3578#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L
3579#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L
3580#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L
3581#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L
3582#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L
3583//MMEA0_DRAM_PAGE_BURST
3584#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0
3585#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8
3586#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10
3587#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18
3588#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL
3589#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L
3590#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L
3591#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L
3592//MMEA0_DRAM_RD_PRI_AGE
3593#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
3594#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
3595#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
3596#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
3597#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
3598#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
3599#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
3600#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
3601#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
3602#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
3603#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
3604#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
3605#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
3606#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
3607#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
3608#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
3609//MMEA0_DRAM_WR_PRI_AGE
3610#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0
3611#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3
3612#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6
3613#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9
3614#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc
3615#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf
3616#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12
3617#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15
3618#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L
3619#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L
3620#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L
3621#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L
3622#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L
3623#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L
3624#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L
3625#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L
3626//MMEA0_DRAM_RD_PRI_QUEUING
3627#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
3628#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
3629#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
3630#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
3631#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
3632#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
3633#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
3634#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
3635//MMEA0_DRAM_WR_PRI_QUEUING
3636#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0
3637#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3
3638#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6
3639#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9
3640#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L
3641#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L
3642#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L
3643#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L
3644//MMEA0_DRAM_RD_PRI_FIXED
3645#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
3646#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
3647#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
3648#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
3649#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
3650#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
3651#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
3652#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
3653//MMEA0_DRAM_WR_PRI_FIXED
3654#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0
3655#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3
3656#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6
3657#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9
3658#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L
3659#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L
3660#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L
3661#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L
3662//MMEA0_DRAM_RD_PRI_URGENCY
3663#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
3664#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
3665#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
3666#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
3667#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
3668#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
3669#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
3670#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
3671#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
3672#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
3673#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
3674#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
3675#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
3676#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
3677#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
3678#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
3679//MMEA0_DRAM_WR_PRI_URGENCY
3680#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0
3681#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3
3682#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6
3683#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9
3684#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc
3685#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd
3686#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe
3687#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf
3688#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L
3689#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L
3690#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L
3691#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L
3692#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L
3693#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L
3694#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L
3695#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L
3696//MMEA0_DRAM_RD_PRI_QUANT_PRI1
3697#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
3698#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
3699#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
3700#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
3701#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
3702#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
3703#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
3704#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
3705//MMEA0_DRAM_RD_PRI_QUANT_PRI2
3706#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
3707#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
3708#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
3709#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
3710#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
3711#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
3712#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
3713#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
3714//MMEA0_DRAM_RD_PRI_QUANT_PRI3
3715#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
3716#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
3717#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
3718#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
3719#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
3720#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
3721#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
3722#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
3723//MMEA0_DRAM_WR_PRI_QUANT_PRI1
3724#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0
3725#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8
3726#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10
3727#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18
3728#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL
3729#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L
3730#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L
3731#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L
3732//MMEA0_DRAM_WR_PRI_QUANT_PRI2
3733#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0
3734#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8
3735#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10
3736#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18
3737#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL
3738#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L
3739#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L
3740#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L
3741//MMEA0_DRAM_WR_PRI_QUANT_PRI3
3742#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0
3743#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8
3744#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10
3745#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18
3746#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL
3747#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L
3748#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L
3749#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L
3750//MMEA0_ADDRNORM_BASE_ADDR0
3751#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0
3752#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1
3753#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4
3754#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8
3755#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc
3756#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L
3757#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
3758#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L
3759#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L
3760#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L
3761//MMEA0_ADDRNORM_LIMIT_ADDR0
3762#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0
3763#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8
3764#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa
3765#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc
3766#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL
3767#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L
3768#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L
3769#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L
3770//MMEA0_ADDRNORM_BASE_ADDR1
3771#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0
3772#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1
3773#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4
3774#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8
3775#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc
3776#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L
3777#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L
3778#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L
3779#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L
3780#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L
3781//MMEA0_ADDRNORM_LIMIT_ADDR1
3782#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0
3783#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8
3784#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa
3785#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc
3786#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL
3787#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L
3788#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L
3789#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L
3790//MMEA0_ADDRNORM_OFFSET_ADDR1
3791#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0
3792#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14
3793#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L
3794#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L
3795//MMEA0_ADDRNORM_HOLE_CNTL
3796#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0
3797#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7
3798#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L
3799#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L
3800//MMEA0_ADDRDEC_BANK_CFG
3801#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0
3802#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5
3803#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa
3804#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd
3805#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10
3806#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11
3807#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL
3808#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L
3809#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L
3810#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L
3811#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L
3812#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L
3813//MMEA0_ADDRDEC_MISC_CFG
3814#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0
3815#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1
3816#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2
3817#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3
3818#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4
3819#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8
3820#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9
3821#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc
3822#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10
3823#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14
3824#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16
3825#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18
3826#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b
3827#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L
3828#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L
3829#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L
3830#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L
3831#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L
3832#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L
3833#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L
3834#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L
3835#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L
3836#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L
3837#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L
3838#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L
3839#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L
3840//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
3841#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0
3842#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1
3843#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe
3844#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L
3845#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL
3846#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L
3847//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
3848#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0
3849#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1
3850#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe
3851#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L
3852#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL
3853#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L
3854//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
3855#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0
3856#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1
3857#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe
3858#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L
3859#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL
3860#define