| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _nbio_6_1_SH_MASK_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | // addressBlock: nbio_pcie_pswuscfg0_cfgdecp |
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| 26 | //PSWUSCFG0_VENDOR_ID |
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| 27 | #define PSWUSCFG0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
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| 28 | #define PSWUSCFG0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
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| 29 | //PSWUSCFG0_DEVICE_ID |
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| 30 | #define PSWUSCFG0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
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| 31 | #define PSWUSCFG0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
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| 32 | //PSWUSCFG0_COMMAND |
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| 33 | #define PSWUSCFG0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
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| 34 | #define PSWUSCFG0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
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| 35 | #define PSWUSCFG0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
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| 36 | #define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
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| 37 | #define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
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| 38 | #define PSWUSCFG0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
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| 39 | #define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
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| 40 | #define PSWUSCFG0_COMMAND__AD_STEPPING__SHIFT 0x7 |
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| 41 | #define PSWUSCFG0_COMMAND__SERR_EN__SHIFT 0x8 |
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| 42 | #define PSWUSCFG0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
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| 43 | #define PSWUSCFG0_COMMAND__INT_DIS__SHIFT 0xa |
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| 44 | #define PSWUSCFG0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
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| 45 | #define PSWUSCFG0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
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| 46 | #define PSWUSCFG0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
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| 47 | #define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
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| 48 | #define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
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| 49 | #define PSWUSCFG0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
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| 50 | #define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
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| 51 | #define PSWUSCFG0_COMMAND__AD_STEPPING_MASK 0x0080L |
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| 52 | #define PSWUSCFG0_COMMAND__SERR_EN_MASK 0x0100L |
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| 53 | #define PSWUSCFG0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
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| 54 | #define PSWUSCFG0_COMMAND__INT_DIS_MASK 0x0400L |
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| 55 | //PSWUSCFG0_STATUS |
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| 56 | #define PSWUSCFG0_STATUS__INT_STATUS__SHIFT 0x3 |
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| 57 | #define PSWUSCFG0_STATUS__CAP_LIST__SHIFT 0x4 |
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| 58 | #define PSWUSCFG0_STATUS__PCI_66_EN__SHIFT 0x5 |
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| 59 | #define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 60 | #define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 61 | #define PSWUSCFG0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 62 | #define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 63 | #define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 64 | #define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 65 | #define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
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| 66 | #define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 67 | #define PSWUSCFG0_STATUS__INT_STATUS_MASK 0x0008L |
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| 68 | #define PSWUSCFG0_STATUS__CAP_LIST_MASK 0x0010L |
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| 69 | #define PSWUSCFG0_STATUS__PCI_66_EN_MASK 0x0020L |
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| 70 | #define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 71 | #define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 72 | #define PSWUSCFG0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 73 | #define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 74 | #define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 75 | #define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 76 | #define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
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| 77 | #define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 78 | //PSWUSCFG0_REVISION_ID |
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| 79 | #define PSWUSCFG0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
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| 80 | #define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
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| 81 | #define PSWUSCFG0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
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| 82 | #define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
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| 83 | //PSWUSCFG0_PROG_INTERFACE |
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| 84 | #define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
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| 85 | #define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
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| 86 | //PSWUSCFG0_SUB_CLASS |
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| 87 | #define PSWUSCFG0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
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| 88 | #define PSWUSCFG0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
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| 89 | //PSWUSCFG0_BASE_CLASS |
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| 90 | #define PSWUSCFG0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
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| 91 | #define PSWUSCFG0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
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| 92 | //PSWUSCFG0_CACHE_LINE |
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| 93 | #define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
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| 94 | #define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
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| 95 | //PSWUSCFG0_LATENCY |
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| 96 | #define PSWUSCFG0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
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| 97 | #define PSWUSCFG0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
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| 98 | //PSWUSCFG0_HEADER |
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| 99 | #define 0x0 |
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| 100 | #define 0x7 |
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| 101 | #define 0x7FL |
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| 102 | #define 0x80L |
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| 103 | //PSWUSCFG0_BIST |
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| 104 | #define PSWUSCFG0_BIST__BIST_COMP__SHIFT 0x0 |
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| 105 | #define PSWUSCFG0_BIST__BIST_STRT__SHIFT 0x6 |
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| 106 | #define PSWUSCFG0_BIST__BIST_CAP__SHIFT 0x7 |
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| 107 | #define PSWUSCFG0_BIST__BIST_COMP_MASK 0x0FL |
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| 108 | #define PSWUSCFG0_BIST__BIST_STRT_MASK 0x40L |
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| 109 | #define PSWUSCFG0_BIST__BIST_CAP_MASK 0x80L |
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| 110 | //PSWUSCFG0_SUB_BUS_NUMBER_LATENCY |
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| 111 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 |
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| 112 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 |
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| 113 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 |
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| 114 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 |
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| 115 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL |
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| 116 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L |
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| 117 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L |
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| 118 | #define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L |
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| 119 | //PSWUSCFG0_IO_BASE_LIMIT |
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| 120 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 |
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| 121 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 |
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| 122 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 |
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| 123 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc |
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| 124 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL |
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| 125 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L |
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| 126 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L |
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| 127 | #define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L |
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| 128 | //PSWUSCFG0_SECONDARY_STATUS |
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| 129 | #define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 |
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| 130 | #define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 |
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| 131 | #define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
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| 132 | #define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
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| 133 | #define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
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| 134 | #define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
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| 135 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
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| 136 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
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| 137 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe |
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| 138 | #define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
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| 139 | #define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST_MASK 0x0010L |
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| 140 | #define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN_MASK 0x0020L |
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| 141 | #define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
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| 142 | #define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
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| 143 | #define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L |
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| 144 | #define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
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| 145 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
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| 146 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
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| 147 | #define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L |
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| 148 | #define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
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| 149 | //PSWUSCFG0_MEM_BASE_LIMIT |
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| 150 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 |
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| 151 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 |
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| 152 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 |
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| 153 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 |
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| 154 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL |
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| 155 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L |
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| 156 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L |
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| 157 | #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L |
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| 158 | //PSWUSCFG0_PREF_BASE_LIMIT |
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| 159 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 |
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| 160 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 |
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| 161 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 |
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| 162 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 |
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| 163 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL |
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| 164 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L |
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| 165 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L |
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| 166 | #define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L |
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| 167 | //PSWUSCFG0_PREF_BASE_UPPER |
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| 168 | #define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 |
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| 169 | #define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL |
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| 170 | //PSWUSCFG0_PREF_LIMIT_UPPER |
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| 171 | #define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 |
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| 172 | #define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL |
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| 173 | //PSWUSCFG0_IO_BASE_LIMIT_HI |
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| 174 | #define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 |
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| 175 | #define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 |
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| 176 | #define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL |
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| 177 | #define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L |
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| 178 | //PSWUSCFG0_CAP_PTR |
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| 179 | #define PSWUSCFG0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
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| 180 | #define PSWUSCFG0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
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| 181 | //PSWUSCFG0_INTERRUPT_LINE |
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| 182 | #define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
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| 183 | #define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
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| 184 | //PSWUSCFG0_INTERRUPT_PIN |
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| 185 | #define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
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| 186 | #define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
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| 187 | //PSWUSCFG0_IRQ_BRIDGE_CNTL |
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| 188 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 |
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| 189 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 |
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| 190 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 |
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| 191 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 |
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| 192 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 |
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| 193 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 |
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| 194 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 |
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| 195 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 |
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| 196 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L |
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| 197 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L |
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| 198 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L |
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| 199 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L |
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| 200 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L |
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| 201 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L |
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| 202 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L |
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| 203 | #define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L |
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| 204 | //EXT_BRIDGE_CNTL |
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| 205 | #define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 |
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| 206 | #define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L |
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| 207 | //PSWUSCFG0_VENDOR_CAP_LIST |
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| 208 | #define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 209 | #define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 210 | #define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
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| 211 | #define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
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| 212 | #define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
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| 213 | #define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
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| 214 | //PSWUSCFG0_ADAPTER_ID_W |
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| 215 | #define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
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| 216 | #define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
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| 217 | #define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
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| 218 | #define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
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| 219 | //PSWUSCFG0_PMI_CAP_LIST |
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| 220 | #define PSWUSCFG0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 221 | #define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 222 | #define PSWUSCFG0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 223 | #define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 224 | //PSWUSCFG0_PMI_CAP |
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| 225 | #define PSWUSCFG0_PMI_CAP__VERSION__SHIFT 0x0 |
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| 226 | #define PSWUSCFG0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
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| 227 | #define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
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| 228 | #define PSWUSCFG0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
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| 229 | #define PSWUSCFG0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
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| 230 | #define PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
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| 231 | #define PSWUSCFG0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
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| 232 | #define PSWUSCFG0_PMI_CAP__VERSION_MASK 0x0007L |
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| 233 | #define PSWUSCFG0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
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| 234 | #define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
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| 235 | #define PSWUSCFG0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
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| 236 | #define PSWUSCFG0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
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| 237 | #define PSWUSCFG0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
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| 238 | #define PSWUSCFG0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
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| 239 | //PSWUSCFG0_PMI_STATUS_CNTL |
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| 240 | #define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
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| 241 | #define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
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| 242 | #define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
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| 243 | #define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
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| 244 | #define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
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| 245 | #define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
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| 246 | #define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
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| 247 | #define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
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| 248 | #define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
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| 249 | #define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
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| 250 | #define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
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| 251 | #define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
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| 252 | #define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
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| 253 | #define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
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| 254 | #define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
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| 255 | #define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
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| 256 | #define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
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| 257 | #define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
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| 258 | //PSWUSCFG0_PCIE_CAP_LIST |
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| 259 | #define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 260 | #define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
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| 261 | #define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
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| 262 | #define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
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| 263 | //PSWUSCFG0_PCIE_CAP |
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| 264 | #define PSWUSCFG0_PCIE_CAP__VERSION__SHIFT 0x0 |
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| 265 | #define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
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| 266 | #define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
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| 267 | #define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
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| 268 | #define PSWUSCFG0_PCIE_CAP__VERSION_MASK 0x000FL |
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| 269 | #define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
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| 270 | #define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
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| 271 | #define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
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| 272 | //PSWUSCFG0_DEVICE_CAP |
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| 273 | #define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
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| 274 | #define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
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| 275 | #define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
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| 276 | #define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
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| 277 | #define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
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| 278 | #define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
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| 279 | #define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
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| 280 | #define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 281 | #define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 282 | #define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 283 | #define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 284 | #define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
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| 285 | #define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 286 | #define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 287 | #define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
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| 288 | #define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 289 | #define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 290 | #define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 291 | //PSWUSCFG0_DEVICE_CNTL |
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| 292 | #define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
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| 293 | #define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 294 | #define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 295 | #define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 296 | #define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 297 | #define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 298 | #define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 299 | #define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 300 | #define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 301 | #define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 302 | #define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 303 | #define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf |
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| 304 | #define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 305 | #define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 306 | #define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 307 | #define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 308 | #define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 309 | #define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 310 | #define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 311 | #define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 312 | #define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 313 | #define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 314 | #define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 315 | #define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L |
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| 316 | //PSWUSCFG0_DEVICE_STATUS |
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| 317 | #define PSWUSCFG0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 318 | #define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 319 | #define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 320 | #define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 321 | #define PSWUSCFG0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 322 | #define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 323 | #define PSWUSCFG0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 324 | #define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 325 | #define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 326 | #define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 327 | #define PSWUSCFG0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 328 | #define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 329 | //PSWUSCFG0_LINK_CAP |
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| 330 | #define PSWUSCFG0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 331 | #define PSWUSCFG0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 332 | #define PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 333 | #define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 334 | #define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 335 | #define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 336 | #define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 337 | #define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 338 | #define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 339 | #define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 340 | #define PSWUSCFG0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 341 | #define PSWUSCFG0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 342 | #define PSWUSCFG0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 343 | #define PSWUSCFG0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 344 | #define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 345 | #define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 346 | #define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 347 | #define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 348 | #define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 349 | #define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 350 | #define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 351 | #define PSWUSCFG0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 352 | //PSWUSCFG0_LINK_CNTL |
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| 353 | #define PSWUSCFG0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 354 | #define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 355 | #define PSWUSCFG0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 356 | #define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 357 | #define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 358 | #define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 359 | #define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 360 | #define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 361 | #define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 362 | #define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 363 | #define PSWUSCFG0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 364 | #define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 365 | #define PSWUSCFG0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 366 | #define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 367 | #define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 368 | #define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 369 | #define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 370 | #define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 371 | #define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 372 | #define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 373 | //PSWUSCFG0_LINK_STATUS |
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| 374 | #define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 375 | #define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 376 | #define PSWUSCFG0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 377 | #define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 378 | #define PSWUSCFG0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 379 | #define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 380 | #define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 381 | #define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 382 | #define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 383 | #define PSWUSCFG0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 384 | #define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 385 | #define PSWUSCFG0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 386 | #define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 387 | #define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 388 | //PSWUSCFG0_DEVICE_CAP2 |
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| 389 | #define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
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| 390 | #define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 391 | #define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 392 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 393 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 394 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 395 | #define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 396 | #define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
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| 397 | #define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 398 | #define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 399 | #define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 400 | #define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 401 | #define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 402 | #define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 403 | #define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
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| 404 | #define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
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| 405 | #define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
|---|
| 406 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
|---|
| 407 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
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| 408 | #define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
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| 409 | #define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 410 | #define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 411 | #define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 412 | #define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 413 | #define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 414 | #define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 415 | #define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 416 | #define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 417 | //PSWUSCFG0_DEVICE_CNTL2 |
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| 418 | #define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 419 | #define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
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| 420 | #define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 421 | #define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 422 | #define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 423 | #define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
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| 424 | #define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 425 | #define PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 426 | #define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 427 | #define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 428 | #define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 429 | #define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 430 | #define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 431 | #define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 432 | #define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 433 | #define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 434 | #define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 435 | #define PSWUSCFG0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 436 | #define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 437 | #define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 438 | //PSWUSCFG0_DEVICE_STATUS2 |
|---|
| 439 | #define PSWUSCFG0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 440 | #define PSWUSCFG0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 441 | //PSWUSCFG0_LINK_CAP2 |
|---|
| 442 | #define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 443 | #define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 444 | #define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 |
|---|
| 445 | #define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 |
|---|
| 446 | #define PSWUSCFG0_LINK_CAP2__RESERVED__SHIFT 0x13 |
|---|
| 447 | #define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 448 | #define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 449 | #define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x00000E00L |
|---|
| 450 | #define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x00070000L |
|---|
| 451 | #define PSWUSCFG0_LINK_CAP2__RESERVED_MASK 0xFFF80000L |
|---|
| 452 | //PSWUSCFG0_LINK_CNTL2 |
|---|
| 453 | #define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 454 | #define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 455 | #define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 456 | #define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 457 | #define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 458 | #define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 459 | #define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 460 | #define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 461 | #define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 462 | #define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 463 | #define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 464 | #define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 465 | #define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 466 | #define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 467 | #define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 468 | #define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 469 | //PSWUSCFG0_LINK_STATUS2 |
|---|
| 470 | #define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 471 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
|---|
| 472 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
|---|
| 473 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
|---|
| 474 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
|---|
| 475 | #define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
|---|
| 476 | #define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 477 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
|---|
| 478 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
|---|
| 479 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
|---|
| 480 | #define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
|---|
| 481 | #define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
|---|
| 482 | //PSWUSCFG0_MSI_CAP_LIST |
|---|
| 483 | #define PSWUSCFG0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 484 | #define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 485 | #define PSWUSCFG0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 486 | #define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 487 | //PSWUSCFG0_MSI_MSG_CNTL |
|---|
| 488 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 489 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 490 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 491 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 492 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 493 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 494 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 495 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 496 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 497 | #define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 498 | //PSWUSCFG0_MSI_MSG_ADDR_LO |
|---|
| 499 | #define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 500 | #define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 501 | //PSWUSCFG0_MSI_MSG_ADDR_HI |
|---|
| 502 | #define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 503 | #define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 504 | //PSWUSCFG0_MSI_MSG_DATA |
|---|
| 505 | #define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 506 | #define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
|---|
| 507 | //PSWUSCFG0_MSI_MSG_DATA_64 |
|---|
| 508 | #define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 509 | #define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL |
|---|
| 510 | //PSWUSCFG0_SSID_CAP_LIST |
|---|
| 511 | #define PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 512 | #define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 513 | #define PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 514 | #define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 515 | //PSWUSCFG0_SSID_CAP |
|---|
| 516 | #define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 517 | #define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 518 | #define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 519 | #define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 520 | //MSI_MAP_CAP_LIST |
|---|
| 521 | #define MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 522 | #define MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 523 | #define MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 524 | #define MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 525 | //MSI_MAP_CAP |
|---|
| 526 | #define MSI_MAP_CAP__EN__SHIFT 0x0 |
|---|
| 527 | #define MSI_MAP_CAP__FIXD__SHIFT 0x1 |
|---|
| 528 | #define MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb |
|---|
| 529 | #define MSI_MAP_CAP__EN_MASK 0x0001L |
|---|
| 530 | #define MSI_MAP_CAP__FIXD_MASK 0x0002L |
|---|
| 531 | #define MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L |
|---|
| 532 | //MSI_MAP_ADDR_LO |
|---|
| 533 | #define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT 0x14 |
|---|
| 534 | #define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK 0xFFF00000L |
|---|
| 535 | //MSI_MAP_ADDR_HI |
|---|
| 536 | #define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT 0x0 |
|---|
| 537 | #define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 538 | //PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 539 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 540 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 541 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 542 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 543 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 544 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 545 | //PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 546 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 547 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 548 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 549 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 550 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 551 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 552 | //PSWUSCFG0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 553 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 554 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 555 | //PSWUSCFG0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 556 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 557 | #define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 558 | //PSWUSCFG0_PCIE_VC_ENH_CAP_LIST |
|---|
| 559 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 560 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 561 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 562 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 563 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 564 | #define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 565 | //PSWUSCFG0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 566 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 567 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
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| 568 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 569 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 570 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 571 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 572 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 573 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 574 | //PSWUSCFG0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 575 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 576 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 577 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 578 | #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 579 | //PSWUSCFG0_PCIE_PORT_VC_CNTL |
|---|
| 580 | #define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 581 | #define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 582 | #define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 583 | #define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 584 | //PSWUSCFG0_PCIE_PORT_VC_STATUS |
|---|
| 585 | #define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 586 | #define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
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| 587 | //PSWUSCFG0_PCIE_VC0_RESOURCE_CAP |
|---|
| 588 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 589 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
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| 590 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
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| 591 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
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| 592 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 593 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 594 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 595 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 596 | //PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 597 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 598 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
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| 599 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
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| 600 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 601 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 602 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 603 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 604 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 605 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 606 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 607 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 608 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 609 | //PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 610 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 611 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 612 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 613 | #define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 614 | //PSWUSCFG0_PCIE_VC1_RESOURCE_CAP |
|---|
| 615 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 616 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 617 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 618 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 619 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 620 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 621 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 622 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 623 | //PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 624 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 625 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 626 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 627 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 628 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 629 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 630 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 631 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 632 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 633 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 634 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 635 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 636 | //PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 637 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 638 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 639 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 640 | #define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 641 | //PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 642 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 643 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 644 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 645 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 646 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 647 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 648 | //PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 649 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 650 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 651 | //PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 652 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 653 | #define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 654 | //PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 655 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 656 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 657 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 658 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 659 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 660 | #define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 661 | //PSWUSCFG0_PCIE_UNCORR_ERR_STATUS |
|---|
| 662 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 663 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 664 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 665 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 666 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 667 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 668 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 669 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 670 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 671 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 672 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 673 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 674 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 675 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 676 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 677 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 678 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a |
|---|
| 679 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 680 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 681 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 682 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 683 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 684 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 685 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 686 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 687 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 688 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 689 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 690 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 691 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 692 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 693 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 694 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 695 | #define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L |
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| 696 | //PSWUSCFG0_PCIE_UNCORR_ERR_MASK |
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| 697 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
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| 698 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
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| 699 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
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| 700 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
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| 701 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
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| 702 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
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| 703 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
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| 704 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
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| 705 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
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| 706 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
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| 707 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
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| 708 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
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| 709 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
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| 710 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
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| 711 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
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| 712 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
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| 713 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a |
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| 714 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
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| 715 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
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| 716 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
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| 717 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
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| 718 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
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| 719 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
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| 720 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
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| 721 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
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| 722 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
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| 723 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
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| 724 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
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| 725 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
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| 726 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
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| 727 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
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| 728 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
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| 729 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
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| 730 | #define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L |
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| 731 | //PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY |
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| 732 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
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| 733 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
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| 734 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
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| 735 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
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| 736 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
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| 737 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
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| 738 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
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| 739 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
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| 740 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
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| 741 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
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| 742 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
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| 743 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
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| 744 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
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| 745 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
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| 746 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
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| 747 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
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| 748 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a |
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| 749 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
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| 750 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
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| 751 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
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| 752 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
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| 753 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
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| 754 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
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| 755 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
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| 756 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
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| 757 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
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| 758 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
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| 759 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
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| 760 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
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| 761 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
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| 762 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
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| 763 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
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| 764 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
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| 765 | #define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L |
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| 766 | //PSWUSCFG0_PCIE_CORR_ERR_STATUS |
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| 767 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
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| 768 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
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| 769 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
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| 770 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
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| 771 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
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| 772 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
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| 773 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
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| 774 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
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| 775 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
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| 776 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
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| 777 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
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| 778 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
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| 779 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
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| 780 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
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| 781 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
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| 782 | #define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
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| 783 | //PSWUSCFG0_PCIE_CORR_ERR_MASK |
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| 784 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
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| 785 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
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| 786 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
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| 787 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
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| 788 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
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| 789 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
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| 790 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
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| 791 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
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| 792 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
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| 793 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
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| 794 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
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| 795 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
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| 796 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
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| 797 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
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| 798 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
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| 799 | #define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
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| 800 | //PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL |
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| 801 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
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| 802 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
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| 803 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
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| 804 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
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| 805 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
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| 806 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
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| 807 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
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| 808 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
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| 809 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
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| 810 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
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| 811 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
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| 812 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
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| 813 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
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| 814 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
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| 815 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
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| 816 | #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
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| 817 | //PSWUSCFG0_PCIE_HDR_LOG0 |
|---|
| 818 | #define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
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| 819 | #define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
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| 820 | //PSWUSCFG0_PCIE_HDR_LOG1 |
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| 821 | #define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
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| 822 | #define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
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| 823 | //PSWUSCFG0_PCIE_HDR_LOG2 |
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| 824 | #define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
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| 825 | #define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
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| 826 | //PSWUSCFG0_PCIE_HDR_LOG3 |
|---|
| 827 | #define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
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| 828 | #define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
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| 829 | //PSWUSCFG0_PCIE_TLP_PREFIX_LOG0 |
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| 830 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
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| 831 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 832 | //PSWUSCFG0_PCIE_TLP_PREFIX_LOG1 |
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| 833 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
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| 834 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 835 | //PSWUSCFG0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 836 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
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| 837 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 838 | //PSWUSCFG0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 839 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
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| 840 | #define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
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| 841 | //PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 842 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
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| 843 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
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| 844 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
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| 845 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
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| 846 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 847 | #define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
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| 848 | //PSWUSCFG0_PCIE_LINK_CNTL3 |
|---|
| 849 | #define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 850 | #define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
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| 851 | #define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 |
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| 852 | #define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x10 |
|---|
| 853 | #define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 854 | #define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 855 | #define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L |
|---|
| 856 | #define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFF0000L |
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| 857 | //PSWUSCFG0_PCIE_LANE_ERROR_STATUS |
|---|
| 858 | #define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 859 | #define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 860 | #define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 861 | #define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
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| 862 | //PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 863 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 864 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 865 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 866 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 867 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 868 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 869 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 870 | #define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 871 | //PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 872 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 873 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 874 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 875 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 876 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 877 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 878 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 879 | #define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 880 | //PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 881 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 882 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 883 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 884 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 885 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 886 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 887 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 888 | #define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 889 | //PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 890 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 891 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 892 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 893 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 894 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 895 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 896 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 897 | #define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 898 | //PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 899 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 900 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 901 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 902 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 903 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 904 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 905 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 906 | #define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 907 | //PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 908 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 909 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 910 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 911 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 912 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 913 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 914 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 915 | #define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 916 | //PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 917 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 918 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 919 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 920 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 921 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 922 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 923 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 924 | #define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 925 | //PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 926 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 927 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 928 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 929 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 930 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 931 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 932 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 933 | #define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 934 | //PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 935 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 936 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 937 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 938 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 939 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 940 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 941 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 942 | #define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 943 | //PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 944 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 945 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 946 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 947 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 948 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 949 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 950 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 951 | #define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 952 | //PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 953 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 954 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 955 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 956 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 957 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 958 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 959 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 960 | #define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 961 | //PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 962 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 963 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 964 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 965 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 966 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 967 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 968 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 969 | #define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 970 | //PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 971 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 972 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 973 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 974 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 975 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 976 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 977 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 978 | #define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 979 | //PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 980 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 981 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 982 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 983 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 984 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 985 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 986 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 987 | #define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 988 | //PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 989 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 990 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 991 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 992 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 993 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 994 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 995 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 996 | #define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 997 | //PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 998 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 999 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 1000 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 1001 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 1002 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 1003 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 1004 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 1005 | #define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 1006 | //PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 1007 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1008 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1009 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1010 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1011 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1012 | #define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1013 | //PSWUSCFG0_PCIE_ACS_CAP |
|---|
| 1014 | #define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 1015 | #define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 1016 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 1017 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 1018 | #define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 1019 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 1020 | #define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 1021 | #define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 1022 | #define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 1023 | #define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 1024 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 1025 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 1026 | #define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 1027 | #define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 1028 | #define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 1029 | #define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 1030 | //PSWUSCFG0_PCIE_ACS_CNTL |
|---|
| 1031 | #define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 1032 | #define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 1033 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 1034 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 1035 | #define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 1036 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 1037 | #define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 1038 | #define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 1039 | #define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 1040 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 1041 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 1042 | #define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 1043 | #define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 1044 | #define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 1045 | //PSWUSCFG0_PCIE_MC_ENH_CAP_LIST |
|---|
| 1046 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1047 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1048 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1049 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1050 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1051 | #define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1052 | //PSWUSCFG0_PCIE_MC_CAP |
|---|
| 1053 | #define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 1054 | #define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 1055 | #define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 1056 | #define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 1057 | //PSWUSCFG0_PCIE_MC_CNTL |
|---|
| 1058 | #define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 1059 | #define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 1060 | #define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 1061 | #define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 1062 | //PSWUSCFG0_PCIE_MC_ADDR0 |
|---|
| 1063 | #define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 1064 | #define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 1065 | #define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 1066 | #define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 1067 | //PSWUSCFG0_PCIE_MC_ADDR1 |
|---|
| 1068 | #define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 1069 | #define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 1070 | //PSWUSCFG0_PCIE_MC_RCV0 |
|---|
| 1071 | #define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 1072 | #define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 1073 | //PSWUSCFG0_PCIE_MC_RCV1 |
|---|
| 1074 | #define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 1075 | #define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 1076 | //PSWUSCFG0_PCIE_MC_BLOCK_ALL0 |
|---|
| 1077 | #define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 1078 | #define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 1079 | //PSWUSCFG0_PCIE_MC_BLOCK_ALL1 |
|---|
| 1080 | #define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 1081 | #define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 1082 | //PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 1083 | #define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 1084 | #define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 1085 | //PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 1086 | #define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 1087 | #define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 1088 | //PCIE_MC_OVERLAY_BAR0 |
|---|
| 1089 | #define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0 |
|---|
| 1090 | #define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6 |
|---|
| 1091 | #define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL |
|---|
| 1092 | #define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L |
|---|
| 1093 | //PCIE_MC_OVERLAY_BAR1 |
|---|
| 1094 | #define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0 |
|---|
| 1095 | #define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL |
|---|
| 1096 | //PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 1097 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1098 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1099 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1100 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1101 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1102 | #define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1103 | //PSWUSCFG0_PCIE_LTR_CAP |
|---|
| 1104 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 1105 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 1106 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 1107 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 1108 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 1109 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 1110 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 1111 | #define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 1112 | //PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 1113 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1114 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1115 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1116 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1117 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1118 | #define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1119 | //PSWUSCFG0_PCIE_ARI_CAP |
|---|
| 1120 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 1121 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 1122 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 1123 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 1124 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 1125 | #define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 1126 | //PSWUSCFG0_PCIE_ARI_CNTL |
|---|
| 1127 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 1128 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 1129 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 1130 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 1131 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 1132 | #define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 1133 | //PCIE_L1_PM_SUB_CAP_LIST |
|---|
| 1134 | #define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1135 | #define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1136 | #define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1137 | #define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1138 | #define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1139 | #define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1140 | //PCIE_L1_PM_SUB_CAP |
|---|
| 1141 | #define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0 |
|---|
| 1142 | #define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1 |
|---|
| 1143 | #define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2 |
|---|
| 1144 | #define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3 |
|---|
| 1145 | #define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4 |
|---|
| 1146 | #define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8 |
|---|
| 1147 | #define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10 |
|---|
| 1148 | #define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13 |
|---|
| 1149 | #define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L |
|---|
| 1150 | #define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L |
|---|
| 1151 | #define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L |
|---|
| 1152 | #define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L |
|---|
| 1153 | #define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L |
|---|
| 1154 | #define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L |
|---|
| 1155 | #define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L |
|---|
| 1156 | #define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L |
|---|
| 1157 | //PCIE_L1_PM_SUB_CNTL |
|---|
| 1158 | #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0 |
|---|
| 1159 | #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1 |
|---|
| 1160 | #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2 |
|---|
| 1161 | #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3 |
|---|
| 1162 | #define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8 |
|---|
| 1163 | #define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10 |
|---|
| 1164 | #define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d |
|---|
| 1165 | #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L |
|---|
| 1166 | #define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L |
|---|
| 1167 | #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L |
|---|
| 1168 | #define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L |
|---|
| 1169 | #define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L |
|---|
| 1170 | #define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L |
|---|
| 1171 | #define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L |
|---|
| 1172 | //PCIE_L1_PM_SUB_CNTL2 |
|---|
| 1173 | #define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0 |
|---|
| 1174 | #define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3 |
|---|
| 1175 | #define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L |
|---|
| 1176 | #define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L |
|---|
| 1177 | //PCIE_ESM_CAP_LIST |
|---|
| 1178 | #define PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1179 | #define PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 1180 | #define PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 1181 | #define PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 1182 | #define PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 1183 | #define PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 1184 | //PCIE_ESM_HEADER_1 |
|---|
| 1185 | #define 0x0 |
|---|
| 1186 | #define 0x10 |
|---|
| 1187 | #define 0x14 |
|---|
| 1188 | #define 0x0000FFFFL |
|---|
| 1189 | #define 0x000F0000L |
|---|
| 1190 | #define 0xFFF00000L |
|---|
| 1191 | //PCIE_ESM_HEADER_2 |
|---|
| 1192 | #define 0x0 |
|---|
| 1193 | #define 0xFFFFL |
|---|
| 1194 | //PCIE_ESM_STATUS |
|---|
| 1195 | #define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0 |
|---|
| 1196 | #define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9 |
|---|
| 1197 | #define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL |
|---|
| 1198 | #define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L |
|---|
| 1199 | //PCIE_ESM_CTRL |
|---|
| 1200 | #define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT 0x0 |
|---|
| 1201 | #define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT 0x8 |
|---|
| 1202 | #define PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf |
|---|
| 1203 | #define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK 0x007FL |
|---|
| 1204 | #define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK 0x7F00L |
|---|
| 1205 | #define PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L |
|---|
| 1206 | //PCIE_ESM_CAP_1 |
|---|
| 1207 | #define PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0 |
|---|
| 1208 | #define PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1 |
|---|
| 1209 | #define PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2 |
|---|
| 1210 | #define PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3 |
|---|
| 1211 | #define PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4 |
|---|
| 1212 | #define PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5 |
|---|
| 1213 | #define PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6 |
|---|
| 1214 | #define PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7 |
|---|
| 1215 | #define PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8 |
|---|
| 1216 | #define PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9 |
|---|
| 1217 | #define PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa |
|---|
| 1218 | #define PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb |
|---|
| 1219 | #define PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc |
|---|
| 1220 | #define PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd |
|---|
| 1221 | #define PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe |
|---|
| 1222 | #define PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf |
|---|
| 1223 | #define PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10 |
|---|
| 1224 | #define PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11 |
|---|
| 1225 | #define PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12 |
|---|
| 1226 | #define PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13 |
|---|
| 1227 | #define PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14 |
|---|
| 1228 | #define PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15 |
|---|
| 1229 | #define PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16 |
|---|
| 1230 | #define PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17 |
|---|
| 1231 | #define PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18 |
|---|
| 1232 | #define PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19 |
|---|
| 1233 | #define PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a |
|---|
| 1234 | #define PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b |
|---|
| 1235 | #define PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c |
|---|
| 1236 | #define PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d |
|---|
| 1237 | #define PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L |
|---|
| 1238 | #define PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L |
|---|
| 1239 | #define PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L |
|---|
| 1240 | #define PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L |
|---|
| 1241 | #define PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L |
|---|
| 1242 | #define PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L |
|---|
| 1243 | #define PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L |
|---|
| 1244 | #define PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L |
|---|
| 1245 | #define PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L |
|---|
| 1246 | #define PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L |
|---|
| 1247 | #define PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L |
|---|
| 1248 | #define PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L |
|---|
| 1249 | #define PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L |
|---|
| 1250 | #define PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L |
|---|
| 1251 | #define PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L |
|---|
| 1252 | #define PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L |
|---|
| 1253 | #define PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L |
|---|
| 1254 | #define PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L |
|---|
| 1255 | #define PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L |
|---|
| 1256 | #define PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L |
|---|
| 1257 | #define PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L |
|---|
| 1258 | #define PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L |
|---|
| 1259 | #define PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L |
|---|
| 1260 | #define PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L |
|---|
| 1261 | #define PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L |
|---|
| 1262 | #define PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L |
|---|
| 1263 | #define PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L |
|---|
| 1264 | #define PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L |
|---|
| 1265 | #define PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L |
|---|
| 1266 | #define PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L |
|---|
| 1267 | //PCIE_ESM_CAP_2 |
|---|
| 1268 | #define PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0 |
|---|
| 1269 | #define PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1 |
|---|
| 1270 | #define PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2 |
|---|
| 1271 | #define PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3 |
|---|
| 1272 | #define PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4 |
|---|
| 1273 | #define PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5 |
|---|
| 1274 | #define PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6 |
|---|
| 1275 | #define PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7 |
|---|
| 1276 | #define PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8 |
|---|
| 1277 | #define PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9 |
|---|
| 1278 | #define PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa |
|---|
| 1279 | #define PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb |
|---|
| 1280 | #define PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc |
|---|
| 1281 | #define PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd |
|---|
| 1282 | #define PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe |
|---|
| 1283 | #define PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf |
|---|
| 1284 | #define PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10 |
|---|
| 1285 | #define PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11 |
|---|
| 1286 | #define PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12 |
|---|
| 1287 | #define PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13 |
|---|
| 1288 | #define PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14 |
|---|
| 1289 | #define PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15 |
|---|
| 1290 | #define PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16 |
|---|
| 1291 | #define PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17 |
|---|
| 1292 | #define PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18 |
|---|
| 1293 | #define PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19 |
|---|
| 1294 | #define PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a |
|---|
| 1295 | #define PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b |
|---|
| 1296 | #define PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c |
|---|
| 1297 | #define PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d |
|---|
| 1298 | #define PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L |
|---|
| 1299 | #define PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L |
|---|
| 1300 | #define PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L |
|---|
| 1301 | #define PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L |
|---|
| 1302 | #define PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L |
|---|
| 1303 | #define PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L |
|---|
| 1304 | #define PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L |
|---|
| 1305 | #define PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L |
|---|
| 1306 | #define PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L |
|---|
| 1307 | #define PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L |
|---|
| 1308 | #define PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L |
|---|
| 1309 | #define PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L |
|---|
| 1310 | #define PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L |
|---|
| 1311 | #define PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L |
|---|
| 1312 | #define PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L |
|---|
| 1313 | #define PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L |
|---|
| 1314 | #define PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L |
|---|
| 1315 | #define PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L |
|---|
| 1316 | #define PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L |
|---|
| 1317 | #define PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L |
|---|
| 1318 | #define PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L |
|---|
| 1319 | #define PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L |
|---|
| 1320 | #define PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L |
|---|
| 1321 | #define PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L |
|---|
| 1322 | #define PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L |
|---|
| 1323 | #define PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L |
|---|
| 1324 | #define PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L |
|---|
| 1325 | #define PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L |
|---|
| 1326 | #define PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L |
|---|
| 1327 | #define PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L |
|---|
| 1328 | //PCIE_ESM_CAP_3 |
|---|
| 1329 | #define PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0 |
|---|
| 1330 | #define PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1 |
|---|
| 1331 | #define PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2 |
|---|
| 1332 | #define PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3 |
|---|
| 1333 | #define PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4 |
|---|
| 1334 | #define PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5 |
|---|
| 1335 | #define PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6 |
|---|
| 1336 | #define PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7 |
|---|
| 1337 | #define PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8 |
|---|
| 1338 | #define PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9 |
|---|
| 1339 | #define PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa |
|---|
| 1340 | #define PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb |
|---|
| 1341 | #define PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc |
|---|
| 1342 | #define PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd |
|---|
| 1343 | #define PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe |
|---|
| 1344 | #define PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf |
|---|
| 1345 | #define PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10 |
|---|
| 1346 | #define PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11 |
|---|
| 1347 | #define PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12 |
|---|
| 1348 | #define PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13 |
|---|
| 1349 | #define PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L |
|---|
| 1350 | #define PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L |
|---|
| 1351 | #define PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L |
|---|
| 1352 | #define PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L |
|---|
| 1353 | #define PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L |
|---|
| 1354 | #define PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L |
|---|
| 1355 | #define PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L |
|---|
| 1356 | #define PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L |
|---|
| 1357 | #define PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L |
|---|
| 1358 | #define PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L |
|---|
| 1359 | #define PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L |
|---|
| 1360 | #define PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L |
|---|
| 1361 | #define PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L |
|---|
| 1362 | #define PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L |
|---|
| 1363 | #define PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L |
|---|
| 1364 | #define PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L |
|---|
| 1365 | #define PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L |
|---|
| 1366 | #define PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L |
|---|
| 1367 | #define PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L |
|---|
| 1368 | #define PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L |
|---|
| 1369 | //PCIE_ESM_CAP_4 |
|---|
| 1370 | #define PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0 |
|---|
| 1371 | #define PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1 |
|---|
| 1372 | #define PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2 |
|---|
| 1373 | #define PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3 |
|---|
| 1374 | #define PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4 |
|---|
| 1375 | #define PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5 |
|---|
| 1376 | #define PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6 |
|---|
| 1377 | #define PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7 |
|---|
| 1378 | #define PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8 |
|---|
| 1379 | #define PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9 |
|---|
| 1380 | #define PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa |
|---|
| 1381 | #define PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb |
|---|
| 1382 | #define PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc |
|---|
| 1383 | #define PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd |
|---|
| 1384 | #define PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe |
|---|
| 1385 | #define PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf |
|---|
| 1386 | #define PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10 |
|---|
| 1387 | #define PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11 |
|---|
| 1388 | #define PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12 |
|---|
| 1389 | #define PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13 |
|---|
| 1390 | #define PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14 |
|---|
| 1391 | #define PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15 |
|---|
| 1392 | #define PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16 |
|---|
| 1393 | #define PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17 |
|---|
| 1394 | #define PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18 |
|---|
| 1395 | #define PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19 |
|---|
| 1396 | #define PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a |
|---|
| 1397 | #define PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b |
|---|
| 1398 | #define PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c |
|---|
| 1399 | #define PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d |
|---|
| 1400 | #define PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L |
|---|
| 1401 | #define PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L |
|---|
| 1402 | #define PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L |
|---|
| 1403 | #define PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L |
|---|
| 1404 | #define PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L |
|---|
| 1405 | #define PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L |
|---|
| 1406 | #define PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L |
|---|
| 1407 | #define PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L |
|---|
| 1408 | #define PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L |
|---|
| 1409 | #define PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L |
|---|
| 1410 | #define PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L |
|---|
| 1411 | #define PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L |
|---|
| 1412 | #define PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L |
|---|
| 1413 | #define PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L |
|---|
| 1414 | #define PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L |
|---|
| 1415 | #define PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L |
|---|
| 1416 | #define PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L |
|---|
| 1417 | #define PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L |
|---|
| 1418 | #define PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L |
|---|
| 1419 | #define PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L |
|---|
| 1420 | #define PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L |
|---|
| 1421 | #define PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L |
|---|
| 1422 | #define PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L |
|---|
| 1423 | #define PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L |
|---|
| 1424 | #define PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L |
|---|
| 1425 | #define PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L |
|---|
| 1426 | #define PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L |
|---|
| 1427 | #define PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L |
|---|
| 1428 | #define PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L |
|---|
| 1429 | #define PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L |
|---|
| 1430 | //PCIE_ESM_CAP_5 |
|---|
| 1431 | #define PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0 |
|---|
| 1432 | #define PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1 |
|---|
| 1433 | #define PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2 |
|---|
| 1434 | #define PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3 |
|---|
| 1435 | #define PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4 |
|---|
| 1436 | #define PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5 |
|---|
| 1437 | #define PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6 |
|---|
| 1438 | #define PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7 |
|---|
| 1439 | #define PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8 |
|---|
| 1440 | #define PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9 |
|---|
| 1441 | #define PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa |
|---|
| 1442 | #define PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb |
|---|
| 1443 | #define PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc |
|---|
| 1444 | #define PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd |
|---|
| 1445 | #define PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe |
|---|
| 1446 | #define PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf |
|---|
| 1447 | #define PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10 |
|---|
| 1448 | #define PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11 |
|---|
| 1449 | #define PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12 |
|---|
| 1450 | #define PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13 |
|---|
| 1451 | #define PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14 |
|---|
| 1452 | #define PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15 |
|---|
| 1453 | #define PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16 |
|---|
| 1454 | #define PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17 |
|---|
| 1455 | #define PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18 |
|---|
| 1456 | #define PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19 |
|---|
| 1457 | #define PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a |
|---|
| 1458 | #define PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b |
|---|
| 1459 | #define PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c |
|---|
| 1460 | #define PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d |
|---|
| 1461 | #define PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L |
|---|
| 1462 | #define PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L |
|---|
| 1463 | #define PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L |
|---|
| 1464 | #define PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L |
|---|
| 1465 | #define PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L |
|---|
| 1466 | #define PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L |
|---|
| 1467 | #define PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L |
|---|
| 1468 | #define PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L |
|---|
| 1469 | #define PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L |
|---|
| 1470 | #define PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L |
|---|
| 1471 | #define PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L |
|---|
| 1472 | #define PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L |
|---|
| 1473 | #define PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L |
|---|
| 1474 | #define PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L |
|---|
| 1475 | #define PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L |
|---|
| 1476 | #define PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L |
|---|
| 1477 | #define PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L |
|---|
| 1478 | #define PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L |
|---|
| 1479 | #define PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L |
|---|
| 1480 | #define PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L |
|---|
| 1481 | #define PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L |
|---|
| 1482 | #define PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L |
|---|
| 1483 | #define PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L |
|---|
| 1484 | #define PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L |
|---|
| 1485 | #define PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L |
|---|
| 1486 | #define PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L |
|---|
| 1487 | #define PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L |
|---|
| 1488 | #define PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L |
|---|
| 1489 | #define PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L |
|---|
| 1490 | #define PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L |
|---|
| 1491 | //PCIE_ESM_CAP_6 |
|---|
| 1492 | #define PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0 |
|---|
| 1493 | #define PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1 |
|---|
| 1494 | #define PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2 |
|---|
| 1495 | #define PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3 |
|---|
| 1496 | #define PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4 |
|---|
| 1497 | #define PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5 |
|---|
| 1498 | #define PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6 |
|---|
| 1499 | #define PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7 |
|---|
| 1500 | #define PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8 |
|---|
| 1501 | #define PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9 |
|---|
| 1502 | #define PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa |
|---|
| 1503 | #define PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb |
|---|
| 1504 | #define PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc |
|---|
| 1505 | #define PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd |
|---|
| 1506 | #define PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe |
|---|
| 1507 | #define PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf |
|---|
| 1508 | #define PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10 |
|---|
| 1509 | #define PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11 |
|---|
| 1510 | #define PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12 |
|---|
| 1511 | #define PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13 |
|---|
| 1512 | #define PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14 |
|---|
| 1513 | #define PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15 |
|---|
| 1514 | #define PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16 |
|---|
| 1515 | #define PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17 |
|---|
| 1516 | #define PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18 |
|---|
| 1517 | #define PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19 |
|---|
| 1518 | #define PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a |
|---|
| 1519 | #define PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b |
|---|
| 1520 | #define PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c |
|---|
| 1521 | #define PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d |
|---|
| 1522 | #define PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L |
|---|
| 1523 | #define PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L |
|---|
| 1524 | #define PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L |
|---|
| 1525 | #define PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L |
|---|
| 1526 | #define PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L |
|---|
| 1527 | #define PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L |
|---|
| 1528 | #define PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L |
|---|
| 1529 | #define PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L |
|---|
| 1530 | #define PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L |
|---|
| 1531 | #define PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L |
|---|
| 1532 | #define PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L |
|---|
| 1533 | #define PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L |
|---|
| 1534 | #define PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L |
|---|
| 1535 | #define PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L |
|---|
| 1536 | #define PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L |
|---|
| 1537 | #define PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L |
|---|
| 1538 | #define PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L |
|---|
| 1539 | #define PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L |
|---|
| 1540 | #define PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L |
|---|
| 1541 | #define PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L |
|---|
| 1542 | #define PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L |
|---|
| 1543 | #define PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L |
|---|
| 1544 | #define PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L |
|---|
| 1545 | #define PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L |
|---|
| 1546 | #define PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L |
|---|
| 1547 | #define PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L |
|---|
| 1548 | #define PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L |
|---|
| 1549 | #define PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L |
|---|
| 1550 | #define PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L |
|---|
| 1551 | #define PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L |
|---|
| 1552 | //PCIE_ESM_CAP_7 |
|---|
| 1553 | #define PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0 |
|---|
| 1554 | #define PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1 |
|---|
| 1555 | #define PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2 |
|---|
| 1556 | #define PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3 |
|---|
| 1557 | #define PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4 |
|---|
| 1558 | #define PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5 |
|---|
| 1559 | #define PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6 |
|---|
| 1560 | #define PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7 |
|---|
| 1561 | #define PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8 |
|---|
| 1562 | #define PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9 |
|---|
| 1563 | #define PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa |
|---|
| 1564 | #define PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb |
|---|
| 1565 | #define PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc |
|---|
| 1566 | #define PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd |
|---|
| 1567 | #define PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe |
|---|
| 1568 | #define PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf |
|---|
| 1569 | #define PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10 |
|---|
| 1570 | #define PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11 |
|---|
| 1571 | #define PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12 |
|---|
| 1572 | #define PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13 |
|---|
| 1573 | #define PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14 |
|---|
| 1574 | #define PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15 |
|---|
| 1575 | #define PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16 |
|---|
| 1576 | #define PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17 |
|---|
| 1577 | #define PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18 |
|---|
| 1578 | #define PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19 |
|---|
| 1579 | #define PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a |
|---|
| 1580 | #define PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b |
|---|
| 1581 | #define PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c |
|---|
| 1582 | #define PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d |
|---|
| 1583 | #define PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e |
|---|
| 1584 | #define PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L |
|---|
| 1585 | #define PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L |
|---|
| 1586 | #define PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L |
|---|
| 1587 | #define PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L |
|---|
| 1588 | #define PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L |
|---|
| 1589 | #define PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L |
|---|
| 1590 | #define PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L |
|---|
| 1591 | #define PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L |
|---|
| 1592 | #define PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L |
|---|
| 1593 | #define PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L |
|---|
| 1594 | #define PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L |
|---|
| 1595 | #define PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L |
|---|
| 1596 | #define PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L |
|---|
| 1597 | #define PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L |
|---|
| 1598 | #define PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L |
|---|
| 1599 | #define PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L |
|---|
| 1600 | #define PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L |
|---|
| 1601 | #define PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L |
|---|
| 1602 | #define PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L |
|---|
| 1603 | #define PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L |
|---|
| 1604 | #define PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L |
|---|
| 1605 | #define PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L |
|---|
| 1606 | #define PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L |
|---|
| 1607 | #define PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L |
|---|
| 1608 | #define PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L |
|---|
| 1609 | #define PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L |
|---|
| 1610 | #define PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L |
|---|
| 1611 | #define PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L |
|---|
| 1612 | #define PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L |
|---|
| 1613 | #define PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L |
|---|
| 1614 | #define PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L |
|---|
| 1615 | |
|---|
| 1616 | |
|---|
| 1617 | // addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp |
|---|
| 1618 | //BIF_CFG_DEV0_EPF0_0_VENDOR_ID |
|---|
| 1619 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 1620 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 1621 | //BIF_CFG_DEV0_EPF0_0_DEVICE_ID |
|---|
| 1622 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 1623 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 1624 | //BIF_CFG_DEV0_EPF0_0_COMMAND |
|---|
| 1625 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 1626 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 1627 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 1628 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 1629 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 1630 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 1631 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 1632 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 1633 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 1634 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 1635 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 1636 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 1637 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 1638 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 1639 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 1640 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 1641 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 1642 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 1643 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 1644 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 1645 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 1646 | #define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 1647 | //BIF_CFG_DEV0_EPF0_0_STATUS |
|---|
| 1648 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 1649 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 1650 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN__SHIFT 0x5 |
|---|
| 1651 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 1652 | #define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 1653 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 1654 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 1655 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 1656 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 1657 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 1658 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 1659 | #define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 1660 | #define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 1661 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN_MASK 0x0020L |
|---|
| 1662 | #define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 1663 | #define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 1664 | #define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 1665 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 1666 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 1667 | #define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 1668 | #define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 1669 | #define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 1670 | //BIF_CFG_DEV0_EPF0_0_REVISION_ID |
|---|
| 1671 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 1672 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 1673 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 1674 | #define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 1675 | //BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE |
|---|
| 1676 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 1677 | #define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 1678 | //BIF_CFG_DEV0_EPF0_0_SUB_CLASS |
|---|
| 1679 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 1680 | #define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 1681 | //BIF_CFG_DEV0_EPF0_0_BASE_CLASS |
|---|
| 1682 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 1683 | #define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 1684 | //BIF_CFG_DEV0_EPF0_0_CACHE_LINE |
|---|
| 1685 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 1686 | #define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 1687 | //BIF_CFG_DEV0_EPF0_0_LATENCY |
|---|
| 1688 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 1689 | #define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 1690 | //BIF_CFG_DEV0_EPF0_0_HEADER |
|---|
| 1691 | #define 0x0 |
|---|
| 1692 | #define 0x7 |
|---|
| 1693 | #define 0x7FL |
|---|
| 1694 | #define 0x80L |
|---|
| 1695 | //BIF_CFG_DEV0_EPF0_0_BIST |
|---|
| 1696 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 1697 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 1698 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 1699 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 1700 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 1701 | #define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 1702 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 |
|---|
| 1703 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 1704 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1705 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 |
|---|
| 1706 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 1707 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1708 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 |
|---|
| 1709 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 1710 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1711 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 |
|---|
| 1712 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 1713 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1714 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 |
|---|
| 1715 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 1716 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1717 | //BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 |
|---|
| 1718 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 1719 | #define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1720 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID |
|---|
| 1721 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 1722 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 1723 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 1724 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 1725 | //BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR |
|---|
| 1726 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 1727 | #define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 1728 | //BIF_CFG_DEV0_EPF0_0_CAP_PTR |
|---|
| 1729 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 1730 | #define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
|---|
| 1731 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE |
|---|
| 1732 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 1733 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 1734 | //BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN |
|---|
| 1735 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 1736 | #define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 1737 | //BIF_CFG_DEV0_EPF0_0_MIN_GRANT |
|---|
| 1738 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 1739 | #define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 1740 | //BIF_CFG_DEV0_EPF0_0_MAX_LATENCY |
|---|
| 1741 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 1742 | #define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 1743 | //BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST |
|---|
| 1744 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1745 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 1746 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 1747 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 1748 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 1749 | #define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 1750 | //BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W |
|---|
| 1751 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 1752 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 1753 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 1754 | #define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 1755 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST |
|---|
| 1756 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1757 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 1758 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 1759 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 1760 | //BIF_CFG_DEV0_EPF0_0_PMI_CAP |
|---|
| 1761 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 1762 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 1763 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 1764 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 1765 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 1766 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 1767 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 1768 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 1769 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 1770 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 1771 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 1772 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 1773 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 1774 | #define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 1775 | //BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL |
|---|
| 1776 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
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| 1777 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 1778 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 1779 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 1780 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 1781 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 1782 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
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| 1783 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 1784 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 1785 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 1786 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 1787 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 1788 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 1789 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 1790 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 1791 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 1792 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 1793 | #define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 1794 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST |
|---|
| 1795 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 1796 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 1797 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 1798 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 1799 | //BIF_CFG_DEV0_EPF0_0_PCIE_CAP |
|---|
| 1800 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 1801 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 1802 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 1803 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 1804 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 1805 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 1806 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 1807 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 1808 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP |
|---|
| 1809 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 1810 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 1811 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 1812 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 1813 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 1814 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 1815 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 1816 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
|---|
| 1817 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
|---|
| 1818 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 1819 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L |
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| 1820 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L |
|---|
| 1821 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L |
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| 1822 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L |
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| 1823 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L |
|---|
| 1824 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L |
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| 1825 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L |
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| 1826 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L |
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| 1827 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL |
|---|
| 1828 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 |
|---|
| 1829 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 |
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| 1830 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 |
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| 1831 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 |
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| 1832 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 |
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| 1833 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 |
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| 1834 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 |
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| 1835 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 |
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| 1836 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa |
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| 1837 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb |
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| 1838 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc |
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| 1839 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf |
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| 1840 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L |
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| 1841 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L |
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| 1842 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L |
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| 1843 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L |
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| 1844 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L |
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| 1845 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L |
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| 1846 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L |
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| 1847 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L |
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| 1848 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L |
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| 1849 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L |
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| 1850 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L |
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| 1851 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L |
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| 1852 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS |
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| 1853 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 |
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| 1854 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 |
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| 1855 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 |
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| 1856 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 |
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| 1857 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 |
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| 1858 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 |
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| 1859 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L |
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| 1860 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L |
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| 1861 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L |
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| 1862 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L |
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| 1863 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L |
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| 1864 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L |
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| 1865 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP |
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| 1866 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 |
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| 1867 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 |
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| 1868 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa |
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| 1869 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc |
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| 1870 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf |
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| 1871 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 |
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| 1872 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 |
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| 1873 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 |
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| 1874 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 |
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| 1875 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 |
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| 1876 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 |
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| 1877 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL |
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| 1878 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L |
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| 1879 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L |
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| 1880 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L |
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| 1881 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L |
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| 1882 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L |
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| 1883 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L |
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| 1884 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L |
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| 1885 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L |
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| 1886 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L |
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| 1887 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L |
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| 1888 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL |
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| 1889 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 |
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| 1890 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 |
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| 1891 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 |
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| 1892 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 |
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| 1893 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 |
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| 1894 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 |
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| 1895 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 |
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| 1896 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 |
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| 1897 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa |
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| 1898 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb |
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| 1899 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L |
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| 1900 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L |
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| 1901 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L |
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| 1902 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L |
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| 1903 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L |
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| 1904 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L |
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| 1905 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L |
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| 1906 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L |
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| 1907 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L |
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| 1908 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L |
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| 1909 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS |
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| 1910 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 |
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| 1911 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 |
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| 1912 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb |
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| 1913 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc |
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| 1914 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd |
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| 1915 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe |
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| 1916 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf |
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| 1917 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL |
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| 1918 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L |
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| 1919 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L |
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| 1920 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L |
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| 1921 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L |
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| 1922 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L |
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| 1923 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L |
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| 1924 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 |
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| 1925 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 |
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| 1926 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 |
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| 1927 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 |
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| 1928 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 |
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| 1929 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 |
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| 1930 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 |
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| 1931 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 |
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| 1932 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa |
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| 1933 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb |
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| 1934 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc |
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| 1935 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 |
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| 1936 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 |
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| 1937 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 |
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| 1938 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 |
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| 1939 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL |
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| 1940 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L |
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| 1941 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L |
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| 1942 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L |
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| 1943 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L |
|---|
| 1944 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L |
|---|
| 1945 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L |
|---|
| 1946 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L |
|---|
| 1947 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L |
|---|
| 1948 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L |
|---|
| 1949 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L |
|---|
| 1950 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L |
|---|
| 1951 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L |
|---|
| 1952 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L |
|---|
| 1953 | //BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 |
|---|
| 1954 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 |
|---|
| 1955 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 |
|---|
| 1956 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 |
|---|
| 1957 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 |
|---|
| 1958 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 |
|---|
| 1959 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 |
|---|
| 1960 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 |
|---|
| 1961 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa |
|---|
| 1962 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd |
|---|
| 1963 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf |
|---|
| 1964 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL |
|---|
| 1965 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L |
|---|
| 1966 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L |
|---|
| 1967 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L |
|---|
| 1968 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L |
|---|
| 1969 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L |
|---|
| 1970 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L |
|---|
| 1971 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L |
|---|
| 1972 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L |
|---|
| 1973 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L |
|---|
| 1974 | //BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 |
|---|
| 1975 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 1976 | #define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 1977 | //BIF_CFG_DEV0_EPF0_0_LINK_CAP2 |
|---|
| 1978 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 |
|---|
| 1979 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 |
|---|
| 1980 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED__SHIFT 0x9 |
|---|
| 1981 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL |
|---|
| 1982 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L |
|---|
| 1983 | #define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED_MASK 0xFFFFFE00L |
|---|
| 1984 | //BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 |
|---|
| 1985 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 |
|---|
| 1986 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 |
|---|
| 1987 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 |
|---|
| 1988 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 |
|---|
| 1989 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 |
|---|
| 1990 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa |
|---|
| 1991 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb |
|---|
| 1992 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc |
|---|
| 1993 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL |
|---|
| 1994 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L |
|---|
| 1995 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L |
|---|
| 1996 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L |
|---|
| 1997 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L |
|---|
| 1998 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L |
|---|
| 1999 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L |
|---|
| 2000 | #define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L |
|---|
| 2001 | //BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 |
|---|
| 2002 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 |
|---|
| 2003 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 |
|---|
| 2004 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 |
|---|
| 2005 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 |
|---|
| 2006 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 |
|---|
| 2007 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 |
|---|
| 2008 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L |
|---|
| 2009 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK 0x0002L |
|---|
| 2010 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK 0x0004L |
|---|
| 2011 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK 0x0008L |
|---|
| 2012 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK 0x0010L |
|---|
| 2013 | #define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK 0x0020L |
|---|
| 2014 | //BIF_CFG_DEV0_EPF0_0_SLOT_CAP2 |
|---|
| 2015 | #define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED__SHIFT 0x0 |
|---|
| 2016 | #define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL |
|---|
| 2017 | //BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 |
|---|
| 2018 | #define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0 |
|---|
| 2019 | #define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL |
|---|
| 2020 | //BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 |
|---|
| 2021 | #define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0 |
|---|
| 2022 | #define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL |
|---|
| 2023 | //BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST |
|---|
| 2024 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2025 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2026 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2027 | #define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2028 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL |
|---|
| 2029 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 |
|---|
| 2030 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 |
|---|
| 2031 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 |
|---|
| 2032 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 |
|---|
| 2033 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 |
|---|
| 2034 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L |
|---|
| 2035 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL |
|---|
| 2036 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L |
|---|
| 2037 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L |
|---|
| 2038 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L |
|---|
| 2039 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO |
|---|
| 2040 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 |
|---|
| 2041 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL |
|---|
| 2042 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI |
|---|
| 2043 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 |
|---|
| 2044 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL |
|---|
| 2045 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA |
|---|
| 2046 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 |
|---|
| 2047 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0x0000FFFFL |
|---|
| 2048 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK |
|---|
| 2049 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 |
|---|
| 2050 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL |
|---|
| 2051 | //BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 |
|---|
| 2052 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 |
|---|
| 2053 | #define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0x0000FFFFL |
|---|
| 2054 | //BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 |
|---|
| 2055 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 |
|---|
| 2056 | #define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL |
|---|
| 2057 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING |
|---|
| 2058 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 |
|---|
| 2059 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL |
|---|
| 2060 | //BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 |
|---|
| 2061 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 |
|---|
| 2062 | #define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL |
|---|
| 2063 | //BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST |
|---|
| 2064 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2065 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 2066 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 2067 | #define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 2068 | //BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL |
|---|
| 2069 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 |
|---|
| 2070 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe |
|---|
| 2071 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf |
|---|
| 2072 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL |
|---|
| 2073 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L |
|---|
| 2074 | #define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L |
|---|
| 2075 | //BIF_CFG_DEV0_EPF0_0_MSIX_TABLE |
|---|
| 2076 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 |
|---|
| 2077 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 |
|---|
| 2078 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L |
|---|
| 2079 | #define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 2080 | //BIF_CFG_DEV0_EPF0_0_MSIX_PBA |
|---|
| 2081 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 |
|---|
| 2082 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 |
|---|
| 2083 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L |
|---|
| 2084 | #define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 2085 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST |
|---|
| 2086 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2087 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2088 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2089 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2090 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2091 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2092 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR |
|---|
| 2093 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 |
|---|
| 2094 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 |
|---|
| 2095 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 2096 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 2097 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L |
|---|
| 2098 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 2099 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 |
|---|
| 2100 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 |
|---|
| 2101 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 2102 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 |
|---|
| 2103 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 |
|---|
| 2104 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL |
|---|
| 2105 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST |
|---|
| 2106 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2107 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2108 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2109 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2110 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2111 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2112 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 |
|---|
| 2113 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 |
|---|
| 2114 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 |
|---|
| 2115 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 |
|---|
| 2116 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa |
|---|
| 2117 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L |
|---|
| 2118 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L |
|---|
| 2119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L |
|---|
| 2120 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L |
|---|
| 2121 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 |
|---|
| 2122 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 |
|---|
| 2123 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2124 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL |
|---|
| 2125 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2126 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL |
|---|
| 2127 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 |
|---|
| 2128 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 |
|---|
| 2129 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L |
|---|
| 2130 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL |
|---|
| 2131 | //BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS |
|---|
| 2132 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 2133 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 2134 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP |
|---|
| 2135 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 2136 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 2137 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 2138 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2139 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 2140 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 2141 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 2142 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2143 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL |
|---|
| 2144 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 2145 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 2146 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 2147 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 2148 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 2149 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 2150 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 2151 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 2152 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 2153 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 2154 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 2155 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 2156 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS |
|---|
| 2157 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 2158 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 2159 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 2160 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 2161 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP |
|---|
| 2162 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 |
|---|
| 2163 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf |
|---|
| 2164 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 |
|---|
| 2165 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 |
|---|
| 2166 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL |
|---|
| 2167 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L |
|---|
| 2168 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L |
|---|
| 2169 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L |
|---|
| 2170 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL |
|---|
| 2171 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 |
|---|
| 2172 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 |
|---|
| 2173 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 |
|---|
| 2174 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 |
|---|
| 2175 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 |
|---|
| 2176 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f |
|---|
| 2177 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L |
|---|
| 2178 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL |
|---|
| 2179 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L |
|---|
| 2180 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L |
|---|
| 2181 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L |
|---|
| 2182 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L |
|---|
| 2183 | //BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS |
|---|
| 2184 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 |
|---|
| 2185 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 |
|---|
| 2186 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L |
|---|
| 2187 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L |
|---|
| 2188 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST |
|---|
| 2189 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2190 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2191 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2192 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2193 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2194 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2195 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 |
|---|
| 2196 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 |
|---|
| 2197 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL |
|---|
| 2198 | //BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 |
|---|
| 2199 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 |
|---|
| 2200 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL |
|---|
| 2201 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST |
|---|
| 2202 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2203 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2204 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2205 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2206 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2207 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2208 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS |
|---|
| 2209 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 |
|---|
| 2210 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 |
|---|
| 2211 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc |
|---|
| 2212 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd |
|---|
| 2213 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe |
|---|
| 2214 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf |
|---|
| 2215 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 |
|---|
| 2216 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 |
|---|
| 2217 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 |
|---|
| 2218 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 |
|---|
| 2219 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 |
|---|
| 2220 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 |
|---|
| 2221 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 |
|---|
| 2222 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 |
|---|
| 2223 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 |
|---|
| 2224 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 |
|---|
| 2225 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L |
|---|
| 2226 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L |
|---|
| 2227 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L |
|---|
| 2228 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L |
|---|
| 2229 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L |
|---|
| 2230 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L |
|---|
| 2231 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L |
|---|
| 2232 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L |
|---|
| 2233 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L |
|---|
| 2234 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L |
|---|
| 2235 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L |
|---|
| 2236 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L |
|---|
| 2237 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L |
|---|
| 2238 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L |
|---|
| 2239 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L |
|---|
| 2240 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L |
|---|
| 2241 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK |
|---|
| 2242 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 |
|---|
| 2243 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 |
|---|
| 2244 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc |
|---|
| 2245 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd |
|---|
| 2246 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe |
|---|
| 2247 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf |
|---|
| 2248 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 |
|---|
| 2249 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 |
|---|
| 2250 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 |
|---|
| 2251 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 |
|---|
| 2252 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 |
|---|
| 2253 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 |
|---|
| 2254 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 |
|---|
| 2255 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 |
|---|
| 2256 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 |
|---|
| 2257 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 |
|---|
| 2258 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L |
|---|
| 2259 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L |
|---|
| 2260 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L |
|---|
| 2261 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L |
|---|
| 2262 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L |
|---|
| 2263 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L |
|---|
| 2264 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L |
|---|
| 2265 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L |
|---|
| 2266 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L |
|---|
| 2267 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L |
|---|
| 2268 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L |
|---|
| 2269 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L |
|---|
| 2270 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L |
|---|
| 2271 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L |
|---|
| 2272 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L |
|---|
| 2273 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L |
|---|
| 2274 | //BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY |
|---|
| 2275 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 |
|---|
| 2276 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 |
|---|
| 2277 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc |
|---|
| 2278 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd |
|---|
| 2279 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe |
|---|
| 2280 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf |
|---|
| 2281 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 |
|---|
| 2282 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 |
|---|
| 2283 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 |
|---|
| 2284 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 |
|---|
| 2285 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 |
|---|
| 2286 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 |
|---|
| 2287 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 |
|---|
| 2288 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 |
|---|
| 2289 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 |
|---|
| 2290 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 |
|---|
| 2291 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L |
|---|
| 2292 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L |
|---|
| 2293 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L |
|---|
| 2294 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L |
|---|
| 2295 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L |
|---|
| 2296 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L |
|---|
| 2297 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L |
|---|
| 2298 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L |
|---|
| 2299 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L |
|---|
| 2300 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L |
|---|
| 2301 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L |
|---|
| 2302 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L |
|---|
| 2303 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L |
|---|
| 2304 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L |
|---|
| 2305 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L |
|---|
| 2306 | #define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L |
|---|
| 2307 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS |
|---|
| 2308 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 |
|---|
| 2309 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 |
|---|
| 2310 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 |
|---|
| 2311 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 |
|---|
| 2312 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc |
|---|
| 2313 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd |
|---|
| 2314 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe |
|---|
| 2315 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf |
|---|
| 2316 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L |
|---|
| 2317 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L |
|---|
| 2318 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L |
|---|
| 2319 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L |
|---|
| 2320 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L |
|---|
| 2321 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L |
|---|
| 2322 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L |
|---|
| 2323 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L |
|---|
| 2324 | //BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK |
|---|
| 2325 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 |
|---|
| 2326 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 |
|---|
| 2327 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 |
|---|
| 2328 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 |
|---|
| 2329 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc |
|---|
| 2330 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd |
|---|
| 2331 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe |
|---|
| 2332 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf |
|---|
| 2333 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L |
|---|
| 2334 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L |
|---|
| 2335 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L |
|---|
| 2336 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L |
|---|
| 2337 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L |
|---|
| 2338 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L |
|---|
| 2339 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L |
|---|
| 2340 | #define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L |
|---|
| 2341 | //BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL |
|---|
| 2342 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 |
|---|
| 2343 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 |
|---|
| 2344 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 |
|---|
| 2345 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 |
|---|
| 2346 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 |
|---|
| 2347 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 |
|---|
| 2348 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa |
|---|
| 2349 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb |
|---|
| 2350 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL |
|---|
| 2351 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L |
|---|
| 2352 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L |
|---|
| 2353 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L |
|---|
| 2354 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L |
|---|
| 2355 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L |
|---|
| 2356 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L |
|---|
| 2357 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L |
|---|
| 2358 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 |
|---|
| 2359 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 |
|---|
| 2360 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 2361 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 |
|---|
| 2362 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 |
|---|
| 2363 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 2364 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 |
|---|
| 2365 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 |
|---|
| 2366 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 2367 | //BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 |
|---|
| 2368 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 |
|---|
| 2369 | #define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL |
|---|
| 2370 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 |
|---|
| 2371 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 |
|---|
| 2372 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 2373 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 |
|---|
| 2374 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 |
|---|
| 2375 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 2376 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 |
|---|
| 2377 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 |
|---|
| 2378 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 2379 | //BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 |
|---|
| 2380 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 |
|---|
| 2381 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL |
|---|
| 2382 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST |
|---|
| 2383 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2384 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2385 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2386 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2387 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2388 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2389 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP |
|---|
| 2390 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2391 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2392 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL |
|---|
| 2393 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2394 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2395 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2396 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2397 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2398 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2399 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP |
|---|
| 2400 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2401 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2402 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL |
|---|
| 2403 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2404 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2405 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2406 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2407 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2408 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2409 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP |
|---|
| 2410 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2411 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2412 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL |
|---|
| 2413 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2414 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2415 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2416 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2417 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2418 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2419 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP |
|---|
| 2420 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2421 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2422 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL |
|---|
| 2423 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2424 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2425 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2426 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2427 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2428 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2429 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP |
|---|
| 2430 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2431 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2432 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL |
|---|
| 2433 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2434 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2435 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2436 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2437 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2438 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2439 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP |
|---|
| 2440 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 |
|---|
| 2441 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0x00FFFFF0L |
|---|
| 2442 | //BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL |
|---|
| 2443 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 |
|---|
| 2444 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 |
|---|
| 2445 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 |
|---|
| 2446 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x0007L |
|---|
| 2447 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x00E0L |
|---|
| 2448 | #define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x1F00L |
|---|
| 2449 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST |
|---|
| 2450 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2451 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2452 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2453 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2454 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2455 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2456 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT |
|---|
| 2457 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 |
|---|
| 2458 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL |
|---|
| 2459 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA |
|---|
| 2460 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 |
|---|
| 2461 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 |
|---|
| 2462 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa |
|---|
| 2463 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd |
|---|
| 2464 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf |
|---|
| 2465 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 |
|---|
| 2466 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL |
|---|
| 2467 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L |
|---|
| 2468 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L |
|---|
| 2469 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L |
|---|
| 2470 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L |
|---|
| 2471 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L |
|---|
| 2472 | //BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP |
|---|
| 2473 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 |
|---|
| 2474 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L |
|---|
| 2475 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST |
|---|
| 2476 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2477 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2478 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2479 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2480 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2481 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2482 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP |
|---|
| 2483 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 |
|---|
| 2484 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 |
|---|
| 2485 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc |
|---|
| 2486 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 |
|---|
| 2487 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 |
|---|
| 2488 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL |
|---|
| 2489 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L |
|---|
| 2490 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L |
|---|
| 2491 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L |
|---|
| 2492 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L |
|---|
| 2493 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR |
|---|
| 2494 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 |
|---|
| 2495 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL |
|---|
| 2496 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS |
|---|
| 2497 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 |
|---|
| 2498 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 |
|---|
| 2499 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL |
|---|
| 2500 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L |
|---|
| 2501 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL |
|---|
| 2502 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 |
|---|
| 2503 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x1FL |
|---|
| 2504 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 |
|---|
| 2505 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2506 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2507 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 |
|---|
| 2508 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2509 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2510 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 |
|---|
| 2511 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2512 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2513 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 |
|---|
| 2514 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2515 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2516 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 |
|---|
| 2517 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2518 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2519 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 |
|---|
| 2520 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2521 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2522 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 |
|---|
| 2523 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2524 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2525 | //BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 |
|---|
| 2526 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 |
|---|
| 2527 | #define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL |
|---|
| 2528 | //BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST |
|---|
| 2529 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2530 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2531 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2532 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2533 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2534 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2535 | //BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 |
|---|
| 2536 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 |
|---|
| 2537 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 |
|---|
| 2538 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 |
|---|
| 2539 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L |
|---|
| 2540 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L |
|---|
| 2541 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK 0xFFFFFFFCL |
|---|
| 2542 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS |
|---|
| 2543 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 |
|---|
| 2544 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 |
|---|
| 2545 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL |
|---|
| 2546 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK 0xFFFF0000L |
|---|
| 2547 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL |
|---|
| 2548 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2549 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2550 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2551 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2552 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2553 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2554 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2555 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2556 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2557 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2558 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL |
|---|
| 2559 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2560 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2561 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2562 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2563 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2564 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2565 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2566 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2567 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2568 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2569 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL |
|---|
| 2570 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2571 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2572 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2573 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2574 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2575 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2576 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2577 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2578 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2579 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2580 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL |
|---|
| 2581 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2582 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2583 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2584 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2585 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2586 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2587 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2588 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2589 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2590 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2591 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL |
|---|
| 2592 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2593 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2594 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2595 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2596 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2597 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2598 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2599 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2600 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2601 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2602 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL |
|---|
| 2603 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2604 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2605 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2606 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2607 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2608 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2609 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2610 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2611 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2612 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2613 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL |
|---|
| 2614 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2615 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2616 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2617 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2618 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2619 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2620 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2621 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2622 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2623 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2624 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL |
|---|
| 2625 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2626 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2627 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2628 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2629 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2630 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2631 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2632 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2633 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2634 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2635 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL |
|---|
| 2636 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2637 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2638 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2639 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2640 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2641 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2642 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2643 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2644 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2645 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2646 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL |
|---|
| 2647 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2648 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2649 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2650 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2651 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2652 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2653 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2654 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2655 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2656 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2657 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL |
|---|
| 2658 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2659 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2660 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2661 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2662 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2663 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2664 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2665 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2666 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2667 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2668 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL |
|---|
| 2669 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2670 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2671 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2672 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2673 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2674 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2675 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2676 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2677 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2678 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2679 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL |
|---|
| 2680 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2681 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2682 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2683 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2684 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2685 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2686 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2687 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2688 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2689 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2690 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL |
|---|
| 2691 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2692 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2693 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2694 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2695 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2696 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2697 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2698 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2699 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2700 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2701 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL |
|---|
| 2702 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2703 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2704 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2705 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2706 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2707 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2708 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2709 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2710 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2711 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2712 | //BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL |
|---|
| 2713 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 |
|---|
| 2714 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 |
|---|
| 2715 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 |
|---|
| 2716 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc |
|---|
| 2717 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf |
|---|
| 2718 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL |
|---|
| 2719 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L |
|---|
| 2720 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L |
|---|
| 2721 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L |
|---|
| 2722 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK 0x8000L |
|---|
| 2723 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST |
|---|
| 2724 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2725 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2726 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2727 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2728 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2729 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2730 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP |
|---|
| 2731 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 |
|---|
| 2732 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 |
|---|
| 2733 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 |
|---|
| 2734 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 |
|---|
| 2735 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 |
|---|
| 2736 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 |
|---|
| 2737 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 |
|---|
| 2738 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 |
|---|
| 2739 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L |
|---|
| 2740 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L |
|---|
| 2741 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L |
|---|
| 2742 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L |
|---|
| 2743 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L |
|---|
| 2744 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L |
|---|
| 2745 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L |
|---|
| 2746 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L |
|---|
| 2747 | //BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL |
|---|
| 2748 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 |
|---|
| 2749 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 |
|---|
| 2750 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 |
|---|
| 2751 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 |
|---|
| 2752 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 |
|---|
| 2753 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 |
|---|
| 2754 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 |
|---|
| 2755 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L |
|---|
| 2756 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L |
|---|
| 2757 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L |
|---|
| 2758 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L |
|---|
| 2759 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L |
|---|
| 2760 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L |
|---|
| 2761 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L |
|---|
| 2762 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST |
|---|
| 2763 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2764 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2765 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2766 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2767 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2768 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2769 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP |
|---|
| 2770 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 |
|---|
| 2771 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 |
|---|
| 2772 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 |
|---|
| 2773 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL |
|---|
| 2774 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L |
|---|
| 2775 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L |
|---|
| 2776 | //BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL |
|---|
| 2777 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 |
|---|
| 2778 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf |
|---|
| 2779 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL |
|---|
| 2780 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L |
|---|
| 2781 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST |
|---|
| 2782 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2783 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2784 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2785 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2786 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2787 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2788 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL |
|---|
| 2789 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 |
|---|
| 2790 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 |
|---|
| 2791 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L |
|---|
| 2792 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L |
|---|
| 2793 | //BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS |
|---|
| 2794 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 |
|---|
| 2795 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 |
|---|
| 2796 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 |
|---|
| 2797 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf |
|---|
| 2798 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L |
|---|
| 2799 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L |
|---|
| 2800 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L |
|---|
| 2801 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L |
|---|
| 2802 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY |
|---|
| 2803 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 |
|---|
| 2804 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL |
|---|
| 2805 | //BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC |
|---|
| 2806 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 |
|---|
| 2807 | #define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL |
|---|
| 2808 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST |
|---|
| 2809 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2810 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2811 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2812 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2813 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2814 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2815 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP |
|---|
| 2816 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 |
|---|
| 2817 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 2818 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 |
|---|
| 2819 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L |
|---|
| 2820 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L |
|---|
| 2821 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L |
|---|
| 2822 | //BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL |
|---|
| 2823 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 |
|---|
| 2824 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 |
|---|
| 2825 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 |
|---|
| 2826 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L |
|---|
| 2827 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L |
|---|
| 2828 | #define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L |
|---|
| 2829 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST |
|---|
| 2830 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2831 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2832 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2833 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2834 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2835 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2836 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP |
|---|
| 2837 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 |
|---|
| 2838 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 |
|---|
| 2839 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 |
|---|
| 2840 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 |
|---|
| 2841 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 |
|---|
| 2842 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 |
|---|
| 2843 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L |
|---|
| 2844 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L |
|---|
| 2845 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L |
|---|
| 2846 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L |
|---|
| 2847 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L |
|---|
| 2848 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L |
|---|
| 2849 | //BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL |
|---|
| 2850 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 |
|---|
| 2851 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 |
|---|
| 2852 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L |
|---|
| 2853 | #define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L |
|---|
| 2854 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST |
|---|
| 2855 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2856 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2857 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2858 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2859 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2860 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2861 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP |
|---|
| 2862 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 |
|---|
| 2863 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 |
|---|
| 2864 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf |
|---|
| 2865 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL |
|---|
| 2866 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L |
|---|
| 2867 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L |
|---|
| 2868 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL |
|---|
| 2869 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 |
|---|
| 2870 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf |
|---|
| 2871 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL |
|---|
| 2872 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L |
|---|
| 2873 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 |
|---|
| 2874 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 |
|---|
| 2875 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc |
|---|
| 2876 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL |
|---|
| 2877 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L |
|---|
| 2878 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 |
|---|
| 2879 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 |
|---|
| 2880 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL |
|---|
| 2881 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 |
|---|
| 2882 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 |
|---|
| 2883 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL |
|---|
| 2884 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 |
|---|
| 2885 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 |
|---|
| 2886 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL |
|---|
| 2887 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 |
|---|
| 2888 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 |
|---|
| 2889 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL |
|---|
| 2890 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 |
|---|
| 2891 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 |
|---|
| 2892 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL |
|---|
| 2893 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 |
|---|
| 2894 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 |
|---|
| 2895 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL |
|---|
| 2896 | //BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 |
|---|
| 2897 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 |
|---|
| 2898 | #define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL |
|---|
| 2899 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST |
|---|
| 2900 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2901 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2902 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2903 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2904 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2905 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2906 | //BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP |
|---|
| 2907 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 |
|---|
| 2908 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa |
|---|
| 2909 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 |
|---|
| 2910 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a |
|---|
| 2911 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL |
|---|
| 2912 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L |
|---|
| 2913 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L |
|---|
| 2914 | #define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L |
|---|
| 2915 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST |
|---|
| 2916 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2917 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2918 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2919 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2920 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2921 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2922 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP |
|---|
| 2923 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 |
|---|
| 2924 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 |
|---|
| 2925 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 |
|---|
| 2926 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L |
|---|
| 2927 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L |
|---|
| 2928 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L |
|---|
| 2929 | //BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL |
|---|
| 2930 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 |
|---|
| 2931 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 |
|---|
| 2932 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 |
|---|
| 2933 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L |
|---|
| 2934 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L |
|---|
| 2935 | #define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L |
|---|
| 2936 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST |
|---|
| 2937 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 2938 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 |
|---|
| 2939 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 |
|---|
| 2940 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL |
|---|
| 2941 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L |
|---|
| 2942 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 2943 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP |
|---|
| 2944 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 |
|---|
| 2945 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 |
|---|
| 2946 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 |
|---|
| 2947 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L |
|---|
| 2948 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L |
|---|
| 2949 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L |
|---|
| 2950 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL |
|---|
| 2951 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 |
|---|
| 2952 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 |
|---|
| 2953 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 |
|---|
| 2954 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 |
|---|
| 2955 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 |
|---|
| 2956 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L |
|---|
| 2957 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L |
|---|
| 2958 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L |
|---|
| 2959 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L |
|---|
| 2960 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L |
|---|
| 2961 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS |
|---|
| 2962 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 |
|---|
| 2963 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L |
|---|
| 2964 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS |
|---|
| 2965 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 |
|---|
| 2966 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL |
|---|
| 2967 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS |
|---|
| 2968 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 |
|---|
| 2969 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL |
|---|
| 2970 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS |
|---|
| 2971 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 |
|---|
| 2972 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL |
|---|
| 2973 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK |
|---|
| 2974 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 |
|---|
| 2975 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0x00FFL |
|---|
| 2976 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET |
|---|
| 2977 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 |
|---|
| 2978 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL |
|---|
| 2979 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE |
|---|
| 2980 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 |
|---|
| 2981 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL |
|---|
| 2982 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID |
|---|
| 2983 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 |
|---|
| 2984 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL |
|---|
| 2985 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE |
|---|
| 2986 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 |
|---|
| 2987 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 2988 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE |
|---|
| 2989 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 |
|---|
| 2990 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL |
|---|
| 2991 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 |
|---|
| 2992 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 2993 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 2994 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 |
|---|
| 2995 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 2996 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 2997 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 |
|---|
| 2998 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 2999 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3000 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 |
|---|
| 3001 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 3002 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3003 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 |
|---|
| 3004 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 3005 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3006 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 |
|---|
| 3007 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 |
|---|
| 3008 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3009 | //BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET |
|---|
| 3010 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 |
|---|
| 3011 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 |
|---|
| 3012 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK 0x00000007L |
|---|
| 3013 | #define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L |
|---|
| 3014 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV |
|---|
| 3015 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 |
|---|
| 3016 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 |
|---|
| 3017 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 |
|---|
| 3018 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL |
|---|
| 3019 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L |
|---|
| 3020 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L |
|---|
| 3021 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV |
|---|
| 3022 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 |
|---|
| 3023 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 |
|---|
| 3024 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 |
|---|
| 3025 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL |
|---|
| 3026 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L |
|---|
| 3027 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L |
|---|
| 3028 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW |
|---|
| 3029 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 |
|---|
| 3030 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 |
|---|
| 3031 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L |
|---|
| 3032 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L |
|---|
| 3033 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE |
|---|
| 3034 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 |
|---|
| 3035 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 |
|---|
| 3036 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 |
|---|
| 3037 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 |
|---|
| 3038 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 |
|---|
| 3039 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 |
|---|
| 3040 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa |
|---|
| 3041 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb |
|---|
| 3042 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 |
|---|
| 3043 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 |
|---|
| 3044 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 |
|---|
| 3045 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 |
|---|
| 3046 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 |
|---|
| 3047 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 |
|---|
| 3048 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L |
|---|
| 3049 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L |
|---|
| 3050 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L |
|---|
| 3051 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L |
|---|
| 3052 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L |
|---|
| 3053 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L |
|---|
| 3054 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L |
|---|
| 3055 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L |
|---|
| 3056 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L |
|---|
| 3057 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L |
|---|
| 3058 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L |
|---|
| 3059 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L |
|---|
| 3060 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L |
|---|
| 3061 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L |
|---|
| 3062 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS |
|---|
| 3063 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 |
|---|
| 3064 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 |
|---|
| 3065 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 |
|---|
| 3066 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 |
|---|
| 3067 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 |
|---|
| 3068 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 |
|---|
| 3069 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa |
|---|
| 3070 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb |
|---|
| 3071 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 |
|---|
| 3072 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 |
|---|
| 3073 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 |
|---|
| 3074 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 |
|---|
| 3075 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 |
|---|
| 3076 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 |
|---|
| 3077 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L |
|---|
| 3078 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L |
|---|
| 3079 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L |
|---|
| 3080 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L |
|---|
| 3081 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L |
|---|
| 3082 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L |
|---|
| 3083 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L |
|---|
| 3084 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L |
|---|
| 3085 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L |
|---|
| 3086 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L |
|---|
| 3087 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L |
|---|
| 3088 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L |
|---|
| 3089 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L |
|---|
| 3090 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L |
|---|
| 3091 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL |
|---|
| 3092 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 |
|---|
| 3093 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L |
|---|
| 3094 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 |
|---|
| 3095 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 |
|---|
| 3096 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 |
|---|
| 3097 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf |
|---|
| 3098 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 |
|---|
| 3099 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 |
|---|
| 3100 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL |
|---|
| 3101 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L |
|---|
| 3102 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L |
|---|
| 3103 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L |
|---|
| 3104 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L |
|---|
| 3105 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 |
|---|
| 3106 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 |
|---|
| 3107 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 |
|---|
| 3108 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 |
|---|
| 3109 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 |
|---|
| 3110 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 |
|---|
| 3111 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 |
|---|
| 3112 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 |
|---|
| 3113 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 |
|---|
| 3114 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 |
|---|
| 3115 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 |
|---|
| 3116 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa |
|---|
| 3117 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb |
|---|
| 3118 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc |
|---|
| 3119 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd |
|---|
| 3120 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe |
|---|
| 3121 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf |
|---|
| 3122 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 |
|---|
| 3123 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 |
|---|
| 3124 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 |
|---|
| 3125 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 |
|---|
| 3126 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 |
|---|
| 3127 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 |
|---|
| 3128 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 |
|---|
| 3129 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 |
|---|
| 3130 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 |
|---|
| 3131 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 |
|---|
| 3132 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a |
|---|
| 3133 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b |
|---|
| 3134 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c |
|---|
| 3135 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d |
|---|
| 3136 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e |
|---|
| 3137 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f |
|---|
| 3138 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L |
|---|
| 3139 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L |
|---|
| 3140 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L |
|---|
| 3141 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L |
|---|
| 3142 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L |
|---|
| 3143 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L |
|---|
| 3144 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L |
|---|
| 3145 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L |
|---|
| 3146 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L |
|---|
| 3147 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L |
|---|
| 3148 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L |
|---|
| 3149 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L |
|---|
| 3150 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L |
|---|
| 3151 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L |
|---|
| 3152 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L |
|---|
| 3153 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L |
|---|
| 3154 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L |
|---|
| 3155 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L |
|---|
| 3156 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L |
|---|
| 3157 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L |
|---|
| 3158 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L |
|---|
| 3159 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L |
|---|
| 3160 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L |
|---|
| 3161 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L |
|---|
| 3162 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L |
|---|
| 3163 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L |
|---|
| 3164 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L |
|---|
| 3165 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L |
|---|
| 3166 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L |
|---|
| 3167 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L |
|---|
| 3168 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L |
|---|
| 3169 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L |
|---|
| 3170 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 |
|---|
| 3171 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 |
|---|
| 3172 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 |
|---|
| 3173 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x00000001L |
|---|
| 3174 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x00000002L |
|---|
| 3175 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT |
|---|
| 3176 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 |
|---|
| 3177 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 |
|---|
| 3178 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa |
|---|
| 3179 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL |
|---|
| 3180 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L |
|---|
| 3181 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L |
|---|
| 3182 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB |
|---|
| 3183 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 |
|---|
| 3184 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 |
|---|
| 3185 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL |
|---|
| 3186 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L |
|---|
| 3187 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS |
|---|
| 3188 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 |
|---|
| 3189 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 |
|---|
| 3190 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 |
|---|
| 3191 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK 0x000000FFL |
|---|
| 3192 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK 0x0000FF00L |
|---|
| 3193 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L |
|---|
| 3194 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB |
|---|
| 3195 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 |
|---|
| 3196 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 |
|---|
| 3197 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3198 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3199 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB |
|---|
| 3200 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 |
|---|
| 3201 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 |
|---|
| 3202 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3203 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3204 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB |
|---|
| 3205 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 |
|---|
| 3206 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 |
|---|
| 3207 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3208 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3209 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB |
|---|
| 3210 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 |
|---|
| 3211 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 |
|---|
| 3212 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3213 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3214 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB |
|---|
| 3215 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 |
|---|
| 3216 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 |
|---|
| 3217 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3218 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3219 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB |
|---|
| 3220 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 |
|---|
| 3221 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 |
|---|
| 3222 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3223 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3224 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB |
|---|
| 3225 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 |
|---|
| 3226 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 |
|---|
| 3227 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3228 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3229 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB |
|---|
| 3230 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 |
|---|
| 3231 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 |
|---|
| 3232 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3233 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3234 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB |
|---|
| 3235 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 |
|---|
| 3236 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 |
|---|
| 3237 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3238 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3239 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB |
|---|
| 3240 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 |
|---|
| 3241 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 |
|---|
| 3242 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3243 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3244 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB |
|---|
| 3245 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 |
|---|
| 3246 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 |
|---|
| 3247 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3248 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3249 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB |
|---|
| 3250 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 |
|---|
| 3251 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 |
|---|
| 3252 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3253 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3254 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB |
|---|
| 3255 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 |
|---|
| 3256 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 |
|---|
| 3257 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3258 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3259 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB |
|---|
| 3260 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 |
|---|
| 3261 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 |
|---|
| 3262 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3263 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3264 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB |
|---|
| 3265 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 |
|---|
| 3266 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 |
|---|
| 3267 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3268 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3269 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB |
|---|
| 3270 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 |
|---|
| 3271 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 |
|---|
| 3272 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL |
|---|
| 3273 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L |
|---|
| 3274 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 |
|---|
| 3275 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 3276 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 3277 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 |
|---|
| 3278 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 3279 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 3280 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 |
|---|
| 3281 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 3282 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 3283 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 |
|---|
| 3284 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 3285 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 3286 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 |
|---|
| 3287 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 3288 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 3289 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 |
|---|
| 3290 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 3291 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 3292 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 |
|---|
| 3293 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 3294 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 3295 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 |
|---|
| 3296 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 3297 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 3298 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 |
|---|
| 3299 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 3300 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 3301 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 |
|---|
| 3302 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 |
|---|
| 3303 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 3304 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 |
|---|
| 3305 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 |
|---|
| 3306 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 3307 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 |
|---|
| 3308 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 |
|---|
| 3309 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 3310 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 |
|---|
| 3311 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 |
|---|
| 3312 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 3313 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 |
|---|
| 3314 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 |
|---|
| 3315 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 3316 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 |
|---|
| 3317 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 |
|---|
| 3318 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 3319 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 |
|---|
| 3320 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 |
|---|
| 3321 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 3322 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 |
|---|
| 3323 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 |
|---|
| 3324 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 3325 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 |
|---|
| 3326 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0 |
|---|
| 3327 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 3328 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 |
|---|
| 3329 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 |
|---|
| 3330 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL |
|---|
| 3331 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 |
|---|
| 3332 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 |
|---|
| 3333 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL |
|---|
| 3334 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 |
|---|
| 3335 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 |
|---|
| 3336 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL |
|---|
| 3337 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 |
|---|
| 3338 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 |
|---|
| 3339 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL |
|---|
| 3340 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 |
|---|
| 3341 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 |
|---|
| 3342 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL |
|---|
| 3343 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 |
|---|
| 3344 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 |
|---|
| 3345 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL |
|---|
| 3346 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 |
|---|
| 3347 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 |
|---|
| 3348 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL |
|---|
| 3349 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 |
|---|
| 3350 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 |
|---|
| 3351 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL |
|---|
| 3352 | //BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 |
|---|
| 3353 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0 |
|---|
| 3354 | #define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL |
|---|
| 3355 | |
|---|
| 3356 | |
|---|
| 3357 | // addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp |
|---|
| 3358 | //BIF_CFG_DEV0_EPF1_0_VENDOR_ID |
|---|
| 3359 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 |
|---|
| 3360 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL |
|---|
| 3361 | //BIF_CFG_DEV0_EPF1_0_DEVICE_ID |
|---|
| 3362 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
|---|
| 3363 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL |
|---|
| 3364 | //BIF_CFG_DEV0_EPF1_0_COMMAND |
|---|
| 3365 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 |
|---|
| 3366 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 |
|---|
| 3367 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 |
|---|
| 3368 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 |
|---|
| 3369 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 |
|---|
| 3370 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 |
|---|
| 3371 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 |
|---|
| 3372 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 |
|---|
| 3373 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 |
|---|
| 3374 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 |
|---|
| 3375 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa |
|---|
| 3376 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L |
|---|
| 3377 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L |
|---|
| 3378 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L |
|---|
| 3379 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L |
|---|
| 3380 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L |
|---|
| 3381 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L |
|---|
| 3382 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L |
|---|
| 3383 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L |
|---|
| 3384 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L |
|---|
| 3385 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L |
|---|
| 3386 | #define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L |
|---|
| 3387 | //BIF_CFG_DEV0_EPF1_0_STATUS |
|---|
| 3388 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 |
|---|
| 3389 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 |
|---|
| 3390 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT 0x5 |
|---|
| 3391 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 |
|---|
| 3392 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 |
|---|
| 3393 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 |
|---|
| 3394 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb |
|---|
| 3395 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc |
|---|
| 3396 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd |
|---|
| 3397 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe |
|---|
| 3398 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf |
|---|
| 3399 | #define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L |
|---|
| 3400 | #define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L |
|---|
| 3401 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK 0x0020L |
|---|
| 3402 | #define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L |
|---|
| 3403 | #define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L |
|---|
| 3404 | #define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L |
|---|
| 3405 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L |
|---|
| 3406 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L |
|---|
| 3407 | #define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L |
|---|
| 3408 | #define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L |
|---|
| 3409 | #define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L |
|---|
| 3410 | //BIF_CFG_DEV0_EPF1_0_REVISION_ID |
|---|
| 3411 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 |
|---|
| 3412 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 |
|---|
| 3413 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL |
|---|
| 3414 | #define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L |
|---|
| 3415 | //BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE |
|---|
| 3416 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 |
|---|
| 3417 | #define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL |
|---|
| 3418 | //BIF_CFG_DEV0_EPF1_0_SUB_CLASS |
|---|
| 3419 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 |
|---|
| 3420 | #define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL |
|---|
| 3421 | //BIF_CFG_DEV0_EPF1_0_BASE_CLASS |
|---|
| 3422 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 |
|---|
| 3423 | #define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL |
|---|
| 3424 | //BIF_CFG_DEV0_EPF1_0_CACHE_LINE |
|---|
| 3425 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 |
|---|
| 3426 | #define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL |
|---|
| 3427 | //BIF_CFG_DEV0_EPF1_0_LATENCY |
|---|
| 3428 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 |
|---|
| 3429 | #define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL |
|---|
| 3430 | //BIF_CFG_DEV0_EPF1_0_HEADER |
|---|
| 3431 | #define 0x0 |
|---|
| 3432 | #define 0x7 |
|---|
| 3433 | #define 0x7FL |
|---|
| 3434 | #define 0x80L |
|---|
| 3435 | //BIF_CFG_DEV0_EPF1_0_BIST |
|---|
| 3436 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 |
|---|
| 3437 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 |
|---|
| 3438 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 |
|---|
| 3439 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL |
|---|
| 3440 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L |
|---|
| 3441 | #define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L |
|---|
| 3442 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 |
|---|
| 3443 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 |
|---|
| 3444 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3445 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 |
|---|
| 3446 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 |
|---|
| 3447 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3448 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 |
|---|
| 3449 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 |
|---|
| 3450 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3451 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 |
|---|
| 3452 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 |
|---|
| 3453 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3454 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 |
|---|
| 3455 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 |
|---|
| 3456 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3457 | //BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 |
|---|
| 3458 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 |
|---|
| 3459 | #define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3460 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID |
|---|
| 3461 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 3462 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 3463 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 3464 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 3465 | //BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR |
|---|
| 3466 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
|---|
| 3467 | #define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
|---|
| 3468 | //BIF_CFG_DEV0_EPF1_0_CAP_PTR |
|---|
| 3469 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 |
|---|
| 3470 | #define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0x000000FFL |
|---|
| 3471 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE |
|---|
| 3472 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 |
|---|
| 3473 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL |
|---|
| 3474 | //BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN |
|---|
| 3475 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 |
|---|
| 3476 | #define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL |
|---|
| 3477 | //BIF_CFG_DEV0_EPF1_0_MIN_GRANT |
|---|
| 3478 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 |
|---|
| 3479 | #define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL |
|---|
| 3480 | //BIF_CFG_DEV0_EPF1_0_MAX_LATENCY |
|---|
| 3481 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 |
|---|
| 3482 | #define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL |
|---|
| 3483 | //BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST |
|---|
| 3484 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3485 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 3486 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 |
|---|
| 3487 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL |
|---|
| 3488 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L |
|---|
| 3489 | #define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L |
|---|
| 3490 | //BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W |
|---|
| 3491 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 |
|---|
| 3492 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 |
|---|
| 3493 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL |
|---|
| 3494 | #define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L |
|---|
| 3495 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST |
|---|
| 3496 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3497 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 3498 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 3499 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 3500 | //BIF_CFG_DEV0_EPF1_0_PMI_CAP |
|---|
| 3501 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 |
|---|
| 3502 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 |
|---|
| 3503 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 |
|---|
| 3504 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 |
|---|
| 3505 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 |
|---|
| 3506 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa |
|---|
| 3507 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb |
|---|
| 3508 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L |
|---|
| 3509 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L |
|---|
| 3510 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L |
|---|
| 3511 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L |
|---|
| 3512 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L |
|---|
| 3513 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L |
|---|
| 3514 | #define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L |
|---|
| 3515 | //BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL |
|---|
| 3516 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 |
|---|
| 3517 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 |
|---|
| 3518 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 |
|---|
| 3519 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 |
|---|
| 3520 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd |
|---|
| 3521 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf |
|---|
| 3522 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 |
|---|
| 3523 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 |
|---|
| 3524 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 |
|---|
| 3525 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L |
|---|
| 3526 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L |
|---|
| 3527 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L |
|---|
| 3528 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L |
|---|
| 3529 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L |
|---|
| 3530 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L |
|---|
| 3531 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L |
|---|
| 3532 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L |
|---|
| 3533 | #define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L |
|---|
| 3534 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST |
|---|
| 3535 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 |
|---|
| 3536 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 |
|---|
| 3537 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL |
|---|
| 3538 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L |
|---|
| 3539 | //BIF_CFG_DEV0_EPF1_0_PCIE_CAP |
|---|
| 3540 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 |
|---|
| 3541 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 |
|---|
| 3542 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 |
|---|
| 3543 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 |
|---|
| 3544 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL |
|---|
| 3545 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L |
|---|
| 3546 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L |
|---|
| 3547 | #define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L |
|---|
| 3548 | //BIF_CFG_DEV0_EPF1_0_DEVICE_CAP |
|---|
| 3549 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 |
|---|
| 3550 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 |
|---|
| 3551 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 |
|---|
| 3552 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 |
|---|
| 3553 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 |
|---|
| 3554 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf |
|---|
| 3555 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 |
|---|
| 3556 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a |
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| 3557 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c |
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| 3558 | #define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L |
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| 3559 | #define |
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