1/*
2 * OSS_2_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef OSS_2_0_SH_MASK_H
25#define OSS_2_0_SH_MASK_H
26
27#define IH_VMID_0_LUT__PASID_MASK 0xffff
28#define IH_VMID_0_LUT__PASID__SHIFT 0x0
29#define IH_VMID_1_LUT__PASID_MASK 0xffff
30#define IH_VMID_1_LUT__PASID__SHIFT 0x0
31#define IH_VMID_2_LUT__PASID_MASK 0xffff
32#define IH_VMID_2_LUT__PASID__SHIFT 0x0
33#define IH_VMID_3_LUT__PASID_MASK 0xffff
34#define IH_VMID_3_LUT__PASID__SHIFT 0x0
35#define IH_VMID_4_LUT__PASID_MASK 0xffff
36#define IH_VMID_4_LUT__PASID__SHIFT 0x0
37#define IH_VMID_5_LUT__PASID_MASK 0xffff
38#define IH_VMID_5_LUT__PASID__SHIFT 0x0
39#define IH_VMID_6_LUT__PASID_MASK 0xffff
40#define IH_VMID_6_LUT__PASID__SHIFT 0x0
41#define IH_VMID_7_LUT__PASID_MASK 0xffff
42#define IH_VMID_7_LUT__PASID__SHIFT 0x0
43#define IH_VMID_8_LUT__PASID_MASK 0xffff
44#define IH_VMID_8_LUT__PASID__SHIFT 0x0
45#define IH_VMID_9_LUT__PASID_MASK 0xffff
46#define IH_VMID_9_LUT__PASID__SHIFT 0x0
47#define IH_VMID_10_LUT__PASID_MASK 0xffff
48#define IH_VMID_10_LUT__PASID__SHIFT 0x0
49#define IH_VMID_11_LUT__PASID_MASK 0xffff
50#define IH_VMID_11_LUT__PASID__SHIFT 0x0
51#define IH_VMID_12_LUT__PASID_MASK 0xffff
52#define IH_VMID_12_LUT__PASID__SHIFT 0x0
53#define IH_VMID_13_LUT__PASID_MASK 0xffff
54#define IH_VMID_13_LUT__PASID__SHIFT 0x0
55#define IH_VMID_14_LUT__PASID_MASK 0xffff
56#define IH_VMID_14_LUT__PASID__SHIFT 0x0
57#define IH_VMID_15_LUT__PASID_MASK 0xffff
58#define IH_VMID_15_LUT__PASID__SHIFT 0x0
59#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
60#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
61#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
62#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
63#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
64#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
65#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
66#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
67#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
68#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
69#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
70#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
71#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
72#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
73#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
74#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
75#define IH_RB_BASE__ADDR_MASK 0xffffffff
76#define IH_RB_BASE__ADDR__SHIFT 0x0
77#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
78#define IH_RB_RPTR__OFFSET__SHIFT 0x2
79#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
80#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
81#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
82#define IH_RB_WPTR__OFFSET__SHIFT 0x2
83#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
84#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
85#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
86#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
87#define IH_CNTL__ENABLE_INTR_MASK 0x1
88#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
89#define IH_CNTL__MC_SWAP_MASK 0x6
90#define IH_CNTL__MC_SWAP__SHIFT 0x1
91#define IH_CNTL__MC_TRAN_MASK 0x8
92#define IH_CNTL__MC_TRAN__SHIFT 0x3
93#define IH_CNTL__RPTR_REARM_MASK 0x10
94#define IH_CNTL__RPTR_REARM__SHIFT 0x4
95#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
96#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
97#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
98#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
99#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
100#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
101#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
102#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
103#define IH_CNTL__MC_VMID_MASK 0x1e000000
104#define IH_CNTL__MC_VMID__SHIFT 0x19
105#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
106#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
107#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
108#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
109#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
110#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
111#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
112#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
113#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
114#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
115#define IH_STATUS__IDLE_MASK 0x1
116#define IH_STATUS__IDLE__SHIFT 0x0
117#define IH_STATUS__INPUT_IDLE_MASK 0x2
118#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
119#define IH_STATUS__RB_IDLE_MASK 0x4
120#define IH_STATUS__RB_IDLE__SHIFT 0x2
121#define IH_STATUS__RB_FULL_MASK 0x8
122#define IH_STATUS__RB_FULL__SHIFT 0x3
123#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
124#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
125#define IH_STATUS__RB_OVERFLOW_MASK 0x20
126#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
127#define IH_STATUS__MC_WR_IDLE_MASK 0x40
128#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
129#define IH_STATUS__MC_WR_STALL_MASK 0x80
130#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
131#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
132#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
133#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
134#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
135#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
136#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
137#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
138#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
139#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
140#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
141#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
142#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
143#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
144#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
145#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
146#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
147#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
148#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
149#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
150#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
151#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
152#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
153#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x7
154#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x0
155#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x8
156#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x3
157#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x10
158#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x4
159#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0xff00
160#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x8
161#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000
162#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x10
163#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
164#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
165#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
166#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
167#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
168#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
169#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
170#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
171#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
172#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
173#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
174#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
175#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
176#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
177#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
178#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
179#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
180#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
181#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
182#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
183#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
184#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
185#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
186#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
187#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
188#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
189#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
190#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
191#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
192#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
193#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
194#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
195#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
196#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
197#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
198#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
199#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
200#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
201#define SEM_STATUS__SEM_IDLE_MASK 0x1
202#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
203#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
204#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
205#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
206#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
207#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
208#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
209#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
210#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
211#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
212#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
213#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
214#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
215#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
216#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
217#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
218#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
219#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
220#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
221#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
222#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
223#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
224#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
225#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
226#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
227#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
228#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
229#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
230#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
231#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
232#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
233#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
234#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
235#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
236#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
237#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
238#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
239#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
240#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
241#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
242#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
243#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
244#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
245#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
246#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
247#define SEM_MAILBOX__SIDEPORT_MASK 0xff
248#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
249#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
250#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
251#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
252#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
253#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
254#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
255#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
256#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
257#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
258#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
259#define SRBM_CNTL__READ_TIMEOUT_MASK 0x1fff
260#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
261#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
262#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
263#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
264#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
265#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
266#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
267#define SRBM_GFX_CNTL__MEID_MASK 0xc
268#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
269#define SRBM_GFX_CNTL__VMID_MASK 0xf0
270#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
271#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
272#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
273#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
274#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
275#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
276#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
277#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
278#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
279#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x8
280#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x3
281#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
282#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
283#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
284#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
285#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
286#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
287#define SRBM_STATUS2__VCE_BUSY_MASK 0x80
288#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x7
289#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
290#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
291#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
292#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
293#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
294#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
295#define SRBM_STATUS__SAM_RQ_PENDING_MASK 0x4
296#define SRBM_STATUS__SAM_RQ_PENDING__SHIFT 0x2
297#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
298#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
299#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
300#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
301#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
302#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
303#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
304#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
305#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x80
306#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x7
307#define SRBM_STATUS__VMC_BUSY_MASK 0x100
308#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
309#define SRBM_STATUS__MCB_BUSY_MASK 0x200
310#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
311#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
312#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
313#define SRBM_STATUS__MCC_BUSY_MASK 0x800
314#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
315#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
316#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
317#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
318#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
319#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
320#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
321#define SRBM_STATUS__IH_BUSY_MASK 0x20000
322#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
323#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
324#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
325#define SRBM_STATUS__SAM_BUSY_MASK 0x100000
326#define SRBM_STATUS__SAM_BUSY__SHIFT 0x14
327#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
328#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
329#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
330#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
331#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
332#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
333#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
334#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
335#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
336#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
337#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
338#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
339#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
340#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
341#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
342#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
343#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
344#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
345#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
346#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
347#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
348#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
349#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
350#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
351#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
352#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
353#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
354#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
355#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
356#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
357#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
358#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
359#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
360#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
361#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
362#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
363#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
364#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
365#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
366#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
367#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
368#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
369#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
370#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
371#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
372#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
373#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x1000000
374#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x18
375#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
376#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
377#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
378#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
379#define SRBM_SOFT_RESET__SOFT_RESET_SAM_MASK 0x8000000
380#define SRBM_SOFT_RESET__SOFT_RESET_SAM__SHIFT 0x1b
381#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
382#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
383#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
384#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
385#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
386#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
387#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
388#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
389#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
390#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
391#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
392#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
393#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
394#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
395#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
396#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
397#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
398#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
399#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
400#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
401#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
402#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
403#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
404#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
405#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
406#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
407#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
408#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
409#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
410#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
411#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
412#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
413#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
414#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
415#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
416#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
417#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
418#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
419#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
420#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
421#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
422#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
423#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
424#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
425#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
426#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
427#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
428#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
429#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
430#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
431#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
432#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
433#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
434#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
435#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
436#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
437#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
438#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
439#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
440#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
441#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
442#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
443#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
444#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
445#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
446#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
447#define SRBM_DEBUG_SNAPSHOT__SAM_RDY_MASK 0x8
448#define SRBM_DEBUG_SNAPSHOT__SAM_RDY__SHIFT 0x3
449#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
450#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
451#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
452#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
453#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
454#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
455#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
456#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
457#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
458#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
459#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
460#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
461#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
462#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
463#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
464#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
465#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
466#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
467#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
468#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
469#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
470#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
471#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
472#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
473#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
474#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
475#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
476#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
477#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
478#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
479#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
480#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
481#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
482#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
483#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
484#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
485#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
486#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
487#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
488#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
489#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
490#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
491#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
492#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
493#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
494#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
495#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
496#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
497#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
498#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
499#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000
500#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x1d
501#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
502#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
503#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x100000
504#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x14
505#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
506#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
507#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
508#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
509#define SRBM_READ_ERROR__READ_REQUESTER_SAM_MASK 0x800000
510#define SRBM_READ_ERROR__READ_REQUESTER_SAM__SHIFT 0x17
511#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
512#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
513#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
514#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
515#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
516#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
517#define SRBM_READ_ERROR__READ_REQUESTER_ACP_MASK 0x8000000
518#define SRBM_READ_ERROR__READ_REQUESTER_ACP__SHIFT 0x1b
519#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
520#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
521#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
522#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
523#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
524#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
525#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
526#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
527#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
528#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
529#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
530#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
531#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
532#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
533#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
534#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
535#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
536#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
537#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
538#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
539#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
540#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
541#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
542#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
543#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
544#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
545#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
546#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
547#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
548#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
549#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0xffff0
550#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x4
551#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
552#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
553#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
554#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
555#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
556#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
557#define DH_TEST__DH_TEST_MASK 0x1
558#define DH_TEST__DH_TEST__SHIFT 0x0
559#define KHFS0__RESERVED_MASK 0xffffffff
560#define KHFS0__RESERVED__SHIFT 0x0
561#define KHFS1__RESERVED_MASK 0xffffffff
562#define KHFS1__RESERVED__SHIFT 0x0
563#define KHFS2__RESERVED_MASK 0xffffffff
564#define KHFS2__RESERVED__SHIFT 0x0
565#define KHFS3__RESERVED_MASK 0xffffffff
566#define KHFS3__RESERVED__SHIFT 0x0
567#define KSESSION0__RESERVED_MASK 0xffffffff
568#define KSESSION0__RESERVED__SHIFT 0x0
569#define KSESSION1__RESERVED_MASK 0xffffffff
570#define KSESSION1__RESERVED__SHIFT 0x0
571#define KSESSION2__RESERVED_MASK 0xffffffff
572#define KSESSION2__RESERVED__SHIFT 0x0
573#define KSESSION3__RESERVED_MASK 0xffffffff
574#define KSESSION3__RESERVED__SHIFT 0x0
575#define KSIG0__RESERVED_MASK 0xffffffff
576#define KSIG0__RESERVED__SHIFT 0x0
577#define KSIG1__RESERVED_MASK 0xffffffff
578#define KSIG1__RESERVED__SHIFT 0x0
579#define KSIG2__RESERVED_MASK 0xffffffff
580#define KSIG2__RESERVED__SHIFT 0x0
581#define KSIG3__RESERVED_MASK 0xffffffff
582#define KSIG3__RESERVED__SHIFT 0x0
583#define EXP0__RESERVED_MASK 0xffffffff
584#define EXP0__RESERVED__SHIFT 0x0
585#define EXP1__RESERVED_MASK 0xffffffff
586#define EXP1__RESERVED__SHIFT 0x0
587#define EXP2__RESERVED_MASK 0xffffffff
588#define EXP2__RESERVED__SHIFT 0x0
589#define EXP3__RESERVED_MASK 0xffffffff
590#define EXP3__RESERVED__SHIFT 0x0
591#define EXP4__RESERVED_MASK 0xffffffff
592#define EXP4__RESERVED__SHIFT 0x0
593#define EXP5__RESERVED_MASK 0xffffffff
594#define EXP5__RESERVED__SHIFT 0x0
595#define EXP6__RESERVED_MASK 0xffffffff
596#define EXP6__RESERVED__SHIFT 0x0
597#define EXP7__RESERVED_MASK 0xffffffff
598#define EXP7__RESERVED__SHIFT 0x0
599#define LX0__RESERVED_MASK 0xffffffff
600#define LX0__RESERVED__SHIFT 0x0
601#define LX1__RESERVED_MASK 0xffffffff
602#define LX1__RESERVED__SHIFT 0x0
603#define LX2__RESERVED_MASK 0xffffffff
604#define LX2__RESERVED__SHIFT 0x0
605#define LX3__RESERVED_MASK 0xffffffff
606#define LX3__RESERVED__SHIFT 0x0
607#define CLIENT2_K0__RESERVED_MASK 0xffffffff
608#define CLIENT2_K0__RESERVED__SHIFT 0x0
609#define CLIENT2_K1__RESERVED_MASK 0xffffffff
610#define CLIENT2_K1__RESERVED__SHIFT 0x0
611#define CLIENT2_K2__RESERVED_MASK 0xffffffff
612#define CLIENT2_K2__RESERVED__SHIFT 0x0
613#define CLIENT2_K3__RESERVED_MASK 0xffffffff
614#define CLIENT2_K3__RESERVED__SHIFT 0x0
615#define CLIENT2_CK0__RESERVED_MASK 0xffffffff
616#define CLIENT2_CK0__RESERVED__SHIFT 0x0
617#define CLIENT2_CK1__RESERVED_MASK 0xffffffff
618#define CLIENT2_CK1__RESERVED__SHIFT 0x0
619#define CLIENT2_CK2__RESERVED_MASK 0xffffffff
620#define CLIENT2_CK2__RESERVED__SHIFT 0x0
621#define CLIENT2_CK3__RESERVED_MASK 0xffffffff
622#define CLIENT2_CK3__RESERVED__SHIFT 0x0
623#define CLIENT2_CD0__RESERVED_MASK 0xffffffff
624#define CLIENT2_CD0__RESERVED__SHIFT 0x0
625#define CLIENT2_CD1__RESERVED_MASK 0xffffffff
626#define CLIENT2_CD1__RESERVED__SHIFT 0x0
627#define CLIENT2_CD2__RESERVED_MASK 0xffffffff
628#define CLIENT2_CD2__RESERVED__SHIFT 0x0
629#define CLIENT2_CD3__RESERVED_MASK 0xffffffff
630#define CLIENT2_CD3__RESERVED__SHIFT 0x0
631#define CLIENT2_BM__RESERVED_MASK 0xffffffff
632#define CLIENT2_BM__RESERVED__SHIFT 0x0
633#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffff
634#define CLIENT2_OFFSET__RESERVED__SHIFT 0x0
635#define CLIENT2_STATUS__RESERVED_MASK 0xffffffff
636#define CLIENT2_STATUS__RESERVED__SHIFT 0x0
637#define CLIENT0_K0__RESERVED_MASK 0xffffffff
638#define CLIENT0_K0__RESERVED__SHIFT 0x0
639#define CLIENT0_K1__RESERVED_MASK 0xffffffff
640#define CLIENT0_K1__RESERVED__SHIFT 0x0
641#define CLIENT0_K2__RESERVED_MASK 0xffffffff
642#define CLIENT0_K2__RESERVED__SHIFT 0x0
643#define CLIENT0_K3__RESERVED_MASK 0xffffffff
644#define CLIENT0_K3__RESERVED__SHIFT 0x0
645#define CLIENT0_CK0__RESERVED_MASK 0xffffffff
646#define CLIENT0_CK0__RESERVED__SHIFT 0x0
647#define CLIENT0_CK1__RESERVED_MASK 0xffffffff
648#define CLIENT0_CK1__RESERVED__SHIFT 0x0
649#define CLIENT0_CK2__RESERVED_MASK 0xffffffff
650#define CLIENT0_CK2__RESERVED__SHIFT 0x0
651#define CLIENT0_CK3__RESERVED_MASK 0xffffffff
652#define CLIENT0_CK3__RESERVED__SHIFT 0x0
653#define CLIENT0_CD0__RESERVED_MASK 0xffffffff
654#define CLIENT0_CD0__RESERVED__SHIFT 0x0
655#define CLIENT0_CD1__RESERVED_MASK 0xffffffff
656#define CLIENT0_CD1__RESERVED__SHIFT 0x0
657#define CLIENT0_CD2__RESERVED_MASK 0xffffffff
658#define CLIENT0_CD2__RESERVED__SHIFT 0x0
659#define CLIENT0_CD3__RESERVED_MASK 0xffffffff
660#define CLIENT0_CD3__RESERVED__SHIFT 0x0
661#define CLIENT0_BM__RESERVED_MASK 0xffffffff
662#define CLIENT0_BM__RESERVED__SHIFT 0x0
663#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffff
664#define CLIENT0_OFFSET__RESERVED__SHIFT 0x0
665#define CLIENT0_STATUS__RESERVED_MASK 0xffffffff
666#define CLIENT0_STATUS__RESERVED__SHIFT 0x0
667#define CLIENT1_K0__RESERVED_MASK 0xffffffff
668#define CLIENT1_K0__RESERVED__SHIFT 0x0
669#define CLIENT1_K1__RESERVED_MASK 0xffffffff
670#define CLIENT1_K1__RESERVED__SHIFT 0x0
671#define CLIENT1_K2__RESERVED_MASK 0xffffffff
672#define CLIENT1_K2__RESERVED__SHIFT 0x0
673#define CLIENT1_K3__RESERVED_MASK 0xffffffff
674#define CLIENT1_K3__RESERVED__SHIFT 0x0
675#define CLIENT1_CK0__RESERVED_MASK 0xffffffff
676#define CLIENT1_CK0__RESERVED__SHIFT 0x0
677#define CLIENT1_CK1__RESERVED_MASK 0xffffffff
678#define CLIENT1_CK1__RESERVED__SHIFT 0x0
679#define CLIENT1_CK2__RESERVED_MASK 0xffffffff
680#define CLIENT1_CK2__RESERVED__SHIFT 0x0
681#define CLIENT1_CK3__RESERVED_MASK 0xffffffff
682#define CLIENT1_CK3__RESERVED__SHIFT 0x0
683#define CLIENT1_CD0__RESERVED_MASK 0xffffffff
684#define CLIENT1_CD0__RESERVED__SHIFT 0x0
685#define CLIENT1_CD1__RESERVED_MASK 0xffffffff
686#define CLIENT1_CD1__RESERVED__SHIFT 0x0
687#define CLIENT1_CD2__RESERVED_MASK 0xffffffff
688#define CLIENT1_CD2__RESERVED__SHIFT 0x0
689#define CLIENT1_CD3__RESERVED_MASK 0xffffffff
690#define CLIENT1_CD3__RESERVED__SHIFT 0x0
691#define CLIENT1_BM__RESERVED_MASK 0xffffffff
692#define CLIENT1_BM__RESERVED__SHIFT 0x0
693#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffff
694#define CLIENT1_OFFSET__RESERVED__SHIFT 0x0
695#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffff
696#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x0
697#define KEFUSE0__RESERVED_MASK 0xffffffff
698#define KEFUSE0__RESERVED__SHIFT 0x0
699#define KEFUSE1__RESERVED_MASK 0xffffffff
700#define KEFUSE1__RESERVED__SHIFT 0x0
701#define KEFUSE2__RESERVED_MASK 0xffffffff
702#define KEFUSE2__RESERVED__SHIFT 0x0
703#define KEFUSE3__RESERVED_MASK 0xffffffff
704#define KEFUSE3__RESERVED__SHIFT 0x0
705#define HFS_SEED0__RESERVED_MASK 0xffffffff
706#define HFS_SEED0__RESERVED__SHIFT 0x0
707#define HFS_SEED1__RESERVED_MASK 0xffffffff
708#define HFS_SEED1__RESERVED__SHIFT 0x0
709#define HFS_SEED2__RESERVED_MASK 0xffffffff
710#define HFS_SEED2__RESERVED__SHIFT 0x0
711#define HFS_SEED3__RESERVED_MASK 0xffffffff
712#define HFS_SEED3__RESERVED__SHIFT 0x0
713#define RINGOSC_MASK__MASK_MASK 0xffff
714#define RINGOSC_MASK__MASK__SHIFT 0x0
715#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffff
716#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x0
717#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffff
718#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x0
719#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffff
720#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x0
721#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffff
722#define SPU_PORT_STATUS__RESERVED__SHIFT 0x0
723#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffff
724#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x0
725#define CLIENT3_K0__RESERVED_MASK 0xffffffff
726#define CLIENT3_K0__RESERVED__SHIFT 0x0
727#define CLIENT3_K1__RESERVED_MASK 0xffffffff
728#define CLIENT3_K1__RESERVED__SHIFT 0x0
729#define CLIENT3_K2__RESERVED_MASK 0xffffffff
730#define CLIENT3_K2__RESERVED__SHIFT 0x0
731#define CLIENT3_K3__RESERVED_MASK 0xffffffff
732#define CLIENT3_K3__RESERVED__SHIFT 0x0
733#define CLIENT3_CK0__RESERVED_MASK 0xffffffff
734#define CLIENT3_CK0__RESERVED__SHIFT 0x0
735#define CLIENT3_CK1__RESERVED_MASK 0xffffffff
736#define CLIENT3_CK1__RESERVED__SHIFT 0x0
737#define CLIENT3_CK2__RESERVED_MASK 0xffffffff
738#define CLIENT3_CK2__RESERVED__SHIFT 0x0
739#define CLIENT3_CK3__RESERVED_MASK 0xffffffff
740#define CLIENT3_CK3__RESERVED__SHIFT 0x0
741#define CLIENT3_CD0__RESERVED_MASK 0xffffffff
742#define CLIENT3_CD0__RESERVED__SHIFT 0x0
743#define CLIENT3_CD1__RESERVED_MASK 0xffffffff
744#define CLIENT3_CD1__RESERVED__SHIFT 0x0
745#define CLIENT3_CD2__RESERVED_MASK 0xffffffff
746#define CLIENT3_CD2__RESERVED__SHIFT 0x0
747#define CLIENT3_CD3__RESERVED_MASK 0xffffffff
748#define CLIENT3_CD3__RESERVED__SHIFT 0x0
749#define CLIENT3_BM__RESERVED_MASK 0xffffffff
750#define CLIENT3_BM__RESERVED__SHIFT 0x0
751#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffff
752#define CLIENT3_OFFSET__RESERVED__SHIFT 0x0
753#define CLIENT3_STATUS__RESERVED_MASK 0xffffffff
754#define CLIENT3_STATUS__RESERVED__SHIFT 0x0
755#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0xff
756#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x0
757#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x100
758#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x8
759#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffff
760#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x0
761#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES_MASK 0x1
762#define XDMA_SLV_CNTL__XDMA_SLV_READ_LINES__SHIFT 0x0
763#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x200
764#define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x9
765#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x400
766#define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0xa
767#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION_MASK 0x3000
768#define XDMA_SLV_CNTL__XDMA_SLV_ALPHA_POSITION__SHIFT 0xc
769#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x10000
770#define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x10
771#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x80000
772#define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x13
773#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x100000
774#define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x14
775#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT_MASK 0x1000000
776#define XDMA_SLV_CNTL__XDMA_SLV_REQ_MAXED_OUT__SHIFT 0x18
777#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x300
778#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x8
779#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0xf000
780#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0xc
781#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x10000
782#define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x10
783#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x3fff
784#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x0
785#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000
786#define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x10
787#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x1
788#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x0
789#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0xf0
790#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x4
791#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0xf00
792#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x8
793#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0xf000
794#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0xc
795#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000
796#define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x10
797#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x1
798#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x0
799#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0xf00
800#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x8
801#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0xf000
802#define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0xc
803#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x1ff
804#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x0
805#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000
806#define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x10
807#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0xffff
808#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x0
809#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000
810#define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x10
811#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0xfffff
812#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x0
813#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000
814#define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x14
815#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x3ff
816#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x0
817#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x3000
818#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0xc
819#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x10000
820#define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x10
821#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0xffff
822#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x0
823#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x30000
824#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x10
825#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000
826#define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x1f
827#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES_MASK 0x3ff
828#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_FREE_ENTRIES__SHIFT 0x0
829#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE_MASK 0x3ff000
830#define XDMA_SLV_RDRET_BUF_STATUS__XDMA_SLV_RDRET_BUF_SIZE__SHIFT 0xc
831#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0xffff
832#define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x0
833#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x1
834#define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x0
835#define SDMA0_UCODE_ADDR__VALUE_MASK 0x7ff
836#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
837#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
838#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
839#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
840#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
841#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
842#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
843#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
844#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
845#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
846#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
847#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
848#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
849#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
850#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
851#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
852#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
853#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
854#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
855#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
856#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
857#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
858#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
859#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
860#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
861#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
862#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
863#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
864#define SDMA0_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
865#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
866#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
867#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
868#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
869#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
870#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
871#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
872#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
873#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
874#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
875#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
876#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
877#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
878#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
879#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
880#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
881#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
882#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
883#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
884#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
885#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
886#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
887#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
888#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
889#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
890#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
891#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
892#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
893#define SDMA0_HASH__BANK_BITS_MASK 0x70
894#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
895#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
896#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
897#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
898#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
899#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
900#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
901#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
902#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
903#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
904#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
905#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
906#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
907#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
908#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
909#define SDMA0_STATUS_REG__IDLE_MASK 0x1
910#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
911#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
912#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
913#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
914#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
915#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
916#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
917#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
918#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
919#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
920#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
921#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
922#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
923#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
924#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
925#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
926#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
927#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
928#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
929#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
930#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
931#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
932#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
933#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
934#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
935#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
936#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
937#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
938#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
939#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
940#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
941#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
942#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
943#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
944#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
945#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
946#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
947#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
948#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
949#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
950#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
951#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
952#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
953#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
954#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
955#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
956#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
957#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
958#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
959#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
960#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
961#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
962#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
963#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
964#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
965#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
966#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
967#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
968#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
969#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
970#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
971#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
972#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
973#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
974#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
975#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
976#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
977#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
978#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
979#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
980#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
981#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
982#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
983#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
984#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
985#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
986#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
987#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
988#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
989#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
990#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
991#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
992#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
993#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
994#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
995#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
996#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
997#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
998#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
999#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
1000#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
1001#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
1002#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
1003#define SDMA0_F32_CNTL__HALT_MASK 0x1
1004#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
1005#define SDMA0_F32_CNTL__STEP_MASK 0x2
1006#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
1007#define SDMA0_FREEZE__FREEZE_MASK 0x10
1008#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
1009#define SDMA0_FREEZE__FROZEN_MASK 0x20
1010#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
1011#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
1012#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
1013#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
1014#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
1015#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
1016#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
1017#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
1018#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
1019#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
1020#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
1021#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
1022#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
1023#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
1024#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
1025#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1026#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
1027#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
1028#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1029#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
1030#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
1031#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
1032#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
1033#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
1034#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
1035#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
1036#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
1037#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
1038#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
1039#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
1040#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
1041#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
1042#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
1043#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
1044#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
1045#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
1046#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
1047#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
1048#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
1049#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
1050#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
1051#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
1052#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
1053#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
1054#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
1055#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
1056#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
1057#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
1058#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
1059#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
1060#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
1061#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1062#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1063#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
1064#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1065#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1066#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
1067#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
1068#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1069#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1070#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1071#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1072#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1073#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1074#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1075#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1076#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1077#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
1078#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
1079#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
1080#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
1081#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
1082#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
1083#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
1084#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
1085#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
1086#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1087#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
1088#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1089#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1090#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1091#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1092#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1093#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1094#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1095#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1096#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1097#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1098#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1099#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1100#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1101#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1102#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1103#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1104#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1105#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1106#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
1107#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1108#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1109#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1110#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1111#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
1112#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
1113#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
1114#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1115#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
1116#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1117#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
1118#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
1119#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
1120#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
1121#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
1122#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
1123#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1124#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1125#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1126#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1127#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
1128#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1129#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
1130#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1131#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1132#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1133#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1134#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1135#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1136#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1137#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
1138#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
1139#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
1140#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
1141#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1142#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
1143#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
1144#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1145#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1146#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1147#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1148#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1149#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
1150#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
1151#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
1152#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
1153#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1154#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1155#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1156#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1157#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
1158#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1159#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
1160#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1161#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1162#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1163#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1164#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1165#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1166#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1167#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1168#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1169#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
1170#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
1171#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
1172#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
1173#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
1174#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
1175#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
1176#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
1177#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
1178#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1179#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
1180#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1181#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1182#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1183#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1184#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1185#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1186#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1187#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1188#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1189#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1190#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1191#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1192#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1193#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1194#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1195#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1196#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1197#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
1198#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1199#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1200#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1201#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1202#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1203#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
1204#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
1205#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
1206#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1207#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
1208#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1209#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
1210#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
1211#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
1212#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
1213#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
1214#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
1215#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1216#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1217#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
1218#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1219#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
1220#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1221#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
1222#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1223#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1224#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1225#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1226#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1227#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1228#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1229#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
1230#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
1231#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
1232#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
1233#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
1234#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
1235#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
1236#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
1237#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
1238#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1239#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1240#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1241#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1242#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1243#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
1244#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
1245#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
1246#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
1247#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
1248#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1249#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
1250#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1251#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1252#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1253#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1254#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1255#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
1256#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1257#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
1258#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1259#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1260#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1261#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1262#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1263#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1264#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1265#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1266#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1267#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
1268#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
1269#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
1270#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
1271#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
1272#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
1273#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
1274#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
1275#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
1276#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1277#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
1278#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1279#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1280#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1281#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1282#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1283#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1284#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1285#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1286#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1287#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1288#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1289#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1290#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1291#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1292#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1293#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1294#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1295#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
1296#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1297#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1298#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1299#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1300#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1301#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
1302#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
1303#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
1304#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1305#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
1306#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1307#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
1308#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
1309#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
1310#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
1311#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
1312#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
1313#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1314#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1315#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
1316#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1317#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
1318#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1319#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
1320#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1321#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1322#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1323#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1324#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1325#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1326#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1327#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
1328#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
1329#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
1330#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
1331#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
1332#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
1333#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
1334#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
1335#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
1336#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1337#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1338#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1339#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1340#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1341#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
1342#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
1343#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
1344#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
1345#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
1346#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1347#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
1348#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1349#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1350#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1351#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1352#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1353#define SDMA1_UCODE_ADDR__VALUE_MASK 0x7ff
1354#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
1355#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
1356#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
1357#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
1358#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
1359#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
1360#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
1361#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1362#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1363#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
1364#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1365#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
1366#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1367#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
1368#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1369#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
1370#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1371#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
1372#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1373#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
1374#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1375#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
1376#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1377#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
1378#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1379#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
1380#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
1381#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE_MASK 0x2
1382#define SDMA1_CNTL__SEM_INCOMPLETE_INT_ENABLE__SHIFT 0x1
1383#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
1384#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1385#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
1386#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
1387#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
1388#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
1389#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
1390#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
1391#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
1392#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
1393#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
1394#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
1395#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
1396#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
1397#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
1398#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
1399#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
1400#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
1401#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
1402#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
1403#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
1404#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
1405#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
1406#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
1407#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1408#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1409#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
1410#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
1411#define SDMA1_HASH__BANK_BITS_MASK 0x70
1412#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
1413#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
1414#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
1415#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
1416#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
1417#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER_MASK 0xffff
1418#define SDMA1_SEM_INCOMPLETE_TIMER_CNTL__TIMER__SHIFT 0x0
1419#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
1420#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
1421#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
1422#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1423#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
1424#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1425#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
1426#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
1427#define SDMA1_STATUS_REG__IDLE_MASK 0x1
1428#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
1429#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
1430#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
1431#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
1432#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
1433#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
1434#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
1435#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
1436#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
1437#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
1438#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
1439#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
1440#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
1441#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
1442#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
1443#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
1444#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
1445#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
1446#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
1447#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
1448#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
1449#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
1450#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
1451#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
1452#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
1453#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
1454#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
1455#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
1456#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
1457#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
1458#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
1459#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
1460#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
1461#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
1462#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
1463#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
1464#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
1465#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
1466#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
1467#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
1468#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
1469#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
1470#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
1471#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
1472#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
1473#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
1474#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
1475#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
1476#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
1477#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
1478#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
1479#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
1480#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
1481#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
1482#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
1483#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1484#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
1485#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
1486#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1487#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
1488#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
1489#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
1490#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
1491#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
1492#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
1493#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
1494#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
1495#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
1496#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
1497#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
1498#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
1499#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
1500#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
1501#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
1502#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
1503#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
1504#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
1505#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
1506#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
1507#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1508#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
1509#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
1510#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1511#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
1512#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
1513#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
1514#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
1515#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
1516#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
1517#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
1518#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
1519#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
1520#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
1521#define SDMA1_F32_CNTL__HALT_MASK 0x1
1522#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
1523#define SDMA1_F32_CNTL__STEP_MASK 0x2
1524#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
1525#define SDMA1_FREEZE__FREEZE_MASK 0x10
1526#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
1527#define SDMA1_FREEZE__FROZEN_MASK 0x20
1528#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
1529#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
1530#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
1531#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
1532#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
1533#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
1534#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
1535#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
1536#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
1537#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
1538#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
1539#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
1540#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
1541#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
1542#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1543#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
1544#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1545#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1546#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
1547#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
1548#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1549#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1550#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1551#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1552#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1553#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1554#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1555#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1556#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1557#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
1558#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
1559#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
1560#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
1561#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
1562#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
1563#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
1564#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
1565#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
1566#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1567#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
1568#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1569#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1570#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1571#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1572#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1573#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1574#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1575#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1576#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1577#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1578#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1579#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1580#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1581#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1582#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1583#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1584#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1585#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1586#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
1587#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1588#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1589#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1590#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1591#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
1592#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
1593#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
1594#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1595#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
1596#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1597#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
1598#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
1599#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
1600#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
1601#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
1602#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
1603#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1604#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1605#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1606#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1607#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
1608#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1609#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
1610#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1611#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1612#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1613#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1614#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1615#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1616#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1617#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
1618#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
1619#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
1620#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
1621#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1622#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
1623#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
1624#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1625#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1626#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1627#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1628#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1629#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
1630#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
1631#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
1632#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
1633#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1634#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1635#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1636#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1637#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
1638#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1639#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
1640#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1641#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1642#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1643#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1644#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1645#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1646#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1647#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1648#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1649#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
1650#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
1651#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
1652#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
1653#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
1654#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
1655#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
1656#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
1657#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
1658#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1659#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
1660#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1661#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1662#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1663#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1664#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1665#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1666#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1667#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1668#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1669#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1670#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1671#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1672#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1673#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1674#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1675#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1676#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1677#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
1678#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1679#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1680#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1681#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1682#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1683#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
1684#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
1685#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
1686#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1687#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
1688#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1689#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
1690#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
1691#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
1692#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
1693#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
1694#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
1695#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1696#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1697#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
1698#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1699#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
1700#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1701#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
1702#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1703#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1704#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1705#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1706#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1707#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1708#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1709#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
1710#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
1711#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
1712#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
1713#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
1714#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
1715#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
1716#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
1717#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
1718#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1719#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1720#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1721#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1722#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1723#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
1724#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
1725#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
1726#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
1727#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
1728#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1729#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
1730#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1731#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1732#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1733#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1734#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1735#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
1736#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1737#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
1738#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1739#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1740#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1741#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1742#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1743#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1744#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1745#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1746#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1747#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
1748#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
1749#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
1750#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
1751#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
1752#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
1753#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
1754#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
1755#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
1756#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1757#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
1758#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1759#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1760#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1761#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1762#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1763#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1764#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1765#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1766#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1767#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1768#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1769#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1770#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1771#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1772#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1773#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1774#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1775#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
1776#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1777#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1778#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1779#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1780#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1781#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
1782#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
1783#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
1784#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1785#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
1786#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1787#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
1788#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
1789#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
1790#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
1791#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
1792#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
1793#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1794#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1795#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
1796#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1797#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
1798#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1799#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
1800#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1801#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1802#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1803#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1804#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1805#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1806#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1807#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
1808#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
1809#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
1810#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
1811#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
1812#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
1813#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
1814#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
1815#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
1816#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1817#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1818#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1819#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1820#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1821#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
1822#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
1823#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
1824#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
1825#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
1826#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1827#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
1828#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1829#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1830#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1831#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1832#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1833#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT_MASK 0x1ff
1834#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_WEIGHT__SHIFT 0x0
1835#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER_MASK 0x10000
1836#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_STOP_TRANSFER__SHIFT 0x10
1837#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET_MASK 0x20000
1838#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_SOFT_RESET__SHIFT 0x11
1839#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE_MASK 0x1000000
1840#define XDMA_SLV_CHANNEL_CNTL__XDMA_SLV_CHANNEL_ACTIVE__SHIFT 0x18
1841#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffff
1842#define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x0
1843#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
1844#define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
1845#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES_MASK 0xff
1846#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_LINES__SHIFT 0x0
1847#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST_MASK 0x100
1848#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_READ_REQUEST__SHIFT 0x8
1849#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE_MASK 0x200
1850#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FRAME_MODE__SHIFT 0x9
1851#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET_MASK 0x400
1852#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_SOFT_RESET__SHIFT 0xa
1853#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE_MASK 0x800
1854#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_CACHE_INVALIDATE__SHIFT 0xb
1855#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID_MASK 0x7000
1856#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_CHANNEL_ID__SHIFT 0xc
1857#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE_MASK 0x8000
1858#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_FLIP_MODE__SHIFT 0xf
1859#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN_MASK 0xff0000
1860#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_REQUEST_MIN__SHIFT 0x10
1861#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE_MASK 0x1000000
1862#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_ACTIVE__SHIFT 0x18
1863#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING_MASK 0x2000000
1864#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLUSHING__SHIFT 0x19
1865#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING_MASK 0x4000000
1866#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_PIPE_FLIP_PENDING__SHIFT 0x1a
1867#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE_MASK 0x8000000
1868#define XDMA_MSTR_PIPE_CNTL__XDMA_MSTR_VSYNC_GSL_ENABLE__SHIFT 0x1b
1869#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x3fff
1870#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x0
1871#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000
1872#define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x10
1873#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH_MASK 0x3fff
1874#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_WIDTH__SHIFT 0x0
1875#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT_MASK 0x3fff0000
1876#define XDMA_MSTR_CHANNEL_DIM__XDMA_MSTR_CHANNEL_HEIGHT__SHIFT 0x10
1877#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x3fff
1878#define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x0
1879#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000
1880#define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x10
1881#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffff
1882#define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x0
1883#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0xff
1884#define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x0
1885#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffff
1886#define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x0
1887#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0xff
1888#define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x0
1889#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR_MASK 0xffffffff
1890#define XDMA_MSTR_CACHE_BASE_ADDR__XDMA_MSTR_CACHE_BASE_ADDR__SHIFT 0x0
1891#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH_MASK 0xff
1892#define XDMA_MSTR_CACHE_BASE_ADDR_HIGH__XDMA_MSTR_CACHE_BASE_ADDR_HIGH__SHIFT 0x0
1893#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH_MASK 0x3fff
1894#define XDMA_MSTR_CACHE_PITCH__XDMA_MSTR_CACHE_PITCH__SHIFT 0x0
1895#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X_MASK 0x3fff
1896#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_X__SHIFT 0x0
1897#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y_MASK 0x3fff0000
1898#define XDMA_MSTR_CHANNEL_START__XDMA_MSTR_CHANNEL_START_Y__SHIFT 0x10
1899#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0xffff
1900#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x0
1901#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000
1902#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x10
1903#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE_MASK 0x40000000
1904#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_BP_ENABLE__SHIFT 0x1e
1905#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000
1906#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x1f
1907#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT_MASK 0xffff
1908#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_COUNT__SHIFT 0x0
1909#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD_MASK 0x3fff0000
1910#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_THRESHOLD__SHIFT 0x10
1911#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE_MASK 0x80000000
1912#define XDMA_MSTR_MEM_UNDERFLOW_CNTL__XDMA_MSTR_UNDERFLOW_DETECT_ENABLE__SHIFT 0x1f
1913#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA_MASK 0xffffff
1914#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_DATA__SHIFT 0x0
1915#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MASK 0x7000000
1916#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX__SHIFT 0x18
1917#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE_MASK 0xc0000000
1918#define XDMA_MSTR_PERFMEAS_STATUS__XDMA_MSTR_PERFMEAS_INDEX_MODE__SHIFT 0x1e
1919#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER_MASK 0xfff
1920#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_MEAS_ITER__SHIFT 0x0
1921#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL_MASK 0x1f000
1922#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_SEGID_SEL__SHIFT 0xc
1923#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST_MASK 0x20000
1924#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_CACHE_BW_COUNTER_RST__SHIFT 0x11
1925#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER_MASK 0x7ff80000
1926#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_MEAS_ITER__SHIFT 0x13
1927#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST_MASK 0x80000000
1928#define XDMA_MSTR_PERFMEAS_CNTL__XDMA_MSTR_LT_COUNTER_RST__SHIFT 0x1f
1929#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION_MASK 0x3000
1930#define XDMA_MSTR_CNTL__XDMA_MSTR_ALPHA_POSITION__SHIFT 0xc
1931#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x4000
1932#define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0xe
1933#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x10000
1934#define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x10
1935#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x40000
1936#define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x12
1937#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x80000
1938#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x13
1939#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x100000
1940#define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x14
1941#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN_MASK 0x200000
1942#define XDMA_MSTR_CNTL__XDMA_MSTR_BIF_STALL_EN__SHIFT 0x15
1943#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x3fff
1944#define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x0
1945#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0xfff0000
1946#define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x10
1947#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT_MASK 0x70000000
1948#define XDMA_MSTR_STATUS__XDMA_MSTR_STATUS_SELECT__SHIFT 0x1c
1949#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x300
1950#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x8
1951#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0xf000
1952#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0xc
1953#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x10000
1954#define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x10
1955#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffff
1956#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x0
1957#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0xff
1958#define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x0
1959#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x3fff
1960#define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x0
1961#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL_MASK 0x1
1962#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_CLIENT_STALL__SHIFT 0x0
1963#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0xf00
1964#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x8
1965#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY_MASK 0xf000
1966#define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_STALL_DELAY__SHIFT 0xc
1967#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x1
1968#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x0
1969#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0xf0
1970#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x4
1971#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0xf00
1972#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x8
1973#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0xf000
1974#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0xc
1975#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000
1976#define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x10
1977#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT_MASK 0xffff
1978#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_LIMIT__SHIFT 0x0
1979#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER_MASK 0xffff0000
1980#define XDMA_MSTR_MEM_UNDERFLOW_CONFIG__XDMA_MSTR_UNDERFLOW_TIMER__SHIFT 0x10
1981#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x3ff
1982#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x0
1983#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x3000
1984#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0xc
1985#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x10000
1986#define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x10
1987#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x3ff
1988#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x0
1989#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x3000
1990#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0xc
1991#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x10000
1992#define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x10
1993#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL_MASK 0x7
1994#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_SEL__SHIFT 0x0
1995#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT_MASK 0x3fff00
1996#define XDMA_MSTR_VSYNC_GSL_CHECK__XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT__SHIFT 0x8
1997#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
1998#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
1999#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
2000#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
2001#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
2002#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
2003#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
2004#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
2005#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
2006#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
2007#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
2008#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
2009#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
2010#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
2011#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
2012#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
2013#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
2014#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
2015#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
2016#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
2017#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
2018#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
2019#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
2020#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
2021#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
2022#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
2023#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
2024#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
2025#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
2026#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
2027#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
2028#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
2029#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
2030#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
2031#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
2032#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
2033#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
2034#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
2035#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
2036#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
2037#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
2038#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
2039#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
2040#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
2041#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
2042#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
2043#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
2044#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
2045#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
2046#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
2047#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
2048#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
2049#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
2050#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
2051#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
2052#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
2053#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
2054#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
2055#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
2056#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
2057#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
2058#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
2059#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
2060#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
2061#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
2062#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
2063#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
2064#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
2065#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
2066#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
2067#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
2068#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
2069#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
2070#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
2071#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
2072#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
2073#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
2074#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
2075#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
2076#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
2077#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
2078#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
2079#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
2080#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
2081#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
2082#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
2083#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
2084#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
2085#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
2086#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
2087#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
2088#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
2089#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
2090#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
2091#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
2092#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
2093#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
2094#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
2095#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
2096#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
2097#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
2098#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
2099#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
2100#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
2101#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
2102#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
2103#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
2104#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
2105#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
2106#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
2107#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
2108#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
2109#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
2110#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
2111#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
2112#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
2113#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
2114#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
2115#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
2116#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
2117#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
2118#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
2119#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
2120#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
2121#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
2122#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
2123#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
2124#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
2125#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
2126#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
2127#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
2128#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
2129#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
2130#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
2131#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
2132#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
2133#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
2134#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
2135#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
2136#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
2137#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
2138#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
2139#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
2140#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
2141#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
2142#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
2143#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
2144#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
2145#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
2146#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
2147#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
2148#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
2149#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
2150#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
2151#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
2152#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
2153#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
2154#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
2155#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
2156#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
2157#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
2158#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
2159#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
2160#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
2161#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
2162#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
2163#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
2164#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
2165#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
2166#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
2167#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
2168#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
2169#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
2170#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
2171#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
2172#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
2173#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
2174#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
2175#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
2176#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
2177#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
2178#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
2179#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
2180#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
2181#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
2182#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
2183#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
2184#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
2185#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
2186#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
2187#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
2188#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
2189#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
2190#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
2191#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
2192#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
2193#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
2194#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
2195#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
2196#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
2197#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
2198#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
2199#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
2200#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
2201#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
2202#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
2203#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
2204#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
2205#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
2206#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
2207#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
2208#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
2209#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
2210#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
2211#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
2212#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
2213#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
2214#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
2215#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
2216#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
2217#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
2218#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
2219#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
2220#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
2221#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
2222#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
2223#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
2224#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
2225#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
2226#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
2227#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
2228#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
2229#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
2230#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
2231#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
2232#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
2233#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
2234#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
2235#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
2236#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
2237#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
2238#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
2239#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
2240#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
2241#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
2242#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
2243#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
2244#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
2245#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
2246#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
2247#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
2248#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
2249#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
2250#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
2251#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
2252#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
2253#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
2254#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
2255#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
2256#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
2257#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
2258#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
2259#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
2260#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
2261#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
2262#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
2263#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
2264#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
2265#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
2266#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
2267#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
2268#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
2269#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
2270#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
2271#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
2272#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
2273#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
2274#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
2275#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
2276#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
2277#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
2278#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
2279#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
2280#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
2281#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
2282#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
2283#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
2284#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
2285#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
2286#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
2287#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
2288#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
2289#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
2290#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
2291#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
2292#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
2293#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
2294#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
2295#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
2296#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
2297#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
2298#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
2299#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
2300#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
2301#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
2302#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
2303#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
2304#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
2305#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
2306#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
2307#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
2308#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
2309#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
2310#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
2311#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
2312#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
2313#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
2314#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
2315#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
2316#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
2317#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
2318#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
2319#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
2320#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
2321#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
2322#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
2323#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
2324#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
2325#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
2326#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
2327#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
2328#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
2329#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
2330#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
2331#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
2332#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
2333#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
2334#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
2335#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
2336#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
2337#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
2338#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
2339#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
2340#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
2341#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
2342#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
2343#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
2344#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
2345#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
2346#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
2347#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
2348#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
2349#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
2350#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
2351#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
2352#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
2353#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
2354#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
2355#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
2356#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
2357#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
2358#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
2359#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
2360#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
2361#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
2362#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
2363#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
2364#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
2365#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
2366#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
2367#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
2368#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
2369#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
2370#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
2371#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
2372#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
2373#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
2374#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
2375#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
2376#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
2377#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
2378#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
2379#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
2380#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
2381#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
2382#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
2383#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
2384#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
2385#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
2386#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
2387#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
2388#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
2389#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
2390#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
2391#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
2392#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
2393#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
2394#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
2395#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
2396#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
2397#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
2398#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
2399#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
2400#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
2401#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
2402#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
2403#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
2404#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
2405#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
2406#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
2407#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
2408#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
2409#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
2410#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
2411#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
2412#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
2413#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
2414#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
2415#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
2416#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
2417#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
2418#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
2419#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
2420#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
2421#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
2422#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
2423#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
2424#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
2425#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
2426#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
2427#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
2428#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
2429#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
2430#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
2431#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
2432#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
2433#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
2434#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
2435#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
2436#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
2437#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
2438#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
2439#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
2440#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
2441#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
2442#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
2443#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
2444#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
2445#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
2446#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
2447#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
2448#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
2449#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
2450#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
2451#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
2452#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
2453#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
2454#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
2455#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
2456#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
2457#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
2458#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
2459#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
2460#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
2461#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
2462#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
2463#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
2464#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
2465#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
2466#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
2467#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
2468#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
2469#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
2470#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
2471#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
2472#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
2473#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
2474#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
2475
2476#endif /* OSS_2_0_SH_MASK_H */
2477