1/*
2 * OSS_2_4 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef OSS_2_4_SH_MASK_H
25#define OSS_2_4_SH_MASK_H
26
27#define IH_VMID_0_LUT__PASID_MASK 0xffff
28#define IH_VMID_0_LUT__PASID__SHIFT 0x0
29#define IH_VMID_1_LUT__PASID_MASK 0xffff
30#define IH_VMID_1_LUT__PASID__SHIFT 0x0
31#define IH_VMID_2_LUT__PASID_MASK 0xffff
32#define IH_VMID_2_LUT__PASID__SHIFT 0x0
33#define IH_VMID_3_LUT__PASID_MASK 0xffff
34#define IH_VMID_3_LUT__PASID__SHIFT 0x0
35#define IH_VMID_4_LUT__PASID_MASK 0xffff
36#define IH_VMID_4_LUT__PASID__SHIFT 0x0
37#define IH_VMID_5_LUT__PASID_MASK 0xffff
38#define IH_VMID_5_LUT__PASID__SHIFT 0x0
39#define IH_VMID_6_LUT__PASID_MASK 0xffff
40#define IH_VMID_6_LUT__PASID__SHIFT 0x0
41#define IH_VMID_7_LUT__PASID_MASK 0xffff
42#define IH_VMID_7_LUT__PASID__SHIFT 0x0
43#define IH_VMID_8_LUT__PASID_MASK 0xffff
44#define IH_VMID_8_LUT__PASID__SHIFT 0x0
45#define IH_VMID_9_LUT__PASID_MASK 0xffff
46#define IH_VMID_9_LUT__PASID__SHIFT 0x0
47#define IH_VMID_10_LUT__PASID_MASK 0xffff
48#define IH_VMID_10_LUT__PASID__SHIFT 0x0
49#define IH_VMID_11_LUT__PASID_MASK 0xffff
50#define IH_VMID_11_LUT__PASID__SHIFT 0x0
51#define IH_VMID_12_LUT__PASID_MASK 0xffff
52#define IH_VMID_12_LUT__PASID__SHIFT 0x0
53#define IH_VMID_13_LUT__PASID_MASK 0xffff
54#define IH_VMID_13_LUT__PASID__SHIFT 0x0
55#define IH_VMID_14_LUT__PASID_MASK 0xffff
56#define IH_VMID_14_LUT__PASID__SHIFT 0x0
57#define IH_VMID_15_LUT__PASID_MASK 0xffff
58#define IH_VMID_15_LUT__PASID__SHIFT 0x0
59#define IH_RB_CNTL__RB_ENABLE_MASK 0x1
60#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0
61#define IH_RB_CNTL__RB_SIZE_MASK 0x3e
62#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
63#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40
64#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6
65#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80
66#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7
67#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100
68#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
69#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00
70#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
71#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000
72#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10
73#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
74#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
75#define IH_RB_BASE__ADDR_MASK 0xffffffff
76#define IH_RB_BASE__ADDR__SHIFT 0x0
77#define IH_RB_RPTR__OFFSET_MASK 0x3fffc
78#define IH_RB_RPTR__OFFSET__SHIFT 0x2
79#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
80#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0
81#define IH_RB_WPTR__OFFSET_MASK 0x3fffc
82#define IH_RB_WPTR__OFFSET__SHIFT 0x2
83#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000
84#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12
85#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000
86#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13
87#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff
88#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
89#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc
90#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
91#define IH_CNTL__ENABLE_INTR_MASK 0x1
92#define IH_CNTL__ENABLE_INTR__SHIFT 0x0
93#define IH_CNTL__MC_SWAP_MASK 0x6
94#define IH_CNTL__MC_SWAP__SHIFT 0x1
95#define IH_CNTL__RPTR_REARM_MASK 0x10
96#define IH_CNTL__RPTR_REARM__SHIFT 0x4
97#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300
98#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8
99#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00
100#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
101#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000
102#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf
103#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000
104#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14
105#define IH_CNTL__MC_VMID_MASK 0x1e000000
106#define IH_CNTL__MC_VMID__SHIFT 0x19
107#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
108#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0
109#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4
110#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2
111#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8
112#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3
113#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10
114#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4
115#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20
116#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5
117#define IH_STATUS__IDLE_MASK 0x1
118#define IH_STATUS__IDLE__SHIFT 0x0
119#define IH_STATUS__INPUT_IDLE_MASK 0x2
120#define IH_STATUS__INPUT_IDLE__SHIFT 0x1
121#define IH_STATUS__RB_IDLE_MASK 0x4
122#define IH_STATUS__RB_IDLE__SHIFT 0x2
123#define IH_STATUS__RB_FULL_MASK 0x8
124#define IH_STATUS__RB_FULL__SHIFT 0x3
125#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10
126#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4
127#define IH_STATUS__RB_OVERFLOW_MASK 0x20
128#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5
129#define IH_STATUS__MC_WR_IDLE_MASK 0x40
130#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6
131#define IH_STATUS__MC_WR_STALL_MASK 0x80
132#define IH_STATUS__MC_WR_STALL__SHIFT 0x7
133#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100
134#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8
135#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200
136#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9
137#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400
138#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
139#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
140#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0
141#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2
142#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
143#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
144#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
145#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100
146#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8
147#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200
148#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9
149#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
150#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
151#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
152#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
153#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
154#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
155#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff
156#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0
157#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff
158#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0
159#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff
160#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0
161#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
162#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0
163#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4
164#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2
165#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8
166#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3
167#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10
168#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4
169#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20
170#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5
171#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff
172#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0
173#define IH_VERSION__VALUE_MASK 0xfff
174#define IH_VERSION__VALUE__SHIFT 0x0
175#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3
176#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0
177#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc
178#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2
179#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00
180#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8
181#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
182#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
183#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
184#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
185#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00
186#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8
187#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000
188#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10
189#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00
190#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8
191#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000
192#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10
193#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00
194#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8
195#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000
196#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10
197#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00
198#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8
199#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000
200#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10
201#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00
202#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8
203#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000
204#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10
205#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00
206#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8
207#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000
208#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10
209#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00
210#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8
211#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000
212#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10
213#define SEM_STATUS__SEM_IDLE_MASK 0x1
214#define SEM_STATUS__SEM_IDLE__SHIFT 0x0
215#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2
216#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
217#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4
218#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2
219#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8
220#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3
221#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10
222#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4
223#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20
224#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5
225#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40
226#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6
227#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80
228#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7
229#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100
230#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8
231#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200
232#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9
233#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400
234#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
235#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800
236#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb
237#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000
238#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc
239#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000
240#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd
241#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000
242#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe
243#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2
244#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
245#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7
246#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0
247#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38
248#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3
249#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0
250#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6
251#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00
252#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9
253#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000
254#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc
255#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000
256#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf
257#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000
258#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12
259#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000
260#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15
261#define SEM_MAILBOX__SIDEPORT_MASK 0xff
262#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0
263#define SEM_MAILBOX__HOSTPORT_MASK 0xff00
264#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8
265#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000
266#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10
267#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000
268#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18
269#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff
270#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0
271#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00
272#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8
273#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000
274#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10
275#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000
276#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18
277#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
278#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0
279#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2
280#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
281#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4
282#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2
283#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18
284#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3
285#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00
286#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8
287#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f
288#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0
289#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000
290#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10
291#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000
292#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11
293#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000
294#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12
295#define SRBM_GFX_CNTL__PIPEID_MASK 0x3
296#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0
297#define SRBM_GFX_CNTL__MEID_MASK 0xc
298#define SRBM_GFX_CNTL__MEID__SHIFT 0x2
299#define SRBM_GFX_CNTL__VMID_MASK 0xf0
300#define SRBM_GFX_CNTL__VMID__SHIFT 0x4
301#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700
302#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
303#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff
304#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0
305#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
306#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0
307#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2
308#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
309#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4
310#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2
311#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8
312#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3
313#define SRBM_STATUS2__XSP_BUSY_MASK 0x10
314#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4
315#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20
316#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5
317#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40
318#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6
319#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80
320#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7
321#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100
322#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8
323#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200
324#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9
325#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400
326#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
327#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800
328#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb
329#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000
330#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc
331#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000
332#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd
333#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000
334#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe
335#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000
336#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10
337#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000
338#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11
339#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000
340#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12
341#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000
342#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13
343#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000
344#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14
345#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2
346#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
347#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4
348#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2
349#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8
350#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3
351#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10
352#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4
353#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20
354#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5
355#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40
356#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6
357#define SRBM_STATUS__VMC_BUSY_MASK 0x100
358#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
359#define SRBM_STATUS__MCB_BUSY_MASK 0x200
360#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
361#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
362#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
363#define SRBM_STATUS__MCC_BUSY_MASK 0x800
364#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
365#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
366#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
367#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000
368#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd
369#define SRBM_STATUS__SEM_BUSY_MASK 0x4000
370#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe
371#define SRBM_STATUS__ACP_BUSY_MASK 0x10000
372#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10
373#define SRBM_STATUS__IH_BUSY_MASK 0x20000
374#define SRBM_STATUS__IH_BUSY__SHIFT 0x11
375#define SRBM_STATUS__UVD_BUSY_MASK 0x80000
376#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13
377#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000
378#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14
379#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000
380#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15
381#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000
382#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16
383#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000
384#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d
385#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
386#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0
387#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2
388#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
389#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4
390#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2
391#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8
392#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3
393#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10
394#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4
395#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20
396#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5
397#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40
398#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6
399#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80
400#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7
401#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100
402#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8
403#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200
404#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9
405#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400
406#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
407#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800
408#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb
409#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000
410#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc
411#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000
412#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd
413#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000
414#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe
415#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000
416#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf
417#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
418#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0
419#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2
420#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
421#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4
422#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2
423#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8
424#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3
425#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10
426#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4
427#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20
428#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5
429#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40
430#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6
431#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100
432#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8
433#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200
434#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9
435#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400
436#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
437#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800
438#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb
439#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000
440#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc
441#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000
442#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd
443#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000
444#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe
445#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000
446#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf
447#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000
448#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10
449#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000
450#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11
451#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000
452#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12
453#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000
454#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13
455#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000
456#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14
457#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000
458#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15
459#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000
460#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16
461#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000
462#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17
463#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000
464#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18
465#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000
466#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19
467#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000
468#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a
469#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000
470#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b
471#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000
472#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c
473#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000
474#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d
475#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000
476#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e
477#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000
478#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f
479#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f
480#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0
481#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff
482#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0
483#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff
484#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
485#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
486#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
487#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
488#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
489#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
490#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
491#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
492#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
493#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
494#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
495#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
496#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
497#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
498#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
499#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
500#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
501#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
502#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
503#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
504#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
505#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
506#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
507#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
508#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
509#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
510#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
511#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
512#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
513#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
514#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
515#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
516#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
517#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
518#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
519#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
520#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
521#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
522#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
523#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
524#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
525#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
526#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0
527#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2
528#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
529#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4
530#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2
531#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10
532#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4
533#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20
534#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5
535#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40
536#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6
537#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80
538#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7
539#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100
540#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8
541#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200
542#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9
543#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400
544#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
545#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
546#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0
547#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2
548#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1
549#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4
550#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2
551#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8
552#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3
553#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10
554#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4
555#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20
556#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5
557#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40
558#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6
559#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80
560#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7
561#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100
562#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8
563#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200
564#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9
565#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400
566#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
567#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800
568#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb
569#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000
570#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc
571#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000
572#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd
573#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000
574#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe
575#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000
576#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf
577#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000
578#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10
579#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000
580#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11
581#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000
582#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12
583#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000
584#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13
585#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000
586#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14
587#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000
588#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15
589#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000
590#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16
591#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000
592#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17
593#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000
594#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18
595#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000
596#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19
597#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000
598#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a
599#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000
600#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b
601#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000
602#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c
603#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000
604#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d
605#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000
606#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e
607#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000
608#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f
609#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
610#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0
611#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
612#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
613#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000
614#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12
615#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000
616#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13
617#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000
618#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14
619#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000
620#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15
621#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000
622#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16
623#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000
624#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17
625#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000
626#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18
627#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000
628#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19
629#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000
630#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a
631#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000
632#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b
633#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000
634#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c
635#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000
636#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d
637#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
638#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
639#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
640#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0
641#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2
642#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
643#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4
644#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2
645#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000
646#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17
647#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000
648#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18
649#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
650#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0
651#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2
652#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
653#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
654#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0
655#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2
656#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
657#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
658#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0
659#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2
660#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
661#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
662#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0
663#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2
664#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
665#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4
666#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2
667#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8
668#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3
669#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20
670#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5
671#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40
672#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6
673#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80
674#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7
675#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100
676#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8
677#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200
678#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9
679#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400
680#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa
681#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800
682#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb
683#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000
684#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc
685#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000
686#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd
687#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000
688#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe
689#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000
690#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf
691#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000
692#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10
693#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000
694#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11
695#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000
696#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12
697#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000
698#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13
699#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000
700#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14
701#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000
702#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18
703#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000
704#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19
705#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000
706#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a
707#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000
708#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b
709#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000
710#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c
711#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc
712#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2
713#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000
714#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13
715#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000
716#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14
717#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000
718#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f
719#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff
720#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0
721#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000
722#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10
723#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff
724#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0
725#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff
726#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0
727#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000
728#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10
729#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff
730#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0
731#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
732#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
733#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
734#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
735#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
736#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
737#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
738#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
739#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
740#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
741#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff
742#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0
743#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff
744#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0
745#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff
746#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0
747#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff
748#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0
749#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3
750#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
751#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
752#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
753#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
754#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
755#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
756#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
757#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
758#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
759#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
760#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
761#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
762#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
763#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
764#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
765#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
766#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
767#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
768#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
769#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
770#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
771#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
772#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
773#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
774#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
775#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
776#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
777#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
778#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
779#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
780#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
781#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
782#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
783#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
784#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
785#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
786#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
787#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
788#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
789#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
790#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
791#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
792#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
793#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
794#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
795#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
796#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
797#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
798#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
799#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff
800#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0
801#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000
802#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10
803#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff
804#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0
805#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000
806#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10
807#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff
808#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0
809#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000
810#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10
811#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
812#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
813#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
814#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
815#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
816#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
817#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
818#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
819#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
820#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
821#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
822#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
823#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff
824#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0
825#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000
826#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10
827#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
828#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
829#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
830#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
831#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
832#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
833#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
834#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
835#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
836#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
837#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
838#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
839#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
840#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
841#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
842#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
843#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
844#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
845#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
846#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
847#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
848#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
849#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
850#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
851#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
852#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
853#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
854#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
855#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
856#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
857#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
858#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
859#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
860#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
861#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
862#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
863#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff
864#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0
865#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000
866#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10
867#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff
868#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0
869#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000
870#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10
871#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff
872#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0
873#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000
874#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10
875#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf
876#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0
877#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff
878#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0
879#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00
880#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8
881#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000
882#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10
883#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000
884#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d
885#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
886#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
887#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000
888#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f
889#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf
890#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0
891#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3
892#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0
893#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc
894#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2
895#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0
896#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4
897#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700
898#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8
899#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
900#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0
901#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
902#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0
903#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff
904#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0
905#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000
906#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f
907#define SDMA0_UCODE_ADDR__VALUE_MASK 0xfff
908#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0
909#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff
910#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0
911#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
912#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
913#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf
914#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
915#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
916#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
917#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
918#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
919#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
920#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
921#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
922#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
923#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
924#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
925#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
926#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
927#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
928#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
929#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
930#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
931#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
932#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
933#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
934#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
935#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
936#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
937#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8
938#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
939#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
940#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
941#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
942#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
943#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
944#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
945#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
946#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
947#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
948#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
949#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
950#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
951#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
952#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
953#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
954#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
955#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
956#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
957#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
958#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
959#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
960#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
961#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
962#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
963#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
964#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
965#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
966#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
967#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
968#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
969#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
970#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
971#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
972#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
973#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7
974#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0
975#define SDMA0_HASH__BANK_BITS_MASK 0x70
976#define SDMA0_HASH__BANK_BITS__SHIFT 0x4
977#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700
978#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
979#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000
980#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc
981#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
982#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
983#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
984#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
985#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
986#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
987#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff
988#define SDMA0_PROGRAM__STREAM__SHIFT 0x0
989#define SDMA0_STATUS_REG__IDLE_MASK 0x1
990#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0
991#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2
992#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
993#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4
994#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2
995#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8
996#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3
997#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10
998#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
999#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20
1000#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
1001#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40
1002#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
1003#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80
1004#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
1005#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100
1006#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
1007#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200
1008#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9
1009#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400
1010#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
1011#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
1012#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
1013#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000
1014#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc
1015#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000
1016#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
1017#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000
1018#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe
1019#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
1020#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
1021#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
1022#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
1023#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
1024#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
1025#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
1026#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
1027#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000
1028#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
1029#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
1030#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
1031#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
1032#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
1033#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
1034#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
1035#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
1036#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
1037#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000
1038#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a
1039#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
1040#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
1041#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
1042#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
1043#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000
1044#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e
1045#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
1046#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
1047#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
1048#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
1049#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1050#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
1051#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
1052#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1053#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
1054#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
1055#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
1056#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
1057#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20
1058#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
1059#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40
1060#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
1061#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
1062#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
1063#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
1064#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
1065#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
1066#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
1067#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
1068#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
1069#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000
1070#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
1071#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000
1072#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
1073#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
1074#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
1075#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1076#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
1077#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
1078#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1079#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
1080#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
1081#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
1082#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
1083#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
1084#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
1085#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
1086#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
1087#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
1088#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
1089#define SDMA0_F32_CNTL__HALT_MASK 0x1
1090#define SDMA0_F32_CNTL__HALT__SHIFT 0x0
1091#define SDMA0_F32_CNTL__STEP_MASK 0x2
1092#define SDMA0_F32_CNTL__STEP__SHIFT 0x1
1093#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
1094#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1095#define SDMA0_FREEZE__FREEZE_MASK 0x10
1096#define SDMA0_FREEZE__FREEZE__SHIFT 0x4
1097#define SDMA0_FREEZE__FROZEN_MASK 0x20
1098#define SDMA0_FREEZE__FROZEN__SHIFT 0x5
1099#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40
1100#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6
1101#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf
1102#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
1103#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00
1104#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
1105#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000
1106#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
1107#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf
1108#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
1109#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00
1110#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
1111#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000
1112#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
1113#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
1114#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0
1115#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2
1116#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
1117#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4
1118#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2
1119#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30
1120#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4
1121#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40
1122#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6
1123#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80
1124#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7
1125#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00
1126#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8
1127#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000
1128#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14
1129#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
1130#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
1131#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
1132#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
1133#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200
1134#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
1135#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400
1136#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
1137#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800
1138#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
1139#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000
1140#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc
1141#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000
1142#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd
1143#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
1144#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
1145#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
1146#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
1147#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff
1148#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0
1149#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff
1150#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0
1151#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2
1152#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1153#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
1154#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1155#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff
1156#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0
1157#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
1158#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
1159#define SDMA0_ID__DEVICE_ID_MASK 0xff
1160#define SDMA0_ID__DEVICE_ID__SHIFT 0x0
1161#define SDMA0_VERSION__VALUE_MASK 0xffff
1162#define SDMA0_VERSION__VALUE__SHIFT 0x0
1163#define SDMA0_STATUS2_REG__ID_MASK 0x3
1164#define SDMA0_STATUS2_REG__ID__SHIFT 0x0
1165#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
1166#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1167#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000
1168#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10
1169#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1170#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
1171#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
1172#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1173#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1174#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1175#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1176#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1177#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1178#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1179#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1180#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1181#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
1182#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
1183#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
1184#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
1185#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff
1186#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0
1187#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
1188#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
1189#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
1190#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1191#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
1192#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1193#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1194#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1195#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1196#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1197#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1198#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1199#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1200#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1201#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1202#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1203#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1204#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1205#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1206#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1207#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1208#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1209#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1210#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
1211#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1212#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1213#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1214#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1215#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
1216#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
1217#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
1218#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1219#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
1220#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1221#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
1222#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
1223#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
1224#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
1225#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff
1226#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0
1227#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1228#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1229#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1230#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1231#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1232#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
1233#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
1234#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1235#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
1236#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1237#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1238#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1239#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1240#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1241#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1242#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1243#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
1244#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1245#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
1246#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1247#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
1248#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
1249#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
1250#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
1251#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1252#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
1253#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
1254#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1255#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1256#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1257#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1258#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1259#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff
1260#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0
1261#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
1262#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
1263#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1264#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1265#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1266#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1267#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
1268#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1269#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
1270#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
1271#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
1272#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
1273#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
1274#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1275#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
1276#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
1277#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
1278#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1279#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
1280#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1281#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1282#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1283#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1284#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1285#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1286#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1287#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1288#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1289#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
1290#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
1291#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
1292#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
1293#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff
1294#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0
1295#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
1296#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
1297#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
1298#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1299#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
1300#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1301#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1302#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1303#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1304#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1305#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1306#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1307#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1308#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1309#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1310#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1311#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1312#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1313#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1314#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1315#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1316#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1317#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
1318#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1319#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1320#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1321#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1322#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1323#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
1324#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
1325#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
1326#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1327#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
1328#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1329#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
1330#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
1331#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
1332#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
1333#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff
1334#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0
1335#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1336#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1337#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
1338#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1339#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1340#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
1341#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
1342#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1343#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
1344#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1345#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1346#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1347#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1348#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1349#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1350#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1351#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
1352#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1353#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
1354#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1355#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
1356#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0
1357#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000
1358#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
1359#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
1360#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
1361#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
1362#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
1363#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
1364#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1365#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1366#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1367#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1368#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1369#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff
1370#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0
1371#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
1372#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
1373#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
1374#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1375#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
1376#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1377#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1378#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1379#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1380#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1381#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
1382#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1383#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
1384#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
1385#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
1386#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
1387#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
1388#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1389#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
1390#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
1391#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
1392#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1393#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
1394#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1395#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1396#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1397#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1398#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1399#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1400#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1401#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1402#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1403#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
1404#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
1405#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
1406#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
1407#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff
1408#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0
1409#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
1410#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
1411#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
1412#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1413#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
1414#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1415#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1416#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1417#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1418#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1419#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1420#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1421#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1422#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1423#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1424#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1425#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1426#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1427#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1428#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1429#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1430#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1431#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
1432#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1433#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1434#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1435#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1436#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1437#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
1438#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
1439#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
1440#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
1441#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
1442#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
1443#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
1444#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
1445#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
1446#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
1447#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff
1448#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0
1449#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1450#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1451#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
1452#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1453#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1454#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
1455#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
1456#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
1457#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
1458#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1459#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1460#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1461#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1462#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1463#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1464#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1465#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
1466#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1467#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
1468#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1469#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
1470#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0
1471#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000
1472#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
1473#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
1474#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
1475#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
1476#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
1477#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
1478#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1479#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1480#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1481#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1482#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1483#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff
1484#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
1485#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
1486#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
1487#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
1488#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1489#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
1490#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
1491#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1492#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1493#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1494#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1495#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
1496#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
1497#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
1498#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
1499#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
1500#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
1501#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
1502#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1503#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
1504#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
1505#define SDMA1_UCODE_ADDR__VALUE_MASK 0xfff
1506#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0
1507#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff
1508#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0
1509#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100
1510#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
1511#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf
1512#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0
1513#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1514#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1515#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
1516#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1517#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
1518#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1519#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
1520#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1521#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
1522#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1523#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
1524#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1525#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
1526#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1527#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
1528#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1529#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
1530#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1531#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
1532#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0
1533#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4
1534#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
1535#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8
1536#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
1537#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10
1538#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
1539#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800
1540#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb
1541#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000
1542#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
1543#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000
1544#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16
1545#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000
1546#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
1547#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000
1548#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
1549#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000
1550#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
1551#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
1552#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0
1553#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2
1554#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
1555#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4
1556#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
1557#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000
1558#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
1559#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000
1560#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14
1561#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000
1562#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17
1563#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000
1564#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a
1565#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000
1566#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
1567#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000
1568#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e
1569#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1570#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1571#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7
1572#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0
1573#define SDMA1_HASH__BANK_BITS_MASK 0x70
1574#define SDMA1_HASH__BANK_BITS__SHIFT 0x4
1575#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700
1576#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8
1577#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000
1578#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc
1579#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff
1580#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
1581#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc
1582#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2
1583#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc
1584#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2
1585#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff
1586#define SDMA1_PROGRAM__STREAM__SHIFT 0x0
1587#define SDMA1_STATUS_REG__IDLE_MASK 0x1
1588#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0
1589#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2
1590#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
1591#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4
1592#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2
1593#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8
1594#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3
1595#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10
1596#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4
1597#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20
1598#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5
1599#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40
1600#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6
1601#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80
1602#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7
1603#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100
1604#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8
1605#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200
1606#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9
1607#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400
1608#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
1609#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800
1610#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb
1611#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000
1612#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc
1613#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000
1614#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd
1615#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000
1616#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe
1617#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000
1618#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf
1619#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000
1620#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10
1621#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000
1622#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11
1623#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000
1624#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12
1625#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000
1626#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13
1627#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000
1628#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14
1629#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000
1630#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15
1631#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000
1632#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16
1633#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000
1634#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19
1635#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000
1636#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a
1637#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000
1638#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b
1639#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000
1640#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c
1641#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000
1642#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e
1643#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000
1644#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f
1645#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
1646#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
1647#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2
1648#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
1649#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4
1650#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2
1651#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8
1652#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
1653#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10
1654#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
1655#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20
1656#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
1657#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40
1658#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6
1659#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200
1660#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9
1661#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400
1662#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
1663#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000
1664#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd
1665#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000
1666#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe
1667#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000
1668#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11
1669#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000
1670#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12
1671#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
1672#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0
1673#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2
1674#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
1675#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc
1676#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2
1677#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100
1678#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8
1679#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200
1680#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9
1681#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00
1682#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
1683#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff
1684#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0
1685#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff
1686#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0
1687#define SDMA1_F32_CNTL__HALT_MASK 0x1
1688#define SDMA1_F32_CNTL__HALT__SHIFT 0x0
1689#define SDMA1_F32_CNTL__STEP_MASK 0x2
1690#define SDMA1_F32_CNTL__STEP__SHIFT 0x1
1691#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc
1692#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2
1693#define SDMA1_FREEZE__FREEZE_MASK 0x10
1694#define SDMA1_FREEZE__FREEZE__SHIFT 0x4
1695#define SDMA1_FREEZE__FROZEN_MASK 0x20
1696#define SDMA1_FREEZE__FROZEN__SHIFT 0x5
1697#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40
1698#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6
1699#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf
1700#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0
1701#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00
1702#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8
1703#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000
1704#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e
1705#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf
1706#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0
1707#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00
1708#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8
1709#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000
1710#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e
1711#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2
1712#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1713#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4
1714#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2
1715#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff
1716#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0
1717#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000
1718#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10
1719#define SDMA1_ID__DEVICE_ID_MASK 0xff
1720#define SDMA1_ID__DEVICE_ID__SHIFT 0x0
1721#define SDMA1_VERSION__VALUE_MASK 0xffff
1722#define SDMA1_VERSION__VALUE__SHIFT 0x0
1723#define SDMA1_STATUS2_REG__ID_MASK 0x3
1724#define SDMA1_STATUS2_REG__ID__SHIFT 0x0
1725#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc
1726#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2
1727#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000
1728#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10
1729#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1730#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0
1731#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e
1732#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1733#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1734#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1735#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1736#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1737#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1738#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1739#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1740#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1741#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000
1742#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17
1743#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000
1744#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18
1745#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff
1746#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0
1747#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff
1748#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0
1749#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc
1750#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2
1751#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc
1752#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2
1753#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1754#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1755#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1756#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1757#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1758#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1759#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1760#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1761#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1762#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1763#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1764#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1765#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1766#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1767#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1768#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1769#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1770#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0
1771#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1772#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1773#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1774#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1775#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000
1776#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10
1777#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc
1778#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2
1779#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc
1780#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2
1781#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0
1782#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5
1783#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff
1784#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0
1785#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff
1786#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0
1787#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1788#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1789#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1790#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1791#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1792#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
1793#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4
1794#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2
1795#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8
1796#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1797#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1798#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1799#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1800#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1801#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1802#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1803#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200
1804#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1805#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
1806#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1807#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000
1808#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10
1809#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000
1810#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18
1811#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1812#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0
1813#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10
1814#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1815#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1816#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1817#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1818#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1819#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff
1820#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0
1821#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000
1822#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10
1823#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1824#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1825#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1826#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1827#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
1828#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2
1829#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff
1830#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0
1831#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff
1832#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0
1833#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff
1834#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1835#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
1836#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0
1837#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
1838#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0
1839#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e
1840#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1841#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1842#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1843#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1844#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1845#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1846#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1847#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1848#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1849#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000
1850#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17
1851#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000
1852#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18
1853#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff
1854#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0
1855#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff
1856#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0
1857#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc
1858#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2
1859#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc
1860#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2
1861#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1862#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1863#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1864#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1865#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1866#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1867#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1868#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1869#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1870#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1871#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1872#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1873#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1874#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1875#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1876#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1877#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
1878#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0
1879#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1880#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1881#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1882#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1883#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000
1884#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10
1885#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc
1886#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2
1887#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc
1888#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2
1889#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0
1890#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5
1891#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff
1892#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0
1893#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff
1894#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0
1895#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
1896#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
1897#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
1898#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0
1899#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
1900#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
1901#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4
1902#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2
1903#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8
1904#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
1905#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70
1906#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
1907#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
1908#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
1909#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
1910#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
1911#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200
1912#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
1913#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
1914#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
1915#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff
1916#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0
1917#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000
1918#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c
1919#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000
1920#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e
1921#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
1922#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0
1923#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10
1924#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4
1925#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
1926#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
1927#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
1928#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
1929#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff
1930#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0
1931#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000
1932#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
1933#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
1934#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
1935#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc
1936#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2
1937#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff
1938#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
1939#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
1940#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
1941#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
1942#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2
1943#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff
1944#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0
1945#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff
1946#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0
1947#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff
1948#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0
1949#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
1950#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0
1951#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
1952#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0
1953#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e
1954#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1955#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200
1956#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9
1957#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000
1958#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc
1959#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000
1960#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd
1961#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000
1962#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
1963#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000
1964#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17
1965#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000
1966#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18
1967#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff
1968#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0
1969#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff
1970#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0
1971#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc
1972#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2
1973#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc
1974#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2
1975#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1976#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0
1977#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2
1978#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1979#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0
1980#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
1981#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
1982#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1983#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff
1984#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
1985#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc
1986#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2
1987#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff
1988#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0
1989#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc
1990#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2
1991#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
1992#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0
1993#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10
1994#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4
1995#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100
1996#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8
1997#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000
1998#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10
1999#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc
2000#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2
2001#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc
2002#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2
2003#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0
2004#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5
2005#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff
2006#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0
2007#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff
2008#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0
2009#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff
2010#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0
2011#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
2012#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0
2013#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2
2014#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1
2015#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4
2016#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
2017#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8
2018#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3
2019#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70
2020#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4
2021#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80
2022#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7
2023#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100
2024#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8
2025#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200
2026#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9
2027#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400
2028#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa
2029#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff
2030#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0
2031#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000
2032#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c
2033#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000
2034#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e
2035#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
2036#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0
2037#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10
2038#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4
2039#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700
2040#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8
2041#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000
2042#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e
2043#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff
2044#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0
2045#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000
2046#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
2047#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
2048#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0
2049#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc
2050#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2
2051#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff
2052#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0
2053#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000
2054#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10
2055#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc
2056#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2
2057#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff
2058#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0
2059#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff
2060#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0
2061#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff
2062#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0
2063#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
2064#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0
2065#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7
2066#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0
2067#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8
2068#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3
2069#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600
2070#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9
2071#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800
2072#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb
2073#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000
2074#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13
2075#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000
2076#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15
2077#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000
2078#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16
2079#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000
2080#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17
2081#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000
2082#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18
2083#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000
2084#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d
2085#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000
2086#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e
2087#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000
2088#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f
2089#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff
2090#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0
2091#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
2092#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0
2093#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e
2094#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
2095#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60
2096#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5
2097#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380
2098#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7
2099#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00
2100#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa
2101#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000
2102#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd
2103#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000
2104#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf
2105#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000
2106#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10
2107#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000
2108#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11
2109#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000
2110#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14
2111#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000
2112#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16
2113#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000
2114#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18
2115#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000
2116#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a
2117#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000
2118#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c
2119#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000
2120#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f
2121#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff
2122#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0
2123#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800
2124#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb
2125#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
2126#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0
2127#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2
2128#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
2129#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
2130#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0
2131#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2
2132#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
2133#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff
2134#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0
2135#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0
2136#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0
2137#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f
2138#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0
2139#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe
2140#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
2141#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30
2142#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4
2143#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0
2144#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6
2145#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700
2146#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8
2147#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800
2148#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb
2149#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000
2150#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe
2151#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7
2152#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0
2153#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18
2154#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3
2155#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff
2156#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0
2157#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00
2158#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8
2159#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7
2160#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
2161#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
2162#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
2163#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
2164#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
2165#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
2166#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
2167#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
2168#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
2169#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
2170#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
2171#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
2172#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
2173#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
2174#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
2175#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
2176#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
2177#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
2178#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0
2179#define HDP_MISC_CNTL__VM_ID_MASK 0x1e
2180#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
2181#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20
2182#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
2183#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40
2184#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
2185#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780
2186#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7
2187#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800
2188#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
2189#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000
2190#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc
2191#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000
2192#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd
2193#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000
2194#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13
2195#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000
2196#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14
2197#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000
2198#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
2199#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
2200#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0
2201#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e
2202#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
2203#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80
2204#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7
2205#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7
2206#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0
2207#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38
2208#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3
2209#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0
2210#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6
2211#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00
2212#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9
2213#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000
2214#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b
2215#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
2216#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0
2217#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2
2218#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
2219#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c
2220#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2
2221#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40
2222#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6
2223#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80
2224#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7
2225#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00
2226#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8
2227#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000
2228#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe
2229#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000
2230#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf
2231#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff
2232#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0
2233#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
2234#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0
2235#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2
2236#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
2237#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4
2238#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2
2239#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8
2240#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3
2241#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff
2242#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0
2243#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff
2244#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0
2245#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff
2246#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0
2247#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf
2248#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0
2249#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0
2250#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4
2251#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700
2252#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8
2253#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800
2254#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb
2255#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000
2256#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10
2257#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000
2258#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11
2259#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000
2260#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12
2261#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000
2262#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13
2263#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000
2264#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14
2265#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff
2266#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0
2267#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000
2268#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10
2269#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000
2270#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14
2271#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff
2272#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0
2273#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff
2274#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0
2275#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff
2276#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0
2277#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff
2278#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0
2279#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff
2280#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0
2281#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff
2282#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0
2283#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff
2284#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0
2285#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff
2286#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0
2287#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff
2288#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0
2289#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff
2290#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0
2291#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff
2292#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0
2293#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff
2294#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0
2295#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff
2296#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0
2297#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff
2298#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0
2299#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff
2300#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0
2301#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff
2302#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0
2303#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff
2304#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0
2305#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff
2306#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0
2307#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff
2308#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0
2309#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff
2310#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0
2311#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff
2312#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0
2313#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff
2314#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0
2315#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff
2316#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0
2317#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff
2318#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0
2319#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff
2320#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0
2321#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff
2322#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0
2323#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff
2324#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0
2325#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff
2326#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0
2327#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff
2328#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0
2329#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff
2330#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0
2331#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff
2332#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0
2333#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff
2334#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0
2335#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff
2336#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0
2337#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf
2338#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0
2339#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30
2340#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4
2341#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff
2342#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0
2343#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
2344#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0
2345#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe
2346#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
2347#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000
2348#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15
2349#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
2350#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0
2351#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe
2352#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
2353#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000
2354#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15
2355#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
2356#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0
2357#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe
2358#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
2359#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000
2360#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15
2361#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
2362#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0
2363#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe
2364#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
2365#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000
2366#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15
2367#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
2368#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0
2369#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe
2370#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
2371#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000
2372#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15
2373#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
2374#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0
2375#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe
2376#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
2377#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000
2378#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15
2379#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
2380#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0
2381#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe
2382#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
2383#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000
2384#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15
2385#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
2386#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0
2387#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6
2388#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
2389#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8
2390#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3
2391#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0
2392#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4
2393#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
2394#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0
2395#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6
2396#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
2397#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8
2398#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3
2399#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10
2400#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4
2401#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60
2402#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5
2403#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80
2404#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7
2405#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00
2406#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8
2407#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000
2408#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe
2409#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000
2410#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14
2411#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000
2412#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17
2413#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000
2414#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b
2415#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
2416#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0
2417#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6
2418#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
2419#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
2420#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0
2421#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6
2422#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1
2423#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18
2424#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3
2425#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f
2426#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0
2427#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0
2428#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6
2429#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000
2430#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc
2431#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000
2432#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd
2433#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f
2434#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0
2435#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40
2436#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6
2437#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80
2438#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7
2439#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf
2440#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0
2441#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0
2442#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4
2443#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000
2444#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc
2445#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000
2446#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e
2447#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000
2448#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f
2449#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff
2450#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0
2451#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000
2452#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10
2453#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000
2454#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14
2455#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff
2456#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0
2457#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000
2458#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10
2459#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000
2460#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14
2461#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff
2462#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0
2463#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000
2464#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10
2465#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000
2466#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14
2467#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff
2468#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0
2469#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000
2470#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10
2471#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000
2472#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14
2473#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff
2474#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0
2475#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000
2476#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10
2477#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000
2478#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14
2479#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff
2480#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0
2481#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000
2482#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10
2483#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000
2484#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14
2485#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff
2486#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0
2487#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000
2488#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10
2489#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000
2490#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14
2491#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff
2492#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0
2493#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000
2494#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10
2495#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000
2496#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14
2497#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff
2498#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0
2499#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff
2500#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0
2501#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff
2502#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0
2503#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff
2504#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0
2505#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000
2506#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10
2507#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff
2508#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0
2509#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00
2510#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8
2511#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000
2512#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10
2513#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000
2514#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18
2515#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff
2516#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0
2517#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000
2518#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10
2519#define HDP_XDP_DBG_DATA__STS_MASK 0xffff
2520#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0
2521#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000
2522#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10
2523#define HDP_XDP_DBG_MASK__STS_MASK 0xffff
2524#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0
2525#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000
2526#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10
2527#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf
2528#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0
2529#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0
2530#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4
2531#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00
2532#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8
2533#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000
2534#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc
2535#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000
2536#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10
2537#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000
2538#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14
2539#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000
2540#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18
2541#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000
2542#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c
2543
2544#endif /* OSS_2_4_SH_MASK_H */
2545