1/*
2 * OSS_3_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef OSS_3_0_D_H
25#define OSS_3_0_D_H
26
27#define mmIH_VMID_0_LUT 0xe00
28#define mmIH_VMID_1_LUT 0xe01
29#define mmIH_VMID_2_LUT 0xe02
30#define mmIH_VMID_3_LUT 0xe03
31#define mmIH_VMID_4_LUT 0xe04
32#define mmIH_VMID_5_LUT 0xe05
33#define mmIH_VMID_6_LUT 0xe06
34#define mmIH_VMID_7_LUT 0xe07
35#define mmIH_VMID_8_LUT 0xe08
36#define mmIH_VMID_9_LUT 0xe09
37#define mmIH_VMID_10_LUT 0xe0a
38#define mmIH_VMID_11_LUT 0xe0b
39#define mmIH_VMID_12_LUT 0xe0c
40#define mmIH_VMID_13_LUT 0xe0d
41#define mmIH_VMID_14_LUT 0xe0e
42#define mmIH_VMID_15_LUT 0xe0f
43#define mmIH_RB_CNTL 0xe30
44#define mmIH_RB_BASE 0xe31
45#define mmIH_RB_RPTR 0xe32
46#define mmIH_RB_WPTR 0xe33
47#define mmIH_RB_WPTR_ADDR_HI 0xe34
48#define mmIH_RB_WPTR_ADDR_LO 0xe35
49#define mmIH_CNTL 0xe36
50#define mmIH_LEVEL_STATUS 0xe37
51#define mmIH_STATUS 0xe38
52#define mmIH_PERFMON_CNTL 0xe39
53#define mmIH_PERFCOUNTER0_RESULT 0xe3a
54#define mmIH_PERFCOUNTER1_RESULT 0xe3b
55#define mmIH_DEBUG 0xe3c
56#define mmIH_DSM_MATCH_VALUE_BIT_31_0 0xe3d
57#define mmIH_DSM_MATCH_VALUE_BIT_63_32 0xe3e
58#define mmIH_DSM_MATCH_VALUE_BIT_95_64 0xe3f
59#define mmIH_DSM_MATCH_FIELD_CONTROL 0xe40
60#define mmIH_DSM_MATCH_DATA_CONTROL 0xe41
61#define mmIH_DOORBELL_RPTR 0xe42
62#define mmIH_ACTIVE_FCN_ID 0xe43
63#define mmIH_VF_RB_STATUS 0xe44
64#define mmIH_VF_ENABLE 0xe45
65#define mmIH_VIRT_RESET_REQ 0xe46
66#define mmIH_VF_RB_BIF_STATUS 0xe47
67#define mmIH_VERSION 0xe48
68#define mmIH_LEVEL_INTR_MASK 0xe49
69#define mmIH_RESET_INCOMPLETE_INT_CNTL 0xe4a
70#define mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0xe4b
71#define mmSEM_MCIF_CONFIG 0xf90
72#define mmSDMA_CONFIG 0xf91
73#define mmSDMA1_CONFIG 0xf92
74#define mmUVD_CONFIG 0xf93
75#define mmVCE_CONFIG 0xf94
76#define mmSEM_VF_ENABLE 0xf95
77#define mmCP_CONFIG 0xf96
78#define mmSEM_ACTIVE_FCN_ID 0xf97
79#define mmSEM_VIRT_RESET_REQ 0xf98
80#define mmSEM_STATUS 0xf99
81#define mmSEM_EDC_CONFIG 0xf9a
82#define mmSEM_MAILBOX_CLIENTCONFIG 0xf9b
83#define mmSEM_MAILBOX 0xf9c
84#define mmSEM_MAILBOX_CONTROL 0xf9d
85#define mmSEM_CHICKEN_BITS 0xf9e
86#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0xf9f
87#define mmSRBM_CNTL 0x390
88#define mmSRBM_GFX_CNTL 0x391
89#define mmSRBM_READ_CNTL 0x392
90#define mmSRBM_STATUS2 0x393
91#define mmSRBM_STATUS 0x394
92#define mmSRBM_STATUS3 0x395
93#define mmSRBM_SOFT_RESET 0x398
94#define mmSRBM_DEBUG_CNTL 0x399
95#define mmSRBM_DEBUG_DATA 0x39a
96#define mmSRBM_CHIP_REVISION 0x39b
97#define mmSRBM_CREDIT_RECOVER_CNTL 0x39c
98#define mmSRBM_CREDIT_RECOVER 0x39d
99#define mmSRBM_CREDIT_RESET 0x39e
100#define mmCC_SYS_RB_REDUNDANCY 0x39f
101#define mmCC_SYS_RB_BACKEND_DISABLE 0x3a0
102#define mmGC_USER_SYS_RB_BACKEND_DISABLE 0x3a1
103#define mmSRBM_MC_CLKEN_CNTL 0x3b3
104#define mmSRBM_SYS_CLKEN_CNTL 0x3b4
105#define mmSRBM_VCE_CLKEN_CNTL 0x3b5
106#define mmSRBM_UVD_CLKEN_CNTL 0x3b6
107#define mmSRBM_SDMA_CLKEN_CNTL 0x3b7
108#define mmSRBM_SAM_CLKEN_CNTL 0x3b8
109#define mmSRBM_ISP_CLKEN_CNTL 0x3b9
110#define mmSRBM_VP8_CLKEN_CNTL 0x3ba
111#define mmSRBM_DEBUG 0x3a4
112#define mmSRBM_DEBUG_SNAPSHOT 0x3a5
113#define mmSRBM_DEBUG_SNAPSHOT2 0x3ad
114#define mmSRBM_READ_ERROR 0x3a6
115#define mmSRBM_READ_ERROR2 0x3ae
116#define mmSRBM_INT_CNTL 0x3a8
117#define mmSRBM_INT_STATUS 0x3a9
118#define mmSRBM_INT_ACK 0x3aa
119#define mmSRBM_FIREWALL_ERROR_SRC 0x3ab
120#define mmSRBM_FIREWALL_ERROR_ADDR 0x3ac
121#define mmSRBM_DSM_TRIG_CNTL0 0x3af
122#define mmSRBM_DSM_TRIG_CNTL1 0x3b0
123#define mmSRBM_DSM_TRIG_MASK0 0x3b1
124#define mmSRBM_DSM_TRIG_MASK1 0x3b2
125#define mmSRBM_PERFMON_CNTL 0x7c00
126#define mmSRBM_PERFCOUNTER0_SELECT 0x7c01
127#define mmSRBM_PERFCOUNTER1_SELECT 0x7c02
128#define mmSRBM_PERFCOUNTER0_LO 0x7c03
129#define mmSRBM_PERFCOUNTER0_HI 0x7c04
130#define mmSRBM_PERFCOUNTER1_LO 0x7c05
131#define mmSRBM_PERFCOUNTER1_HI 0x7c06
132#define mmSRBM_CAM_INDEX 0xfe34
133#define mmSRBM_CAM_DATA 0xfe35
134#define mmSRBM_MC_DOMAIN_ADDR0 0xfa00
135#define mmSRBM_MC_DOMAIN_ADDR1 0xfa01
136#define mmSRBM_MC_DOMAIN_ADDR2 0xfa02
137#define mmSRBM_MC_DOMAIN_ADDR3 0xfa03
138#define mmSRBM_MC_DOMAIN_ADDR4 0xfa04
139#define mmSRBM_MC_DOMAIN_ADDR5 0xfa05
140#define mmSRBM_MC_DOMAIN_ADDR6 0xfa06
141#define mmSRBM_SYS_DOMAIN_ADDR0 0xfa08
142#define mmSRBM_SYS_DOMAIN_ADDR1 0xfa09
143#define mmSRBM_SYS_DOMAIN_ADDR2 0xfa0a
144#define mmSRBM_SYS_DOMAIN_ADDR3 0xfa0b
145#define mmSRBM_SYS_DOMAIN_ADDR4 0xfa0c
146#define mmSRBM_SYS_DOMAIN_ADDR5 0xfa0d
147#define mmSRBM_SYS_DOMAIN_ADDR6 0xfa0e
148#define mmSRBM_SDMA_DOMAIN_ADDR0 0xfa10
149#define mmSRBM_SDMA_DOMAIN_ADDR1 0xfa11
150#define mmSRBM_SDMA_DOMAIN_ADDR2 0xfa12
151#define mmSRBM_SDMA_DOMAIN_ADDR3 0xfa13
152#define mmSRBM_UVD_DOMAIN_ADDR0 0xfa14
153#define mmSRBM_UVD_DOMAIN_ADDR1 0xfa15
154#define mmSRBM_UVD_DOMAIN_ADDR2 0xfa16
155#define mmSRBM_VCE_DOMAIN_ADDR0 0xfa18
156#define mmSRBM_VCE_DOMAIN_ADDR1 0xfa19
157#define mmSRBM_VCE_DOMAIN_ADDR2 0xfa1a
158#define mmSRBM_SAM_DOMAIN_ADDR0 0xfa1c
159#define mmSRBM_SAM_DOMAIN_ADDR1 0xfa1d
160#define mmSRBM_SAM_DOMAIN_ADDR2 0xfa1e
161#define mmSRBM_ISP_DOMAIN_ADDR0 0xfa20
162#define mmSRBM_ISP_DOMAIN_ADDR1 0xfa21
163#define mmSRBM_ISP_DOMAIN_ADDR2 0xfa22
164#define mmSRBM_VP8_DOMAIN_ADDR0 0xfa24
165#define mmSYS_GRBM_GFX_INDEX_SELECT 0xfa2c
166#define mmSYS_GRBM_GFX_INDEX_DATA 0xfa2d
167#define mmSRBM_GFX_CNTL_SELECT 0xfa2e
168#define mmSRBM_GFX_CNTL_DATA 0xfa2f
169#define mmSRBM_VF_ENABLE 0xfa30
170#define mmSRBM_VIRT_CNTL 0xfa31
171#define mmSRBM_VIRT_RESET_REQ 0xfa32
172#define mmCC_DRM_ID_STRAPS 0x1559
173#define mmCGTT_DRM_CLK_CTRL0 0x1579
174#define ixDH_TEST 0x0
175#define ixKHFS0 0x4
176#define ixKHFS1 0x8
177#define ixKHFS2 0xc
178#define ixKHFS3 0x10
179#define ixKSESSION0 0x14
180#define ixKSESSION1 0x18
181#define ixKSESSION2 0x1c
182#define ixKSESSION3 0x20
183#define ixKSIG0 0x24
184#define ixKSIG1 0x28
185#define ixKSIG2 0x2c
186#define ixKSIG3 0x30
187#define ixEXP0 0x34
188#define ixEXP1 0x38
189#define ixEXP2 0x3c
190#define ixEXP3 0x40
191#define ixEXP4 0x44
192#define ixEXP5 0x48
193#define ixEXP6 0x4c
194#define ixEXP7 0x50
195#define ixLX0 0x54
196#define ixLX1 0x58
197#define ixLX2 0x5c
198#define ixLX3 0x60
199#define ixCLIENT2_K0 0x1b4
200#define ixCLIENT2_K1 0x1b8
201#define ixCLIENT2_K2 0x1bc
202#define ixCLIENT2_K3 0x1c0
203#define ixCLIENT2_CK0 0x1c4
204#define ixCLIENT2_CK1 0x1c8
205#define ixCLIENT2_CK2 0x1cc
206#define ixCLIENT2_CK3 0x1d0
207#define ixCLIENT2_CD0 0x1d4
208#define ixCLIENT2_CD1 0x1d8
209#define ixCLIENT2_CD2 0x1dc
210#define ixCLIENT2_CD3 0x1e0
211#define ixCLIENT2_BM 0x1e4
212#define ixCLIENT2_OFFSET 0x1e8
213#define ixCLIENT2_STATUS 0x1ec
214#define ixCLIENT0_K0 0x1f0
215#define ixCLIENT0_K1 0x1f4
216#define ixCLIENT0_K2 0x1f8
217#define ixCLIENT0_K3 0x1fc
218#define ixCLIENT0_CK0 0x200
219#define ixCLIENT0_CK1 0x204
220#define ixCLIENT0_CK2 0x208
221#define ixCLIENT0_CK3 0x20c
222#define ixCLIENT0_CD0 0x210
223#define ixCLIENT0_CD1 0x214
224#define ixCLIENT0_CD2 0x218
225#define ixCLIENT0_CD3 0x21c
226#define ixCLIENT0_BM 0x220
227#define ixCLIENT0_OFFSET 0x224
228#define ixCLIENT0_STATUS 0x228
229#define ixCLIENT1_K0 0x22c
230#define ixCLIENT1_K1 0x230
231#define ixCLIENT1_K2 0x234
232#define ixCLIENT1_K3 0x238
233#define ixCLIENT1_CK0 0x23c
234#define ixCLIENT1_CK1 0x240
235#define ixCLIENT1_CK2 0x244
236#define ixCLIENT1_CK3 0x248
237#define ixCLIENT1_CD0 0x24c
238#define ixCLIENT1_CD1 0x250
239#define ixCLIENT1_CD2 0x254
240#define ixCLIENT1_CD3 0x258
241#define ixCLIENT1_BM 0x25c
242#define ixCLIENT1_OFFSET 0x260
243#define ixCLIENT1_PORT_STATUS 0x264
244#define ixKEFUSE0 0x268
245#define ixKEFUSE1 0x26c
246#define ixKEFUSE2 0x270
247#define ixKEFUSE3 0x274
248#define ixHFS_SEED0 0x278
249#define ixHFS_SEED1 0x27c
250#define ixHFS_SEED2 0x280
251#define ixHFS_SEED3 0x284
252#define ixRINGOSC_MASK 0x288
253#define ixCLIENT0_OFFSET_HI 0x290
254#define ixCLIENT1_OFFSET_HI 0x294
255#define ixCLIENT2_OFFSET_HI 0x298
256#define ixSPU_PORT_STATUS 0x29c
257#define ixCLIENT3_OFFSET_HI 0x2a0
258#define ixCLIENT3_K0 0x2a4
259#define ixCLIENT3_K1 0x2a8
260#define ixCLIENT3_K2 0x2ac
261#define ixCLIENT3_K3 0x2b0
262#define ixCLIENT3_CK0 0x2b4
263#define ixCLIENT3_CK1 0x2b8
264#define ixCLIENT3_CK2 0x2bc
265#define ixCLIENT3_CK3 0x2c0
266#define ixCLIENT3_CD0 0x2c4
267#define ixCLIENT3_CD1 0x2c8
268#define ixCLIENT3_CD2 0x2cc
269#define ixCLIENT3_CD3 0x2d0
270#define ixCLIENT3_BM 0x2d4
271#define ixCLIENT3_OFFSET 0x2d8
272#define ixCLIENT3_STATUS 0x2dc
273#define ixCLIENT4_OFFSET_HI 0x2e0
274#define ixCLIENT4_K0 0x2e4
275#define ixCLIENT4_K1 0x2e8
276#define ixCLIENT4_K2 0x2ec
277#define ixCLIENT4_K3 0x2f0
278#define ixCLIENT4_CK0 0x2f4
279#define ixCLIENT4_CK1 0x2f8
280#define ixCLIENT4_CK2 0x2fc
281#define ixCLIENT4_CK3 0x300
282#define ixCLIENT4_CD0 0x304
283#define ixCLIENT4_CD1 0x308
284#define ixCLIENT4_CD2 0x30c
285#define ixCLIENT4_CD3 0x310
286#define ixCLIENT4_BM 0x314
287#define ixCLIENT4_OFFSET 0x318
288#define ixCLIENT4_STATUS 0x31c
289#define mmDC_TEST_DEBUG_INDEX 0x157c
290#define mmDC_TEST_DEBUG_DATA 0x157d
291#define mmSDMA0_UCODE_ADDR 0x3400
292#define mmSDMA0_UCODE_DATA 0x3401
293#define mmSDMA0_POWER_CNTL 0x3402
294#define mmSDMA0_CLK_CTRL 0x3403
295#define mmSDMA0_CNTL 0x3404
296#define mmSDMA0_CHICKEN_BITS 0x3405
297#define mmSDMA0_TILING_CONFIG 0x3406
298#define mmSDMA0_HASH 0x3407
299#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x3409
300#define mmSDMA0_RB_RPTR_FETCH 0x340a
301#define mmSDMA0_IB_OFFSET_FETCH 0x340b
302#define mmSDMA0_PROGRAM 0x340c
303#define mmSDMA0_STATUS_REG 0x340d
304#define mmSDMA0_STATUS1_REG 0x340e
305#define mmSDMA0_RD_BURST_CNTL 0x340f
306#define mmSDMA0_PERFMON_CNTL 0x9000
307#define mmSDMA0_PERFCOUNTER0_RESULT 0x9001
308#define mmSDMA0_PERFCOUNTER1_RESULT 0x9002
309#define mmSDMA0_F32_CNTL 0x3412
310#define mmSDMA0_FREEZE 0x3413
311#define mmSDMA0_PHASE0_QUANTUM 0x3414
312#define mmSDMA0_PHASE1_QUANTUM 0x3415
313#define mmSDMA_POWER_GATING 0x3416
314#define mmSDMA_PGFSM_CONFIG 0x3417
315#define mmSDMA_PGFSM_WRITE 0x3418
316#define mmSDMA_PGFSM_READ 0x3419
317#define mmSDMA0_EDC_CONFIG 0x341a
318#define mmSDMA0_VM_CNTL 0x3420
319#define mmSDMA0_VM_CTX_LO 0x3421
320#define mmSDMA0_VM_CTX_HI 0x3422
321#define mmSDMA0_STATUS2_REG 0x3423
322#define mmSDMA0_ACTIVE_FCN_ID 0x3424
323#define mmSDMA0_VM_CTX_CNTL 0x3425
324#define mmSDMA0_VIRT_RESET_REQ 0x3426
325#define mmSDMA0_VF_ENABLE 0x3427
326#define mmSDMA0_BA_THRESHOLD 0x341b
327#define mmSDMA0_ID 0x341c
328#define mmSDMA0_VERSION 0x341d
329#define mmSDMA0_ATOMIC_CNTL 0x3428
330#define mmSDMA0_ATOMIC_PREOP_LO 0x3429
331#define mmSDMA0_ATOMIC_PREOP_HI 0x342a
332#define mmSDMA0_POWER_CNTL_IDLE 0x342c
333#define mmSDMA0_PERF_REG_TYPE0 0x3477
334#define mmSDMA0_CONTEXT_REG_TYPE0 0x3478
335#define mmSDMA0_CONTEXT_REG_TYPE1 0x3479
336#define mmSDMA0_CONTEXT_REG_TYPE2 0x347a
337#define mmSDMA0_PUB_REG_TYPE0 0x347c
338#define mmSDMA0_PUB_REG_TYPE1 0x347d
339#define mmSDMA0_GFX_RB_CNTL 0x3480
340#define mmSDMA0_GFX_RB_BASE 0x3481
341#define mmSDMA0_GFX_RB_BASE_HI 0x3482
342#define mmSDMA0_GFX_RB_RPTR 0x3483
343#define mmSDMA0_GFX_RB_WPTR 0x3484
344#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x3485
345#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486
346#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487
347#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x3488
348#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x3489
349#define mmSDMA0_GFX_IB_CNTL 0x348a
350#define mmSDMA0_GFX_IB_RPTR 0x348b
351#define mmSDMA0_GFX_IB_OFFSET 0x348c
352#define mmSDMA0_GFX_IB_BASE_LO 0x348d
353#define mmSDMA0_GFX_IB_BASE_HI 0x348e
354#define mmSDMA0_GFX_IB_SIZE 0x348f
355#define mmSDMA0_GFX_SKIP_CNTL 0x3490
356#define mmSDMA0_GFX_CONTEXT_STATUS 0x3491
357#define mmSDMA0_GFX_DOORBELL 0x3492
358#define mmSDMA0_GFX_CONTEXT_CNTL 0x3493
359#define mmSDMA0_GFX_VIRTUAL_ADDR 0x34a7
360#define mmSDMA0_GFX_APE1_CNTL 0x34a8
361#define mmSDMA0_GFX_DOORBELL_LOG 0x34a9
362#define mmSDMA0_GFX_WATERMARK 0x34aa
363#define mmSDMA0_GFX_CSA_ADDR_LO 0x34ac
364#define mmSDMA0_GFX_CSA_ADDR_HI 0x34ad
365#define mmSDMA0_GFX_IB_SUB_REMAIN 0x34af
366#define mmSDMA0_GFX_PREEMPT 0x34b0
367#define mmSDMA0_GFX_DUMMY_REG 0x34b1
368#define mmSDMA0_GFX_MIDCMD_DATA0 0x34c1
369#define mmSDMA0_GFX_MIDCMD_DATA1 0x34c2
370#define mmSDMA0_GFX_MIDCMD_DATA2 0x34c3
371#define mmSDMA0_GFX_MIDCMD_DATA3 0x34c4
372#define mmSDMA0_GFX_MIDCMD_DATA4 0x34c5
373#define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6
374#define mmSDMA0_GFX_MIDCMD_CNTL 0x34c7
375#define mmSDMA0_RLC0_RB_CNTL 0x3500
376#define mmSDMA0_RLC0_RB_BASE 0x3501
377#define mmSDMA0_RLC0_RB_BASE_HI 0x3502
378#define mmSDMA0_RLC0_RB_RPTR 0x3503
379#define mmSDMA0_RLC0_RB_WPTR 0x3504
380#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505
381#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x3506
382#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x3507
383#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x3508
384#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x3509
385#define mmSDMA0_RLC0_IB_CNTL 0x350a
386#define mmSDMA0_RLC0_IB_RPTR 0x350b
387#define mmSDMA0_RLC0_IB_OFFSET 0x350c
388#define mmSDMA0_RLC0_IB_BASE_LO 0x350d
389#define mmSDMA0_RLC0_IB_BASE_HI 0x350e
390#define mmSDMA0_RLC0_IB_SIZE 0x350f
391#define mmSDMA0_RLC0_SKIP_CNTL 0x3510
392#define mmSDMA0_RLC0_CONTEXT_STATUS 0x3511
393#define mmSDMA0_RLC0_DOORBELL 0x3512
394#define mmSDMA0_RLC0_VIRTUAL_ADDR 0x3527
395#define mmSDMA0_RLC0_APE1_CNTL 0x3528
396#define mmSDMA0_RLC0_DOORBELL_LOG 0x3529
397#define mmSDMA0_RLC0_WATERMARK 0x352a
398#define mmSDMA0_RLC0_CSA_ADDR_LO 0x352c
399#define mmSDMA0_RLC0_CSA_ADDR_HI 0x352d
400#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x352f
401#define mmSDMA0_RLC0_PREEMPT 0x3530
402#define mmSDMA0_RLC0_DUMMY_REG 0x3531
403#define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541
404#define mmSDMA0_RLC0_MIDCMD_DATA1 0x3542
405#define mmSDMA0_RLC0_MIDCMD_DATA2 0x3543
406#define mmSDMA0_RLC0_MIDCMD_DATA3 0x3544
407#define mmSDMA0_RLC0_MIDCMD_DATA4 0x3545
408#define mmSDMA0_RLC0_MIDCMD_DATA5 0x3546
409#define mmSDMA0_RLC0_MIDCMD_CNTL 0x3547
410#define mmSDMA0_RLC1_RB_CNTL 0x3580
411#define mmSDMA0_RLC1_RB_BASE 0x3581
412#define mmSDMA0_RLC1_RB_BASE_HI 0x3582
413#define mmSDMA0_RLC1_RB_RPTR 0x3583
414#define mmSDMA0_RLC1_RB_WPTR 0x3584
415#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x3585
416#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x3586
417#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x3587
418#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x3588
419#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x3589
420#define mmSDMA0_RLC1_IB_CNTL 0x358a
421#define mmSDMA0_RLC1_IB_RPTR 0x358b
422#define mmSDMA0_RLC1_IB_OFFSET 0x358c
423#define mmSDMA0_RLC1_IB_BASE_LO 0x358d
424#define mmSDMA0_RLC1_IB_BASE_HI 0x358e
425#define mmSDMA0_RLC1_IB_SIZE 0x358f
426#define mmSDMA0_RLC1_SKIP_CNTL 0x3590
427#define mmSDMA0_RLC1_CONTEXT_STATUS 0x3591
428#define mmSDMA0_RLC1_DOORBELL 0x3592
429#define mmSDMA0_RLC1_VIRTUAL_ADDR 0x35a7
430#define mmSDMA0_RLC1_APE1_CNTL 0x35a8
431#define mmSDMA0_RLC1_DOORBELL_LOG 0x35a9
432#define mmSDMA0_RLC1_WATERMARK 0x35aa
433#define mmSDMA0_RLC1_CSA_ADDR_LO 0x35ac
434#define mmSDMA0_RLC1_CSA_ADDR_HI 0x35ad
435#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x35af
436#define mmSDMA0_RLC1_PREEMPT 0x35b0
437#define mmSDMA0_RLC1_DUMMY_REG 0x35b1
438#define mmSDMA0_RLC1_MIDCMD_DATA0 0x35c1
439#define mmSDMA0_RLC1_MIDCMD_DATA1 0x35c2
440#define mmSDMA0_RLC1_MIDCMD_DATA2 0x35c3
441#define mmSDMA0_RLC1_MIDCMD_DATA3 0x35c4
442#define mmSDMA0_RLC1_MIDCMD_DATA4 0x35c5
443#define mmSDMA0_RLC1_MIDCMD_DATA5 0x35c6
444#define mmSDMA0_RLC1_MIDCMD_CNTL 0x35c7
445#define mmSDMA1_UCODE_ADDR 0x3600
446#define mmSDMA1_UCODE_DATA 0x3601
447#define mmSDMA1_POWER_CNTL 0x3602
448#define mmSDMA1_CLK_CTRL 0x3603
449#define mmSDMA1_CNTL 0x3604
450#define mmSDMA1_CHICKEN_BITS 0x3605
451#define mmSDMA1_TILING_CONFIG 0x3606
452#define mmSDMA1_HASH 0x3607
453#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x3609
454#define mmSDMA1_RB_RPTR_FETCH 0x360a
455#define mmSDMA1_IB_OFFSET_FETCH 0x360b
456#define mmSDMA1_PROGRAM 0x360c
457#define mmSDMA1_STATUS_REG 0x360d
458#define mmSDMA1_STATUS1_REG 0x360e
459#define mmSDMA1_RD_BURST_CNTL 0x360f
460#define mmSDMA1_PERFMON_CNTL 0x9010
461#define mmSDMA1_PERFCOUNTER0_RESULT 0x9011
462#define mmSDMA1_PERFCOUNTER1_RESULT 0x9012
463#define mmSDMA1_F32_CNTL 0x3612
464#define mmSDMA1_FREEZE 0x3613
465#define mmSDMA1_PHASE0_QUANTUM 0x3614
466#define mmSDMA1_PHASE1_QUANTUM 0x3615
467#define mmSDMA1_EDC_CONFIG 0x361a
468#define mmSDMA1_VM_CNTL 0x3620
469#define mmSDMA1_VM_CTX_LO 0x3621
470#define mmSDMA1_VM_CTX_HI 0x3622
471#define mmSDMA1_STATUS2_REG 0x3623
472#define mmSDMA1_ACTIVE_FCN_ID 0x3624
473#define mmSDMA1_VM_CTX_CNTL 0x3625
474#define mmSDMA1_VIRT_RESET_REQ 0x3626
475#define mmSDMA1_VF_ENABLE 0x3627
476#define mmSDMA1_BA_THRESHOLD 0x361b
477#define mmSDMA1_ID 0x361c
478#define mmSDMA1_VERSION 0x361d
479#define mmSDMA1_ATOMIC_CNTL 0x3628
480#define mmSDMA1_ATOMIC_PREOP_LO 0x3629
481#define mmSDMA1_ATOMIC_PREOP_HI 0x362a
482#define mmSDMA1_POWER_CNTL_IDLE 0x362c
483#define mmSDMA1_PERF_REG_TYPE0 0x3677
484#define mmSDMA1_CONTEXT_REG_TYPE0 0x3678
485#define mmSDMA1_CONTEXT_REG_TYPE1 0x3679
486#define mmSDMA1_CONTEXT_REG_TYPE2 0x367a
487#define mmSDMA1_PUB_REG_TYPE0 0x367c
488#define mmSDMA1_PUB_REG_TYPE1 0x367d
489#define mmSDMA1_GFX_RB_CNTL 0x3680
490#define mmSDMA1_GFX_RB_BASE 0x3681
491#define mmSDMA1_GFX_RB_BASE_HI 0x3682
492#define mmSDMA1_GFX_RB_RPTR 0x3683
493#define mmSDMA1_GFX_RB_WPTR 0x3684
494#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x3685
495#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x3686
496#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x3687
497#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x3688
498#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x3689
499#define mmSDMA1_GFX_IB_CNTL 0x368a
500#define mmSDMA1_GFX_IB_RPTR 0x368b
501#define mmSDMA1_GFX_IB_OFFSET 0x368c
502#define mmSDMA1_GFX_IB_BASE_LO 0x368d
503#define mmSDMA1_GFX_IB_BASE_HI 0x368e
504#define mmSDMA1_GFX_IB_SIZE 0x368f
505#define mmSDMA1_GFX_SKIP_CNTL 0x3690
506#define mmSDMA1_GFX_CONTEXT_STATUS 0x3691
507#define mmSDMA1_GFX_DOORBELL 0x3692
508#define mmSDMA1_GFX_CONTEXT_CNTL 0x3693
509#define mmSDMA1_GFX_VIRTUAL_ADDR 0x36a7
510#define mmSDMA1_GFX_APE1_CNTL 0x36a8
511#define mmSDMA1_GFX_DOORBELL_LOG 0x36a9
512#define mmSDMA1_GFX_WATERMARK 0x36aa
513#define mmSDMA1_GFX_CSA_ADDR_LO 0x36ac
514#define mmSDMA1_GFX_CSA_ADDR_HI 0x36ad
515#define mmSDMA1_GFX_IB_SUB_REMAIN 0x36af
516#define mmSDMA1_GFX_PREEMPT 0x36b0
517#define mmSDMA1_GFX_DUMMY_REG 0x36b1
518#define mmSDMA1_GFX_MIDCMD_DATA0 0x36c1
519#define mmSDMA1_GFX_MIDCMD_DATA1 0x36c2
520#define mmSDMA1_GFX_MIDCMD_DATA2 0x36c3
521#define mmSDMA1_GFX_MIDCMD_DATA3 0x36c4
522#define mmSDMA1_GFX_MIDCMD_DATA4 0x36c5
523#define mmSDMA1_GFX_MIDCMD_DATA5 0x36c6
524#define mmSDMA1_GFX_MIDCMD_CNTL 0x36c7
525#define mmSDMA1_RLC0_RB_CNTL 0x3700
526#define mmSDMA1_RLC0_RB_BASE 0x3701
527#define mmSDMA1_RLC0_RB_BASE_HI 0x3702
528#define mmSDMA1_RLC0_RB_RPTR 0x3703
529#define mmSDMA1_RLC0_RB_WPTR 0x3704
530#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705
531#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x3706
532#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x3707
533#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x3708
534#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x3709
535#define mmSDMA1_RLC0_IB_CNTL 0x370a
536#define mmSDMA1_RLC0_IB_RPTR 0x370b
537#define mmSDMA1_RLC0_IB_OFFSET 0x370c
538#define mmSDMA1_RLC0_IB_BASE_LO 0x370d
539#define mmSDMA1_RLC0_IB_BASE_HI 0x370e
540#define mmSDMA1_RLC0_IB_SIZE 0x370f
541#define mmSDMA1_RLC0_SKIP_CNTL 0x3710
542#define mmSDMA1_RLC0_CONTEXT_STATUS 0x3711
543#define mmSDMA1_RLC0_DOORBELL 0x3712
544#define mmSDMA1_RLC0_VIRTUAL_ADDR 0x3727
545#define mmSDMA1_RLC0_APE1_CNTL 0x3728
546#define mmSDMA1_RLC0_DOORBELL_LOG 0x3729
547#define mmSDMA1_RLC0_WATERMARK 0x372a
548#define mmSDMA1_RLC0_CSA_ADDR_LO 0x372c
549#define mmSDMA1_RLC0_CSA_ADDR_HI 0x372d
550#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x372f
551#define mmSDMA1_RLC0_PREEMPT 0x3730
552#define mmSDMA1_RLC0_DUMMY_REG 0x3731
553#define mmSDMA1_RLC0_MIDCMD_DATA0 0x3741
554#define mmSDMA1_RLC0_MIDCMD_DATA1 0x3742
555#define mmSDMA1_RLC0_MIDCMD_DATA2 0x3743
556#define mmSDMA1_RLC0_MIDCMD_DATA3 0x3744
557#define mmSDMA1_RLC0_MIDCMD_DATA4 0x3745
558#define mmSDMA1_RLC0_MIDCMD_DATA5 0x3746
559#define mmSDMA1_RLC0_MIDCMD_CNTL 0x3747
560#define mmSDMA1_RLC1_RB_CNTL 0x3780
561#define mmSDMA1_RLC1_RB_BASE 0x3781
562#define mmSDMA1_RLC1_RB_BASE_HI 0x3782
563#define mmSDMA1_RLC1_RB_RPTR 0x3783
564#define mmSDMA1_RLC1_RB_WPTR 0x3784
565#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x3785
566#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x3786
567#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x3787
568#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x3788
569#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x3789
570#define mmSDMA1_RLC1_IB_CNTL 0x378a
571#define mmSDMA1_RLC1_IB_RPTR 0x378b
572#define mmSDMA1_RLC1_IB_OFFSET 0x378c
573#define mmSDMA1_RLC1_IB_BASE_LO 0x378d
574#define mmSDMA1_RLC1_IB_BASE_HI 0x378e
575#define mmSDMA1_RLC1_IB_SIZE 0x378f
576#define mmSDMA1_RLC1_SKIP_CNTL 0x3790
577#define mmSDMA1_RLC1_CONTEXT_STATUS 0x3791
578#define mmSDMA1_RLC1_DOORBELL 0x3792
579#define mmSDMA1_RLC1_VIRTUAL_ADDR 0x37a7
580#define mmSDMA1_RLC1_APE1_CNTL 0x37a8
581#define mmSDMA1_RLC1_DOORBELL_LOG 0x37a9
582#define mmSDMA1_RLC1_WATERMARK 0x37aa
583#define mmSDMA1_RLC1_CSA_ADDR_LO 0x37ac
584#define mmSDMA1_RLC1_CSA_ADDR_HI 0x37ad
585#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x37af
586#define mmSDMA1_RLC1_PREEMPT 0x37b0
587#define mmSDMA1_RLC1_DUMMY_REG 0x37b1
588#define mmSDMA1_RLC1_MIDCMD_DATA0 0x37c1
589#define mmSDMA1_RLC1_MIDCMD_DATA1 0x37c2
590#define mmSDMA1_RLC1_MIDCMD_DATA2 0x37c3
591#define mmSDMA1_RLC1_MIDCMD_DATA3 0x37c4
592#define mmSDMA1_RLC1_MIDCMD_DATA4 0x37c5
593#define mmSDMA1_RLC1_MIDCMD_DATA5 0x37c6
594#define mmSDMA1_RLC1_MIDCMD_CNTL 0x37c7
595#define mmHDP_HOST_PATH_CNTL 0xb00
596#define mmHDP_NONSURFACE_BASE 0xb01
597#define mmHDP_NONSURFACE_INFO 0xb02
598#define mmHDP_NONSURFACE_SIZE 0xb03
599#define mmHDP_NONSURF_FLAGS 0xbc9
600#define mmHDP_NONSURF_FLAGS_CLR 0xbca
601#define mmHDP_SW_SEMAPHORE 0xbcb
602#define mmHDP_DEBUG0 0xbcc
603#define mmHDP_DEBUG1 0xbcd
604#define mmHDP_LAST_SURFACE_HIT 0xbce
605#define mmHDP_TILING_CONFIG 0xbcf
606#define mmHDP_SC_MULTI_CHIP_CNTL 0xbd0
607#define mmHDP_OUTSTANDING_REQ 0xbd1
608#define mmHDP_ADDR_CONFIG 0xbd2
609#define mmHDP_MISC_CNTL 0xbd3
610#define mmHDP_MEM_POWER_LS 0xbd4
611#define mmHDP_NONSURFACE_PREFETCH 0xbd5
612#define mmHDP_MEMIO_CNTL 0xbf6
613#define mmHDP_MEMIO_ADDR 0xbf7
614#define mmHDP_MEMIO_STATUS 0xbf8
615#define mmHDP_MEMIO_WR_DATA 0xbf9
616#define mmHDP_MEMIO_RD_DATA 0xbfa
617#define mmHDP_VF_ENABLE 0xbfb
618#define mmHDP_XDP_DIRECT2HDP_FIRST 0xc00
619#define mmHDP_XDP_D2H_FLUSH 0xc01
620#define mmHDP_XDP_D2H_BAR_UPDATE 0xc02
621#define mmHDP_XDP_D2H_RSVD_3 0xc03
622#define mmHDP_XDP_D2H_RSVD_4 0xc04
623#define mmHDP_XDP_D2H_RSVD_5 0xc05
624#define mmHDP_XDP_D2H_RSVD_6 0xc06
625#define mmHDP_XDP_D2H_RSVD_7 0xc07
626#define mmHDP_XDP_D2H_RSVD_8 0xc08
627#define mmHDP_XDP_D2H_RSVD_9 0xc09
628#define mmHDP_XDP_D2H_RSVD_10 0xc0a
629#define mmHDP_XDP_D2H_RSVD_11 0xc0b
630#define mmHDP_XDP_D2H_RSVD_12 0xc0c
631#define mmHDP_XDP_D2H_RSVD_13 0xc0d
632#define mmHDP_XDP_D2H_RSVD_14 0xc0e
633#define mmHDP_XDP_D2H_RSVD_15 0xc0f
634#define mmHDP_XDP_D2H_RSVD_16 0xc10
635#define mmHDP_XDP_D2H_RSVD_17 0xc11
636#define mmHDP_XDP_D2H_RSVD_18 0xc12
637#define mmHDP_XDP_D2H_RSVD_19 0xc13
638#define mmHDP_XDP_D2H_RSVD_20 0xc14
639#define mmHDP_XDP_D2H_RSVD_21 0xc15
640#define mmHDP_XDP_D2H_RSVD_22 0xc16
641#define mmHDP_XDP_D2H_RSVD_23 0xc17
642#define mmHDP_XDP_D2H_RSVD_24 0xc18
643#define mmHDP_XDP_D2H_RSVD_25 0xc19
644#define mmHDP_XDP_D2H_RSVD_26 0xc1a
645#define mmHDP_XDP_D2H_RSVD_27 0xc1b
646#define mmHDP_XDP_D2H_RSVD_28 0xc1c
647#define mmHDP_XDP_D2H_RSVD_29 0xc1d
648#define mmHDP_XDP_D2H_RSVD_30 0xc1e
649#define mmHDP_XDP_D2H_RSVD_31 0xc1f
650#define mmHDP_XDP_D2H_RSVD_32 0xc20
651#define mmHDP_XDP_D2H_RSVD_33 0xc21
652#define mmHDP_XDP_D2H_RSVD_34 0xc22
653#define mmHDP_XDP_DIRECT2HDP_LAST 0xc23
654#define mmHDP_XDP_P2P_BAR_CFG 0xc24
655#define mmHDP_XDP_P2P_MBX_OFFSET 0xc25
656#define mmHDP_XDP_P2P_MBX_ADDR0 0xc26
657#define mmHDP_XDP_P2P_MBX_ADDR1 0xc27
658#define mmHDP_XDP_P2P_MBX_ADDR2 0xc28
659#define mmHDP_XDP_P2P_MBX_ADDR3 0xc29
660#define mmHDP_XDP_P2P_MBX_ADDR4 0xc2a
661#define mmHDP_XDP_P2P_MBX_ADDR5 0xc2b
662#define mmHDP_XDP_P2P_MBX_ADDR6 0xc2c
663#define mmHDP_XDP_HDP_MBX_MC_CFG 0xc2d
664#define mmHDP_XDP_HDP_MC_CFG 0xc2e
665#define mmHDP_XDP_HST_CFG 0xc2f
666#define mmHDP_XDP_SID_CFG 0xc30
667#define mmHDP_XDP_HDP_IPH_CFG 0xc31
668#define mmHDP_XDP_SRBM_CFG 0xc32
669#define mmHDP_XDP_CGTT_BLK_CTRL 0xc33
670#define mmHDP_XDP_P2P_BAR0 0xc34
671#define mmHDP_XDP_P2P_BAR1 0xc35
672#define mmHDP_XDP_P2P_BAR2 0xc36
673#define mmHDP_XDP_P2P_BAR3 0xc37
674#define mmHDP_XDP_P2P_BAR4 0xc38
675#define mmHDP_XDP_P2P_BAR5 0xc39
676#define mmHDP_XDP_P2P_BAR6 0xc3a
677#define mmHDP_XDP_P2P_BAR7 0xc3b
678#define mmHDP_XDP_FLUSH_ARMED_STS 0xc3c
679#define mmHDP_XDP_FLUSH_CNTR0_STS 0xc3d
680#define mmHDP_XDP_BUSY_STS 0xc3e
681#define mmHDP_XDP_STICKY 0xc3f
682#define mmHDP_XDP_CHKN 0xc40
683#define mmHDP_XDP_DBG_ADDR 0xc41
684#define mmHDP_XDP_DBG_DATA 0xc42
685#define mmHDP_XDP_DBG_MASK 0xc43
686#define mmHDP_XDP_BARS_ADDR_39_36 0xc44
687
688#endif /* OSS_3_0_D_H */
689