1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _sdma0_4_1_DEFAULT_HEADER
22#define _sdma0_4_1_DEFAULT_HEADER
23
24
25// addressBlock: sdma0_sdma0dec
26#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
36#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff
37#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000
38#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000
39#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882
40#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc66880
41#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000
42#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000
43#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000
44#define mmSDMA0_POWER_CNTL_DEFAULT 0x4003c050
45#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100
46#define mmSDMA0_CNTL_DEFAULT 0x00000002
47#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07
48#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012
49#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012
50#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
51#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
52#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
53#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
54#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
55#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
56#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
57#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003
58#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
59#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
60#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
61#define mmSDMA0_FREEZE_DEFAULT 0x00000000
62#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
63#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
64#define mmSDMA_POWER_GATING_DEFAULT 0x00000000
65#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000
66#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000
67#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000
68#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
69#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
70#define mmSDMA0_ID_DEFAULT 0x00000001
71#define mmSDMA0_VERSION_DEFAULT 0x00000401
72#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
73#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
74#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
75#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
76#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
77#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
78#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019
79#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe
80#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff
81#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff
82#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600
83#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
84#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
85#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
86#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
87#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
88#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
89#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001
90#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0
91#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200
92#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
93#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005
94#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000
95#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
96#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
97#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
98#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
99#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
100#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
101#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
102#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
103#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000
104#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd
105#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000
106#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000
107#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000
108#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0
109#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000
110#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000
111#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000
112#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
113#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
114#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000
115#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
116#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
117#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
118#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
119#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
120#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000
121#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
122#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
123#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
124#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100
125#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000
126#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000
127#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000
128#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000
129#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000
130#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000
131#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005
132#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000
133#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000
134#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000
135#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000
136#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000
137#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000
138#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000
139#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000
140#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000
141#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000
142#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f
143#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
144#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
145#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000
146#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000
147#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000
148#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000
149#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000
150#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000
151#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000
152#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000
153#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000
154#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000
155#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000
156#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000
157#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000
158#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000
159#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000
160#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000
161#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000
162#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000
163#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000
164#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
165#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
166#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
167#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100
168#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000
169#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000
170#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000
171#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000
172#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000
173#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000
174#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004
175#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000
176#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000
177#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000
178#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000
179#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000
180#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000
181#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000
182#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000
183#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000
184#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f
185#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
186#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
187#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000
188#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000
189#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000
190#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000
191#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000
192#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000
193#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000
194#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000
195#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000
196#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000
197#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000
198#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000
199#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000
200#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000
201#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000
202#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000
203#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000
204#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000
205#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000
206#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000
207#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000
208#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000
209#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100
210#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000
211#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000
212#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000
213#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000
214#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000
215#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000
216#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004
217#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000
218#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000
219#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000
220#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000
221#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000
222#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000
223#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000
224#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000
225#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000
226#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f
227#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000
228#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000
229#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000
230#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000
231#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000
232#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000
233#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000
234#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000
235#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000
236#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000
237#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000
238#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000
239#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000
240#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000
241
242#endif
243

source code of linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h