1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _sdma1_4_0_OFFSET_HEADER
22#define _sdma1_4_0_OFFSET_HEADER
23
24
25
26// addressBlock: sdma1_sdma1dec
27// base address: 0x5180
28#define mmSDMA1_UCODE_ADDR 0x0000
29#define mmSDMA1_UCODE_ADDR_BASE_IDX 0
30#define mmSDMA1_UCODE_DATA 0x0001
31#define mmSDMA1_UCODE_DATA_BASE_IDX 0
32#define mmSDMA1_VM_CNTL 0x0004
33#define mmSDMA1_VM_CNTL_BASE_IDX 0
34#define mmSDMA1_VM_CTX_LO 0x0005
35#define mmSDMA1_VM_CTX_LO_BASE_IDX 0
36#define mmSDMA1_VM_CTX_HI 0x0006
37#define mmSDMA1_VM_CTX_HI_BASE_IDX 0
38#define mmSDMA1_ACTIVE_FCN_ID 0x0007
39#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0
40#define mmSDMA1_VM_CTX_CNTL 0x0008
41#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0
42#define mmSDMA1_VIRT_RESET_REQ 0x0009
43#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0
44#define mmSDMA1_VF_ENABLE 0x000a
45#define mmSDMA1_VF_ENABLE_BASE_IDX 0
46#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b
47#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0
48#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c
49#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0
50#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d
51#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0
52#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e
53#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0
54#define mmSDMA1_PUB_REG_TYPE0 0x000f
55#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0
56#define mmSDMA1_PUB_REG_TYPE1 0x0010
57#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0
58#define mmSDMA1_PUB_REG_TYPE2 0x0011
59#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0
60#define mmSDMA1_PUB_REG_TYPE3 0x0012
61#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0
62#define mmSDMA1_MMHUB_CNTL 0x0013
63#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0
64#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019
65#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0
66#define mmSDMA1_POWER_CNTL 0x001a
67#define mmSDMA1_POWER_CNTL_BASE_IDX 0
68#define mmSDMA1_CLK_CTRL 0x001b
69#define mmSDMA1_CLK_CTRL_BASE_IDX 0
70#define mmSDMA1_CNTL 0x001c
71#define mmSDMA1_CNTL_BASE_IDX 0
72#define mmSDMA1_CHICKEN_BITS 0x001d
73#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0
74#define mmSDMA1_GB_ADDR_CONFIG 0x001e
75#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0
76#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f
77#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0
78#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020
79#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0
80#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021
81#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
82#define mmSDMA1_RB_RPTR_FETCH 0x0022
83#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0
84#define mmSDMA1_IB_OFFSET_FETCH 0x0023
85#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0
86#define mmSDMA1_PROGRAM 0x0024
87#define mmSDMA1_PROGRAM_BASE_IDX 0
88#define mmSDMA1_STATUS_REG 0x0025
89#define mmSDMA1_STATUS_REG_BASE_IDX 0
90#define mmSDMA1_STATUS1_REG 0x0026
91#define mmSDMA1_STATUS1_REG_BASE_IDX 0
92#define mmSDMA1_RD_BURST_CNTL 0x0027
93#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0
94#define mmSDMA1_HBM_PAGE_CONFIG 0x0028
95#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0
96#define mmSDMA1_UCODE_CHECKSUM 0x0029
97#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0
98#define mmSDMA1_F32_CNTL 0x002a
99#define mmSDMA1_F32_CNTL_BASE_IDX 0
100#define mmSDMA1_FREEZE 0x002b
101#define mmSDMA1_FREEZE_BASE_IDX 0
102#define mmSDMA1_PHASE0_QUANTUM 0x002c
103#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0
104#define mmSDMA1_PHASE1_QUANTUM 0x002d
105#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0
106#define mmSDMA1_EDC_CONFIG 0x0032
107#define mmSDMA1_EDC_CONFIG_BASE_IDX 0
108#define mmSDMA1_BA_THRESHOLD 0x0033
109#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0
110#define mmSDMA1_ID 0x0034
111#define mmSDMA1_ID_BASE_IDX 0
112#define mmSDMA1_VERSION 0x0035
113#define mmSDMA1_VERSION_BASE_IDX 0
114#define mmSDMA1_EDC_COUNTER 0x0036
115#define mmSDMA1_EDC_COUNTER_BASE_IDX 0
116#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037
117#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0
118#define mmSDMA1_STATUS2_REG 0x0038
119#define mmSDMA1_STATUS2_REG_BASE_IDX 0
120#define mmSDMA1_ATOMIC_CNTL 0x0039
121#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0
122#define mmSDMA1_ATOMIC_PREOP_LO 0x003a
123#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0
124#define mmSDMA1_ATOMIC_PREOP_HI 0x003b
125#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0
126#define mmSDMA1_UTCL1_CNTL 0x003c
127#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0
128#define mmSDMA1_UTCL1_WATERMK 0x003d
129#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0
130#define mmSDMA1_UTCL1_RD_STATUS 0x003e
131#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0
132#define mmSDMA1_UTCL1_WR_STATUS 0x003f
133#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0
134#define mmSDMA1_UTCL1_INV0 0x0040
135#define mmSDMA1_UTCL1_INV0_BASE_IDX 0
136#define mmSDMA1_UTCL1_INV1 0x0041
137#define mmSDMA1_UTCL1_INV1_BASE_IDX 0
138#define mmSDMA1_UTCL1_INV2 0x0042
139#define mmSDMA1_UTCL1_INV2_BASE_IDX 0
140#define mmSDMA1_UTCL1_RD_XNACK0 0x0043
141#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0
142#define mmSDMA1_UTCL1_RD_XNACK1 0x0044
143#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0
144#define mmSDMA1_UTCL1_WR_XNACK0 0x0045
145#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0
146#define mmSDMA1_UTCL1_WR_XNACK1 0x0046
147#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0
148#define mmSDMA1_UTCL1_TIMEOUT 0x0047
149#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0
150#define mmSDMA1_UTCL1_PAGE 0x0048
151#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0
152#define mmSDMA1_POWER_CNTL_IDLE 0x0049
153#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0
154#define mmSDMA1_RELAX_ORDERING_LUT 0x004a
155#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0
156#define mmSDMA1_CHICKEN_BITS_2 0x004b
157#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0
158#define mmSDMA1_STATUS3_REG 0x004c
159#define mmSDMA1_STATUS3_REG_BASE_IDX 0
160#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d
161#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0
162#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e
163#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0
164#define mmSDMA1_PHASE2_QUANTUM 0x004f
165#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0
166#define mmSDMA1_ERROR_LOG 0x0050
167#define mmSDMA1_ERROR_LOG_BASE_IDX 0
168#define mmSDMA1_PUB_DUMMY_REG0 0x0051
169#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0
170#define mmSDMA1_PUB_DUMMY_REG1 0x0052
171#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0
172#define mmSDMA1_PUB_DUMMY_REG2 0x0053
173#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0
174#define mmSDMA1_PUB_DUMMY_REG3 0x0054
175#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0
176#define mmSDMA1_F32_COUNTER 0x0055
177#define mmSDMA1_F32_COUNTER_BASE_IDX 0
178#define mmSDMA1_UNBREAKABLE 0x0056
179#define mmSDMA1_UNBREAKABLE_BASE_IDX 0
180#define mmSDMA1_PERFMON_CNTL 0x0057
181#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0
182#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058
183#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0
184#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059
185#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0
186#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a
187#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0
188#define mmSDMA1_CRD_CNTL 0x005b
189#define mmSDMA1_CRD_CNTL_BASE_IDX 0
190#define mmSDMA1_MMHUB_TRUSTLVL 0x005c
191#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0
192#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d
193#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0
194#define mmSDMA1_ULV_CNTL 0x005e
195#define mmSDMA1_ULV_CNTL_BASE_IDX 0
196#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060
197#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0
198#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061
199#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0
200#define mmSDMA1_GFX_RB_CNTL 0x0080
201#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0
202#define mmSDMA1_GFX_RB_BASE 0x0081
203#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0
204#define mmSDMA1_GFX_RB_BASE_HI 0x0082
205#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0
206#define mmSDMA1_GFX_RB_RPTR 0x0083
207#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0
208#define mmSDMA1_GFX_RB_RPTR_HI 0x0084
209#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0
210#define mmSDMA1_GFX_RB_WPTR 0x0085
211#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0
212#define mmSDMA1_GFX_RB_WPTR_HI 0x0086
213#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0
214#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087
215#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0
216#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088
217#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0
218#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089
219#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0
220#define mmSDMA1_GFX_IB_CNTL 0x008a
221#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0
222#define mmSDMA1_GFX_IB_RPTR 0x008b
223#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0
224#define mmSDMA1_GFX_IB_OFFSET 0x008c
225#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0
226#define mmSDMA1_GFX_IB_BASE_LO 0x008d
227#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0
228#define mmSDMA1_GFX_IB_BASE_HI 0x008e
229#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0
230#define mmSDMA1_GFX_IB_SIZE 0x008f
231#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0
232#define mmSDMA1_GFX_SKIP_CNTL 0x0090
233#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0
234#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091
235#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0
236#define mmSDMA1_GFX_DOORBELL 0x0092
237#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0
238#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093
239#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0
240#define mmSDMA1_GFX_STATUS 0x00a8
241#define mmSDMA1_GFX_STATUS_BASE_IDX 0
242#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9
243#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0
244#define mmSDMA1_GFX_WATERMARK 0x00aa
245#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0
246#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab
247#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0
248#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac
249#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0
250#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad
251#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0
252#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af
253#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0
254#define mmSDMA1_GFX_PREEMPT 0x00b0
255#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0
256#define mmSDMA1_GFX_DUMMY_REG 0x00b1
257#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0
258#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
259#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
260#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
261#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
262#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4
263#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0
264#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5
265#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0
266#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0
267#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0
268#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1
269#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0
270#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2
271#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0
272#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3
273#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0
274#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4
275#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0
276#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5
277#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0
278#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6
279#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0
280#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7
281#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0
282#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8
283#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0
284#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9
285#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0
286#define mmSDMA1_PAGE_RB_CNTL 0x00e0
287#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0
288#define mmSDMA1_PAGE_RB_BASE 0x00e1
289#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0
290#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2
291#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0
292#define mmSDMA1_PAGE_RB_RPTR 0x00e3
293#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0
294#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4
295#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0
296#define mmSDMA1_PAGE_RB_WPTR 0x00e5
297#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0
298#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6
299#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0
300#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7
301#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0
302#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8
303#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0
304#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9
305#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0
306#define mmSDMA1_PAGE_IB_CNTL 0x00ea
307#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0
308#define mmSDMA1_PAGE_IB_RPTR 0x00eb
309#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0
310#define mmSDMA1_PAGE_IB_OFFSET 0x00ec
311#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0
312#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed
313#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0
314#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee
315#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0
316#define mmSDMA1_PAGE_IB_SIZE 0x00ef
317#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0
318#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0
319#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0
320#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1
321#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0
322#define mmSDMA1_PAGE_DOORBELL 0x00f2
323#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0
324#define mmSDMA1_PAGE_STATUS 0x0108
325#define mmSDMA1_PAGE_STATUS_BASE_IDX 0
326#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109
327#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0
328#define mmSDMA1_PAGE_WATERMARK 0x010a
329#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0
330#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b
331#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0
332#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c
333#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0
334#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d
335#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0
336#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f
337#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0
338#define mmSDMA1_PAGE_PREEMPT 0x0110
339#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0
340#define mmSDMA1_PAGE_DUMMY_REG 0x0111
341#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0
342#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112
343#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
344#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
345#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
346#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114
347#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0
348#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115
349#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0
350#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120
351#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0
352#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121
353#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0
354#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122
355#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0
356#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123
357#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0
358#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124
359#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0
360#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125
361#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0
362#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126
363#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0
364#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127
365#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0
366#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128
367#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0
368#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129
369#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0
370#define mmSDMA1_RLC0_RB_CNTL 0x0140
371#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0
372#define mmSDMA1_RLC0_RB_BASE 0x0141
373#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0
374#define mmSDMA1_RLC0_RB_BASE_HI 0x0142
375#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0
376#define mmSDMA1_RLC0_RB_RPTR 0x0143
377#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0
378#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144
379#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0
380#define mmSDMA1_RLC0_RB_WPTR 0x0145
381#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0
382#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146
383#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0
384#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147
385#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0
386#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148
387#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0
388#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149
389#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0
390#define mmSDMA1_RLC0_IB_CNTL 0x014a
391#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0
392#define mmSDMA1_RLC0_IB_RPTR 0x014b
393#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0
394#define mmSDMA1_RLC0_IB_OFFSET 0x014c
395#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0
396#define mmSDMA1_RLC0_IB_BASE_LO 0x014d
397#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0
398#define mmSDMA1_RLC0_IB_BASE_HI 0x014e
399#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0
400#define mmSDMA1_RLC0_IB_SIZE 0x014f
401#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0
402#define mmSDMA1_RLC0_SKIP_CNTL 0x0150
403#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0
404#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151
405#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0
406#define mmSDMA1_RLC0_DOORBELL 0x0152
407#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0
408#define mmSDMA1_RLC0_STATUS 0x0168
409#define mmSDMA1_RLC0_STATUS_BASE_IDX 0
410#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169
411#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0
412#define mmSDMA1_RLC0_WATERMARK 0x016a
413#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0
414#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b
415#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0
416#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c
417#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0
418#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d
419#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0
420#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f
421#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0
422#define mmSDMA1_RLC0_PREEMPT 0x0170
423#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0
424#define mmSDMA1_RLC0_DUMMY_REG 0x0171
425#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0
426#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172
427#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
428#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173
429#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
430#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174
431#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0
432#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175
433#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0
434#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180
435#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0
436#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181
437#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0
438#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182
439#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0
440#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183
441#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0
442#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184
443#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0
444#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185
445#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0
446#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186
447#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0
448#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187
449#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0
450#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188
451#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0
452#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189
453#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0
454#define mmSDMA1_RLC1_RB_CNTL 0x01a0
455#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0
456#define mmSDMA1_RLC1_RB_BASE 0x01a1
457#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0
458#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2
459#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0
460#define mmSDMA1_RLC1_RB_RPTR 0x01a3
461#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0
462#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4
463#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0
464#define mmSDMA1_RLC1_RB_WPTR 0x01a5
465#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0
466#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6
467#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0
468#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7
469#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0
470#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8
471#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0
472#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9
473#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0
474#define mmSDMA1_RLC1_IB_CNTL 0x01aa
475#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0
476#define mmSDMA1_RLC1_IB_RPTR 0x01ab
477#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0
478#define mmSDMA1_RLC1_IB_OFFSET 0x01ac
479#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0
480#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad
481#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0
482#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae
483#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0
484#define mmSDMA1_RLC1_IB_SIZE 0x01af
485#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0
486#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0
487#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0
488#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1
489#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0
490#define mmSDMA1_RLC1_DOORBELL 0x01b2
491#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0
492#define mmSDMA1_RLC1_STATUS 0x01c8
493#define mmSDMA1_RLC1_STATUS_BASE_IDX 0
494#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9
495#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0
496#define mmSDMA1_RLC1_WATERMARK 0x01ca
497#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0
498#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb
499#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0
500#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc
501#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0
502#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd
503#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0
504#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf
505#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0
506#define mmSDMA1_RLC1_PREEMPT 0x01d0
507#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0
508#define mmSDMA1_RLC1_DUMMY_REG 0x01d1
509#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0
510#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2
511#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0
512#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3
513#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0
514#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4
515#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0
516#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5
517#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0
518#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0
519#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0
520#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1
521#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0
522#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2
523#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0
524#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3
525#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0
526#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4
527#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0
528#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5
529#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0
530#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6
531#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0
532#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7
533#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0
534#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8
535#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0
536#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9
537#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0
538
539#endif
540

source code of linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h