1/*
2 * SMU_7_0_1 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef SMU_7_0_1_SH_MASK_H
25#define SMU_7_0_1_SH_MASK_H
26
27#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
37#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
38#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
39#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
40#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
41#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
42#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
43#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
44#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
45#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
46#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
47#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
48#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
49#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
50#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
51#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
52#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
53#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
54#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
55#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
56#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
57#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
58#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
59#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
60#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
61#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
62#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
63#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
64#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
65#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
66#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
67#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
68#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
69#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
70#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
71#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
72#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
73#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
74#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
75#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
76#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
77#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
78#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
79#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
80#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
81#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
82#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
83#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
84#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
85#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
86#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
87#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
88#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
89#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
90#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
91#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
92#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
93#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
94#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
95#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
96#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
97#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
98#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
99#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
100#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
101#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
102#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
103#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
104#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
105#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
106#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
107#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
108#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
109#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
110#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
111#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
112#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
113#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
114#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
115#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
116#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
117#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
118#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
119#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
120#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
121#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
122#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
123#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
124#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
125#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
126#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
127#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
128#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
129#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
130#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
131#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
132#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
133#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
134#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
135#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
136#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
137#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
138#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
139#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
140#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
141#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
142#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
143#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
144#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
145#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
146#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
147#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
148#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
149#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
150#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
151#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
152#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
153#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fe00
154#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
155#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
156#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
157#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
158#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
159#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
160#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
161#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
162#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
163#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
164#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
165#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
166#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
167#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
168#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
169#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
170#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
171#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
172#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
173#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
174#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
175#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
176#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
177#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
178#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
179#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
180#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
181#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
182#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
183#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
184#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
185#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
186#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
187#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
188#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
189#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
190#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
191#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
192#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
193#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
194#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
195#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
196#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
197#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
198#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
199#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
200#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
201#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
202#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
203#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
204#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
205#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
206#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
207#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
208#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
209#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
210#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
211#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
212#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
213#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
214#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
215#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
216#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
217#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
218#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
219#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
220#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
221#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
222#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
223#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
224#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
225#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
226#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
227#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
228#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
229#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
230#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
231#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
232#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
233#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
234#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
235#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
236#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
237#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
238#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
239#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
240#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
241#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
242#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
243#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
244#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
245#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
246#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
247#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
248#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
249#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
250#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
251#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
252#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
253#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
254#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
255#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
256#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
257#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
258#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
259#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
260#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
261#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
262#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
263#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
264#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
265#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
266#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
267#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
268#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
269#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
270#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
271#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
272#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
273#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
274#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
275#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
276#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
277#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
278#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
279#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
280#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
281#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
282#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
283#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
284#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
285#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
286#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
287#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
288#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
289#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
290#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
291#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
292#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
293#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
294#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
295#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
296#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
297#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
298#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
299#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
300#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
301#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
302#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
303#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
304#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
305#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
306#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
307#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
308#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
309#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
310#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
311#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
312#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
313#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
314#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
315#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
316#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
317#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
318#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
319#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
320#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
321#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
322#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
323#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
324#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
325#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
326#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
327#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
328#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
329#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
330#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
331#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
332#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
333#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
334#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
335#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
336#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
337#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
338#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
339#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
340#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
341#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
342#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
343#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
344#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
345#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
346#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
347#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
348#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
349#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
350#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
351#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
352#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
353#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
354#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
355#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
356#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
357#define SMC_RESP_0__SMC_RESP_MASK 0xffff
358#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
359#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
360#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
361#define SMC_RESP_1__SMC_RESP_MASK 0xffff
362#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
363#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
364#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
365#define SMC_RESP_2__SMC_RESP_MASK 0xffff
366#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
367#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
368#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
369#define SMC_RESP_3__SMC_RESP_MASK 0xffff
370#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
371#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
372#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
373#define SMC_RESP_4__SMC_RESP_MASK 0xffff
374#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
375#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
376#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
377#define SMC_RESP_5__SMC_RESP_MASK 0xffff
378#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
379#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
380#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
381#define SMC_RESP_6__SMC_RESP_MASK 0xffff
382#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
383#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
384#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
385#define SMC_RESP_7__SMC_RESP_MASK 0xffff
386#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
387#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
388#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
389#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
390#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
391#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
392#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
393#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
394#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
395#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
396#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
397#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
398#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
399#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
400#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
401#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
402#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
403#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
404#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
405#define SMC_RESP_8__SMC_RESP_MASK 0xffff
406#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
407#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
408#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
409#define SMC_RESP_9__SMC_RESP_MASK 0xffff
410#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
411#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
412#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
413#define SMC_RESP_10__SMC_RESP_MASK 0xffff
414#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
415#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
416#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
417#define SMC_RESP_11__SMC_RESP_MASK 0xffff
418#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
419#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
420#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
421#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
422#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
423#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
424#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
425#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
426#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
427#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
428#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
429#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
430#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
431#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
432#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
433#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
434#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
435#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
436#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
437#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
438#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
439#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
440#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
441#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
442#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
443#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
444#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
445#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
446#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
447#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
448#define SMC_PC_C__smc_pc_c__SHIFT 0x0
449#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
450#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
451#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
452#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
453#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
454#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
455#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
456#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
457#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
458#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
459#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
460#define GPIOPAD_A__GPIO_A__SHIFT 0x0
461#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
462#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
463#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
464#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
465#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
466#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
467#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
468#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
469#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
470#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
471#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
472#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
473#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
474#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
475#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
476#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
477#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
478#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
479#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
480#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
481#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
482#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
483#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
484#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
485#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
486#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
487#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
488#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
489#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
490#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
491#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
492#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
493#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
494#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
495#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
496#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
497#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
498#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
499#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
500#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
501#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
502#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
503#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
504#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
505#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
506#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
507#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
508#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
509#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
510#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
511#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
512#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
513#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
514#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
515#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
516#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
517#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
518#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
519#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
520#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
521#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
522#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
523#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
524#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
525#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
526#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
527#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
528#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
529#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
530#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
531#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
532#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
533#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
534#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
535#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
536#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
537#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
538#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
539#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
540#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
541#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
542#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
543#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
544#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
545#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
546#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
547#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
548#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
549#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
550#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
551#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
552#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
553#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
554#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
555#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
556#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
557#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
558#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
559#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
560#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
561#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
562#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
563#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
564#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
565#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
566#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
567#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
568#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
569#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
570#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
571#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
572#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
573#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
574#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
575#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
576#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
577#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
578#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
579#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
580#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
581#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
582#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
583#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
584#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
585#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
586#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
587#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
588#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
589#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
590#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
591#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
592#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
593#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
594#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
595#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
596#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
597#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
598#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
599#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
600#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
601#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
602#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
603#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
604#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
605#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
606#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
607#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
608#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
609#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
610#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
611#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
612#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
613#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
614#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
615#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
616#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
617#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
618#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
619#define CG_FPS_CNT__FPS_CNT_MASK 0xff
620#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
621#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
622#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
623#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
624#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
625#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
626#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
627#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
628#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
629#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
630#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
631#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
632#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
633#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
634#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
635#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
636#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
637#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
638#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
639#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
640#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
641#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
642#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
643#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
644#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
645#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
646#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
647#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
648#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
649#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
650#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
651#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
652#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
653#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
654#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
655#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
656#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
657#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
658#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
659#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
660#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
661#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
662#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
663#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
664#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
665#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
666#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
667#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
668#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
669#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
670#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
671#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
672#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
673#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
674#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
675#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
676#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
677#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
678#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
679#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
680#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
681#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
682#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
683#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
684#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
685#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
686#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
687#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
688#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
689#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
690#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
691#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
692#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
693#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
694#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
695#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
696#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
697#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
698#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
699#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
700#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
701#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
702#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
703#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
704#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
705#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
706#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
707#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
708#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
709#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
710#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
711#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
712#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
713#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfe000000
714#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
715#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
716#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
717#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
718#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
719#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
720#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
721#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
722#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
723#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
724#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
725#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
726#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
727#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
728#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
729#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
730#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
731#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
732#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
733#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
734#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
735#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
736#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
737#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
738#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
739#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
740#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
741#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
742#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
743#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
744#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
745#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
746#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
747#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
748#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
749#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
750#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
751#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
752#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
753#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
754#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
755#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
756#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
757#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
758#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
759#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
760#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
761#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
762#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
763#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
764#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
765#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
766#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
767#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
768#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
769#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
770#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
771#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
772#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
773#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
774#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
775#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
776#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
777#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
778#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
779#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
780#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
781#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
782#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
783#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
784#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
785#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
786#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
787#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
788#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
789#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
790#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
791#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
792#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
793#define SMU_STATUS__SMU_DONE_MASK 0x1
794#define SMU_STATUS__SMU_DONE__SHIFT 0x0
795#define SMU_STATUS__SMU_PASS_MASK 0x2
796#define SMU_STATUS__SMU_PASS__SHIFT 0x1
797#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
798#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
799#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
800#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
801#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
802#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
803#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
804#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
805#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
806#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
807#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
808#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
809#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
810#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
811#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
812#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
813#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
814#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
815#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
816#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
817#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
818#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
819#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
820#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
821#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
822#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
823#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
824#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
825#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
826#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
827#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
828#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
829#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
830#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
831#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
832#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
833#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
834#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
835#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
836#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
837#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
838#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
839#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
840#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
841#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
842#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
843#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
844#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
845#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
846#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
847#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
848#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
849#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
850#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
851#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
852#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
853#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
854#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
855#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
856#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
857#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
858#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
859#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
860#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
861#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
862#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
863#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
864#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
865#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
866#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
867#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
868#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
869#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
870#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
871#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
872#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
873#define DPM_TABLE_29__SmioMaskVddcVid_MASK 0xffffffff
874#define DPM_TABLE_29__SmioMaskVddcVid__SHIFT 0x0
875#define DPM_TABLE_30__SmioMaskVddcPhase_MASK 0xffffffff
876#define DPM_TABLE_30__SmioMaskVddcPhase__SHIFT 0x0
877#define DPM_TABLE_31__SmioMaskVddciVid_MASK 0xffffffff
878#define DPM_TABLE_31__SmioMaskVddciVid__SHIFT 0x0
879#define DPM_TABLE_32__SmioMaskMvddVid_MASK 0xffffffff
880#define DPM_TABLE_32__SmioMaskMvddVid__SHIFT 0x0
881#define DPM_TABLE_33__VddcLevelCount_MASK 0xffffffff
882#define DPM_TABLE_33__VddcLevelCount__SHIFT 0x0
883#define DPM_TABLE_34__VddciLevelCount_MASK 0xffffffff
884#define DPM_TABLE_34__VddciLevelCount__SHIFT 0x0
885#define DPM_TABLE_35__MvddLevelCount_MASK 0xffffffff
886#define DPM_TABLE_35__MvddLevelCount__SHIFT 0x0
887#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd_MASK 0xffff
888#define DPM_TABLE_36__VddcLevel_0_StdVoltageHiSidd__SHIFT 0x0
889#define DPM_TABLE_36__VddcLevel_0_Voltage_MASK 0xffff0000
890#define DPM_TABLE_36__VddcLevel_0_Voltage__SHIFT 0x10
891#define DPM_TABLE_37__VddcLevel_0_padding_MASK 0xff
892#define DPM_TABLE_37__VddcLevel_0_padding__SHIFT 0x0
893#define DPM_TABLE_37__VddcLevel_0_Smio_MASK 0xff00
894#define DPM_TABLE_37__VddcLevel_0_Smio__SHIFT 0x8
895#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd_MASK 0xffff0000
896#define DPM_TABLE_37__VddcLevel_0_StdVoltageLoSidd__SHIFT 0x10
897#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd_MASK 0xffff
898#define DPM_TABLE_38__VddcLevel_1_StdVoltageHiSidd__SHIFT 0x0
899#define DPM_TABLE_38__VddcLevel_1_Voltage_MASK 0xffff0000
900#define DPM_TABLE_38__VddcLevel_1_Voltage__SHIFT 0x10
901#define DPM_TABLE_39__VddcLevel_1_padding_MASK 0xff
902#define DPM_TABLE_39__VddcLevel_1_padding__SHIFT 0x0
903#define DPM_TABLE_39__VddcLevel_1_Smio_MASK 0xff00
904#define DPM_TABLE_39__VddcLevel_1_Smio__SHIFT 0x8
905#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd_MASK 0xffff0000
906#define DPM_TABLE_39__VddcLevel_1_StdVoltageLoSidd__SHIFT 0x10
907#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd_MASK 0xffff
908#define DPM_TABLE_40__VddcLevel_2_StdVoltageHiSidd__SHIFT 0x0
909#define DPM_TABLE_40__VddcLevel_2_Voltage_MASK 0xffff0000
910#define DPM_TABLE_40__VddcLevel_2_Voltage__SHIFT 0x10
911#define DPM_TABLE_41__VddcLevel_2_padding_MASK 0xff
912#define DPM_TABLE_41__VddcLevel_2_padding__SHIFT 0x0
913#define DPM_TABLE_41__VddcLevel_2_Smio_MASK 0xff00
914#define DPM_TABLE_41__VddcLevel_2_Smio__SHIFT 0x8
915#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd_MASK 0xffff0000
916#define DPM_TABLE_41__VddcLevel_2_StdVoltageLoSidd__SHIFT 0x10
917#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd_MASK 0xffff
918#define DPM_TABLE_42__VddcLevel_3_StdVoltageHiSidd__SHIFT 0x0
919#define DPM_TABLE_42__VddcLevel_3_Voltage_MASK 0xffff0000
920#define DPM_TABLE_42__VddcLevel_3_Voltage__SHIFT 0x10
921#define DPM_TABLE_43__VddcLevel_3_padding_MASK 0xff
922#define DPM_TABLE_43__VddcLevel_3_padding__SHIFT 0x0
923#define DPM_TABLE_43__VddcLevel_3_Smio_MASK 0xff00
924#define DPM_TABLE_43__VddcLevel_3_Smio__SHIFT 0x8
925#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd_MASK 0xffff0000
926#define DPM_TABLE_43__VddcLevel_3_StdVoltageLoSidd__SHIFT 0x10
927#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd_MASK 0xffff
928#define DPM_TABLE_44__VddcLevel_4_StdVoltageHiSidd__SHIFT 0x0
929#define DPM_TABLE_44__VddcLevel_4_Voltage_MASK 0xffff0000
930#define DPM_TABLE_44__VddcLevel_4_Voltage__SHIFT 0x10
931#define DPM_TABLE_45__VddcLevel_4_padding_MASK 0xff
932#define DPM_TABLE_45__VddcLevel_4_padding__SHIFT 0x0
933#define DPM_TABLE_45__VddcLevel_4_Smio_MASK 0xff00
934#define DPM_TABLE_45__VddcLevel_4_Smio__SHIFT 0x8
935#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd_MASK 0xffff0000
936#define DPM_TABLE_45__VddcLevel_4_StdVoltageLoSidd__SHIFT 0x10
937#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd_MASK 0xffff
938#define DPM_TABLE_46__VddcLevel_5_StdVoltageHiSidd__SHIFT 0x0
939#define DPM_TABLE_46__VddcLevel_5_Voltage_MASK 0xffff0000
940#define DPM_TABLE_46__VddcLevel_5_Voltage__SHIFT 0x10
941#define DPM_TABLE_47__VddcLevel_5_padding_MASK 0xff
942#define DPM_TABLE_47__VddcLevel_5_padding__SHIFT 0x0
943#define DPM_TABLE_47__VddcLevel_5_Smio_MASK 0xff00
944#define DPM_TABLE_47__VddcLevel_5_Smio__SHIFT 0x8
945#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd_MASK 0xffff0000
946#define DPM_TABLE_47__VddcLevel_5_StdVoltageLoSidd__SHIFT 0x10
947#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd_MASK 0xffff
948#define DPM_TABLE_48__VddcLevel_6_StdVoltageHiSidd__SHIFT 0x0
949#define DPM_TABLE_48__VddcLevel_6_Voltage_MASK 0xffff0000
950#define DPM_TABLE_48__VddcLevel_6_Voltage__SHIFT 0x10
951#define DPM_TABLE_49__VddcLevel_6_padding_MASK 0xff
952#define DPM_TABLE_49__VddcLevel_6_padding__SHIFT 0x0
953#define DPM_TABLE_49__VddcLevel_6_Smio_MASK 0xff00
954#define DPM_TABLE_49__VddcLevel_6_Smio__SHIFT 0x8
955#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd_MASK 0xffff0000
956#define DPM_TABLE_49__VddcLevel_6_StdVoltageLoSidd__SHIFT 0x10
957#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd_MASK 0xffff
958#define DPM_TABLE_50__VddcLevel_7_StdVoltageHiSidd__SHIFT 0x0
959#define DPM_TABLE_50__VddcLevel_7_Voltage_MASK 0xffff0000
960#define DPM_TABLE_50__VddcLevel_7_Voltage__SHIFT 0x10
961#define DPM_TABLE_51__VddcLevel_7_padding_MASK 0xff
962#define DPM_TABLE_51__VddcLevel_7_padding__SHIFT 0x0
963#define DPM_TABLE_51__VddcLevel_7_Smio_MASK 0xff00
964#define DPM_TABLE_51__VddcLevel_7_Smio__SHIFT 0x8
965#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd_MASK 0xffff0000
966#define DPM_TABLE_51__VddcLevel_7_StdVoltageLoSidd__SHIFT 0x10
967#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd_MASK 0xffff
968#define DPM_TABLE_52__VddciLevel_0_StdVoltageHiSidd__SHIFT 0x0
969#define DPM_TABLE_52__VddciLevel_0_Voltage_MASK 0xffff0000
970#define DPM_TABLE_52__VddciLevel_0_Voltage__SHIFT 0x10
971#define DPM_TABLE_53__VddciLevel_0_padding_MASK 0xff
972#define DPM_TABLE_53__VddciLevel_0_padding__SHIFT 0x0
973#define DPM_TABLE_53__VddciLevel_0_Smio_MASK 0xff00
974#define DPM_TABLE_53__VddciLevel_0_Smio__SHIFT 0x8
975#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd_MASK 0xffff0000
976#define DPM_TABLE_53__VddciLevel_0_StdVoltageLoSidd__SHIFT 0x10
977#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd_MASK 0xffff
978#define DPM_TABLE_54__VddciLevel_1_StdVoltageHiSidd__SHIFT 0x0
979#define DPM_TABLE_54__VddciLevel_1_Voltage_MASK 0xffff0000
980#define DPM_TABLE_54__VddciLevel_1_Voltage__SHIFT 0x10
981#define DPM_TABLE_55__VddciLevel_1_padding_MASK 0xff
982#define DPM_TABLE_55__VddciLevel_1_padding__SHIFT 0x0
983#define DPM_TABLE_55__VddciLevel_1_Smio_MASK 0xff00
984#define DPM_TABLE_55__VddciLevel_1_Smio__SHIFT 0x8
985#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd_MASK 0xffff0000
986#define DPM_TABLE_55__VddciLevel_1_StdVoltageLoSidd__SHIFT 0x10
987#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd_MASK 0xffff
988#define DPM_TABLE_56__VddciLevel_2_StdVoltageHiSidd__SHIFT 0x0
989#define DPM_TABLE_56__VddciLevel_2_Voltage_MASK 0xffff0000
990#define DPM_TABLE_56__VddciLevel_2_Voltage__SHIFT 0x10
991#define DPM_TABLE_57__VddciLevel_2_padding_MASK 0xff
992#define DPM_TABLE_57__VddciLevel_2_padding__SHIFT 0x0
993#define DPM_TABLE_57__VddciLevel_2_Smio_MASK 0xff00
994#define DPM_TABLE_57__VddciLevel_2_Smio__SHIFT 0x8
995#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd_MASK 0xffff0000
996#define DPM_TABLE_57__VddciLevel_2_StdVoltageLoSidd__SHIFT 0x10
997#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd_MASK 0xffff
998#define DPM_TABLE_58__VddciLevel_3_StdVoltageHiSidd__SHIFT 0x0
999#define DPM_TABLE_58__VddciLevel_3_Voltage_MASK 0xffff0000
1000#define DPM_TABLE_58__VddciLevel_3_Voltage__SHIFT 0x10
1001#define DPM_TABLE_59__VddciLevel_3_padding_MASK 0xff
1002#define DPM_TABLE_59__VddciLevel_3_padding__SHIFT 0x0
1003#define DPM_TABLE_59__VddciLevel_3_Smio_MASK 0xff00
1004#define DPM_TABLE_59__VddciLevel_3_Smio__SHIFT 0x8
1005#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd_MASK 0xffff0000
1006#define DPM_TABLE_59__VddciLevel_3_StdVoltageLoSidd__SHIFT 0x10
1007#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd_MASK 0xffff
1008#define DPM_TABLE_60__MvddLevel_0_StdVoltageHiSidd__SHIFT 0x0
1009#define DPM_TABLE_60__MvddLevel_0_Voltage_MASK 0xffff0000
1010#define DPM_TABLE_60__MvddLevel_0_Voltage__SHIFT 0x10
1011#define DPM_TABLE_61__MvddLevel_0_padding_MASK 0xff
1012#define DPM_TABLE_61__MvddLevel_0_padding__SHIFT 0x0
1013#define DPM_TABLE_61__MvddLevel_0_Smio_MASK 0xff00
1014#define DPM_TABLE_61__MvddLevel_0_Smio__SHIFT 0x8
1015#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd_MASK 0xffff0000
1016#define DPM_TABLE_61__MvddLevel_0_StdVoltageLoSidd__SHIFT 0x10
1017#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd_MASK 0xffff
1018#define DPM_TABLE_62__MvddLevel_1_StdVoltageHiSidd__SHIFT 0x0
1019#define DPM_TABLE_62__MvddLevel_1_Voltage_MASK 0xffff0000
1020#define DPM_TABLE_62__MvddLevel_1_Voltage__SHIFT 0x10
1021#define DPM_TABLE_63__MvddLevel_1_padding_MASK 0xff
1022#define DPM_TABLE_63__MvddLevel_1_padding__SHIFT 0x0
1023#define DPM_TABLE_63__MvddLevel_1_Smio_MASK 0xff00
1024#define DPM_TABLE_63__MvddLevel_1_Smio__SHIFT 0x8
1025#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd_MASK 0xffff0000
1026#define DPM_TABLE_63__MvddLevel_1_StdVoltageLoSidd__SHIFT 0x10
1027#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd_MASK 0xffff
1028#define DPM_TABLE_64__MvddLevel_2_StdVoltageHiSidd__SHIFT 0x0
1029#define DPM_TABLE_64__MvddLevel_2_Voltage_MASK 0xffff0000
1030#define DPM_TABLE_64__MvddLevel_2_Voltage__SHIFT 0x10
1031#define DPM_TABLE_65__MvddLevel_2_padding_MASK 0xff
1032#define DPM_TABLE_65__MvddLevel_2_padding__SHIFT 0x0
1033#define DPM_TABLE_65__MvddLevel_2_Smio_MASK 0xff00
1034#define DPM_TABLE_65__MvddLevel_2_Smio__SHIFT 0x8
1035#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd_MASK 0xffff0000
1036#define DPM_TABLE_65__MvddLevel_2_StdVoltageLoSidd__SHIFT 0x10
1037#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd_MASK 0xffff
1038#define DPM_TABLE_66__MvddLevel_3_StdVoltageHiSidd__SHIFT 0x0
1039#define DPM_TABLE_66__MvddLevel_3_Voltage_MASK 0xffff0000
1040#define DPM_TABLE_66__MvddLevel_3_Voltage__SHIFT 0x10
1041#define DPM_TABLE_67__MvddLevel_3_padding_MASK 0xff
1042#define DPM_TABLE_67__MvddLevel_3_padding__SHIFT 0x0
1043#define DPM_TABLE_67__MvddLevel_3_Smio_MASK 0xff00
1044#define DPM_TABLE_67__MvddLevel_3_Smio__SHIFT 0x8
1045#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd_MASK 0xffff0000
1046#define DPM_TABLE_67__MvddLevel_3_StdVoltageLoSidd__SHIFT 0x10
1047#define DPM_TABLE_68__UvdLevelCount_MASK 0xff
1048#define DPM_TABLE_68__UvdLevelCount__SHIFT 0x0
1049#define DPM_TABLE_68__LinkLevelCount_MASK 0xff00
1050#define DPM_TABLE_68__LinkLevelCount__SHIFT 0x8
1051#define DPM_TABLE_68__MemoryDpmLevelCount_MASK 0xff0000
1052#define DPM_TABLE_68__MemoryDpmLevelCount__SHIFT 0x10
1053#define DPM_TABLE_68__GraphicsDpmLevelCount_MASK 0xff000000
1054#define DPM_TABLE_68__GraphicsDpmLevelCount__SHIFT 0x18
1055#define DPM_TABLE_69__padding2_MASK 0xff
1056#define DPM_TABLE_69__padding2__SHIFT 0x0
1057#define DPM_TABLE_69__SamuLevelCount_MASK 0xff00
1058#define DPM_TABLE_69__SamuLevelCount__SHIFT 0x8
1059#define DPM_TABLE_69__AcpLevelCount_MASK 0xff0000
1060#define DPM_TABLE_69__AcpLevelCount__SHIFT 0x10
1061#define DPM_TABLE_69__VceLevelCount_MASK 0xff000000
1062#define DPM_TABLE_69__VceLevelCount__SHIFT 0x18
1063#define DPM_TABLE_70__Reserved_0_MASK 0xffffffff
1064#define DPM_TABLE_70__Reserved_0__SHIFT 0x0
1065#define DPM_TABLE_71__Reserved_1_MASK 0xffffffff
1066#define DPM_TABLE_71__Reserved_1__SHIFT 0x0
1067#define DPM_TABLE_72__Reserved_2_MASK 0xffffffff
1068#define DPM_TABLE_72__Reserved_2__SHIFT 0x0
1069#define DPM_TABLE_73__Reserved_3_MASK 0xffffffff
1070#define DPM_TABLE_73__Reserved_3__SHIFT 0x0
1071#define DPM_TABLE_74__Reserved_4_MASK 0xffffffff
1072#define DPM_TABLE_74__Reserved_4__SHIFT 0x0
1073#define DPM_TABLE_75__GraphicsLevel_0_Flags_MASK 0xffffffff
1074#define DPM_TABLE_75__GraphicsLevel_0_Flags__SHIFT 0x0
1075#define DPM_TABLE_76__GraphicsLevel_0_MinVddc_MASK 0xffffffff
1076#define DPM_TABLE_76__GraphicsLevel_0_MinVddc__SHIFT 0x0
1077#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases_MASK 0xffffffff
1078#define DPM_TABLE_77__GraphicsLevel_0_MinVddcPhases__SHIFT 0x0
1079#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
1080#define DPM_TABLE_78__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
1081#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel_MASK 0xffff
1082#define DPM_TABLE_79__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
1083#define DPM_TABLE_79__GraphicsLevel_0_padding1_1_MASK 0xff0000
1084#define DPM_TABLE_79__GraphicsLevel_0_padding1_1__SHIFT 0x10
1085#define DPM_TABLE_79__GraphicsLevel_0_padding1_0_MASK 0xff000000
1086#define DPM_TABLE_79__GraphicsLevel_0_padding1_0__SHIFT 0x18
1087#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
1088#define DPM_TABLE_80__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
1089#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
1090#define DPM_TABLE_81__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
1091#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
1092#define DPM_TABLE_82__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
1093#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
1094#define DPM_TABLE_83__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
1095#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
1096#define DPM_TABLE_84__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
1097#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
1098#define DPM_TABLE_85__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
1099#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
1100#define DPM_TABLE_86__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
1101#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
1102#define DPM_TABLE_86__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
1103#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
1104#define DPM_TABLE_86__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
1105#define DPM_TABLE_86__GraphicsLevel_0_SclkDid_MASK 0xff000000
1106#define DPM_TABLE_86__GraphicsLevel_0_SclkDid__SHIFT 0x18
1107#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle_MASK 0xff
1108#define DPM_TABLE_87__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
1109#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
1110#define DPM_TABLE_87__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
1111#define DPM_TABLE_87__GraphicsLevel_0_DownHyst_MASK 0xff0000
1112#define DPM_TABLE_87__GraphicsLevel_0_DownHyst__SHIFT 0x10
1113#define DPM_TABLE_87__GraphicsLevel_0_UpHyst_MASK 0xff000000
1114#define DPM_TABLE_87__GraphicsLevel_0_UpHyst__SHIFT 0x18
1115#define DPM_TABLE_88__GraphicsLevel_0_padding_2_MASK 0xff
1116#define DPM_TABLE_88__GraphicsLevel_0_padding_2__SHIFT 0x0
1117#define DPM_TABLE_88__GraphicsLevel_0_padding_1_MASK 0xff00
1118#define DPM_TABLE_88__GraphicsLevel_0_padding_1__SHIFT 0x8
1119#define DPM_TABLE_88__GraphicsLevel_0_padding_0_MASK 0xff0000
1120#define DPM_TABLE_88__GraphicsLevel_0_padding_0__SHIFT 0x10
1121#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId_MASK 0xff000000
1122#define DPM_TABLE_88__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x18
1123#define DPM_TABLE_89__GraphicsLevel_1_Flags_MASK 0xffffffff
1124#define DPM_TABLE_89__GraphicsLevel_1_Flags__SHIFT 0x0
1125#define DPM_TABLE_90__GraphicsLevel_1_MinVddc_MASK 0xffffffff
1126#define DPM_TABLE_90__GraphicsLevel_1_MinVddc__SHIFT 0x0
1127#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases_MASK 0xffffffff
1128#define DPM_TABLE_91__GraphicsLevel_1_MinVddcPhases__SHIFT 0x0
1129#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
1130#define DPM_TABLE_92__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
1131#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel_MASK 0xffff
1132#define DPM_TABLE_93__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
1133#define DPM_TABLE_93__GraphicsLevel_1_padding1_1_MASK 0xff0000
1134#define DPM_TABLE_93__GraphicsLevel_1_padding1_1__SHIFT 0x10
1135#define DPM_TABLE_93__GraphicsLevel_1_padding1_0_MASK 0xff000000
1136#define DPM_TABLE_93__GraphicsLevel_1_padding1_0__SHIFT 0x18
1137#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
1138#define DPM_TABLE_94__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
1139#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
1140#define DPM_TABLE_95__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
1141#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
1142#define DPM_TABLE_96__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
1143#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
1144#define DPM_TABLE_97__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
1145#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
1146#define DPM_TABLE_98__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
1147#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
1148#define DPM_TABLE_99__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
1149#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
1150#define DPM_TABLE_100__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
1151#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
1152#define DPM_TABLE_100__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
1153#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
1154#define DPM_TABLE_100__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
1155#define DPM_TABLE_100__GraphicsLevel_1_SclkDid_MASK 0xff000000
1156#define DPM_TABLE_100__GraphicsLevel_1_SclkDid__SHIFT 0x18
1157#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle_MASK 0xff
1158#define DPM_TABLE_101__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
1159#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
1160#define DPM_TABLE_101__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
1161#define DPM_TABLE_101__GraphicsLevel_1_DownHyst_MASK 0xff0000
1162#define DPM_TABLE_101__GraphicsLevel_1_DownHyst__SHIFT 0x10
1163#define DPM_TABLE_101__GraphicsLevel_1_UpHyst_MASK 0xff000000
1164#define DPM_TABLE_101__GraphicsLevel_1_UpHyst__SHIFT 0x18
1165#define DPM_TABLE_102__GraphicsLevel_1_padding_2_MASK 0xff
1166#define DPM_TABLE_102__GraphicsLevel_1_padding_2__SHIFT 0x0
1167#define DPM_TABLE_102__GraphicsLevel_1_padding_1_MASK 0xff00
1168#define DPM_TABLE_102__GraphicsLevel_1_padding_1__SHIFT 0x8
1169#define DPM_TABLE_102__GraphicsLevel_1_padding_0_MASK 0xff0000
1170#define DPM_TABLE_102__GraphicsLevel_1_padding_0__SHIFT 0x10
1171#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId_MASK 0xff000000
1172#define DPM_TABLE_102__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x18
1173#define DPM_TABLE_103__GraphicsLevel_2_Flags_MASK 0xffffffff
1174#define DPM_TABLE_103__GraphicsLevel_2_Flags__SHIFT 0x0
1175#define DPM_TABLE_104__GraphicsLevel_2_MinVddc_MASK 0xffffffff
1176#define DPM_TABLE_104__GraphicsLevel_2_MinVddc__SHIFT 0x0
1177#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases_MASK 0xffffffff
1178#define DPM_TABLE_105__GraphicsLevel_2_MinVddcPhases__SHIFT 0x0
1179#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
1180#define DPM_TABLE_106__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
1181#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel_MASK 0xffff
1182#define DPM_TABLE_107__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
1183#define DPM_TABLE_107__GraphicsLevel_2_padding1_1_MASK 0xff0000
1184#define DPM_TABLE_107__GraphicsLevel_2_padding1_1__SHIFT 0x10
1185#define DPM_TABLE_107__GraphicsLevel_2_padding1_0_MASK 0xff000000
1186#define DPM_TABLE_107__GraphicsLevel_2_padding1_0__SHIFT 0x18
1187#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
1188#define DPM_TABLE_108__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
1189#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
1190#define DPM_TABLE_109__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
1191#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
1192#define DPM_TABLE_110__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
1193#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
1194#define DPM_TABLE_111__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
1195#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
1196#define DPM_TABLE_112__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
1197#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
1198#define DPM_TABLE_113__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
1199#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
1200#define DPM_TABLE_114__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
1201#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
1202#define DPM_TABLE_114__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
1203#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
1204#define DPM_TABLE_114__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
1205#define DPM_TABLE_114__GraphicsLevel_2_SclkDid_MASK 0xff000000
1206#define DPM_TABLE_114__GraphicsLevel_2_SclkDid__SHIFT 0x18
1207#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle_MASK 0xff
1208#define DPM_TABLE_115__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
1209#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
1210#define DPM_TABLE_115__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
1211#define DPM_TABLE_115__GraphicsLevel_2_DownHyst_MASK 0xff0000
1212#define DPM_TABLE_115__GraphicsLevel_2_DownHyst__SHIFT 0x10
1213#define DPM_TABLE_115__GraphicsLevel_2_UpHyst_MASK 0xff000000
1214#define DPM_TABLE_115__GraphicsLevel_2_UpHyst__SHIFT 0x18
1215#define DPM_TABLE_116__GraphicsLevel_2_padding_2_MASK 0xff
1216#define DPM_TABLE_116__GraphicsLevel_2_padding_2__SHIFT 0x0
1217#define DPM_TABLE_116__GraphicsLevel_2_padding_1_MASK 0xff00
1218#define DPM_TABLE_116__GraphicsLevel_2_padding_1__SHIFT 0x8
1219#define DPM_TABLE_116__GraphicsLevel_2_padding_0_MASK 0xff0000
1220#define DPM_TABLE_116__GraphicsLevel_2_padding_0__SHIFT 0x10
1221#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId_MASK 0xff000000
1222#define DPM_TABLE_116__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x18
1223#define DPM_TABLE_117__GraphicsLevel_3_Flags_MASK 0xffffffff
1224#define DPM_TABLE_117__GraphicsLevel_3_Flags__SHIFT 0x0
1225#define DPM_TABLE_118__GraphicsLevel_3_MinVddc_MASK 0xffffffff
1226#define DPM_TABLE_118__GraphicsLevel_3_MinVddc__SHIFT 0x0
1227#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases_MASK 0xffffffff
1228#define DPM_TABLE_119__GraphicsLevel_3_MinVddcPhases__SHIFT 0x0
1229#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
1230#define DPM_TABLE_120__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
1231#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel_MASK 0xffff
1232#define DPM_TABLE_121__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
1233#define DPM_TABLE_121__GraphicsLevel_3_padding1_1_MASK 0xff0000
1234#define DPM_TABLE_121__GraphicsLevel_3_padding1_1__SHIFT 0x10
1235#define DPM_TABLE_121__GraphicsLevel_3_padding1_0_MASK 0xff000000
1236#define DPM_TABLE_121__GraphicsLevel_3_padding1_0__SHIFT 0x18
1237#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
1238#define DPM_TABLE_122__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
1239#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
1240#define DPM_TABLE_123__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
1241#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
1242#define DPM_TABLE_124__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
1243#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
1244#define DPM_TABLE_125__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
1245#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
1246#define DPM_TABLE_126__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
1247#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
1248#define DPM_TABLE_127__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
1249#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
1250#define DPM_TABLE_128__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
1251#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
1252#define DPM_TABLE_128__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
1253#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
1254#define DPM_TABLE_128__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
1255#define DPM_TABLE_128__GraphicsLevel_3_SclkDid_MASK 0xff000000
1256#define DPM_TABLE_128__GraphicsLevel_3_SclkDid__SHIFT 0x18
1257#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle_MASK 0xff
1258#define DPM_TABLE_129__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
1259#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
1260#define DPM_TABLE_129__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
1261#define DPM_TABLE_129__GraphicsLevel_3_DownHyst_MASK 0xff0000
1262#define DPM_TABLE_129__GraphicsLevel_3_DownHyst__SHIFT 0x10
1263#define DPM_TABLE_129__GraphicsLevel_3_UpHyst_MASK 0xff000000
1264#define DPM_TABLE_129__GraphicsLevel_3_UpHyst__SHIFT 0x18
1265#define DPM_TABLE_130__GraphicsLevel_3_padding_2_MASK 0xff
1266#define DPM_TABLE_130__GraphicsLevel_3_padding_2__SHIFT 0x0
1267#define DPM_TABLE_130__GraphicsLevel_3_padding_1_MASK 0xff00
1268#define DPM_TABLE_130__GraphicsLevel_3_padding_1__SHIFT 0x8
1269#define DPM_TABLE_130__GraphicsLevel_3_padding_0_MASK 0xff0000
1270#define DPM_TABLE_130__GraphicsLevel_3_padding_0__SHIFT 0x10
1271#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff000000
1272#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x18
1273#define DPM_TABLE_131__GraphicsLevel_4_Flags_MASK 0xffffffff
1274#define DPM_TABLE_131__GraphicsLevel_4_Flags__SHIFT 0x0
1275#define DPM_TABLE_132__GraphicsLevel_4_MinVddc_MASK 0xffffffff
1276#define DPM_TABLE_132__GraphicsLevel_4_MinVddc__SHIFT 0x0
1277#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases_MASK 0xffffffff
1278#define DPM_TABLE_133__GraphicsLevel_4_MinVddcPhases__SHIFT 0x0
1279#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
1280#define DPM_TABLE_134__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
1281#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel_MASK 0xffff
1282#define DPM_TABLE_135__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
1283#define DPM_TABLE_135__GraphicsLevel_4_padding1_1_MASK 0xff0000
1284#define DPM_TABLE_135__GraphicsLevel_4_padding1_1__SHIFT 0x10
1285#define DPM_TABLE_135__GraphicsLevel_4_padding1_0_MASK 0xff000000
1286#define DPM_TABLE_135__GraphicsLevel_4_padding1_0__SHIFT 0x18
1287#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
1288#define DPM_TABLE_136__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
1289#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
1290#define DPM_TABLE_137__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
1291#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
1292#define DPM_TABLE_138__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
1293#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
1294#define DPM_TABLE_139__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
1295#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
1296#define DPM_TABLE_140__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
1297#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
1298#define DPM_TABLE_141__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
1299#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
1300#define DPM_TABLE_142__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
1301#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
1302#define DPM_TABLE_142__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
1303#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
1304#define DPM_TABLE_142__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
1305#define DPM_TABLE_142__GraphicsLevel_4_SclkDid_MASK 0xff000000
1306#define DPM_TABLE_142__GraphicsLevel_4_SclkDid__SHIFT 0x18
1307#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle_MASK 0xff
1308#define DPM_TABLE_143__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
1309#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
1310#define DPM_TABLE_143__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
1311#define DPM_TABLE_143__GraphicsLevel_4_DownHyst_MASK 0xff0000
1312#define DPM_TABLE_143__GraphicsLevel_4_DownHyst__SHIFT 0x10
1313#define DPM_TABLE_143__GraphicsLevel_4_UpHyst_MASK 0xff000000
1314#define DPM_TABLE_143__GraphicsLevel_4_UpHyst__SHIFT 0x18
1315#define DPM_TABLE_144__GraphicsLevel_4_padding_2_MASK 0xff
1316#define DPM_TABLE_144__GraphicsLevel_4_padding_2__SHIFT 0x0
1317#define DPM_TABLE_144__GraphicsLevel_4_padding_1_MASK 0xff00
1318#define DPM_TABLE_144__GraphicsLevel_4_padding_1__SHIFT 0x8
1319#define DPM_TABLE_144__GraphicsLevel_4_padding_0_MASK 0xff0000
1320#define DPM_TABLE_144__GraphicsLevel_4_padding_0__SHIFT 0x10
1321#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId_MASK 0xff000000
1322#define DPM_TABLE_144__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x18
1323#define DPM_TABLE_145__GraphicsLevel_5_Flags_MASK 0xffffffff
1324#define DPM_TABLE_145__GraphicsLevel_5_Flags__SHIFT 0x0
1325#define DPM_TABLE_146__GraphicsLevel_5_MinVddc_MASK 0xffffffff
1326#define DPM_TABLE_146__GraphicsLevel_5_MinVddc__SHIFT 0x0
1327#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases_MASK 0xffffffff
1328#define DPM_TABLE_147__GraphicsLevel_5_MinVddcPhases__SHIFT 0x0
1329#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
1330#define DPM_TABLE_148__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
1331#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel_MASK 0xffff
1332#define DPM_TABLE_149__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
1333#define DPM_TABLE_149__GraphicsLevel_5_padding1_1_MASK 0xff0000
1334#define DPM_TABLE_149__GraphicsLevel_5_padding1_1__SHIFT 0x10
1335#define DPM_TABLE_149__GraphicsLevel_5_padding1_0_MASK 0xff000000
1336#define DPM_TABLE_149__GraphicsLevel_5_padding1_0__SHIFT 0x18
1337#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
1338#define DPM_TABLE_150__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
1339#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
1340#define DPM_TABLE_151__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
1341#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
1342#define DPM_TABLE_152__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
1343#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
1344#define DPM_TABLE_153__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
1345#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
1346#define DPM_TABLE_154__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
1347#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
1348#define DPM_TABLE_155__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
1349#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
1350#define DPM_TABLE_156__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
1351#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
1352#define DPM_TABLE_156__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
1353#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
1354#define DPM_TABLE_156__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
1355#define DPM_TABLE_156__GraphicsLevel_5_SclkDid_MASK 0xff000000
1356#define DPM_TABLE_156__GraphicsLevel_5_SclkDid__SHIFT 0x18
1357#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle_MASK 0xff
1358#define DPM_TABLE_157__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
1359#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
1360#define DPM_TABLE_157__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
1361#define DPM_TABLE_157__GraphicsLevel_5_DownHyst_MASK 0xff0000
1362#define DPM_TABLE_157__GraphicsLevel_5_DownHyst__SHIFT 0x10
1363#define DPM_TABLE_157__GraphicsLevel_5_UpHyst_MASK 0xff000000
1364#define DPM_TABLE_157__GraphicsLevel_5_UpHyst__SHIFT 0x18
1365#define DPM_TABLE_158__GraphicsLevel_5_padding_2_MASK 0xff
1366#define DPM_TABLE_158__GraphicsLevel_5_padding_2__SHIFT 0x0
1367#define DPM_TABLE_158__GraphicsLevel_5_padding_1_MASK 0xff00
1368#define DPM_TABLE_158__GraphicsLevel_5_padding_1__SHIFT 0x8
1369#define DPM_TABLE_158__GraphicsLevel_5_padding_0_MASK 0xff0000
1370#define DPM_TABLE_158__GraphicsLevel_5_padding_0__SHIFT 0x10
1371#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId_MASK 0xff000000
1372#define DPM_TABLE_158__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x18
1373#define DPM_TABLE_159__GraphicsLevel_6_Flags_MASK 0xffffffff
1374#define DPM_TABLE_159__GraphicsLevel_6_Flags__SHIFT 0x0
1375#define DPM_TABLE_160__GraphicsLevel_6_MinVddc_MASK 0xffffffff
1376#define DPM_TABLE_160__GraphicsLevel_6_MinVddc__SHIFT 0x0
1377#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases_MASK 0xffffffff
1378#define DPM_TABLE_161__GraphicsLevel_6_MinVddcPhases__SHIFT 0x0
1379#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
1380#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
1381#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
1382#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
1383#define DPM_TABLE_163__GraphicsLevel_6_padding1_1_MASK 0xff0000
1384#define DPM_TABLE_163__GraphicsLevel_6_padding1_1__SHIFT 0x10
1385#define DPM_TABLE_163__GraphicsLevel_6_padding1_0_MASK 0xff000000
1386#define DPM_TABLE_163__GraphicsLevel_6_padding1_0__SHIFT 0x18
1387#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
1388#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
1389#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
1390#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
1391#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
1392#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
1393#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
1394#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
1395#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
1396#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
1397#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
1398#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
1399#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
1400#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
1401#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
1402#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
1403#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
1404#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
1405#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
1406#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
1407#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
1408#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
1409#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
1410#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
1411#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
1412#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
1413#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
1414#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
1415#define DPM_TABLE_172__GraphicsLevel_6_padding_2_MASK 0xff
1416#define DPM_TABLE_172__GraphicsLevel_6_padding_2__SHIFT 0x0
1417#define DPM_TABLE_172__GraphicsLevel_6_padding_1_MASK 0xff00
1418#define DPM_TABLE_172__GraphicsLevel_6_padding_1__SHIFT 0x8
1419#define DPM_TABLE_172__GraphicsLevel_6_padding_0_MASK 0xff0000
1420#define DPM_TABLE_172__GraphicsLevel_6_padding_0__SHIFT 0x10
1421#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId_MASK 0xff000000
1422#define DPM_TABLE_172__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x18
1423#define DPM_TABLE_173__GraphicsLevel_7_Flags_MASK 0xffffffff
1424#define DPM_TABLE_173__GraphicsLevel_7_Flags__SHIFT 0x0
1425#define DPM_TABLE_174__GraphicsLevel_7_MinVddc_MASK 0xffffffff
1426#define DPM_TABLE_174__GraphicsLevel_7_MinVddc__SHIFT 0x0
1427#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases_MASK 0xffffffff
1428#define DPM_TABLE_175__GraphicsLevel_7_MinVddcPhases__SHIFT 0x0
1429#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
1430#define DPM_TABLE_176__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
1431#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel_MASK 0xffff
1432#define DPM_TABLE_177__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
1433#define DPM_TABLE_177__GraphicsLevel_7_padding1_1_MASK 0xff0000
1434#define DPM_TABLE_177__GraphicsLevel_7_padding1_1__SHIFT 0x10
1435#define DPM_TABLE_177__GraphicsLevel_7_padding1_0_MASK 0xff000000
1436#define DPM_TABLE_177__GraphicsLevel_7_padding1_0__SHIFT 0x18
1437#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
1438#define DPM_TABLE_178__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
1439#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
1440#define DPM_TABLE_179__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
1441#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
1442#define DPM_TABLE_180__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
1443#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
1444#define DPM_TABLE_181__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
1445#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
1446#define DPM_TABLE_182__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
1447#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
1448#define DPM_TABLE_183__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
1449#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
1450#define DPM_TABLE_184__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
1451#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
1452#define DPM_TABLE_184__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
1453#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
1454#define DPM_TABLE_184__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
1455#define DPM_TABLE_184__GraphicsLevel_7_SclkDid_MASK 0xff000000
1456#define DPM_TABLE_184__GraphicsLevel_7_SclkDid__SHIFT 0x18
1457#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle_MASK 0xff
1458#define DPM_TABLE_185__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
1459#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
1460#define DPM_TABLE_185__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
1461#define DPM_TABLE_185__GraphicsLevel_7_DownHyst_MASK 0xff0000
1462#define DPM_TABLE_185__GraphicsLevel_7_DownHyst__SHIFT 0x10
1463#define DPM_TABLE_185__GraphicsLevel_7_UpHyst_MASK 0xff000000
1464#define DPM_TABLE_185__GraphicsLevel_7_UpHyst__SHIFT 0x18
1465#define DPM_TABLE_186__GraphicsLevel_7_padding_2_MASK 0xff
1466#define DPM_TABLE_186__GraphicsLevel_7_padding_2__SHIFT 0x0
1467#define DPM_TABLE_186__GraphicsLevel_7_padding_1_MASK 0xff00
1468#define DPM_TABLE_186__GraphicsLevel_7_padding_1__SHIFT 0x8
1469#define DPM_TABLE_186__GraphicsLevel_7_padding_0_MASK 0xff0000
1470#define DPM_TABLE_186__GraphicsLevel_7_padding_0__SHIFT 0x10
1471#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId_MASK 0xff000000
1472#define DPM_TABLE_186__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x18
1473#define DPM_TABLE_187__MemoryACPILevel_MinVddc_MASK 0xffffffff
1474#define DPM_TABLE_187__MemoryACPILevel_MinVddc__SHIFT 0x0
1475#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases_MASK 0xffffffff
1476#define DPM_TABLE_188__MemoryACPILevel_MinVddcPhases__SHIFT 0x0
1477#define DPM_TABLE_189__MemoryACPILevel_MinVddci_MASK 0xffffffff
1478#define DPM_TABLE_189__MemoryACPILevel_MinVddci__SHIFT 0x0
1479#define DPM_TABLE_190__MemoryACPILevel_MinMvdd_MASK 0xffffffff
1480#define DPM_TABLE_190__MemoryACPILevel_MinMvdd__SHIFT 0x0
1481#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
1482#define DPM_TABLE_191__MemoryACPILevel_MclkFrequency__SHIFT 0x0
1483#define DPM_TABLE_192__MemoryACPILevel_StutterEnable_MASK 0xff
1484#define DPM_TABLE_192__MemoryACPILevel_StutterEnable__SHIFT 0x0
1485#define DPM_TABLE_192__MemoryACPILevel_RttEnable_MASK 0xff00
1486#define DPM_TABLE_192__MemoryACPILevel_RttEnable__SHIFT 0x8
1487#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable_MASK 0xff0000
1488#define DPM_TABLE_192__MemoryACPILevel_EdcWriteEnable__SHIFT 0x10
1489#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable_MASK 0xff000000
1490#define DPM_TABLE_192__MemoryACPILevel_EdcReadEnable__SHIFT 0x18
1491#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity_MASK 0xff
1492#define DPM_TABLE_193__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
1493#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
1494#define DPM_TABLE_193__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
1495#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio_MASK 0xff0000
1496#define DPM_TABLE_193__MemoryACPILevel_StrobeRatio__SHIFT 0x10
1497#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable_MASK 0xff000000
1498#define DPM_TABLE_193__MemoryACPILevel_StrobeEnable__SHIFT 0x18
1499#define DPM_TABLE_194__MemoryACPILevel_padding_MASK 0xff
1500#define DPM_TABLE_194__MemoryACPILevel_padding__SHIFT 0x0
1501#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
1502#define DPM_TABLE_194__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
1503#define DPM_TABLE_194__MemoryACPILevel_DownHyst_MASK 0xff0000
1504#define DPM_TABLE_194__MemoryACPILevel_DownHyst__SHIFT 0x10
1505#define DPM_TABLE_194__MemoryACPILevel_UpHyst_MASK 0xff000000
1506#define DPM_TABLE_194__MemoryACPILevel_UpHyst__SHIFT 0x18
1507#define DPM_TABLE_195__MemoryACPILevel_padding1_1_MASK 0xff
1508#define DPM_TABLE_195__MemoryACPILevel_padding1_1__SHIFT 0x0
1509#define DPM_TABLE_195__MemoryACPILevel_padding1_0_MASK 0xff00
1510#define DPM_TABLE_195__MemoryACPILevel_padding1_0__SHIFT 0x8
1511#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
1512#define DPM_TABLE_195__MemoryACPILevel_ActivityLevel__SHIFT 0x10
1513#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl_MASK 0xffffffff
1514#define DPM_TABLE_196__MemoryACPILevel_MpllFuncCntl__SHIFT 0x0
1515#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1_MASK 0xffffffff
1516#define DPM_TABLE_197__MemoryACPILevel_MpllFuncCntl_1__SHIFT 0x0
1517#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2_MASK 0xffffffff
1518#define DPM_TABLE_198__MemoryACPILevel_MpllFuncCntl_2__SHIFT 0x0
1519#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl_MASK 0xffffffff
1520#define DPM_TABLE_199__MemoryACPILevel_MpllAdFuncCntl__SHIFT 0x0
1521#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl_MASK 0xffffffff
1522#define DPM_TABLE_200__MemoryACPILevel_MpllDqFuncCntl__SHIFT 0x0
1523#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl_MASK 0xffffffff
1524#define DPM_TABLE_201__MemoryACPILevel_MclkPwrmgtCntl__SHIFT 0x0
1525#define DPM_TABLE_202__MemoryACPILevel_DllCntl_MASK 0xffffffff
1526#define DPM_TABLE_202__MemoryACPILevel_DllCntl__SHIFT 0x0
1527#define DPM_TABLE_203__MemoryACPILevel_MpllSs1_MASK 0xffffffff
1528#define DPM_TABLE_203__MemoryACPILevel_MpllSs1__SHIFT 0x0
1529#define DPM_TABLE_204__MemoryACPILevel_MpllSs2_MASK 0xffffffff
1530#define DPM_TABLE_204__MemoryACPILevel_MpllSs2__SHIFT 0x0
1531#define DPM_TABLE_205__MemoryLevel_0_MinVddc_MASK 0xffffffff
1532#define DPM_TABLE_205__MemoryLevel_0_MinVddc__SHIFT 0x0
1533#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases_MASK 0xffffffff
1534#define DPM_TABLE_206__MemoryLevel_0_MinVddcPhases__SHIFT 0x0
1535#define DPM_TABLE_207__MemoryLevel_0_MinVddci_MASK 0xffffffff
1536#define DPM_TABLE_207__MemoryLevel_0_MinVddci__SHIFT 0x0
1537#define DPM_TABLE_208__MemoryLevel_0_MinMvdd_MASK 0xffffffff
1538#define DPM_TABLE_208__MemoryLevel_0_MinMvdd__SHIFT 0x0
1539#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
1540#define DPM_TABLE_209__MemoryLevel_0_MclkFrequency__SHIFT 0x0
1541#define DPM_TABLE_210__MemoryLevel_0_StutterEnable_MASK 0xff
1542#define DPM_TABLE_210__MemoryLevel_0_StutterEnable__SHIFT 0x0
1543#define DPM_TABLE_210__MemoryLevel_0_RttEnable_MASK 0xff00
1544#define DPM_TABLE_210__MemoryLevel_0_RttEnable__SHIFT 0x8
1545#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable_MASK 0xff0000
1546#define DPM_TABLE_210__MemoryLevel_0_EdcWriteEnable__SHIFT 0x10
1547#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable_MASK 0xff000000
1548#define DPM_TABLE_210__MemoryLevel_0_EdcReadEnable__SHIFT 0x18
1549#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity_MASK 0xff
1550#define DPM_TABLE_211__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
1551#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
1552#define DPM_TABLE_211__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
1553#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio_MASK 0xff0000
1554#define DPM_TABLE_211__MemoryLevel_0_StrobeRatio__SHIFT 0x10
1555#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable_MASK 0xff000000
1556#define DPM_TABLE_211__MemoryLevel_0_StrobeEnable__SHIFT 0x18
1557#define DPM_TABLE_212__MemoryLevel_0_padding_MASK 0xff
1558#define DPM_TABLE_212__MemoryLevel_0_padding__SHIFT 0x0
1559#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
1560#define DPM_TABLE_212__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
1561#define DPM_TABLE_212__MemoryLevel_0_DownHyst_MASK 0xff0000
1562#define DPM_TABLE_212__MemoryLevel_0_DownHyst__SHIFT 0x10
1563#define DPM_TABLE_212__MemoryLevel_0_UpHyst_MASK 0xff000000
1564#define DPM_TABLE_212__MemoryLevel_0_UpHyst__SHIFT 0x18
1565#define DPM_TABLE_213__MemoryLevel_0_padding1_1_MASK 0xff
1566#define DPM_TABLE_213__MemoryLevel_0_padding1_1__SHIFT 0x0
1567#define DPM_TABLE_213__MemoryLevel_0_padding1_0_MASK 0xff00
1568#define DPM_TABLE_213__MemoryLevel_0_padding1_0__SHIFT 0x8
1569#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
1570#define DPM_TABLE_213__MemoryLevel_0_ActivityLevel__SHIFT 0x10
1571#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl_MASK 0xffffffff
1572#define DPM_TABLE_214__MemoryLevel_0_MpllFuncCntl__SHIFT 0x0
1573#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1_MASK 0xffffffff
1574#define DPM_TABLE_215__MemoryLevel_0_MpllFuncCntl_1__SHIFT 0x0
1575#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2_MASK 0xffffffff
1576#define DPM_TABLE_216__MemoryLevel_0_MpllFuncCntl_2__SHIFT 0x0
1577#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl_MASK 0xffffffff
1578#define DPM_TABLE_217__MemoryLevel_0_MpllAdFuncCntl__SHIFT 0x0
1579#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl_MASK 0xffffffff
1580#define DPM_TABLE_218__MemoryLevel_0_MpllDqFuncCntl__SHIFT 0x0
1581#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl_MASK 0xffffffff
1582#define DPM_TABLE_219__MemoryLevel_0_MclkPwrmgtCntl__SHIFT 0x0
1583#define DPM_TABLE_220__MemoryLevel_0_DllCntl_MASK 0xffffffff
1584#define DPM_TABLE_220__MemoryLevel_0_DllCntl__SHIFT 0x0
1585#define DPM_TABLE_221__MemoryLevel_0_MpllSs1_MASK 0xffffffff
1586#define DPM_TABLE_221__MemoryLevel_0_MpllSs1__SHIFT 0x0
1587#define DPM_TABLE_222__MemoryLevel_0_MpllSs2_MASK 0xffffffff
1588#define DPM_TABLE_222__MemoryLevel_0_MpllSs2__SHIFT 0x0
1589#define DPM_TABLE_223__MemoryLevel_1_MinVddc_MASK 0xffffffff
1590#define DPM_TABLE_223__MemoryLevel_1_MinVddc__SHIFT 0x0
1591#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases_MASK 0xffffffff
1592#define DPM_TABLE_224__MemoryLevel_1_MinVddcPhases__SHIFT 0x0
1593#define DPM_TABLE_225__MemoryLevel_1_MinVddci_MASK 0xffffffff
1594#define DPM_TABLE_225__MemoryLevel_1_MinVddci__SHIFT 0x0
1595#define DPM_TABLE_226__MemoryLevel_1_MinMvdd_MASK 0xffffffff
1596#define DPM_TABLE_226__MemoryLevel_1_MinMvdd__SHIFT 0x0
1597#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
1598#define DPM_TABLE_227__MemoryLevel_1_MclkFrequency__SHIFT 0x0
1599#define DPM_TABLE_228__MemoryLevel_1_StutterEnable_MASK 0xff
1600#define DPM_TABLE_228__MemoryLevel_1_StutterEnable__SHIFT 0x0
1601#define DPM_TABLE_228__MemoryLevel_1_RttEnable_MASK 0xff00
1602#define DPM_TABLE_228__MemoryLevel_1_RttEnable__SHIFT 0x8
1603#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable_MASK 0xff0000
1604#define DPM_TABLE_228__MemoryLevel_1_EdcWriteEnable__SHIFT 0x10
1605#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable_MASK 0xff000000
1606#define DPM_TABLE_228__MemoryLevel_1_EdcReadEnable__SHIFT 0x18
1607#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity_MASK 0xff
1608#define DPM_TABLE_229__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
1609#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
1610#define DPM_TABLE_229__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
1611#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio_MASK 0xff0000
1612#define DPM_TABLE_229__MemoryLevel_1_StrobeRatio__SHIFT 0x10
1613#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable_MASK 0xff000000
1614#define DPM_TABLE_229__MemoryLevel_1_StrobeEnable__SHIFT 0x18
1615#define DPM_TABLE_230__MemoryLevel_1_padding_MASK 0xff
1616#define DPM_TABLE_230__MemoryLevel_1_padding__SHIFT 0x0
1617#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
1618#define DPM_TABLE_230__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
1619#define DPM_TABLE_230__MemoryLevel_1_DownHyst_MASK 0xff0000
1620#define DPM_TABLE_230__MemoryLevel_1_DownHyst__SHIFT 0x10
1621#define DPM_TABLE_230__MemoryLevel_1_UpHyst_MASK 0xff000000
1622#define DPM_TABLE_230__MemoryLevel_1_UpHyst__SHIFT 0x18
1623#define DPM_TABLE_231__MemoryLevel_1_padding1_1_MASK 0xff
1624#define DPM_TABLE_231__MemoryLevel_1_padding1_1__SHIFT 0x0
1625#define DPM_TABLE_231__MemoryLevel_1_padding1_0_MASK 0xff00
1626#define DPM_TABLE_231__MemoryLevel_1_padding1_0__SHIFT 0x8
1627#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
1628#define DPM_TABLE_231__MemoryLevel_1_ActivityLevel__SHIFT 0x10
1629#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl_MASK 0xffffffff
1630#define DPM_TABLE_232__MemoryLevel_1_MpllFuncCntl__SHIFT 0x0
1631#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1_MASK 0xffffffff
1632#define DPM_TABLE_233__MemoryLevel_1_MpllFuncCntl_1__SHIFT 0x0
1633#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2_MASK 0xffffffff
1634#define DPM_TABLE_234__MemoryLevel_1_MpllFuncCntl_2__SHIFT 0x0
1635#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl_MASK 0xffffffff
1636#define DPM_TABLE_235__MemoryLevel_1_MpllAdFuncCntl__SHIFT 0x0
1637#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl_MASK 0xffffffff
1638#define DPM_TABLE_236__MemoryLevel_1_MpllDqFuncCntl__SHIFT 0x0
1639#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl_MASK 0xffffffff
1640#define DPM_TABLE_237__MemoryLevel_1_MclkPwrmgtCntl__SHIFT 0x0
1641#define DPM_TABLE_238__MemoryLevel_1_DllCntl_MASK 0xffffffff
1642#define DPM_TABLE_238__MemoryLevel_1_DllCntl__SHIFT 0x0
1643#define DPM_TABLE_239__MemoryLevel_1_MpllSs1_MASK 0xffffffff
1644#define DPM_TABLE_239__MemoryLevel_1_MpllSs1__SHIFT 0x0
1645#define DPM_TABLE_240__MemoryLevel_1_MpllSs2_MASK 0xffffffff
1646#define DPM_TABLE_240__MemoryLevel_1_MpllSs2__SHIFT 0x0
1647#define DPM_TABLE_241__MemoryLevel_2_MinVddc_MASK 0xffffffff
1648#define DPM_TABLE_241__MemoryLevel_2_MinVddc__SHIFT 0x0
1649#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases_MASK 0xffffffff
1650#define DPM_TABLE_242__MemoryLevel_2_MinVddcPhases__SHIFT 0x0
1651#define DPM_TABLE_243__MemoryLevel_2_MinVddci_MASK 0xffffffff
1652#define DPM_TABLE_243__MemoryLevel_2_MinVddci__SHIFT 0x0
1653#define DPM_TABLE_244__MemoryLevel_2_MinMvdd_MASK 0xffffffff
1654#define DPM_TABLE_244__MemoryLevel_2_MinMvdd__SHIFT 0x0
1655#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
1656#define DPM_TABLE_245__MemoryLevel_2_MclkFrequency__SHIFT 0x0
1657#define DPM_TABLE_246__MemoryLevel_2_StutterEnable_MASK 0xff
1658#define DPM_TABLE_246__MemoryLevel_2_StutterEnable__SHIFT 0x0
1659#define DPM_TABLE_246__MemoryLevel_2_RttEnable_MASK 0xff00
1660#define DPM_TABLE_246__MemoryLevel_2_RttEnable__SHIFT 0x8
1661#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable_MASK 0xff0000
1662#define DPM_TABLE_246__MemoryLevel_2_EdcWriteEnable__SHIFT 0x10
1663#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable_MASK 0xff000000
1664#define DPM_TABLE_246__MemoryLevel_2_EdcReadEnable__SHIFT 0x18
1665#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity_MASK 0xff
1666#define DPM_TABLE_247__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
1667#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
1668#define DPM_TABLE_247__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
1669#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio_MASK 0xff0000
1670#define DPM_TABLE_247__MemoryLevel_2_StrobeRatio__SHIFT 0x10
1671#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable_MASK 0xff000000
1672#define DPM_TABLE_247__MemoryLevel_2_StrobeEnable__SHIFT 0x18
1673#define DPM_TABLE_248__MemoryLevel_2_padding_MASK 0xff
1674#define DPM_TABLE_248__MemoryLevel_2_padding__SHIFT 0x0
1675#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
1676#define DPM_TABLE_248__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
1677#define DPM_TABLE_248__MemoryLevel_2_DownHyst_MASK 0xff0000
1678#define DPM_TABLE_248__MemoryLevel_2_DownHyst__SHIFT 0x10
1679#define DPM_TABLE_248__MemoryLevel_2_UpHyst_MASK 0xff000000
1680#define DPM_TABLE_248__MemoryLevel_2_UpHyst__SHIFT 0x18
1681#define DPM_TABLE_249__MemoryLevel_2_padding1_1_MASK 0xff
1682#define DPM_TABLE_249__MemoryLevel_2_padding1_1__SHIFT 0x0
1683#define DPM_TABLE_249__MemoryLevel_2_padding1_0_MASK 0xff00
1684#define DPM_TABLE_249__MemoryLevel_2_padding1_0__SHIFT 0x8
1685#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
1686#define DPM_TABLE_249__MemoryLevel_2_ActivityLevel__SHIFT 0x10
1687#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl_MASK 0xffffffff
1688#define DPM_TABLE_250__MemoryLevel_2_MpllFuncCntl__SHIFT 0x0
1689#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1_MASK 0xffffffff
1690#define DPM_TABLE_251__MemoryLevel_2_MpllFuncCntl_1__SHIFT 0x0
1691#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2_MASK 0xffffffff
1692#define DPM_TABLE_252__MemoryLevel_2_MpllFuncCntl_2__SHIFT 0x0
1693#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl_MASK 0xffffffff
1694#define DPM_TABLE_253__MemoryLevel_2_MpllAdFuncCntl__SHIFT 0x0
1695#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl_MASK 0xffffffff
1696#define DPM_TABLE_254__MemoryLevel_2_MpllDqFuncCntl__SHIFT 0x0
1697#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl_MASK 0xffffffff
1698#define DPM_TABLE_255__MemoryLevel_2_MclkPwrmgtCntl__SHIFT 0x0
1699#define DPM_TABLE_256__MemoryLevel_2_DllCntl_MASK 0xffffffff
1700#define DPM_TABLE_256__MemoryLevel_2_DllCntl__SHIFT 0x0
1701#define DPM_TABLE_257__MemoryLevel_2_MpllSs1_MASK 0xffffffff
1702#define DPM_TABLE_257__MemoryLevel_2_MpllSs1__SHIFT 0x0
1703#define DPM_TABLE_258__MemoryLevel_2_MpllSs2_MASK 0xffffffff
1704#define DPM_TABLE_258__MemoryLevel_2_MpllSs2__SHIFT 0x0
1705#define DPM_TABLE_259__MemoryLevel_3_MinVddc_MASK 0xffffffff
1706#define DPM_TABLE_259__MemoryLevel_3_MinVddc__SHIFT 0x0
1707#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases_MASK 0xffffffff
1708#define DPM_TABLE_260__MemoryLevel_3_MinVddcPhases__SHIFT 0x0
1709#define DPM_TABLE_261__MemoryLevel_3_MinVddci_MASK 0xffffffff
1710#define DPM_TABLE_261__MemoryLevel_3_MinVddci__SHIFT 0x0
1711#define DPM_TABLE_262__MemoryLevel_3_MinMvdd_MASK 0xffffffff
1712#define DPM_TABLE_262__MemoryLevel_3_MinMvdd__SHIFT 0x0
1713#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
1714#define DPM_TABLE_263__MemoryLevel_3_MclkFrequency__SHIFT 0x0
1715#define DPM_TABLE_264__MemoryLevel_3_StutterEnable_MASK 0xff
1716#define DPM_TABLE_264__MemoryLevel_3_StutterEnable__SHIFT 0x0
1717#define DPM_TABLE_264__MemoryLevel_3_RttEnable_MASK 0xff00
1718#define DPM_TABLE_264__MemoryLevel_3_RttEnable__SHIFT 0x8
1719#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable_MASK 0xff0000
1720#define DPM_TABLE_264__MemoryLevel_3_EdcWriteEnable__SHIFT 0x10
1721#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable_MASK 0xff000000
1722#define DPM_TABLE_264__MemoryLevel_3_EdcReadEnable__SHIFT 0x18
1723#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity_MASK 0xff
1724#define DPM_TABLE_265__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
1725#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
1726#define DPM_TABLE_265__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
1727#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio_MASK 0xff0000
1728#define DPM_TABLE_265__MemoryLevel_3_StrobeRatio__SHIFT 0x10
1729#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable_MASK 0xff000000
1730#define DPM_TABLE_265__MemoryLevel_3_StrobeEnable__SHIFT 0x18
1731#define DPM_TABLE_266__MemoryLevel_3_padding_MASK 0xff
1732#define DPM_TABLE_266__MemoryLevel_3_padding__SHIFT 0x0
1733#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
1734#define DPM_TABLE_266__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
1735#define DPM_TABLE_266__MemoryLevel_3_DownHyst_MASK 0xff0000
1736#define DPM_TABLE_266__MemoryLevel_3_DownHyst__SHIFT 0x10
1737#define DPM_TABLE_266__MemoryLevel_3_UpHyst_MASK 0xff000000
1738#define DPM_TABLE_266__MemoryLevel_3_UpHyst__SHIFT 0x18
1739#define DPM_TABLE_267__MemoryLevel_3_padding1_1_MASK 0xff
1740#define DPM_TABLE_267__MemoryLevel_3_padding1_1__SHIFT 0x0
1741#define DPM_TABLE_267__MemoryLevel_3_padding1_0_MASK 0xff00
1742#define DPM_TABLE_267__MemoryLevel_3_padding1_0__SHIFT 0x8
1743#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
1744#define DPM_TABLE_267__MemoryLevel_3_ActivityLevel__SHIFT 0x10
1745#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl_MASK 0xffffffff
1746#define DPM_TABLE_268__MemoryLevel_3_MpllFuncCntl__SHIFT 0x0
1747#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1_MASK 0xffffffff
1748#define DPM_TABLE_269__MemoryLevel_3_MpllFuncCntl_1__SHIFT 0x0
1749#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2_MASK 0xffffffff
1750#define DPM_TABLE_270__MemoryLevel_3_MpllFuncCntl_2__SHIFT 0x0
1751#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl_MASK 0xffffffff
1752#define DPM_TABLE_271__MemoryLevel_3_MpllAdFuncCntl__SHIFT 0x0
1753#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl_MASK 0xffffffff
1754#define DPM_TABLE_272__MemoryLevel_3_MpllDqFuncCntl__SHIFT 0x0
1755#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl_MASK 0xffffffff
1756#define DPM_TABLE_273__MemoryLevel_3_MclkPwrmgtCntl__SHIFT 0x0
1757#define DPM_TABLE_274__MemoryLevel_3_DllCntl_MASK 0xffffffff
1758#define DPM_TABLE_274__MemoryLevel_3_DllCntl__SHIFT 0x0
1759#define DPM_TABLE_275__MemoryLevel_3_MpllSs1_MASK 0xffffffff
1760#define DPM_TABLE_275__MemoryLevel_3_MpllSs1__SHIFT 0x0
1761#define DPM_TABLE_276__MemoryLevel_3_MpllSs2_MASK 0xffffffff
1762#define DPM_TABLE_276__MemoryLevel_3_MpllSs2__SHIFT 0x0
1763#define DPM_TABLE_277__MemoryLevel_4_MinVddc_MASK 0xffffffff
1764#define DPM_TABLE_277__MemoryLevel_4_MinVddc__SHIFT 0x0
1765#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases_MASK 0xffffffff
1766#define DPM_TABLE_278__MemoryLevel_4_MinVddcPhases__SHIFT 0x0
1767#define DPM_TABLE_279__MemoryLevel_4_MinVddci_MASK 0xffffffff
1768#define DPM_TABLE_279__MemoryLevel_4_MinVddci__SHIFT 0x0
1769#define DPM_TABLE_280__MemoryLevel_4_MinMvdd_MASK 0xffffffff
1770#define DPM_TABLE_280__MemoryLevel_4_MinMvdd__SHIFT 0x0
1771#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency_MASK 0xffffffff
1772#define DPM_TABLE_281__MemoryLevel_4_MclkFrequency__SHIFT 0x0
1773#define DPM_TABLE_282__MemoryLevel_4_StutterEnable_MASK 0xff
1774#define DPM_TABLE_282__MemoryLevel_4_StutterEnable__SHIFT 0x0
1775#define DPM_TABLE_282__MemoryLevel_4_RttEnable_MASK 0xff00
1776#define DPM_TABLE_282__MemoryLevel_4_RttEnable__SHIFT 0x8
1777#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable_MASK 0xff0000
1778#define DPM_TABLE_282__MemoryLevel_4_EdcWriteEnable__SHIFT 0x10
1779#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable_MASK 0xff000000
1780#define DPM_TABLE_282__MemoryLevel_4_EdcReadEnable__SHIFT 0x18
1781#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity_MASK 0xff
1782#define DPM_TABLE_283__MemoryLevel_4_EnabledForActivity__SHIFT 0x0
1783#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle_MASK 0xff00
1784#define DPM_TABLE_283__MemoryLevel_4_EnabledForThrottle__SHIFT 0x8
1785#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio_MASK 0xff0000
1786#define DPM_TABLE_283__MemoryLevel_4_StrobeRatio__SHIFT 0x10
1787#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable_MASK 0xff000000
1788#define DPM_TABLE_283__MemoryLevel_4_StrobeEnable__SHIFT 0x18
1789#define DPM_TABLE_284__MemoryLevel_4_padding_MASK 0xff
1790#define DPM_TABLE_284__MemoryLevel_4_padding__SHIFT 0x0
1791#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst_MASK 0xff00
1792#define DPM_TABLE_284__MemoryLevel_4_VoltageDownHyst__SHIFT 0x8
1793#define DPM_TABLE_284__MemoryLevel_4_DownHyst_MASK 0xff0000
1794#define DPM_TABLE_284__MemoryLevel_4_DownHyst__SHIFT 0x10
1795#define DPM_TABLE_284__MemoryLevel_4_UpHyst_MASK 0xff000000
1796#define DPM_TABLE_284__MemoryLevel_4_UpHyst__SHIFT 0x18
1797#define DPM_TABLE_285__MemoryLevel_4_padding1_1_MASK 0xff
1798#define DPM_TABLE_285__MemoryLevel_4_padding1_1__SHIFT 0x0
1799#define DPM_TABLE_285__MemoryLevel_4_padding1_0_MASK 0xff00
1800#define DPM_TABLE_285__MemoryLevel_4_padding1_0__SHIFT 0x8
1801#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel_MASK 0xffff0000
1802#define DPM_TABLE_285__MemoryLevel_4_ActivityLevel__SHIFT 0x10
1803#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl_MASK 0xffffffff
1804#define DPM_TABLE_286__MemoryLevel_4_MpllFuncCntl__SHIFT 0x0
1805#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1_MASK 0xffffffff
1806#define DPM_TABLE_287__MemoryLevel_4_MpllFuncCntl_1__SHIFT 0x0
1807#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2_MASK 0xffffffff
1808#define DPM_TABLE_288__MemoryLevel_4_MpllFuncCntl_2__SHIFT 0x0
1809#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl_MASK 0xffffffff
1810#define DPM_TABLE_289__MemoryLevel_4_MpllAdFuncCntl__SHIFT 0x0
1811#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl_MASK 0xffffffff
1812#define DPM_TABLE_290__MemoryLevel_4_MpllDqFuncCntl__SHIFT 0x0
1813#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl_MASK 0xffffffff
1814#define DPM_TABLE_291__MemoryLevel_4_MclkPwrmgtCntl__SHIFT 0x0
1815#define DPM_TABLE_292__MemoryLevel_4_DllCntl_MASK 0xffffffff
1816#define DPM_TABLE_292__MemoryLevel_4_DllCntl__SHIFT 0x0
1817#define DPM_TABLE_293__MemoryLevel_4_MpllSs1_MASK 0xffffffff
1818#define DPM_TABLE_293__MemoryLevel_4_MpllSs1__SHIFT 0x0
1819#define DPM_TABLE_294__MemoryLevel_4_MpllSs2_MASK 0xffffffff
1820#define DPM_TABLE_294__MemoryLevel_4_MpllSs2__SHIFT 0x0
1821#define DPM_TABLE_295__MemoryLevel_5_MinVddc_MASK 0xffffffff
1822#define DPM_TABLE_295__MemoryLevel_5_MinVddc__SHIFT 0x0
1823#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases_MASK 0xffffffff
1824#define DPM_TABLE_296__MemoryLevel_5_MinVddcPhases__SHIFT 0x0
1825#define DPM_TABLE_297__MemoryLevel_5_MinVddci_MASK 0xffffffff
1826#define DPM_TABLE_297__MemoryLevel_5_MinVddci__SHIFT 0x0
1827#define DPM_TABLE_298__MemoryLevel_5_MinMvdd_MASK 0xffffffff
1828#define DPM_TABLE_298__MemoryLevel_5_MinMvdd__SHIFT 0x0
1829#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency_MASK 0xffffffff
1830#define DPM_TABLE_299__MemoryLevel_5_MclkFrequency__SHIFT 0x0
1831#define DPM_TABLE_300__MemoryLevel_5_StutterEnable_MASK 0xff
1832#define DPM_TABLE_300__MemoryLevel_5_StutterEnable__SHIFT 0x0
1833#define DPM_TABLE_300__MemoryLevel_5_RttEnable_MASK 0xff00
1834#define DPM_TABLE_300__MemoryLevel_5_RttEnable__SHIFT 0x8
1835#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable_MASK 0xff0000
1836#define DPM_TABLE_300__MemoryLevel_5_EdcWriteEnable__SHIFT 0x10
1837#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable_MASK 0xff000000
1838#define DPM_TABLE_300__MemoryLevel_5_EdcReadEnable__SHIFT 0x18
1839#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity_MASK 0xff
1840#define DPM_TABLE_301__MemoryLevel_5_EnabledForActivity__SHIFT 0x0
1841#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle_MASK 0xff00
1842#define DPM_TABLE_301__MemoryLevel_5_EnabledForThrottle__SHIFT 0x8
1843#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio_MASK 0xff0000
1844#define DPM_TABLE_301__MemoryLevel_5_StrobeRatio__SHIFT 0x10
1845#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable_MASK 0xff000000
1846#define DPM_TABLE_301__MemoryLevel_5_StrobeEnable__SHIFT 0x18
1847#define DPM_TABLE_302__MemoryLevel_5_padding_MASK 0xff
1848#define DPM_TABLE_302__MemoryLevel_5_padding__SHIFT 0x0
1849#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst_MASK 0xff00
1850#define DPM_TABLE_302__MemoryLevel_5_VoltageDownHyst__SHIFT 0x8
1851#define DPM_TABLE_302__MemoryLevel_5_DownHyst_MASK 0xff0000
1852#define DPM_TABLE_302__MemoryLevel_5_DownHyst__SHIFT 0x10
1853#define DPM_TABLE_302__MemoryLevel_5_UpHyst_MASK 0xff000000
1854#define DPM_TABLE_302__MemoryLevel_5_UpHyst__SHIFT 0x18
1855#define DPM_TABLE_303__MemoryLevel_5_padding1_1_MASK 0xff
1856#define DPM_TABLE_303__MemoryLevel_5_padding1_1__SHIFT 0x0
1857#define DPM_TABLE_303__MemoryLevel_5_padding1_0_MASK 0xff00
1858#define DPM_TABLE_303__MemoryLevel_5_padding1_0__SHIFT 0x8
1859#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel_MASK 0xffff0000
1860#define DPM_TABLE_303__MemoryLevel_5_ActivityLevel__SHIFT 0x10
1861#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl_MASK 0xffffffff
1862#define DPM_TABLE_304__MemoryLevel_5_MpllFuncCntl__SHIFT 0x0
1863#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1_MASK 0xffffffff
1864#define DPM_TABLE_305__MemoryLevel_5_MpllFuncCntl_1__SHIFT 0x0
1865#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2_MASK 0xffffffff
1866#define DPM_TABLE_306__MemoryLevel_5_MpllFuncCntl_2__SHIFT 0x0
1867#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl_MASK 0xffffffff
1868#define DPM_TABLE_307__MemoryLevel_5_MpllAdFuncCntl__SHIFT 0x0
1869#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl_MASK 0xffffffff
1870#define DPM_TABLE_308__MemoryLevel_5_MpllDqFuncCntl__SHIFT 0x0
1871#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl_MASK 0xffffffff
1872#define DPM_TABLE_309__MemoryLevel_5_MclkPwrmgtCntl__SHIFT 0x0
1873#define DPM_TABLE_310__MemoryLevel_5_DllCntl_MASK 0xffffffff
1874#define DPM_TABLE_310__MemoryLevel_5_DllCntl__SHIFT 0x0
1875#define DPM_TABLE_311__MemoryLevel_5_MpllSs1_MASK 0xffffffff
1876#define DPM_TABLE_311__MemoryLevel_5_MpllSs1__SHIFT 0x0
1877#define DPM_TABLE_312__MemoryLevel_5_MpllSs2_MASK 0xffffffff
1878#define DPM_TABLE_312__MemoryLevel_5_MpllSs2__SHIFT 0x0
1879#define DPM_TABLE_313__LinkLevel_0_Padding_MASK 0xff
1880#define DPM_TABLE_313__LinkLevel_0_Padding__SHIFT 0x0
1881#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity_MASK 0xff00
1882#define DPM_TABLE_313__LinkLevel_0_EnabledForActivity__SHIFT 0x8
1883#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount_MASK 0xff0000
1884#define DPM_TABLE_313__LinkLevel_0_PcieLaneCount__SHIFT 0x10
1885#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
1886#define DPM_TABLE_313__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
1887#define DPM_TABLE_314__LinkLevel_0_DownThreshold_MASK 0xffffffff
1888#define DPM_TABLE_314__LinkLevel_0_DownThreshold__SHIFT 0x0
1889#define DPM_TABLE_315__LinkLevel_0_UpThreshold_MASK 0xffffffff
1890#define DPM_TABLE_315__LinkLevel_0_UpThreshold__SHIFT 0x0
1891#define DPM_TABLE_316__LinkLevel_0_Reserved_MASK 0xffffffff
1892#define DPM_TABLE_316__LinkLevel_0_Reserved__SHIFT 0x0
1893#define DPM_TABLE_317__LinkLevel_1_Padding_MASK 0xff
1894#define DPM_TABLE_317__LinkLevel_1_Padding__SHIFT 0x0
1895#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity_MASK 0xff00
1896#define DPM_TABLE_317__LinkLevel_1_EnabledForActivity__SHIFT 0x8
1897#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount_MASK 0xff0000
1898#define DPM_TABLE_317__LinkLevel_1_PcieLaneCount__SHIFT 0x10
1899#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
1900#define DPM_TABLE_317__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
1901#define DPM_TABLE_318__LinkLevel_1_DownThreshold_MASK 0xffffffff
1902#define DPM_TABLE_318__LinkLevel_1_DownThreshold__SHIFT 0x0
1903#define DPM_TABLE_319__LinkLevel_1_UpThreshold_MASK 0xffffffff
1904#define DPM_TABLE_319__LinkLevel_1_UpThreshold__SHIFT 0x0
1905#define DPM_TABLE_320__LinkLevel_1_Reserved_MASK 0xffffffff
1906#define DPM_TABLE_320__LinkLevel_1_Reserved__SHIFT 0x0
1907#define DPM_TABLE_321__LinkLevel_2_Padding_MASK 0xff
1908#define DPM_TABLE_321__LinkLevel_2_Padding__SHIFT 0x0
1909#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity_MASK 0xff00
1910#define DPM_TABLE_321__LinkLevel_2_EnabledForActivity__SHIFT 0x8
1911#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount_MASK 0xff0000
1912#define DPM_TABLE_321__LinkLevel_2_PcieLaneCount__SHIFT 0x10
1913#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
1914#define DPM_TABLE_321__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
1915#define DPM_TABLE_322__LinkLevel_2_DownThreshold_MASK 0xffffffff
1916#define DPM_TABLE_322__LinkLevel_2_DownThreshold__SHIFT 0x0
1917#define DPM_TABLE_323__LinkLevel_2_UpThreshold_MASK 0xffffffff
1918#define DPM_TABLE_323__LinkLevel_2_UpThreshold__SHIFT 0x0
1919#define DPM_TABLE_324__LinkLevel_2_Reserved_MASK 0xffffffff
1920#define DPM_TABLE_324__LinkLevel_2_Reserved__SHIFT 0x0
1921#define DPM_TABLE_325__LinkLevel_3_Padding_MASK 0xff
1922#define DPM_TABLE_325__LinkLevel_3_Padding__SHIFT 0x0
1923#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity_MASK 0xff00
1924#define DPM_TABLE_325__LinkLevel_3_EnabledForActivity__SHIFT 0x8
1925#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount_MASK 0xff0000
1926#define DPM_TABLE_325__LinkLevel_3_PcieLaneCount__SHIFT 0x10
1927#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
1928#define DPM_TABLE_325__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
1929#define DPM_TABLE_326__LinkLevel_3_DownThreshold_MASK 0xffffffff
1930#define DPM_TABLE_326__LinkLevel_3_DownThreshold__SHIFT 0x0
1931#define DPM_TABLE_327__LinkLevel_3_UpThreshold_MASK 0xffffffff
1932#define DPM_TABLE_327__LinkLevel_3_UpThreshold__SHIFT 0x0
1933#define DPM_TABLE_328__LinkLevel_3_Reserved_MASK 0xffffffff
1934#define DPM_TABLE_328__LinkLevel_3_Reserved__SHIFT 0x0
1935#define DPM_TABLE_329__LinkLevel_4_Padding_MASK 0xff
1936#define DPM_TABLE_329__LinkLevel_4_Padding__SHIFT 0x0
1937#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity_MASK 0xff00
1938#define DPM_TABLE_329__LinkLevel_4_EnabledForActivity__SHIFT 0x8
1939#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount_MASK 0xff0000
1940#define DPM_TABLE_329__LinkLevel_4_PcieLaneCount__SHIFT 0x10
1941#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
1942#define DPM_TABLE_329__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
1943#define DPM_TABLE_330__LinkLevel_4_DownThreshold_MASK 0xffffffff
1944#define DPM_TABLE_330__LinkLevel_4_DownThreshold__SHIFT 0x0
1945#define DPM_TABLE_331__LinkLevel_4_UpThreshold_MASK 0xffffffff
1946#define DPM_TABLE_331__LinkLevel_4_UpThreshold__SHIFT 0x0
1947#define DPM_TABLE_332__LinkLevel_4_Reserved_MASK 0xffffffff
1948#define DPM_TABLE_332__LinkLevel_4_Reserved__SHIFT 0x0
1949#define DPM_TABLE_333__LinkLevel_5_Padding_MASK 0xff
1950#define DPM_TABLE_333__LinkLevel_5_Padding__SHIFT 0x0
1951#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity_MASK 0xff00
1952#define DPM_TABLE_333__LinkLevel_5_EnabledForActivity__SHIFT 0x8
1953#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount_MASK 0xff0000
1954#define DPM_TABLE_333__LinkLevel_5_PcieLaneCount__SHIFT 0x10
1955#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
1956#define DPM_TABLE_333__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
1957#define DPM_TABLE_334__LinkLevel_5_DownThreshold_MASK 0xffffffff
1958#define DPM_TABLE_334__LinkLevel_5_DownThreshold__SHIFT 0x0
1959#define DPM_TABLE_335__LinkLevel_5_UpThreshold_MASK 0xffffffff
1960#define DPM_TABLE_335__LinkLevel_5_UpThreshold__SHIFT 0x0
1961#define DPM_TABLE_336__LinkLevel_5_Reserved_MASK 0xffffffff
1962#define DPM_TABLE_336__LinkLevel_5_Reserved__SHIFT 0x0
1963#define DPM_TABLE_337__LinkLevel_6_Padding_MASK 0xff
1964#define DPM_TABLE_337__LinkLevel_6_Padding__SHIFT 0x0
1965#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity_MASK 0xff00
1966#define DPM_TABLE_337__LinkLevel_6_EnabledForActivity__SHIFT 0x8
1967#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount_MASK 0xff0000
1968#define DPM_TABLE_337__LinkLevel_6_PcieLaneCount__SHIFT 0x10
1969#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
1970#define DPM_TABLE_337__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
1971#define DPM_TABLE_338__LinkLevel_6_DownThreshold_MASK 0xffffffff
1972#define DPM_TABLE_338__LinkLevel_6_DownThreshold__SHIFT 0x0
1973#define DPM_TABLE_339__LinkLevel_6_UpThreshold_MASK 0xffffffff
1974#define DPM_TABLE_339__LinkLevel_6_UpThreshold__SHIFT 0x0
1975#define DPM_TABLE_340__LinkLevel_6_Reserved_MASK 0xffffffff
1976#define DPM_TABLE_340__LinkLevel_6_Reserved__SHIFT 0x0
1977#define DPM_TABLE_341__LinkLevel_7_Padding_MASK 0xff
1978#define DPM_TABLE_341__LinkLevel_7_Padding__SHIFT 0x0
1979#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity_MASK 0xff00
1980#define DPM_TABLE_341__LinkLevel_7_EnabledForActivity__SHIFT 0x8
1981#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount_MASK 0xff0000
1982#define DPM_TABLE_341__LinkLevel_7_PcieLaneCount__SHIFT 0x10
1983#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
1984#define DPM_TABLE_341__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
1985#define DPM_TABLE_342__LinkLevel_7_DownThreshold_MASK 0xffffffff
1986#define DPM_TABLE_342__LinkLevel_7_DownThreshold__SHIFT 0x0
1987#define DPM_TABLE_343__LinkLevel_7_UpThreshold_MASK 0xffffffff
1988#define DPM_TABLE_343__LinkLevel_7_UpThreshold__SHIFT 0x0
1989#define DPM_TABLE_344__LinkLevel_7_Reserved_MASK 0xffffffff
1990#define DPM_TABLE_344__LinkLevel_7_Reserved__SHIFT 0x0
1991#define DPM_TABLE_345__ACPILevel_Flags_MASK 0xffffffff
1992#define DPM_TABLE_345__ACPILevel_Flags__SHIFT 0x0
1993#define DPM_TABLE_346__ACPILevel_MinVddc_MASK 0xffffffff
1994#define DPM_TABLE_346__ACPILevel_MinVddc__SHIFT 0x0
1995#define DPM_TABLE_347__ACPILevel_MinVddcPhases_MASK 0xffffffff
1996#define DPM_TABLE_347__ACPILevel_MinVddcPhases__SHIFT 0x0
1997#define DPM_TABLE_348__ACPILevel_SclkFrequency_MASK 0xffffffff
1998#define DPM_TABLE_348__ACPILevel_SclkFrequency__SHIFT 0x0
1999#define DPM_TABLE_349__ACPILevel_padding_MASK 0xff
2000#define DPM_TABLE_349__ACPILevel_padding__SHIFT 0x0
2001#define DPM_TABLE_349__ACPILevel_DeepSleepDivId_MASK 0xff00
2002#define DPM_TABLE_349__ACPILevel_DeepSleepDivId__SHIFT 0x8
2003#define DPM_TABLE_349__ACPILevel_DisplayWatermark_MASK 0xff0000
2004#define DPM_TABLE_349__ACPILevel_DisplayWatermark__SHIFT 0x10
2005#define DPM_TABLE_349__ACPILevel_SclkDid_MASK 0xff000000
2006#define DPM_TABLE_349__ACPILevel_SclkDid__SHIFT 0x18
2007#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
2008#define DPM_TABLE_350__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
2009#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
2010#define DPM_TABLE_351__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
2011#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
2012#define DPM_TABLE_352__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
2013#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
2014#define DPM_TABLE_353__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
2015#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
2016#define DPM_TABLE_354__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
2017#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
2018#define DPM_TABLE_355__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
2019#define DPM_TABLE_356__ACPILevel_CcPwrDynRm_MASK 0xffffffff
2020#define DPM_TABLE_356__ACPILevel_CcPwrDynRm__SHIFT 0x0
2021#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
2022#define DPM_TABLE_357__ACPILevel_CcPwrDynRm1__SHIFT 0x0
2023#define DPM_TABLE_358__UvdLevel_0_VclkFrequency_MASK 0xffffffff
2024#define DPM_TABLE_358__UvdLevel_0_VclkFrequency__SHIFT 0x0
2025#define DPM_TABLE_359__UvdLevel_0_DclkFrequency_MASK 0xffffffff
2026#define DPM_TABLE_359__UvdLevel_0_DclkFrequency__SHIFT 0x0
2027#define DPM_TABLE_360__UvdLevel_0_VclkDivider_MASK 0xff
2028#define DPM_TABLE_360__UvdLevel_0_VclkDivider__SHIFT 0x0
2029#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases_MASK 0xff00
2030#define DPM_TABLE_360__UvdLevel_0_MinVddcPhases__SHIFT 0x8
2031#define DPM_TABLE_360__UvdLevel_0_MinVddc_MASK 0xffff0000
2032#define DPM_TABLE_360__UvdLevel_0_MinVddc__SHIFT 0x10
2033#define DPM_TABLE_361__UvdLevel_0_padding_2_MASK 0xff
2034#define DPM_TABLE_361__UvdLevel_0_padding_2__SHIFT 0x0
2035#define DPM_TABLE_361__UvdLevel_0_padding_1_MASK 0xff00
2036#define DPM_TABLE_361__UvdLevel_0_padding_1__SHIFT 0x8
2037#define DPM_TABLE_361__UvdLevel_0_padding_0_MASK 0xff0000
2038#define DPM_TABLE_361__UvdLevel_0_padding_0__SHIFT 0x10
2039#define DPM_TABLE_361__UvdLevel_0_DclkDivider_MASK 0xff000000
2040#define DPM_TABLE_361__UvdLevel_0_DclkDivider__SHIFT 0x18
2041#define DPM_TABLE_362__UvdLevel_1_VclkFrequency_MASK 0xffffffff
2042#define DPM_TABLE_362__UvdLevel_1_VclkFrequency__SHIFT 0x0
2043#define DPM_TABLE_363__UvdLevel_1_DclkFrequency_MASK 0xffffffff
2044#define DPM_TABLE_363__UvdLevel_1_DclkFrequency__SHIFT 0x0
2045#define DPM_TABLE_364__UvdLevel_1_VclkDivider_MASK 0xff
2046#define DPM_TABLE_364__UvdLevel_1_VclkDivider__SHIFT 0x0
2047#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases_MASK 0xff00
2048#define DPM_TABLE_364__UvdLevel_1_MinVddcPhases__SHIFT 0x8
2049#define DPM_TABLE_364__UvdLevel_1_MinVddc_MASK 0xffff0000
2050#define DPM_TABLE_364__UvdLevel_1_MinVddc__SHIFT 0x10
2051#define DPM_TABLE_365__UvdLevel_1_padding_2_MASK 0xff
2052#define DPM_TABLE_365__UvdLevel_1_padding_2__SHIFT 0x0
2053#define DPM_TABLE_365__UvdLevel_1_padding_1_MASK 0xff00
2054#define DPM_TABLE_365__UvdLevel_1_padding_1__SHIFT 0x8
2055#define DPM_TABLE_365__UvdLevel_1_padding_0_MASK 0xff0000
2056#define DPM_TABLE_365__UvdLevel_1_padding_0__SHIFT 0x10
2057#define DPM_TABLE_365__UvdLevel_1_DclkDivider_MASK 0xff000000
2058#define DPM_TABLE_365__UvdLevel_1_DclkDivider__SHIFT 0x18
2059#define DPM_TABLE_366__UvdLevel_2_VclkFrequency_MASK 0xffffffff
2060#define DPM_TABLE_366__UvdLevel_2_VclkFrequency__SHIFT 0x0
2061#define DPM_TABLE_367__UvdLevel_2_DclkFrequency_MASK 0xffffffff
2062#define DPM_TABLE_367__UvdLevel_2_DclkFrequency__SHIFT 0x0
2063#define DPM_TABLE_368__UvdLevel_2_VclkDivider_MASK 0xff
2064#define DPM_TABLE_368__UvdLevel_2_VclkDivider__SHIFT 0x0
2065#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases_MASK 0xff00
2066#define DPM_TABLE_368__UvdLevel_2_MinVddcPhases__SHIFT 0x8
2067#define DPM_TABLE_368__UvdLevel_2_MinVddc_MASK 0xffff0000
2068#define DPM_TABLE_368__UvdLevel_2_MinVddc__SHIFT 0x10
2069#define DPM_TABLE_369__UvdLevel_2_padding_2_MASK 0xff
2070#define DPM_TABLE_369__UvdLevel_2_padding_2__SHIFT 0x0
2071#define DPM_TABLE_369__UvdLevel_2_padding_1_MASK 0xff00
2072#define DPM_TABLE_369__UvdLevel_2_padding_1__SHIFT 0x8
2073#define DPM_TABLE_369__UvdLevel_2_padding_0_MASK 0xff0000
2074#define DPM_TABLE_369__UvdLevel_2_padding_0__SHIFT 0x10
2075#define DPM_TABLE_369__UvdLevel_2_DclkDivider_MASK 0xff000000
2076#define DPM_TABLE_369__UvdLevel_2_DclkDivider__SHIFT 0x18
2077#define DPM_TABLE_370__UvdLevel_3_VclkFrequency_MASK 0xffffffff
2078#define DPM_TABLE_370__UvdLevel_3_VclkFrequency__SHIFT 0x0
2079#define DPM_TABLE_371__UvdLevel_3_DclkFrequency_MASK 0xffffffff
2080#define DPM_TABLE_371__UvdLevel_3_DclkFrequency__SHIFT 0x0
2081#define DPM_TABLE_372__UvdLevel_3_VclkDivider_MASK 0xff
2082#define DPM_TABLE_372__UvdLevel_3_VclkDivider__SHIFT 0x0
2083#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases_MASK 0xff00
2084#define DPM_TABLE_372__UvdLevel_3_MinVddcPhases__SHIFT 0x8
2085#define DPM_TABLE_372__UvdLevel_3_MinVddc_MASK 0xffff0000
2086#define DPM_TABLE_372__UvdLevel_3_MinVddc__SHIFT 0x10
2087#define DPM_TABLE_373__UvdLevel_3_padding_2_MASK 0xff
2088#define DPM_TABLE_373__UvdLevel_3_padding_2__SHIFT 0x0
2089#define DPM_TABLE_373__UvdLevel_3_padding_1_MASK 0xff00
2090#define DPM_TABLE_373__UvdLevel_3_padding_1__SHIFT 0x8
2091#define DPM_TABLE_373__UvdLevel_3_padding_0_MASK 0xff0000
2092#define DPM_TABLE_373__UvdLevel_3_padding_0__SHIFT 0x10
2093#define DPM_TABLE_373__UvdLevel_3_DclkDivider_MASK 0xff000000
2094#define DPM_TABLE_373__UvdLevel_3_DclkDivider__SHIFT 0x18
2095#define DPM_TABLE_374__UvdLevel_4_VclkFrequency_MASK 0xffffffff
2096#define DPM_TABLE_374__UvdLevel_4_VclkFrequency__SHIFT 0x0
2097#define DPM_TABLE_375__UvdLevel_4_DclkFrequency_MASK 0xffffffff
2098#define DPM_TABLE_375__UvdLevel_4_DclkFrequency__SHIFT 0x0
2099#define DPM_TABLE_376__UvdLevel_4_VclkDivider_MASK 0xff
2100#define DPM_TABLE_376__UvdLevel_4_VclkDivider__SHIFT 0x0
2101#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases_MASK 0xff00
2102#define DPM_TABLE_376__UvdLevel_4_MinVddcPhases__SHIFT 0x8
2103#define DPM_TABLE_376__UvdLevel_4_MinVddc_MASK 0xffff0000
2104#define DPM_TABLE_376__UvdLevel_4_MinVddc__SHIFT 0x10
2105#define DPM_TABLE_377__UvdLevel_4_padding_2_MASK 0xff
2106#define DPM_TABLE_377__UvdLevel_4_padding_2__SHIFT 0x0
2107#define DPM_TABLE_377__UvdLevel_4_padding_1_MASK 0xff00
2108#define DPM_TABLE_377__UvdLevel_4_padding_1__SHIFT 0x8
2109#define DPM_TABLE_377__UvdLevel_4_padding_0_MASK 0xff0000
2110#define DPM_TABLE_377__UvdLevel_4_padding_0__SHIFT 0x10
2111#define DPM_TABLE_377__UvdLevel_4_DclkDivider_MASK 0xff000000
2112#define DPM_TABLE_377__UvdLevel_4_DclkDivider__SHIFT 0x18
2113#define DPM_TABLE_378__UvdLevel_5_VclkFrequency_MASK 0xffffffff
2114#define DPM_TABLE_378__UvdLevel_5_VclkFrequency__SHIFT 0x0
2115#define DPM_TABLE_379__UvdLevel_5_DclkFrequency_MASK 0xffffffff
2116#define DPM_TABLE_379__UvdLevel_5_DclkFrequency__SHIFT 0x0
2117#define DPM_TABLE_380__UvdLevel_5_VclkDivider_MASK 0xff
2118#define DPM_TABLE_380__UvdLevel_5_VclkDivider__SHIFT 0x0
2119#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases_MASK 0xff00
2120#define DPM_TABLE_380__UvdLevel_5_MinVddcPhases__SHIFT 0x8
2121#define DPM_TABLE_380__UvdLevel_5_MinVddc_MASK 0xffff0000
2122#define DPM_TABLE_380__UvdLevel_5_MinVddc__SHIFT 0x10
2123#define DPM_TABLE_381__UvdLevel_5_padding_2_MASK 0xff
2124#define DPM_TABLE_381__UvdLevel_5_padding_2__SHIFT 0x0
2125#define DPM_TABLE_381__UvdLevel_5_padding_1_MASK 0xff00
2126#define DPM_TABLE_381__UvdLevel_5_padding_1__SHIFT 0x8
2127#define DPM_TABLE_381__UvdLevel_5_padding_0_MASK 0xff0000
2128#define DPM_TABLE_381__UvdLevel_5_padding_0__SHIFT 0x10
2129#define DPM_TABLE_381__UvdLevel_5_DclkDivider_MASK 0xff000000
2130#define DPM_TABLE_381__UvdLevel_5_DclkDivider__SHIFT 0x18
2131#define DPM_TABLE_382__UvdLevel_6_VclkFrequency_MASK 0xffffffff
2132#define DPM_TABLE_382__UvdLevel_6_VclkFrequency__SHIFT 0x0
2133#define DPM_TABLE_383__UvdLevel_6_DclkFrequency_MASK 0xffffffff
2134#define DPM_TABLE_383__UvdLevel_6_DclkFrequency__SHIFT 0x0
2135#define DPM_TABLE_384__UvdLevel_6_VclkDivider_MASK 0xff
2136#define DPM_TABLE_384__UvdLevel_6_VclkDivider__SHIFT 0x0
2137#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases_MASK 0xff00
2138#define DPM_TABLE_384__UvdLevel_6_MinVddcPhases__SHIFT 0x8
2139#define DPM_TABLE_384__UvdLevel_6_MinVddc_MASK 0xffff0000
2140#define DPM_TABLE_384__UvdLevel_6_MinVddc__SHIFT 0x10
2141#define DPM_TABLE_385__UvdLevel_6_padding_2_MASK 0xff
2142#define DPM_TABLE_385__UvdLevel_6_padding_2__SHIFT 0x0
2143#define DPM_TABLE_385__UvdLevel_6_padding_1_MASK 0xff00
2144#define DPM_TABLE_385__UvdLevel_6_padding_1__SHIFT 0x8
2145#define DPM_TABLE_385__UvdLevel_6_padding_0_MASK 0xff0000
2146#define DPM_TABLE_385__UvdLevel_6_padding_0__SHIFT 0x10
2147#define DPM_TABLE_385__UvdLevel_6_DclkDivider_MASK 0xff000000
2148#define DPM_TABLE_385__UvdLevel_6_DclkDivider__SHIFT 0x18
2149#define DPM_TABLE_386__UvdLevel_7_VclkFrequency_MASK 0xffffffff
2150#define DPM_TABLE_386__UvdLevel_7_VclkFrequency__SHIFT 0x0
2151#define DPM_TABLE_387__UvdLevel_7_DclkFrequency_MASK 0xffffffff
2152#define DPM_TABLE_387__UvdLevel_7_DclkFrequency__SHIFT 0x0
2153#define DPM_TABLE_388__UvdLevel_7_VclkDivider_MASK 0xff
2154#define DPM_TABLE_388__UvdLevel_7_VclkDivider__SHIFT 0x0
2155#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases_MASK 0xff00
2156#define DPM_TABLE_388__UvdLevel_7_MinVddcPhases__SHIFT 0x8
2157#define DPM_TABLE_388__UvdLevel_7_MinVddc_MASK 0xffff0000
2158#define DPM_TABLE_388__UvdLevel_7_MinVddc__SHIFT 0x10
2159#define DPM_TABLE_389__UvdLevel_7_padding_2_MASK 0xff
2160#define DPM_TABLE_389__UvdLevel_7_padding_2__SHIFT 0x0
2161#define DPM_TABLE_389__UvdLevel_7_padding_1_MASK 0xff00
2162#define DPM_TABLE_389__UvdLevel_7_padding_1__SHIFT 0x8
2163#define DPM_TABLE_389__UvdLevel_7_padding_0_MASK 0xff0000
2164#define DPM_TABLE_389__UvdLevel_7_padding_0__SHIFT 0x10
2165#define DPM_TABLE_389__UvdLevel_7_DclkDivider_MASK 0xff000000
2166#define DPM_TABLE_389__UvdLevel_7_DclkDivider__SHIFT 0x18
2167#define DPM_TABLE_390__VceLevel_0_Frequency_MASK 0xffffffff
2168#define DPM_TABLE_390__VceLevel_0_Frequency__SHIFT 0x0
2169#define DPM_TABLE_391__VceLevel_0_Divider_MASK 0xff
2170#define DPM_TABLE_391__VceLevel_0_Divider__SHIFT 0x0
2171#define DPM_TABLE_391__VceLevel_0_MinPhases_MASK 0xff00
2172#define DPM_TABLE_391__VceLevel_0_MinPhases__SHIFT 0x8
2173#define DPM_TABLE_391__VceLevel_0_MinVoltage_MASK 0xffff0000
2174#define DPM_TABLE_391__VceLevel_0_MinVoltage__SHIFT 0x10
2175#define DPM_TABLE_392__VceLevel_1_Frequency_MASK 0xffffffff
2176#define DPM_TABLE_392__VceLevel_1_Frequency__SHIFT 0x0
2177#define DPM_TABLE_393__VceLevel_1_Divider_MASK 0xff
2178#define DPM_TABLE_393__VceLevel_1_Divider__SHIFT 0x0
2179#define DPM_TABLE_393__VceLevel_1_MinPhases_MASK 0xff00
2180#define DPM_TABLE_393__VceLevel_1_MinPhases__SHIFT 0x8
2181#define DPM_TABLE_393__VceLevel_1_MinVoltage_MASK 0xffff0000
2182#define DPM_TABLE_393__VceLevel_1_MinVoltage__SHIFT 0x10
2183#define DPM_TABLE_394__VceLevel_2_Frequency_MASK 0xffffffff
2184#define DPM_TABLE_394__VceLevel_2_Frequency__SHIFT 0x0
2185#define DPM_TABLE_395__VceLevel_2_Divider_MASK 0xff
2186#define DPM_TABLE_395__VceLevel_2_Divider__SHIFT 0x0
2187#define DPM_TABLE_395__VceLevel_2_MinPhases_MASK 0xff00
2188#define DPM_TABLE_395__VceLevel_2_MinPhases__SHIFT 0x8
2189#define DPM_TABLE_395__VceLevel_2_MinVoltage_MASK 0xffff0000
2190#define DPM_TABLE_395__VceLevel_2_MinVoltage__SHIFT 0x10
2191#define DPM_TABLE_396__VceLevel_3_Frequency_MASK 0xffffffff
2192#define DPM_TABLE_396__VceLevel_3_Frequency__SHIFT 0x0
2193#define DPM_TABLE_397__VceLevel_3_Divider_MASK 0xff
2194#define DPM_TABLE_397__VceLevel_3_Divider__SHIFT 0x0
2195#define DPM_TABLE_397__VceLevel_3_MinPhases_MASK 0xff00
2196#define DPM_TABLE_397__VceLevel_3_MinPhases__SHIFT 0x8
2197#define DPM_TABLE_397__VceLevel_3_MinVoltage_MASK 0xffff0000
2198#define DPM_TABLE_397__VceLevel_3_MinVoltage__SHIFT 0x10
2199#define DPM_TABLE_398__VceLevel_4_Frequency_MASK 0xffffffff
2200#define DPM_TABLE_398__VceLevel_4_Frequency__SHIFT 0x0
2201#define DPM_TABLE_399__VceLevel_4_Divider_MASK 0xff
2202#define DPM_TABLE_399__VceLevel_4_Divider__SHIFT 0x0
2203#define DPM_TABLE_399__VceLevel_4_MinPhases_MASK 0xff00
2204#define DPM_TABLE_399__VceLevel_4_MinPhases__SHIFT 0x8
2205#define DPM_TABLE_399__VceLevel_4_MinVoltage_MASK 0xffff0000
2206#define DPM_TABLE_399__VceLevel_4_MinVoltage__SHIFT 0x10
2207#define DPM_TABLE_400__VceLevel_5_Frequency_MASK 0xffffffff
2208#define DPM_TABLE_400__VceLevel_5_Frequency__SHIFT 0x0
2209#define DPM_TABLE_401__VceLevel_5_Divider_MASK 0xff
2210#define DPM_TABLE_401__VceLevel_5_Divider__SHIFT 0x0
2211#define DPM_TABLE_401__VceLevel_5_MinPhases_MASK 0xff00
2212#define DPM_TABLE_401__VceLevel_5_MinPhases__SHIFT 0x8
2213#define DPM_TABLE_401__VceLevel_5_MinVoltage_MASK 0xffff0000
2214#define DPM_TABLE_401__VceLevel_5_MinVoltage__SHIFT 0x10
2215#define DPM_TABLE_402__VceLevel_6_Frequency_MASK 0xffffffff
2216#define DPM_TABLE_402__VceLevel_6_Frequency__SHIFT 0x0
2217#define DPM_TABLE_403__VceLevel_6_Divider_MASK 0xff
2218#define DPM_TABLE_403__VceLevel_6_Divider__SHIFT 0x0
2219#define DPM_TABLE_403__VceLevel_6_MinPhases_MASK 0xff00
2220#define DPM_TABLE_403__VceLevel_6_MinPhases__SHIFT 0x8
2221#define DPM_TABLE_403__VceLevel_6_MinVoltage_MASK 0xffff0000
2222#define DPM_TABLE_403__VceLevel_6_MinVoltage__SHIFT 0x10
2223#define DPM_TABLE_404__VceLevel_7_Frequency_MASK 0xffffffff
2224#define DPM_TABLE_404__VceLevel_7_Frequency__SHIFT 0x0
2225#define DPM_TABLE_405__VceLevel_7_Divider_MASK 0xff
2226#define DPM_TABLE_405__VceLevel_7_Divider__SHIFT 0x0
2227#define DPM_TABLE_405__VceLevel_7_MinPhases_MASK 0xff00
2228#define DPM_TABLE_405__VceLevel_7_MinPhases__SHIFT 0x8
2229#define DPM_TABLE_405__VceLevel_7_MinVoltage_MASK 0xffff0000
2230#define DPM_TABLE_405__VceLevel_7_MinVoltage__SHIFT 0x10
2231#define DPM_TABLE_406__AcpLevel_0_Frequency_MASK 0xffffffff
2232#define DPM_TABLE_406__AcpLevel_0_Frequency__SHIFT 0x0
2233#define DPM_TABLE_407__AcpLevel_0_Divider_MASK 0xff
2234#define DPM_TABLE_407__AcpLevel_0_Divider__SHIFT 0x0
2235#define DPM_TABLE_407__AcpLevel_0_MinPhases_MASK 0xff00
2236#define DPM_TABLE_407__AcpLevel_0_MinPhases__SHIFT 0x8
2237#define DPM_TABLE_407__AcpLevel_0_MinVoltage_MASK 0xffff0000
2238#define DPM_TABLE_407__AcpLevel_0_MinVoltage__SHIFT 0x10
2239#define DPM_TABLE_408__AcpLevel_1_Frequency_MASK 0xffffffff
2240#define DPM_TABLE_408__AcpLevel_1_Frequency__SHIFT 0x0
2241#define DPM_TABLE_409__AcpLevel_1_Divider_MASK 0xff
2242#define DPM_TABLE_409__AcpLevel_1_Divider__SHIFT 0x0
2243#define DPM_TABLE_409__AcpLevel_1_MinPhases_MASK 0xff00
2244#define DPM_TABLE_409__AcpLevel_1_MinPhases__SHIFT 0x8
2245#define DPM_TABLE_409__AcpLevel_1_MinVoltage_MASK 0xffff0000
2246#define DPM_TABLE_409__AcpLevel_1_MinVoltage__SHIFT 0x10
2247#define DPM_TABLE_410__AcpLevel_2_Frequency_MASK 0xffffffff
2248#define DPM_TABLE_410__AcpLevel_2_Frequency__SHIFT 0x0
2249#define DPM_TABLE_411__AcpLevel_2_Divider_MASK 0xff
2250#define DPM_TABLE_411__AcpLevel_2_Divider__SHIFT 0x0
2251#define DPM_TABLE_411__AcpLevel_2_MinPhases_MASK 0xff00
2252#define DPM_TABLE_411__AcpLevel_2_MinPhases__SHIFT 0x8
2253#define DPM_TABLE_411__AcpLevel_2_MinVoltage_MASK 0xffff0000
2254#define DPM_TABLE_411__AcpLevel_2_MinVoltage__SHIFT 0x10
2255#define DPM_TABLE_412__AcpLevel_3_Frequency_MASK 0xffffffff
2256#define DPM_TABLE_412__AcpLevel_3_Frequency__SHIFT 0x0
2257#define DPM_TABLE_413__AcpLevel_3_Divider_MASK 0xff
2258#define DPM_TABLE_413__AcpLevel_3_Divider__SHIFT 0x0
2259#define DPM_TABLE_413__AcpLevel_3_MinPhases_MASK 0xff00
2260#define DPM_TABLE_413__AcpLevel_3_MinPhases__SHIFT 0x8
2261#define DPM_TABLE_413__AcpLevel_3_MinVoltage_MASK 0xffff0000
2262#define DPM_TABLE_413__AcpLevel_3_MinVoltage__SHIFT 0x10
2263#define DPM_TABLE_414__AcpLevel_4_Frequency_MASK 0xffffffff
2264#define DPM_TABLE_414__AcpLevel_4_Frequency__SHIFT 0x0
2265#define DPM_TABLE_415__AcpLevel_4_Divider_MASK 0xff
2266#define DPM_TABLE_415__AcpLevel_4_Divider__SHIFT 0x0
2267#define DPM_TABLE_415__AcpLevel_4_MinPhases_MASK 0xff00
2268#define DPM_TABLE_415__AcpLevel_4_MinPhases__SHIFT 0x8
2269#define DPM_TABLE_415__AcpLevel_4_MinVoltage_MASK 0xffff0000
2270#define DPM_TABLE_415__AcpLevel_4_MinVoltage__SHIFT 0x10
2271#define DPM_TABLE_416__AcpLevel_5_Frequency_MASK 0xffffffff
2272#define DPM_TABLE_416__AcpLevel_5_Frequency__SHIFT 0x0
2273#define DPM_TABLE_417__AcpLevel_5_Divider_MASK 0xff
2274#define DPM_TABLE_417__AcpLevel_5_Divider__SHIFT 0x0
2275#define DPM_TABLE_417__AcpLevel_5_MinPhases_MASK 0xff00
2276#define DPM_TABLE_417__AcpLevel_5_MinPhases__SHIFT 0x8
2277#define DPM_TABLE_417__AcpLevel_5_MinVoltage_MASK 0xffff0000
2278#define DPM_TABLE_417__AcpLevel_5_MinVoltage__SHIFT 0x10
2279#define DPM_TABLE_418__AcpLevel_6_Frequency_MASK 0xffffffff
2280#define DPM_TABLE_418__AcpLevel_6_Frequency__SHIFT 0x0
2281#define DPM_TABLE_419__AcpLevel_6_Divider_MASK 0xff
2282#define DPM_TABLE_419__AcpLevel_6_Divider__SHIFT 0x0
2283#define DPM_TABLE_419__AcpLevel_6_MinPhases_MASK 0xff00
2284#define DPM_TABLE_419__AcpLevel_6_MinPhases__SHIFT 0x8
2285#define DPM_TABLE_419__AcpLevel_6_MinVoltage_MASK 0xffff0000
2286#define DPM_TABLE_419__AcpLevel_6_MinVoltage__SHIFT 0x10
2287#define DPM_TABLE_420__AcpLevel_7_Frequency_MASK 0xffffffff
2288#define DPM_TABLE_420__AcpLevel_7_Frequency__SHIFT 0x0
2289#define DPM_TABLE_421__AcpLevel_7_Divider_MASK 0xff
2290#define DPM_TABLE_421__AcpLevel_7_Divider__SHIFT 0x0
2291#define DPM_TABLE_421__AcpLevel_7_MinPhases_MASK 0xff00
2292#define DPM_TABLE_421__AcpLevel_7_MinPhases__SHIFT 0x8
2293#define DPM_TABLE_421__AcpLevel_7_MinVoltage_MASK 0xffff0000
2294#define DPM_TABLE_421__AcpLevel_7_MinVoltage__SHIFT 0x10
2295#define DPM_TABLE_422__SamuLevel_0_Frequency_MASK 0xffffffff
2296#define DPM_TABLE_422__SamuLevel_0_Frequency__SHIFT 0x0
2297#define DPM_TABLE_423__SamuLevel_0_Divider_MASK 0xff
2298#define DPM_TABLE_423__SamuLevel_0_Divider__SHIFT 0x0
2299#define DPM_TABLE_423__SamuLevel_0_MinPhases_MASK 0xff00
2300#define DPM_TABLE_423__SamuLevel_0_MinPhases__SHIFT 0x8
2301#define DPM_TABLE_423__SamuLevel_0_MinVoltage_MASK 0xffff0000
2302#define DPM_TABLE_423__SamuLevel_0_MinVoltage__SHIFT 0x10
2303#define DPM_TABLE_424__SamuLevel_1_Frequency_MASK 0xffffffff
2304#define DPM_TABLE_424__SamuLevel_1_Frequency__SHIFT 0x0
2305#define DPM_TABLE_425__SamuLevel_1_Divider_MASK 0xff
2306#define DPM_TABLE_425__SamuLevel_1_Divider__SHIFT 0x0
2307#define DPM_TABLE_425__SamuLevel_1_MinPhases_MASK 0xff00
2308#define DPM_TABLE_425__SamuLevel_1_MinPhases__SHIFT 0x8
2309#define DPM_TABLE_425__SamuLevel_1_MinVoltage_MASK 0xffff0000
2310#define DPM_TABLE_425__SamuLevel_1_MinVoltage__SHIFT 0x10
2311#define DPM_TABLE_426__SamuLevel_2_Frequency_MASK 0xffffffff
2312#define DPM_TABLE_426__SamuLevel_2_Frequency__SHIFT 0x0
2313#define DPM_TABLE_427__SamuLevel_2_Divider_MASK 0xff
2314#define DPM_TABLE_427__SamuLevel_2_Divider__SHIFT 0x0
2315#define DPM_TABLE_427__SamuLevel_2_MinPhases_MASK 0xff00
2316#define DPM_TABLE_427__SamuLevel_2_MinPhases__SHIFT 0x8
2317#define DPM_TABLE_427__SamuLevel_2_MinVoltage_MASK 0xffff0000
2318#define DPM_TABLE_427__SamuLevel_2_MinVoltage__SHIFT 0x10
2319#define DPM_TABLE_428__SamuLevel_3_Frequency_MASK 0xffffffff
2320#define DPM_TABLE_428__SamuLevel_3_Frequency__SHIFT 0x0
2321#define DPM_TABLE_429__SamuLevel_3_Divider_MASK 0xff
2322#define DPM_TABLE_429__SamuLevel_3_Divider__SHIFT 0x0
2323#define DPM_TABLE_429__SamuLevel_3_MinPhases_MASK 0xff00
2324#define DPM_TABLE_429__SamuLevel_3_MinPhases__SHIFT 0x8
2325#define DPM_TABLE_429__SamuLevel_3_MinVoltage_MASK 0xffff0000
2326#define DPM_TABLE_429__SamuLevel_3_MinVoltage__SHIFT 0x10
2327#define DPM_TABLE_430__SamuLevel_4_Frequency_MASK 0xffffffff
2328#define DPM_TABLE_430__SamuLevel_4_Frequency__SHIFT 0x0
2329#define DPM_TABLE_431__SamuLevel_4_Divider_MASK 0xff
2330#define DPM_TABLE_431__SamuLevel_4_Divider__SHIFT 0x0
2331#define DPM_TABLE_431__SamuLevel_4_MinPhases_MASK 0xff00
2332#define DPM_TABLE_431__SamuLevel_4_MinPhases__SHIFT 0x8
2333#define DPM_TABLE_431__SamuLevel_4_MinVoltage_MASK 0xffff0000
2334#define DPM_TABLE_431__SamuLevel_4_MinVoltage__SHIFT 0x10
2335#define DPM_TABLE_432__SamuLevel_5_Frequency_MASK 0xffffffff
2336#define DPM_TABLE_432__SamuLevel_5_Frequency__SHIFT 0x0
2337#define DPM_TABLE_433__SamuLevel_5_Divider_MASK 0xff
2338#define DPM_TABLE_433__SamuLevel_5_Divider__SHIFT 0x0
2339#define DPM_TABLE_433__SamuLevel_5_MinPhases_MASK 0xff00
2340#define DPM_TABLE_433__SamuLevel_5_MinPhases__SHIFT 0x8
2341#define DPM_TABLE_433__SamuLevel_5_MinVoltage_MASK 0xffff0000
2342#define DPM_TABLE_433__SamuLevel_5_MinVoltage__SHIFT 0x10
2343#define DPM_TABLE_434__SamuLevel_6_Frequency_MASK 0xffffffff
2344#define DPM_TABLE_434__SamuLevel_6_Frequency__SHIFT 0x0
2345#define DPM_TABLE_435__SamuLevel_6_Divider_MASK 0xff
2346#define DPM_TABLE_435__SamuLevel_6_Divider__SHIFT 0x0
2347#define DPM_TABLE_435__SamuLevel_6_MinPhases_MASK 0xff00
2348#define DPM_TABLE_435__SamuLevel_6_MinPhases__SHIFT 0x8
2349#define DPM_TABLE_435__SamuLevel_6_MinVoltage_MASK 0xffff0000
2350#define DPM_TABLE_435__SamuLevel_6_MinVoltage__SHIFT 0x10
2351#define DPM_TABLE_436__SamuLevel_7_Frequency_MASK 0xffffffff
2352#define DPM_TABLE_436__SamuLevel_7_Frequency__SHIFT 0x0
2353#define DPM_TABLE_437__SamuLevel_7_Divider_MASK 0xff
2354#define DPM_TABLE_437__SamuLevel_7_Divider__SHIFT 0x0
2355#define DPM_TABLE_437__SamuLevel_7_MinPhases_MASK 0xff00
2356#define DPM_TABLE_437__SamuLevel_7_MinPhases__SHIFT 0x8
2357#define DPM_TABLE_437__SamuLevel_7_MinVoltage_MASK 0xffff0000
2358#define DPM_TABLE_437__SamuLevel_7_MinVoltage__SHIFT 0x10
2359#define DPM_TABLE_438__Ulv_CcPwrDynRm_MASK 0xffffffff
2360#define DPM_TABLE_438__Ulv_CcPwrDynRm__SHIFT 0x0
2361#define DPM_TABLE_439__Ulv_CcPwrDynRm1_MASK 0xffffffff
2362#define DPM_TABLE_439__Ulv_CcPwrDynRm1__SHIFT 0x0
2363#define DPM_TABLE_440__Ulv_VddcPhase_MASK 0xff
2364#define DPM_TABLE_440__Ulv_VddcPhase__SHIFT 0x0
2365#define DPM_TABLE_440__Ulv_VddcOffsetVid_MASK 0xff00
2366#define DPM_TABLE_440__Ulv_VddcOffsetVid__SHIFT 0x8
2367#define DPM_TABLE_440__Ulv_VddcOffset_MASK 0xffff0000
2368#define DPM_TABLE_440__Ulv_VddcOffset__SHIFT 0x10
2369#define DPM_TABLE_441__Ulv_Reserved_MASK 0xffffffff
2370#define DPM_TABLE_441__Ulv_Reserved__SHIFT 0x0
2371#define DPM_TABLE_442__SclkStepSize_MASK 0xffffffff
2372#define DPM_TABLE_442__SclkStepSize__SHIFT 0x0
2373#define DPM_TABLE_443__Smio_0_MASK 0xffffffff
2374#define DPM_TABLE_443__Smio_0__SHIFT 0x0
2375#define DPM_TABLE_444__Smio_1_MASK 0xffffffff
2376#define DPM_TABLE_444__Smio_1__SHIFT 0x0
2377#define DPM_TABLE_445__Smio_2_MASK 0xffffffff
2378#define DPM_TABLE_445__Smio_2__SHIFT 0x0
2379#define DPM_TABLE_446__Smio_3_MASK 0xffffffff
2380#define DPM_TABLE_446__Smio_3__SHIFT 0x0
2381#define DPM_TABLE_447__Smio_4_MASK 0xffffffff
2382#define DPM_TABLE_447__Smio_4__SHIFT 0x0
2383#define DPM_TABLE_448__Smio_5_MASK 0xffffffff
2384#define DPM_TABLE_448__Smio_5__SHIFT 0x0
2385#define DPM_TABLE_449__Smio_6_MASK 0xffffffff
2386#define DPM_TABLE_449__Smio_6__SHIFT 0x0
2387#define DPM_TABLE_450__Smio_7_MASK 0xffffffff
2388#define DPM_TABLE_450__Smio_7__SHIFT 0x0
2389#define DPM_TABLE_451__Smio_8_MASK 0xffffffff
2390#define DPM_TABLE_451__Smio_8__SHIFT 0x0
2391#define DPM_TABLE_452__Smio_9_MASK 0xffffffff
2392#define DPM_TABLE_452__Smio_9__SHIFT 0x0
2393#define DPM_TABLE_453__Smio_10_MASK 0xffffffff
2394#define DPM_TABLE_453__Smio_10__SHIFT 0x0
2395#define DPM_TABLE_454__Smio_11_MASK 0xffffffff
2396#define DPM_TABLE_454__Smio_11__SHIFT 0x0
2397#define DPM_TABLE_455__Smio_12_MASK 0xffffffff
2398#define DPM_TABLE_455__Smio_12__SHIFT 0x0
2399#define DPM_TABLE_456__Smio_13_MASK 0xffffffff
2400#define DPM_TABLE_456__Smio_13__SHIFT 0x0
2401#define DPM_TABLE_457__Smio_14_MASK 0xffffffff
2402#define DPM_TABLE_457__Smio_14__SHIFT 0x0
2403#define DPM_TABLE_458__Smio_15_MASK 0xffffffff
2404#define DPM_TABLE_458__Smio_15__SHIFT 0x0
2405#define DPM_TABLE_459__Smio_16_MASK 0xffffffff
2406#define DPM_TABLE_459__Smio_16__SHIFT 0x0
2407#define DPM_TABLE_460__Smio_17_MASK 0xffffffff
2408#define DPM_TABLE_460__Smio_17__SHIFT 0x0
2409#define DPM_TABLE_461__Smio_18_MASK 0xffffffff
2410#define DPM_TABLE_461__Smio_18__SHIFT 0x0
2411#define DPM_TABLE_462__Smio_19_MASK 0xffffffff
2412#define DPM_TABLE_462__Smio_19__SHIFT 0x0
2413#define DPM_TABLE_463__Smio_20_MASK 0xffffffff
2414#define DPM_TABLE_463__Smio_20__SHIFT 0x0
2415#define DPM_TABLE_464__Smio_21_MASK 0xffffffff
2416#define DPM_TABLE_464__Smio_21__SHIFT 0x0
2417#define DPM_TABLE_465__Smio_22_MASK 0xffffffff
2418#define DPM_TABLE_465__Smio_22__SHIFT 0x0
2419#define DPM_TABLE_466__Smio_23_MASK 0xffffffff
2420#define DPM_TABLE_466__Smio_23__SHIFT 0x0
2421#define DPM_TABLE_467__Smio_24_MASK 0xffffffff
2422#define DPM_TABLE_467__Smio_24__SHIFT 0x0
2423#define DPM_TABLE_468__Smio_25_MASK 0xffffffff
2424#define DPM_TABLE_468__Smio_25__SHIFT 0x0
2425#define DPM_TABLE_469__Smio_26_MASK 0xffffffff
2426#define DPM_TABLE_469__Smio_26__SHIFT 0x0
2427#define DPM_TABLE_470__Smio_27_MASK 0xffffffff
2428#define DPM_TABLE_470__Smio_27__SHIFT 0x0
2429#define DPM_TABLE_471__Smio_28_MASK 0xffffffff
2430#define DPM_TABLE_471__Smio_28__SHIFT 0x0
2431#define DPM_TABLE_472__Smio_29_MASK 0xffffffff
2432#define DPM_TABLE_472__Smio_29__SHIFT 0x0
2433#define DPM_TABLE_473__Smio_30_MASK 0xffffffff
2434#define DPM_TABLE_473__Smio_30__SHIFT 0x0
2435#define DPM_TABLE_474__Smio_31_MASK 0xffffffff
2436#define DPM_TABLE_474__Smio_31__SHIFT 0x0
2437#define DPM_TABLE_475__SamuBootLevel_MASK 0xff
2438#define DPM_TABLE_475__SamuBootLevel__SHIFT 0x0
2439#define DPM_TABLE_475__AcpBootLevel_MASK 0xff00
2440#define DPM_TABLE_475__AcpBootLevel__SHIFT 0x8
2441#define DPM_TABLE_475__VceBootLevel_MASK 0xff0000
2442#define DPM_TABLE_475__VceBootLevel__SHIFT 0x10
2443#define DPM_TABLE_475__UvdBootLevel_MASK 0xff000000
2444#define DPM_TABLE_475__UvdBootLevel__SHIFT 0x18
2445#define DPM_TABLE_476__SAMUInterval_MASK 0xff
2446#define DPM_TABLE_476__SAMUInterval__SHIFT 0x0
2447#define DPM_TABLE_476__ACPInterval_MASK 0xff00
2448#define DPM_TABLE_476__ACPInterval__SHIFT 0x8
2449#define DPM_TABLE_476__VCEInterval_MASK 0xff0000
2450#define DPM_TABLE_476__VCEInterval__SHIFT 0x10
2451#define DPM_TABLE_476__UVDInterval_MASK 0xff000000
2452#define DPM_TABLE_476__UVDInterval__SHIFT 0x18
2453#define DPM_TABLE_477__GraphicsInterval_MASK 0xff
2454#define DPM_TABLE_477__GraphicsInterval__SHIFT 0x0
2455#define DPM_TABLE_477__GraphicsThermThrottleEnable_MASK 0xff00
2456#define DPM_TABLE_477__GraphicsThermThrottleEnable__SHIFT 0x8
2457#define DPM_TABLE_477__GraphicsVoltageChangeEnable_MASK 0xff0000
2458#define DPM_TABLE_477__GraphicsVoltageChangeEnable__SHIFT 0x10
2459#define DPM_TABLE_477__GraphicsBootLevel_MASK 0xff000000
2460#define DPM_TABLE_477__GraphicsBootLevel__SHIFT 0x18
2461#define DPM_TABLE_478__TemperatureLimitHigh_MASK 0xffff
2462#define DPM_TABLE_478__TemperatureLimitHigh__SHIFT 0x0
2463#define DPM_TABLE_478__ThermalInterval_MASK 0xff0000
2464#define DPM_TABLE_478__ThermalInterval__SHIFT 0x10
2465#define DPM_TABLE_478__VoltageInterval_MASK 0xff000000
2466#define DPM_TABLE_478__VoltageInterval__SHIFT 0x18
2467#define DPM_TABLE_479__MemoryVoltageChangeEnable_MASK 0xff
2468#define DPM_TABLE_479__MemoryVoltageChangeEnable__SHIFT 0x0
2469#define DPM_TABLE_479__MemoryBootLevel_MASK 0xff00
2470#define DPM_TABLE_479__MemoryBootLevel__SHIFT 0x8
2471#define DPM_TABLE_479__TemperatureLimitLow_MASK 0xffff0000
2472#define DPM_TABLE_479__TemperatureLimitLow__SHIFT 0x10
2473#define DPM_TABLE_480__VddcVddciDelta_MASK 0xffff
2474#define DPM_TABLE_480__VddcVddciDelta__SHIFT 0x0
2475#define DPM_TABLE_480__MemoryThermThrottleEnable_MASK 0xff0000
2476#define DPM_TABLE_480__MemoryThermThrottleEnable__SHIFT 0x10
2477#define DPM_TABLE_480__MemoryInterval_MASK 0xff000000
2478#define DPM_TABLE_480__MemoryInterval__SHIFT 0x18
2479#define DPM_TABLE_481__PhaseResponseTime_MASK 0xffff
2480#define DPM_TABLE_481__PhaseResponseTime__SHIFT 0x0
2481#define DPM_TABLE_481__VoltageResponseTime_MASK 0xffff0000
2482#define DPM_TABLE_481__VoltageResponseTime__SHIFT 0x10
2483#define DPM_TABLE_482__DTEMode_MASK 0xff
2484#define DPM_TABLE_482__DTEMode__SHIFT 0x0
2485#define DPM_TABLE_482__DTEInterval_MASK 0xff00
2486#define DPM_TABLE_482__DTEInterval__SHIFT 0x8
2487#define DPM_TABLE_482__PCIeGenInterval_MASK 0xff0000
2488#define DPM_TABLE_482__PCIeGenInterval__SHIFT 0x10
2489#define DPM_TABLE_482__PCIeBootLinkLevel_MASK 0xff000000
2490#define DPM_TABLE_482__PCIeBootLinkLevel__SHIFT 0x18
2491#define DPM_TABLE_483__ThermGpio_MASK 0xff
2492#define DPM_TABLE_483__ThermGpio__SHIFT 0x0
2493#define DPM_TABLE_483__AcDcGpio_MASK 0xff00
2494#define DPM_TABLE_483__AcDcGpio__SHIFT 0x8
2495#define DPM_TABLE_483__VRHotGpio_MASK 0xff0000
2496#define DPM_TABLE_483__VRHotGpio__SHIFT 0x10
2497#define DPM_TABLE_483__SVI2Enable_MASK 0xff000000
2498#define DPM_TABLE_483__SVI2Enable__SHIFT 0x18
2499#define DPM_TABLE_484__DisplayCac_MASK 0xffffffff
2500#define DPM_TABLE_484__DisplayCac__SHIFT 0x0
2501#define DPM_TABLE_485__NomPwr_MASK 0xffff
2502#define DPM_TABLE_485__NomPwr__SHIFT 0x0
2503#define DPM_TABLE_485__MaxPwr_MASK 0xffff0000
2504#define DPM_TABLE_485__MaxPwr__SHIFT 0x10
2505#define DPM_TABLE_486__FpsLowThreshold_MASK 0xffff
2506#define DPM_TABLE_486__FpsLowThreshold__SHIFT 0x0
2507#define DPM_TABLE_486__FpsHighThreshold_MASK 0xffff0000
2508#define DPM_TABLE_486__FpsHighThreshold__SHIFT 0x10
2509#define DPM_TABLE_487__BAPMTI_R_0_1_0_MASK 0xffff
2510#define DPM_TABLE_487__BAPMTI_R_0_1_0__SHIFT 0x0
2511#define DPM_TABLE_487__BAPMTI_R_0_0_0_MASK 0xffff0000
2512#define DPM_TABLE_487__BAPMTI_R_0_0_0__SHIFT 0x10
2513#define DPM_TABLE_488__BAPMTI_R_1_0_0_MASK 0xffff
2514#define DPM_TABLE_488__BAPMTI_R_1_0_0__SHIFT 0x0
2515#define DPM_TABLE_488__BAPMTI_R_0_2_0_MASK 0xffff0000
2516#define DPM_TABLE_488__BAPMTI_R_0_2_0__SHIFT 0x10
2517#define DPM_TABLE_489__BAPMTI_R_1_2_0_MASK 0xffff
2518#define DPM_TABLE_489__BAPMTI_R_1_2_0__SHIFT 0x0
2519#define DPM_TABLE_489__BAPMTI_R_1_1_0_MASK 0xffff0000
2520#define DPM_TABLE_489__BAPMTI_R_1_1_0__SHIFT 0x10
2521#define DPM_TABLE_490__BAPMTI_R_2_1_0_MASK 0xffff
2522#define DPM_TABLE_490__BAPMTI_R_2_1_0__SHIFT 0x0
2523#define DPM_TABLE_490__BAPMTI_R_2_0_0_MASK 0xffff0000
2524#define DPM_TABLE_490__BAPMTI_R_2_0_0__SHIFT 0x10
2525#define DPM_TABLE_491__BAPMTI_R_3_0_0_MASK 0xffff
2526#define DPM_TABLE_491__BAPMTI_R_3_0_0__SHIFT 0x0
2527#define DPM_TABLE_491__BAPMTI_R_2_2_0_MASK 0xffff0000
2528#define DPM_TABLE_491__BAPMTI_R_2_2_0__SHIFT 0x10
2529#define DPM_TABLE_492__BAPMTI_R_3_2_0_MASK 0xffff
2530#define DPM_TABLE_492__BAPMTI_R_3_2_0__SHIFT 0x0
2531#define DPM_TABLE_492__BAPMTI_R_3_1_0_MASK 0xffff0000
2532#define DPM_TABLE_492__BAPMTI_R_3_1_0__SHIFT 0x10
2533#define DPM_TABLE_493__BAPMTI_R_4_1_0_MASK 0xffff
2534#define DPM_TABLE_493__BAPMTI_R_4_1_0__SHIFT 0x0
2535#define DPM_TABLE_493__BAPMTI_R_4_0_0_MASK 0xffff0000
2536#define DPM_TABLE_493__BAPMTI_R_4_0_0__SHIFT 0x10
2537#define DPM_TABLE_494__BAPMTI_RC_0_0_0_MASK 0xffff
2538#define DPM_TABLE_494__BAPMTI_RC_0_0_0__SHIFT 0x0
2539#define DPM_TABLE_494__BAPMTI_R_4_2_0_MASK 0xffff0000
2540#define DPM_TABLE_494__BAPMTI_R_4_2_0__SHIFT 0x10
2541#define DPM_TABLE_495__BAPMTI_RC_0_2_0_MASK 0xffff
2542#define DPM_TABLE_495__BAPMTI_RC_0_2_0__SHIFT 0x0
2543#define DPM_TABLE_495__BAPMTI_RC_0_1_0_MASK 0xffff0000
2544#define DPM_TABLE_495__BAPMTI_RC_0_1_0__SHIFT 0x10
2545#define DPM_TABLE_496__BAPMTI_RC_1_1_0_MASK 0xffff
2546#define DPM_TABLE_496__BAPMTI_RC_1_1_0__SHIFT 0x0
2547#define DPM_TABLE_496__BAPMTI_RC_1_0_0_MASK 0xffff0000
2548#define DPM_TABLE_496__BAPMTI_RC_1_0_0__SHIFT 0x10
2549#define DPM_TABLE_497__BAPMTI_RC_2_0_0_MASK 0xffff
2550#define DPM_TABLE_497__BAPMTI_RC_2_0_0__SHIFT 0x0
2551#define DPM_TABLE_497__BAPMTI_RC_1_2_0_MASK 0xffff0000
2552#define DPM_TABLE_497__BAPMTI_RC_1_2_0__SHIFT 0x10
2553#define DPM_TABLE_498__BAPMTI_RC_2_2_0_MASK 0xffff
2554#define DPM_TABLE_498__BAPMTI_RC_2_2_0__SHIFT 0x0
2555#define DPM_TABLE_498__BAPMTI_RC_2_1_0_MASK 0xffff0000
2556#define DPM_TABLE_498__BAPMTI_RC_2_1_0__SHIFT 0x10
2557#define DPM_TABLE_499__BAPMTI_RC_3_1_0_MASK 0xffff
2558#define DPM_TABLE_499__BAPMTI_RC_3_1_0__SHIFT 0x0
2559#define DPM_TABLE_499__BAPMTI_RC_3_0_0_MASK 0xffff0000
2560#define DPM_TABLE_499__BAPMTI_RC_3_0_0__SHIFT 0x10
2561#define DPM_TABLE_500__BAPMTI_RC_4_0_0_MASK 0xffff
2562#define DPM_TABLE_500__BAPMTI_RC_4_0_0__SHIFT 0x0
2563#define DPM_TABLE_500__BAPMTI_RC_3_2_0_MASK 0xffff0000
2564#define DPM_TABLE_500__BAPMTI_RC_3_2_0__SHIFT 0x10
2565#define DPM_TABLE_501__BAPMTI_RC_4_2_0_MASK 0xffff
2566#define DPM_TABLE_501__BAPMTI_RC_4_2_0__SHIFT 0x0
2567#define DPM_TABLE_501__BAPMTI_RC_4_1_0_MASK 0xffff0000
2568#define DPM_TABLE_501__BAPMTI_RC_4_1_0__SHIFT 0x10
2569#define DPM_TABLE_502__GpuTjHyst_MASK 0xff
2570#define DPM_TABLE_502__GpuTjHyst__SHIFT 0x0
2571#define DPM_TABLE_502__GpuTjMax_MASK 0xff00
2572#define DPM_TABLE_502__GpuTjMax__SHIFT 0x8
2573#define DPM_TABLE_502__DTETjOffset_MASK 0xff0000
2574#define DPM_TABLE_502__DTETjOffset__SHIFT 0x10
2575#define DPM_TABLE_502__DTEAmbientTempBase_MASK 0xff000000
2576#define DPM_TABLE_502__DTEAmbientTempBase__SHIFT 0x18
2577#define DPM_TABLE_503__BootVddci_MASK 0xffff
2578#define DPM_TABLE_503__BootVddci__SHIFT 0x0
2579#define DPM_TABLE_503__BootVddc_MASK 0xffff0000
2580#define DPM_TABLE_503__BootVddc__SHIFT 0x10
2581#define DPM_TABLE_504__padding_MASK 0xffff
2582#define DPM_TABLE_504__padding__SHIFT 0x0
2583#define DPM_TABLE_504__BootMVdd_MASK 0xffff0000
2584#define DPM_TABLE_504__BootMVdd__SHIFT 0x10
2585#define DPM_TABLE_505__DRAM_LOG_ADDR_H_MASK 0xffffffff
2586#define DPM_TABLE_505__DRAM_LOG_ADDR_H__SHIFT 0x0
2587#define DPM_TABLE_506__DRAM_LOG_ADDR_L_MASK 0xffffffff
2588#define DPM_TABLE_506__DRAM_LOG_ADDR_L__SHIFT 0x0
2589#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
2590#define DPM_TABLE_507__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
2591#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
2592#define DPM_TABLE_508__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
2593#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
2594#define DPM_TABLE_509__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
2595#define DPM_TABLE_510__BAPM_TEMP_GRADIENT_MASK 0xffffffff
2596#define DPM_TABLE_510__BAPM_TEMP_GRADIENT__SHIFT 0x0
2597#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
2598#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
2599#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
2600#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
2601#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
2602#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
2603#define TDC_STATUS__VDD_Boost_MASK 0xff
2604#define TDC_STATUS__VDD_Boost__SHIFT 0x0
2605#define TDC_STATUS__VDD_Throttle_MASK 0xff00
2606#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
2607#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
2608#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
2609#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
2610#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
2611#define TDC_MV_AVERAGE__IDD_MASK 0xffff
2612#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
2613#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
2614#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
2615#define TDC_VRM_LIMIT__IDD_MASK 0xffff
2616#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
2617#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
2618#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
2619#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
2620#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
2621#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
2622#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
2623#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
2624#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
2625#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
2626#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
2627#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
2628#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
2629#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
2630#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
2631#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
2632#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
2633#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
2634#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
2635#define FEATURE_STATUS__BAPM_ON_MASK 0x100
2636#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
2637#define FEATURE_STATUS__LPMX_ON_MASK 0x200
2638#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
2639#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
2640#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
2641#define FEATURE_STATUS__LHTC_ON_MASK 0x800
2642#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
2643#define FEATURE_STATUS__VPC_ON_MASK 0x1000
2644#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
2645#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
2646#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
2647#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
2648#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
2649#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
2650#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
2651#define FEATURE_STATUS__AVS_ON_MASK 0x10000
2652#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
2653#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
2654#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
2655#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
2656#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
2657#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
2658#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
2659#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
2660#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
2661#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
2662#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
2663#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
2664#define FEATURE_STATUS__RESERVED__SHIFT 0x16
2665#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
2666#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
2667#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
2668#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
2669#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
2670#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
2671#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
2672#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
2673#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
2674#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
2675#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
2676#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
2677#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
2678#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
2679#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
2680#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
2681#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
2682#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
2683#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
2684#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
2685#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
2686#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
2687#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
2688#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
2689#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
2690#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
2691#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
2692#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
2693#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
2694#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
2695#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
2696#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
2697#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
2698#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
2699#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
2700#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
2701#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
2702#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
2703#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
2704#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
2705#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
2706#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
2707#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
2708#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
2709#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
2710#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
2711#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
2712#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
2713#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
2714#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
2715#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming_MASK 0xffffffff
2716#define MCARB_DRAM_TIMING_TABLE_13__entries_0_4_McArbDramTiming__SHIFT 0x0
2717#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2_MASK 0xffffffff
2718#define MCARB_DRAM_TIMING_TABLE_14__entries_0_4_McArbDramTiming2__SHIFT 0x0
2719#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2_MASK 0xff
2720#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_2__SHIFT 0x0
2721#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1_MASK 0xff00
2722#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_1__SHIFT 0x8
2723#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0_MASK 0xff0000
2724#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_padding_0__SHIFT 0x10
2725#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime_MASK 0xff000000
2726#define MCARB_DRAM_TIMING_TABLE_15__entries_0_4_McArbBurstTime__SHIFT 0x18
2727#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming_MASK 0xffffffff
2728#define MCARB_DRAM_TIMING_TABLE_16__entries_0_5_McArbDramTiming__SHIFT 0x0
2729#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2_MASK 0xffffffff
2730#define MCARB_DRAM_TIMING_TABLE_17__entries_0_5_McArbDramTiming2__SHIFT 0x0
2731#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2_MASK 0xff
2732#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_2__SHIFT 0x0
2733#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1_MASK 0xff00
2734#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_1__SHIFT 0x8
2735#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0_MASK 0xff0000
2736#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_padding_0__SHIFT 0x10
2737#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime_MASK 0xff000000
2738#define MCARB_DRAM_TIMING_TABLE_18__entries_0_5_McArbBurstTime__SHIFT 0x18
2739#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming_MASK 0xffffffff
2740#define MCARB_DRAM_TIMING_TABLE_19__entries_1_0_McArbDramTiming__SHIFT 0x0
2741#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2_MASK 0xffffffff
2742#define MCARB_DRAM_TIMING_TABLE_20__entries_1_0_McArbDramTiming2__SHIFT 0x0
2743#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2_MASK 0xff
2744#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_2__SHIFT 0x0
2745#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1_MASK 0xff00
2746#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_1__SHIFT 0x8
2747#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0_MASK 0xff0000
2748#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_padding_0__SHIFT 0x10
2749#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime_MASK 0xff000000
2750#define MCARB_DRAM_TIMING_TABLE_21__entries_1_0_McArbBurstTime__SHIFT 0x18
2751#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming_MASK 0xffffffff
2752#define MCARB_DRAM_TIMING_TABLE_22__entries_1_1_McArbDramTiming__SHIFT 0x0
2753#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2_MASK 0xffffffff
2754#define MCARB_DRAM_TIMING_TABLE_23__entries_1_1_McArbDramTiming2__SHIFT 0x0
2755#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2_MASK 0xff
2756#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_2__SHIFT 0x0
2757#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1_MASK 0xff00
2758#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_1__SHIFT 0x8
2759#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0_MASK 0xff0000
2760#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_padding_0__SHIFT 0x10
2761#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime_MASK 0xff000000
2762#define MCARB_DRAM_TIMING_TABLE_24__entries_1_1_McArbBurstTime__SHIFT 0x18
2763#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming_MASK 0xffffffff
2764#define MCARB_DRAM_TIMING_TABLE_25__entries_1_2_McArbDramTiming__SHIFT 0x0
2765#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2_MASK 0xffffffff
2766#define MCARB_DRAM_TIMING_TABLE_26__entries_1_2_McArbDramTiming2__SHIFT 0x0
2767#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2_MASK 0xff
2768#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_2__SHIFT 0x0
2769#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1_MASK 0xff00
2770#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_1__SHIFT 0x8
2771#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0_MASK 0xff0000
2772#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_padding_0__SHIFT 0x10
2773#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime_MASK 0xff000000
2774#define MCARB_DRAM_TIMING_TABLE_27__entries_1_2_McArbBurstTime__SHIFT 0x18
2775#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming_MASK 0xffffffff
2776#define MCARB_DRAM_TIMING_TABLE_28__entries_1_3_McArbDramTiming__SHIFT 0x0
2777#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2_MASK 0xffffffff
2778#define MCARB_DRAM_TIMING_TABLE_29__entries_1_3_McArbDramTiming2__SHIFT 0x0
2779#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2_MASK 0xff
2780#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_2__SHIFT 0x0
2781#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1_MASK 0xff00
2782#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_1__SHIFT 0x8
2783#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0_MASK 0xff0000
2784#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_padding_0__SHIFT 0x10
2785#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime_MASK 0xff000000
2786#define MCARB_DRAM_TIMING_TABLE_30__entries_1_3_McArbBurstTime__SHIFT 0x18
2787#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming_MASK 0xffffffff
2788#define MCARB_DRAM_TIMING_TABLE_31__entries_1_4_McArbDramTiming__SHIFT 0x0
2789#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2_MASK 0xffffffff
2790#define MCARB_DRAM_TIMING_TABLE_32__entries_1_4_McArbDramTiming2__SHIFT 0x0
2791#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2_MASK 0xff
2792#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_2__SHIFT 0x0
2793#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1_MASK 0xff00
2794#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_1__SHIFT 0x8
2795#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0_MASK 0xff0000
2796#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_padding_0__SHIFT 0x10
2797#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime_MASK 0xff000000
2798#define MCARB_DRAM_TIMING_TABLE_33__entries_1_4_McArbBurstTime__SHIFT 0x18
2799#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming_MASK 0xffffffff
2800#define MCARB_DRAM_TIMING_TABLE_34__entries_1_5_McArbDramTiming__SHIFT 0x0
2801#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2_MASK 0xffffffff
2802#define MCARB_DRAM_TIMING_TABLE_35__entries_1_5_McArbDramTiming2__SHIFT 0x0
2803#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2_MASK 0xff
2804#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_2__SHIFT 0x0
2805#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1_MASK 0xff00
2806#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_1__SHIFT 0x8
2807#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0_MASK 0xff0000
2808#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_padding_0__SHIFT 0x10
2809#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime_MASK 0xff000000
2810#define MCARB_DRAM_TIMING_TABLE_36__entries_1_5_McArbBurstTime__SHIFT 0x18
2811#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming_MASK 0xffffffff
2812#define MCARB_DRAM_TIMING_TABLE_37__entries_2_0_McArbDramTiming__SHIFT 0x0
2813#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2_MASK 0xffffffff
2814#define MCARB_DRAM_TIMING_TABLE_38__entries_2_0_McArbDramTiming2__SHIFT 0x0
2815#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2_MASK 0xff
2816#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_2__SHIFT 0x0
2817#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1_MASK 0xff00
2818#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_1__SHIFT 0x8
2819#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0_MASK 0xff0000
2820#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_padding_0__SHIFT 0x10
2821#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime_MASK 0xff000000
2822#define MCARB_DRAM_TIMING_TABLE_39__entries_2_0_McArbBurstTime__SHIFT 0x18
2823#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming_MASK 0xffffffff
2824#define MCARB_DRAM_TIMING_TABLE_40__entries_2_1_McArbDramTiming__SHIFT 0x0
2825#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2_MASK 0xffffffff
2826#define MCARB_DRAM_TIMING_TABLE_41__entries_2_1_McArbDramTiming2__SHIFT 0x0
2827#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2_MASK 0xff
2828#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_2__SHIFT 0x0
2829#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1_MASK 0xff00
2830#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_1__SHIFT 0x8
2831#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0_MASK 0xff0000
2832#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_padding_0__SHIFT 0x10
2833#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime_MASK 0xff000000
2834#define MCARB_DRAM_TIMING_TABLE_42__entries_2_1_McArbBurstTime__SHIFT 0x18
2835#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming_MASK 0xffffffff
2836#define MCARB_DRAM_TIMING_TABLE_43__entries_2_2_McArbDramTiming__SHIFT 0x0
2837#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2_MASK 0xffffffff
2838#define MCARB_DRAM_TIMING_TABLE_44__entries_2_2_McArbDramTiming2__SHIFT 0x0
2839#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2_MASK 0xff
2840#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_2__SHIFT 0x0
2841#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1_MASK 0xff00
2842#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_1__SHIFT 0x8
2843#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0_MASK 0xff0000
2844#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_padding_0__SHIFT 0x10
2845#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime_MASK 0xff000000
2846#define MCARB_DRAM_TIMING_TABLE_45__entries_2_2_McArbBurstTime__SHIFT 0x18
2847#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming_MASK 0xffffffff
2848#define MCARB_DRAM_TIMING_TABLE_46__entries_2_3_McArbDramTiming__SHIFT 0x0
2849#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2_MASK 0xffffffff
2850#define MCARB_DRAM_TIMING_TABLE_47__entries_2_3_McArbDramTiming2__SHIFT 0x0
2851#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2_MASK 0xff
2852#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_2__SHIFT 0x0
2853#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1_MASK 0xff00
2854#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_1__SHIFT 0x8
2855#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0_MASK 0xff0000
2856#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_padding_0__SHIFT 0x10
2857#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime_MASK 0xff000000
2858#define MCARB_DRAM_TIMING_TABLE_48__entries_2_3_McArbBurstTime__SHIFT 0x18
2859#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming_MASK 0xffffffff
2860#define MCARB_DRAM_TIMING_TABLE_49__entries_2_4_McArbDramTiming__SHIFT 0x0
2861#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2_MASK 0xffffffff
2862#define MCARB_DRAM_TIMING_TABLE_50__entries_2_4_McArbDramTiming2__SHIFT 0x0
2863#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2_MASK 0xff
2864#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_2__SHIFT 0x0
2865#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1_MASK 0xff00
2866#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_1__SHIFT 0x8
2867#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0_MASK 0xff0000
2868#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_padding_0__SHIFT 0x10
2869#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime_MASK 0xff000000
2870#define MCARB_DRAM_TIMING_TABLE_51__entries_2_4_McArbBurstTime__SHIFT 0x18
2871#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming_MASK 0xffffffff
2872#define MCARB_DRAM_TIMING_TABLE_52__entries_2_5_McArbDramTiming__SHIFT 0x0
2873#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2_MASK 0xffffffff
2874#define MCARB_DRAM_TIMING_TABLE_53__entries_2_5_McArbDramTiming2__SHIFT 0x0
2875#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2_MASK 0xff
2876#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_2__SHIFT 0x0
2877#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1_MASK 0xff00
2878#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_1__SHIFT 0x8
2879#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0_MASK 0xff0000
2880#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_padding_0__SHIFT 0x10
2881#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime_MASK 0xff000000
2882#define MCARB_DRAM_TIMING_TABLE_54__entries_2_5_McArbBurstTime__SHIFT 0x18
2883#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming_MASK 0xffffffff
2884#define MCARB_DRAM_TIMING_TABLE_55__entries_3_0_McArbDramTiming__SHIFT 0x0
2885#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2_MASK 0xffffffff
2886#define MCARB_DRAM_TIMING_TABLE_56__entries_3_0_McArbDramTiming2__SHIFT 0x0
2887#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2_MASK 0xff
2888#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_2__SHIFT 0x0
2889#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1_MASK 0xff00
2890#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_1__SHIFT 0x8
2891#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0_MASK 0xff0000
2892#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_padding_0__SHIFT 0x10
2893#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime_MASK 0xff000000
2894#define MCARB_DRAM_TIMING_TABLE_57__entries_3_0_McArbBurstTime__SHIFT 0x18
2895#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming_MASK 0xffffffff
2896#define MCARB_DRAM_TIMING_TABLE_58__entries_3_1_McArbDramTiming__SHIFT 0x0
2897#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2_MASK 0xffffffff
2898#define MCARB_DRAM_TIMING_TABLE_59__entries_3_1_McArbDramTiming2__SHIFT 0x0
2899#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2_MASK 0xff
2900#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_2__SHIFT 0x0
2901#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1_MASK 0xff00
2902#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_1__SHIFT 0x8
2903#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0_MASK 0xff0000
2904#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_padding_0__SHIFT 0x10
2905#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime_MASK 0xff000000
2906#define MCARB_DRAM_TIMING_TABLE_60__entries_3_1_McArbBurstTime__SHIFT 0x18
2907#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming_MASK 0xffffffff
2908#define MCARB_DRAM_TIMING_TABLE_61__entries_3_2_McArbDramTiming__SHIFT 0x0
2909#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2_MASK 0xffffffff
2910#define MCARB_DRAM_TIMING_TABLE_62__entries_3_2_McArbDramTiming2__SHIFT 0x0
2911#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2_MASK 0xff
2912#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_2__SHIFT 0x0
2913#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1_MASK 0xff00
2914#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_1__SHIFT 0x8
2915#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0_MASK 0xff0000
2916#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_padding_0__SHIFT 0x10
2917#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime_MASK 0xff000000
2918#define MCARB_DRAM_TIMING_TABLE_63__entries_3_2_McArbBurstTime__SHIFT 0x18
2919#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming_MASK 0xffffffff
2920#define MCARB_DRAM_TIMING_TABLE_64__entries_3_3_McArbDramTiming__SHIFT 0x0
2921#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2_MASK 0xffffffff
2922#define MCARB_DRAM_TIMING_TABLE_65__entries_3_3_McArbDramTiming2__SHIFT 0x0
2923#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2_MASK 0xff
2924#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_2__SHIFT 0x0
2925#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1_MASK 0xff00
2926#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_1__SHIFT 0x8
2927#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0_MASK 0xff0000
2928#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_padding_0__SHIFT 0x10
2929#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime_MASK 0xff000000
2930#define MCARB_DRAM_TIMING_TABLE_66__entries_3_3_McArbBurstTime__SHIFT 0x18
2931#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming_MASK 0xffffffff
2932#define MCARB_DRAM_TIMING_TABLE_67__entries_3_4_McArbDramTiming__SHIFT 0x0
2933#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2_MASK 0xffffffff
2934#define MCARB_DRAM_TIMING_TABLE_68__entries_3_4_McArbDramTiming2__SHIFT 0x0
2935#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2_MASK 0xff
2936#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_2__SHIFT 0x0
2937#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1_MASK 0xff00
2938#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_1__SHIFT 0x8
2939#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0_MASK 0xff0000
2940#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_padding_0__SHIFT 0x10
2941#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime_MASK 0xff000000
2942#define MCARB_DRAM_TIMING_TABLE_69__entries_3_4_McArbBurstTime__SHIFT 0x18
2943#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming_MASK 0xffffffff
2944#define MCARB_DRAM_TIMING_TABLE_70__entries_3_5_McArbDramTiming__SHIFT 0x0
2945#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2_MASK 0xffffffff
2946#define MCARB_DRAM_TIMING_TABLE_71__entries_3_5_McArbDramTiming2__SHIFT 0x0
2947#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2_MASK 0xff
2948#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_2__SHIFT 0x0
2949#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1_MASK 0xff00
2950#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_1__SHIFT 0x8
2951#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0_MASK 0xff0000
2952#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_padding_0__SHIFT 0x10
2953#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime_MASK 0xff000000
2954#define MCARB_DRAM_TIMING_TABLE_72__entries_3_5_McArbBurstTime__SHIFT 0x18
2955#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming_MASK 0xffffffff
2956#define MCARB_DRAM_TIMING_TABLE_73__entries_4_0_McArbDramTiming__SHIFT 0x0
2957#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2_MASK 0xffffffff
2958#define MCARB_DRAM_TIMING_TABLE_74__entries_4_0_McArbDramTiming2__SHIFT 0x0
2959#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2_MASK 0xff
2960#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_2__SHIFT 0x0
2961#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1_MASK 0xff00
2962#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_1__SHIFT 0x8
2963#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0_MASK 0xff0000
2964#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_padding_0__SHIFT 0x10
2965#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime_MASK 0xff000000
2966#define MCARB_DRAM_TIMING_TABLE_75__entries_4_0_McArbBurstTime__SHIFT 0x18
2967#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming_MASK 0xffffffff
2968#define MCARB_DRAM_TIMING_TABLE_76__entries_4_1_McArbDramTiming__SHIFT 0x0
2969#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2_MASK 0xffffffff
2970#define MCARB_DRAM_TIMING_TABLE_77__entries_4_1_McArbDramTiming2__SHIFT 0x0
2971#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2_MASK 0xff
2972#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_2__SHIFT 0x0
2973#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1_MASK 0xff00
2974#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_1__SHIFT 0x8
2975#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0_MASK 0xff0000
2976#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_padding_0__SHIFT 0x10
2977#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime_MASK 0xff000000
2978#define MCARB_DRAM_TIMING_TABLE_78__entries_4_1_McArbBurstTime__SHIFT 0x18
2979#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming_MASK 0xffffffff
2980#define MCARB_DRAM_TIMING_TABLE_79__entries_4_2_McArbDramTiming__SHIFT 0x0
2981#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2_MASK 0xffffffff
2982#define MCARB_DRAM_TIMING_TABLE_80__entries_4_2_McArbDramTiming2__SHIFT 0x0
2983#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2_MASK 0xff
2984#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_2__SHIFT 0x0
2985#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1_MASK 0xff00
2986#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_1__SHIFT 0x8
2987#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0_MASK 0xff0000
2988#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_padding_0__SHIFT 0x10
2989#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime_MASK 0xff000000
2990#define MCARB_DRAM_TIMING_TABLE_81__entries_4_2_McArbBurstTime__SHIFT 0x18
2991#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming_MASK 0xffffffff
2992#define MCARB_DRAM_TIMING_TABLE_82__entries_4_3_McArbDramTiming__SHIFT 0x0
2993#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2_MASK 0xffffffff
2994#define MCARB_DRAM_TIMING_TABLE_83__entries_4_3_McArbDramTiming2__SHIFT 0x0
2995#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2_MASK 0xff
2996#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_2__SHIFT 0x0
2997#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1_MASK 0xff00
2998#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_1__SHIFT 0x8
2999#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0_MASK 0xff0000
3000#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_padding_0__SHIFT 0x10
3001#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime_MASK 0xff000000
3002#define MCARB_DRAM_TIMING_TABLE_84__entries_4_3_McArbBurstTime__SHIFT 0x18
3003#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming_MASK 0xffffffff
3004#define MCARB_DRAM_TIMING_TABLE_85__entries_4_4_McArbDramTiming__SHIFT 0x0
3005#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2_MASK 0xffffffff
3006#define MCARB_DRAM_TIMING_TABLE_86__entries_4_4_McArbDramTiming2__SHIFT 0x0
3007#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2_MASK 0xff
3008#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_2__SHIFT 0x0
3009#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1_MASK 0xff00
3010#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_1__SHIFT 0x8
3011#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0_MASK 0xff0000
3012#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_padding_0__SHIFT 0x10
3013#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime_MASK 0xff000000
3014#define MCARB_DRAM_TIMING_TABLE_87__entries_4_4_McArbBurstTime__SHIFT 0x18
3015#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming_MASK 0xffffffff
3016#define MCARB_DRAM_TIMING_TABLE_88__entries_4_5_McArbDramTiming__SHIFT 0x0
3017#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2_MASK 0xffffffff
3018#define MCARB_DRAM_TIMING_TABLE_89__entries_4_5_McArbDramTiming2__SHIFT 0x0
3019#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2_MASK 0xff
3020#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_2__SHIFT 0x0
3021#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1_MASK 0xff00
3022#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_1__SHIFT 0x8
3023#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0_MASK 0xff0000
3024#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_padding_0__SHIFT 0x10
3025#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime_MASK 0xff000000
3026#define MCARB_DRAM_TIMING_TABLE_90__entries_4_5_McArbBurstTime__SHIFT 0x18
3027#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming_MASK 0xffffffff
3028#define MCARB_DRAM_TIMING_TABLE_91__entries_5_0_McArbDramTiming__SHIFT 0x0
3029#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2_MASK 0xffffffff
3030#define MCARB_DRAM_TIMING_TABLE_92__entries_5_0_McArbDramTiming2__SHIFT 0x0
3031#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2_MASK 0xff
3032#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_2__SHIFT 0x0
3033#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1_MASK 0xff00
3034#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_1__SHIFT 0x8
3035#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0_MASK 0xff0000
3036#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_padding_0__SHIFT 0x10
3037#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime_MASK 0xff000000
3038#define MCARB_DRAM_TIMING_TABLE_93__entries_5_0_McArbBurstTime__SHIFT 0x18
3039#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming_MASK 0xffffffff
3040#define MCARB_DRAM_TIMING_TABLE_94__entries_5_1_McArbDramTiming__SHIFT 0x0
3041#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2_MASK 0xffffffff
3042#define MCARB_DRAM_TIMING_TABLE_95__entries_5_1_McArbDramTiming2__SHIFT 0x0
3043#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2_MASK 0xff
3044#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_2__SHIFT 0x0
3045#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1_MASK 0xff00
3046#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_1__SHIFT 0x8
3047#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0_MASK 0xff0000
3048#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_padding_0__SHIFT 0x10
3049#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime_MASK 0xff000000
3050#define MCARB_DRAM_TIMING_TABLE_96__entries_5_1_McArbBurstTime__SHIFT 0x18
3051#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming_MASK 0xffffffff
3052#define MCARB_DRAM_TIMING_TABLE_97__entries_5_2_McArbDramTiming__SHIFT 0x0
3053#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2_MASK 0xffffffff
3054#define MCARB_DRAM_TIMING_TABLE_98__entries_5_2_McArbDramTiming2__SHIFT 0x0
3055#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2_MASK 0xff
3056#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_2__SHIFT 0x0
3057#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1_MASK 0xff00
3058#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_1__SHIFT 0x8
3059#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0_MASK 0xff0000
3060#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_padding_0__SHIFT 0x10
3061#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime_MASK 0xff000000
3062#define MCARB_DRAM_TIMING_TABLE_99__entries_5_2_McArbBurstTime__SHIFT 0x18
3063#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming_MASK 0xffffffff
3064#define MCARB_DRAM_TIMING_TABLE_100__entries_5_3_McArbDramTiming__SHIFT 0x0
3065#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2_MASK 0xffffffff
3066#define MCARB_DRAM_TIMING_TABLE_101__entries_5_3_McArbDramTiming2__SHIFT 0x0
3067#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2_MASK 0xff
3068#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_2__SHIFT 0x0
3069#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1_MASK 0xff00
3070#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_1__SHIFT 0x8
3071#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0_MASK 0xff0000
3072#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_padding_0__SHIFT 0x10
3073#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime_MASK 0xff000000
3074#define MCARB_DRAM_TIMING_TABLE_102__entries_5_3_McArbBurstTime__SHIFT 0x18
3075#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming_MASK 0xffffffff
3076#define MCARB_DRAM_TIMING_TABLE_103__entries_5_4_McArbDramTiming__SHIFT 0x0
3077#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2_MASK 0xffffffff
3078#define MCARB_DRAM_TIMING_TABLE_104__entries_5_4_McArbDramTiming2__SHIFT 0x0
3079#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2_MASK 0xff
3080#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_2__SHIFT 0x0
3081#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1_MASK 0xff00
3082#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_1__SHIFT 0x8
3083#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0_MASK 0xff0000
3084#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_padding_0__SHIFT 0x10
3085#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime_MASK 0xff000000
3086#define MCARB_DRAM_TIMING_TABLE_105__entries_5_4_McArbBurstTime__SHIFT 0x18
3087#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming_MASK 0xffffffff
3088#define MCARB_DRAM_TIMING_TABLE_106__entries_5_5_McArbDramTiming__SHIFT 0x0
3089#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2_MASK 0xffffffff
3090#define MCARB_DRAM_TIMING_TABLE_107__entries_5_5_McArbDramTiming2__SHIFT 0x0
3091#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2_MASK 0xff
3092#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_2__SHIFT 0x0
3093#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1_MASK 0xff00
3094#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_1__SHIFT 0x8
3095#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0_MASK 0xff0000
3096#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_padding_0__SHIFT 0x10
3097#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime_MASK 0xff000000
3098#define MCARB_DRAM_TIMING_TABLE_108__entries_5_5_McArbBurstTime__SHIFT 0x18
3099#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming_MASK 0xffffffff
3100#define MCARB_DRAM_TIMING_TABLE_109__entries_6_0_McArbDramTiming__SHIFT 0x0
3101#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2_MASK 0xffffffff
3102#define MCARB_DRAM_TIMING_TABLE_110__entries_6_0_McArbDramTiming2__SHIFT 0x0
3103#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2_MASK 0xff
3104#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_2__SHIFT 0x0
3105#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1_MASK 0xff00
3106#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_1__SHIFT 0x8
3107#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0_MASK 0xff0000
3108#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_padding_0__SHIFT 0x10
3109#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime_MASK 0xff000000
3110#define MCARB_DRAM_TIMING_TABLE_111__entries_6_0_McArbBurstTime__SHIFT 0x18
3111#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming_MASK 0xffffffff
3112#define MCARB_DRAM_TIMING_TABLE_112__entries_6_1_McArbDramTiming__SHIFT 0x0
3113#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2_MASK 0xffffffff
3114#define MCARB_DRAM_TIMING_TABLE_113__entries_6_1_McArbDramTiming2__SHIFT 0x0
3115#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2_MASK 0xff
3116#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_2__SHIFT 0x0
3117#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1_MASK 0xff00
3118#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_1__SHIFT 0x8
3119#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0_MASK 0xff0000
3120#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_padding_0__SHIFT 0x10
3121#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime_MASK 0xff000000
3122#define MCARB_DRAM_TIMING_TABLE_114__entries_6_1_McArbBurstTime__SHIFT 0x18
3123#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming_MASK 0xffffffff
3124#define MCARB_DRAM_TIMING_TABLE_115__entries_6_2_McArbDramTiming__SHIFT 0x0
3125#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2_MASK 0xffffffff
3126#define MCARB_DRAM_TIMING_TABLE_116__entries_6_2_McArbDramTiming2__SHIFT 0x0
3127#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2_MASK 0xff
3128#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_2__SHIFT 0x0
3129#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1_MASK 0xff00
3130#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_1__SHIFT 0x8
3131#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0_MASK 0xff0000
3132#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_padding_0__SHIFT 0x10
3133#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime_MASK 0xff000000
3134#define MCARB_DRAM_TIMING_TABLE_117__entries_6_2_McArbBurstTime__SHIFT 0x18
3135#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming_MASK 0xffffffff
3136#define MCARB_DRAM_TIMING_TABLE_118__entries_6_3_McArbDramTiming__SHIFT 0x0
3137#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2_MASK 0xffffffff
3138#define MCARB_DRAM_TIMING_TABLE_119__entries_6_3_McArbDramTiming2__SHIFT 0x0
3139#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2_MASK 0xff
3140#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_2__SHIFT 0x0
3141#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1_MASK 0xff00
3142#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_1__SHIFT 0x8
3143#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0_MASK 0xff0000
3144#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_padding_0__SHIFT 0x10
3145#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime_MASK 0xff000000
3146#define MCARB_DRAM_TIMING_TABLE_120__entries_6_3_McArbBurstTime__SHIFT 0x18
3147#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming_MASK 0xffffffff
3148#define MCARB_DRAM_TIMING_TABLE_121__entries_6_4_McArbDramTiming__SHIFT 0x0
3149#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2_MASK 0xffffffff
3150#define MCARB_DRAM_TIMING_TABLE_122__entries_6_4_McArbDramTiming2__SHIFT 0x0
3151#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2_MASK 0xff
3152#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_2__SHIFT 0x0
3153#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1_MASK 0xff00
3154#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_1__SHIFT 0x8
3155#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0_MASK 0xff0000
3156#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_padding_0__SHIFT 0x10
3157#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime_MASK 0xff000000
3158#define MCARB_DRAM_TIMING_TABLE_123__entries_6_4_McArbBurstTime__SHIFT 0x18
3159#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming_MASK 0xffffffff
3160#define MCARB_DRAM_TIMING_TABLE_124__entries_6_5_McArbDramTiming__SHIFT 0x0
3161#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2_MASK 0xffffffff
3162#define MCARB_DRAM_TIMING_TABLE_125__entries_6_5_McArbDramTiming2__SHIFT 0x0
3163#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2_MASK 0xff
3164#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_2__SHIFT 0x0
3165#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1_MASK 0xff00
3166#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_1__SHIFT 0x8
3167#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0_MASK 0xff0000
3168#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_padding_0__SHIFT 0x10
3169#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime_MASK 0xff000000
3170#define MCARB_DRAM_TIMING_TABLE_126__entries_6_5_McArbBurstTime__SHIFT 0x18
3171#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming_MASK 0xffffffff
3172#define MCARB_DRAM_TIMING_TABLE_127__entries_7_0_McArbDramTiming__SHIFT 0x0
3173#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2_MASK 0xffffffff
3174#define MCARB_DRAM_TIMING_TABLE_128__entries_7_0_McArbDramTiming2__SHIFT 0x0
3175#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2_MASK 0xff
3176#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_2__SHIFT 0x0
3177#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1_MASK 0xff00
3178#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_1__SHIFT 0x8
3179#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0_MASK 0xff0000
3180#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_padding_0__SHIFT 0x10
3181#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime_MASK 0xff000000
3182#define MCARB_DRAM_TIMING_TABLE_129__entries_7_0_McArbBurstTime__SHIFT 0x18
3183#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming_MASK 0xffffffff
3184#define MCARB_DRAM_TIMING_TABLE_130__entries_7_1_McArbDramTiming__SHIFT 0x0
3185#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2_MASK 0xffffffff
3186#define MCARB_DRAM_TIMING_TABLE_131__entries_7_1_McArbDramTiming2__SHIFT 0x0
3187#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2_MASK 0xff
3188#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_2__SHIFT 0x0
3189#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1_MASK 0xff00
3190#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_1__SHIFT 0x8
3191#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0_MASK 0xff0000
3192#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_padding_0__SHIFT 0x10
3193#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime_MASK 0xff000000
3194#define MCARB_DRAM_TIMING_TABLE_132__entries_7_1_McArbBurstTime__SHIFT 0x18
3195#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming_MASK 0xffffffff
3196#define MCARB_DRAM_TIMING_TABLE_133__entries_7_2_McArbDramTiming__SHIFT 0x0
3197#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2_MASK 0xffffffff
3198#define MCARB_DRAM_TIMING_TABLE_134__entries_7_2_McArbDramTiming2__SHIFT 0x0
3199#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2_MASK 0xff
3200#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_2__SHIFT 0x0
3201#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1_MASK 0xff00
3202#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_1__SHIFT 0x8
3203#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0_MASK 0xff0000
3204#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_padding_0__SHIFT 0x10
3205#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime_MASK 0xff000000
3206#define MCARB_DRAM_TIMING_TABLE_135__entries_7_2_McArbBurstTime__SHIFT 0x18
3207#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming_MASK 0xffffffff
3208#define MCARB_DRAM_TIMING_TABLE_136__entries_7_3_McArbDramTiming__SHIFT 0x0
3209#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2_MASK 0xffffffff
3210#define MCARB_DRAM_TIMING_TABLE_137__entries_7_3_McArbDramTiming2__SHIFT 0x0
3211#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2_MASK 0xff
3212#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_2__SHIFT 0x0
3213#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1_MASK 0xff00
3214#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_1__SHIFT 0x8
3215#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0_MASK 0xff0000
3216#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_padding_0__SHIFT 0x10
3217#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime_MASK 0xff000000
3218#define MCARB_DRAM_TIMING_TABLE_138__entries_7_3_McArbBurstTime__SHIFT 0x18
3219#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming_MASK 0xffffffff
3220#define MCARB_DRAM_TIMING_TABLE_139__entries_7_4_McArbDramTiming__SHIFT 0x0
3221#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2_MASK 0xffffffff
3222#define MCARB_DRAM_TIMING_TABLE_140__entries_7_4_McArbDramTiming2__SHIFT 0x0
3223#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2_MASK 0xff
3224#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_2__SHIFT 0x0
3225#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1_MASK 0xff00
3226#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_1__SHIFT 0x8
3227#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0_MASK 0xff0000
3228#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_padding_0__SHIFT 0x10
3229#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime_MASK 0xff000000
3230#define MCARB_DRAM_TIMING_TABLE_141__entries_7_4_McArbBurstTime__SHIFT 0x18
3231#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming_MASK 0xffffffff
3232#define MCARB_DRAM_TIMING_TABLE_142__entries_7_5_McArbDramTiming__SHIFT 0x0
3233#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2_MASK 0xffffffff
3234#define MCARB_DRAM_TIMING_TABLE_143__entries_7_5_McArbDramTiming2__SHIFT 0x0
3235#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2_MASK 0xff
3236#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_2__SHIFT 0x0
3237#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1_MASK 0xff00
3238#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_1__SHIFT 0x8
3239#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0_MASK 0xff0000
3240#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_padding_0__SHIFT 0x10
3241#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime_MASK 0xff000000
3242#define MCARB_DRAM_TIMING_TABLE_144__entries_7_5_McArbBurstTime__SHIFT 0x18
3243#define MC_REGISTERS_TABLE_1__reserved_2_MASK 0xff
3244#define MC_REGISTERS_TABLE_1__reserved_2__SHIFT 0x0
3245#define MC_REGISTERS_TABLE_1__reserved_1_MASK 0xff00
3246#define MC_REGISTERS_TABLE_1__reserved_1__SHIFT 0x8
3247#define MC_REGISTERS_TABLE_1__reserved_0_MASK 0xff0000
3248#define MC_REGISTERS_TABLE_1__reserved_0__SHIFT 0x10
3249#define MC_REGISTERS_TABLE_1__last_MASK 0xff000000
3250#define MC_REGISTERS_TABLE_1__last__SHIFT 0x18
3251#define MC_REGISTERS_TABLE_2__address_0_s1_MASK 0xffff
3252#define MC_REGISTERS_TABLE_2__address_0_s1__SHIFT 0x0
3253#define MC_REGISTERS_TABLE_2__address_0_s0_MASK 0xffff0000
3254#define MC_REGISTERS_TABLE_2__address_0_s0__SHIFT 0x10
3255#define MC_REGISTERS_TABLE_3__address_1_s1_MASK 0xffff
3256#define MC_REGISTERS_TABLE_3__address_1_s1__SHIFT 0x0
3257#define MC_REGISTERS_TABLE_3__address_1_s0_MASK 0xffff0000
3258#define MC_REGISTERS_TABLE_3__address_1_s0__SHIFT 0x10
3259#define MC_REGISTERS_TABLE_4__address_2_s1_MASK 0xffff
3260#define MC_REGISTERS_TABLE_4__address_2_s1__SHIFT 0x0
3261#define MC_REGISTERS_TABLE_4__address_2_s0_MASK 0xffff0000
3262#define MC_REGISTERS_TABLE_4__address_2_s0__SHIFT 0x10
3263#define MC_REGISTERS_TABLE_5__address_3_s1_MASK 0xffff
3264#define MC_REGISTERS_TABLE_5__address_3_s1__SHIFT 0x0
3265#define MC_REGISTERS_TABLE_5__address_3_s0_MASK 0xffff0000
3266#define MC_REGISTERS_TABLE_5__address_3_s0__SHIFT 0x10
3267#define MC_REGISTERS_TABLE_6__address_4_s1_MASK 0xffff
3268#define MC_REGISTERS_TABLE_6__address_4_s1__SHIFT 0x0
3269#define MC_REGISTERS_TABLE_6__address_4_s0_MASK 0xffff0000
3270#define MC_REGISTERS_TABLE_6__address_4_s0__SHIFT 0x10
3271#define MC_REGISTERS_TABLE_7__address_5_s1_MASK 0xffff
3272#define MC_REGISTERS_TABLE_7__address_5_s1__SHIFT 0x0
3273#define MC_REGISTERS_TABLE_7__address_5_s0_MASK 0xffff0000
3274#define MC_REGISTERS_TABLE_7__address_5_s0__SHIFT 0x10
3275#define MC_REGISTERS_TABLE_8__address_6_s1_MASK 0xffff
3276#define MC_REGISTERS_TABLE_8__address_6_s1__SHIFT 0x0
3277#define MC_REGISTERS_TABLE_8__address_6_s0_MASK 0xffff0000
3278#define MC_REGISTERS_TABLE_8__address_6_s0__SHIFT 0x10
3279#define MC_REGISTERS_TABLE_9__address_7_s1_MASK 0xffff
3280#define MC_REGISTERS_TABLE_9__address_7_s1__SHIFT 0x0
3281#define MC_REGISTERS_TABLE_9__address_7_s0_MASK 0xffff0000
3282#define MC_REGISTERS_TABLE_9__address_7_s0__SHIFT 0x10
3283#define MC_REGISTERS_TABLE_10__address_8_s1_MASK 0xffff
3284#define MC_REGISTERS_TABLE_10__address_8_s1__SHIFT 0x0
3285#define MC_REGISTERS_TABLE_10__address_8_s0_MASK 0xffff0000
3286#define MC_REGISTERS_TABLE_10__address_8_s0__SHIFT 0x10
3287#define MC_REGISTERS_TABLE_11__address_9_s1_MASK 0xffff
3288#define MC_REGISTERS_TABLE_11__address_9_s1__SHIFT 0x0
3289#define MC_REGISTERS_TABLE_11__address_9_s0_MASK 0xffff0000
3290#define MC_REGISTERS_TABLE_11__address_9_s0__SHIFT 0x10
3291#define MC_REGISTERS_TABLE_12__address_10_s1_MASK 0xffff
3292#define MC_REGISTERS_TABLE_12__address_10_s1__SHIFT 0x0
3293#define MC_REGISTERS_TABLE_12__address_10_s0_MASK 0xffff0000
3294#define MC_REGISTERS_TABLE_12__address_10_s0__SHIFT 0x10
3295#define MC_REGISTERS_TABLE_13__address_11_s1_MASK 0xffff
3296#define MC_REGISTERS_TABLE_13__address_11_s1__SHIFT 0x0
3297#define MC_REGISTERS_TABLE_13__address_11_s0_MASK 0xffff0000
3298#define MC_REGISTERS_TABLE_13__address_11_s0__SHIFT 0x10
3299#define MC_REGISTERS_TABLE_14__address_12_s1_MASK 0xffff
3300#define MC_REGISTERS_TABLE_14__address_12_s1__SHIFT 0x0
3301#define MC_REGISTERS_TABLE_14__address_12_s0_MASK 0xffff0000
3302#define MC_REGISTERS_TABLE_14__address_12_s0__SHIFT 0x10
3303#define MC_REGISTERS_TABLE_15__address_13_s1_MASK 0xffff
3304#define MC_REGISTERS_TABLE_15__address_13_s1__SHIFT 0x0
3305#define MC_REGISTERS_TABLE_15__address_13_s0_MASK 0xffff0000
3306#define MC_REGISTERS_TABLE_15__address_13_s0__SHIFT 0x10
3307#define MC_REGISTERS_TABLE_16__address_14_s1_MASK 0xffff
3308#define MC_REGISTERS_TABLE_16__address_14_s1__SHIFT 0x0
3309#define MC_REGISTERS_TABLE_16__address_14_s0_MASK 0xffff0000
3310#define MC_REGISTERS_TABLE_16__address_14_s0__SHIFT 0x10
3311#define MC_REGISTERS_TABLE_17__address_15_s1_MASK 0xffff
3312#define MC_REGISTERS_TABLE_17__address_15_s1__SHIFT 0x0
3313#define MC_REGISTERS_TABLE_17__address_15_s0_MASK 0xffff0000
3314#define MC_REGISTERS_TABLE_17__address_15_s0__SHIFT 0x10
3315#define MC_REGISTERS_TABLE_18__data_0_value_0_MASK 0xffffffff
3316#define MC_REGISTERS_TABLE_18__data_0_value_0__SHIFT 0x0
3317#define MC_REGISTERS_TABLE_19__data_0_value_1_MASK 0xffffffff
3318#define MC_REGISTERS_TABLE_19__data_0_value_1__SHIFT 0x0
3319#define MC_REGISTERS_TABLE_20__data_0_value_2_MASK 0xffffffff
3320#define MC_REGISTERS_TABLE_20__data_0_value_2__SHIFT 0x0
3321#define MC_REGISTERS_TABLE_21__data_0_value_3_MASK 0xffffffff
3322#define MC_REGISTERS_TABLE_21__data_0_value_3__SHIFT 0x0
3323#define MC_REGISTERS_TABLE_22__data_0_value_4_MASK 0xffffffff
3324#define MC_REGISTERS_TABLE_22__data_0_value_4__SHIFT 0x0
3325#define MC_REGISTERS_TABLE_23__data_0_value_5_MASK 0xffffffff
3326#define MC_REGISTERS_TABLE_23__data_0_value_5__SHIFT 0x0
3327#define MC_REGISTERS_TABLE_24__data_0_value_6_MASK 0xffffffff
3328#define MC_REGISTERS_TABLE_24__data_0_value_6__SHIFT 0x0
3329#define MC_REGISTERS_TABLE_25__data_0_value_7_MASK 0xffffffff
3330#define MC_REGISTERS_TABLE_25__data_0_value_7__SHIFT 0x0
3331#define MC_REGISTERS_TABLE_26__data_0_value_8_MASK 0xffffffff
3332#define MC_REGISTERS_TABLE_26__data_0_value_8__SHIFT 0x0
3333#define MC_REGISTERS_TABLE_27__data_0_value_9_MASK 0xffffffff
3334#define MC_REGISTERS_TABLE_27__data_0_value_9__SHIFT 0x0
3335#define MC_REGISTERS_TABLE_28__data_0_value_10_MASK 0xffffffff
3336#define MC_REGISTERS_TABLE_28__data_0_value_10__SHIFT 0x0
3337#define MC_REGISTERS_TABLE_29__data_0_value_11_MASK 0xffffffff
3338#define MC_REGISTERS_TABLE_29__data_0_value_11__SHIFT 0x0
3339#define MC_REGISTERS_TABLE_30__data_0_value_12_MASK 0xffffffff
3340#define MC_REGISTERS_TABLE_30__data_0_value_12__SHIFT 0x0
3341#define MC_REGISTERS_TABLE_31__data_0_value_13_MASK 0xffffffff
3342#define MC_REGISTERS_TABLE_31__data_0_value_13__SHIFT 0x0
3343#define MC_REGISTERS_TABLE_32__data_0_value_14_MASK 0xffffffff
3344#define MC_REGISTERS_TABLE_32__data_0_value_14__SHIFT 0x0
3345#define MC_REGISTERS_TABLE_33__data_0_value_15_MASK 0xffffffff
3346#define MC_REGISTERS_TABLE_33__data_0_value_15__SHIFT 0x0
3347#define MC_REGISTERS_TABLE_34__data_1_value_0_MASK 0xffffffff
3348#define MC_REGISTERS_TABLE_34__data_1_value_0__SHIFT 0x0
3349#define MC_REGISTERS_TABLE_35__data_1_value_1_MASK 0xffffffff
3350#define MC_REGISTERS_TABLE_35__data_1_value_1__SHIFT 0x0
3351#define MC_REGISTERS_TABLE_36__data_1_value_2_MASK 0xffffffff
3352#define MC_REGISTERS_TABLE_36__data_1_value_2__SHIFT 0x0
3353#define MC_REGISTERS_TABLE_37__data_1_value_3_MASK 0xffffffff
3354#define MC_REGISTERS_TABLE_37__data_1_value_3__SHIFT 0x0
3355#define MC_REGISTERS_TABLE_38__data_1_value_4_MASK 0xffffffff
3356#define MC_REGISTERS_TABLE_38__data_1_value_4__SHIFT 0x0
3357#define MC_REGISTERS_TABLE_39__data_1_value_5_MASK 0xffffffff
3358#define MC_REGISTERS_TABLE_39__data_1_value_5__SHIFT 0x0
3359#define MC_REGISTERS_TABLE_40__data_1_value_6_MASK 0xffffffff
3360#define MC_REGISTERS_TABLE_40__data_1_value_6__SHIFT 0x0
3361#define MC_REGISTERS_TABLE_41__data_1_value_7_MASK 0xffffffff
3362#define MC_REGISTERS_TABLE_41__data_1_value_7__SHIFT 0x0
3363#define MC_REGISTERS_TABLE_42__data_1_value_8_MASK 0xffffffff
3364#define MC_REGISTERS_TABLE_42__data_1_value_8__SHIFT 0x0
3365#define MC_REGISTERS_TABLE_43__data_1_value_9_MASK 0xffffffff
3366#define MC_REGISTERS_TABLE_43__data_1_value_9__SHIFT 0x0
3367#define MC_REGISTERS_TABLE_44__data_1_value_10_MASK 0xffffffff
3368#define MC_REGISTERS_TABLE_44__data_1_value_10__SHIFT 0x0
3369#define MC_REGISTERS_TABLE_45__data_1_value_11_MASK 0xffffffff
3370#define MC_REGISTERS_TABLE_45__data_1_value_11__SHIFT 0x0
3371#define MC_REGISTERS_TABLE_46__data_1_value_12_MASK 0xffffffff
3372#define MC_REGISTERS_TABLE_46__data_1_value_12__SHIFT 0x0
3373#define MC_REGISTERS_TABLE_47__data_1_value_13_MASK 0xffffffff
3374#define MC_REGISTERS_TABLE_47__data_1_value_13__SHIFT 0x0
3375#define MC_REGISTERS_TABLE_48__data_1_value_14_MASK 0xffffffff
3376#define MC_REGISTERS_TABLE_48__data_1_value_14__SHIFT 0x0
3377#define MC_REGISTERS_TABLE_49__data_1_value_15_MASK 0xffffffff
3378#define MC_REGISTERS_TABLE_49__data_1_value_15__SHIFT 0x0
3379#define MC_REGISTERS_TABLE_50__data_2_value_0_MASK 0xffffffff
3380#define MC_REGISTERS_TABLE_50__data_2_value_0__SHIFT 0x0
3381#define MC_REGISTERS_TABLE_51__data_2_value_1_MASK 0xffffffff
3382#define MC_REGISTERS_TABLE_51__data_2_value_1__SHIFT 0x0
3383#define MC_REGISTERS_TABLE_52__data_2_value_2_MASK 0xffffffff
3384#define MC_REGISTERS_TABLE_52__data_2_value_2__SHIFT 0x0
3385#define MC_REGISTERS_TABLE_53__data_2_value_3_MASK 0xffffffff
3386#define MC_REGISTERS_TABLE_53__data_2_value_3__SHIFT 0x0
3387#define MC_REGISTERS_TABLE_54__data_2_value_4_MASK 0xffffffff
3388#define MC_REGISTERS_TABLE_54__data_2_value_4__SHIFT 0x0
3389#define MC_REGISTERS_TABLE_55__data_2_value_5_MASK 0xffffffff
3390#define MC_REGISTERS_TABLE_55__data_2_value_5__SHIFT 0x0
3391#define MC_REGISTERS_TABLE_56__data_2_value_6_MASK 0xffffffff
3392#define MC_REGISTERS_TABLE_56__data_2_value_6__SHIFT 0x0
3393#define MC_REGISTERS_TABLE_57__data_2_value_7_MASK 0xffffffff
3394#define MC_REGISTERS_TABLE_57__data_2_value_7__SHIFT 0x0
3395#define MC_REGISTERS_TABLE_58__data_2_value_8_MASK 0xffffffff
3396#define MC_REGISTERS_TABLE_58__data_2_value_8__SHIFT 0x0
3397#define MC_REGISTERS_TABLE_59__data_2_value_9_MASK 0xffffffff
3398#define MC_REGISTERS_TABLE_59__data_2_value_9__SHIFT 0x0
3399#define MC_REGISTERS_TABLE_60__data_2_value_10_MASK 0xffffffff
3400#define MC_REGISTERS_TABLE_60__data_2_value_10__SHIFT 0x0
3401#define MC_REGISTERS_TABLE_61__data_2_value_11_MASK 0xffffffff
3402#define MC_REGISTERS_TABLE_61__data_2_value_11__SHIFT 0x0
3403#define MC_REGISTERS_TABLE_62__data_2_value_12_MASK 0xffffffff
3404#define MC_REGISTERS_TABLE_62__data_2_value_12__SHIFT 0x0
3405#define MC_REGISTERS_TABLE_63__data_2_value_13_MASK 0xffffffff
3406#define MC_REGISTERS_TABLE_63__data_2_value_13__SHIFT 0x0
3407#define MC_REGISTERS_TABLE_64__data_2_value_14_MASK 0xffffffff
3408#define MC_REGISTERS_TABLE_64__data_2_value_14__SHIFT 0x0
3409#define MC_REGISTERS_TABLE_65__data_2_value_15_MASK 0xffffffff
3410#define MC_REGISTERS_TABLE_65__data_2_value_15__SHIFT 0x0
3411#define MC_REGISTERS_TABLE_66__data_3_value_0_MASK 0xffffffff
3412#define MC_REGISTERS_TABLE_66__data_3_value_0__SHIFT 0x0
3413#define MC_REGISTERS_TABLE_67__data_3_value_1_MASK 0xffffffff
3414#define MC_REGISTERS_TABLE_67__data_3_value_1__SHIFT 0x0
3415#define MC_REGISTERS_TABLE_68__data_3_value_2_MASK 0xffffffff
3416#define MC_REGISTERS_TABLE_68__data_3_value_2__SHIFT 0x0
3417#define MC_REGISTERS_TABLE_69__data_3_value_3_MASK 0xffffffff
3418#define MC_REGISTERS_TABLE_69__data_3_value_3__SHIFT 0x0
3419#define MC_REGISTERS_TABLE_70__data_3_value_4_MASK 0xffffffff
3420#define MC_REGISTERS_TABLE_70__data_3_value_4__SHIFT 0x0
3421#define MC_REGISTERS_TABLE_71__data_3_value_5_MASK 0xffffffff
3422#define MC_REGISTERS_TABLE_71__data_3_value_5__SHIFT 0x0
3423#define MC_REGISTERS_TABLE_72__data_3_value_6_MASK 0xffffffff
3424#define MC_REGISTERS_TABLE_72__data_3_value_6__SHIFT 0x0
3425#define MC_REGISTERS_TABLE_73__data_3_value_7_MASK 0xffffffff
3426#define MC_REGISTERS_TABLE_73__data_3_value_7__SHIFT 0x0
3427#define MC_REGISTERS_TABLE_74__data_3_value_8_MASK 0xffffffff
3428#define MC_REGISTERS_TABLE_74__data_3_value_8__SHIFT 0x0
3429#define MC_REGISTERS_TABLE_75__data_3_value_9_MASK 0xffffffff
3430#define MC_REGISTERS_TABLE_75__data_3_value_9__SHIFT 0x0
3431#define MC_REGISTERS_TABLE_76__data_3_value_10_MASK 0xffffffff
3432#define MC_REGISTERS_TABLE_76__data_3_value_10__SHIFT 0x0
3433#define MC_REGISTERS_TABLE_77__data_3_value_11_MASK 0xffffffff
3434#define MC_REGISTERS_TABLE_77__data_3_value_11__SHIFT 0x0
3435#define MC_REGISTERS_TABLE_78__data_3_value_12_MASK 0xffffffff
3436#define MC_REGISTERS_TABLE_78__data_3_value_12__SHIFT 0x0
3437#define MC_REGISTERS_TABLE_79__data_3_value_13_MASK 0xffffffff
3438#define MC_REGISTERS_TABLE_79__data_3_value_13__SHIFT 0x0
3439#define MC_REGISTERS_TABLE_80__data_3_value_14_MASK 0xffffffff
3440#define MC_REGISTERS_TABLE_80__data_3_value_14__SHIFT 0x0
3441#define MC_REGISTERS_TABLE_81__data_3_value_15_MASK 0xffffffff
3442#define MC_REGISTERS_TABLE_81__data_3_value_15__SHIFT 0x0
3443#define MC_REGISTERS_TABLE_82__data_4_value_0_MASK 0xffffffff
3444#define MC_REGISTERS_TABLE_82__data_4_value_0__SHIFT 0x0
3445#define MC_REGISTERS_TABLE_83__data_4_value_1_MASK 0xffffffff
3446#define MC_REGISTERS_TABLE_83__data_4_value_1__SHIFT 0x0
3447#define MC_REGISTERS_TABLE_84__data_4_value_2_MASK 0xffffffff
3448#define MC_REGISTERS_TABLE_84__data_4_value_2__SHIFT 0x0
3449#define MC_REGISTERS_TABLE_85__data_4_value_3_MASK 0xffffffff
3450#define MC_REGISTERS_TABLE_85__data_4_value_3__SHIFT 0x0
3451#define MC_REGISTERS_TABLE_86__data_4_value_4_MASK 0xffffffff
3452#define MC_REGISTERS_TABLE_86__data_4_value_4__SHIFT 0x0
3453#define MC_REGISTERS_TABLE_87__data_4_value_5_MASK 0xffffffff
3454#define MC_REGISTERS_TABLE_87__data_4_value_5__SHIFT 0x0
3455#define MC_REGISTERS_TABLE_88__data_4_value_6_MASK 0xffffffff
3456#define MC_REGISTERS_TABLE_88__data_4_value_6__SHIFT 0x0
3457#define MC_REGISTERS_TABLE_89__data_4_value_7_MASK 0xffffffff
3458#define MC_REGISTERS_TABLE_89__data_4_value_7__SHIFT 0x0
3459#define MC_REGISTERS_TABLE_90__data_4_value_8_MASK 0xffffffff
3460#define MC_REGISTERS_TABLE_90__data_4_value_8__SHIFT 0x0
3461#define MC_REGISTERS_TABLE_91__data_4_value_9_MASK 0xffffffff
3462#define MC_REGISTERS_TABLE_91__data_4_value_9__SHIFT 0x0
3463#define MC_REGISTERS_TABLE_92__data_4_value_10_MASK 0xffffffff
3464#define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0
3465#define MC_REGISTERS_TABLE_93__data_4_value_11_MASK 0xffffffff
3466#define MC_REGISTERS_TABLE_93__data_4_value_11__SHIFT 0x0
3467#define MC_REGISTERS_TABLE_94__data_4_value_12_MASK 0xffffffff
3468#define MC_REGISTERS_TABLE_94__data_4_value_12__SHIFT 0x0
3469#define MC_REGISTERS_TABLE_95__data_4_value_13_MASK 0xffffffff
3470#define MC_REGISTERS_TABLE_95__data_4_value_13__SHIFT 0x0
3471#define MC_REGISTERS_TABLE_96__data_4_value_14_MASK 0xffffffff
3472#define MC_REGISTERS_TABLE_96__data_4_value_14__SHIFT 0x0
3473#define MC_REGISTERS_TABLE_97__data_4_value_15_MASK 0xffffffff
3474#define MC_REGISTERS_TABLE_97__data_4_value_15__SHIFT 0x0
3475#define MC_REGISTERS_TABLE_98__data_5_value_0_MASK 0xffffffff
3476#define MC_REGISTERS_TABLE_98__data_5_value_0__SHIFT 0x0
3477#define MC_REGISTERS_TABLE_99__data_5_value_1_MASK 0xffffffff
3478#define MC_REGISTERS_TABLE_99__data_5_value_1__SHIFT 0x0
3479#define MC_REGISTERS_TABLE_100__data_5_value_2_MASK 0xffffffff
3480#define MC_REGISTERS_TABLE_100__data_5_value_2__SHIFT 0x0
3481#define MC_REGISTERS_TABLE_101__data_5_value_3_MASK 0xffffffff
3482#define MC_REGISTERS_TABLE_101__data_5_value_3__SHIFT 0x0
3483#define MC_REGISTERS_TABLE_102__data_5_value_4_MASK 0xffffffff
3484#define MC_REGISTERS_TABLE_102__data_5_value_4__SHIFT 0x0
3485#define MC_REGISTERS_TABLE_103__data_5_value_5_MASK 0xffffffff
3486#define MC_REGISTERS_TABLE_103__data_5_value_5__SHIFT 0x0
3487#define MC_REGISTERS_TABLE_104__data_5_value_6_MASK 0xffffffff
3488#define MC_REGISTERS_TABLE_104__data_5_value_6__SHIFT 0x0
3489#define MC_REGISTERS_TABLE_105__data_5_value_7_MASK 0xffffffff
3490#define MC_REGISTERS_TABLE_105__data_5_value_7__SHIFT 0x0
3491#define MC_REGISTERS_TABLE_106__data_5_value_8_MASK 0xffffffff
3492#define MC_REGISTERS_TABLE_106__data_5_value_8__SHIFT 0x0
3493#define MC_REGISTERS_TABLE_107__data_5_value_9_MASK 0xffffffff
3494#define MC_REGISTERS_TABLE_107__data_5_value_9__SHIFT 0x0
3495#define MC_REGISTERS_TABLE_108__data_5_value_10_MASK 0xffffffff
3496#define MC_REGISTERS_TABLE_108__data_5_value_10__SHIFT 0x0
3497#define MC_REGISTERS_TABLE_109__data_5_value_11_MASK 0xffffffff
3498#define MC_REGISTERS_TABLE_109__data_5_value_11__SHIFT 0x0
3499#define MC_REGISTERS_TABLE_110__data_5_value_12_MASK 0xffffffff
3500#define MC_REGISTERS_TABLE_110__data_5_value_12__SHIFT 0x0
3501#define MC_REGISTERS_TABLE_111__data_5_value_13_MASK 0xffffffff
3502#define MC_REGISTERS_TABLE_111__data_5_value_13__SHIFT 0x0
3503#define MC_REGISTERS_TABLE_112__data_5_value_14_MASK 0xffffffff
3504#define MC_REGISTERS_TABLE_112__data_5_value_14__SHIFT 0x0
3505#define MC_REGISTERS_TABLE_113__data_5_value_15_MASK 0xffffffff
3506#define MC_REGISTERS_TABLE_113__data_5_value_15__SHIFT 0x0
3507#define FAN_TABLE_1__TempMin_MASK 0xffff
3508#define FAN_TABLE_1__TempMin__SHIFT 0x0
3509#define FAN_TABLE_1__FdoMode_MASK 0xffff0000
3510#define FAN_TABLE_1__FdoMode__SHIFT 0x10
3511#define FAN_TABLE_2__TempMax_MASK 0xffff
3512#define FAN_TABLE_2__TempMax__SHIFT 0x0
3513#define FAN_TABLE_2__TempMed_MASK 0xffff0000
3514#define FAN_TABLE_2__TempMed__SHIFT 0x10
3515#define FAN_TABLE_3__Slope2_MASK 0xffff
3516#define FAN_TABLE_3__Slope2__SHIFT 0x0
3517#define FAN_TABLE_3__Slope1_MASK 0xffff0000
3518#define FAN_TABLE_3__Slope1__SHIFT 0x10
3519#define FAN_TABLE_4__HystUp_MASK 0xffff
3520#define FAN_TABLE_4__HystUp__SHIFT 0x0
3521#define FAN_TABLE_4__FdoMin_MASK 0xffff0000
3522#define FAN_TABLE_4__FdoMin__SHIFT 0x10
3523#define FAN_TABLE_5__HystSlope_MASK 0xffff
3524#define FAN_TABLE_5__HystSlope__SHIFT 0x0
3525#define FAN_TABLE_5__HystDown_MASK 0xffff0000
3526#define FAN_TABLE_5__HystDown__SHIFT 0x10
3527#define FAN_TABLE_6__TempCurr_MASK 0xffff
3528#define FAN_TABLE_6__TempCurr__SHIFT 0x0
3529#define FAN_TABLE_6__TempRespLim_MASK 0xffff0000
3530#define FAN_TABLE_6__TempRespLim__SHIFT 0x10
3531#define FAN_TABLE_7__PwmCurr_MASK 0xffff
3532#define FAN_TABLE_7__PwmCurr__SHIFT 0x0
3533#define FAN_TABLE_7__SlopeCurr_MASK 0xffff0000
3534#define FAN_TABLE_7__SlopeCurr__SHIFT 0x10
3535#define FAN_TABLE_8__RefreshPeriod_MASK 0xffffffff
3536#define FAN_TABLE_8__RefreshPeriod__SHIFT 0x0
3537#define FAN_TABLE_9__Padding_MASK 0xff
3538#define FAN_TABLE_9__Padding__SHIFT 0x0
3539#define FAN_TABLE_9__TempSrc_MASK 0xff00
3540#define FAN_TABLE_9__TempSrc__SHIFT 0x8
3541#define FAN_TABLE_9__FdoMax_MASK 0xffff0000
3542#define FAN_TABLE_9__FdoMax__SHIFT 0x10
3543#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
3544#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
3545#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
3546#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
3547#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
3548#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
3549#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
3550#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
3551#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
3552#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
3553#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
3554#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
3555#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
3556#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
3557#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
3558#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
3559#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
3560#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
3561#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
3562#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
3563#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
3564#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
3565#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
3566#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
3567#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
3568#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
3569#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
3570#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
3571#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
3572#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
3573#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
3574#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
3575#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
3576#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
3577#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
3578#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
3579#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
3580#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
3581#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
3582#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
3583#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
3584#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
3585#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
3586#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
3587#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
3588#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
3589#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
3590#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
3591#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
3592#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
3593#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
3594#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
3595#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
3596#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
3597#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
3598#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
3599#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
3600#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
3601#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
3602#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
3603#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
3604#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
3605#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
3606#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
3607#define SOFT_REGISTERS_TABLE_21__Reserved_0_MASK 0xffffffff
3608#define SOFT_REGISTERS_TABLE_21__Reserved_0__SHIFT 0x0
3609#define SOFT_REGISTERS_TABLE_22__Reserved_1_MASK 0xffffffff
3610#define SOFT_REGISTERS_TABLE_22__Reserved_1__SHIFT 0x0
3611#define SOFT_REGISTERS_TABLE_23__Reserved_2_MASK 0xffffffff
3612#define SOFT_REGISTERS_TABLE_23__Reserved_2__SHIFT 0x0
3613#define SOFT_REGISTERS_TABLE_24__Reserved_3_MASK 0xffffffff
3614#define SOFT_REGISTERS_TABLE_24__Reserved_3__SHIFT 0x0
3615#define SOFT_REGISTERS_TABLE_25__Reserved_4_MASK 0xffffffff
3616#define SOFT_REGISTERS_TABLE_25__Reserved_4__SHIFT 0x0
3617#define SOFT_REGISTERS_TABLE_26__Reserved_5_MASK 0xffffffff
3618#define SOFT_REGISTERS_TABLE_26__Reserved_5__SHIFT 0x0
3619#define SOFT_REGISTERS_TABLE_27__Reserved_6_MASK 0xffffffff
3620#define SOFT_REGISTERS_TABLE_27__Reserved_6__SHIFT 0x0
3621#define SOFT_REGISTERS_TABLE_28__Reserved_7_MASK 0xffffffff
3622#define SOFT_REGISTERS_TABLE_28__Reserved_7__SHIFT 0x0
3623#define SOFT_REGISTERS_TABLE_29__Reserved_8_MASK 0xffffffff
3624#define SOFT_REGISTERS_TABLE_29__Reserved_8__SHIFT 0x0
3625#define SOFT_REGISTERS_TABLE_30__Reserved_9_MASK 0xffffffff
3626#define SOFT_REGISTERS_TABLE_30__Reserved_9__SHIFT 0x0
3627#define PM_FUSES_1__BapmVddCVidHiSidd_3_MASK 0xff
3628#define PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT 0x0
3629#define PM_FUSES_1__BapmVddCVidHiSidd_2_MASK 0xff00
3630#define PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT 0x8
3631#define PM_FUSES_1__BapmVddCVidHiSidd_1_MASK 0xff0000
3632#define PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT 0x10
3633#define PM_FUSES_1__BapmVddCVidHiSidd_0_MASK 0xff000000
3634#define PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT 0x18
3635#define PM_FUSES_2__BapmVddCVidHiSidd_7_MASK 0xff
3636#define PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT 0x0
3637#define PM_FUSES_2__BapmVddCVidHiSidd_6_MASK 0xff00
3638#define PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT 0x8
3639#define PM_FUSES_2__BapmVddCVidHiSidd_5_MASK 0xff0000
3640#define PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT 0x10
3641#define PM_FUSES_2__BapmVddCVidHiSidd_4_MASK 0xff000000
3642#define PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT 0x18
3643#define PM_FUSES_3__BapmVddCVidLoSidd_3_MASK 0xff
3644#define PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT 0x0
3645#define PM_FUSES_3__BapmVddCVidLoSidd_2_MASK 0xff00
3646#define PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT 0x8
3647#define PM_FUSES_3__BapmVddCVidLoSidd_1_MASK 0xff0000
3648#define PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT 0x10
3649#define PM_FUSES_3__BapmVddCVidLoSidd_0_MASK 0xff000000
3650#define PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT 0x18
3651#define PM_FUSES_4__BapmVddCVidLoSidd_7_MASK 0xff
3652#define PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT 0x0
3653#define PM_FUSES_4__BapmVddCVidLoSidd_6_MASK 0xff00
3654#define PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT 0x8
3655#define PM_FUSES_4__BapmVddCVidLoSidd_5_MASK 0xff0000
3656#define PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT 0x10
3657#define PM_FUSES_4__BapmVddCVidLoSidd_4_MASK 0xff000000
3658#define PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT 0x18
3659#define PM_FUSES_5__VddCVid_3_MASK 0xff
3660#define PM_FUSES_5__VddCVid_3__SHIFT 0x0
3661#define PM_FUSES_5__VddCVid_2_MASK 0xff00
3662#define PM_FUSES_5__VddCVid_2__SHIFT 0x8
3663#define PM_FUSES_5__VddCVid_1_MASK 0xff0000
3664#define PM_FUSES_5__VddCVid_1__SHIFT 0x10
3665#define PM_FUSES_5__VddCVid_0_MASK 0xff000000
3666#define PM_FUSES_5__VddCVid_0__SHIFT 0x18
3667#define PM_FUSES_6__VddCVid_7_MASK 0xff
3668#define PM_FUSES_6__VddCVid_7__SHIFT 0x0
3669#define PM_FUSES_6__VddCVid_6_MASK 0xff00
3670#define PM_FUSES_6__VddCVid_6__SHIFT 0x8
3671#define PM_FUSES_6__VddCVid_5_MASK 0xff0000
3672#define PM_FUSES_6__VddCVid_5__SHIFT 0x10
3673#define PM_FUSES_6__VddCVid_4_MASK 0xff000000
3674#define PM_FUSES_6__VddCVid_4__SHIFT 0x18
3675#define PM_FUSES_7__SviLoadLineOffsetVddC_MASK 0xff
3676#define PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT 0x0
3677#define PM_FUSES_7__SviLoadLineTrimVddC_MASK 0xff00
3678#define PM_FUSES_7__SviLoadLineTrimVddC__SHIFT 0x8
3679#define PM_FUSES_7__SviLoadLineVddC_MASK 0xff0000
3680#define PM_FUSES_7__SviLoadLineVddC__SHIFT 0x10
3681#define PM_FUSES_7__SviLoadLineEn_MASK 0xff000000
3682#define PM_FUSES_7__SviLoadLineEn__SHIFT 0x18
3683#define PM_FUSES_8__TDC_MAWt_MASK 0xff
3684#define PM_FUSES_8__TDC_MAWt__SHIFT 0x0
3685#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
3686#define PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
3687#define PM_FUSES_8__TDC_VDDC_PkgLimit_MASK 0xffff0000
3688#define PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT 0x10
3689#define PM_FUSES_9__Reserved_MASK 0xff
3690#define PM_FUSES_9__Reserved__SHIFT 0x0
3691#define PM_FUSES_9__LPMLTemperatureMax_MASK 0xff00
3692#define PM_FUSES_9__LPMLTemperatureMax__SHIFT 0x8
3693#define PM_FUSES_9__LPMLTemperatureMin_MASK 0xff0000
3694#define PM_FUSES_9__LPMLTemperatureMin__SHIFT 0x10
3695#define PM_FUSES_9__TdcWaterfallCtl_MASK 0xff000000
3696#define PM_FUSES_9__TdcWaterfallCtl__SHIFT 0x18
3697#define PM_FUSES_10__LPMLTemperatureScaler_3_MASK 0xff
3698#define PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT 0x0
3699#define PM_FUSES_10__LPMLTemperatureScaler_2_MASK 0xff00
3700#define PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT 0x8
3701#define PM_FUSES_10__LPMLTemperatureScaler_1_MASK 0xff0000
3702#define PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT 0x10
3703#define PM_FUSES_10__LPMLTemperatureScaler_0_MASK 0xff000000
3704#define PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT 0x18
3705#define PM_FUSES_11__LPMLTemperatureScaler_7_MASK 0xff
3706#define PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT 0x0
3707#define PM_FUSES_11__LPMLTemperatureScaler_6_MASK 0xff00
3708#define PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT 0x8
3709#define PM_FUSES_11__LPMLTemperatureScaler_5_MASK 0xff0000
3710#define PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT 0x10
3711#define PM_FUSES_11__LPMLTemperatureScaler_4_MASK 0xff000000
3712#define PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT 0x18
3713#define PM_FUSES_12__LPMLTemperatureScaler_11_MASK 0xff
3714#define PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT 0x0
3715#define PM_FUSES_12__LPMLTemperatureScaler_10_MASK 0xff00
3716#define PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT 0x8
3717#define PM_FUSES_12__LPMLTemperatureScaler_9_MASK 0xff0000
3718#define PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT 0x10
3719#define PM_FUSES_12__LPMLTemperatureScaler_8_MASK 0xff000000
3720#define PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT 0x18
3721#define PM_FUSES_13__LPMLTemperatureScaler_15_MASK 0xff
3722#define PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT 0x0
3723#define PM_FUSES_13__LPMLTemperatureScaler_14_MASK 0xff00
3724#define PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT 0x8
3725#define PM_FUSES_13__LPMLTemperatureScaler_13_MASK 0xff0000
3726#define PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT 0x10
3727#define PM_FUSES_13__LPMLTemperatureScaler_12_MASK 0xff000000
3728#define PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT 0x18
3729#define PM_FUSES_14__GnbLPML_3_MASK 0xff
3730#define PM_FUSES_14__GnbLPML_3__SHIFT 0x0
3731#define PM_FUSES_14__GnbLPML_2_MASK 0xff00
3732#define PM_FUSES_14__GnbLPML_2__SHIFT 0x8
3733#define PM_FUSES_14__GnbLPML_1_MASK 0xff0000
3734#define PM_FUSES_14__GnbLPML_1__SHIFT 0x10
3735#define PM_FUSES_14__GnbLPML_0_MASK 0xff000000
3736#define PM_FUSES_14__GnbLPML_0__SHIFT 0x18
3737#define PM_FUSES_15__GnbLPML_7_MASK 0xff
3738#define PM_FUSES_15__GnbLPML_7__SHIFT 0x0
3739#define PM_FUSES_15__GnbLPML_6_MASK 0xff00
3740#define PM_FUSES_15__GnbLPML_6__SHIFT 0x8
3741#define PM_FUSES_15__GnbLPML_5_MASK 0xff0000
3742#define PM_FUSES_15__GnbLPML_5__SHIFT 0x10
3743#define PM_FUSES_15__GnbLPML_4_MASK 0xff000000
3744#define PM_FUSES_15__GnbLPML_4__SHIFT 0x18
3745#define PM_FUSES_16__GnbLPML_11_MASK 0xff
3746#define PM_FUSES_16__GnbLPML_11__SHIFT 0x0
3747#define PM_FUSES_16__GnbLPML_10_MASK 0xff00
3748#define PM_FUSES_16__GnbLPML_10__SHIFT 0x8
3749#define PM_FUSES_16__GnbLPML_9_MASK 0xff0000
3750#define PM_FUSES_16__GnbLPML_9__SHIFT 0x10
3751#define PM_FUSES_16__GnbLPML_8_MASK 0xff000000
3752#define PM_FUSES_16__GnbLPML_8__SHIFT 0x18
3753#define PM_FUSES_17__GnbLPML_15_MASK 0xff
3754#define PM_FUSES_17__GnbLPML_15__SHIFT 0x0
3755#define PM_FUSES_17__GnbLPML_14_MASK 0xff00
3756#define PM_FUSES_17__GnbLPML_14__SHIFT 0x8
3757#define PM_FUSES_17__GnbLPML_13_MASK 0xff0000
3758#define PM_FUSES_17__GnbLPML_13__SHIFT 0x10
3759#define PM_FUSES_17__GnbLPML_12_MASK 0xff000000
3760#define PM_FUSES_17__GnbLPML_12__SHIFT 0x18
3761#define PM_FUSES_18__Reserved1_1_MASK 0xff
3762#define PM_FUSES_18__Reserved1_1__SHIFT 0x0
3763#define PM_FUSES_18__Reserved1_0_MASK 0xff00
3764#define PM_FUSES_18__Reserved1_0__SHIFT 0x8
3765#define PM_FUSES_18__GnbLPMLMinVid_MASK 0xff0000
3766#define PM_FUSES_18__GnbLPMLMinVid__SHIFT 0x10
3767#define PM_FUSES_18__GnbLPMLMaxVid_MASK 0xff000000
3768#define PM_FUSES_18__GnbLPMLMaxVid__SHIFT 0x18
3769#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK 0xffff
3770#define PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
3771#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
3772#define PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
3773#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
3774#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
3775#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
3776#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
3777#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
3778#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
3779#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
3780#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
3781#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
3782#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
3783#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
3784#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
3785#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
3786#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
3787#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
3788#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
3789#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
3790#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
3791#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
3792#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
3793#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
3794#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
3795#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
3796#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
3797#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
3798#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
3799#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
3800#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
3801#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
3802#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
3803#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
3804#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
3805#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
3806#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
3807#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
3808#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
3809#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
3810#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
3811#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
3812#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
3813#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
3814#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
3815#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
3816#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
3817#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
3818#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
3819#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
3820#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
3821#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
3822#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
3823#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
3824#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
3825#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
3826#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
3827#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
3828#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
3829#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
3830#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
3831#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
3832#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
3833#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
3834#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
3835#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
3836#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
3837#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
3838#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
3839#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
3840#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
3841#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
3842#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
3843#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
3844#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
3845#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
3846#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
3847#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
3848#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
3849#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
3850#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
3851#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
3852#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
3853#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
3854#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
3855#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
3856#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
3857#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
3858#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
3859#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
3860#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
3861#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
3862#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
3863#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
3864#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
3865#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
3866#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
3867#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
3868#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
3869#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
3870#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
3871#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
3872#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
3873#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
3874#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
3875#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
3876#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
3877#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
3878#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
3879#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
3880#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
3881#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
3882#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
3883#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
3884#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
3885#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
3886#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
3887#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
3888#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
3889#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
3890#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
3891#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
3892#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
3893#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
3894#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
3895#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
3896#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
3897#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
3898#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
3899#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
3900#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
3901#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
3902#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
3903#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
3904#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
3905#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
3906#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
3907#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
3908#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
3909#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
3910#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
3911#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
3912#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
3913#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
3914#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
3915#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
3916#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
3917#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
3918#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
3919#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
3920#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
3921#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
3922#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
3923#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
3924#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
3925#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
3926#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
3927#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
3928#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
3929#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
3930#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
3931#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
3932#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
3933#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
3934#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
3935#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
3936#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
3937#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
3938#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
3939#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
3940#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
3941#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
3942#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
3943#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
3944#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
3945#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
3946#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
3947#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
3948#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
3949#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
3950#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
3951#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
3952#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
3953#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
3954#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
3955#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
3956#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
3957#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
3958#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
3959#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
3960#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
3961#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
3962#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
3963#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
3964#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
3965#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
3966#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
3967#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
3968#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
3969#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
3970#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
3971#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
3972#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
3973#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
3974#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
3975#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
3976#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
3977#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
3978#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
3979#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
3980#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
3981#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
3982#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
3983#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
3984#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
3985#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
3986#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
3987#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
3988#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
3989#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
3990#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
3991#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
3992#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
3993#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
3994#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
3995#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
3996#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
3997#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
3998#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
3999#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
4000#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
4001#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
4002#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
4003#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
4004#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
4005#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
4006#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
4007#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
4008#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
4009#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
4010#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
4011#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
4012#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
4013#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
4014#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
4015#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
4016#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
4017#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
4018#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
4019#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
4020#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
4021#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
4022#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
4023#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
4024#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
4025#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
4026#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
4027#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
4028#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
4029#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
4030#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
4031#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
4032#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
4033#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
4034#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
4035#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
4036#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
4037#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
4038#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
4039#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
4040#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
4041#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
4042#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
4043#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
4044#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
4045#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
4046#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
4047#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
4048#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
4049#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
4050#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
4051#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
4052#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
4053#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
4054#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
4055#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
4056#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
4057#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
4058#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
4059#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
4060#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
4061#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
4062#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
4063#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
4064#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
4065#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
4066#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
4067#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
4068#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
4069#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
4070#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
4071#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
4072#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
4073#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
4074#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
4075#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
4076#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
4077#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
4078#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
4079#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
4080#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
4081#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
4082#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
4083#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
4084#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
4085#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
4086#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
4087#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
4088#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
4089#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
4090#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
4091#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
4092#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
4093#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
4094#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
4095#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
4096#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
4097#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0xf0
4098#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
4099#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
4100#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
4101#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
4102#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
4103#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
4104#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
4105#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
4106#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
4107#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
4108#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
4109#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
4110#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
4111#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
4112#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
4113#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
4114#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
4115#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
4116#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
4117#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
4118#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
4119#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
4120#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
4121#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
4122#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
4123#define CG_FDO_CTRL1__M_MASK 0xff0000
4124#define CG_FDO_CTRL1__M__SHIFT 0x10
4125#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
4126#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
4127#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
4128#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
4129#define CG_FDO_CTRL2__TMIN_MASK 0xff
4130#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
4131#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
4132#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
4133#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
4134#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
4135#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
4136#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
4137#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
4138#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
4139#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
4140#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
4141#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
4142#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
4143#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
4144#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
4145#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
4146#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
4147#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
4148#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
4149#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
4150#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
4151#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
4152#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
4153#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
4154#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
4155#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
4156#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
4157#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
4158#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
4159#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
4160#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
4161#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
4162#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
4163#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
4164#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
4165#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
4166#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
4167#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
4168#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
4169#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
4170#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
4171#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
4172#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
4173#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
4174#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
4175#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
4176#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
4177#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
4178#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
4179#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
4180#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
4181#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
4182#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
4183#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
4184#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
4185#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
4186#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
4187#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
4188#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
4189#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
4190#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
4191#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
4192#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
4193#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
4194#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
4195#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
4196#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
4197#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
4198#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
4199#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
4200#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
4201#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
4202#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
4203#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
4204#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
4205#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
4206#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
4207#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
4208#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
4209#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
4210#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
4211#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
4212#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
4213#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
4214#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
4215#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
4216#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
4217#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
4218#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
4219#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
4220#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
4221#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
4222#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
4223#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
4224#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
4225#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
4226#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
4227#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
4228#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
4229#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
4230#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
4231#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
4232#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
4233#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
4234#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
4235#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
4236#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
4237#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
4238#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
4239#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
4240#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
4241#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
4242#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
4243#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
4244#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
4245#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
4246#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
4247#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
4248#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
4249#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
4250#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
4251#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
4252#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
4253#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
4254#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
4255#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
4256#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
4257#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
4258#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
4259#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
4260#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
4261#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
4262#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
4263#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
4264#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
4265#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
4266#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
4267#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
4268#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
4269#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
4270#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
4271#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
4272#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
4273#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
4274#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
4275#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
4276#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
4277#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
4278#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
4279#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
4280#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
4281#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
4282#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
4283#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
4284#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
4285#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
4286#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
4287#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
4288#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
4289#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
4290#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
4291#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
4292#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
4293#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
4294#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
4295#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
4296#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
4297#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
4298#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
4299#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
4300#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
4301#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
4302#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
4303#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
4304#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
4305#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
4306#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
4307#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
4308#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
4309#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
4310#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
4311#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
4312#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
4313#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
4314#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
4315#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
4316#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
4317#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
4318#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
4319#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
4320#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
4321#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
4322#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
4323#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
4324#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
4325#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
4326#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
4327#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
4328#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
4329#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
4330#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
4331#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
4332#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
4333#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
4334#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
4335#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
4336#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
4337#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
4338#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
4339#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
4340#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
4341#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
4342#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
4343#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
4344#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
4345#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
4346#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
4347#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
4348#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
4349#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
4350#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
4351#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
4352#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
4353#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
4354#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
4355#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
4356#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
4357#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
4358#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
4359#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
4360#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
4361#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
4362#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
4363#define THM_TMON0_INT_DATA__Z_MASK 0x7ff
4364#define THM_TMON0_INT_DATA__Z__SHIFT 0x0
4365#define THM_TMON0_INT_DATA__VALID_MASK 0x800
4366#define THM_TMON0_INT_DATA__VALID__SHIFT 0xb
4367#define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000
4368#define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc
4369#define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f
4370#define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0
4371#define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0
4372#define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5
4373#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
4374#define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
4375#define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
4376#define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
4377#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
4378#define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
4379#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
4380#define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
4381#define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
4382#define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
4383#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
4384#define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
4385#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
4386#define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
4387#define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
4388#define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
4389#define GENERAL_PWRMGT__SPARE11_MASK 0x800
4390#define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
4391#define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
4392#define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
4393#define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
4394#define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
4395#define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
4396#define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
4397#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
4398#define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
4399#define GENERAL_PWRMGT__SPARE18_MASK 0x40000
4400#define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
4401#define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
4402#define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
4403#define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
4404#define