1 | /* |
2 | * SMU_7_1_1 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef SMU_7_1_1_D_H |
25 | #define SMU_7_1_1_D_H |
26 | |
27 | #define mmGCK_SMC_IND_INDEX 0x80 |
28 | #define mmGCK0_GCK_SMC_IND_INDEX 0x80 |
29 | #define mmGCK1_GCK_SMC_IND_INDEX 0x82 |
30 | #define mmGCK2_GCK_SMC_IND_INDEX 0x84 |
31 | #define mmGCK3_GCK_SMC_IND_INDEX 0x86 |
32 | #define mmGCK_SMC_IND_DATA 0x81 |
33 | #define mmGCK0_GCK_SMC_IND_DATA 0x81 |
34 | #define mmGCK1_GCK_SMC_IND_DATA 0x83 |
35 | #define mmGCK2_GCK_SMC_IND_DATA 0x85 |
36 | #define mmGCK3_GCK_SMC_IND_DATA 0x87 |
37 | #define ixCG_DCLK_CNTL 0xc050009c |
38 | #define ixCG_DCLK_STATUS 0xc05000a0 |
39 | #define ixCG_VCLK_CNTL 0xc05000a4 |
40 | #define ixCG_VCLK_STATUS 0xc05000a8 |
41 | #define ixCG_ECLK_CNTL 0xc05000ac |
42 | #define ixCG_ECLK_STATUS 0xc05000b0 |
43 | #define ixCG_ACLK_CNTL 0xc05000dc |
44 | #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 |
45 | #define ixCG_SPLL_FUNC_CNTL 0xc0500140 |
46 | #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 |
47 | #define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 |
48 | #define ixCG_SPLL_FUNC_CNTL_4 0xc050014c |
49 | #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 |
50 | #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 |
51 | #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 |
52 | #define ixSPLL_CNTL_MODE 0xc0500160 |
53 | #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 |
54 | #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 |
55 | #define ixMPLL_BYPASSCLK_SEL 0xc050019c |
56 | #define ixCG_CLKPIN_CNTL 0xc05001a0 |
57 | #define ixCG_CLKPIN_CNTL_2 0xc05001a4 |
58 | #define ixCG_CLKPIN_CNTL_DC 0xc0500204 |
59 | #define ixTHM_CLK_CNTL 0xc05001a8 |
60 | #define ixMISC_CLK_CTRL 0xc05001ac |
61 | #define ixGCK_PLL_TEST_CNTL 0xc05001c0 |
62 | #define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 |
63 | #define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 |
64 | #define mmSMC_IND_INDEX 0x80 |
65 | #define mmSMC0_SMC_IND_INDEX 0x80 |
66 | #define mmSMC1_SMC_IND_INDEX 0x82 |
67 | #define mmSMC2_SMC_IND_INDEX 0x84 |
68 | #define mmSMC3_SMC_IND_INDEX 0x86 |
69 | #define mmSMC_IND_DATA 0x81 |
70 | #define mmSMC0_SMC_IND_DATA 0x81 |
71 | #define mmSMC1_SMC_IND_DATA 0x83 |
72 | #define mmSMC2_SMC_IND_DATA 0x85 |
73 | #define mmSMC3_SMC_IND_DATA 0x87 |
74 | #define mmSMC_IND_INDEX_0 0x80 |
75 | #define mmSMC_IND_DATA_0 0x81 |
76 | #define mmSMC_IND_INDEX_1 0x82 |
77 | #define mmSMC_IND_DATA_1 0x83 |
78 | #define mmSMC_IND_INDEX_2 0x84 |
79 | #define mmSMC_IND_DATA_2 0x85 |
80 | #define mmSMC_IND_INDEX_3 0x86 |
81 | #define mmSMC_IND_DATA_3 0x87 |
82 | #define mmSMC_IND_INDEX_4 0x88 |
83 | #define mmSMC_IND_DATA_4 0x89 |
84 | #define mmSMC_IND_INDEX_5 0x8a |
85 | #define mmSMC_IND_DATA_5 0x8b |
86 | #define mmSMC_IND_INDEX_6 0x8c |
87 | #define mmSMC_IND_DATA_6 0x8d |
88 | #define mmSMC_IND_INDEX_7 0x8e |
89 | #define mmSMC_IND_DATA_7 0x8f |
90 | #define mmSMC_IND_ACCESS_CNTL 0x92 |
91 | #define mmSMC_MESSAGE_0 0x94 |
92 | #define mmSMC_RESP_0 0x95 |
93 | #define mmSMC_MESSAGE_1 0x96 |
94 | #define mmSMC_RESP_1 0x97 |
95 | #define mmSMC_MESSAGE_2 0x98 |
96 | #define mmSMC_RESP_2 0x99 |
97 | #define mmSMC_MESSAGE_3 0x9a |
98 | #define mmSMC_RESP_3 0x9b |
99 | #define mmSMC_MESSAGE_4 0x9c |
100 | #define mmSMC_RESP_4 0x9d |
101 | #define mmSMC_MESSAGE_5 0x9e |
102 | #define mmSMC_RESP_5 0x9f |
103 | #define mmSMC_MESSAGE_6 0xa0 |
104 | #define mmSMC_RESP_6 0xa1 |
105 | #define mmSMC_MESSAGE_7 0xa2 |
106 | #define mmSMC_RESP_7 0xa3 |
107 | #define mmSMC_MSG_ARG_0 0xa4 |
108 | #define mmSMC_MSG_ARG_1 0xa5 |
109 | #define mmSMC_MSG_ARG_2 0xa6 |
110 | #define mmSMC_MSG_ARG_3 0xa7 |
111 | #define mmSMC_MSG_ARG_4 0xa8 |
112 | #define mmSMC_MSG_ARG_5 0xa9 |
113 | #define mmSMC_MSG_ARG_6 0xaa |
114 | #define mmSMC_MSG_ARG_7 0xab |
115 | #define mmSMC_MESSAGE_8 0xb5 |
116 | #define mmSMC_RESP_8 0xb6 |
117 | #define mmSMC_MESSAGE_9 0xb7 |
118 | #define mmSMC_RESP_9 0xb8 |
119 | #define mmSMC_MESSAGE_10 0xb9 |
120 | #define mmSMC_RESP_10 0xba |
121 | #define mmSMC_MESSAGE_11 0xbb |
122 | #define mmSMC_RESP_11 0xbc |
123 | #define mmSMC_MSG_ARG_8 0xbd |
124 | #define mmSMC_MSG_ARG_9 0xbe |
125 | #define mmSMC_MSG_ARG_10 0xbf |
126 | #define mmSMC_MSG_ARG_11 0x93 |
127 | #define ixSMC_SYSCON_RESET_CNTL 0x80000000 |
128 | #define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 |
129 | #define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 |
130 | #define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c |
131 | #define ixSMC_SYSCON_MISC_CNTL 0x80000010 |
132 | #define ixSMC_SYSCON_MSG_ARG_0 0x80000068 |
133 | #define ixSMC_PC_C 0x80000370 |
134 | #define ixSMC_SCRATCH9 0x80000424 |
135 | #define mmGPIOPAD_SW_INT_STAT 0x180 |
136 | #define mmGPIOPAD_STRENGTH 0x181 |
137 | #define mmGPIOPAD_MASK 0x182 |
138 | #define mmGPIOPAD_A 0x183 |
139 | #define mmGPIOPAD_EN 0x184 |
140 | #define mmGPIOPAD_Y 0x185 |
141 | #define mmGPIOPAD_PINSTRAPS 0x186 |
142 | #define mmGPIOPAD_INT_STAT_EN 0x187 |
143 | #define mmGPIOPAD_INT_STAT 0x188 |
144 | #define mmGPIOPAD_INT_STAT_AK 0x189 |
145 | #define mmGPIOPAD_INT_EN 0x18a |
146 | #define mmGPIOPAD_INT_TYPE 0x18b |
147 | #define mmGPIOPAD_INT_POLARITY 0x18c |
148 | #define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d |
149 | #define mmGPIOPAD_RCVR_SEL 0x191 |
150 | #define mmGPIOPAD_PU_EN 0x192 |
151 | #define mmGPIOPAD_PD_EN 0x193 |
152 | #define mmCG_FPS_CNT 0x1b6 |
153 | #define mmSMU_IND_INDEX_0 0x1a6 |
154 | #define mmSMU_IND_DATA_0 0x1a7 |
155 | #define mmSMU_IND_INDEX_1 0x1a8 |
156 | #define mmSMU_IND_DATA_1 0x1a9 |
157 | #define mmSMU_IND_INDEX_2 0x1aa |
158 | #define mmSMU_IND_DATA_2 0x1ab |
159 | #define mmSMU_IND_INDEX_3 0x1ac |
160 | #define mmSMU_IND_DATA_3 0x1ad |
161 | #define mmSMU_IND_INDEX_4 0x1ae |
162 | #define mmSMU_IND_DATA_4 0x1af |
163 | #define mmSMU_IND_INDEX_5 0x1b0 |
164 | #define mmSMU_IND_DATA_5 0x1b1 |
165 | #define mmSMU_IND_INDEX_6 0x1b2 |
166 | #define mmSMU_IND_DATA_6 0x1b3 |
167 | #define mmSMU_IND_INDEX_7 0x1b4 |
168 | #define mmSMU_IND_DATA_7 0x1b5 |
169 | #define mmSMU_SMC_IND_INDEX 0x80 |
170 | #define mmSMU0_SMU_SMC_IND_INDEX 0x80 |
171 | #define mmSMU1_SMU_SMC_IND_INDEX 0x82 |
172 | #define mmSMU2_SMU_SMC_IND_INDEX 0x84 |
173 | #define mmSMU3_SMU_SMC_IND_INDEX 0x86 |
174 | #define mmSMU_SMC_IND_DATA 0x81 |
175 | #define mmSMU0_SMU_SMC_IND_DATA 0x81 |
176 | #define mmSMU1_SMU_SMC_IND_DATA 0x83 |
177 | #define mmSMU2_SMU_SMC_IND_DATA 0x85 |
178 | #define mmSMU3_SMU_SMC_IND_DATA 0x87 |
179 | #define mmSMC_IND_INDEX_11 0x1AC |
180 | #define mmSMC_IND_DATA_11 0x1AD |
181 | #define ixRCU_UC_EVENTS 0xc0000004 |
182 | #define ixRCU_MISC_CTRL 0xc0000010 |
183 | #define ixCC_RCU_FUSES 0xc00c0000 |
184 | #define ixCC_SMU_MISC_FUSES 0xc00c0004 |
185 | #define ixCC_SCLK_VID_FUSES 0xc00c0008 |
186 | #define ixCC_GIO_IOCCFG_FUSES 0xc00c000c |
187 | #define ixCC_GIO_IOC_FUSES 0xc00c0010 |
188 | #define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c |
189 | #define ixCC_TST_ID_STRAPS 0xc00c0020 |
190 | #define ixCC_FCTRL_FUSES 0xc00c0024 |
191 | #define ixCC_HARVEST_FUSES 0xc00c0028 |
192 | #define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 |
193 | #define ixSMU_STATUS 0xe0003088 |
194 | #define ixSMU_FIRMWARE 0xe00030a4 |
195 | #define ixSMU_INPUT_DATA 0xe00030b8 |
196 | #define ixSMU_EFUSE_0 0xc0100000 |
197 | #define ixMCARB_DRAM_TIMING_TABLE_1 0x33018 |
198 | #define ixMCARB_DRAM_TIMING_TABLE_2 0x3301c |
199 | #define ixMCARB_DRAM_TIMING_TABLE_3 0x33020 |
200 | #define ixMCARB_DRAM_TIMING_TABLE_4 0x33024 |
201 | #define ixMCARB_DRAM_TIMING_TABLE_5 0x33028 |
202 | #define ixMCARB_DRAM_TIMING_TABLE_6 0x3302c |
203 | #define ixMCARB_DRAM_TIMING_TABLE_7 0x33030 |
204 | #define ixMCARB_DRAM_TIMING_TABLE_8 0x33034 |
205 | #define ixMCARB_DRAM_TIMING_TABLE_9 0x33038 |
206 | #define ixMCARB_DRAM_TIMING_TABLE_10 0x3303c |
207 | #define ixMCARB_DRAM_TIMING_TABLE_11 0x33040 |
208 | #define ixMCARB_DRAM_TIMING_TABLE_12 0x33044 |
209 | #define ixMCARB_DRAM_TIMING_TABLE_13 0x33048 |
210 | #define ixMCARB_DRAM_TIMING_TABLE_14 0x3304c |
211 | #define ixMCARB_DRAM_TIMING_TABLE_15 0x33050 |
212 | #define ixMCARB_DRAM_TIMING_TABLE_16 0x33054 |
213 | #define ixMCARB_DRAM_TIMING_TABLE_17 0x33058 |
214 | #define ixMCARB_DRAM_TIMING_TABLE_18 0x3305c |
215 | #define ixMCARB_DRAM_TIMING_TABLE_19 0x33060 |
216 | #define ixMCARB_DRAM_TIMING_TABLE_20 0x33064 |
217 | #define ixMCARB_DRAM_TIMING_TABLE_21 0x33068 |
218 | #define ixMCARB_DRAM_TIMING_TABLE_22 0x3306c |
219 | #define ixMCARB_DRAM_TIMING_TABLE_23 0x33070 |
220 | #define ixMCARB_DRAM_TIMING_TABLE_24 0x33074 |
221 | #define ixMCARB_DRAM_TIMING_TABLE_25 0x33078 |
222 | #define ixMCARB_DRAM_TIMING_TABLE_26 0x3307c |
223 | #define ixMCARB_DRAM_TIMING_TABLE_27 0x33080 |
224 | #define ixMCARB_DRAM_TIMING_TABLE_28 0x33084 |
225 | #define ixMCARB_DRAM_TIMING_TABLE_29 0x33088 |
226 | #define ixMCARB_DRAM_TIMING_TABLE_30 0x3308c |
227 | #define ixMCARB_DRAM_TIMING_TABLE_31 0x33090 |
228 | #define ixMCARB_DRAM_TIMING_TABLE_32 0x33094 |
229 | #define ixMCARB_DRAM_TIMING_TABLE_33 0x33098 |
230 | #define ixMCARB_DRAM_TIMING_TABLE_34 0x3309c |
231 | #define ixMCARB_DRAM_TIMING_TABLE_35 0x330a0 |
232 | #define ixMCARB_DRAM_TIMING_TABLE_36 0x330a4 |
233 | #define ixMCARB_DRAM_TIMING_TABLE_37 0x330a8 |
234 | #define ixMCARB_DRAM_TIMING_TABLE_38 0x330ac |
235 | #define ixMCARB_DRAM_TIMING_TABLE_39 0x330b0 |
236 | #define ixMCARB_DRAM_TIMING_TABLE_40 0x330b4 |
237 | #define ixMCARB_DRAM_TIMING_TABLE_41 0x330b8 |
238 | #define ixMCARB_DRAM_TIMING_TABLE_42 0x330bc |
239 | #define ixMCARB_DRAM_TIMING_TABLE_43 0x330c0 |
240 | #define ixMCARB_DRAM_TIMING_TABLE_44 0x330c4 |
241 | #define ixMCARB_DRAM_TIMING_TABLE_45 0x330c8 |
242 | #define ixMCARB_DRAM_TIMING_TABLE_46 0x330cc |
243 | #define ixMCARB_DRAM_TIMING_TABLE_47 0x330d0 |
244 | #define ixMCARB_DRAM_TIMING_TABLE_48 0x330d4 |
245 | #define ixMCARB_DRAM_TIMING_TABLE_49 0x330d8 |
246 | #define ixMCARB_DRAM_TIMING_TABLE_50 0x330dc |
247 | #define ixMCARB_DRAM_TIMING_TABLE_51 0x330e0 |
248 | #define ixMCARB_DRAM_TIMING_TABLE_52 0x330e4 |
249 | #define ixMCARB_DRAM_TIMING_TABLE_53 0x330e8 |
250 | #define ixMCARB_DRAM_TIMING_TABLE_54 0x330ec |
251 | #define ixMCARB_DRAM_TIMING_TABLE_55 0x330f0 |
252 | #define ixMCARB_DRAM_TIMING_TABLE_56 0x330f4 |
253 | #define ixMCARB_DRAM_TIMING_TABLE_57 0x330f8 |
254 | #define ixMCARB_DRAM_TIMING_TABLE_58 0x330fc |
255 | #define ixMCARB_DRAM_TIMING_TABLE_59 0x33100 |
256 | #define ixMCARB_DRAM_TIMING_TABLE_60 0x33104 |
257 | #define ixMCARB_DRAM_TIMING_TABLE_61 0x33108 |
258 | #define ixMCARB_DRAM_TIMING_TABLE_62 0x3310c |
259 | #define ixMCARB_DRAM_TIMING_TABLE_63 0x33110 |
260 | #define ixMCARB_DRAM_TIMING_TABLE_64 0x33114 |
261 | #define ixMCARB_DRAM_TIMING_TABLE_65 0x33118 |
262 | #define ixMCARB_DRAM_TIMING_TABLE_66 0x3311c |
263 | #define ixMCARB_DRAM_TIMING_TABLE_67 0x33120 |
264 | #define ixMCARB_DRAM_TIMING_TABLE_68 0x33124 |
265 | #define ixMCARB_DRAM_TIMING_TABLE_69 0x33128 |
266 | #define ixMCARB_DRAM_TIMING_TABLE_70 0x3312c |
267 | #define ixMCARB_DRAM_TIMING_TABLE_71 0x33130 |
268 | #define ixMCARB_DRAM_TIMING_TABLE_72 0x33134 |
269 | #define ixMCARB_DRAM_TIMING_TABLE_73 0x33138 |
270 | #define ixMCARB_DRAM_TIMING_TABLE_74 0x3313c |
271 | #define ixMCARB_DRAM_TIMING_TABLE_75 0x33140 |
272 | #define ixMCARB_DRAM_TIMING_TABLE_76 0x33144 |
273 | #define ixMCARB_DRAM_TIMING_TABLE_77 0x33148 |
274 | #define ixMCARB_DRAM_TIMING_TABLE_78 0x3314c |
275 | #define ixMCARB_DRAM_TIMING_TABLE_79 0x33150 |
276 | #define ixMCARB_DRAM_TIMING_TABLE_80 0x33154 |
277 | #define ixMCARB_DRAM_TIMING_TABLE_81 0x33158 |
278 | #define ixMCARB_DRAM_TIMING_TABLE_82 0x3315c |
279 | #define ixMCARB_DRAM_TIMING_TABLE_83 0x33160 |
280 | #define ixMCARB_DRAM_TIMING_TABLE_84 0x33164 |
281 | #define ixMCARB_DRAM_TIMING_TABLE_85 0x33168 |
282 | #define ixMCARB_DRAM_TIMING_TABLE_86 0x3316c |
283 | #define ixMCARB_DRAM_TIMING_TABLE_87 0x33170 |
284 | #define ixMCARB_DRAM_TIMING_TABLE_88 0x33174 |
285 | #define ixMCARB_DRAM_TIMING_TABLE_89 0x33178 |
286 | #define ixMCARB_DRAM_TIMING_TABLE_90 0x3317c |
287 | #define ixMCARB_DRAM_TIMING_TABLE_91 0x33180 |
288 | #define ixMCARB_DRAM_TIMING_TABLE_92 0x33184 |
289 | #define ixMCARB_DRAM_TIMING_TABLE_93 0x33188 |
290 | #define ixMCARB_DRAM_TIMING_TABLE_94 0x3318c |
291 | #define ixMCARB_DRAM_TIMING_TABLE_95 0x33190 |
292 | #define ixMCARB_DRAM_TIMING_TABLE_96 0x33194 |
293 | #define ixMC_REGISTERS_TABLE_1 0x33198 |
294 | #define ixMC_REGISTERS_TABLE_2 0x3319c |
295 | #define ixMC_REGISTERS_TABLE_3 0x331a0 |
296 | #define ixMC_REGISTERS_TABLE_4 0x331a4 |
297 | #define ixMC_REGISTERS_TABLE_5 0x331a8 |
298 | #define ixMC_REGISTERS_TABLE_6 0x331ac |
299 | #define ixMC_REGISTERS_TABLE_7 0x331b0 |
300 | #define ixMC_REGISTERS_TABLE_8 0x331b4 |
301 | #define ixMC_REGISTERS_TABLE_9 0x331b8 |
302 | #define ixMC_REGISTERS_TABLE_10 0x331bc |
303 | #define ixMC_REGISTERS_TABLE_11 0x331c0 |
304 | #define ixMC_REGISTERS_TABLE_12 0x331c4 |
305 | #define ixMC_REGISTERS_TABLE_13 0x331c8 |
306 | #define ixMC_REGISTERS_TABLE_14 0x331cc |
307 | #define ixMC_REGISTERS_TABLE_15 0x331d0 |
308 | #define ixMC_REGISTERS_TABLE_16 0x331d4 |
309 | #define ixMC_REGISTERS_TABLE_17 0x331d8 |
310 | #define ixMC_REGISTERS_TABLE_18 0x331dc |
311 | #define ixMC_REGISTERS_TABLE_19 0x331e0 |
312 | #define ixMC_REGISTERS_TABLE_20 0x331e4 |
313 | #define ixMC_REGISTERS_TABLE_21 0x331e8 |
314 | #define ixMC_REGISTERS_TABLE_22 0x331ec |
315 | #define ixMC_REGISTERS_TABLE_23 0x331f0 |
316 | #define ixMC_REGISTERS_TABLE_24 0x331f4 |
317 | #define ixMC_REGISTERS_TABLE_25 0x331f8 |
318 | #define ixMC_REGISTERS_TABLE_26 0x331fc |
319 | #define ixMC_REGISTERS_TABLE_27 0x33200 |
320 | #define ixMC_REGISTERS_TABLE_28 0x33204 |
321 | #define ixMC_REGISTERS_TABLE_29 0x33208 |
322 | #define ixMC_REGISTERS_TABLE_30 0x3320c |
323 | #define ixMC_REGISTERS_TABLE_31 0x33210 |
324 | #define ixMC_REGISTERS_TABLE_32 0x33214 |
325 | #define ixMC_REGISTERS_TABLE_33 0x33218 |
326 | #define ixMC_REGISTERS_TABLE_34 0x3321c |
327 | #define ixMC_REGISTERS_TABLE_35 0x33220 |
328 | #define ixMC_REGISTERS_TABLE_36 0x33224 |
329 | #define ixMC_REGISTERS_TABLE_37 0x33228 |
330 | #define ixMC_REGISTERS_TABLE_38 0x3322c |
331 | #define ixMC_REGISTERS_TABLE_39 0x33230 |
332 | #define ixMC_REGISTERS_TABLE_40 0x33234 |
333 | #define ixMC_REGISTERS_TABLE_41 0x33238 |
334 | #define ixMC_REGISTERS_TABLE_42 0x3323c |
335 | #define ixMC_REGISTERS_TABLE_43 0x33240 |
336 | #define ixMC_REGISTERS_TABLE_44 0x33244 |
337 | #define ixMC_REGISTERS_TABLE_45 0x33248 |
338 | #define ixMC_REGISTERS_TABLE_46 0x3324c |
339 | #define ixMC_REGISTERS_TABLE_47 0x33250 |
340 | #define ixMC_REGISTERS_TABLE_48 0x33254 |
341 | #define ixMC_REGISTERS_TABLE_49 0x33258 |
342 | #define ixMC_REGISTERS_TABLE_50 0x3325c |
343 | #define ixMC_REGISTERS_TABLE_51 0x33260 |
344 | #define ixMC_REGISTERS_TABLE_52 0x33264 |
345 | #define ixMC_REGISTERS_TABLE_53 0x33268 |
346 | #define ixMC_REGISTERS_TABLE_54 0x3326c |
347 | #define ixMC_REGISTERS_TABLE_55 0x33270 |
348 | #define ixMC_REGISTERS_TABLE_56 0x33274 |
349 | #define ixMC_REGISTERS_TABLE_57 0x33278 |
350 | #define ixMC_REGISTERS_TABLE_58 0x3327c |
351 | #define ixMC_REGISTERS_TABLE_59 0x33280 |
352 | #define ixMC_REGISTERS_TABLE_60 0x33284 |
353 | #define ixMC_REGISTERS_TABLE_61 0x33288 |
354 | #define ixMC_REGISTERS_TABLE_62 0x3328c |
355 | #define ixMC_REGISTERS_TABLE_63 0x33290 |
356 | #define ixMC_REGISTERS_TABLE_64 0x33294 |
357 | #define ixMC_REGISTERS_TABLE_65 0x33298 |
358 | #define ixMC_REGISTERS_TABLE_66 0x3329c |
359 | #define ixMC_REGISTERS_TABLE_67 0x332a0 |
360 | #define ixMC_REGISTERS_TABLE_68 0x332a4 |
361 | #define ixMC_REGISTERS_TABLE_69 0x332a8 |
362 | #define ixMC_REGISTERS_TABLE_70 0x332ac |
363 | #define ixMC_REGISTERS_TABLE_71 0x332b0 |
364 | #define ixMC_REGISTERS_TABLE_72 0x332b4 |
365 | #define ixMC_REGISTERS_TABLE_73 0x332b8 |
366 | #define ixMC_REGISTERS_TABLE_74 0x332bc |
367 | #define ixMC_REGISTERS_TABLE_75 0x332c0 |
368 | #define ixMC_REGISTERS_TABLE_76 0x332c4 |
369 | #define ixMC_REGISTERS_TABLE_77 0x332c8 |
370 | #define ixMC_REGISTERS_TABLE_78 0x332cc |
371 | #define ixMC_REGISTERS_TABLE_79 0x332d0 |
372 | #define ixMC_REGISTERS_TABLE_80 0x332d4 |
373 | #define ixMC_REGISTERS_TABLE_81 0x332d8 |
374 | #define ixDPM_TABLE_1 0x332dc |
375 | #define ixDPM_TABLE_2 0x332e0 |
376 | #define ixDPM_TABLE_3 0x332e4 |
377 | #define ixDPM_TABLE_4 0x332e8 |
378 | #define ixDPM_TABLE_5 0x332ec |
379 | #define ixDPM_TABLE_6 0x332f0 |
380 | #define ixDPM_TABLE_7 0x332f4 |
381 | #define ixDPM_TABLE_8 0x332f8 |
382 | #define ixDPM_TABLE_9 0x332fc |
383 | #define ixDPM_TABLE_10 0x33300 |
384 | #define ixDPM_TABLE_11 0x33304 |
385 | #define ixDPM_TABLE_12 0x33308 |
386 | #define ixDPM_TABLE_13 0x3330c |
387 | #define ixDPM_TABLE_14 0x33310 |
388 | #define ixDPM_TABLE_15 0x33314 |
389 | #define ixDPM_TABLE_16 0x33318 |
390 | #define ixDPM_TABLE_17 0x3331c |
391 | #define ixDPM_TABLE_18 0x33320 |
392 | #define ixDPM_TABLE_19 0x33324 |
393 | #define ixDPM_TABLE_20 0x33328 |
394 | #define ixDPM_TABLE_21 0x3332c |
395 | #define ixDPM_TABLE_22 0x33330 |
396 | #define ixDPM_TABLE_23 0x33334 |
397 | #define ixDPM_TABLE_24 0x33338 |
398 | #define ixDPM_TABLE_25 0x3333c |
399 | #define ixDPM_TABLE_26 0x33340 |
400 | #define ixDPM_TABLE_27 0x33344 |
401 | #define ixDPM_TABLE_28 0x33348 |
402 | #define ixDPM_TABLE_29 0x3334c |
403 | #define ixDPM_TABLE_30 0x33350 |
404 | #define ixDPM_TABLE_31 0x33354 |
405 | #define ixDPM_TABLE_32 0x33358 |
406 | #define ixDPM_TABLE_33 0x3335c |
407 | #define ixDPM_TABLE_34 0x33360 |
408 | #define ixDPM_TABLE_35 0x33364 |
409 | #define ixDPM_TABLE_36 0x33368 |
410 | #define ixDPM_TABLE_37 0x3336c |
411 | #define ixDPM_TABLE_38 0x33370 |
412 | #define ixDPM_TABLE_39 0x33374 |
413 | #define ixDPM_TABLE_40 0x33378 |
414 | #define ixDPM_TABLE_41 0x3337c |
415 | #define ixDPM_TABLE_42 0x33380 |
416 | #define ixDPM_TABLE_43 0x33384 |
417 | #define ixDPM_TABLE_44 0x33388 |
418 | #define ixDPM_TABLE_45 0x3338c |
419 | #define ixDPM_TABLE_46 0x33390 |
420 | #define ixDPM_TABLE_47 0x33394 |
421 | #define ixDPM_TABLE_48 0x33398 |
422 | #define ixDPM_TABLE_49 0x3339c |
423 | #define ixDPM_TABLE_50 0x333a0 |
424 | #define ixDPM_TABLE_51 0x333a4 |
425 | #define ixDPM_TABLE_52 0x333a8 |
426 | #define ixDPM_TABLE_53 0x333ac |
427 | #define ixDPM_TABLE_54 0x333b0 |
428 | #define ixDPM_TABLE_55 0x333b4 |
429 | #define ixDPM_TABLE_56 0x333b8 |
430 | #define ixDPM_TABLE_57 0x333bc |
431 | #define ixDPM_TABLE_58 0x333c0 |
432 | #define ixDPM_TABLE_59 0x333c4 |
433 | #define ixDPM_TABLE_60 0x333c8 |
434 | #define ixDPM_TABLE_61 0x333cc |
435 | #define ixDPM_TABLE_62 0x333d0 |
436 | #define ixDPM_TABLE_63 0x333d4 |
437 | #define ixDPM_TABLE_64 0x333d8 |
438 | #define ixDPM_TABLE_65 0x333dc |
439 | #define ixDPM_TABLE_66 0x333e0 |
440 | #define ixDPM_TABLE_67 0x333e4 |
441 | #define ixDPM_TABLE_68 0x333e8 |
442 | #define ixDPM_TABLE_69 0x333ec |
443 | #define ixDPM_TABLE_70 0x333f0 |
444 | #define ixDPM_TABLE_71 0x333f4 |
445 | #define ixDPM_TABLE_72 0x333f8 |
446 | #define ixDPM_TABLE_73 0x333fc |
447 | #define ixDPM_TABLE_74 0x33400 |
448 | #define ixDPM_TABLE_75 0x33404 |
449 | #define ixDPM_TABLE_76 0x33408 |
450 | #define ixDPM_TABLE_77 0x3340c |
451 | #define ixDPM_TABLE_78 0x33410 |
452 | #define ixDPM_TABLE_79 0x33414 |
453 | #define ixDPM_TABLE_80 0x33418 |
454 | #define ixDPM_TABLE_81 0x3341c |
455 | #define ixDPM_TABLE_82 0x33420 |
456 | #define ixDPM_TABLE_83 0x33424 |
457 | #define ixDPM_TABLE_84 0x33428 |
458 | #define ixDPM_TABLE_85 0x3342c |
459 | #define ixDPM_TABLE_86 0x33430 |
460 | #define ixDPM_TABLE_87 0x33434 |
461 | #define ixDPM_TABLE_88 0x33438 |
462 | #define ixDPM_TABLE_89 0x3343c |
463 | #define ixDPM_TABLE_90 0x33440 |
464 | #define ixDPM_TABLE_91 0x33444 |
465 | #define ixDPM_TABLE_92 0x33448 |
466 | #define ixDPM_TABLE_93 0x3344c |
467 | #define ixDPM_TABLE_94 0x33450 |
468 | #define ixDPM_TABLE_95 0x33454 |
469 | #define ixDPM_TABLE_96 0x33458 |
470 | #define ixDPM_TABLE_97 0x3345c |
471 | #define ixDPM_TABLE_98 0x33460 |
472 | #define ixDPM_TABLE_99 0x33464 |
473 | #define ixDPM_TABLE_100 0x33468 |
474 | #define ixDPM_TABLE_101 0x3346c |
475 | #define ixDPM_TABLE_102 0x33470 |
476 | #define ixDPM_TABLE_103 0x33474 |
477 | #define ixDPM_TABLE_104 0x33478 |
478 | #define ixDPM_TABLE_105 0x3347c |
479 | #define ixDPM_TABLE_106 0x33480 |
480 | #define ixDPM_TABLE_107 0x33484 |
481 | #define ixDPM_TABLE_108 0x33488 |
482 | #define ixDPM_TABLE_109 0x3348c |
483 | #define ixDPM_TABLE_110 0x33490 |
484 | #define ixDPM_TABLE_111 0x33494 |
485 | #define ixDPM_TABLE_112 0x33498 |
486 | #define ixDPM_TABLE_113 0x3349c |
487 | #define ixDPM_TABLE_114 0x334a0 |
488 | #define ixDPM_TABLE_115 0x334a4 |
489 | #define ixDPM_TABLE_116 0x334a8 |
490 | #define ixDPM_TABLE_117 0x334ac |
491 | #define ixDPM_TABLE_118 0x334b0 |
492 | #define ixDPM_TABLE_119 0x334b4 |
493 | #define ixDPM_TABLE_120 0x334b8 |
494 | #define ixDPM_TABLE_121 0x334bc |
495 | #define ixDPM_TABLE_122 0x334c0 |
496 | #define ixDPM_TABLE_123 0x334c4 |
497 | #define ixDPM_TABLE_124 0x334c8 |
498 | #define ixDPM_TABLE_125 0x334cc |
499 | #define ixDPM_TABLE_126 0x334d0 |
500 | #define ixDPM_TABLE_127 0x334d4 |
501 | #define ixDPM_TABLE_128 0x334d8 |
502 | #define ixDPM_TABLE_129 0x334dc |
503 | #define ixDPM_TABLE_130 0x334e0 |
504 | #define ixDPM_TABLE_131 0x334e4 |
505 | #define ixDPM_TABLE_132 0x334e8 |
506 | #define ixDPM_TABLE_133 0x334ec |
507 | #define ixDPM_TABLE_134 0x334f0 |
508 | #define ixDPM_TABLE_135 0x334f4 |
509 | #define ixDPM_TABLE_136 0x334f8 |
510 | #define ixDPM_TABLE_137 0x334fc |
511 | #define ixDPM_TABLE_138 0x33500 |
512 | #define ixDPM_TABLE_139 0x33504 |
513 | #define ixDPM_TABLE_140 0x33508 |
514 | #define ixDPM_TABLE_141 0x3350c |
515 | #define ixDPM_TABLE_142 0x33510 |
516 | #define ixDPM_TABLE_143 0x33514 |
517 | #define ixDPM_TABLE_144 0x33518 |
518 | #define ixDPM_TABLE_145 0x3351c |
519 | #define ixDPM_TABLE_146 0x33520 |
520 | #define ixDPM_TABLE_147 0x33524 |
521 | #define ixDPM_TABLE_148 0x33528 |
522 | #define ixDPM_TABLE_149 0x3352c |
523 | #define ixDPM_TABLE_150 0x33530 |
524 | #define ixDPM_TABLE_151 0x33534 |
525 | #define ixDPM_TABLE_152 0x33538 |
526 | #define ixDPM_TABLE_153 0x3353c |
527 | #define ixDPM_TABLE_154 0x33540 |
528 | #define ixDPM_TABLE_155 0x33544 |
529 | #define ixDPM_TABLE_156 0x33548 |
530 | #define ixDPM_TABLE_157 0x3354c |
531 | #define ixDPM_TABLE_158 0x33550 |
532 | #define ixDPM_TABLE_159 0x33554 |
533 | #define ixDPM_TABLE_160 0x33558 |
534 | #define ixDPM_TABLE_161 0x3355c |
535 | #define ixDPM_TABLE_162 0x33560 |
536 | #define ixDPM_TABLE_163 0x33564 |
537 | #define ixDPM_TABLE_164 0x33568 |
538 | #define ixDPM_TABLE_165 0x3356c |
539 | #define ixDPM_TABLE_166 0x33570 |
540 | #define ixDPM_TABLE_167 0x33574 |
541 | #define ixDPM_TABLE_168 0x33578 |
542 | #define ixDPM_TABLE_169 0x3357c |
543 | #define ixDPM_TABLE_170 0x33580 |
544 | #define ixDPM_TABLE_171 0x33584 |
545 | #define ixDPM_TABLE_172 0x33588 |
546 | #define ixDPM_TABLE_173 0x3358c |
547 | #define ixDPM_TABLE_174 0x33590 |
548 | #define ixDPM_TABLE_175 0x33594 |
549 | #define ixDPM_TABLE_176 0x33598 |
550 | #define ixDPM_TABLE_177 0x3359c |
551 | #define ixDPM_TABLE_178 0x335a0 |
552 | #define ixDPM_TABLE_179 0x335a4 |
553 | #define ixDPM_TABLE_180 0x335a8 |
554 | #define ixDPM_TABLE_181 0x335ac |
555 | #define ixDPM_TABLE_182 0x335b0 |
556 | #define ixDPM_TABLE_183 0x335b4 |
557 | #define ixDPM_TABLE_184 0x335b8 |
558 | #define ixDPM_TABLE_185 0x335bc |
559 | #define ixDPM_TABLE_186 0x335c0 |
560 | #define ixDPM_TABLE_187 0x335c4 |
561 | #define ixDPM_TABLE_188 0x335c8 |
562 | #define ixDPM_TABLE_189 0x335cc |
563 | #define ixDPM_TABLE_190 0x335d0 |
564 | #define ixDPM_TABLE_191 0x335d4 |
565 | #define ixDPM_TABLE_192 0x335d8 |
566 | #define ixDPM_TABLE_193 0x335dc |
567 | #define ixDPM_TABLE_194 0x335e0 |
568 | #define ixDPM_TABLE_195 0x335e4 |
569 | #define ixDPM_TABLE_196 0x335e8 |
570 | #define ixDPM_TABLE_197 0x335ec |
571 | #define ixDPM_TABLE_198 0x335f0 |
572 | #define ixDPM_TABLE_199 0x335f4 |
573 | #define ixDPM_TABLE_200 0x335f8 |
574 | #define ixDPM_TABLE_201 0x335fc |
575 | #define ixDPM_TABLE_202 0x33600 |
576 | #define ixDPM_TABLE_203 0x33604 |
577 | #define ixDPM_TABLE_204 0x33608 |
578 | #define ixDPM_TABLE_205 0x3360c |
579 | #define ixDPM_TABLE_206 0x33610 |
580 | #define ixDPM_TABLE_207 0x33614 |
581 | #define ixDPM_TABLE_208 0x33618 |
582 | #define ixDPM_TABLE_209 0x3361c |
583 | #define ixDPM_TABLE_210 0x33620 |
584 | #define ixDPM_TABLE_211 0x33624 |
585 | #define ixDPM_TABLE_212 0x33628 |
586 | #define ixDPM_TABLE_213 0x3362c |
587 | #define ixDPM_TABLE_214 0x33630 |
588 | #define ixDPM_TABLE_215 0x33634 |
589 | #define ixDPM_TABLE_216 0x33638 |
590 | #define ixDPM_TABLE_217 0x3363c |
591 | #define ixDPM_TABLE_218 0x33640 |
592 | #define ixDPM_TABLE_219 0x33644 |
593 | #define ixDPM_TABLE_220 0x33648 |
594 | #define ixDPM_TABLE_221 0x3364c |
595 | #define ixDPM_TABLE_222 0x33650 |
596 | #define ixDPM_TABLE_223 0x33654 |
597 | #define ixDPM_TABLE_224 0x33658 |
598 | #define ixDPM_TABLE_225 0x3365c |
599 | #define ixDPM_TABLE_226 0x33660 |
600 | #define ixDPM_TABLE_227 0x33664 |
601 | #define ixDPM_TABLE_228 0x33668 |
602 | #define ixDPM_TABLE_229 0x3366c |
603 | #define ixDPM_TABLE_230 0x33670 |
604 | #define ixDPM_TABLE_231 0x33674 |
605 | #define ixDPM_TABLE_232 0x33678 |
606 | #define ixDPM_TABLE_233 0x3367c |
607 | #define ixDPM_TABLE_234 0x33680 |
608 | #define ixDPM_TABLE_235 0x33684 |
609 | #define ixDPM_TABLE_236 0x33688 |
610 | #define ixDPM_TABLE_237 0x3368c |
611 | #define ixDPM_TABLE_238 0x33690 |
612 | #define ixDPM_TABLE_239 0x33694 |
613 | #define ixDPM_TABLE_240 0x33698 |
614 | #define ixDPM_TABLE_241 0x3369c |
615 | #define ixDPM_TABLE_242 0x336a0 |
616 | #define ixDPM_TABLE_243 0x336a4 |
617 | #define ixDPM_TABLE_244 0x336a8 |
618 | #define ixDPM_TABLE_245 0x336ac |
619 | #define ixDPM_TABLE_246 0x336b0 |
620 | #define ixDPM_TABLE_247 0x336b4 |
621 | #define ixDPM_TABLE_248 0x336b8 |
622 | #define ixDPM_TABLE_249 0x336bc |
623 | #define ixDPM_TABLE_250 0x336c0 |
624 | #define ixDPM_TABLE_251 0x336c4 |
625 | #define ixDPM_TABLE_252 0x336c8 |
626 | #define ixDPM_TABLE_253 0x336cc |
627 | #define ixDPM_TABLE_254 0x336d0 |
628 | #define ixDPM_TABLE_255 0x336d4 |
629 | #define ixDPM_TABLE_256 0x336d8 |
630 | #define ixDPM_TABLE_257 0x336dc |
631 | #define ixDPM_TABLE_258 0x336e0 |
632 | #define ixDPM_TABLE_259 0x336e4 |
633 | #define ixDPM_TABLE_260 0x336e8 |
634 | #define ixDPM_TABLE_261 0x336ec |
635 | #define ixDPM_TABLE_262 0x336f0 |
636 | #define ixDPM_TABLE_263 0x336f4 |
637 | #define ixDPM_TABLE_264 0x336f8 |
638 | #define ixDPM_TABLE_265 0x336fc |
639 | #define ixDPM_TABLE_266 0x33700 |
640 | #define ixDPM_TABLE_267 0x33704 |
641 | #define ixDPM_TABLE_268 0x33708 |
642 | #define ixDPM_TABLE_269 0x3370c |
643 | #define ixDPM_TABLE_270 0x33710 |
644 | #define ixDPM_TABLE_271 0x33714 |
645 | #define ixDPM_TABLE_272 0x33718 |
646 | #define ixDPM_TABLE_273 0x3371c |
647 | #define ixDPM_TABLE_274 0x33720 |
648 | #define ixDPM_TABLE_275 0x33724 |
649 | #define ixDPM_TABLE_276 0x33728 |
650 | #define ixDPM_TABLE_277 0x3372c |
651 | #define ixDPM_TABLE_278 0x33730 |
652 | #define ixDPM_TABLE_279 0x33734 |
653 | #define ixDPM_TABLE_280 0x33738 |
654 | #define ixDPM_TABLE_281 0x3373c |
655 | #define ixDPM_TABLE_282 0x33740 |
656 | #define ixDPM_TABLE_283 0x33744 |
657 | #define ixDPM_TABLE_284 0x33748 |
658 | #define ixDPM_TABLE_285 0x3374c |
659 | #define ixDPM_TABLE_286 0x33750 |
660 | #define ixDPM_TABLE_287 0x33754 |
661 | #define ixDPM_TABLE_288 0x33758 |
662 | #define ixDPM_TABLE_289 0x3375c |
663 | #define ixDPM_TABLE_290 0x33760 |
664 | #define ixDPM_TABLE_291 0x33764 |
665 | #define ixDPM_TABLE_292 0x33768 |
666 | #define ixDPM_TABLE_293 0x3376c |
667 | #define ixDPM_TABLE_294 0x33770 |
668 | #define ixDPM_TABLE_295 0x33774 |
669 | #define ixDPM_TABLE_296 0x33778 |
670 | #define ixDPM_TABLE_297 0x3377c |
671 | #define ixDPM_TABLE_298 0x33780 |
672 | #define ixDPM_TABLE_299 0x33784 |
673 | #define ixDPM_TABLE_300 0x33788 |
674 | #define ixDPM_TABLE_301 0x3378c |
675 | #define ixDPM_TABLE_302 0x33790 |
676 | #define ixDPM_TABLE_303 0x33794 |
677 | #define ixDPM_TABLE_304 0x33798 |
678 | #define ixDPM_TABLE_305 0x3379c |
679 | #define ixDPM_TABLE_306 0x337a0 |
680 | #define ixDPM_TABLE_307 0x337a4 |
681 | #define ixDPM_TABLE_308 0x337a8 |
682 | #define ixDPM_TABLE_309 0x337ac |
683 | #define ixDPM_TABLE_310 0x337b0 |
684 | #define ixDPM_TABLE_311 0x337b4 |
685 | #define ixDPM_TABLE_312 0x337b8 |
686 | #define ixDPM_TABLE_313 0x337bc |
687 | #define ixDPM_TABLE_314 0x337c0 |
688 | #define ixDPM_TABLE_315 0x337c4 |
689 | #define ixDPM_TABLE_316 0x337c8 |
690 | #define ixDPM_TABLE_317 0x337cc |
691 | #define ixDPM_TABLE_318 0x337d0 |
692 | #define ixDPM_TABLE_319 0x337d4 |
693 | #define ixDPM_TABLE_320 0x337d8 |
694 | #define ixDPM_TABLE_321 0x337dc |
695 | #define ixDPM_TABLE_322 0x337e0 |
696 | #define ixDPM_TABLE_323 0x337e4 |
697 | #define ixDPM_TABLE_324 0x337e8 |
698 | #define ixDPM_TABLE_325 0x337ec |
699 | #define ixDPM_TABLE_326 0x337f0 |
700 | #define ixDPM_TABLE_327 0x337f4 |
701 | #define ixDPM_TABLE_328 0x337f8 |
702 | #define ixDPM_TABLE_329 0x337fc |
703 | #define ixDPM_TABLE_330 0x33800 |
704 | #define ixDPM_TABLE_331 0x33804 |
705 | #define ixDPM_TABLE_332 0x33808 |
706 | #define ixDPM_TABLE_333 0x3380c |
707 | #define ixDPM_TABLE_334 0x33810 |
708 | #define ixDPM_TABLE_335 0x33814 |
709 | #define ixDPM_TABLE_336 0x33818 |
710 | #define ixDPM_TABLE_337 0x3381c |
711 | #define ixDPM_TABLE_338 0x33820 |
712 | #define ixDPM_TABLE_339 0x33824 |
713 | #define ixDPM_TABLE_340 0x33828 |
714 | #define ixDPM_TABLE_341 0x3382c |
715 | #define ixDPM_TABLE_342 0x33830 |
716 | #define ixDPM_TABLE_343 0x33834 |
717 | #define ixDPM_TABLE_344 0x33838 |
718 | #define ixDPM_TABLE_345 0x3383c |
719 | #define ixDPM_TABLE_346 0x33840 |
720 | #define ixDPM_TABLE_347 0x33844 |
721 | #define ixDPM_TABLE_348 0x33848 |
722 | #define ixDPM_TABLE_349 0x3384c |
723 | #define ixDPM_TABLE_350 0x33850 |
724 | #define ixDPM_TABLE_351 0x33854 |
725 | #define ixDPM_TABLE_352 0x33858 |
726 | #define ixDPM_TABLE_353 0x3385c |
727 | #define ixDPM_TABLE_354 0x33860 |
728 | #define ixDPM_TABLE_355 0x33864 |
729 | #define ixDPM_TABLE_356 0x33868 |
730 | #define ixDPM_TABLE_357 0x3386c |
731 | #define ixDPM_TABLE_358 0x33870 |
732 | #define ixDPM_TABLE_359 0x33874 |
733 | #define ixDPM_TABLE_360 0x33878 |
734 | #define ixDPM_TABLE_361 0x3387c |
735 | #define ixDPM_TABLE_362 0x33880 |
736 | #define ixDPM_TABLE_363 0x33884 |
737 | #define ixDPM_TABLE_364 0x33888 |
738 | #define ixDPM_TABLE_365 0x3388c |
739 | #define ixDPM_TABLE_366 0x33890 |
740 | #define ixDPM_TABLE_367 0x33894 |
741 | #define ixDPM_TABLE_368 0x33898 |
742 | #define ixDPM_TABLE_369 0x3389c |
743 | #define ixDPM_TABLE_370 0x338a0 |
744 | #define ixSOFT_REGISTERS_TABLE_1 0x338c8 |
745 | #define ixSOFT_REGISTERS_TABLE_2 0x338cc |
746 | #define ixSOFT_REGISTERS_TABLE_3 0x338d0 |
747 | #define ixSOFT_REGISTERS_TABLE_4 0x338d4 |
748 | #define ixSOFT_REGISTERS_TABLE_5 0x338d8 |
749 | #define ixSOFT_REGISTERS_TABLE_6 0x338dc |
750 | #define ixSOFT_REGISTERS_TABLE_7 0x338e0 |
751 | #define ixSOFT_REGISTERS_TABLE_8 0x338e4 |
752 | #define ixSOFT_REGISTERS_TABLE_9 0x338e8 |
753 | #define ixSOFT_REGISTERS_TABLE_10 0x338ec |
754 | #define ixSOFT_REGISTERS_TABLE_11 0x338f0 |
755 | #define ixSOFT_REGISTERS_TABLE_12 0x338f4 |
756 | #define ixSOFT_REGISTERS_TABLE_13 0x338f8 |
757 | #define ixSOFT_REGISTERS_TABLE_14 0x338fc |
758 | #define ixSOFT_REGISTERS_TABLE_15 0x33900 |
759 | #define ixSOFT_REGISTERS_TABLE_16 0x33904 |
760 | #define ixSOFT_REGISTERS_TABLE_17 0x33908 |
761 | #define ixSOFT_REGISTERS_TABLE_18 0x3390c |
762 | #define ixSOFT_REGISTERS_TABLE_19 0x33910 |
763 | #define ixSOFT_REGISTERS_TABLE_20 0x33914 |
764 | #define ixSOFT_REGISTERS_TABLE_21 0x33918 |
765 | #define ixSOFT_REGISTERS_TABLE_22 0x3391c |
766 | #define ixSOFT_REGISTERS_TABLE_23 0x33920 |
767 | #define ixSOFT_REGISTERS_TABLE_24 0x33924 |
768 | #define ixSOFT_REGISTERS_TABLE_25 0x33928 |
769 | #define ixSOFT_REGISTERS_TABLE_26 0x3392c |
770 | #define ixSOFT_REGISTERS_TABLE_27 0x33930 |
771 | #define ixSOFT_REGISTERS_TABLE_28 0x33934 |
772 | #define ixSOFT_REGISTERS_TABLE_29 0x33938 |
773 | #define ixFIRMWARE_FLAGS 0x33000 |
774 | #define ixTDC_STATUS 0x33004 |
775 | #define ixTDC_MV_AVERAGE 0x33008 |
776 | #define ixTDC_VRM_LIMIT 0x3300c |
777 | #define ixFEATURE_STATUS 0x33010 |
778 | #define ixENTITY_TEMPERATURES_1 0x33014 |
779 | #define ixPM_FUSES_1 0x3394c |
780 | #define ixPM_FUSES_2 0x33950 |
781 | #define ixPM_FUSES_3 0x33954 |
782 | #define ixPM_FUSES_4 0x33958 |
783 | #define ixPM_FUSES_5 0x3395c |
784 | #define ixPM_FUSES_6 0x33960 |
785 | #define ixPM_FUSES_7 0x33964 |
786 | #define ixPM_FUSES_8 0x33968 |
787 | #define ixPM_FUSES_9 0x3396c |
788 | #define ixPM_FUSES_10 0x33970 |
789 | #define ixPM_FUSES_11 0x33974 |
790 | #define ixPM_FUSES_12 0x33978 |
791 | #define ixPM_FUSES_13 0x3397c |
792 | #define ixPM_FUSES_14 0x33980 |
793 | #define ixPM_FUSES_15 0x33984 |
794 | #define ixPM_FUSES_16 0x33988 |
795 | #define ixPM_FUSES_17 0x3398c |
796 | #define ixPM_FUSES_18 0x33990 |
797 | #define ixPM_FUSES_19 0x33994 |
798 | #define ixPM_FUSES_20 0x33998 |
799 | #define ixPM_FUSES_21 0x3399c |
800 | #define ixSMU_PM_STATUS_0 0x33e00 |
801 | #define ixSMU_PM_STATUS_1 0x33e04 |
802 | #define ixSMU_PM_STATUS_2 0x33e08 |
803 | #define ixSMU_PM_STATUS_3 0x33e0c |
804 | #define ixSMU_PM_STATUS_4 0x33e10 |
805 | #define ixSMU_PM_STATUS_5 0x33e14 |
806 | #define ixSMU_PM_STATUS_6 0x33e18 |
807 | #define ixSMU_PM_STATUS_7 0x33e1c |
808 | #define ixSMU_PM_STATUS_8 0x33e20 |
809 | #define ixSMU_PM_STATUS_9 0x33e24 |
810 | #define ixSMU_PM_STATUS_10 0x33e28 |
811 | #define ixSMU_PM_STATUS_11 0x33e2c |
812 | #define ixSMU_PM_STATUS_12 0x33e30 |
813 | #define ixSMU_PM_STATUS_13 0x33e34 |
814 | #define ixSMU_PM_STATUS_14 0x33e38 |
815 | #define ixSMU_PM_STATUS_15 0x33e3c |
816 | #define ixSMU_PM_STATUS_16 0x33e40 |
817 | #define ixSMU_PM_STATUS_17 0x33e44 |
818 | #define ixSMU_PM_STATUS_18 0x33e48 |
819 | #define ixSMU_PM_STATUS_19 0x33e4c |
820 | #define ixSMU_PM_STATUS_20 0x33e50 |
821 | #define ixSMU_PM_STATUS_21 0x33e54 |
822 | #define ixSMU_PM_STATUS_22 0x33e58 |
823 | #define ixSMU_PM_STATUS_23 0x33e5c |
824 | #define ixSMU_PM_STATUS_24 0x33e60 |
825 | #define ixSMU_PM_STATUS_25 0x33e64 |
826 | #define ixSMU_PM_STATUS_26 0x33e68 |
827 | #define ixSMU_PM_STATUS_27 0x33e6c |
828 | #define ixSMU_PM_STATUS_28 0x33e70 |
829 | #define ixSMU_PM_STATUS_29 0x33e74 |
830 | #define ixSMU_PM_STATUS_30 0x33e78 |
831 | #define ixSMU_PM_STATUS_31 0x33e7c |
832 | #define ixSMU_PM_STATUS_32 0x33e80 |
833 | #define ixSMU_PM_STATUS_33 0x33e84 |
834 | #define ixSMU_PM_STATUS_34 0x33e88 |
835 | #define ixSMU_PM_STATUS_35 0x33e8c |
836 | #define ixSMU_PM_STATUS_36 0x33e90 |
837 | #define ixSMU_PM_STATUS_37 0x33e94 |
838 | #define ixSMU_PM_STATUS_38 0x33e98 |
839 | #define ixSMU_PM_STATUS_39 0x33e9c |
840 | #define ixSMU_PM_STATUS_40 0x33ea0 |
841 | #define ixSMU_PM_STATUS_41 0x33ea4 |
842 | #define ixSMU_PM_STATUS_42 0x33ea8 |
843 | #define ixSMU_PM_STATUS_43 0x33eac |
844 | #define ixSMU_PM_STATUS_44 0x33eb0 |
845 | #define ixSMU_PM_STATUS_45 0x33eb4 |
846 | #define ixSMU_PM_STATUS_46 0x33eb8 |
847 | #define ixSMU_PM_STATUS_47 0x33ebc |
848 | #define ixSMU_PM_STATUS_48 0x33ec0 |
849 | #define ixSMU_PM_STATUS_49 0x33ec4 |
850 | #define ixSMU_PM_STATUS_50 0x33ec8 |
851 | #define ixSMU_PM_STATUS_51 0x33ecc |
852 | #define ixSMU_PM_STATUS_52 0x33ed0 |
853 | #define ixSMU_PM_STATUS_53 0x33ed4 |
854 | #define ixSMU_PM_STATUS_54 0x33ed8 |
855 | #define ixSMU_PM_STATUS_55 0x33edc |
856 | #define ixSMU_PM_STATUS_56 0x33ee0 |
857 | #define ixSMU_PM_STATUS_57 0x33ee4 |
858 | #define ixSMU_PM_STATUS_58 0x33ee8 |
859 | #define ixSMU_PM_STATUS_59 0x33eec |
860 | #define ixSMU_PM_STATUS_60 0x33ef0 |
861 | #define ixSMU_PM_STATUS_61 0x33ef4 |
862 | #define ixSMU_PM_STATUS_62 0x33ef8 |
863 | #define ixSMU_PM_STATUS_63 0x33efc |
864 | #define ixSMU_PM_STATUS_64 0x33f00 |
865 | #define ixSMU_PM_STATUS_65 0x33f04 |
866 | #define ixSMU_PM_STATUS_66 0x33f08 |
867 | #define ixSMU_PM_STATUS_67 0x33f0c |
868 | #define ixSMU_PM_STATUS_68 0x33f10 |
869 | #define ixSMU_PM_STATUS_69 0x33f14 |
870 | #define ixSMU_PM_STATUS_70 0x33f18 |
871 | #define ixSMU_PM_STATUS_71 0x33f1c |
872 | #define ixSMU_PM_STATUS_72 0x33f20 |
873 | #define ixSMU_PM_STATUS_73 0x33f24 |
874 | #define ixSMU_PM_STATUS_74 0x33f28 |
875 | #define ixSMU_PM_STATUS_75 0x33f2c |
876 | #define ixSMU_PM_STATUS_76 0x33f30 |
877 | #define ixSMU_PM_STATUS_77 0x33f34 |
878 | #define ixSMU_PM_STATUS_78 0x33f38 |
879 | #define ixSMU_PM_STATUS_79 0x33f3c |
880 | #define ixSMU_PM_STATUS_80 0x33f40 |
881 | #define ixSMU_PM_STATUS_81 0x33f44 |
882 | #define ixSMU_PM_STATUS_82 0x33f48 |
883 | #define ixSMU_PM_STATUS_83 0x33f4c |
884 | #define ixSMU_PM_STATUS_84 0x33f50 |
885 | #define ixSMU_PM_STATUS_85 0x33f54 |
886 | #define ixSMU_PM_STATUS_86 0x33f58 |
887 | #define ixSMU_PM_STATUS_87 0x33f5c |
888 | #define ixSMU_PM_STATUS_88 0x33f60 |
889 | #define ixSMU_PM_STATUS_89 0x33f64 |
890 | #define ixSMU_PM_STATUS_90 0x33f68 |
891 | #define ixSMU_PM_STATUS_91 0x33f6c |
892 | #define ixSMU_PM_STATUS_92 0x33f70 |
893 | #define ixSMU_PM_STATUS_93 0x33f74 |
894 | #define ixSMU_PM_STATUS_94 0x33f78 |
895 | #define ixSMU_PM_STATUS_95 0x33f7c |
896 | #define ixSMU_PM_STATUS_96 0x33f80 |
897 | #define ixSMU_PM_STATUS_97 0x33f84 |
898 | #define ixSMU_PM_STATUS_98 0x33f88 |
899 | #define ixSMU_PM_STATUS_99 0x33f8c |
900 | #define ixSMU_PM_STATUS_100 0x33f90 |
901 | #define ixSMU_PM_STATUS_101 0x33f94 |
902 | #define ixSMU_PM_STATUS_102 0x33f98 |
903 | #define ixSMU_PM_STATUS_103 0x33f9c |
904 | #define ixSMU_PM_STATUS_104 0x33fa0 |
905 | #define ixSMU_PM_STATUS_105 0x33fa4 |
906 | #define ixSMU_PM_STATUS_106 0x33fa8 |
907 | #define ixSMU_PM_STATUS_107 0x33fac |
908 | #define ixSMU_PM_STATUS_108 0x33fb0 |
909 | #define ixSMU_PM_STATUS_109 0x33fb4 |
910 | #define ixSMU_PM_STATUS_110 0x33fb8 |
911 | #define ixSMU_PM_STATUS_111 0x33fbc |
912 | #define ixSMU_PM_STATUS_112 0x33fc0 |
913 | #define ixSMU_PM_STATUS_113 0x33fc4 |
914 | #define ixSMU_PM_STATUS_114 0x33fc8 |
915 | #define ixSMU_PM_STATUS_115 0x33fcc |
916 | #define ixSMU_PM_STATUS_116 0x33fd0 |
917 | #define ixSMU_PM_STATUS_117 0x33fd4 |
918 | #define ixSMU_PM_STATUS_118 0x33fd8 |
919 | #define ixSMU_PM_STATUS_119 0x33fdc |
920 | #define ixSMU_PM_STATUS_120 0x33fe0 |
921 | #define ixSMU_PM_STATUS_121 0x33fe4 |
922 | #define ixSMU_PM_STATUS_122 0x33fe8 |
923 | #define ixSMU_PM_STATUS_123 0x33fec |
924 | #define ixSMU_PM_STATUS_124 0x33ff0 |
925 | #define ixSMU_PM_STATUS_125 0x33ff4 |
926 | #define ixSMU_PM_STATUS_126 0x33ff8 |
927 | #define ixSMU_PM_STATUS_127 0x33ffc |
928 | #define ixCG_THERMAL_INT_ENA 0xc2100024 |
929 | #define ixCG_THERMAL_INT_CTRL 0xc2100028 |
930 | #define ixCG_THERMAL_INT_STATUS 0xc210002c |
931 | #define ixCG_THERMAL_CTRL 0xc0300004 |
932 | #define ixCG_THERMAL_STATUS 0xc0300008 |
933 | #define ixCG_THERMAL_INT 0xc030000c |
934 | #define ixCG_MULT_THERMAL_CTRL 0xc0300010 |
935 | #define ixCG_MULT_THERMAL_STATUS 0xc0300014 |
936 | #define ixCG_FDO_CTRL0 0xc0300064 |
937 | #define ixCG_FDO_CTRL1 0xc0300068 |
938 | #define ixCG_FDO_CTRL2 0xc030006c |
939 | #define ixCG_TACH_CTRL 0xc0300070 |
940 | #define ixCG_TACH_STATUS 0xc0300074 |
941 | #define ixCC_THM_STRAPS0 0xc0300080 |
942 | #define ixTHM_TMON0_RDIL0_DATA 0xc0300100 |
943 | #define ixTHM_TMON0_RDIL1_DATA 0xc0300104 |
944 | #define ixTHM_TMON0_RDIL2_DATA 0xc0300108 |
945 | #define ixTHM_TMON0_RDIL3_DATA 0xc030010c |
946 | #define ixTHM_TMON0_RDIL4_DATA 0xc0300110 |
947 | #define ixTHM_TMON0_RDIL5_DATA 0xc0300114 |
948 | #define ixTHM_TMON0_RDIL6_DATA 0xc0300118 |
949 | #define ixTHM_TMON0_RDIL7_DATA 0xc030011c |
950 | #define ixTHM_TMON0_RDIL8_DATA 0xc0300120 |
951 | #define ixTHM_TMON0_RDIL9_DATA 0xc0300124 |
952 | #define ixTHM_TMON0_RDIL10_DATA 0xc0300128 |
953 | #define ixTHM_TMON0_RDIL11_DATA 0xc030012c |
954 | #define ixTHM_TMON0_RDIL12_DATA 0xc0300130 |
955 | #define ixTHM_TMON0_RDIL13_DATA 0xc0300134 |
956 | #define ixTHM_TMON0_RDIL14_DATA 0xc0300138 |
957 | #define ixTHM_TMON0_RDIL15_DATA 0xc030013c |
958 | #define ixTHM_TMON0_RDIR0_DATA 0xc0300140 |
959 | #define ixTHM_TMON0_RDIR1_DATA 0xc0300144 |
960 | #define ixTHM_TMON0_RDIR2_DATA 0xc0300148 |
961 | #define ixTHM_TMON0_RDIR3_DATA 0xc030014c |
962 | #define ixTHM_TMON0_RDIR4_DATA 0xc0300150 |
963 | #define ixTHM_TMON0_RDIR5_DATA 0xc0300154 |
964 | #define ixTHM_TMON0_RDIR6_DATA 0xc0300158 |
965 | #define ixTHM_TMON0_RDIR7_DATA 0xc030015c |
966 | #define ixTHM_TMON0_RDIR8_DATA 0xc0300160 |
967 | #define ixTHM_TMON0_RDIR9_DATA 0xc0300164 |
968 | #define ixTHM_TMON0_RDIR10_DATA 0xc0300168 |
969 | #define ixTHM_TMON0_RDIR11_DATA 0xc030016c |
970 | #define ixTHM_TMON0_RDIR12_DATA 0xc0300170 |
971 | #define ixTHM_TMON0_RDIR13_DATA 0xc0300174 |
972 | #define ixTHM_TMON0_RDIR14_DATA 0xc0300178 |
973 | #define ixTHM_TMON0_RDIR15_DATA 0xc030017c |
974 | #define ixTHM_TMON0_INT_DATA 0xc0300300 |
975 | #define ixTHM_TMON0_DEBUG 0xc0300310 |
976 | #define ixTHM_TMON0_STATUS 0xc0300320 |
977 | #define ixGENERAL_PWRMGT 0xc0200000 |
978 | #define ixCNB_PWRMGT_CNTL 0xc0200004 |
979 | #define ixSCLK_PWRMGT_CNTL 0xc0200008 |
980 | #define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 |
981 | #define ixPWR_PCC_CONTROL 0xc0200018 |
982 | #define ixPWR_PCC_GPIO_SELECT 0xc020001c |
983 | #define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 |
984 | #define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac |
985 | #define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 |
986 | #define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 |
987 | #define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 |
988 | #define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc |
989 | #define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 |
990 | #define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 |
991 | #define ixPLL_TEST_CNTL 0xc020003c |
992 | #define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 |
993 | #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 |
994 | #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 |
995 | #define ixCG_ACPI_CNTL 0xc0200064 |
996 | #define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 |
997 | #define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 |
998 | #define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c |
999 | #define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 |
1000 | #define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c |
1001 | #define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 |
1002 | #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 |
1003 | #define ixCG_ULV_PARAMETER 0xc020015c |
1004 | #define ixSCLK_MIN_DIV 0xc02003ac |
1005 | #define ixPWR_DISP_TIMER_0_CONTROL 0xc0200390 |
1006 | #define ixPWR_DISP_TIMER_1_CONTROL 0xc020037c |
1007 | #define ixPWR_DISP_TIMER_2_CONTROL 0xc02003d0 |
1008 | #define ixPWR_DISP_TIMER_3_CONTROL 0xc02003d4 |
1009 | #define ixPWR_DISP_TIMER_4_CONTROL 0xc02003d8 |
1010 | #define ixPWR_DISP_TIMER_5_CONTROL 0xc02003dc |
1011 | #define ixPWR_DISP_TIMER_6_CONTROL 0xc02003e0 |
1012 | #define ixPWR_DISP_TIMER_7_CONTROL 0xc02003e4 |
1013 | #define ixPWR_DISP_TIMER_8_CONTROL 0xc02003e8 |
1014 | #define ixPWR_DISP_TIMER_9_CONTROL 0xc02003ec |
1015 | #define ixPWR_DISP_TIMER_10_CONTROL 0xc02003f0 |
1016 | #define ixPWR_DISP_TIMER_11_CONTROL 0xc02003f4 |
1017 | #define ixPWR_DISP_TIMER_12_CONTROL 0xc02003f8 |
1018 | #define ixPWR_DISP_TIMER_13_CONTROL 0xc02003fc |
1019 | #define ixPWR_DISP_TIMER_14_CONTROL 0xc0200074 |
1020 | #define ixPWR_DISP_TIMER_15_CONTROL 0xc0200078 |
1021 | #define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 |
1022 | #define ixVDDGFX_IDLE_PARAMETER 0xc020036c |
1023 | #define ixVDDGFX_IDLE_CONTROL 0xc0200370 |
1024 | #define ixVDDGFX_IDLE_EXIT 0xc0200374 |
1025 | #define ixLCAC_MC0_CNTL 0xc0400130 |
1026 | #define ixLCAC_MC0_OVR_SEL 0xc0400134 |
1027 | #define ixLCAC_MC0_OVR_VAL 0xc0400138 |
1028 | #define ixLCAC_MC1_CNTL 0xc040013c |
1029 | #define ixLCAC_MC1_OVR_SEL 0xc0400140 |
1030 | #define ixLCAC_MC1_OVR_VAL 0xc0400144 |
1031 | #define ixLCAC_MC2_CNTL 0xc0400148 |
1032 | #define ixLCAC_MC2_OVR_SEL 0xc040014c |
1033 | #define ixLCAC_MC2_OVR_VAL 0xc0400150 |
1034 | #define ixLCAC_MC3_CNTL 0xc0400154 |
1035 | #define ixLCAC_MC3_OVR_SEL 0xc0400158 |
1036 | #define ixLCAC_MC3_OVR_VAL 0xc040015c |
1037 | #define ixLCAC_CPL_CNTL 0xc0400160 |
1038 | #define ixLCAC_CPL_OVR_SEL 0xc0400164 |
1039 | #define ixLCAC_CPL_OVR_VAL 0xc0400168 |
1040 | #define mmROM_SMC_IND_INDEX 0x80 |
1041 | #define mmROM0_ROM_SMC_IND_INDEX 0x80 |
1042 | #define mmROM1_ROM_SMC_IND_INDEX 0x82 |
1043 | #define mmROM2_ROM_SMC_IND_INDEX 0x84 |
1044 | #define mmROM3_ROM_SMC_IND_INDEX 0x86 |
1045 | #define mmROM_SMC_IND_DATA 0x81 |
1046 | #define mmROM0_ROM_SMC_IND_DATA 0x81 |
1047 | #define mmROM1_ROM_SMC_IND_DATA 0x83 |
1048 | #define mmROM2_ROM_SMC_IND_DATA 0x85 |
1049 | #define mmROM3_ROM_SMC_IND_DATA 0x87 |
1050 | #define ixROM_CNTL 0xc0600000 |
1051 | #define ixPAGE_MIRROR_CNTL 0xc0600004 |
1052 | #define ixROM_STATUS 0xc0600008 |
1053 | #define ixCGTT_ROM_CLK_CTRL0 0xc060000c |
1054 | #define ixROM_INDEX 0xc0600010 |
1055 | #define ixROM_DATA 0xc0600014 |
1056 | #define ixROM_START 0xc0600018 |
1057 | #define ixROM_SW_CNTL 0xc060001c |
1058 | #define ixROM_SW_STATUS 0xc0600020 |
1059 | #define ixROM_SW_COMMAND 0xc0600024 |
1060 | #define ixROM_SW_DATA_1 0xc0600028 |
1061 | #define ixROM_SW_DATA_2 0xc060002c |
1062 | #define ixROM_SW_DATA_3 0xc0600030 |
1063 | #define ixROM_SW_DATA_4 0xc0600034 |
1064 | #define ixROM_SW_DATA_5 0xc0600038 |
1065 | #define ixROM_SW_DATA_6 0xc060003c |
1066 | #define ixROM_SW_DATA_7 0xc0600040 |
1067 | #define ixROM_SW_DATA_8 0xc0600044 |
1068 | #define ixROM_SW_DATA_9 0xc0600048 |
1069 | #define ixROM_SW_DATA_10 0xc060004c |
1070 | #define ixROM_SW_DATA_11 0xc0600050 |
1071 | #define ixROM_SW_DATA_12 0xc0600054 |
1072 | #define ixROM_SW_DATA_13 0xc0600058 |
1073 | #define ixROM_SW_DATA_14 0xc060005c |
1074 | #define ixROM_SW_DATA_15 0xc0600060 |
1075 | #define ixROM_SW_DATA_16 0xc0600064 |
1076 | #define ixROM_SW_DATA_17 0xc0600068 |
1077 | #define ixROM_SW_DATA_18 0xc060006c |
1078 | #define ixROM_SW_DATA_19 0xc0600070 |
1079 | #define ixROM_SW_DATA_20 0xc0600074 |
1080 | #define ixROM_SW_DATA_21 0xc0600078 |
1081 | #define ixROM_SW_DATA_22 0xc060007c |
1082 | #define ixROM_SW_DATA_23 0xc0600080 |
1083 | #define ixROM_SW_DATA_24 0xc0600084 |
1084 | #define ixROM_SW_DATA_25 0xc0600088 |
1085 | #define ixROM_SW_DATA_26 0xc060008c |
1086 | #define ixROM_SW_DATA_27 0xc0600090 |
1087 | #define ixROM_SW_DATA_28 0xc0600094 |
1088 | #define ixROM_SW_DATA_29 0xc0600098 |
1089 | #define ixROM_SW_DATA_30 0xc060009c |
1090 | #define ixROM_SW_DATA_31 0xc06000a0 |
1091 | #define ixROM_SW_DATA_32 0xc06000a4 |
1092 | #define ixROM_SW_DATA_33 0xc06000a8 |
1093 | #define ixROM_SW_DATA_34 0xc06000ac |
1094 | #define ixROM_SW_DATA_35 0xc06000b0 |
1095 | #define ixROM_SW_DATA_36 0xc06000b4 |
1096 | #define ixROM_SW_DATA_37 0xc06000b8 |
1097 | #define ixROM_SW_DATA_38 0xc06000bc |
1098 | #define ixROM_SW_DATA_39 0xc06000c0 |
1099 | #define ixROM_SW_DATA_40 0xc06000c4 |
1100 | #define ixROM_SW_DATA_41 0xc06000c8 |
1101 | #define ixROM_SW_DATA_42 0xc06000cc |
1102 | #define ixROM_SW_DATA_43 0xc06000d0 |
1103 | #define ixROM_SW_DATA_44 0xc06000d4 |
1104 | #define ixROM_SW_DATA_45 0xc06000d8 |
1105 | #define ixROM_SW_DATA_46 0xc06000dc |
1106 | #define ixROM_SW_DATA_47 0xc06000e0 |
1107 | #define ixROM_SW_DATA_48 0xc06000e4 |
1108 | #define ixROM_SW_DATA_49 0xc06000e8 |
1109 | #define ixROM_SW_DATA_50 0xc06000ec |
1110 | #define ixROM_SW_DATA_51 0xc06000f0 |
1111 | #define ixROM_SW_DATA_52 0xc06000f4 |
1112 | #define ixROM_SW_DATA_53 0xc06000f8 |
1113 | #define ixROM_SW_DATA_54 0xc06000fc |
1114 | #define ixROM_SW_DATA_55 0xc0600100 |
1115 | #define ixROM_SW_DATA_56 0xc0600104 |
1116 | #define ixROM_SW_DATA_57 0xc0600108 |
1117 | #define ixROM_SW_DATA_58 0xc060010c |
1118 | #define ixROM_SW_DATA_59 0xc0600110 |
1119 | #define ixROM_SW_DATA_60 0xc0600114 |
1120 | #define ixROM_SW_DATA_61 0xc0600118 |
1121 | #define ixROM_SW_DATA_62 0xc060011c |
1122 | #define ixROM_SW_DATA_63 0xc0600120 |
1123 | #define ixROM_SW_DATA_64 0xc0600124 |
1124 | #define ixCURRENT_PG_STATUS 0xc020029c |
1125 | |
1126 | #endif /* SMU_7_1_1_D_H */ |
1127 | |