1/*
2 * SMU_7_1_3 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef SMU_7_1_3_D_H
25#define SMU_7_1_3_D_H
26
27#define mmGCK_SMC_IND_INDEX 0x80
28#define mmGCK0_GCK_SMC_IND_INDEX 0x80
29#define mmGCK1_GCK_SMC_IND_INDEX 0x82
30#define mmGCK2_GCK_SMC_IND_INDEX 0x84
31#define mmGCK3_GCK_SMC_IND_INDEX 0x86
32#define mmGCK_SMC_IND_DATA 0x81
33#define mmGCK0_GCK_SMC_IND_DATA 0x81
34#define mmGCK1_GCK_SMC_IND_DATA 0x83
35#define mmGCK2_GCK_SMC_IND_DATA 0x85
36#define mmGCK3_GCK_SMC_IND_DATA 0x87
37#define ixGCK_MCLK_FUSES 0xc0500008
38#define ixCG_DCLK_CNTL 0xc050009c
39#define ixCG_DCLK_STATUS 0xc05000a0
40#define ixCG_VCLK_CNTL 0xc05000a4
41#define ixCG_VCLK_STATUS 0xc05000a8
42#define ixCG_ECLK_CNTL 0xc05000ac
43#define ixCG_ECLK_STATUS 0xc05000b0
44#define ixCG_ACLK_CNTL 0xc05000dc
45#define ixCG_MCLK_CNTL 0xc0500120
46#define ixCG_MCLK_STATUS 0xc0500124
47#define ixGCK_DFS_BYPASS_CNTL 0xc0500118
48#define ixCG_SPLL_FUNC_CNTL 0xc0500140
49#define ixCG_SPLL_FUNC_CNTL_2 0xc0500144
50#define ixCG_SPLL_FUNC_CNTL_3 0xc0500148
51#define ixCG_SPLL_FUNC_CNTL_4 0xc050014c
52#define ixCG_SPLL_FUNC_CNTL_5 0xc0500150
53#define ixCG_SPLL_FUNC_CNTL_6 0xc0500154
54#define ixCG_SPLL_FUNC_CNTL_7 0xc0500158
55#define ixSPLL_CNTL_MODE 0xc0500160
56#define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164
57#define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168
58#define ixMPLL_BYPASSCLK_SEL 0xc050019c
59#define ixCG_CLKPIN_CNTL 0xc05001a0
60#define ixCG_CLKPIN_CNTL_2 0xc05001a4
61#define ixCG_CLKPIN_CNTL_DC 0xc0500204
62#define ixTHM_CLK_CNTL 0xc05001a8
63#define ixMISC_CLK_CTRL 0xc05001ac
64#define ixGCK_PLL_TEST_CNTL 0xc05001c0
65#define ixGCK_PLL_TEST_CNTL_2 0xc05001c4
66#define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8
67#define mmSMC_IND_INDEX 0x80
68#define mmSMC0_SMC_IND_INDEX 0x80
69#define mmSMC1_SMC_IND_INDEX 0x82
70#define mmSMC2_SMC_IND_INDEX 0x84
71#define mmSMC3_SMC_IND_INDEX 0x86
72#define mmSMC_IND_DATA 0x81
73#define mmSMC0_SMC_IND_DATA 0x81
74#define mmSMC1_SMC_IND_DATA 0x83
75#define mmSMC2_SMC_IND_DATA 0x85
76#define mmSMC3_SMC_IND_DATA 0x87
77#define mmSMC_IND_INDEX_0 0x80
78#define mmSMC_IND_DATA_0 0x81
79#define mmSMC_IND_INDEX_1 0x82
80#define mmSMC_IND_DATA_1 0x83
81#define mmSMC_IND_INDEX_2 0x84
82#define mmSMC_IND_DATA_2 0x85
83#define mmSMC_IND_INDEX_3 0x86
84#define mmSMC_IND_DATA_3 0x87
85#define mmSMC_IND_INDEX_4 0x88
86#define mmSMC_IND_DATA_4 0x89
87#define mmSMC_IND_INDEX_5 0x8a
88#define mmSMC_IND_DATA_5 0x8b
89#define mmSMC_IND_INDEX_6 0x8c
90#define mmSMC_IND_DATA_6 0x8d
91#define mmSMC_IND_INDEX_7 0x8e
92#define mmSMC_IND_DATA_7 0x8f
93#define mmSMC_IND_INDEX_11 0x1AC
94#define mmSMC_IND_DATA_11 0x1AD
95#define mmSMC_IND_ACCESS_CNTL 0x92
96#define mmSMC_MESSAGE_0 0x94
97#define mmSMC_RESP_0 0x95
98#define mmSMC_MESSAGE_1 0x96
99#define mmSMC_RESP_1 0x97
100#define mmSMC_MESSAGE_2 0x98
101#define mmSMC_RESP_2 0x99
102#define mmSMC_MESSAGE_3 0x9a
103#define mmSMC_RESP_3 0x9b
104#define mmSMC_MESSAGE_4 0x9c
105#define mmSMC_RESP_4 0x9d
106#define mmSMC_MESSAGE_5 0x9e
107#define mmSMC_RESP_5 0x9f
108#define mmSMC_MESSAGE_6 0xa0
109#define mmSMC_RESP_6 0xa1
110#define mmSMC_MESSAGE_7 0xa2
111#define mmSMC_RESP_7 0xa3
112#define mmSMC_MSG_ARG_0 0xa4
113#define mmSMC_MSG_ARG_1 0xa5
114#define mmSMC_MSG_ARG_2 0xa6
115#define mmSMC_MSG_ARG_3 0xa7
116#define mmSMC_MSG_ARG_4 0xa8
117#define mmSMC_MSG_ARG_5 0xa9
118#define mmSMC_MSG_ARG_6 0xaa
119#define mmSMC_MSG_ARG_7 0xab
120#define mmSMC_MESSAGE_8 0xb5
121#define mmSMC_RESP_8 0xb6
122#define mmSMC_MESSAGE_9 0xb7
123#define mmSMC_RESP_9 0xb8
124#define mmSMC_MESSAGE_10 0xb9
125#define mmSMC_RESP_10 0xba
126#define mmSMC_MESSAGE_11 0xbb
127#define mmSMC_RESP_11 0xbc
128#define mmSMC_MSG_ARG_8 0xbd
129#define mmSMC_MSG_ARG_9 0xbe
130#define mmSMC_MSG_ARG_10 0xbf
131#define mmSMC_MSG_ARG_11 0x93
132#define ixSMC_SYSCON_RESET_CNTL 0x80000000
133#define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004
134#define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008
135#define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c
136#define ixSMC_SYSCON_MISC_CNTL 0x80000010
137#define ixSMC_SYSCON_MSG_ARG_0 0x80000068
138#define ixSMC_PC_C 0x80000370
139#define ixSMC_SCRATCH9 0x80000424
140#define mmGPIOPAD_SW_INT_STAT 0x180
141#define mmGPIOPAD_STRENGTH 0x181
142#define mmGPIOPAD_MASK 0x182
143#define mmGPIOPAD_A 0x183
144#define mmGPIOPAD_EN 0x184
145#define mmGPIOPAD_Y 0x185
146#define mmGPIOPAD_PINSTRAPS 0x186
147#define mmGPIOPAD_INT_STAT_EN 0x187
148#define mmGPIOPAD_INT_STAT 0x188
149#define mmGPIOPAD_INT_STAT_AK 0x189
150#define mmGPIOPAD_INT_EN 0x18a
151#define mmGPIOPAD_INT_TYPE 0x18b
152#define mmGPIOPAD_INT_POLARITY 0x18c
153#define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d
154#define mmGPIOPAD_RCVR_SEL 0x191
155#define mmGPIOPAD_PU_EN 0x192
156#define mmGPIOPAD_PD_EN 0x193
157#define mmCG_FPS_CNT 0x1b6
158#define mmSMU_IND_INDEX_0 0x1a6
159#define mmSMU_IND_DATA_0 0x1a7
160#define mmSMU_IND_INDEX_1 0x1a8
161#define mmSMU_IND_DATA_1 0x1a9
162#define mmSMU_IND_INDEX_2 0x1aa
163#define mmSMU_IND_DATA_2 0x1ab
164#define mmSMU_IND_INDEX_3 0x1ac
165#define mmSMU_IND_DATA_3 0x1ad
166#define mmSMU_IND_INDEX_4 0x1ae
167#define mmSMU_IND_DATA_4 0x1af
168#define mmSMU_IND_INDEX_5 0x1b0
169#define mmSMU_IND_DATA_5 0x1b1
170#define mmSMU_IND_INDEX_6 0x1b2
171#define mmSMU_IND_DATA_6 0x1b3
172#define mmSMU_IND_INDEX_7 0x1b4
173#define mmSMU_IND_DATA_7 0x1b5
174#define mmSMU_SMC_IND_INDEX 0x80
175#define mmSMU0_SMU_SMC_IND_INDEX 0x80
176#define mmSMU1_SMU_SMC_IND_INDEX 0x82
177#define mmSMU2_SMU_SMC_IND_INDEX 0x84
178#define mmSMU3_SMU_SMC_IND_INDEX 0x86
179#define mmSMU_SMC_IND_DATA 0x81
180#define mmSMU0_SMU_SMC_IND_DATA 0x81
181#define mmSMU1_SMU_SMC_IND_DATA 0x83
182#define mmSMU2_SMU_SMC_IND_DATA 0x85
183#define mmSMU3_SMU_SMC_IND_DATA 0x87
184#define ixRCU_UC_EVENTS 0xc0000004
185#define ixRCU_MISC_CTRL 0xc0000010
186#define ixRCU_VIRT_RESET_REQ 0xc0000024
187#define ixCC_RCU_FUSES 0xc00c0000
188#define ixCC_SMU_MISC_FUSES 0xc00c0004
189#define ixCC_SCLK_VID_FUSES 0xc00c0008
190#define ixCC_GIO_IOCCFG_FUSES 0xc00c000c
191#define ixCC_GIO_IOC_FUSES 0xc00c0010
192#define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c
193#define ixCC_TST_ID_STRAPS 0xc00c0020
194#define ixCC_FCTRL_FUSES 0xc00c0024
195#define ixCC_HARVEST_FUSES 0xc00c0028
196#define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020
197#define ixSMU_STATUS 0xe0003088
198#define ixSMU_FIRMWARE 0xe00030a4
199#define ixSMU_INPUT_DATA 0xe00030b8
200#define ixSMU_EFUSE_0 0xc0100000
201#define ixFIRMWARE_FLAGS 0x3f000
202#define ixTDC_STATUS 0x3f004
203#define ixTDC_MV_AVERAGE 0x3f008
204#define ixTDC_VRM_LIMIT 0x3f00c
205#define ixFEATURE_STATUS 0x3f010
206#define ixENTITY_TEMPERATURES_1 0x3f014
207#define ixMCARB_DRAM_TIMING_TABLE_1 0x3f018
208#define ixMCARB_DRAM_TIMING_TABLE_2 0x3f01c
209#define ixMCARB_DRAM_TIMING_TABLE_3 0x3f020
210#define ixMCARB_DRAM_TIMING_TABLE_4 0x3f024
211#define ixMCARB_DRAM_TIMING_TABLE_5 0x3f028
212#define ixMCARB_DRAM_TIMING_TABLE_6 0x3f02c
213#define ixMCARB_DRAM_TIMING_TABLE_7 0x3f030
214#define ixMCARB_DRAM_TIMING_TABLE_8 0x3f034
215#define ixMCARB_DRAM_TIMING_TABLE_9 0x3f038
216#define ixMCARB_DRAM_TIMING_TABLE_10 0x3f03c
217#define ixMCARB_DRAM_TIMING_TABLE_11 0x3f040
218#define ixMCARB_DRAM_TIMING_TABLE_12 0x3f044
219#define ixMCARB_DRAM_TIMING_TABLE_13 0x3f048
220#define ixMCARB_DRAM_TIMING_TABLE_14 0x3f04c
221#define ixMCARB_DRAM_TIMING_TABLE_15 0x3f050
222#define ixMCARB_DRAM_TIMING_TABLE_16 0x3f054
223#define ixMCARB_DRAM_TIMING_TABLE_17 0x3f058
224#define ixMCARB_DRAM_TIMING_TABLE_18 0x3f05c
225#define ixMCARB_DRAM_TIMING_TABLE_19 0x3f060
226#define ixMCARB_DRAM_TIMING_TABLE_20 0x3f064
227#define ixMCARB_DRAM_TIMING_TABLE_21 0x3f068
228#define ixMCARB_DRAM_TIMING_TABLE_22 0x3f06c
229#define ixMCARB_DRAM_TIMING_TABLE_23 0x3f070
230#define ixMCARB_DRAM_TIMING_TABLE_24 0x3f074
231#define ixMCARB_DRAM_TIMING_TABLE_25 0x3f078
232#define ixMCARB_DRAM_TIMING_TABLE_26 0x3f07c
233#define ixMCARB_DRAM_TIMING_TABLE_27 0x3f080
234#define ixMCARB_DRAM_TIMING_TABLE_28 0x3f084
235#define ixMCARB_DRAM_TIMING_TABLE_29 0x3f088
236#define ixMCARB_DRAM_TIMING_TABLE_30 0x3f08c
237#define ixMCARB_DRAM_TIMING_TABLE_31 0x3f090
238#define ixMCARB_DRAM_TIMING_TABLE_32 0x3f094
239#define ixMCARB_DRAM_TIMING_TABLE_33 0x3f098
240#define ixMCARB_DRAM_TIMING_TABLE_34 0x3f09c
241#define ixMCARB_DRAM_TIMING_TABLE_35 0x3f0a0
242#define ixMCARB_DRAM_TIMING_TABLE_36 0x3f0a4
243#define ixMCARB_DRAM_TIMING_TABLE_37 0x3f0a8
244#define ixMCARB_DRAM_TIMING_TABLE_38 0x3f0ac
245#define ixMCARB_DRAM_TIMING_TABLE_39 0x3f0b0
246#define ixMCARB_DRAM_TIMING_TABLE_40 0x3f0b4
247#define ixMCARB_DRAM_TIMING_TABLE_41 0x3f0b8
248#define ixMCARB_DRAM_TIMING_TABLE_42 0x3f0bc
249#define ixMCARB_DRAM_TIMING_TABLE_43 0x3f0c0
250#define ixMCARB_DRAM_TIMING_TABLE_44 0x3f0c4
251#define ixMCARB_DRAM_TIMING_TABLE_45 0x3f0c8
252#define ixMCARB_DRAM_TIMING_TABLE_46 0x3f0cc
253#define ixMCARB_DRAM_TIMING_TABLE_47 0x3f0d0
254#define ixMCARB_DRAM_TIMING_TABLE_48 0x3f0d4
255#define ixMCARB_DRAM_TIMING_TABLE_49 0x3f0d8
256#define ixMCARB_DRAM_TIMING_TABLE_50 0x3f0dc
257#define ixMCARB_DRAM_TIMING_TABLE_51 0x3f0e0
258#define ixMCARB_DRAM_TIMING_TABLE_52 0x3f0e4
259#define ixMCARB_DRAM_TIMING_TABLE_53 0x3f0e8
260#define ixMCARB_DRAM_TIMING_TABLE_54 0x3f0ec
261#define ixMCARB_DRAM_TIMING_TABLE_55 0x3f0f0
262#define ixMCARB_DRAM_TIMING_TABLE_56 0x3f0f4
263#define ixMCARB_DRAM_TIMING_TABLE_57 0x3f0f8
264#define ixMCARB_DRAM_TIMING_TABLE_58 0x3f0fc
265#define ixMCARB_DRAM_TIMING_TABLE_59 0x3f100
266#define ixMCARB_DRAM_TIMING_TABLE_60 0x3f104
267#define ixMCARB_DRAM_TIMING_TABLE_61 0x3f108
268#define ixMCARB_DRAM_TIMING_TABLE_62 0x3f10c
269#define ixMCARB_DRAM_TIMING_TABLE_63 0x3f110
270#define ixMCARB_DRAM_TIMING_TABLE_64 0x3f114
271#define ixMCARB_DRAM_TIMING_TABLE_65 0x3f118
272#define ixMCARB_DRAM_TIMING_TABLE_66 0x3f11c
273#define ixMCARB_DRAM_TIMING_TABLE_67 0x3f120
274#define ixMCARB_DRAM_TIMING_TABLE_68 0x3f124
275#define ixMCARB_DRAM_TIMING_TABLE_69 0x3f128
276#define ixMCARB_DRAM_TIMING_TABLE_70 0x3f12c
277#define ixMCARB_DRAM_TIMING_TABLE_71 0x3f130
278#define ixMCARB_DRAM_TIMING_TABLE_72 0x3f134
279#define ixMCARB_DRAM_TIMING_TABLE_73 0x3f138
280#define ixMCARB_DRAM_TIMING_TABLE_74 0x3f13c
281#define ixMCARB_DRAM_TIMING_TABLE_75 0x3f140
282#define ixMCARB_DRAM_TIMING_TABLE_76 0x3f144
283#define ixMCARB_DRAM_TIMING_TABLE_77 0x3f148
284#define ixMCARB_DRAM_TIMING_TABLE_78 0x3f14c
285#define ixMCARB_DRAM_TIMING_TABLE_79 0x3f150
286#define ixMCARB_DRAM_TIMING_TABLE_80 0x3f154
287#define ixMCARB_DRAM_TIMING_TABLE_81 0x3f158
288#define ixMCARB_DRAM_TIMING_TABLE_82 0x3f15c
289#define ixMCARB_DRAM_TIMING_TABLE_83 0x3f160
290#define ixMCARB_DRAM_TIMING_TABLE_84 0x3f164
291#define ixMCARB_DRAM_TIMING_TABLE_85 0x3f168
292#define ixMCARB_DRAM_TIMING_TABLE_86 0x3f16c
293#define ixMCARB_DRAM_TIMING_TABLE_87 0x3f170
294#define ixMCARB_DRAM_TIMING_TABLE_88 0x3f174
295#define ixMCARB_DRAM_TIMING_TABLE_89 0x3f178
296#define ixMCARB_DRAM_TIMING_TABLE_90 0x3f17c
297#define ixMCARB_DRAM_TIMING_TABLE_91 0x3f180
298#define ixMCARB_DRAM_TIMING_TABLE_92 0x3f184
299#define ixMCARB_DRAM_TIMING_TABLE_93 0x3f188
300#define ixMCARB_DRAM_TIMING_TABLE_94 0x3f18c
301#define ixMCARB_DRAM_TIMING_TABLE_95 0x3f190
302#define ixMCARB_DRAM_TIMING_TABLE_96 0x3f194
303#define ixDPM_TABLE_1 0x3f198
304#define ixDPM_TABLE_2 0x3f19c
305#define ixDPM_TABLE_3 0x3f1a0
306#define ixDPM_TABLE_4 0x3f1a4
307#define ixDPM_TABLE_5 0x3f1a8
308#define ixDPM_TABLE_6 0x3f1ac
309#define ixDPM_TABLE_7 0x3f1b0
310#define ixDPM_TABLE_8 0x3f1b4
311#define ixDPM_TABLE_9 0x3f1b8
312#define ixDPM_TABLE_10 0x3f1bc
313#define ixDPM_TABLE_11 0x3f1c0
314#define ixDPM_TABLE_12 0x3f1c4
315#define ixDPM_TABLE_13 0x3f1c8
316#define ixDPM_TABLE_14 0x3f1cc
317#define ixDPM_TABLE_15 0x3f1d0
318#define ixDPM_TABLE_16 0x3f1d4
319#define ixDPM_TABLE_17 0x3f1d8
320#define ixDPM_TABLE_18 0x3f1dc
321#define ixDPM_TABLE_19 0x3f1e0
322#define ixDPM_TABLE_20 0x3f1e4
323#define ixDPM_TABLE_21 0x3f1e8
324#define ixDPM_TABLE_22 0x3f1ec
325#define ixDPM_TABLE_23 0x3f1f0
326#define ixDPM_TABLE_24 0x3f1f4
327#define ixDPM_TABLE_25 0x3f1f8
328#define ixDPM_TABLE_26 0x3f1fc
329#define ixDPM_TABLE_27 0x3f200
330#define ixDPM_TABLE_28 0x3f204
331#define ixDPM_TABLE_29 0x3f208
332#define ixDPM_TABLE_30 0x3f20c
333#define ixDPM_TABLE_31 0x3f210
334#define ixDPM_TABLE_32 0x3f214
335#define ixDPM_TABLE_33 0x3f218
336#define ixDPM_TABLE_34 0x3f21c
337#define ixDPM_TABLE_35 0x3f220
338#define ixDPM_TABLE_36 0x3f224
339#define ixDPM_TABLE_37 0x3f228
340#define ixDPM_TABLE_38 0x3f22c
341#define ixDPM_TABLE_39 0x3f230
342#define ixDPM_TABLE_40 0x3f234
343#define ixDPM_TABLE_41 0x3f238
344#define ixDPM_TABLE_42 0x3f23c
345#define ixDPM_TABLE_43 0x3f240
346#define ixDPM_TABLE_44 0x3f244
347#define ixDPM_TABLE_45 0x3f248
348#define ixDPM_TABLE_46 0x3f24c
349#define ixDPM_TABLE_47 0x3f250
350#define ixDPM_TABLE_48 0x3f254
351#define ixDPM_TABLE_49 0x3f258
352#define ixDPM_TABLE_50 0x3f25c
353#define ixDPM_TABLE_51 0x3f260
354#define ixDPM_TABLE_52 0x3f264
355#define ixDPM_TABLE_53 0x3f268
356#define ixDPM_TABLE_54 0x3f26c
357#define ixDPM_TABLE_55 0x3f270
358#define ixDPM_TABLE_56 0x3f274
359#define ixDPM_TABLE_57 0x3f278
360#define ixDPM_TABLE_58 0x3f27c
361#define ixDPM_TABLE_59 0x3f280
362#define ixDPM_TABLE_60 0x3f284
363#define ixDPM_TABLE_61 0x3f288
364#define ixDPM_TABLE_62 0x3f28c
365#define ixDPM_TABLE_63 0x3f290
366#define ixDPM_TABLE_64 0x3f294
367#define ixDPM_TABLE_65 0x3f298
368#define ixDPM_TABLE_66 0x3f29c
369#define ixDPM_TABLE_67 0x3f2a0
370#define ixDPM_TABLE_68 0x3f2a4
371#define ixDPM_TABLE_69 0x3f2a8
372#define ixDPM_TABLE_70 0x3f2ac
373#define ixDPM_TABLE_71 0x3f2b0
374#define ixDPM_TABLE_72 0x3f2b4
375#define ixDPM_TABLE_73 0x3f2b8
376#define ixDPM_TABLE_74 0x3f2bc
377#define ixDPM_TABLE_75 0x3f2c0
378#define ixDPM_TABLE_76 0x3f2c4
379#define ixDPM_TABLE_77 0x3f2c8
380#define ixDPM_TABLE_78 0x3f2cc
381#define ixDPM_TABLE_79 0x3f2d0
382#define ixDPM_TABLE_80 0x3f2d4
383#define ixDPM_TABLE_81 0x3f2d8
384#define ixDPM_TABLE_82 0x3f2dc
385#define ixDPM_TABLE_83 0x3f2e0
386#define ixDPM_TABLE_84 0x3f2e4
387#define ixDPM_TABLE_85 0x3f2e8
388#define ixDPM_TABLE_86 0x3f2ec
389#define ixDPM_TABLE_87 0x3f2f0
390#define ixDPM_TABLE_88 0x3f2f4
391#define ixDPM_TABLE_89 0x3f2f8
392#define ixDPM_TABLE_90 0x3f2fc
393#define ixDPM_TABLE_91 0x3f300
394#define ixDPM_TABLE_92 0x3f304
395#define ixDPM_TABLE_93 0x3f308
396#define ixDPM_TABLE_94 0x3f30c
397#define ixDPM_TABLE_95 0x3f310
398#define ixDPM_TABLE_96 0x3f314
399#define ixDPM_TABLE_97 0x3f318
400#define ixDPM_TABLE_98 0x3f31c
401#define ixDPM_TABLE_99 0x3f320
402#define ixDPM_TABLE_100 0x3f324
403#define ixDPM_TABLE_101 0x3f328
404#define ixDPM_TABLE_102 0x3f32c
405#define ixDPM_TABLE_103 0x3f330
406#define ixDPM_TABLE_104 0x3f334
407#define ixDPM_TABLE_105 0x3f338
408#define ixDPM_TABLE_106 0x3f33c
409#define ixDPM_TABLE_107 0x3f340
410#define ixDPM_TABLE_108 0x3f344
411#define ixDPM_TABLE_109 0x3f348
412#define ixDPM_TABLE_110 0x3f34c
413#define ixDPM_TABLE_111 0x3f350
414#define ixDPM_TABLE_112 0x3f354
415#define ixDPM_TABLE_113 0x3f358
416#define ixDPM_TABLE_114 0x3f35c
417#define ixDPM_TABLE_115 0x3f360
418#define ixDPM_TABLE_116 0x3f364
419#define ixDPM_TABLE_117 0x3f368
420#define ixDPM_TABLE_118 0x3f36c
421#define ixDPM_TABLE_119 0x3f370
422#define ixDPM_TABLE_120 0x3f374
423#define ixDPM_TABLE_121 0x3f378
424#define ixDPM_TABLE_122 0x3f37c
425#define ixDPM_TABLE_123 0x3f380
426#define ixDPM_TABLE_124 0x3f384
427#define ixDPM_TABLE_125 0x3f388
428#define ixDPM_TABLE_126 0x3f38c
429#define ixDPM_TABLE_127 0x3f390
430#define ixDPM_TABLE_128 0x3f394
431#define ixDPM_TABLE_129 0x3f398
432#define ixDPM_TABLE_130 0x3f39c
433#define ixDPM_TABLE_131 0x3f3a0
434#define ixDPM_TABLE_132 0x3f3a4
435#define ixDPM_TABLE_133 0x3f3a8
436#define ixDPM_TABLE_134 0x3f3ac
437#define ixDPM_TABLE_135 0x3f3b0
438#define ixDPM_TABLE_136 0x3f3b4
439#define ixDPM_TABLE_137 0x3f3b8
440#define ixDPM_TABLE_138 0x3f3bc
441#define ixDPM_TABLE_139 0x3f3c0
442#define ixDPM_TABLE_140 0x3f3c4
443#define ixDPM_TABLE_141 0x3f3c8
444#define ixDPM_TABLE_142 0x3f3cc
445#define ixDPM_TABLE_143 0x3f3d0
446#define ixDPM_TABLE_144 0x3f3d4
447#define ixDPM_TABLE_145 0x3f3d8
448#define ixDPM_TABLE_146 0x3f3dc
449#define ixDPM_TABLE_147 0x3f3e0
450#define ixDPM_TABLE_148 0x3f3e4
451#define ixDPM_TABLE_149 0x3f3e8
452#define ixDPM_TABLE_150 0x3f3ec
453#define ixDPM_TABLE_151 0x3f3f0
454#define ixDPM_TABLE_152 0x3f3f4
455#define ixDPM_TABLE_153 0x3f3f8
456#define ixDPM_TABLE_154 0x3f3fc
457#define ixDPM_TABLE_155 0x3f400
458#define ixDPM_TABLE_156 0x3f404
459#define ixDPM_TABLE_157 0x3f408
460#define ixDPM_TABLE_158 0x3f40c
461#define ixDPM_TABLE_159 0x3f410
462#define ixDPM_TABLE_160 0x3f414
463#define ixDPM_TABLE_161 0x3f418
464#define ixDPM_TABLE_162 0x3f41c
465#define ixDPM_TABLE_163 0x3f420
466#define ixDPM_TABLE_164 0x3f424
467#define ixDPM_TABLE_165 0x3f428
468#define ixDPM_TABLE_166 0x3f42c
469#define ixDPM_TABLE_167 0x3f430
470#define ixDPM_TABLE_168 0x3f434
471#define ixDPM_TABLE_169 0x3f438
472#define ixDPM_TABLE_170 0x3f43c
473#define ixDPM_TABLE_171 0x3f440
474#define ixDPM_TABLE_172 0x3f444
475#define ixDPM_TABLE_173 0x3f448
476#define ixDPM_TABLE_174 0x3f44c
477#define ixDPM_TABLE_175 0x3f450
478#define ixDPM_TABLE_176 0x3f454
479#define ixDPM_TABLE_177 0x3f458
480#define ixDPM_TABLE_178 0x3f45c
481#define ixDPM_TABLE_179 0x3f460
482#define ixDPM_TABLE_180 0x3f464
483#define ixDPM_TABLE_181 0x3f468
484#define ixDPM_TABLE_182 0x3f46c
485#define ixDPM_TABLE_183 0x3f470
486#define ixDPM_TABLE_184 0x3f474
487#define ixDPM_TABLE_185 0x3f478
488#define ixDPM_TABLE_186 0x3f47c
489#define ixDPM_TABLE_187 0x3f480
490#define ixDPM_TABLE_188 0x3f484
491#define ixDPM_TABLE_189 0x3f488
492#define ixDPM_TABLE_190 0x3f48c
493#define ixDPM_TABLE_191 0x3f490
494#define ixDPM_TABLE_192 0x3f494
495#define ixDPM_TABLE_193 0x3f498
496#define ixDPM_TABLE_194 0x3f49c
497#define ixDPM_TABLE_195 0x3f4a0
498#define ixDPM_TABLE_196 0x3f4a4
499#define ixDPM_TABLE_197 0x3f4a8
500#define ixDPM_TABLE_198 0x3f4ac
501#define ixDPM_TABLE_199 0x3f4b0
502#define ixDPM_TABLE_200 0x3f4b4
503#define ixDPM_TABLE_201 0x3f4b8
504#define ixDPM_TABLE_202 0x3f4bc
505#define ixDPM_TABLE_203 0x3f4c0
506#define ixDPM_TABLE_204 0x3f4c4
507#define ixDPM_TABLE_205 0x3f4c8
508#define ixDPM_TABLE_206 0x3f4cc
509#define ixDPM_TABLE_207 0x3f4d0
510#define ixDPM_TABLE_208 0x3f4d4
511#define ixDPM_TABLE_209 0x3f4d8
512#define ixDPM_TABLE_210 0x3f4dc
513#define ixDPM_TABLE_211 0x3f4e0
514#define ixDPM_TABLE_212 0x3f4e4
515#define ixDPM_TABLE_213 0x3f4e8
516#define ixDPM_TABLE_214 0x3f4ec
517#define ixDPM_TABLE_215 0x3f4f0
518#define ixDPM_TABLE_216 0x3f4f4
519#define ixDPM_TABLE_217 0x3f4f8
520#define ixDPM_TABLE_218 0x3f4fc
521#define ixDPM_TABLE_219 0x3f500
522#define ixDPM_TABLE_220 0x3f504
523#define ixDPM_TABLE_221 0x3f508
524#define ixDPM_TABLE_222 0x3f50c
525#define ixDPM_TABLE_223 0x3f510
526#define ixDPM_TABLE_224 0x3f514
527#define ixDPM_TABLE_225 0x3f518
528#define ixDPM_TABLE_226 0x3f51c
529#define ixDPM_TABLE_227 0x3f520
530#define ixDPM_TABLE_228 0x3f524
531#define ixDPM_TABLE_229 0x3f528
532#define ixDPM_TABLE_230 0x3f52c
533#define ixDPM_TABLE_231 0x3f530
534#define ixDPM_TABLE_232 0x3f534
535#define ixDPM_TABLE_233 0x3f538
536#define ixDPM_TABLE_234 0x3f53c
537#define ixDPM_TABLE_235 0x3f540
538#define ixDPM_TABLE_236 0x3f544
539#define ixDPM_TABLE_237 0x3f548
540#define ixDPM_TABLE_238 0x3f54c
541#define ixDPM_TABLE_239 0x3f550
542#define ixDPM_TABLE_240 0x3f554
543#define ixDPM_TABLE_241 0x3f558
544#define ixDPM_TABLE_242 0x3f55c
545#define ixDPM_TABLE_243 0x3f560
546#define ixDPM_TABLE_244 0x3f564
547#define ixDPM_TABLE_245 0x3f568
548#define ixDPM_TABLE_246 0x3f56c
549#define ixDPM_TABLE_247 0x3f570
550#define ixDPM_TABLE_248 0x3f574
551#define ixDPM_TABLE_249 0x3f578
552#define ixDPM_TABLE_250 0x3f57c
553#define ixDPM_TABLE_251 0x3f580
554#define ixDPM_TABLE_252 0x3f584
555#define ixDPM_TABLE_253 0x3f588
556#define ixDPM_TABLE_254 0x3f58c
557#define ixDPM_TABLE_255 0x3f590
558#define ixDPM_TABLE_256 0x3f594
559#define ixDPM_TABLE_257 0x3f598
560#define ixDPM_TABLE_258 0x3f59c
561#define ixDPM_TABLE_259 0x3f5a0
562#define ixDPM_TABLE_260 0x3f5a4
563#define ixDPM_TABLE_261 0x3f5a8
564#define ixDPM_TABLE_262 0x3f5ac
565#define ixDPM_TABLE_263 0x3f5b0
566#define ixDPM_TABLE_264 0x3f5b4
567#define ixDPM_TABLE_265 0x3f5b8
568#define ixDPM_TABLE_266 0x3f5bc
569#define ixDPM_TABLE_267 0x3f5c0
570#define ixDPM_TABLE_268 0x3f5c4
571#define ixDPM_TABLE_269 0x3f5c8
572#define ixDPM_TABLE_270 0x3f5cc
573#define ixDPM_TABLE_271 0x3f5d0
574#define ixDPM_TABLE_272 0x3f5d4
575#define ixDPM_TABLE_273 0x3f5d8
576#define ixDPM_TABLE_274 0x3f5dc
577#define ixDPM_TABLE_275 0x3f5e0
578#define ixDPM_TABLE_276 0x3f5e4
579#define ixDPM_TABLE_277 0x3f5e8
580#define ixDPM_TABLE_278 0x3f5ec
581#define ixDPM_TABLE_279 0x3f5f0
582#define ixDPM_TABLE_280 0x3f5f4
583#define ixDPM_TABLE_281 0x3f5f8
584#define ixDPM_TABLE_282 0x3f5fc
585#define ixDPM_TABLE_283 0x3f600
586#define ixDPM_TABLE_284 0x3f604
587#define ixDPM_TABLE_285 0x3f608
588#define ixDPM_TABLE_286 0x3f60c
589#define ixDPM_TABLE_287 0x3f610
590#define ixDPM_TABLE_288 0x3f614
591#define ixDPM_TABLE_289 0x3f618
592#define ixDPM_TABLE_290 0x3f61c
593#define ixDPM_TABLE_291 0x3f620
594#define ixDPM_TABLE_292 0x3f624
595#define ixDPM_TABLE_293 0x3f628
596#define ixDPM_TABLE_294 0x3f62c
597#define ixDPM_TABLE_295 0x3f630
598#define ixDPM_TABLE_296 0x3f634
599#define ixDPM_TABLE_297 0x3f638
600#define ixDPM_TABLE_298 0x3f63c
601#define ixDPM_TABLE_299 0x3f640
602#define ixDPM_TABLE_300 0x3f644
603#define ixDPM_TABLE_301 0x3f648
604#define ixDPM_TABLE_302 0x3f64c
605#define ixDPM_TABLE_303 0x3f650
606#define ixDPM_TABLE_304 0x3f654
607#define ixDPM_TABLE_305 0x3f658
608#define ixDPM_TABLE_306 0x3f65c
609#define ixDPM_TABLE_307 0x3f660
610#define ixDPM_TABLE_308 0x3f664
611#define ixDPM_TABLE_309 0x3f668
612#define ixDPM_TABLE_310 0x3f66c
613#define ixDPM_TABLE_311 0x3f670
614#define ixDPM_TABLE_312 0x3f674
615#define ixDPM_TABLE_313 0x3f678
616#define ixDPM_TABLE_314 0x3f67c
617#define ixDPM_TABLE_315 0x3f680
618#define ixDPM_TABLE_316 0x3f684
619#define ixDPM_TABLE_317 0x3f688
620#define ixDPM_TABLE_318 0x3f68c
621#define ixDPM_TABLE_319 0x3f690
622#define ixDPM_TABLE_320 0x3f694
623#define ixDPM_TABLE_321 0x3f698
624#define ixDPM_TABLE_322 0x3f69c
625#define ixDPM_TABLE_323 0x3f6a0
626#define ixDPM_TABLE_324 0x3f6a4
627#define ixDPM_TABLE_325 0x3f6a8
628#define ixDPM_TABLE_326 0x3f6ac
629#define ixDPM_TABLE_327 0x3f6b0
630#define ixDPM_TABLE_328 0x3f6b4
631#define ixDPM_TABLE_329 0x3f6b8
632#define ixDPM_TABLE_330 0x3f6bc
633#define ixDPM_TABLE_331 0x3f6c0
634#define ixDPM_TABLE_332 0x3f6c4
635#define ixDPM_TABLE_333 0x3f6c8
636#define ixDPM_TABLE_334 0x3f6cc
637#define ixDPM_TABLE_335 0x3f6d0
638#define ixDPM_TABLE_336 0x3f6d4
639#define ixDPM_TABLE_337 0x3f6d8
640#define ixDPM_TABLE_338 0x3f6dc
641#define ixDPM_TABLE_339 0x3f6e0
642#define ixDPM_TABLE_340 0x3f6e4
643#define ixDPM_TABLE_341 0x3f6e8
644#define ixDPM_TABLE_342 0x3f6ec
645#define ixDPM_TABLE_343 0x3f6f0
646#define ixDPM_TABLE_344 0x3f6f4
647#define ixDPM_TABLE_345 0x3f6f8
648#define ixDPM_TABLE_346 0x3f6fc
649#define ixDPM_TABLE_347 0x3f700
650#define ixDPM_TABLE_348 0x3f704
651#define ixDPM_TABLE_349 0x3f708
652#define ixDPM_TABLE_350 0x3f70c
653#define ixDPM_TABLE_351 0x3f710
654#define ixDPM_TABLE_352 0x3f714
655#define ixDPM_TABLE_353 0x3f718
656#define ixDPM_TABLE_354 0x3f71c
657#define ixDPM_TABLE_355 0x3f720
658#define ixDPM_TABLE_356 0x3f724
659#define ixDPM_TABLE_357 0x3f728
660#define ixDPM_TABLE_358 0x3f72c
661#define ixDPM_TABLE_359 0x3f730
662#define ixDPM_TABLE_360 0x3f734
663#define ixDPM_TABLE_361 0x3f738
664#define ixDPM_TABLE_362 0x3f73c
665#define ixDPM_TABLE_363 0x3f740
666#define ixDPM_TABLE_364 0x3f744
667#define ixDPM_TABLE_365 0x3f748
668#define ixDPM_TABLE_366 0x3f74c
669#define ixDPM_TABLE_367 0x3f750
670#define ixDPM_TABLE_368 0x3f754
671#define ixDPM_TABLE_369 0x3f758
672#define ixDPM_TABLE_370 0x3f75c
673#define ixDPM_TABLE_371 0x3f760
674#define ixDPM_TABLE_372 0x3f764
675#define ixDPM_TABLE_373 0x3f768
676#define ixDPM_TABLE_374 0x3f76c
677#define ixDPM_TABLE_375 0x3f770
678#define ixDPM_TABLE_376 0x3f774
679#define ixDPM_TABLE_377 0x3f778
680#define ixDPM_TABLE_378 0x3f77c
681#define ixDPM_TABLE_379 0x3f780
682#define ixDPM_TABLE_380 0x3f784
683#define ixDPM_TABLE_381 0x3f788
684#define ixDPM_TABLE_382 0x3f78c
685#define ixDPM_TABLE_383 0x3f790
686#define ixDPM_TABLE_384 0x3f794
687#define ixDPM_TABLE_385 0x3f798
688#define ixDPM_TABLE_386 0x3f79c
689#define ixDPM_TABLE_387 0x3f7a0
690#define ixDPM_TABLE_388 0x3f7a4
691#define ixDPM_TABLE_389 0x3f7a8
692#define ixDPM_TABLE_390 0x3f7ac
693#define ixDPM_TABLE_391 0x3f7b0
694#define ixDPM_TABLE_392 0x3f7b4
695#define ixDPM_TABLE_393 0x3f7b8
696#define ixDPM_TABLE_394 0x3f7bc
697#define ixDPM_TABLE_395 0x3f7c0
698#define ixDPM_TABLE_396 0x3f7c4
699#define ixDPM_TABLE_397 0x3f7c8
700#define ixDPM_TABLE_398 0x3f7cc
701#define ixDPM_TABLE_399 0x3f7d0
702#define ixDPM_TABLE_400 0x3f7d4
703#define ixDPM_TABLE_401 0x3f7d8
704#define ixDPM_TABLE_402 0x3f7dc
705#define ixDPM_TABLE_403 0x3f7e0
706#define ixDPM_TABLE_404 0x3f7e4
707#define ixDPM_TABLE_405 0x3f7e8
708#define ixDPM_TABLE_406 0x3f7ec
709#define ixDPM_TABLE_407 0x3f7f0
710#define ixDPM_TABLE_408 0x3f7f4
711#define ixDPM_TABLE_409 0x3f7f8
712#define ixDPM_TABLE_410 0x3f7fc
713#define ixDPM_TABLE_411 0x3f800
714#define ixDPM_TABLE_412 0x3f804
715#define ixDPM_TABLE_413 0x3f808
716#define ixDPM_TABLE_414 0x3f80c
717#define ixDPM_TABLE_415 0x3f810
718#define ixDPM_TABLE_416 0x3f814
719#define ixDPM_TABLE_417 0x3f818
720#define ixDPM_TABLE_418 0x3f81c
721#define ixDPM_TABLE_419 0x3f820
722#define ixDPM_TABLE_420 0x3f824
723#define ixDPM_TABLE_421 0x3f828
724#define ixDPM_TABLE_422 0x3f82c
725#define ixDPM_TABLE_423 0x3f830
726#define ixDPM_TABLE_424 0x3f834
727#define ixDPM_TABLE_425 0x3f838
728#define ixDPM_TABLE_426 0x3f83c
729#define ixDPM_TABLE_427 0x3f840
730#define ixDPM_TABLE_428 0x3f844
731#define ixDPM_TABLE_429 0x3f848
732#define ixDPM_TABLE_430 0x3f84c
733#define ixDPM_TABLE_431 0x3f850
734#define ixDPM_TABLE_432 0x3f854
735#define ixDPM_TABLE_433 0x3f858
736#define ixDPM_TABLE_434 0x3f85c
737#define ixDPM_TABLE_435 0x3f860
738#define ixDPM_TABLE_436 0x3f864
739#define ixDPM_TABLE_437 0x3f868
740#define ixDPM_TABLE_438 0x3f86c
741#define ixDPM_TABLE_439 0x3f870
742#define ixDPM_TABLE_440 0x3f874
743#define ixSOFT_REGISTERS_TABLE_1 0x3f89c
744#define ixSOFT_REGISTERS_TABLE_2 0x3f8a0
745#define ixSOFT_REGISTERS_TABLE_3 0x3f8a4
746#define ixSOFT_REGISTERS_TABLE_4 0x3f8a8
747#define ixSOFT_REGISTERS_TABLE_5 0x3f8ac
748#define ixSOFT_REGISTERS_TABLE_6 0x3f8b0
749#define ixSOFT_REGISTERS_TABLE_7 0x3f8b4
750#define ixSOFT_REGISTERS_TABLE_8 0x3f8b8
751#define ixSOFT_REGISTERS_TABLE_9 0x3f8bc
752#define ixSOFT_REGISTERS_TABLE_10 0x3f8c0
753#define ixSOFT_REGISTERS_TABLE_11 0x3f8c4
754#define ixSOFT_REGISTERS_TABLE_12 0x3f8c8
755#define ixSOFT_REGISTERS_TABLE_13 0x3f8cc
756#define ixSOFT_REGISTERS_TABLE_14 0x3f8d0
757#define ixSOFT_REGISTERS_TABLE_15 0x3f8d4
758#define ixSOFT_REGISTERS_TABLE_16 0x3f8d8
759#define ixSOFT_REGISTERS_TABLE_17 0x3f8dc
760#define ixSOFT_REGISTERS_TABLE_18 0x3f8e0
761#define ixSOFT_REGISTERS_TABLE_19 0x3f8e4
762#define ixSOFT_REGISTERS_TABLE_20 0x3f8e8
763#define ixSOFT_REGISTERS_TABLE_21 0x3f8ec
764#define ixSOFT_REGISTERS_TABLE_22 0x3f8f0
765#define ixSOFT_REGISTERS_TABLE_23 0x3f8f4
766#define ixSOFT_REGISTERS_TABLE_24 0x3f8f8
767#define ixSOFT_REGISTERS_TABLE_25 0x3f8fc
768#define ixSOFT_REGISTERS_TABLE_26 0x3f900
769#define ixSOFT_REGISTERS_TABLE_27 0x3f904
770#define ixSOFT_REGISTERS_TABLE_28 0x3f888
771#define ixSOFT_REGISTERS_TABLE_29 0x3f90c
772#define ixSOFT_REGISTERS_TABLE_30 0x3f910
773#define ixPM_FUSES_1 0x3f914
774#define ixPM_FUSES_2 0x3f918
775#define ixPM_FUSES_3 0x3f91c
776#define ixPM_FUSES_4 0x3f920
777#define ixPM_FUSES_5 0x3f924
778#define ixPM_FUSES_6 0x3f928
779#define ixPM_FUSES_7 0x3f92c
780#define ixPM_FUSES_8 0x3f930
781#define ixPM_FUSES_9 0x3f934
782#define ixPM_FUSES_10 0x3f938
783#define ixPM_FUSES_11 0x3f93c
784#define ixPM_FUSES_12 0x3f940
785#define ixPM_FUSES_13 0x3f944
786#define ixPM_FUSES_14 0x3f948
787#define ixPM_FUSES_15 0x3f94c
788#define ixSMU_PM_STATUS_0 0x3fe00
789#define ixSMU_PM_STATUS_1 0x3fe04
790#define ixSMU_PM_STATUS_2 0x3fe08
791#define ixSMU_PM_STATUS_3 0x3fe0c
792#define ixSMU_PM_STATUS_4 0x3fe10
793#define ixSMU_PM_STATUS_5 0x3fe14
794#define ixSMU_PM_STATUS_6 0x3fe18
795#define ixSMU_PM_STATUS_7 0x3fe1c
796#define ixSMU_PM_STATUS_8 0x3fe20
797#define ixSMU_PM_STATUS_9 0x3fe24
798#define ixSMU_PM_STATUS_10 0x3fe28
799#define ixSMU_PM_STATUS_11 0x3fe2c
800#define ixSMU_PM_STATUS_12 0x3fe30
801#define ixSMU_PM_STATUS_13 0x3fe34
802#define ixSMU_PM_STATUS_14 0x3fe38
803#define ixSMU_PM_STATUS_15 0x3fe3c
804#define ixSMU_PM_STATUS_16 0x3fe40
805#define ixSMU_PM_STATUS_17 0x3fe44
806#define ixSMU_PM_STATUS_18 0x3fe48
807#define ixSMU_PM_STATUS_19 0x3fe4c
808#define ixSMU_PM_STATUS_20 0x3fe50
809#define ixSMU_PM_STATUS_21 0x3fe54
810#define ixSMU_PM_STATUS_22 0x3fe58
811#define ixSMU_PM_STATUS_23 0x3fe5c
812#define ixSMU_PM_STATUS_24 0x3fe60
813#define ixSMU_PM_STATUS_25 0x3fe64
814#define ixSMU_PM_STATUS_26 0x3fe68
815#define ixSMU_PM_STATUS_27 0x3fe6c
816#define ixSMU_PM_STATUS_28 0x3fe70
817#define ixSMU_PM_STATUS_29 0x3fe74
818#define ixSMU_PM_STATUS_30 0x3fe78
819#define ixSMU_PM_STATUS_31 0x3fe7c
820#define ixSMU_PM_STATUS_32 0x3fe80
821#define ixSMU_PM_STATUS_33 0x3fe84
822#define ixSMU_PM_STATUS_34 0x3fe88
823#define ixSMU_PM_STATUS_35 0x3fe8c
824#define ixSMU_PM_STATUS_36 0x3fe90
825#define ixSMU_PM_STATUS_37 0x3fe94
826#define ixSMU_PM_STATUS_38 0x3fe98
827#define ixSMU_PM_STATUS_39 0x3fe9c
828#define ixSMU_PM_STATUS_40 0x3fea0
829#define ixSMU_PM_STATUS_41 0x3fea4
830#define ixSMU_PM_STATUS_42 0x3fea8
831#define ixSMU_PM_STATUS_43 0x3feac
832#define ixSMU_PM_STATUS_44 0x3feb0
833#define ixSMU_PM_STATUS_45 0x3feb4
834#define ixSMU_PM_STATUS_46 0x3feb8
835#define ixSMU_PM_STATUS_47 0x3febc
836#define ixSMU_PM_STATUS_48 0x3fec0
837#define ixSMU_PM_STATUS_49 0x3fec4
838#define ixSMU_PM_STATUS_50 0x3fec8
839#define ixSMU_PM_STATUS_51 0x3fecc
840#define ixSMU_PM_STATUS_52 0x3fed0
841#define ixSMU_PM_STATUS_53 0x3fed4
842#define ixSMU_PM_STATUS_54 0x3fed8
843#define ixSMU_PM_STATUS_55 0x3fedc
844#define ixSMU_PM_STATUS_56 0x3fee0
845#define ixSMU_PM_STATUS_57 0x3fee4
846#define ixSMU_PM_STATUS_58 0x3fee8
847#define ixSMU_PM_STATUS_59 0x3feec
848#define ixSMU_PM_STATUS_60 0x3fef0
849#define ixSMU_PM_STATUS_61 0x3fef4
850#define ixSMU_PM_STATUS_62 0x3fef8
851#define ixSMU_PM_STATUS_63 0x3fefc
852#define ixSMU_PM_STATUS_64 0x3ff00
853#define ixSMU_PM_STATUS_65 0x3ff04
854#define ixSMU_PM_STATUS_66 0x3ff08
855#define ixSMU_PM_STATUS_67 0x3ff0c
856#define ixSMU_PM_STATUS_68 0x3ff10
857#define ixSMU_PM_STATUS_69 0x3ff14
858#define ixSMU_PM_STATUS_70 0x3ff18
859#define ixSMU_PM_STATUS_71 0x3ff1c
860#define ixSMU_PM_STATUS_72 0x3ff20
861#define ixSMU_PM_STATUS_73 0x3ff24
862#define ixSMU_PM_STATUS_74 0x3ff28
863#define ixSMU_PM_STATUS_75 0x3ff2c
864#define ixSMU_PM_STATUS_76 0x3ff30
865#define ixSMU_PM_STATUS_77 0x3ff34
866#define ixSMU_PM_STATUS_78 0x3ff38
867#define ixSMU_PM_STATUS_79 0x3ff3c
868#define ixSMU_PM_STATUS_80 0x3ff40
869#define ixSMU_PM_STATUS_81 0x3ff44
870#define ixSMU_PM_STATUS_82 0x3ff48
871#define ixSMU_PM_STATUS_83 0x3ff4c
872#define ixSMU_PM_STATUS_84 0x3ff50
873#define ixSMU_PM_STATUS_85 0x3ff54
874#define ixSMU_PM_STATUS_86 0x3ff58
875#define ixSMU_PM_STATUS_87 0x3ff5c
876#define ixSMU_PM_STATUS_88 0x3ff60
877#define ixSMU_PM_STATUS_89 0x3ff64
878#define ixSMU_PM_STATUS_90 0x3ff68
879#define ixSMU_PM_STATUS_91 0x3ff6c
880#define ixSMU_PM_STATUS_92 0x3ff70
881#define ixSMU_PM_STATUS_93 0x3ff74
882#define ixSMU_PM_STATUS_94 0x3ff78
883#define ixSMU_PM_STATUS_95 0x3ff7c
884#define ixSMU_PM_STATUS_96 0x3ff80
885#define ixSMU_PM_STATUS_97 0x3ff84
886#define ixSMU_PM_STATUS_98 0x3ff88
887#define ixSMU_PM_STATUS_99 0x3ff8c
888#define ixSMU_PM_STATUS_100 0x3ff90
889#define ixSMU_PM_STATUS_101 0x3ff94
890#define ixSMU_PM_STATUS_102 0x3ff98
891#define ixSMU_PM_STATUS_103 0x3ff9c
892#define ixSMU_PM_STATUS_104 0x3ffa0
893#define ixSMU_PM_STATUS_105 0x3ffa4
894#define ixSMU_PM_STATUS_106 0x3ffa8
895#define ixSMU_PM_STATUS_107 0x3ffac
896#define ixSMU_PM_STATUS_108 0x3ffb0
897#define ixSMU_PM_STATUS_109 0x3ffb4
898#define ixSMU_PM_STATUS_110 0x3ffb8
899#define ixSMU_PM_STATUS_111 0x3ffbc
900#define ixSMU_PM_STATUS_112 0x3ffc0
901#define ixSMU_PM_STATUS_113 0x3ffc4
902#define ixSMU_PM_STATUS_114 0x3ffc8
903#define ixSMU_PM_STATUS_115 0x3ffcc
904#define ixSMU_PM_STATUS_116 0x3ffd0
905#define ixSMU_PM_STATUS_117 0x3ffd4
906#define ixSMU_PM_STATUS_118 0x3ffd8
907#define ixSMU_PM_STATUS_119 0x3ffdc
908#define ixSMU_PM_STATUS_120 0x3ffe0
909#define ixSMU_PM_STATUS_121 0x3ffe4
910#define ixSMU_PM_STATUS_122 0x3ffe8
911#define ixSMU_PM_STATUS_123 0x3ffec
912#define ixSMU_PM_STATUS_124 0x3fff0
913#define ixSMU_PM_STATUS_125 0x3fff4
914#define ixSMU_PM_STATUS_126 0x3fff8
915#define ixSMU_PM_STATUS_127 0x3fffc
916#define ixCG_THERMAL_INT_ENA 0xc2100024
917#define ixCG_THERMAL_INT_CTRL 0xc2100028
918#define ixCG_THERMAL_INT_STATUS 0xc210002c
919#define ixCG_THERMAL_CTRL 0xc0300004
920#define ixCG_THERMAL_STATUS 0xc0300008
921#define ixCG_THERMAL_INT 0xc030000c
922#define ixCG_MULT_THERMAL_CTRL 0xc0300010
923#define ixCG_MULT_THERMAL_STATUS 0xc0300014
924#define ixTHM_TMON2_CTRL 0xc0300034
925#define ixTHM_TMON2_CTRL2 0xc0300038
926#define ixTHM_TMON2_CSR_WR 0xc0300054
927#define ixTHM_TMON2_CSR_RD 0xc0300058
928#define ixCG_FDO_CTRL0 0xc0300064
929#define ixCG_FDO_CTRL1 0xc0300068
930#define ixCG_FDO_CTRL2 0xc030006c
931#define ixCG_TACH_CTRL 0xc0300070
932#define ixCG_TACH_STATUS 0xc0300074
933#define ixCC_THM_STRAPS0 0xc0300080
934#define ixTHM_TMON0_RDIL0_DATA 0xc0300100
935#define ixTHM_TMON0_RDIL1_DATA 0xc0300104
936#define ixTHM_TMON0_RDIL2_DATA 0xc0300108
937#define ixTHM_TMON0_RDIL3_DATA 0xc030010c
938#define ixTHM_TMON0_RDIL4_DATA 0xc0300110
939#define ixTHM_TMON0_RDIL5_DATA 0xc0300114
940#define ixTHM_TMON0_RDIL6_DATA 0xc0300118
941#define ixTHM_TMON0_RDIL7_DATA 0xc030011c
942#define ixTHM_TMON0_RDIL8_DATA 0xc0300120
943#define ixTHM_TMON0_RDIL9_DATA 0xc0300124
944#define ixTHM_TMON0_RDIL10_DATA 0xc0300128
945#define ixTHM_TMON0_RDIL11_DATA 0xc030012c
946#define ixTHM_TMON0_RDIL12_DATA 0xc0300130
947#define ixTHM_TMON0_RDIL13_DATA 0xc0300134
948#define ixTHM_TMON0_RDIL14_DATA 0xc0300138
949#define ixTHM_TMON0_RDIL15_DATA 0xc030013c
950#define ixTHM_TMON0_RDIR0_DATA 0xc0300140
951#define ixTHM_TMON0_RDIR1_DATA 0xc0300144
952#define ixTHM_TMON0_RDIR2_DATA 0xc0300148
953#define ixTHM_TMON0_RDIR3_DATA 0xc030014c
954#define ixTHM_TMON0_RDIR4_DATA 0xc0300150
955#define ixTHM_TMON0_RDIR5_DATA 0xc0300154
956#define ixTHM_TMON0_RDIR6_DATA 0xc0300158
957#define ixTHM_TMON0_RDIR7_DATA 0xc030015c
958#define ixTHM_TMON0_RDIR8_DATA 0xc0300160
959#define ixTHM_TMON0_RDIR9_DATA 0xc0300164
960#define ixTHM_TMON0_RDIR10_DATA 0xc0300168
961#define ixTHM_TMON0_RDIR11_DATA 0xc030016c
962#define ixTHM_TMON0_RDIR12_DATA 0xc0300170
963#define ixTHM_TMON0_RDIR13_DATA 0xc0300174
964#define ixTHM_TMON0_RDIR14_DATA 0xc0300178
965#define ixTHM_TMON0_RDIR15_DATA 0xc030017c
966#define ixTHM_TMON1_RDIL0_DATA 0xc0300180
967#define ixTHM_TMON1_RDIL1_DATA 0xc0300184
968#define ixTHM_TMON1_RDIL2_DATA 0xc0300188
969#define ixTHM_TMON1_RDIL3_DATA 0xc030018c
970#define ixTHM_TMON1_RDIL4_DATA 0xc0300190
971#define ixTHM_TMON1_RDIL5_DATA 0xc0300194
972#define ixTHM_TMON1_RDIL6_DATA 0xc0300198
973#define ixTHM_TMON1_RDIL7_DATA 0xc030019c
974#define ixTHM_TMON1_RDIL8_DATA 0xc03001a0
975#define ixTHM_TMON1_RDIL9_DATA 0xc03001a4
976#define ixTHM_TMON1_RDIL10_DATA 0xc03001a8
977#define ixTHM_TMON1_RDIL11_DATA 0xc03001ac
978#define ixTHM_TMON1_RDIL12_DATA 0xc03001b0
979#define ixTHM_TMON1_RDIL13_DATA 0xc03001b4
980#define ixTHM_TMON1_RDIL14_DATA 0xc03001b8
981#define ixTHM_TMON1_RDIL15_DATA 0xc03001bc
982#define ixTHM_TMON1_RDIR0_DATA 0xc03001c0
983#define ixTHM_TMON1_RDIR1_DATA 0xc03001c4
984#define ixTHM_TMON1_RDIR2_DATA 0xc03001c8
985#define ixTHM_TMON1_RDIR3_DATA 0xc03001cc
986#define ixTHM_TMON1_RDIR4_DATA 0xc03001d0
987#define ixTHM_TMON1_RDIR5_DATA 0xc03001d4
988#define ixTHM_TMON1_RDIR6_DATA 0xc03001d8
989#define ixTHM_TMON1_RDIR7_DATA 0xc03001dc
990#define ixTHM_TMON1_RDIR8_DATA 0xc03001e0
991#define ixTHM_TMON1_RDIR9_DATA 0xc03001e4
992#define ixTHM_TMON1_RDIR10_DATA 0xc03001e8
993#define ixTHM_TMON1_RDIR11_DATA 0xc03001ec
994#define ixTHM_TMON1_RDIR12_DATA 0xc03001f0
995#define ixTHM_TMON1_RDIR13_DATA 0xc03001f4
996#define ixTHM_TMON1_RDIR14_DATA 0xc03001f8
997#define ixTHM_TMON1_RDIR15_DATA 0xc03001fc
998#define ixTHM_TMON2_RDIL0_DATA 0xc0300200
999#define ixTHM_TMON2_RDIL1_DATA 0xc0300204
1000#define ixTHM_TMON2_RDIL2_DATA 0xc0300208
1001#define ixTHM_TMON2_RDIL3_DATA 0xc030020c
1002#define ixTHM_TMON2_RDIL4_DATA 0xc0300210
1003#define ixTHM_TMON2_RDIL5_DATA 0xc0300214
1004#define ixTHM_TMON2_RDIL6_DATA 0xc0300218
1005#define ixTHM_TMON2_RDIL7_DATA 0xc030021c
1006#define ixTHM_TMON2_RDIL8_DATA 0xc0300220
1007#define ixTHM_TMON2_RDIL9_DATA 0xc0300224
1008#define ixTHM_TMON2_RDIL10_DATA 0xc0300228
1009#define ixTHM_TMON2_RDIL11_DATA 0xc030022c
1010#define ixTHM_TMON2_RDIL12_DATA 0xc0300230
1011#define ixTHM_TMON2_RDIL13_DATA 0xc0300234
1012#define ixTHM_TMON2_RDIL14_DATA 0xc0300238
1013#define ixTHM_TMON2_RDIL15_DATA 0xc030023c
1014#define ixTHM_TMON2_RDIR0_DATA 0xc0300240
1015#define ixTHM_TMON2_RDIR1_DATA 0xc0300244
1016#define ixTHM_TMON2_RDIR2_DATA 0xc0300248
1017#define ixTHM_TMON2_RDIR3_DATA 0xc030024c
1018#define ixTHM_TMON2_RDIR4_DATA 0xc0300250
1019#define ixTHM_TMON2_RDIR5_DATA 0xc0300254
1020#define ixTHM_TMON2_RDIR6_DATA 0xc0300258
1021#define ixTHM_TMON2_RDIR7_DATA 0xc030025c
1022#define ixTHM_TMON2_RDIR8_DATA 0xc0300260
1023#define ixTHM_TMON2_RDIR9_DATA 0xc0300264
1024#define ixTHM_TMON2_RDIR10_DATA 0xc0300268
1025#define ixTHM_TMON2_RDIR11_DATA 0xc030026c
1026#define ixTHM_TMON2_RDIR12_DATA 0xc0300270
1027#define ixTHM_TMON2_RDIR13_DATA 0xc0300274
1028#define ixTHM_TMON2_RDIR14_DATA 0xc0300278
1029#define ixTHM_TMON2_RDIR15_DATA 0xc030027c
1030#define ixTHM_TMON0_INT_DATA 0xc0300300
1031#define ixTHM_TMON1_INT_DATA 0xc0300304
1032#define ixTHM_TMON2_INT_DATA 0xc0300308
1033#define ixTHM_TMON0_DEBUG 0xc0300310
1034#define ixTHM_TMON1_DEBUG 0xc0300314
1035#define ixTHM_TMON2_DEBUG 0xc0300318
1036#define ixTHM_TMON0_STATUS 0xc0300320
1037#define ixTHM_TMON1_STATUS 0xc0300324
1038#define ixTHM_TMON2_STATUS 0xc0300328
1039#define ixGENERAL_PWRMGT 0xc0200000
1040#define ixCNB_PWRMGT_CNTL 0xc0200004
1041#define ixSCLK_PWRMGT_CNTL 0xc0200008
1042#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014
1043#define ixPWR_PCC_CONTROL 0xc0200018
1044#define ixPWR_PCC_GPIO_SELECT 0xc020001c
1045#define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8
1046#define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac
1047#define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0
1048#define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4
1049#define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8
1050#define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc
1051#define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0
1052#define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4
1053#define ixPLL_TEST_CNTL 0xc020003c
1054#define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044
1055#define ixCG_DISPLAY_GAP_CNTL 0xc0200060
1056#define ixCG_DISPLAY_GAP_CNTL2 0xc0200230
1057#define ixCG_ACPI_CNTL 0xc0200064
1058#define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080
1059#define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084
1060#define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c
1061#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088
1062#define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c
1063#define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310
1064#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0
1065#define ixCG_ULV_PARAMETER 0xc020015c
1066#define ixSCLK_MIN_DIV 0xc02003ac
1067#define ixPWR_AVFS_SEL 0xc0200384
1068#define ixPWR_AVFS_CNTL 0xc0200388
1069#define ixPWR_AVFS0_CNTL_STATUS 0xc0200400
1070#define ixPWR_AVFS1_CNTL_STATUS 0xc0200404
1071#define ixPWR_AVFS2_CNTL_STATUS 0xc0200408
1072#define ixPWR_AVFS3_CNTL_STATUS 0xc020040c
1073#define ixPWR_AVFS4_CNTL_STATUS 0xc0200410
1074#define ixPWR_AVFS5_CNTL_STATUS 0xc0200414
1075#define ixPWR_AVFS6_CNTL_STATUS 0xc0200418
1076#define ixPWR_AVFS7_CNTL_STATUS 0xc020041c
1077#define ixPWR_AVFS8_CNTL_STATUS 0xc0200420
1078#define ixPWR_AVFS9_CNTL_STATUS 0xc0200424
1079#define ixPWR_AVFS10_CNTL_STATUS 0xc0200428
1080#define ixPWR_AVFS11_CNTL_STATUS 0xc020042c
1081#define ixPWR_AVFS12_CNTL_STATUS 0xc0200430
1082#define ixPWR_AVFS13_CNTL_STATUS 0xc0200434
1083#define ixPWR_AVFS14_CNTL_STATUS 0xc0200438
1084#define ixPWR_AVFS15_CNTL_STATUS 0xc020043c
1085#define ixPWR_AVFS16_CNTL_STATUS 0xc0200440
1086#define ixPWR_AVFS17_CNTL_STATUS 0xc0200444
1087#define ixPWR_AVFS18_CNTL_STATUS 0xc0200448
1088#define ixPWR_AVFS19_CNTL_STATUS 0xc020044c
1089#define ixPWR_AVFS20_CNTL_STATUS 0xc0200450
1090#define ixPWR_AVFS21_CNTL_STATUS 0xc0200454
1091#define ixPWR_AVFS22_CNTL_STATUS 0xc0200458
1092#define ixPWR_AVFS23_CNTL_STATUS 0xc020045c
1093#define ixPWR_AVFS24_CNTL_STATUS 0xc0200460
1094#define ixPWR_AVFS25_CNTL_STATUS 0xc0200464
1095#define ixPWR_AVFS26_CNTL_STATUS 0xc0200468
1096#define ixPWR_AVFS27_CNTL_STATUS 0xc020046c
1097#define ixPWR_CKS_ENABLE 0xc020034c
1098#define ixPWR_CKS_CNTL 0xc0200350
1099#define ixPWR_DISP_TIMER_CONTROL 0xc02003c0
1100#define ixPWR_DISP_TIMER_DEBUG 0xc02003c4
1101#define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8
1102#define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc
1103#define ixPWR_DISP_TIMER_CONTROL2 0xc0200378
1104#define ixVDDGFX_IDLE_PARAMETER 0xc020036c
1105#define ixVDDGFX_IDLE_CONTROL 0xc0200370
1106#define ixVDDGFX_IDLE_EXIT 0xc0200374
1107#define ixLCAC_MC0_CNTL 0xc0400130
1108#define ixLCAC_MC0_OVR_SEL 0xc0400134
1109#define ixLCAC_MC0_OVR_VAL 0xc0400138
1110#define ixLCAC_MC1_CNTL 0xc040013c
1111#define ixLCAC_MC1_OVR_SEL 0xc0400140
1112#define ixLCAC_MC1_OVR_VAL 0xc0400144
1113#define ixLCAC_MC2_CNTL 0xc0400148
1114#define ixLCAC_MC2_OVR_SEL 0xc040014c
1115#define ixLCAC_MC2_OVR_VAL 0xc0400150
1116#define ixLCAC_MC3_CNTL 0xc0400154
1117#define ixLCAC_MC3_OVR_SEL 0xc0400158
1118#define ixLCAC_MC3_OVR_VAL 0xc040015c
1119#define ixLCAC_MC4_CNTL 0xc0400d60
1120#define ixLCAC_MC4_OVR_SEL 0xc0400d64
1121#define ixLCAC_MC4_OVR_VAL 0xc0400d68
1122#define ixLCAC_MC5_CNTL 0xc0400d6c
1123#define ixLCAC_MC5_OVR_SEL 0xc0400d70
1124#define ixLCAC_MC5_OVR_VAL 0xc0400d74
1125#define ixLCAC_MC6_CNTL 0xc0400d78
1126#define ixLCAC_MC6_OVR_SEL 0xc0400d7c
1127#define ixLCAC_MC6_OVR_VAL 0xc0400d80
1128#define ixLCAC_MC7_CNTL 0xc0400d84
1129#define ixLCAC_MC7_OVR_SEL 0xc0400d88
1130#define ixLCAC_MC7_OVR_VAL 0xc0400d8c
1131#define ixLCAC_CPL_CNTL 0xc0400160
1132#define ixLCAC_CPL_OVR_SEL 0xc0400164
1133#define ixLCAC_CPL_OVR_VAL 0xc0400168
1134#define mmROM_SMC_IND_INDEX 0x80
1135#define mmROM0_ROM_SMC_IND_INDEX 0x80
1136#define mmROM1_ROM_SMC_IND_INDEX 0x82
1137#define mmROM2_ROM_SMC_IND_INDEX 0x84
1138#define mmROM3_ROM_SMC_IND_INDEX 0x86
1139#define mmROM_SMC_IND_DATA 0x81
1140#define mmROM0_ROM_SMC_IND_DATA 0x81
1141#define mmROM1_ROM_SMC_IND_DATA 0x83
1142#define mmROM2_ROM_SMC_IND_DATA 0x85
1143#define mmROM3_ROM_SMC_IND_DATA 0x87
1144#define ixROM_CNTL 0xc0600000
1145#define ixPAGE_MIRROR_CNTL 0xc0600004
1146#define ixROM_STATUS 0xc0600008
1147#define ixCGTT_ROM_CLK_CTRL0 0xc060000c
1148#define ixROM_INDEX 0xc0600010
1149#define ixROM_DATA 0xc0600014
1150#define ixROM_START 0xc0600018
1151#define ixROM_SW_CNTL 0xc060001c
1152#define ixROM_SW_STATUS 0xc0600020
1153#define ixROM_SW_COMMAND 0xc0600024
1154#define ixROM_SW_DATA_1 0xc0600028
1155#define ixROM_SW_DATA_2 0xc060002c
1156#define ixROM_SW_DATA_3 0xc0600030
1157#define ixROM_SW_DATA_4 0xc0600034
1158#define ixROM_SW_DATA_5 0xc0600038
1159#define ixROM_SW_DATA_6 0xc060003c
1160#define ixROM_SW_DATA_7 0xc0600040
1161#define ixROM_SW_DATA_8 0xc0600044
1162#define ixROM_SW_DATA_9 0xc0600048
1163#define ixROM_SW_DATA_10 0xc060004c
1164#define ixROM_SW_DATA_11 0xc0600050
1165#define ixROM_SW_DATA_12 0xc0600054
1166#define ixROM_SW_DATA_13 0xc0600058
1167#define ixROM_SW_DATA_14 0xc060005c
1168#define ixROM_SW_DATA_15 0xc0600060
1169#define ixROM_SW_DATA_16 0xc0600064
1170#define ixROM_SW_DATA_17 0xc0600068
1171#define ixROM_SW_DATA_18 0xc060006c
1172#define ixROM_SW_DATA_19 0xc0600070
1173#define ixROM_SW_DATA_20 0xc0600074
1174#define ixROM_SW_DATA_21 0xc0600078
1175#define ixROM_SW_DATA_22 0xc060007c
1176#define ixROM_SW_DATA_23 0xc0600080
1177#define ixROM_SW_DATA_24 0xc0600084
1178#define ixROM_SW_DATA_25 0xc0600088
1179#define ixROM_SW_DATA_26 0xc060008c
1180#define ixROM_SW_DATA_27 0xc0600090
1181#define ixROM_SW_DATA_28 0xc0600094
1182#define ixROM_SW_DATA_29 0xc0600098
1183#define ixROM_SW_DATA_30 0xc060009c
1184#define ixROM_SW_DATA_31 0xc06000a0
1185#define ixROM_SW_DATA_32 0xc06000a4
1186#define ixROM_SW_DATA_33 0xc06000a8
1187#define ixROM_SW_DATA_34 0xc06000ac
1188#define ixROM_SW_DATA_35 0xc06000b0
1189#define ixROM_SW_DATA_36 0xc06000b4
1190#define ixROM_SW_DATA_37 0xc06000b8
1191#define ixROM_SW_DATA_38 0xc06000bc
1192#define ixROM_SW_DATA_39 0xc06000c0
1193#define ixROM_SW_DATA_40 0xc06000c4
1194#define ixROM_SW_DATA_41 0xc06000c8
1195#define ixROM_SW_DATA_42 0xc06000cc
1196#define ixROM_SW_DATA_43 0xc06000d0
1197#define ixROM_SW_DATA_44 0xc06000d4
1198#define ixROM_SW_DATA_45 0xc06000d8
1199#define ixROM_SW_DATA_46 0xc06000dc
1200#define ixROM_SW_DATA_47 0xc06000e0
1201#define ixROM_SW_DATA_48 0xc06000e4
1202#define ixROM_SW_DATA_49 0xc06000e8
1203#define ixROM_SW_DATA_50 0xc06000ec
1204#define ixROM_SW_DATA_51 0xc06000f0
1205#define ixROM_SW_DATA_52 0xc06000f4
1206#define ixROM_SW_DATA_53 0xc06000f8
1207#define ixROM_SW_DATA_54 0xc06000fc
1208#define ixROM_SW_DATA_55 0xc0600100
1209#define ixROM_SW_DATA_56 0xc0600104
1210#define ixROM_SW_DATA_57 0xc0600108
1211#define ixROM_SW_DATA_58 0xc060010c
1212#define ixROM_SW_DATA_59 0xc0600110
1213#define ixROM_SW_DATA_60 0xc0600114
1214#define ixROM_SW_DATA_61 0xc0600118
1215#define ixROM_SW_DATA_62 0xc060011c
1216#define ixROM_SW_DATA_63 0xc0600120
1217#define ixROM_SW_DATA_64 0xc0600124
1218#define mmGC_CAC_CGTT_CLK_CTRL 0x3292
1219#define mmSE_CAC_CGTT_CLK_CTRL 0x3293
1220#define mmGC_CAC_LKG_AGGR_LOWER 0x3296
1221#define mmGC_CAC_LKG_AGGR_UPPER 0x3297
1222#define ixGC_CAC_WEIGHT_CU_0 0x32
1223#define ixGC_CAC_WEIGHT_CU_1 0x33
1224#define ixGC_CAC_WEIGHT_CU_2 0x34
1225#define ixGC_CAC_WEIGHT_CU_3 0x35
1226#define ixGC_CAC_WEIGHT_CU_4 0x36
1227#define ixGC_CAC_WEIGHT_CU_5 0x37
1228#define ixGC_CAC_WEIGHT_CU_6 0x38
1229#define ixGC_CAC_WEIGHT_CU_7 0x39
1230#define ixGC_CAC_ACC_CU0 0xba
1231#define ixGC_CAC_ACC_CU1 0xbb
1232#define ixGC_CAC_ACC_CU2 0xbc
1233#define ixGC_CAC_ACC_CU3 0xbd
1234#define ixGC_CAC_ACC_CU4 0xbe
1235#define ixGC_CAC_ACC_CU5 0xbf
1236#define ixGC_CAC_ACC_CU6 0xc0
1237#define ixGC_CAC_ACC_CU7 0xc1
1238#define ixGC_CAC_ACC_CU8 0xc2
1239#define ixGC_CAC_ACC_CU9 0xc3
1240#define ixGC_CAC_ACC_CU10 0xc4
1241#define ixGC_CAC_ACC_CU11 0xc5
1242#define ixGC_CAC_ACC_CU12 0xc6
1243#define ixGC_CAC_ACC_CU13 0xc7
1244#define ixGC_CAC_ACC_CU14 0xc8
1245#define ixGC_CAC_ACC_CU15 0xc9
1246#define ixGC_CAC_OVRD_CU 0xe7
1247#define ixCURRENT_PG_STATUS 0xc020029c
1248#define ixCURRENT_PG_STATUS_APU 0xd020029c
1249#define ixPWR_SVI2_STATUS 0xC0200294
1250
1251#endif /* SMU_7_1_3_D_H */
1252