1/*
2 * SMU_7_1_3 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef SMU_7_1_3_SH_MASK_H
25#define SMU_7_1_3_SH_MASK_H
26
27#define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28#define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29#define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30#define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31#define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32#define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33#define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34#define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35#define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36#define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
37#define GCK_MCLK_FUSES__MClkDiDtWait_MASK 0xe000
38#define GCK_MCLK_FUSES__MClkDiDtWait__SHIFT 0xd
39#define GCK_MCLK_FUSES__MClkDiDtFloor_MASK 0x30000
40#define GCK_MCLK_FUSES__MClkDiDtFloor__SHIFT 0x10
41#define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
42#define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
43#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
44#define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
45#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
46#define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
47#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
48#define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
49#define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
50#define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
51#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
52#define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
53#define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
54#define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
55#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
56#define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
57#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
58#define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
59#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
60#define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
61#define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
62#define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
63#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
64#define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
65#define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
66#define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
67#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
68#define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
69#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
70#define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
71#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
72#define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
73#define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
74#define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
75#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
76#define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
77#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
78#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
79#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
80#define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
81#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
82#define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
83#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
84#define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
85#define CG_MCLK_CNTL__MCLK_DIVIDER_MASK 0x7f
86#define CG_MCLK_CNTL__MCLK_DIVIDER__SHIFT 0x0
87#define CG_MCLK_CNTL__MCLK_DIR_CNTL_EN_MASK 0x100
88#define CG_MCLK_CNTL__MCLK_DIR_CNTL_EN__SHIFT 0x8
89#define CG_MCLK_CNTL__MCLK_DIR_CNTL_TOG_MASK 0x200
90#define CG_MCLK_CNTL__MCLK_DIR_CNTL_TOG__SHIFT 0x9
91#define CG_MCLK_CNTL__MCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
92#define CG_MCLK_CNTL__MCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
93#define CG_MCLK_STATUS__MCLK_STATUS_MASK 0x1
94#define CG_MCLK_STATUS__MCLK_STATUS__SHIFT 0x0
95#define CG_MCLK_STATUS__MCLK_DIR_CNTL_DONETOG_MASK 0x2
96#define CG_MCLK_STATUS__MCLK_DIR_CNTL_DONETOG__SHIFT 0x1
97#define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
98#define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
99#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
100#define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
101#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
102#define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
103#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
104#define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
105#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
106#define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
107#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
108#define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
109#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
110#define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
111#define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
112#define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
113#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
114#define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
115#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
116#define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
117#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
118#define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
119#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
120#define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
121#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
122#define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
123#define GCK_DFS_BYPASS_CNTL__BYPASSMCLK_MASK 0x2000
124#define GCK_DFS_BYPASS_CNTL__BYPASSMCLK__SHIFT 0xd
125#define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
126#define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
127#define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
128#define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
129#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
130#define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
131#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
132#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
133#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
134#define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
135#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
136#define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
137#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
138#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
139#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
140#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
141#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000
142#define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14
143#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000
144#define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b
145#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
146#define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
147#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
148#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
149#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
150#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
151#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
152#define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
153#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
154#define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
155#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
156#define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
157#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
158#define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
159#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
160#define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
161#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
162#define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
163#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
164#define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
165#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
166#define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
167#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
168#define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
169#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
170#define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
171#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
172#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
173#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
174#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
175#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
176#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
177#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0xe00
178#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9
179#define CG_SPLL_FUNC_CNTL_4__PCC_INC_DIV_MASK 0x7f000
180#define CG_SPLL_FUNC_CNTL_4__PCC_INC_DIV__SHIFT 0xc
181#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
182#define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
183#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
184#define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
185#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
186#define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
187#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
188#define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
189#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
190#define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
191#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
192#define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
193#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
194#define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
195#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
196#define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
197#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
198#define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
199#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
200#define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
201#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
202#define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
203#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
204#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
205#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
206#define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
207#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
208#define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
209#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
210#define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
211#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
212#define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
213#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
214#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
215#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
216#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
217#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
218#define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
219#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
220#define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
221#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
222#define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
223#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
224#define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
225#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
226#define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
227#define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
228#define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
229#define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
230#define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
231#define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
232#define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
233#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
234#define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
235#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
236#define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
237#define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
238#define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
239#define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
240#define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
241#define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
242#define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
243#define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
244#define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
245#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
246#define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
247#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
248#define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
249#define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
250#define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
251#define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
252#define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
253#define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
254#define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
255#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
256#define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
257#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
258#define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
259#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
260#define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
261#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
262#define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
263#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
264#define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
265#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
266#define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
267#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
268#define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
269#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
270#define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
271#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
272#define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
273#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
274#define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
275#define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
276#define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
277#define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
278#define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
279#define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1
280#define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0
281#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6
282#define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1
283#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200
284#define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9
285#define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00
286#define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa
287#define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
288#define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
289#define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
290#define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
291#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
292#define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
293#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
294#define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
295#define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
296#define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
297#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
298#define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
299#define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
300#define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
301#define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
302#define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
303#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
304#define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
305#define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
306#define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
307#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
308#define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
309#define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
310#define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
311#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
312#define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
313#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
314#define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
315#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
316#define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
317#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
318#define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
319#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
320#define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
321#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
322#define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
323#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
324#define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
325#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
326#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
327#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
328#define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
329#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
330#define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
331#define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
332#define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
333#define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
334#define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
335#define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
336#define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
337#define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
338#define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
339#define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
340#define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
341#define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
342#define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
343#define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
344#define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
345#define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
346#define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
347#define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
348#define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
349#define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
350#define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
351#define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
352#define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
353#define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
354#define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
355#define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
356#define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
357#define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
358#define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
359#define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
360#define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
361#define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
362#define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
363#define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
364#define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
365#define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
366#define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
367#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
368#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
369#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
370#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
371#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
372#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
373#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
374#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
375#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
376#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
377#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
378#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
379#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
380#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
381#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
382#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
383#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
384#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8
385#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200
386#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9
387#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400
388#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa
389#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800
390#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb
391#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000
392#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc
393#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000
394#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd
395#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000
396#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe
397#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000
398#define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf
399#define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
400#define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
401#define SMC_RESP_0__SMC_RESP_MASK 0xffff
402#define SMC_RESP_0__SMC_RESP__SHIFT 0x0
403#define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
404#define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
405#define SMC_RESP_1__SMC_RESP_MASK 0xffff
406#define SMC_RESP_1__SMC_RESP__SHIFT 0x0
407#define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
408#define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
409#define SMC_RESP_2__SMC_RESP_MASK 0xffff
410#define SMC_RESP_2__SMC_RESP__SHIFT 0x0
411#define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
412#define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
413#define SMC_RESP_3__SMC_RESP_MASK 0xffff
414#define SMC_RESP_3__SMC_RESP__SHIFT 0x0
415#define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
416#define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
417#define SMC_RESP_4__SMC_RESP_MASK 0xffff
418#define SMC_RESP_4__SMC_RESP__SHIFT 0x0
419#define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
420#define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
421#define SMC_RESP_5__SMC_RESP_MASK 0xffff
422#define SMC_RESP_5__SMC_RESP__SHIFT 0x0
423#define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
424#define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
425#define SMC_RESP_6__SMC_RESP_MASK 0xffff
426#define SMC_RESP_6__SMC_RESP__SHIFT 0x0
427#define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
428#define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
429#define SMC_RESP_7__SMC_RESP_MASK 0xffff
430#define SMC_RESP_7__SMC_RESP__SHIFT 0x0
431#define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
432#define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
433#define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
434#define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
435#define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
436#define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
437#define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
438#define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
439#define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
440#define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
441#define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
442#define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
443#define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
444#define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
445#define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
446#define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
447#define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
448#define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
449#define SMC_RESP_8__SMC_RESP_MASK 0xffff
450#define SMC_RESP_8__SMC_RESP__SHIFT 0x0
451#define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
452#define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
453#define SMC_RESP_9__SMC_RESP_MASK 0xffff
454#define SMC_RESP_9__SMC_RESP__SHIFT 0x0
455#define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
456#define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
457#define SMC_RESP_10__SMC_RESP_MASK 0xffff
458#define SMC_RESP_10__SMC_RESP__SHIFT 0x0
459#define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
460#define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
461#define SMC_RESP_11__SMC_RESP_MASK 0xffff
462#define SMC_RESP_11__SMC_RESP__SHIFT 0x0
463#define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
464#define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
465#define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
466#define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
467#define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
468#define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
469#define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
470#define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
471#define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
472#define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
473#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
474#define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
475#define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
476#define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
477#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
478#define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
479#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
480#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
481#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
482#define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
483#define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
484#define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
485#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
486#define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
487#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
488#define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
489#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2
490#define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1
491#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
492#define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
493#define SMC_PC_C__smc_pc_c_MASK 0xffffffff
494#define SMC_PC_C__smc_pc_c__SHIFT 0x0
495#define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
496#define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
497#define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1
498#define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0
499#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf
500#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0
501#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0
502#define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4
503#define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff
504#define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0
505#define GPIOPAD_A__GPIO_A_MASK 0x7fffffff
506#define GPIOPAD_A__GPIO_A__SHIFT 0x0
507#define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff
508#define GPIOPAD_EN__GPIO_EN__SHIFT 0x0
509#define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff
510#define GPIOPAD_Y__GPIO_Y__SHIFT 0x0
511#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1
512#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0
513#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2
514#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1
515#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4
516#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2
517#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8
518#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3
519#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10
520#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4
521#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20
522#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5
523#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40
524#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6
525#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80
526#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7
527#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
528#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8
529#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200
530#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9
531#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400
532#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa
533#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800
534#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb
535#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000
536#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc
537#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000
538#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd
539#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000
540#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe
541#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000
542#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf
543#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000
544#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10
545#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000
546#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11
547#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000
548#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12
549#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000
550#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13
551#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000
552#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14
553#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000
554#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15
555#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000
556#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16
557#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000
558#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17
559#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000
560#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18
561#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000
562#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19
563#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000
564#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a
565#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000
566#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b
567#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000
568#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c
569#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000
570#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d
571#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000
572#define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e
573#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff
574#define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0
575#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000
576#define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f
577#define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff
578#define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0
579#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000
580#define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f
581#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1
582#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0
583#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2
584#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1
585#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4
586#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2
587#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8
588#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3
589#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10
590#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4
591#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20
592#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5
593#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40
594#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6
595#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80
596#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7
597#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
598#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8
599#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200
600#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9
601#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400
602#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
603#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800
604#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb
605#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000
606#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc
607#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000
608#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd
609#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000
610#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe
611#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000
612#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf
613#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000
614#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10
615#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000
616#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11
617#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000
618#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12
619#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000
620#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13
621#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000
622#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14
623#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000
624#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15
625#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000
626#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16
627#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000
628#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17
629#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000
630#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18
631#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000
632#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19
633#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000
634#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a
635#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000
636#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b
637#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000
638#define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c
639#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000
640#define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f
641#define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff
642#define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0
643#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000
644#define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f
645#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff
646#define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0
647#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000
648#define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f
649#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff
650#define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0
651#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000
652#define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f
653#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f
654#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0
655#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20
656#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5
657#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40
658#define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6
659#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff
660#define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0
661#define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff
662#define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0
663#define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff
664#define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0
665#define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff
666#define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
667#define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
668#define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
669#define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
670#define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
671#define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
672#define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
673#define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
674#define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
675#define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
676#define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
677#define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
678#define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
679#define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
680#define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
681#define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
682#define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
683#define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
684#define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
685#define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
686#define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
687#define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
688#define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
689#define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
690#define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
691#define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
692#define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
693#define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
694#define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
695#define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
696#define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
697#define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
698#define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
699#define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
700#define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
701#define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
702#define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
703#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
704#define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
705#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
706#define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
707#define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
708#define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
709#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8
710#define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3
711#define RCU_UC_EVENTS__TP_Tester_MASK 0x40
712#define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
713#define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
714#define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
715#define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
716#define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
717#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
718#define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
719#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
720#define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
721#define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
722#define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
723#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
724#define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
725#define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
726#define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
727#define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
728#define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
729#define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
730#define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
731#define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
732#define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
733#define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
734#define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
735#define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
736#define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
737#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
738#define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
739#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
740#define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
741#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
742#define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
743#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
744#define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
745#define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
746#define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
747#define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
748#define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
749#define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
750#define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
751#define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
752#define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
753#define RCU_VIRT_RESET_REQ__VF_MASK 0xffff
754#define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0
755#define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000
756#define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f
757#define CC_RCU_FUSES__GPU_DIS_MASK 0x2
758#define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
759#define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
760#define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
761#define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
762#define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
763#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
764#define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
765#define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
766#define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
767#define CC_RCU_FUSES__ROM_DIS_MASK 0x80
768#define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
769#define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
770#define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
771#define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
772#define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
773#define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
774#define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
775#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000
776#define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe
777#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000
778#define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf
779#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000
780#define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10
781#define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000
782#define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11
783#define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000
784#define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12
785#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000
786#define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13
787#define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000
788#define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15
789#define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000
790#define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16
791#define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000
792#define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17
793#define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000
794#define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18
795#define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000
796#define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19
797#define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000
798#define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a
799#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
800#define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
801#define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
802#define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
803#define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
804#define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
805#define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
806#define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
807#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
808#define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
809#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
810#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
811#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
812#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
813#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
814#define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
815#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
816#define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
817#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
818#define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
819#define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
820#define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
821#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
822#define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
823#define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
824#define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
825#define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
826#define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
827#define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
828#define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
829#define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
830#define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
831#define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
832#define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
833#define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
834#define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
835#define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e
836#define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
837#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
838#define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
839#define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
840#define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
841#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
842#define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
843#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
844#define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
845#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
846#define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
847#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
848#define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
849#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
850#define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
851#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
852#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
853#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
854#define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
855#define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
856#define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
857#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
858#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
859#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
860#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
861#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
862#define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
863#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
864#define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
865#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
866#define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
867#define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
868#define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
869#define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
870#define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
871#define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
872#define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
873#define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
874#define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
875#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
876#define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
877#define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6
878#define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1
879#define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10
880#define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4
881#define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40
882#define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6
883#define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00
884#define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8
885#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
886#define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
887#define SMU_STATUS__SMU_DONE_MASK 0x1
888#define SMU_STATUS__SMU_DONE__SHIFT 0x0
889#define SMU_STATUS__SMU_PASS_MASK 0x2
890#define SMU_STATUS__SMU_PASS__SHIFT 0x1
891#define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
892#define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
893#define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
894#define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
895#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
896#define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
897#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
898#define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
899#define SMU_FIRMWARE__SMU_counter_MASK 0xf00
900#define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
901#define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
902#define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
903#define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
904#define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
905#define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
906#define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
907#define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
908#define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
909#define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
910#define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
911#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
912#define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
913#define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
914#define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
915#define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
916#define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
917#define TDC_STATUS__VDD_Boost_MASK 0xff
918#define TDC_STATUS__VDD_Boost__SHIFT 0x0
919#define TDC_STATUS__VDD_Throttle_MASK 0xff00
920#define TDC_STATUS__VDD_Throttle__SHIFT 0x8
921#define TDC_STATUS__VDDC_Boost_MASK 0xff0000
922#define TDC_STATUS__VDDC_Boost__SHIFT 0x10
923#define TDC_STATUS__VDDC_Throttle_MASK 0xff000000
924#define TDC_STATUS__VDDC_Throttle__SHIFT 0x18
925#define TDC_MV_AVERAGE__IDD_MASK 0xffff
926#define TDC_MV_AVERAGE__IDD__SHIFT 0x0
927#define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000
928#define TDC_MV_AVERAGE__IDDC__SHIFT 0x10
929#define TDC_VRM_LIMIT__IDD_MASK 0xffff
930#define TDC_VRM_LIMIT__IDD__SHIFT 0x0
931#define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000
932#define TDC_VRM_LIMIT__IDDC__SHIFT 0x10
933#define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
934#define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
935#define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
936#define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
937#define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
938#define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
939#define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
940#define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
941#define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
942#define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
943#define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20
944#define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5
945#define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40
946#define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6
947#define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
948#define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
949#define FEATURE_STATUS__BAPM_ON_MASK 0x100
950#define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
951#define FEATURE_STATUS__LPMX_ON_MASK 0x200
952#define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
953#define FEATURE_STATUS__NBDPM_ON_MASK 0x400
954#define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
955#define FEATURE_STATUS__LHTC_ON_MASK 0x800
956#define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
957#define FEATURE_STATUS__VPC_ON_MASK 0x1000
958#define FEATURE_STATUS__VPC_ON__SHIFT 0xc
959#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
960#define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
961#define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
962#define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
963#define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
964#define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
965#define FEATURE_STATUS__AVS_ON_MASK 0x10000
966#define FEATURE_STATUS__AVS_ON__SHIFT 0x10
967#define FEATURE_STATUS__SPMI_ON_MASK 0x20000
968#define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
969#define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
970#define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
971#define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
972#define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
973#define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
974#define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
975#define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
976#define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
977#define FEATURE_STATUS__RESERVED_MASK 0xffc00000
978#define FEATURE_STATUS__RESERVED__SHIFT 0x16
979#define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff
980#define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0
981#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff
982#define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0
983#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff
984#define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0
985#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff
986#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0
987#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00
988#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8
989#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000
990#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10
991#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000
992#define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18
993#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff
994#define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0
995#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff
996#define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0
997#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff
998#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0
999#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00
1000#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8
1001#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000
1002#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10
1003#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000
1004#define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18
1005#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff
1006#define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0
1007#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff
1008#define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0
1009#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff
1010#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0
1011#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00
1012#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8
1013#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000
1014#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10
1015#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000
1016#define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18
1017#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff
1018#define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0
1019#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff
1020#define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0
1021#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff
1022#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0
1023#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00
1024#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8
1025#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000
1026#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10
1027#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000
1028#define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18
1029#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff
1030#define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0
1031#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff
1032#define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0
1033#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff
1034#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0
1035#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00
1036#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8
1037#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000
1038#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10
1039#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000
1040#define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18
1041#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff
1042#define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0
1043#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff
1044#define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0
1045#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff
1046#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0
1047#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00
1048#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8
1049#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000
1050#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10
1051#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000
1052#define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18
1053#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff
1054#define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0
1055#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff
1056#define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0
1057#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff
1058#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0
1059#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00
1060#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8
1061#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000
1062#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10
1063#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000
1064#define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18
1065#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff
1066#define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0
1067#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff
1068#define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0
1069#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff
1070#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0
1071#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00
1072#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8
1073#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000
1074#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10
1075#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000
1076#define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18
1077#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff
1078#define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0
1079#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff
1080#define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0
1081#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff
1082#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0
1083#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00
1084#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8
1085#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000
1086#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10
1087#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000
1088#define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18
1089#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff
1090#define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0
1091#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff
1092#define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0
1093#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff
1094#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0
1095#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00
1096#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8
1097#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000
1098#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10
1099#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000
1100#define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18
1101#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff
1102#define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0
1103#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff
1104#define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0
1105#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff
1106#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0
1107#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00
1108#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8
1109#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000
1110#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10
1111#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000
1112#define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18
1113#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff
1114#define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0
1115#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff
1116#define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0
1117#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff
1118#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0
1119#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00
1120#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8
1121#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000
1122#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10
1123#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000
1124#define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18
1125#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff
1126#define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0
1127#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff
1128#define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0
1129#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff
1130#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0
1131#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00
1132#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8
1133#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000
1134#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10
1135#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000
1136#define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18
1137#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff
1138#define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0
1139#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff
1140#define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0
1141#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff
1142#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0
1143#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00
1144#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8
1145#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000
1146#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10
1147#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000
1148#define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18
1149#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff
1150#define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0
1151#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff
1152#define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0
1153#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff
1154#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0
1155#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00
1156#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8
1157#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000
1158#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10
1159#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000
1160#define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18
1161#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff
1162#define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0
1163#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff
1164#define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0
1165#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff
1166#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0
1167#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00
1168#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8
1169#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000
1170#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10
1171#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000
1172#define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18
1173#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff
1174#define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0
1175#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff
1176#define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0
1177#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff
1178#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0
1179#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00
1180#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8
1181#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000
1182#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10
1183#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000
1184#define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18
1185#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff
1186#define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0
1187#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff
1188#define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0
1189#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff
1190#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0
1191#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00
1192#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8
1193#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000
1194#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10
1195#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000
1196#define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18
1197#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff
1198#define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0
1199#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff
1200#define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0
1201#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff
1202#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0
1203#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00
1204#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8
1205#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000
1206#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10
1207#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000
1208#define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18
1209#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff
1210#define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0
1211#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff
1212#define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0
1213#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff
1214#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0
1215#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00
1216#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8
1217#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000
1218#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10
1219#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000
1220#define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18
1221#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff
1222#define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0
1223#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff
1224#define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0
1225#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff
1226#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0
1227#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00
1228#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8
1229#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000
1230#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10
1231#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000
1232#define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18
1233#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff
1234#define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0
1235#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff
1236#define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0
1237#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff
1238#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0
1239#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00
1240#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8
1241#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000
1242#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10
1243#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000
1244#define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18
1245#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff
1246#define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0
1247#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff
1248#define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0
1249#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff
1250#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0
1251#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00
1252#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8
1253#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000
1254#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10
1255#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000
1256#define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18
1257#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff
1258#define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0
1259#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff
1260#define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0
1261#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff
1262#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0
1263#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00
1264#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8
1265#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000
1266#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10
1267#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000
1268#define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18
1269#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff
1270#define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0
1271#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff
1272#define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0
1273#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff
1274#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0
1275#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00
1276#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8
1277#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000
1278#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10
1279#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000
1280#define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18
1281#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff
1282#define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0
1283#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff
1284#define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0
1285#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff
1286#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0
1287#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00
1288#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8
1289#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000
1290#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10
1291#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000
1292#define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18
1293#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff
1294#define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0
1295#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff
1296#define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0
1297#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff
1298#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0
1299#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00
1300#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8
1301#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000
1302#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10
1303#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000
1304#define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18
1305#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff
1306#define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0
1307#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff
1308#define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0
1309#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff
1310#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0
1311#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00
1312#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8
1313#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000
1314#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10
1315#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000
1316#define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18
1317#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff
1318#define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0
1319#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff
1320#define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0
1321#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff
1322#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0
1323#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00
1324#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8
1325#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000
1326#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10
1327#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000
1328#define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18
1329#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff
1330#define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0
1331#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff
1332#define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0
1333#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff
1334#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0
1335#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00
1336#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8
1337#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000
1338#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10
1339#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000
1340#define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18
1341#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff
1342#define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0
1343#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff
1344#define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0
1345#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff
1346#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0
1347#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00
1348#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8
1349#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000
1350#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10
1351#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000
1352#define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18
1353#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff
1354#define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0
1355#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff
1356#define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0
1357#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff
1358#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0
1359#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00
1360#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8
1361#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000
1362#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10
1363#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000
1364#define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18
1365#define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff
1366#define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0
1367#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
1368#define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
1369#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
1370#define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
1371#define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff
1372#define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0
1373#define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff
1374#define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0
1375#define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff
1376#define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0
1377#define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff
1378#define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0
1379#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
1380#define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
1381#define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff
1382#define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0
1383#define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff
1384#define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0
1385#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff
1386#define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0
1387#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff
1388#define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0
1389#define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff
1390#define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0
1391#define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff
1392#define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0
1393#define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff
1394#define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0
1395#define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff
1396#define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0
1397#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff
1398#define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0
1399#define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff
1400#define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0
1401#define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff
1402#define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0
1403#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff
1404#define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0
1405#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff
1406#define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0
1407#define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff
1408#define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0
1409#define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff
1410#define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0
1411#define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff
1412#define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0
1413#define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff
1414#define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0
1415#define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff
1416#define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0
1417#define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff
1418#define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0
1419#define DPM_TABLE_28__SystemFlags_MASK 0xffffffff
1420#define DPM_TABLE_28__SystemFlags__SHIFT 0x0
1421#define DPM_TABLE_29__VRConfig_MASK 0xffffffff
1422#define DPM_TABLE_29__VRConfig__SHIFT 0x0
1423#define DPM_TABLE_30__SmioMask1_MASK 0xffffffff
1424#define DPM_TABLE_30__SmioMask1__SHIFT 0x0
1425#define DPM_TABLE_31__SmioMask2_MASK 0xffffffff
1426#define DPM_TABLE_31__SmioMask2__SHIFT 0x0
1427#define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff
1428#define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0
1429#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00
1430#define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8
1431#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000
1432#define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10
1433#define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff
1434#define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0
1435#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00
1436#define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8
1437#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000
1438#define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10
1439#define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff
1440#define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0
1441#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00
1442#define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8
1443#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000
1444#define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10
1445#define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff
1446#define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0
1447#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00
1448#define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8
1449#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000
1450#define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10
1451#define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff
1452#define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0
1453#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00
1454#define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8
1455#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000
1456#define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10
1457#define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff
1458#define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0
1459#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00
1460#define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8
1461#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000
1462#define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10
1463#define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff
1464#define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0
1465#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00
1466#define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8
1467#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000
1468#define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10
1469#define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff
1470#define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0
1471#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00
1472#define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8
1473#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000
1474#define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10
1475#define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff
1476#define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0
1477#define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff
1478#define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0
1479#define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff
1480#define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0
1481#define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff
1482#define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0
1483#define DPM_TABLE_44__VddcTable_1_MASK 0xffff
1484#define DPM_TABLE_44__VddcTable_1__SHIFT 0x0
1485#define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000
1486#define DPM_TABLE_44__VddcTable_0__SHIFT 0x10
1487#define DPM_TABLE_45__VddcTable_3_MASK 0xffff
1488#define DPM_TABLE_45__VddcTable_3__SHIFT 0x0
1489#define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000
1490#define DPM_TABLE_45__VddcTable_2__SHIFT 0x10
1491#define DPM_TABLE_46__VddcTable_5_MASK 0xffff
1492#define DPM_TABLE_46__VddcTable_5__SHIFT 0x0
1493#define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000
1494#define DPM_TABLE_46__VddcTable_4__SHIFT 0x10
1495#define DPM_TABLE_47__VddcTable_7_MASK 0xffff
1496#define DPM_TABLE_47__VddcTable_7__SHIFT 0x0
1497#define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000
1498#define DPM_TABLE_47__VddcTable_6__SHIFT 0x10
1499#define DPM_TABLE_48__VddcTable_9_MASK 0xffff
1500#define DPM_TABLE_48__VddcTable_9__SHIFT 0x0
1501#define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000
1502#define DPM_TABLE_48__VddcTable_8__SHIFT 0x10
1503#define DPM_TABLE_49__VddcTable_11_MASK 0xffff
1504#define DPM_TABLE_49__VddcTable_11__SHIFT 0x0
1505#define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000
1506#define DPM_TABLE_49__VddcTable_10__SHIFT 0x10
1507#define DPM_TABLE_50__VddcTable_13_MASK 0xffff
1508#define DPM_TABLE_50__VddcTable_13__SHIFT 0x0
1509#define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000
1510#define DPM_TABLE_50__VddcTable_12__SHIFT 0x10
1511#define DPM_TABLE_51__VddcTable_15_MASK 0xffff
1512#define DPM_TABLE_51__VddcTable_15__SHIFT 0x0
1513#define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000
1514#define DPM_TABLE_51__VddcTable_14__SHIFT 0x10
1515#define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff
1516#define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0
1517#define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000
1518#define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10
1519#define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff
1520#define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0
1521#define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000
1522#define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10
1523#define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff
1524#define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0
1525#define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000
1526#define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10
1527#define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff
1528#define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0
1529#define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000
1530#define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10
1531#define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff
1532#define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0
1533#define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000
1534#define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10
1535#define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff
1536#define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0
1537#define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000
1538#define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10
1539#define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff
1540#define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0
1541#define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000
1542#define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10
1543#define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff
1544#define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0
1545#define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000
1546#define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10
1547#define DPM_TABLE_60__VddciTable_1_MASK 0xffff
1548#define DPM_TABLE_60__VddciTable_1__SHIFT 0x0
1549#define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000
1550#define DPM_TABLE_60__VddciTable_0__SHIFT 0x10
1551#define DPM_TABLE_61__VddciTable_3_MASK 0xffff
1552#define DPM_TABLE_61__VddciTable_3__SHIFT 0x0
1553#define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000
1554#define DPM_TABLE_61__VddciTable_2__SHIFT 0x10
1555#define DPM_TABLE_62__VddciTable_5_MASK 0xffff
1556#define DPM_TABLE_62__VddciTable_5__SHIFT 0x0
1557#define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000
1558#define DPM_TABLE_62__VddciTable_4__SHIFT 0x10
1559#define DPM_TABLE_63__VddciTable_7_MASK 0xffff
1560#define DPM_TABLE_63__VddciTable_7__SHIFT 0x0
1561#define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000
1562#define DPM_TABLE_63__VddciTable_6__SHIFT 0x10
1563#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff
1564#define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0
1565#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00
1566#define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8
1567#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000
1568#define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10
1569#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000
1570#define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18
1571#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff
1572#define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0
1573#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00
1574#define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8
1575#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000
1576#define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10
1577#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000
1578#define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18
1579#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff
1580#define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0
1581#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00
1582#define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8
1583#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000
1584#define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10
1585#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000
1586#define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18
1587#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff
1588#define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0
1589#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00
1590#define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8
1591#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000
1592#define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10
1593#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000
1594#define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18
1595#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff
1596#define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0
1597#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00
1598#define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8
1599#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000
1600#define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10
1601#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000
1602#define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18
1603#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff
1604#define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0
1605#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00
1606#define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8
1607#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000
1608#define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10
1609#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000
1610#define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18
1611#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff
1612#define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0
1613#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00
1614#define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8
1615#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000
1616#define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10
1617#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000
1618#define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18
1619#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff
1620#define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0
1621#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00
1622#define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8
1623#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000
1624#define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10
1625#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000
1626#define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18
1627#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff
1628#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0
1629#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00
1630#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8
1631#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000
1632#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10
1633#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000
1634#define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18
1635#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff
1636#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0
1637#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00
1638#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8
1639#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000
1640#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10
1641#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000
1642#define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18
1643#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff
1644#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0
1645#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00
1646#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8
1647#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000
1648#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10
1649#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000
1650#define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18
1651#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff
1652#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0
1653#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00
1654#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8
1655#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000
1656#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10
1657#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000
1658#define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18
1659#define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff
1660#define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0
1661#define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00
1662#define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8
1663#define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000
1664#define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10
1665#define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000
1666#define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18
1667#define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff
1668#define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0
1669#define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00
1670#define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8
1671#define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000
1672#define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10
1673#define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000
1674#define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18
1675#define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff
1676#define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0
1677#define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00
1678#define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8
1679#define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000
1680#define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10
1681#define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000
1682#define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18
1683#define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff
1684#define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0
1685#define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00
1686#define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8
1687#define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000
1688#define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10
1689#define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000
1690#define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18
1691#define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff
1692#define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0
1693#define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00
1694#define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8
1695#define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000
1696#define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10
1697#define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000
1698#define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18
1699#define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff
1700#define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0
1701#define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00
1702#define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8
1703#define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000
1704#define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10
1705#define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000
1706#define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18
1707#define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff
1708#define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0
1709#define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00
1710#define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8
1711#define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000
1712#define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10
1713#define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000
1714#define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18
1715#define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff
1716#define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0
1717#define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00
1718#define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8
1719#define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000
1720#define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10
1721#define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000
1722#define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18
1723#define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff
1724#define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0
1725#define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00
1726#define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8
1727#define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000
1728#define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10
1729#define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000
1730#define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18
1731#define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff
1732#define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0
1733#define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00
1734#define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8
1735#define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000
1736#define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10
1737#define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000
1738#define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18
1739#define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff
1740#define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0
1741#define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00
1742#define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8
1743#define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000
1744#define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10
1745#define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000
1746#define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18
1747#define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff
1748#define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0
1749#define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00
1750#define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8
1751#define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000
1752#define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10
1753#define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000
1754#define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18
1755#define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff
1756#define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0
1757#define DPM_TABLE_88__LinkLevelCount_MASK 0xff00
1758#define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8
1759#define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000
1760#define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10
1761#define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000
1762#define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18
1763#define DPM_TABLE_89__SamuLevelCount_MASK 0xff
1764#define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0
1765#define DPM_TABLE_89__AcpLevelCount_MASK 0xff00
1766#define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8
1767#define DPM_TABLE_89__VceLevelCount_MASK 0xff0000
1768#define DPM_TABLE_89__VceLevelCount__SHIFT 0x10
1769#define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000
1770#define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18
1771#define DPM_TABLE_90__Reserved_0_MASK 0xff
1772#define DPM_TABLE_90__Reserved_0__SHIFT 0x0
1773#define DPM_TABLE_90__ThermOutMode_MASK 0xff00
1774#define DPM_TABLE_90__ThermOutMode__SHIFT 0x8
1775#define DPM_TABLE_90__ThermOutPolarity_MASK 0xff0000
1776#define DPM_TABLE_90__ThermOutPolarity__SHIFT 0x10
1777#define DPM_TABLE_90__ThermOutGpio_MASK 0xff000000
1778#define DPM_TABLE_90__ThermOutGpio__SHIFT 0x18
1779#define DPM_TABLE_91__Reserved_0_MASK 0xffffffff
1780#define DPM_TABLE_91__Reserved_0__SHIFT 0x0
1781#define DPM_TABLE_92__Reserved_1_MASK 0xffffffff
1782#define DPM_TABLE_92__Reserved_1__SHIFT 0x0
1783#define DPM_TABLE_93__Reserved_2_MASK 0xffffffff
1784#define DPM_TABLE_93__Reserved_2__SHIFT 0x0
1785#define DPM_TABLE_94__Reserved_3_MASK 0xffffffff
1786#define DPM_TABLE_94__Reserved_3__SHIFT 0x0
1787#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff
1788#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0
1789#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00
1790#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8
1791#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000
1792#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10
1793#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000
1794#define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18
1795#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
1796#define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
1797#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff
1798#define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
1799#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000
1800#define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10
1801#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000
1802#define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18
1803#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff
1804#define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0
1805#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff
1806#define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0
1807#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff
1808#define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0
1809#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff
1810#define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0
1811#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff
1812#define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0
1813#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff
1814#define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0
1815#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff
1816#define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0
1817#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00
1818#define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8
1819#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000
1820#define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10
1821#define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000
1822#define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18
1823#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff
1824#define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0
1825#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00
1826#define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8
1827#define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000
1828#define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10
1829#define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000
1830#define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18
1831#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff
1832#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0
1833#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00
1834#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8
1835#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000
1836#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10
1837#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000
1838#define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18
1839#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
1840#define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
1841#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff
1842#define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
1843#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000
1844#define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10
1845#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000
1846#define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18
1847#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff
1848#define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0
1849#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff
1850#define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0
1851#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff
1852#define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0
1853#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff
1854#define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0
1855#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff
1856#define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0
1857#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff
1858#define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0
1859#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff
1860#define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0
1861#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00
1862#define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8
1863#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000
1864#define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10
1865#define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000
1866#define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18
1867#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff
1868#define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0
1869#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00
1870#define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8
1871#define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000
1872#define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10
1873#define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000
1874#define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18
1875#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff
1876#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0
1877#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00
1878#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8
1879#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000
1880#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10
1881#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000
1882#define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18
1883#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
1884#define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
1885#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff
1886#define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
1887#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000
1888#define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10
1889#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000
1890#define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18
1891#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff
1892#define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0
1893#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff
1894#define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0
1895#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff
1896#define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0
1897#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff
1898#define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0
1899#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff
1900#define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0
1901#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff
1902#define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0
1903#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff
1904#define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0
1905#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00
1906#define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8
1907#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000
1908#define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10
1909#define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000
1910#define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18
1911#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff
1912#define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0
1913#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00
1914#define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8
1915#define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000
1916#define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10
1917#define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000
1918#define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18
1919#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff
1920#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0
1921#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00
1922#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8
1923#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000
1924#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10
1925#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000
1926#define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18
1927#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
1928#define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
1929#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff
1930#define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
1931#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000
1932#define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10
1933#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000
1934#define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18
1935#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff
1936#define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0
1937#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff
1938#define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0
1939#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff
1940#define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0
1941#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff
1942#define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0
1943#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff
1944#define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0
1945#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff
1946#define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0
1947#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff
1948#define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0
1949#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00
1950#define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8
1951#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000
1952#define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10
1953#define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000
1954#define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18
1955#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff
1956#define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0
1957#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00
1958#define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8
1959#define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000
1960#define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10
1961#define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000
1962#define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18
1963#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff
1964#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0
1965#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00
1966#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8
1967#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000
1968#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10
1969#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000
1970#define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18
1971#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
1972#define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
1973#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff
1974#define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
1975#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000
1976#define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10
1977#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000
1978#define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18
1979#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff
1980#define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0
1981#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff
1982#define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0
1983#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff
1984#define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0
1985#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff
1986#define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0
1987#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff
1988#define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0
1989#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff
1990#define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0
1991#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff
1992#define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0
1993#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00
1994#define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8
1995#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000
1996#define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10
1997#define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000
1998#define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18
1999#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff
2000#define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0
2001#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00
2002#define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8
2003#define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000
2004#define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10
2005#define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000
2006#define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18
2007#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff
2008#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0
2009#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00
2010#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8
2011#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000
2012#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10
2013#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000
2014#define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18
2015#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
2016#define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
2017#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff
2018#define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
2019#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000
2020#define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10
2021#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000
2022#define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18
2023#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff
2024#define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0
2025#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff
2026#define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0
2027#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff
2028#define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0
2029#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff
2030#define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0
2031#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff
2032#define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0
2033#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff
2034#define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0
2035#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff
2036#define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0
2037#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00
2038#define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8
2039#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000
2040#define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10
2041#define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000
2042#define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18
2043#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff
2044#define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0
2045#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00
2046#define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8
2047#define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000
2048#define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10
2049#define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000
2050#define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18
2051#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff
2052#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0
2053#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00
2054#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8
2055#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000
2056#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10
2057#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000
2058#define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18
2059#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
2060#define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
2061#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff
2062#define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
2063#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000
2064#define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10
2065#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000
2066#define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18
2067#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff
2068#define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0
2069#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff
2070#define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0
2071#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff
2072#define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0
2073#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff
2074#define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0
2075#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff
2076#define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0
2077#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff
2078#define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0
2079#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff
2080#define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0
2081#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00
2082#define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8
2083#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000
2084#define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10
2085#define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000
2086#define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18
2087#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff
2088#define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0
2089#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00
2090#define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8
2091#define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000
2092#define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10
2093#define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000
2094#define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18
2095#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff
2096#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0
2097#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00
2098#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8
2099#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000
2100#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10
2101#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000
2102#define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18
2103#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
2104#define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
2105#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff
2106#define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
2107#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000
2108#define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10
2109#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000
2110#define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18
2111#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff
2112#define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0
2113#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff
2114#define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0
2115#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff
2116#define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0
2117#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff
2118#define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0
2119#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff
2120#define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0
2121#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff
2122#define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0
2123#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff
2124#define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0
2125#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00
2126#define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8
2127#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000
2128#define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10
2129#define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000
2130#define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18
2131#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff
2132#define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0
2133#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00
2134#define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8
2135#define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000
2136#define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10
2137#define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000
2138#define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18
2139#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff
2140#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0
2141#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00
2142#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8
2143#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000
2144#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10
2145#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000
2146#define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18
2147#define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff
2148#define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0
2149#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff
2150#define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0
2151#define DPM_TABLE_186__MemoryACPILevel_EnabledForActivity_MASK 0xff
2152#define DPM_TABLE_186__MemoryACPILevel_EnabledForActivity__SHIFT 0x0
2153#define DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle_MASK 0xff00
2154#define DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8
2155#define DPM_TABLE_186__MemoryACPILevel_FreqRange_MASK 0xff0000
2156#define DPM_TABLE_186__MemoryACPILevel_FreqRange__SHIFT 0x10
2157#define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff000000
2158#define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x18
2159#define DPM_TABLE_187__MemoryACPILevel_padding_MASK 0xff
2160#define DPM_TABLE_187__MemoryACPILevel_padding__SHIFT 0x0
2161#define DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst_MASK 0xff00
2162#define DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8
2163#define DPM_TABLE_187__MemoryACPILevel_DownHyst_MASK 0xff0000
2164#define DPM_TABLE_187__MemoryACPILevel_DownHyst__SHIFT 0x10
2165#define DPM_TABLE_187__MemoryACPILevel_UpHyst_MASK 0xff000000
2166#define DPM_TABLE_187__MemoryACPILevel_UpHyst__SHIFT 0x18
2167#define DPM_TABLE_188__MemoryACPILevel_MclkDivider_MASK 0xff
2168#define DPM_TABLE_188__MemoryACPILevel_MclkDivider__SHIFT 0x0
2169#define DPM_TABLE_188__MemoryACPILevel_DisplayWatermark_MASK 0xff00
2170#define DPM_TABLE_188__MemoryACPILevel_DisplayWatermark__SHIFT 0x8
2171#define DPM_TABLE_188__MemoryACPILevel_ActivityLevel_MASK 0xffff0000
2172#define DPM_TABLE_188__MemoryACPILevel_ActivityLevel__SHIFT 0x10
2173#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases_MASK 0xff
2174#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0
2175#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00
2176#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8
2177#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000
2178#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10
2179#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000
2180#define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18
2181#define DPM_TABLE_190__MemoryLevel_0_MinMvdd_MASK 0xffffffff
2182#define DPM_TABLE_190__MemoryLevel_0_MinMvdd__SHIFT 0x0
2183#define DPM_TABLE_191__MemoryLevel_0_MclkFrequency_MASK 0xffffffff
2184#define DPM_TABLE_191__MemoryLevel_0_MclkFrequency__SHIFT 0x0
2185#define DPM_TABLE_192__MemoryLevel_0_EnabledForActivity_MASK 0xff
2186#define DPM_TABLE_192__MemoryLevel_0_EnabledForActivity__SHIFT 0x0
2187#define DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle_MASK 0xff00
2188#define DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8
2189#define DPM_TABLE_192__MemoryLevel_0_FreqRange_MASK 0xff0000
2190#define DPM_TABLE_192__MemoryLevel_0_FreqRange__SHIFT 0x10
2191#define DPM_TABLE_192__MemoryLevel_0_StutterEnable_MASK 0xff000000
2192#define DPM_TABLE_192__MemoryLevel_0_StutterEnable__SHIFT 0x18
2193#define DPM_TABLE_193__MemoryLevel_0_padding_MASK 0xff
2194#define DPM_TABLE_193__MemoryLevel_0_padding__SHIFT 0x0
2195#define DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst_MASK 0xff00
2196#define DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8
2197#define DPM_TABLE_193__MemoryLevel_0_DownHyst_MASK 0xff0000
2198#define DPM_TABLE_193__MemoryLevel_0_DownHyst__SHIFT 0x10
2199#define DPM_TABLE_193__MemoryLevel_0_UpHyst_MASK 0xff000000
2200#define DPM_TABLE_193__MemoryLevel_0_UpHyst__SHIFT 0x18
2201#define DPM_TABLE_194__MemoryLevel_0_MclkDivider_MASK 0xff
2202#define DPM_TABLE_194__MemoryLevel_0_MclkDivider__SHIFT 0x0
2203#define DPM_TABLE_194__MemoryLevel_0_DisplayWatermark_MASK 0xff00
2204#define DPM_TABLE_194__MemoryLevel_0_DisplayWatermark__SHIFT 0x8
2205#define DPM_TABLE_194__MemoryLevel_0_ActivityLevel_MASK 0xffff0000
2206#define DPM_TABLE_194__MemoryLevel_0_ActivityLevel__SHIFT 0x10
2207#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases_MASK 0xff
2208#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0
2209#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00
2210#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8
2211#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000
2212#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10
2213#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000
2214#define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18
2215#define DPM_TABLE_196__MemoryLevel_1_MinMvdd_MASK 0xffffffff
2216#define DPM_TABLE_196__MemoryLevel_1_MinMvdd__SHIFT 0x0
2217#define DPM_TABLE_197__MemoryLevel_1_MclkFrequency_MASK 0xffffffff
2218#define DPM_TABLE_197__MemoryLevel_1_MclkFrequency__SHIFT 0x0
2219#define DPM_TABLE_198__MemoryLevel_1_EnabledForActivity_MASK 0xff
2220#define DPM_TABLE_198__MemoryLevel_1_EnabledForActivity__SHIFT 0x0
2221#define DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle_MASK 0xff00
2222#define DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8
2223#define DPM_TABLE_198__MemoryLevel_1_FreqRange_MASK 0xff0000
2224#define DPM_TABLE_198__MemoryLevel_1_FreqRange__SHIFT 0x10
2225#define DPM_TABLE_198__MemoryLevel_1_StutterEnable_MASK 0xff000000
2226#define DPM_TABLE_198__MemoryLevel_1_StutterEnable__SHIFT 0x18
2227#define DPM_TABLE_199__MemoryLevel_1_padding_MASK 0xff
2228#define DPM_TABLE_199__MemoryLevel_1_padding__SHIFT 0x0
2229#define DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst_MASK 0xff00
2230#define DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8
2231#define DPM_TABLE_199__MemoryLevel_1_DownHyst_MASK 0xff0000
2232#define DPM_TABLE_199__MemoryLevel_1_DownHyst__SHIFT 0x10
2233#define DPM_TABLE_199__MemoryLevel_1_UpHyst_MASK 0xff000000
2234#define DPM_TABLE_199__MemoryLevel_1_UpHyst__SHIFT 0x18
2235#define DPM_TABLE_200__MemoryLevel_1_MclkDivider_MASK 0xff
2236#define DPM_TABLE_200__MemoryLevel_1_MclkDivider__SHIFT 0x0
2237#define DPM_TABLE_200__MemoryLevel_1_DisplayWatermark_MASK 0xff00
2238#define DPM_TABLE_200__MemoryLevel_1_DisplayWatermark__SHIFT 0x8
2239#define DPM_TABLE_200__MemoryLevel_1_ActivityLevel_MASK 0xffff0000
2240#define DPM_TABLE_200__MemoryLevel_1_ActivityLevel__SHIFT 0x10
2241#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases_MASK 0xff
2242#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0
2243#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00
2244#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8
2245#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000
2246#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10
2247#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000
2248#define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18
2249#define DPM_TABLE_202__MemoryLevel_2_MinMvdd_MASK 0xffffffff
2250#define DPM_TABLE_202__MemoryLevel_2_MinMvdd__SHIFT 0x0
2251#define DPM_TABLE_203__MemoryLevel_2_MclkFrequency_MASK 0xffffffff
2252#define DPM_TABLE_203__MemoryLevel_2_MclkFrequency__SHIFT 0x0
2253#define DPM_TABLE_204__MemoryLevel_2_EnabledForActivity_MASK 0xff
2254#define DPM_TABLE_204__MemoryLevel_2_EnabledForActivity__SHIFT 0x0
2255#define DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle_MASK 0xff00
2256#define DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8
2257#define DPM_TABLE_204__MemoryLevel_2_FreqRange_MASK 0xff0000
2258#define DPM_TABLE_204__MemoryLevel_2_FreqRange__SHIFT 0x10
2259#define DPM_TABLE_204__MemoryLevel_2_StutterEnable_MASK 0xff000000
2260#define DPM_TABLE_204__MemoryLevel_2_StutterEnable__SHIFT 0x18
2261#define DPM_TABLE_205__MemoryLevel_2_padding_MASK 0xff
2262#define DPM_TABLE_205__MemoryLevel_2_padding__SHIFT 0x0
2263#define DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst_MASK 0xff00
2264#define DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8
2265#define DPM_TABLE_205__MemoryLevel_2_DownHyst_MASK 0xff0000
2266#define DPM_TABLE_205__MemoryLevel_2_DownHyst__SHIFT 0x10
2267#define DPM_TABLE_205__MemoryLevel_2_UpHyst_MASK 0xff000000
2268#define DPM_TABLE_205__MemoryLevel_2_UpHyst__SHIFT 0x18
2269#define DPM_TABLE_206__MemoryLevel_2_MclkDivider_MASK 0xff
2270#define DPM_TABLE_206__MemoryLevel_2_MclkDivider__SHIFT 0x0
2271#define DPM_TABLE_206__MemoryLevel_2_DisplayWatermark_MASK 0xff00
2272#define DPM_TABLE_206__MemoryLevel_2_DisplayWatermark__SHIFT 0x8
2273#define DPM_TABLE_206__MemoryLevel_2_ActivityLevel_MASK 0xffff0000
2274#define DPM_TABLE_206__MemoryLevel_2_ActivityLevel__SHIFT 0x10
2275#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases_MASK 0xff
2276#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0
2277#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00
2278#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8
2279#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000
2280#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10
2281#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000
2282#define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18
2283#define DPM_TABLE_208__MemoryLevel_3_MinMvdd_MASK 0xffffffff
2284#define DPM_TABLE_208__MemoryLevel_3_MinMvdd__SHIFT 0x0
2285#define DPM_TABLE_209__MemoryLevel_3_MclkFrequency_MASK 0xffffffff
2286#define DPM_TABLE_209__MemoryLevel_3_MclkFrequency__SHIFT 0x0
2287#define DPM_TABLE_210__MemoryLevel_3_EnabledForActivity_MASK 0xff
2288#define DPM_TABLE_210__MemoryLevel_3_EnabledForActivity__SHIFT 0x0
2289#define DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle_MASK 0xff00
2290#define DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8
2291#define DPM_TABLE_210__MemoryLevel_3_FreqRange_MASK 0xff0000
2292#define DPM_TABLE_210__MemoryLevel_3_FreqRange__SHIFT 0x10
2293#define DPM_TABLE_210__MemoryLevel_3_StutterEnable_MASK 0xff000000
2294#define DPM_TABLE_210__MemoryLevel_3_StutterEnable__SHIFT 0x18
2295#define DPM_TABLE_211__MemoryLevel_3_padding_MASK 0xff
2296#define DPM_TABLE_211__MemoryLevel_3_padding__SHIFT 0x0
2297#define DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst_MASK 0xff00
2298#define DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8
2299#define DPM_TABLE_211__MemoryLevel_3_DownHyst_MASK 0xff0000
2300#define DPM_TABLE_211__MemoryLevel_3_DownHyst__SHIFT 0x10
2301#define DPM_TABLE_211__MemoryLevel_3_UpHyst_MASK 0xff000000
2302#define DPM_TABLE_211__MemoryLevel_3_UpHyst__SHIFT 0x18
2303#define DPM_TABLE_212__MemoryLevel_3_MclkDivider_MASK 0xff
2304#define DPM_TABLE_212__MemoryLevel_3_MclkDivider__SHIFT 0x0
2305#define DPM_TABLE_212__MemoryLevel_3_DisplayWatermark_MASK 0xff00
2306#define DPM_TABLE_212__MemoryLevel_3_DisplayWatermark__SHIFT 0x8
2307#define DPM_TABLE_212__MemoryLevel_3_ActivityLevel_MASK 0xffff0000
2308#define DPM_TABLE_212__MemoryLevel_3_ActivityLevel__SHIFT 0x10
2309#define DPM_TABLE_213__LinkLevel_0_SPC_MASK 0xff
2310#define DPM_TABLE_213__LinkLevel_0_SPC__SHIFT 0x0
2311#define DPM_TABLE_213__LinkLevel_0_EnabledForActivity_MASK 0xff00
2312#define DPM_TABLE_213__LinkLevel_0_EnabledForActivity__SHIFT 0x8
2313#define DPM_TABLE_213__LinkLevel_0_PcieLaneCount_MASK 0xff0000
2314#define DPM_TABLE_213__LinkLevel_0_PcieLaneCount__SHIFT 0x10
2315#define DPM_TABLE_213__LinkLevel_0_PcieGenSpeed_MASK 0xff000000
2316#define DPM_TABLE_213__LinkLevel_0_PcieGenSpeed__SHIFT 0x18
2317#define DPM_TABLE_214__LinkLevel_0_DownThreshold_MASK 0xffffffff
2318#define DPM_TABLE_214__LinkLevel_0_DownThreshold__SHIFT 0x0
2319#define DPM_TABLE_215__LinkLevel_0_UpThreshold_MASK 0xffffffff
2320#define DPM_TABLE_215__LinkLevel_0_UpThreshold__SHIFT 0x0
2321#define DPM_TABLE_216__LinkLevel_0_Reserved_MASK 0xffffffff
2322#define DPM_TABLE_216__LinkLevel_0_Reserved__SHIFT 0x0
2323#define DPM_TABLE_217__LinkLevel_1_SPC_MASK 0xff
2324#define DPM_TABLE_217__LinkLevel_1_SPC__SHIFT 0x0
2325#define DPM_TABLE_217__LinkLevel_1_EnabledForActivity_MASK 0xff00
2326#define DPM_TABLE_217__LinkLevel_1_EnabledForActivity__SHIFT 0x8
2327#define DPM_TABLE_217__LinkLevel_1_PcieLaneCount_MASK 0xff0000
2328#define DPM_TABLE_217__LinkLevel_1_PcieLaneCount__SHIFT 0x10
2329#define DPM_TABLE_217__LinkLevel_1_PcieGenSpeed_MASK 0xff000000
2330#define DPM_TABLE_217__LinkLevel_1_PcieGenSpeed__SHIFT 0x18
2331#define DPM_TABLE_218__LinkLevel_1_DownThreshold_MASK 0xffffffff
2332#define DPM_TABLE_218__LinkLevel_1_DownThreshold__SHIFT 0x0
2333#define DPM_TABLE_219__LinkLevel_1_UpThreshold_MASK 0xffffffff
2334#define DPM_TABLE_219__LinkLevel_1_UpThreshold__SHIFT 0x0
2335#define DPM_TABLE_220__LinkLevel_1_Reserved_MASK 0xffffffff
2336#define DPM_TABLE_220__LinkLevel_1_Reserved__SHIFT 0x0
2337#define DPM_TABLE_221__LinkLevel_2_SPC_MASK 0xff
2338#define DPM_TABLE_221__LinkLevel_2_SPC__SHIFT 0x0
2339#define DPM_TABLE_221__LinkLevel_2_EnabledForActivity_MASK 0xff00
2340#define DPM_TABLE_221__LinkLevel_2_EnabledForActivity__SHIFT 0x8
2341#define DPM_TABLE_221__LinkLevel_2_PcieLaneCount_MASK 0xff0000
2342#define DPM_TABLE_221__LinkLevel_2_PcieLaneCount__SHIFT 0x10
2343#define DPM_TABLE_221__LinkLevel_2_PcieGenSpeed_MASK 0xff000000
2344#define DPM_TABLE_221__LinkLevel_2_PcieGenSpeed__SHIFT 0x18
2345#define DPM_TABLE_222__LinkLevel_2_DownThreshold_MASK 0xffffffff
2346#define DPM_TABLE_222__LinkLevel_2_DownThreshold__SHIFT 0x0
2347#define DPM_TABLE_223__LinkLevel_2_UpThreshold_MASK 0xffffffff
2348#define DPM_TABLE_223__LinkLevel_2_UpThreshold__SHIFT 0x0
2349#define DPM_TABLE_224__LinkLevel_2_Reserved_MASK 0xffffffff
2350#define DPM_TABLE_224__LinkLevel_2_Reserved__SHIFT 0x0
2351#define DPM_TABLE_225__LinkLevel_3_SPC_MASK 0xff
2352#define DPM_TABLE_225__LinkLevel_3_SPC__SHIFT 0x0
2353#define DPM_TABLE_225__LinkLevel_3_EnabledForActivity_MASK 0xff00
2354#define DPM_TABLE_225__LinkLevel_3_EnabledForActivity__SHIFT 0x8
2355#define DPM_TABLE_225__LinkLevel_3_PcieLaneCount_MASK 0xff0000
2356#define DPM_TABLE_225__LinkLevel_3_PcieLaneCount__SHIFT 0x10
2357#define DPM_TABLE_225__LinkLevel_3_PcieGenSpeed_MASK 0xff000000
2358#define DPM_TABLE_225__LinkLevel_3_PcieGenSpeed__SHIFT 0x18
2359#define DPM_TABLE_226__LinkLevel_3_DownThreshold_MASK 0xffffffff
2360#define DPM_TABLE_226__LinkLevel_3_DownThreshold__SHIFT 0x0
2361#define DPM_TABLE_227__LinkLevel_3_UpThreshold_MASK 0xffffffff
2362#define DPM_TABLE_227__LinkLevel_3_UpThreshold__SHIFT 0x0
2363#define DPM_TABLE_228__LinkLevel_3_Reserved_MASK 0xffffffff
2364#define DPM_TABLE_228__LinkLevel_3_Reserved__SHIFT 0x0
2365#define DPM_TABLE_229__LinkLevel_4_SPC_MASK 0xff
2366#define DPM_TABLE_229__LinkLevel_4_SPC__SHIFT 0x0
2367#define DPM_TABLE_229__LinkLevel_4_EnabledForActivity_MASK 0xff00
2368#define DPM_TABLE_229__LinkLevel_4_EnabledForActivity__SHIFT 0x8
2369#define DPM_TABLE_229__LinkLevel_4_PcieLaneCount_MASK 0xff0000
2370#define DPM_TABLE_229__LinkLevel_4_PcieLaneCount__SHIFT 0x10
2371#define DPM_TABLE_229__LinkLevel_4_PcieGenSpeed_MASK 0xff000000
2372#define DPM_TABLE_229__LinkLevel_4_PcieGenSpeed__SHIFT 0x18
2373#define DPM_TABLE_230__LinkLevel_4_DownThreshold_MASK 0xffffffff
2374#define DPM_TABLE_230__LinkLevel_4_DownThreshold__SHIFT 0x0
2375#define DPM_TABLE_231__LinkLevel_4_UpThreshold_MASK 0xffffffff
2376#define DPM_TABLE_231__LinkLevel_4_UpThreshold__SHIFT 0x0
2377#define DPM_TABLE_232__LinkLevel_4_Reserved_MASK 0xffffffff
2378#define DPM_TABLE_232__LinkLevel_4_Reserved__SHIFT 0x0
2379#define DPM_TABLE_233__LinkLevel_5_SPC_MASK 0xff
2380#define DPM_TABLE_233__LinkLevel_5_SPC__SHIFT 0x0
2381#define DPM_TABLE_233__LinkLevel_5_EnabledForActivity_MASK 0xff00
2382#define DPM_TABLE_233__LinkLevel_5_EnabledForActivity__SHIFT 0x8
2383#define DPM_TABLE_233__LinkLevel_5_PcieLaneCount_MASK 0xff0000
2384#define DPM_TABLE_233__LinkLevel_5_PcieLaneCount__SHIFT 0x10
2385#define DPM_TABLE_233__LinkLevel_5_PcieGenSpeed_MASK 0xff000000
2386#define DPM_TABLE_233__LinkLevel_5_PcieGenSpeed__SHIFT 0x18
2387#define DPM_TABLE_234__LinkLevel_5_DownThreshold_MASK 0xffffffff
2388#define DPM_TABLE_234__LinkLevel_5_DownThreshold__SHIFT 0x0
2389#define DPM_TABLE_235__LinkLevel_5_UpThreshold_MASK 0xffffffff
2390#define DPM_TABLE_235__LinkLevel_5_UpThreshold__SHIFT 0x0
2391#define DPM_TABLE_236__LinkLevel_5_Reserved_MASK 0xffffffff
2392#define DPM_TABLE_236__LinkLevel_5_Reserved__SHIFT 0x0
2393#define DPM_TABLE_237__LinkLevel_6_SPC_MASK 0xff
2394#define DPM_TABLE_237__LinkLevel_6_SPC__SHIFT 0x0
2395#define DPM_TABLE_237__LinkLevel_6_EnabledForActivity_MASK 0xff00
2396#define DPM_TABLE_237__LinkLevel_6_EnabledForActivity__SHIFT 0x8
2397#define DPM_TABLE_237__LinkLevel_6_PcieLaneCount_MASK 0xff0000
2398#define DPM_TABLE_237__LinkLevel_6_PcieLaneCount__SHIFT 0x10
2399#define DPM_TABLE_237__LinkLevel_6_PcieGenSpeed_MASK 0xff000000
2400#define DPM_TABLE_237__LinkLevel_6_PcieGenSpeed__SHIFT 0x18
2401#define DPM_TABLE_238__LinkLevel_6_DownThreshold_MASK 0xffffffff
2402#define DPM_TABLE_238__LinkLevel_6_DownThreshold__SHIFT 0x0
2403#define DPM_TABLE_239__LinkLevel_6_UpThreshold_MASK 0xffffffff
2404#define DPM_TABLE_239__LinkLevel_6_UpThreshold__SHIFT 0x0
2405#define DPM_TABLE_240__LinkLevel_6_Reserved_MASK 0xffffffff
2406#define DPM_TABLE_240__LinkLevel_6_Reserved__SHIFT 0x0
2407#define DPM_TABLE_241__LinkLevel_7_SPC_MASK 0xff
2408#define DPM_TABLE_241__LinkLevel_7_SPC__SHIFT 0x0
2409#define DPM_TABLE_241__LinkLevel_7_EnabledForActivity_MASK 0xff00
2410#define DPM_TABLE_241__LinkLevel_7_EnabledForActivity__SHIFT 0x8
2411#define DPM_TABLE_241__LinkLevel_7_PcieLaneCount_MASK 0xff0000
2412#define DPM_TABLE_241__LinkLevel_7_PcieLaneCount__SHIFT 0x10
2413#define DPM_TABLE_241__LinkLevel_7_PcieGenSpeed_MASK 0xff000000
2414#define DPM_TABLE_241__LinkLevel_7_PcieGenSpeed__SHIFT 0x18
2415#define DPM_TABLE_242__LinkLevel_7_DownThreshold_MASK 0xffffffff
2416#define DPM_TABLE_242__LinkLevel_7_DownThreshold__SHIFT 0x0
2417#define DPM_TABLE_243__LinkLevel_7_UpThreshold_MASK 0xffffffff
2418#define DPM_TABLE_243__LinkLevel_7_UpThreshold__SHIFT 0x0
2419#define DPM_TABLE_244__LinkLevel_7_Reserved_MASK 0xffffffff
2420#define DPM_TABLE_244__LinkLevel_7_Reserved__SHIFT 0x0
2421#define DPM_TABLE_245__ACPILevel_Flags_MASK 0xffffffff
2422#define DPM_TABLE_245__ACPILevel_Flags__SHIFT 0x0
2423#define DPM_TABLE_246__ACPILevel_MinVoltage_Phases_MASK 0xff
2424#define DPM_TABLE_246__ACPILevel_MinVoltage_Phases__SHIFT 0x0
2425#define DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx_MASK 0xff00
2426#define DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8
2427#define DPM_TABLE_246__ACPILevel_MinVoltage_Vddci_MASK 0xff0000
2428#define DPM_TABLE_246__ACPILevel_MinVoltage_Vddci__SHIFT 0x10
2429#define DPM_TABLE_246__ACPILevel_MinVoltage_Vddc_MASK 0xff000000
2430#define DPM_TABLE_246__ACPILevel_MinVoltage_Vddc__SHIFT 0x18
2431#define DPM_TABLE_247__ACPILevel_SclkFrequency_MASK 0xffffffff
2432#define DPM_TABLE_247__ACPILevel_SclkFrequency__SHIFT 0x0
2433#define DPM_TABLE_248__ACPILevel_padding_MASK 0xff
2434#define DPM_TABLE_248__ACPILevel_padding__SHIFT 0x0
2435#define DPM_TABLE_248__ACPILevel_DeepSleepDivId_MASK 0xff00
2436#define DPM_TABLE_248__ACPILevel_DeepSleepDivId__SHIFT 0x8
2437#define DPM_TABLE_248__ACPILevel_DisplayWatermark_MASK 0xff0000
2438#define DPM_TABLE_248__ACPILevel_DisplayWatermark__SHIFT 0x10
2439#define DPM_TABLE_248__ACPILevel_SclkDid_MASK 0xff000000
2440#define DPM_TABLE_248__ACPILevel_SclkDid__SHIFT 0x18
2441#define DPM_TABLE_249__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff
2442#define DPM_TABLE_249__ACPILevel_CgSpllFuncCntl__SHIFT 0x0
2443#define DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff
2444#define DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0
2445#define DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff
2446#define DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0
2447#define DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff
2448#define DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0
2449#define DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff
2450#define DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0
2451#define DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff
2452#define DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0
2453#define DPM_TABLE_255__ACPILevel_CcPwrDynRm_MASK 0xffffffff
2454#define DPM_TABLE_255__ACPILevel_CcPwrDynRm__SHIFT 0x0
2455#define DPM_TABLE_256__ACPILevel_CcPwrDynRm1_MASK 0xffffffff
2456#define DPM_TABLE_256__ACPILevel_CcPwrDynRm1__SHIFT 0x0
2457#define DPM_TABLE_257__UvdLevel_0_VclkFrequency_MASK 0xffffffff
2458#define DPM_TABLE_257__UvdLevel_0_VclkFrequency__SHIFT 0x0
2459#define DPM_TABLE_258__UvdLevel_0_DclkFrequency_MASK 0xffffffff
2460#define DPM_TABLE_258__UvdLevel_0_DclkFrequency__SHIFT 0x0
2461#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases_MASK 0xff
2462#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0
2463#define DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00
2464#define DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8
2465#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000
2466#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10
2467#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000
2468#define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18
2469#define DPM_TABLE_260__UvdLevel_0_padding_1_MASK 0xff
2470#define DPM_TABLE_260__UvdLevel_0_padding_1__SHIFT 0x0
2471#define DPM_TABLE_260__UvdLevel_0_padding_0_MASK 0xff00
2472#define DPM_TABLE_260__UvdLevel_0_padding_0__SHIFT 0x8
2473#define DPM_TABLE_260__UvdLevel_0_DclkDivider_MASK 0xff0000
2474#define DPM_TABLE_260__UvdLevel_0_DclkDivider__SHIFT 0x10
2475#define DPM_TABLE_260__UvdLevel_0_VclkDivider_MASK 0xff000000
2476#define DPM_TABLE_260__UvdLevel_0_VclkDivider__SHIFT 0x18
2477#define DPM_TABLE_261__UvdLevel_1_VclkFrequency_MASK 0xffffffff
2478#define DPM_TABLE_261__UvdLevel_1_VclkFrequency__SHIFT 0x0
2479#define DPM_TABLE_262__UvdLevel_1_DclkFrequency_MASK 0xffffffff
2480#define DPM_TABLE_262__UvdLevel_1_DclkFrequency__SHIFT 0x0
2481#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases_MASK 0xff
2482#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0
2483#define DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00
2484#define DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8
2485#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000
2486#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10
2487#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000
2488#define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18
2489#define DPM_TABLE_264__UvdLevel_1_padding_1_MASK 0xff
2490#define DPM_TABLE_264__UvdLevel_1_padding_1__SHIFT 0x0
2491#define DPM_TABLE_264__UvdLevel_1_padding_0_MASK 0xff00
2492#define DPM_TABLE_264__UvdLevel_1_padding_0__SHIFT 0x8
2493#define DPM_TABLE_264__UvdLevel_1_DclkDivider_MASK 0xff0000
2494#define DPM_TABLE_264__UvdLevel_1_DclkDivider__SHIFT 0x10
2495#define DPM_TABLE_264__UvdLevel_1_VclkDivider_MASK 0xff000000
2496#define DPM_TABLE_264__UvdLevel_1_VclkDivider__SHIFT 0x18
2497#define DPM_TABLE_265__UvdLevel_2_VclkFrequency_MASK 0xffffffff
2498#define DPM_TABLE_265__UvdLevel_2_VclkFrequency__SHIFT 0x0
2499#define DPM_TABLE_266__UvdLevel_2_DclkFrequency_MASK 0xffffffff
2500#define DPM_TABLE_266__UvdLevel_2_DclkFrequency__SHIFT 0x0
2501#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases_MASK 0xff
2502#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0
2503#define DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00
2504#define DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8
2505#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000
2506#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10
2507#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000
2508#define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18
2509#define DPM_TABLE_268__UvdLevel_2_padding_1_MASK 0xff
2510#define DPM_TABLE_268__UvdLevel_2_padding_1__SHIFT 0x0
2511#define DPM_TABLE_268__UvdLevel_2_padding_0_MASK 0xff00
2512#define DPM_TABLE_268__UvdLevel_2_padding_0__SHIFT 0x8
2513#define DPM_TABLE_268__UvdLevel_2_DclkDivider_MASK 0xff0000
2514#define DPM_TABLE_268__UvdLevel_2_DclkDivider__SHIFT 0x10
2515#define DPM_TABLE_268__UvdLevel_2_VclkDivider_MASK 0xff000000
2516#define DPM_TABLE_268__UvdLevel_2_VclkDivider__SHIFT 0x18
2517#define DPM_TABLE_269__UvdLevel_3_VclkFrequency_MASK 0xffffffff
2518#define DPM_TABLE_269__UvdLevel_3_VclkFrequency__SHIFT 0x0
2519#define DPM_TABLE_270__UvdLevel_3_DclkFrequency_MASK 0xffffffff
2520#define DPM_TABLE_270__UvdLevel_3_DclkFrequency__SHIFT 0x0
2521#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases_MASK 0xff
2522#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0
2523#define DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00
2524#define DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8
2525#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000
2526#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10
2527#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000
2528#define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18
2529#define DPM_TABLE_272__UvdLevel_3_padding_1_MASK 0xff
2530#define DPM_TABLE_272__UvdLevel_3_padding_1__SHIFT 0x0
2531#define DPM_TABLE_272__UvdLevel_3_padding_0_MASK 0xff00
2532#define DPM_TABLE_272__UvdLevel_3_padding_0__SHIFT 0x8
2533#define DPM_TABLE_272__UvdLevel_3_DclkDivider_MASK 0xff0000
2534#define DPM_TABLE_272__UvdLevel_3_DclkDivider__SHIFT 0x10
2535#define DPM_TABLE_272__UvdLevel_3_VclkDivider_MASK 0xff000000
2536#define DPM_TABLE_272__UvdLevel_3_VclkDivider__SHIFT 0x18
2537#define DPM_TABLE_273__UvdLevel_4_VclkFrequency_MASK 0xffffffff
2538#define DPM_TABLE_273__UvdLevel_4_VclkFrequency__SHIFT 0x0
2539#define DPM_TABLE_274__UvdLevel_4_DclkFrequency_MASK 0xffffffff
2540#define DPM_TABLE_274__UvdLevel_4_DclkFrequency__SHIFT 0x0
2541#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases_MASK 0xff
2542#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0
2543#define DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00
2544#define DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8
2545#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000
2546#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10
2547#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000
2548#define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18
2549#define DPM_TABLE_276__UvdLevel_4_padding_1_MASK 0xff
2550#define DPM_TABLE_276__UvdLevel_4_padding_1__SHIFT 0x0
2551#define DPM_TABLE_276__UvdLevel_4_padding_0_MASK 0xff00
2552#define DPM_TABLE_276__UvdLevel_4_padding_0__SHIFT 0x8
2553#define DPM_TABLE_276__UvdLevel_4_DclkDivider_MASK 0xff0000
2554#define DPM_TABLE_276__UvdLevel_4_DclkDivider__SHIFT 0x10
2555#define DPM_TABLE_276__UvdLevel_4_VclkDivider_MASK 0xff000000
2556#define DPM_TABLE_276__UvdLevel_4_VclkDivider__SHIFT 0x18
2557#define DPM_TABLE_277__UvdLevel_5_VclkFrequency_MASK 0xffffffff
2558#define DPM_TABLE_277__UvdLevel_5_VclkFrequency__SHIFT 0x0
2559#define DPM_TABLE_278__UvdLevel_5_DclkFrequency_MASK 0xffffffff
2560#define DPM_TABLE_278__UvdLevel_5_DclkFrequency__SHIFT 0x0
2561#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases_MASK 0xff
2562#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0
2563#define DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00
2564#define DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8
2565#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000
2566#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10
2567#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000
2568#define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18
2569#define DPM_TABLE_280__UvdLevel_5_padding_1_MASK 0xff
2570#define DPM_TABLE_280__UvdLevel_5_padding_1__SHIFT 0x0
2571#define DPM_TABLE_280__UvdLevel_5_padding_0_MASK 0xff00
2572#define DPM_TABLE_280__UvdLevel_5_padding_0__SHIFT 0x8
2573#define DPM_TABLE_280__UvdLevel_5_DclkDivider_MASK 0xff0000
2574#define DPM_TABLE_280__UvdLevel_5_DclkDivider__SHIFT 0x10
2575#define DPM_TABLE_280__UvdLevel_5_VclkDivider_MASK 0xff000000
2576#define DPM_TABLE_280__UvdLevel_5_VclkDivider__SHIFT 0x18
2577#define DPM_TABLE_281__UvdLevel_6_VclkFrequency_MASK 0xffffffff
2578#define DPM_TABLE_281__UvdLevel_6_VclkFrequency__SHIFT 0x0
2579#define DPM_TABLE_282__UvdLevel_6_DclkFrequency_MASK 0xffffffff
2580#define DPM_TABLE_282__UvdLevel_6_DclkFrequency__SHIFT 0x0
2581#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases_MASK 0xff
2582#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0
2583#define DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00
2584#define DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8
2585#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000
2586#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10
2587#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000
2588#define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18
2589#define DPM_TABLE_284__UvdLevel_6_padding_1_MASK 0xff
2590#define DPM_TABLE_284__UvdLevel_6_padding_1__SHIFT 0x0
2591#define DPM_TABLE_284__UvdLevel_6_padding_0_MASK 0xff00
2592#define DPM_TABLE_284__UvdLevel_6_padding_0__SHIFT 0x8
2593#define DPM_TABLE_284__UvdLevel_6_DclkDivider_MASK 0xff0000
2594#define DPM_TABLE_284__UvdLevel_6_DclkDivider__SHIFT 0x10
2595#define DPM_TABLE_284__UvdLevel_6_VclkDivider_MASK 0xff000000
2596#define DPM_TABLE_284__UvdLevel_6_VclkDivider__SHIFT 0x18
2597#define DPM_TABLE_285__UvdLevel_7_VclkFrequency_MASK 0xffffffff
2598#define DPM_TABLE_285__UvdLevel_7_VclkFrequency__SHIFT 0x0
2599#define DPM_TABLE_286__UvdLevel_7_DclkFrequency_MASK 0xffffffff
2600#define DPM_TABLE_286__UvdLevel_7_DclkFrequency__SHIFT 0x0
2601#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases_MASK 0xff
2602#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0
2603#define DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00
2604#define DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8
2605#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000
2606#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10
2607#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000
2608#define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18
2609#define DPM_TABLE_288__UvdLevel_7_padding_1_MASK 0xff
2610#define DPM_TABLE_288__UvdLevel_7_padding_1__SHIFT 0x0
2611#define DPM_TABLE_288__UvdLevel_7_padding_0_MASK 0xff00
2612#define DPM_TABLE_288__UvdLevel_7_padding_0__SHIFT 0x8
2613#define DPM_TABLE_288__UvdLevel_7_DclkDivider_MASK 0xff0000
2614#define DPM_TABLE_288__UvdLevel_7_DclkDivider__SHIFT 0x10
2615#define DPM_TABLE_288__UvdLevel_7_VclkDivider_MASK 0xff000000
2616#define DPM_TABLE_288__UvdLevel_7_VclkDivider__SHIFT 0x18
2617#define DPM_TABLE_289__VceLevel_0_Frequency_MASK 0xffffffff
2618#define DPM_TABLE_289__VceLevel_0_Frequency__SHIFT 0x0
2619#define DPM_TABLE_290__VceLevel_0_MinVoltage_Phases_MASK 0xff
2620#define DPM_TABLE_290__VceLevel_0_MinVoltage_Phases__SHIFT 0x0
2621#define DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00
2622#define DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8
2623#define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000
2624#define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10
2625#define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000
2626#define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18
2627#define DPM_TABLE_291__VceLevel_0_padding_2_MASK 0xff
2628#define DPM_TABLE_291__VceLevel_0_padding_2__SHIFT 0x0
2629#define DPM_TABLE_291__VceLevel_0_padding_1_MASK 0xff00
2630#define DPM_TABLE_291__VceLevel_0_padding_1__SHIFT 0x8
2631#define DPM_TABLE_291__VceLevel_0_padding_0_MASK 0xff0000
2632#define DPM_TABLE_291__VceLevel_0_padding_0__SHIFT 0x10
2633#define DPM_TABLE_291__VceLevel_0_Divider_MASK 0xff000000
2634#define DPM_TABLE_291__VceLevel_0_Divider__SHIFT 0x18
2635#define DPM_TABLE_292__VceLevel_1_Frequency_MASK 0xffffffff
2636#define DPM_TABLE_292__VceLevel_1_Frequency__SHIFT 0x0
2637#define DPM_TABLE_293__VceLevel_1_MinVoltage_Phases_MASK 0xff
2638#define DPM_TABLE_293__VceLevel_1_MinVoltage_Phases__SHIFT 0x0
2639#define DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00
2640#define DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8
2641#define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000
2642#define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10
2643#define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000
2644#define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18
2645#define DPM_TABLE_294__VceLevel_1_padding_2_MASK 0xff
2646#define DPM_TABLE_294__VceLevel_1_padding_2__SHIFT 0x0
2647#define DPM_TABLE_294__VceLevel_1_padding_1_MASK 0xff00
2648#define DPM_TABLE_294__VceLevel_1_padding_1__SHIFT 0x8
2649#define DPM_TABLE_294__VceLevel_1_padding_0_MASK 0xff0000
2650#define DPM_TABLE_294__VceLevel_1_padding_0__SHIFT 0x10
2651#define DPM_TABLE_294__VceLevel_1_Divider_MASK 0xff000000
2652#define DPM_TABLE_294__VceLevel_1_Divider__SHIFT 0x18
2653#define DPM_TABLE_295__VceLevel_2_Frequency_MASK 0xffffffff
2654#define DPM_TABLE_295__VceLevel_2_Frequency__SHIFT 0x0
2655#define DPM_TABLE_296__VceLevel_2_MinVoltage_Phases_MASK 0xff
2656#define DPM_TABLE_296__VceLevel_2_MinVoltage_Phases__SHIFT 0x0
2657#define DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00
2658#define DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8
2659#define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000
2660#define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10
2661#define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000
2662#define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18
2663#define DPM_TABLE_297__VceLevel_2_padding_2_MASK 0xff
2664#define DPM_TABLE_297__VceLevel_2_padding_2__SHIFT 0x0
2665#define DPM_TABLE_297__VceLevel_2_padding_1_MASK 0xff00
2666#define DPM_TABLE_297__VceLevel_2_padding_1__SHIFT 0x8
2667#define DPM_TABLE_297__VceLevel_2_padding_0_MASK 0xff0000
2668#define DPM_TABLE_297__VceLevel_2_padding_0__SHIFT 0x10
2669#define DPM_TABLE_297__VceLevel_2_Divider_MASK 0xff000000
2670#define DPM_TABLE_297__VceLevel_2_Divider__SHIFT 0x18
2671#define DPM_TABLE_298__VceLevel_3_Frequency_MASK 0xffffffff
2672#define DPM_TABLE_298__VceLevel_3_Frequency__SHIFT 0x0
2673#define DPM_TABLE_299__VceLevel_3_MinVoltage_Phases_MASK 0xff
2674#define DPM_TABLE_299__VceLevel_3_MinVoltage_Phases__SHIFT 0x0
2675#define DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00
2676#define DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8
2677#define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000
2678#define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10
2679#define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000
2680#define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18
2681#define DPM_TABLE_300__VceLevel_3_padding_2_MASK 0xff
2682#define DPM_TABLE_300__VceLevel_3_padding_2__SHIFT 0x0
2683#define DPM_TABLE_300__VceLevel_3_padding_1_MASK 0xff00
2684#define DPM_TABLE_300__VceLevel_3_padding_1__SHIFT 0x8
2685#define DPM_TABLE_300__VceLevel_3_padding_0_MASK 0xff0000
2686#define DPM_TABLE_300__VceLevel_3_padding_0__SHIFT 0x10
2687#define DPM_TABLE_300__VceLevel_3_Divider_MASK 0xff000000
2688#define DPM_TABLE_300__VceLevel_3_Divider__SHIFT 0x18
2689#define DPM_TABLE_301__VceLevel_4_Frequency_MASK 0xffffffff
2690#define DPM_TABLE_301__VceLevel_4_Frequency__SHIFT 0x0
2691#define DPM_TABLE_302__VceLevel_4_MinVoltage_Phases_MASK 0xff
2692#define DPM_TABLE_302__VceLevel_4_MinVoltage_Phases__SHIFT 0x0
2693#define DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00
2694#define DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8
2695#define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000
2696#define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10
2697#define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000
2698#define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18
2699#define DPM_TABLE_303__VceLevel_4_padding_2_MASK 0xff
2700#define DPM_TABLE_303__VceLevel_4_padding_2__SHIFT 0x0
2701#define DPM_TABLE_303__VceLevel_4_padding_1_MASK 0xff00
2702#define DPM_TABLE_303__VceLevel_4_padding_1__SHIFT 0x8
2703#define DPM_TABLE_303__VceLevel_4_padding_0_MASK 0xff0000
2704#define DPM_TABLE_303__VceLevel_4_padding_0__SHIFT 0x10
2705#define DPM_TABLE_303__VceLevel_4_Divider_MASK 0xff000000
2706#define DPM_TABLE_303__VceLevel_4_Divider__SHIFT 0x18
2707#define DPM_TABLE_304__VceLevel_5_Frequency_MASK 0xffffffff
2708#define DPM_TABLE_304__VceLevel_5_Frequency__SHIFT 0x0
2709#define DPM_TABLE_305__VceLevel_5_MinVoltage_Phases_MASK 0xff
2710#define DPM_TABLE_305__VceLevel_5_MinVoltage_Phases__SHIFT 0x0
2711#define DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00
2712#define DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8
2713#define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000
2714#define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10
2715#define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000
2716#define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18
2717#define DPM_TABLE_306__VceLevel_5_padding_2_MASK 0xff
2718#define DPM_TABLE_306__VceLevel_5_padding_2__SHIFT 0x0
2719#define DPM_TABLE_306__VceLevel_5_padding_1_MASK 0xff00
2720#define DPM_TABLE_306__VceLevel_5_padding_1__SHIFT 0x8
2721#define DPM_TABLE_306__VceLevel_5_padding_0_MASK 0xff0000
2722#define DPM_TABLE_306__VceLevel_5_padding_0__SHIFT 0x10
2723#define DPM_TABLE_306__VceLevel_5_Divider_MASK 0xff000000
2724#define DPM_TABLE_306__VceLevel_5_Divider__SHIFT 0x18
2725#define DPM_TABLE_307__VceLevel_6_Frequency_MASK 0xffffffff
2726#define DPM_TABLE_307__VceLevel_6_Frequency__SHIFT 0x0
2727#define DPM_TABLE_308__VceLevel_6_MinVoltage_Phases_MASK 0xff
2728#define DPM_TABLE_308__VceLevel_6_MinVoltage_Phases__SHIFT 0x0
2729#define DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00
2730#define DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8
2731#define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000
2732#define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10
2733#define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000
2734#define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18
2735#define DPM_TABLE_309__VceLevel_6_padding_2_MASK 0xff
2736#define DPM_TABLE_309__VceLevel_6_padding_2__SHIFT 0x0
2737#define DPM_TABLE_309__VceLevel_6_padding_1_MASK 0xff00
2738#define DPM_TABLE_309__VceLevel_6_padding_1__SHIFT 0x8
2739#define DPM_TABLE_309__VceLevel_6_padding_0_MASK 0xff0000
2740#define DPM_TABLE_309__VceLevel_6_padding_0__SHIFT 0x10
2741#define DPM_TABLE_309__VceLevel_6_Divider_MASK 0xff000000
2742#define DPM_TABLE_309__VceLevel_6_Divider__SHIFT 0x18
2743#define DPM_TABLE_310__VceLevel_7_Frequency_MASK 0xffffffff
2744#define DPM_TABLE_310__VceLevel_7_Frequency__SHIFT 0x0
2745#define DPM_TABLE_311__VceLevel_7_MinVoltage_Phases_MASK 0xff
2746#define DPM_TABLE_311__VceLevel_7_MinVoltage_Phases__SHIFT 0x0
2747#define DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00
2748#define DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8
2749#define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000
2750#define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10
2751#define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000
2752#define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18
2753#define DPM_TABLE_312__VceLevel_7_padding_2_MASK 0xff
2754#define DPM_TABLE_312__VceLevel_7_padding_2__SHIFT 0x0
2755#define DPM_TABLE_312__VceLevel_7_padding_1_MASK 0xff00
2756#define DPM_TABLE_312__VceLevel_7_padding_1__SHIFT 0x8
2757#define DPM_TABLE_312__VceLevel_7_padding_0_MASK 0xff0000
2758#define DPM_TABLE_312__VceLevel_7_padding_0__SHIFT 0x10
2759#define DPM_TABLE_312__VceLevel_7_Divider_MASK 0xff000000
2760#define DPM_TABLE_312__VceLevel_7_Divider__SHIFT 0x18
2761#define DPM_TABLE_313__AcpLevel_0_Frequency_MASK 0xffffffff
2762#define DPM_TABLE_313__AcpLevel_0_Frequency__SHIFT 0x0
2763#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases_MASK 0xff
2764#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0
2765#define DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00
2766#define DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8
2767#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000
2768#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10
2769#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000
2770#define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18
2771#define DPM_TABLE_315__AcpLevel_0_padding_2_MASK 0xff
2772#define DPM_TABLE_315__AcpLevel_0_padding_2__SHIFT 0x0
2773#define DPM_TABLE_315__AcpLevel_0_padding_1_MASK 0xff00
2774#define DPM_TABLE_315__AcpLevel_0_padding_1__SHIFT 0x8
2775#define DPM_TABLE_315__AcpLevel_0_padding_0_MASK 0xff0000
2776#define DPM_TABLE_315__AcpLevel_0_padding_0__SHIFT 0x10
2777#define DPM_TABLE_315__AcpLevel_0_Divider_MASK 0xff000000
2778#define DPM_TABLE_315__AcpLevel_0_Divider__SHIFT 0x18
2779#define DPM_TABLE_316__AcpLevel_1_Frequency_MASK 0xffffffff
2780#define DPM_TABLE_316__AcpLevel_1_Frequency__SHIFT 0x0
2781#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases_MASK 0xff
2782#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0
2783#define DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00
2784#define DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8
2785#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000
2786#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10
2787#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000
2788#define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18
2789#define DPM_TABLE_318__AcpLevel_1_padding_2_MASK 0xff
2790#define DPM_TABLE_318__AcpLevel_1_padding_2__SHIFT 0x0
2791#define DPM_TABLE_318__AcpLevel_1_padding_1_MASK 0xff00
2792#define DPM_TABLE_318__AcpLevel_1_padding_1__SHIFT 0x8
2793#define DPM_TABLE_318__AcpLevel_1_padding_0_MASK 0xff0000
2794#define DPM_TABLE_318__AcpLevel_1_padding_0__SHIFT 0x10
2795#define DPM_TABLE_318__AcpLevel_1_Divider_MASK 0xff000000
2796#define DPM_TABLE_318__AcpLevel_1_Divider__SHIFT 0x18
2797#define DPM_TABLE_319__AcpLevel_2_Frequency_MASK 0xffffffff
2798#define DPM_TABLE_319__AcpLevel_2_Frequency__SHIFT 0x0
2799#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases_MASK 0xff
2800#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0
2801#define DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00
2802#define DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8
2803#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000
2804#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10
2805#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000
2806#define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18
2807#define DPM_TABLE_321__AcpLevel_2_padding_2_MASK 0xff
2808#define DPM_TABLE_321__AcpLevel_2_padding_2__SHIFT 0x0
2809#define DPM_TABLE_321__AcpLevel_2_padding_1_MASK 0xff00
2810#define DPM_TABLE_321__AcpLevel_2_padding_1__SHIFT 0x8
2811#define DPM_TABLE_321__AcpLevel_2_padding_0_MASK 0xff0000
2812#define DPM_TABLE_321__AcpLevel_2_padding_0__SHIFT 0x10
2813#define DPM_TABLE_321__AcpLevel_2_Divider_MASK 0xff000000
2814#define DPM_TABLE_321__AcpLevel_2_Divider__SHIFT 0x18
2815#define DPM_TABLE_322__AcpLevel_3_Frequency_MASK 0xffffffff
2816#define DPM_TABLE_322__AcpLevel_3_Frequency__SHIFT 0x0
2817#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases_MASK 0xff
2818#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0
2819#define DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00
2820#define DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8
2821#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000
2822#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10
2823#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000
2824#define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18
2825#define DPM_TABLE_324__AcpLevel_3_padding_2_MASK 0xff
2826#define DPM_TABLE_324__AcpLevel_3_padding_2__SHIFT 0x0
2827#define DPM_TABLE_324__AcpLevel_3_padding_1_MASK 0xff00
2828#define DPM_TABLE_324__AcpLevel_3_padding_1__SHIFT 0x8
2829#define DPM_TABLE_324__AcpLevel_3_padding_0_MASK 0xff0000
2830#define DPM_TABLE_324__AcpLevel_3_padding_0__SHIFT 0x10
2831#define DPM_TABLE_324__AcpLevel_3_Divider_MASK 0xff000000
2832#define DPM_TABLE_324__AcpLevel_3_Divider__SHIFT 0x18
2833#define DPM_TABLE_325__AcpLevel_4_Frequency_MASK 0xffffffff
2834#define DPM_TABLE_325__AcpLevel_4_Frequency__SHIFT 0x0
2835#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases_MASK 0xff
2836#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0
2837#define DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00
2838#define DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8
2839#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000
2840#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10
2841#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000
2842#define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18
2843#define DPM_TABLE_327__AcpLevel_4_padding_2_MASK 0xff
2844#define DPM_TABLE_327__AcpLevel_4_padding_2__SHIFT 0x0
2845#define DPM_TABLE_327__AcpLevel_4_padding_1_MASK 0xff00
2846#define DPM_TABLE_327__AcpLevel_4_padding_1__SHIFT 0x8
2847#define DPM_TABLE_327__AcpLevel_4_padding_0_MASK 0xff0000
2848#define DPM_TABLE_327__AcpLevel_4_padding_0__SHIFT 0x10
2849#define DPM_TABLE_327__AcpLevel_4_Divider_MASK 0xff000000
2850#define DPM_TABLE_327__AcpLevel_4_Divider__SHIFT 0x18
2851#define DPM_TABLE_328__AcpLevel_5_Frequency_MASK 0xffffffff
2852#define DPM_TABLE_328__AcpLevel_5_Frequency__SHIFT 0x0
2853#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases_MASK 0xff
2854#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0
2855#define DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00
2856#define DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8
2857#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000
2858#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10
2859#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000
2860#define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18
2861#define DPM_TABLE_330__AcpLevel_5_padding_2_MASK 0xff
2862#define DPM_TABLE_330__AcpLevel_5_padding_2__SHIFT 0x0
2863#define DPM_TABLE_330__AcpLevel_5_padding_1_MASK 0xff00
2864#define DPM_TABLE_330__AcpLevel_5_padding_1__SHIFT 0x8
2865#define DPM_TABLE_330__AcpLevel_5_padding_0_MASK 0xff0000
2866#define DPM_TABLE_330__AcpLevel_5_padding_0__SHIFT 0x10
2867#define DPM_TABLE_330__AcpLevel_5_Divider_MASK 0xff000000
2868#define DPM_TABLE_330__AcpLevel_5_Divider__SHIFT 0x18
2869#define DPM_TABLE_331__AcpLevel_6_Frequency_MASK 0xffffffff
2870#define DPM_TABLE_331__AcpLevel_6_Frequency__SHIFT 0x0
2871#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases_MASK 0xff
2872#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0
2873#define DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00
2874#define DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8
2875#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000
2876#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10
2877#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000
2878#define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18
2879#define DPM_TABLE_333__AcpLevel_6_padding_2_MASK 0xff
2880#define DPM_TABLE_333__AcpLevel_6_padding_2__SHIFT 0x0
2881#define DPM_TABLE_333__AcpLevel_6_padding_1_MASK 0xff00
2882#define DPM_TABLE_333__AcpLevel_6_padding_1__SHIFT 0x8
2883#define DPM_TABLE_333__AcpLevel_6_padding_0_MASK 0xff0000
2884#define DPM_TABLE_333__AcpLevel_6_padding_0__SHIFT 0x10
2885#define DPM_TABLE_333__AcpLevel_6_Divider_MASK 0xff000000
2886#define DPM_TABLE_333__AcpLevel_6_Divider__SHIFT 0x18
2887#define DPM_TABLE_334__AcpLevel_7_Frequency_MASK 0xffffffff
2888#define DPM_TABLE_334__AcpLevel_7_Frequency__SHIFT 0x0
2889#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases_MASK 0xff
2890#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0
2891#define DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00
2892#define DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8
2893#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000
2894#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10
2895#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000
2896#define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18
2897#define DPM_TABLE_336__AcpLevel_7_padding_2_MASK 0xff
2898#define DPM_TABLE_336__AcpLevel_7_padding_2__SHIFT 0x0
2899#define DPM_TABLE_336__AcpLevel_7_padding_1_MASK 0xff00
2900#define DPM_TABLE_336__AcpLevel_7_padding_1__SHIFT 0x8
2901#define DPM_TABLE_336__AcpLevel_7_padding_0_MASK 0xff0000
2902#define DPM_TABLE_336__AcpLevel_7_padding_0__SHIFT 0x10
2903#define DPM_TABLE_336__AcpLevel_7_Divider_MASK 0xff000000
2904#define DPM_TABLE_336__AcpLevel_7_Divider__SHIFT 0x18
2905#define DPM_TABLE_337__SamuLevel_0_Frequency_MASK 0xffffffff
2906#define DPM_TABLE_337__SamuLevel_0_Frequency__SHIFT 0x0
2907#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases_MASK 0xff
2908#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0
2909#define DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00
2910#define DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8
2911#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000
2912#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10
2913#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000
2914#define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18
2915#define DPM_TABLE_339__SamuLevel_0_padding_2_MASK 0xff
2916#define DPM_TABLE_339__SamuLevel_0_padding_2__SHIFT 0x0
2917#define DPM_TABLE_339__SamuLevel_0_padding_1_MASK 0xff00
2918#define DPM_TABLE_339__SamuLevel_0_padding_1__SHIFT 0x8
2919#define DPM_TABLE_339__SamuLevel_0_padding_0_MASK 0xff0000
2920#define DPM_TABLE_339__SamuLevel_0_padding_0__SHIFT 0x10
2921#define DPM_TABLE_339__SamuLevel_0_Divider_MASK 0xff000000
2922#define DPM_TABLE_339__SamuLevel_0_Divider__SHIFT 0x18
2923#define DPM_TABLE_340__SamuLevel_1_Frequency_MASK 0xffffffff
2924#define DPM_TABLE_340__SamuLevel_1_Frequency__SHIFT 0x0
2925#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases_MASK 0xff
2926#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0
2927#define DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00
2928#define DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8
2929#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000
2930#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10
2931#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000
2932#define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18
2933#define DPM_TABLE_342__SamuLevel_1_padding_2_MASK 0xff
2934#define DPM_TABLE_342__SamuLevel_1_padding_2__SHIFT 0x0
2935#define DPM_TABLE_342__SamuLevel_1_padding_1_MASK 0xff00
2936#define DPM_TABLE_342__SamuLevel_1_padding_1__SHIFT 0x8
2937#define DPM_TABLE_342__SamuLevel_1_padding_0_MASK 0xff0000
2938#define DPM_TABLE_342__SamuLevel_1_padding_0__SHIFT 0x10
2939#define DPM_TABLE_342__SamuLevel_1_Divider_MASK 0xff000000
2940#define DPM_TABLE_342__SamuLevel_1_Divider__SHIFT 0x18
2941#define DPM_TABLE_343__SamuLevel_2_Frequency_MASK 0xffffffff
2942#define DPM_TABLE_343__SamuLevel_2_Frequency__SHIFT 0x0
2943#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases_MASK 0xff
2944#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0
2945#define DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00
2946#define DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8
2947#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000
2948#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10
2949#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000
2950#define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18
2951#define DPM_TABLE_345__SamuLevel_2_padding_2_MASK 0xff
2952#define DPM_TABLE_345__SamuLevel_2_padding_2__SHIFT 0x0
2953#define DPM_TABLE_345__SamuLevel_2_padding_1_MASK 0xff00
2954#define DPM_TABLE_345__SamuLevel_2_padding_1__SHIFT 0x8
2955#define DPM_TABLE_345__SamuLevel_2_padding_0_MASK 0xff0000
2956#define DPM_TABLE_345__SamuLevel_2_padding_0__SHIFT 0x10
2957#define DPM_TABLE_345__SamuLevel_2_Divider_MASK 0xff000000
2958#define DPM_TABLE_345__SamuLevel_2_Divider__SHIFT 0x18
2959#define DPM_TABLE_346__SamuLevel_3_Frequency_MASK 0xffffffff
2960#define DPM_TABLE_346__SamuLevel_3_Frequency__SHIFT 0x0
2961#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases_MASK 0xff
2962#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0
2963#define DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00
2964#define DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8
2965#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000
2966#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10
2967#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000
2968#define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18
2969#define DPM_TABLE_348__SamuLevel_3_padding_2_MASK 0xff
2970#define DPM_TABLE_348__SamuLevel_3_padding_2__SHIFT 0x0
2971#define DPM_TABLE_348__SamuLevel_3_padding_1_MASK 0xff00
2972#define DPM_TABLE_348__SamuLevel_3_padding_1__SHIFT 0x8
2973#define DPM_TABLE_348__SamuLevel_3_padding_0_MASK 0xff0000
2974#define DPM_TABLE_348__SamuLevel_3_padding_0__SHIFT 0x10
2975#define DPM_TABLE_348__SamuLevel_3_Divider_MASK 0xff000000
2976#define DPM_TABLE_348__SamuLevel_3_Divider__SHIFT 0x18
2977#define DPM_TABLE_349__SamuLevel_4_Frequency_MASK 0xffffffff
2978#define DPM_TABLE_349__SamuLevel_4_Frequency__SHIFT 0x0
2979#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases_MASK 0xff
2980#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0
2981#define DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00
2982#define DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8
2983#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000
2984#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10
2985#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000
2986#define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18
2987#define DPM_TABLE_351__SamuLevel_4_padding_2_MASK 0xff
2988#define DPM_TABLE_351__SamuLevel_4_padding_2__SHIFT 0x0
2989#define DPM_TABLE_351__SamuLevel_4_padding_1_MASK 0xff00
2990#define DPM_TABLE_351__SamuLevel_4_padding_1__SHIFT 0x8
2991#define DPM_TABLE_351__SamuLevel_4_padding_0_MASK 0xff0000
2992#define DPM_TABLE_351__SamuLevel_4_padding_0__SHIFT 0x10
2993#define DPM_TABLE_351__SamuLevel_4_Divider_MASK 0xff000000
2994#define DPM_TABLE_351__SamuLevel_4_Divider__SHIFT 0x18
2995#define DPM_TABLE_352__SamuLevel_5_Frequency_MASK 0xffffffff
2996#define DPM_TABLE_352__SamuLevel_5_Frequency__SHIFT 0x0
2997#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases_MASK 0xff
2998#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0
2999#define DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00
3000#define DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8
3001#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000
3002#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10
3003#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000
3004#define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18
3005#define DPM_TABLE_354__SamuLevel_5_padding_2_MASK 0xff
3006#define DPM_TABLE_354__SamuLevel_5_padding_2__SHIFT 0x0
3007#define DPM_TABLE_354__SamuLevel_5_padding_1_MASK 0xff00
3008#define DPM_TABLE_354__SamuLevel_5_padding_1__SHIFT 0x8
3009#define DPM_TABLE_354__SamuLevel_5_padding_0_MASK 0xff0000
3010#define DPM_TABLE_354__SamuLevel_5_padding_0__SHIFT 0x10
3011#define DPM_TABLE_354__SamuLevel_5_Divider_MASK 0xff000000
3012#define DPM_TABLE_354__SamuLevel_5_Divider__SHIFT 0x18
3013#define DPM_TABLE_355__SamuLevel_6_Frequency_MASK 0xffffffff
3014#define DPM_TABLE_355__SamuLevel_6_Frequency__SHIFT 0x0
3015#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases_MASK 0xff
3016#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0
3017#define DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00
3018#define DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8
3019#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000
3020#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10
3021#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000
3022#define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18
3023#define DPM_TABLE_357__SamuLevel_6_padding_2_MASK 0xff
3024#define DPM_TABLE_357__SamuLevel_6_padding_2__SHIFT 0x0
3025#define DPM_TABLE_357__SamuLevel_6_padding_1_MASK 0xff00
3026#define DPM_TABLE_357__SamuLevel_6_padding_1__SHIFT 0x8
3027#define DPM_TABLE_357__SamuLevel_6_padding_0_MASK 0xff0000
3028#define DPM_TABLE_357__SamuLevel_6_padding_0__SHIFT 0x10
3029#define DPM_TABLE_357__SamuLevel_6_Divider_MASK 0xff000000
3030#define DPM_TABLE_357__SamuLevel_6_Divider__SHIFT 0x18
3031#define DPM_TABLE_358__SamuLevel_7_Frequency_MASK 0xffffffff
3032#define DPM_TABLE_358__SamuLevel_7_Frequency__SHIFT 0x0
3033#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases_MASK 0xff
3034#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0
3035#define DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00
3036#define DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8
3037#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000
3038#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10
3039#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000
3040#define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18
3041#define DPM_TABLE_360__SamuLevel_7_padding_2_MASK 0xff
3042#define DPM_TABLE_360__SamuLevel_7_padding_2__SHIFT 0x0
3043#define DPM_TABLE_360__SamuLevel_7_padding_1_MASK 0xff00
3044#define DPM_TABLE_360__SamuLevel_7_padding_1__SHIFT 0x8
3045#define DPM_TABLE_360__SamuLevel_7_padding_0_MASK 0xff0000
3046#define DPM_TABLE_360__SamuLevel_7_padding_0__SHIFT 0x10
3047#define DPM_TABLE_360__SamuLevel_7_Divider_MASK 0xff000000
3048#define DPM_TABLE_360__SamuLevel_7_Divider__SHIFT 0x18
3049#define DPM_TABLE_361__Ulv_CcPwrDynRm_MASK 0xffffffff
3050#define DPM_TABLE_361__Ulv_CcPwrDynRm__SHIFT 0x0
3051#define DPM_TABLE_362__Ulv_CcPwrDynRm1_MASK 0xffffffff
3052#define DPM_TABLE_362__Ulv_CcPwrDynRm1__SHIFT 0x0
3053#define DPM_TABLE_363__Ulv_VddcPhase_MASK 0xff
3054#define DPM_TABLE_363__Ulv_VddcPhase__SHIFT 0x0
3055#define DPM_TABLE_363__Ulv_VddcOffsetVid_MASK 0xff00
3056#define DPM_TABLE_363__Ulv_VddcOffsetVid__SHIFT 0x8
3057#define DPM_TABLE_363__Ulv_VddcOffset_MASK 0xffff0000
3058#define DPM_TABLE_363__Ulv_VddcOffset__SHIFT 0x10
3059#define DPM_TABLE_364__Ulv_Reserved_MASK 0xffffffff
3060#define DPM_TABLE_364__Ulv_Reserved__SHIFT 0x0
3061#define DPM_TABLE_365__SclkStepSize_MASK 0xffffffff
3062#define DPM_TABLE_365__SclkStepSize__SHIFT 0x0
3063#define DPM_TABLE_366__Smio_0_MASK 0xffffffff
3064#define DPM_TABLE_366__Smio_0__SHIFT 0x0
3065#define DPM_TABLE_367__Smio_1_MASK 0xffffffff
3066#define DPM_TABLE_367__Smio_1__SHIFT 0x0
3067#define DPM_TABLE_368__Smio_2_MASK 0xffffffff
3068#define DPM_TABLE_368__Smio_2__SHIFT 0x0
3069#define DPM_TABLE_369__Smio_3_MASK 0xffffffff
3070#define DPM_TABLE_369__Smio_3__SHIFT 0x0
3071#define DPM_TABLE_370__Smio_4_MASK 0xffffffff
3072#define DPM_TABLE_370__Smio_4__SHIFT 0x0
3073#define DPM_TABLE_371__Smio_5_MASK 0xffffffff
3074#define DPM_TABLE_371__Smio_5__SHIFT 0x0
3075#define DPM_TABLE_372__Smio_6_MASK 0xffffffff
3076#define DPM_TABLE_372__Smio_6__SHIFT 0x0
3077#define DPM_TABLE_373__Smio_7_MASK 0xffffffff
3078#define DPM_TABLE_373__Smio_7__SHIFT 0x0
3079#define DPM_TABLE_374__Smio_8_MASK 0xffffffff
3080#define DPM_TABLE_374__Smio_8__SHIFT 0x0
3081#define DPM_TABLE_375__Smio_9_MASK 0xffffffff
3082#define DPM_TABLE_375__Smio_9__SHIFT 0x0
3083#define DPM_TABLE_376__Smio_10_MASK 0xffffffff
3084#define DPM_TABLE_376__Smio_10__SHIFT 0x0
3085#define DPM_TABLE_377__Smio_11_MASK 0xffffffff
3086#define DPM_TABLE_377__Smio_11__SHIFT 0x0
3087#define DPM_TABLE_378__Smio_12_MASK 0xffffffff
3088#define DPM_TABLE_378__Smio_12__SHIFT 0x0
3089#define DPM_TABLE_379__Smio_13_MASK 0xffffffff
3090#define DPM_TABLE_379__Smio_13__SHIFT 0x0
3091#define DPM_TABLE_380__Smio_14_MASK 0xffffffff
3092#define DPM_TABLE_380__Smio_14__SHIFT 0x0
3093#define DPM_TABLE_381__Smio_15_MASK 0xffffffff
3094#define DPM_TABLE_381__Smio_15__SHIFT 0x0
3095#define DPM_TABLE_382__Smio_16_MASK 0xffffffff
3096#define DPM_TABLE_382__Smio_16__SHIFT 0x0
3097#define DPM_TABLE_383__Smio_17_MASK 0xffffffff
3098#define DPM_TABLE_383__Smio_17__SHIFT 0x0
3099#define DPM_TABLE_384__Smio_18_MASK 0xffffffff
3100#define DPM_TABLE_384__Smio_18__SHIFT 0x0
3101#define DPM_TABLE_385__Smio_19_MASK 0xffffffff
3102#define DPM_TABLE_385__Smio_19__SHIFT 0x0
3103#define DPM_TABLE_386__Smio_20_MASK 0xffffffff
3104#define DPM_TABLE_386__Smio_20__SHIFT 0x0
3105#define DPM_TABLE_387__Smio_21_MASK 0xffffffff
3106#define DPM_TABLE_387__Smio_21__SHIFT 0x0
3107#define DPM_TABLE_388__Smio_22_MASK 0xffffffff
3108#define DPM_TABLE_388__Smio_22__SHIFT 0x0
3109#define DPM_TABLE_389__Smio_23_MASK 0xffffffff
3110#define DPM_TABLE_389__Smio_23__SHIFT 0x0
3111#define DPM_TABLE_390__Smio_24_MASK 0xffffffff
3112#define DPM_TABLE_390__Smio_24__SHIFT 0x0
3113#define DPM_TABLE_391__Smio_25_MASK 0xffffffff
3114#define DPM_TABLE_391__Smio_25__SHIFT 0x0
3115#define DPM_TABLE_392__Smio_26_MASK 0xffffffff
3116#define DPM_TABLE_392__Smio_26__SHIFT 0x0
3117#define DPM_TABLE_393__Smio_27_MASK 0xffffffff
3118#define DPM_TABLE_393__Smio_27__SHIFT 0x0
3119#define DPM_TABLE_394__Smio_28_MASK 0xffffffff
3120#define DPM_TABLE_394__Smio_28__SHIFT 0x0
3121#define DPM_TABLE_395__Smio_29_MASK 0xffffffff
3122#define DPM_TABLE_395__Smio_29__SHIFT 0x0
3123#define DPM_TABLE_396__Smio_30_MASK 0xffffffff
3124#define DPM_TABLE_396__Smio_30__SHIFT 0x0
3125#define DPM_TABLE_397__Smio_31_MASK 0xffffffff
3126#define DPM_TABLE_397__Smio_31__SHIFT 0x0
3127#define DPM_TABLE_398__SamuBootLevel_MASK 0xff
3128#define DPM_TABLE_398__SamuBootLevel__SHIFT 0x0
3129#define DPM_TABLE_398__AcpBootLevel_MASK 0xff00
3130#define DPM_TABLE_398__AcpBootLevel__SHIFT 0x8
3131#define DPM_TABLE_398__VceBootLevel_MASK 0xff0000
3132#define DPM_TABLE_398__VceBootLevel__SHIFT 0x10
3133#define DPM_TABLE_398__UvdBootLevel_MASK 0xff000000
3134#define DPM_TABLE_398__UvdBootLevel__SHIFT 0x18
3135#define DPM_TABLE_399__GraphicsInterval_MASK 0xff
3136#define DPM_TABLE_399__GraphicsInterval__SHIFT 0x0
3137#define DPM_TABLE_399__GraphicsThermThrottleEnable_MASK 0xff00
3138#define DPM_TABLE_399__GraphicsThermThrottleEnable__SHIFT 0x8
3139#define DPM_TABLE_399__GraphicsVoltageChangeEnable_MASK 0xff0000
3140#define DPM_TABLE_399__GraphicsVoltageChangeEnable__SHIFT 0x10
3141#define DPM_TABLE_399__GraphicsBootLevel_MASK 0xff000000
3142#define DPM_TABLE_399__GraphicsBootLevel__SHIFT 0x18
3143#define DPM_TABLE_400__TemperatureLimitHigh_MASK 0xffff
3144#define DPM_TABLE_400__TemperatureLimitHigh__SHIFT 0x0
3145#define DPM_TABLE_400__ThermalInterval_MASK 0xff0000
3146#define DPM_TABLE_400__ThermalInterval__SHIFT 0x10
3147#define DPM_TABLE_400__VoltageInterval_MASK 0xff000000
3148#define DPM_TABLE_400__VoltageInterval__SHIFT 0x18
3149#define DPM_TABLE_401__MemoryVoltageChangeEnable_MASK 0xff
3150#define DPM_TABLE_401__MemoryVoltageChangeEnable__SHIFT 0x0
3151#define DPM_TABLE_401__MemoryBootLevel_MASK 0xff00
3152#define DPM_TABLE_401__MemoryBootLevel__SHIFT 0x8
3153#define DPM_TABLE_401__TemperatureLimitLow_MASK 0xffff0000
3154#define DPM_TABLE_401__TemperatureLimitLow__SHIFT 0x10
3155#define DPM_TABLE_402__MemoryThermThrottleEnable_MASK 0xff
3156#define DPM_TABLE_402__MemoryThermThrottleEnable__SHIFT 0x0
3157#define DPM_TABLE_402__MemoryInterval_MASK 0xff00
3158#define DPM_TABLE_402__MemoryInterval__SHIFT 0x8
3159#define DPM_TABLE_402__BootMVdd_MASK 0xffff0000
3160#define DPM_TABLE_402__BootMVdd__SHIFT 0x10
3161#define DPM_TABLE_403__PhaseResponseTime_MASK 0xffff
3162#define DPM_TABLE_403__PhaseResponseTime__SHIFT 0x0
3163#define DPM_TABLE_403__VoltageResponseTime_MASK 0xffff0000
3164#define DPM_TABLE_403__VoltageResponseTime__SHIFT 0x10
3165#define DPM_TABLE_404__DTEMode_MASK 0xff
3166#define DPM_TABLE_404__DTEMode__SHIFT 0x0
3167#define DPM_TABLE_404__DTEInterval_MASK 0xff00
3168#define DPM_TABLE_404__DTEInterval__SHIFT 0x8
3169#define DPM_TABLE_404__PCIeGenInterval_MASK 0xff0000
3170#define DPM_TABLE_404__PCIeGenInterval__SHIFT 0x10
3171#define DPM_TABLE_404__PCIeBootLinkLevel_MASK 0xff000000
3172#define DPM_TABLE_404__PCIeBootLinkLevel__SHIFT 0x18
3173#define DPM_TABLE_405__ThermGpio_MASK 0xff
3174#define DPM_TABLE_405__ThermGpio__SHIFT 0x0
3175#define DPM_TABLE_405__AcDcGpio_MASK 0xff00
3176#define DPM_TABLE_405__AcDcGpio__SHIFT 0x8
3177#define DPM_TABLE_405__VRHotGpio_MASK 0xff0000
3178#define DPM_TABLE_405__VRHotGpio__SHIFT 0x10
3179#define DPM_TABLE_405__SVI2Enable_MASK 0xff000000
3180#define DPM_TABLE_405__SVI2Enable__SHIFT 0x18
3181#define DPM_TABLE_406__PPM_TemperatureLimit_MASK 0xffff
3182#define DPM_TABLE_406__PPM_TemperatureLimit__SHIFT 0x0
3183#define DPM_TABLE_406__PPM_PkgPwrLimit_MASK 0xffff0000
3184#define DPM_TABLE_406__PPM_PkgPwrLimit__SHIFT 0x10
3185#define DPM_TABLE_407__TargetTdp_MASK 0xffff
3186#define DPM_TABLE_407__TargetTdp__SHIFT 0x0
3187#define DPM_TABLE_407__DefaultTdp_MASK 0xffff0000
3188#define DPM_TABLE_407__DefaultTdp__SHIFT 0x10
3189#define DPM_TABLE_408__FpsLowThreshold_MASK 0xffff
3190#define DPM_TABLE_408__FpsLowThreshold__SHIFT 0x0
3191#define DPM_TABLE_408__FpsHighThreshold_MASK 0xffff0000
3192#define DPM_TABLE_408__FpsHighThreshold__SHIFT 0x10
3193#define DPM_TABLE_409__BAPMTI_R_0_1_0_MASK 0xffff
3194#define DPM_TABLE_409__BAPMTI_R_0_1_0__SHIFT 0x0
3195#define DPM_TABLE_409__BAPMTI_R_0_0_0_MASK 0xffff0000
3196#define DPM_TABLE_409__BAPMTI_R_0_0_0__SHIFT 0x10
3197#define DPM_TABLE_410__BAPMTI_R_1_0_0_MASK 0xffff
3198#define DPM_TABLE_410__BAPMTI_R_1_0_0__SHIFT 0x0
3199#define DPM_TABLE_410__BAPMTI_R_0_2_0_MASK 0xffff0000
3200#define DPM_TABLE_410__BAPMTI_R_0_2_0__SHIFT 0x10
3201#define DPM_TABLE_411__BAPMTI_R_1_2_0_MASK 0xffff
3202#define DPM_TABLE_411__BAPMTI_R_1_2_0__SHIFT 0x0
3203#define DPM_TABLE_411__BAPMTI_R_1_1_0_MASK 0xffff0000
3204#define DPM_TABLE_411__BAPMTI_R_1_1_0__SHIFT 0x10
3205#define DPM_TABLE_412__BAPMTI_R_2_1_0_MASK 0xffff
3206#define DPM_TABLE_412__BAPMTI_R_2_1_0__SHIFT 0x0
3207#define DPM_TABLE_412__BAPMTI_R_2_0_0_MASK 0xffff0000
3208#define DPM_TABLE_412__BAPMTI_R_2_0_0__SHIFT 0x10
3209#define DPM_TABLE_413__BAPMTI_R_3_0_0_MASK 0xffff
3210#define DPM_TABLE_413__BAPMTI_R_3_0_0__SHIFT 0x0
3211#define DPM_TABLE_413__BAPMTI_R_2_2_0_MASK 0xffff0000
3212#define DPM_TABLE_413__BAPMTI_R_2_2_0__SHIFT 0x10
3213#define DPM_TABLE_414__BAPMTI_R_3_2_0_MASK 0xffff
3214#define DPM_TABLE_414__BAPMTI_R_3_2_0__SHIFT 0x0
3215#define DPM_TABLE_414__BAPMTI_R_3_1_0_MASK 0xffff0000
3216#define DPM_TABLE_414__BAPMTI_R_3_1_0__SHIFT 0x10
3217#define DPM_TABLE_415__BAPMTI_R_4_1_0_MASK 0xffff
3218#define DPM_TABLE_415__BAPMTI_R_4_1_0__SHIFT 0x0
3219#define DPM_TABLE_415__BAPMTI_R_4_0_0_MASK 0xffff0000
3220#define DPM_TABLE_415__BAPMTI_R_4_0_0__SHIFT 0x10
3221#define DPM_TABLE_416__BAPMTI_RC_0_0_0_MASK 0xffff
3222#define DPM_TABLE_416__BAPMTI_RC_0_0_0__SHIFT 0x0
3223#define DPM_TABLE_416__BAPMTI_R_4_2_0_MASK 0xffff0000
3224#define DPM_TABLE_416__BAPMTI_R_4_2_0__SHIFT 0x10
3225#define DPM_TABLE_417__BAPMTI_RC_0_2_0_MASK 0xffff
3226#define DPM_TABLE_417__BAPMTI_RC_0_2_0__SHIFT 0x0
3227#define DPM_TABLE_417__BAPMTI_RC_0_1_0_MASK 0xffff0000
3228#define DPM_TABLE_417__BAPMTI_RC_0_1_0__SHIFT 0x10
3229#define DPM_TABLE_418__BAPMTI_RC_1_1_0_MASK 0xffff
3230#define DPM_TABLE_418__BAPMTI_RC_1_1_0__SHIFT 0x0
3231#define DPM_TABLE_418__BAPMTI_RC_1_0_0_MASK 0xffff0000
3232#define DPM_TABLE_418__BAPMTI_RC_1_0_0__SHIFT 0x10
3233#define DPM_TABLE_419__BAPMTI_RC_2_0_0_MASK 0xffff
3234#define DPM_TABLE_419__BAPMTI_RC_2_0_0__SHIFT 0x0
3235#define DPM_TABLE_419__BAPMTI_RC_1_2_0_MASK 0xffff0000
3236#define DPM_TABLE_419__BAPMTI_RC_1_2_0__SHIFT 0x10
3237#define DPM_TABLE_420__BAPMTI_RC_2_2_0_MASK 0xffff
3238#define DPM_TABLE_420__BAPMTI_RC_2_2_0__SHIFT 0x0
3239#define DPM_TABLE_420__BAPMTI_RC_2_1_0_MASK 0xffff0000
3240#define DPM_TABLE_420__BAPMTI_RC_2_1_0__SHIFT 0x10
3241#define DPM_TABLE_421__BAPMTI_RC_3_1_0_MASK 0xffff
3242#define DPM_TABLE_421__BAPMTI_RC_3_1_0__SHIFT 0x0
3243#define DPM_TABLE_421__BAPMTI_RC_3_0_0_MASK 0xffff0000
3244#define DPM_TABLE_421__BAPMTI_RC_3_0_0__SHIFT 0x10
3245#define DPM_TABLE_422__BAPMTI_RC_4_0_0_MASK 0xffff
3246#define DPM_TABLE_422__BAPMTI_RC_4_0_0__SHIFT 0x0
3247#define DPM_TABLE_422__BAPMTI_RC_3_2_0_MASK 0xffff0000
3248#define DPM_TABLE_422__BAPMTI_RC_3_2_0__SHIFT 0x10
3249#define DPM_TABLE_423__BAPMTI_RC_4_2_0_MASK 0xffff
3250#define DPM_TABLE_423__BAPMTI_RC_4_2_0__SHIFT 0x0
3251#define DPM_TABLE_423__BAPMTI_RC_4_1_0_MASK 0xffff0000
3252#define DPM_TABLE_423__BAPMTI_RC_4_1_0__SHIFT 0x10
3253#define DPM_TABLE_424__GpuTjHyst_MASK 0xff
3254#define DPM_TABLE_424__GpuTjHyst__SHIFT 0x0
3255#define DPM_TABLE_424__GpuTjMax_MASK 0xff00
3256#define DPM_TABLE_424__GpuTjMax__SHIFT 0x8
3257#define DPM_TABLE_424__DTETjOffset_MASK 0xff0000
3258#define DPM_TABLE_424__DTETjOffset__SHIFT 0x10
3259#define DPM_TABLE_424__DTEAmbientTempBase_MASK 0xff000000
3260#define DPM_TABLE_424__DTEAmbientTempBase__SHIFT 0x18
3261#define DPM_TABLE_425__BootVoltage_Phases_MASK 0xff
3262#define DPM_TABLE_425__BootVoltage_Phases__SHIFT 0x0
3263#define DPM_TABLE_425__BootVoltage_VddGfx_MASK 0xff00
3264#define DPM_TABLE_425__BootVoltage_VddGfx__SHIFT 0x8
3265#define DPM_TABLE_425__BootVoltage_Vddci_MASK 0xff0000
3266#define DPM_TABLE_425__BootVoltage_Vddci__SHIFT 0x10
3267#define DPM_TABLE_425__BootVoltage_Vddc_MASK 0xff000000
3268#define DPM_TABLE_425__BootVoltage_Vddc__SHIFT 0x18
3269#define DPM_TABLE_426__BAPM_TEMP_GRADIENT_MASK 0xffffffff
3270#define DPM_TABLE_426__BAPM_TEMP_GRADIENT__SHIFT 0x0
3271#define DPM_TABLE_427__LowSclkInterruptThreshold_MASK 0xffffffff
3272#define DPM_TABLE_427__LowSclkInterruptThreshold__SHIFT 0x0
3273#define DPM_TABLE_428__VddGfxReChkWait_MASK 0xffffffff
3274#define DPM_TABLE_428__VddGfxReChkWait__SHIFT 0x0
3275#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff
3276#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0
3277#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00
3278#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8
3279#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000
3280#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10
3281#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000
3282#define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18
3283#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff
3284#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0
3285#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00
3286#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8
3287#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000
3288#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10
3289#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000
3290#define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18
3291#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff
3292#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0
3293#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00
3294#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8
3295#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000
3296#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10
3297#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000
3298#define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18
3299#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff
3300#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0
3301#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00
3302#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8
3303#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000
3304#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10
3305#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000
3306#define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18
3307#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff
3308#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0
3309#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00
3310#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8
3311#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000
3312#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10
3313#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000
3314#define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18
3315#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff
3316#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0
3317#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00
3318#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8
3319#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000
3320#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10
3321#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000
3322#define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18
3323#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff
3324#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0
3325#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00
3326#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8
3327#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000
3328#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10
3329#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000
3330#define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18
3331#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff
3332#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0
3333#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00
3334#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8
3335#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000
3336#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10
3337#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000
3338#define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18
3339#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff
3340#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0
3341#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00
3342#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8
3343#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000
3344#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10
3345#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000
3346#define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18
3347#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff
3348#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0
3349#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00
3350#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8
3351#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000
3352#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10
3353#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000
3354#define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18
3355#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff
3356#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0
3357#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00
3358#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8
3359#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000
3360#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10
3361#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000
3362#define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18
3363#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff
3364#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0
3365#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00
3366#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8
3367#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000
3368#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10
3369#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000
3370#define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18
3371#define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
3372#define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
3373#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
3374#define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
3375#define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
3376#define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
3377#define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff
3378#define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0
3379#define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff
3380#define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0
3381#define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff
3382#define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0
3383#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff
3384#define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0
3385#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff
3386#define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0
3387#define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff
3388#define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0
3389#define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff
3390#define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0
3391#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff
3392#define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0
3393#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff
3394#define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0
3395#define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff
3396#define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0
3397#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff
3398#define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0
3399#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00
3400#define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8
3401#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000
3402#define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10
3403#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000
3404#define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18
3405#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff
3406#define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0
3407#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00
3408#define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8
3409#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000
3410#define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10
3411#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000
3412#define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18
3413#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff
3414#define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0
3415#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff
3416#define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0
3417#define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff
3418#define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0
3419#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff
3420#define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0
3421#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00
3422#define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8
3423#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000
3424#define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10
3425#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000
3426#define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18
3427#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff
3428#define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0
3429#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00
3430#define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8
3431#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000
3432#define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10
3433#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000
3434#define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18
3435#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff
3436#define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0
3437#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff
3438#define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0
3439#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff
3440#define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0
3441#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff
3442#define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0
3443#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff
3444#define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0
3445#define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff
3446#define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0
3447#define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff
3448#define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0
3449#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff
3450#define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0
3451#define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff
3452#define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0
3453#define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff
3454#define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0
3455#define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff
3456#define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0
3457#define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00
3458#define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8
3459#define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000
3460#define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10
3461#define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000
3462#define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18
3463#define PM_FUSES_2__TDC_MAWt_MASK 0xff
3464#define PM_FUSES_2__TDC_MAWt__SHIFT 0x0
3465#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00
3466#define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8
3467#define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000
3468#define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10
3469#define PM_FUSES_3__Reserved_MASK 0xff
3470#define PM_FUSES_3__Reserved__SHIFT 0x0
3471#define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00
3472#define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8
3473#define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000
3474#define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10
3475#define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000
3476#define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18
3477#define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff
3478#define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0
3479#define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00
3480#define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8
3481#define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000
3482#define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10
3483#define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000
3484#define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18
3485#define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff
3486#define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0
3487#define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00
3488#define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8
3489#define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000
3490#define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10
3491#define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000
3492#define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18
3493#define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff
3494#define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0
3495#define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00
3496#define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8
3497#define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000
3498#define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10
3499#define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000
3500#define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18
3501#define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff
3502#define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0
3503#define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00
3504#define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8
3505#define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000
3506#define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10
3507#define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000
3508#define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18
3509#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff
3510#define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0
3511#define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000
3512#define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10
3513#define PM_FUSES_9__Reserved6_MASK 0xffff
3514#define PM_FUSES_9__Reserved6__SHIFT 0x0
3515#define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000
3516#define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10
3517#define PM_FUSES_10__GnbLPML_3_MASK 0xff
3518#define PM_FUSES_10__GnbLPML_3__SHIFT 0x0
3519#define PM_FUSES_10__GnbLPML_2_MASK 0xff00
3520#define PM_FUSES_10__GnbLPML_2__SHIFT 0x8
3521#define PM_FUSES_10__GnbLPML_1_MASK 0xff0000
3522#define PM_FUSES_10__GnbLPML_1__SHIFT 0x10
3523#define PM_FUSES_10__GnbLPML_0_MASK 0xff000000
3524#define PM_FUSES_10__GnbLPML_0__SHIFT 0x18
3525#define PM_FUSES_11__GnbLPML_7_MASK 0xff
3526#define PM_FUSES_11__GnbLPML_7__SHIFT 0x0
3527#define PM_FUSES_11__GnbLPML_6_MASK 0xff00
3528#define PM_FUSES_11__GnbLPML_6__SHIFT 0x8
3529#define PM_FUSES_11__GnbLPML_5_MASK 0xff0000
3530#define PM_FUSES_11__GnbLPML_5__SHIFT 0x10
3531#define PM_FUSES_11__GnbLPML_4_MASK 0xff000000
3532#define PM_FUSES_11__GnbLPML_4__SHIFT 0x18
3533#define PM_FUSES_12__GnbLPML_11_MASK 0xff
3534#define PM_FUSES_12__GnbLPML_11__SHIFT 0x0
3535#define PM_FUSES_12__GnbLPML_10_MASK 0xff00
3536#define PM_FUSES_12__GnbLPML_10__SHIFT 0x8
3537#define PM_FUSES_12__GnbLPML_9_MASK 0xff0000
3538#define PM_FUSES_12__GnbLPML_9__SHIFT 0x10
3539#define PM_FUSES_12__GnbLPML_8_MASK 0xff000000
3540#define PM_FUSES_12__GnbLPML_8__SHIFT 0x18
3541#define PM_FUSES_13__GnbLPML_15_MASK 0xff
3542#define PM_FUSES_13__GnbLPML_15__SHIFT 0x0
3543#define PM_FUSES_13__GnbLPML_14_MASK 0xff00
3544#define PM_FUSES_13__GnbLPML_14__SHIFT 0x8
3545#define PM_FUSES_13__GnbLPML_13_MASK 0xff0000
3546#define PM_FUSES_13__GnbLPML_13__SHIFT 0x10
3547#define PM_FUSES_13__GnbLPML_12_MASK 0xff000000
3548#define PM_FUSES_13__GnbLPML_12__SHIFT 0x18
3549#define PM_FUSES_14__Reserved1_1_MASK 0xff
3550#define PM_FUSES_14__Reserved1_1__SHIFT 0x0
3551#define PM_FUSES_14__Reserved1_0_MASK 0xff00
3552#define PM_FUSES_14__Reserved1_0__SHIFT 0x8
3553#define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000
3554#define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10
3555#define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000
3556#define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18
3557#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff
3558#define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0
3559#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000
3560#define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10
3561#define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
3562#define SMU_PM_STATUS_0__DATA__SHIFT 0x0
3563#define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
3564#define SMU_PM_STATUS_1__DATA__SHIFT 0x0
3565#define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
3566#define SMU_PM_STATUS_2__DATA__SHIFT 0x0
3567#define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
3568#define SMU_PM_STATUS_3__DATA__SHIFT 0x0
3569#define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
3570#define SMU_PM_STATUS_4__DATA__SHIFT 0x0
3571#define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
3572#define SMU_PM_STATUS_5__DATA__SHIFT 0x0
3573#define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
3574#define SMU_PM_STATUS_6__DATA__SHIFT 0x0
3575#define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
3576#define SMU_PM_STATUS_7__DATA__SHIFT 0x0
3577#define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
3578#define SMU_PM_STATUS_8__DATA__SHIFT 0x0
3579#define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
3580#define SMU_PM_STATUS_9__DATA__SHIFT 0x0
3581#define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
3582#define SMU_PM_STATUS_10__DATA__SHIFT 0x0
3583#define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
3584#define SMU_PM_STATUS_11__DATA__SHIFT 0x0
3585#define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
3586#define SMU_PM_STATUS_12__DATA__SHIFT 0x0
3587#define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
3588#define SMU_PM_STATUS_13__DATA__SHIFT 0x0
3589#define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
3590#define SMU_PM_STATUS_14__DATA__SHIFT 0x0
3591#define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
3592#define SMU_PM_STATUS_15__DATA__SHIFT 0x0
3593#define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
3594#define SMU_PM_STATUS_16__DATA__SHIFT 0x0
3595#define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
3596#define SMU_PM_STATUS_17__DATA__SHIFT 0x0
3597#define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
3598#define SMU_PM_STATUS_18__DATA__SHIFT 0x0
3599#define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
3600#define SMU_PM_STATUS_19__DATA__SHIFT 0x0
3601#define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
3602#define SMU_PM_STATUS_20__DATA__SHIFT 0x0
3603#define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
3604#define SMU_PM_STATUS_21__DATA__SHIFT 0x0
3605#define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
3606#define SMU_PM_STATUS_22__DATA__SHIFT 0x0
3607#define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
3608#define SMU_PM_STATUS_23__DATA__SHIFT 0x0
3609#define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
3610#define SMU_PM_STATUS_24__DATA__SHIFT 0x0
3611#define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
3612#define SMU_PM_STATUS_25__DATA__SHIFT 0x0
3613#define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
3614#define SMU_PM_STATUS_26__DATA__SHIFT 0x0
3615#define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
3616#define SMU_PM_STATUS_27__DATA__SHIFT 0x0
3617#define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
3618#define SMU_PM_STATUS_28__DATA__SHIFT 0x0
3619#define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
3620#define SMU_PM_STATUS_29__DATA__SHIFT 0x0
3621#define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
3622#define SMU_PM_STATUS_30__DATA__SHIFT 0x0
3623#define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
3624#define SMU_PM_STATUS_31__DATA__SHIFT 0x0
3625#define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
3626#define SMU_PM_STATUS_32__DATA__SHIFT 0x0
3627#define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
3628#define SMU_PM_STATUS_33__DATA__SHIFT 0x0
3629#define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
3630#define SMU_PM_STATUS_34__DATA__SHIFT 0x0
3631#define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
3632#define SMU_PM_STATUS_35__DATA__SHIFT 0x0
3633#define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
3634#define SMU_PM_STATUS_36__DATA__SHIFT 0x0
3635#define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
3636#define SMU_PM_STATUS_37__DATA__SHIFT 0x0
3637#define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
3638#define SMU_PM_STATUS_38__DATA__SHIFT 0x0
3639#define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
3640#define SMU_PM_STATUS_39__DATA__SHIFT 0x0
3641#define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
3642#define SMU_PM_STATUS_40__DATA__SHIFT 0x0
3643#define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
3644#define SMU_PM_STATUS_41__DATA__SHIFT 0x0
3645#define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
3646#define SMU_PM_STATUS_42__DATA__SHIFT 0x0
3647#define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
3648#define SMU_PM_STATUS_43__DATA__SHIFT 0x0
3649#define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
3650#define SMU_PM_STATUS_44__DATA__SHIFT 0x0
3651#define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
3652#define SMU_PM_STATUS_45__DATA__SHIFT 0x0
3653#define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
3654#define SMU_PM_STATUS_46__DATA__SHIFT 0x0
3655#define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
3656#define SMU_PM_STATUS_47__DATA__SHIFT 0x0
3657#define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
3658#define SMU_PM_STATUS_48__DATA__SHIFT 0x0
3659#define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
3660#define SMU_PM_STATUS_49__DATA__SHIFT 0x0
3661#define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
3662#define SMU_PM_STATUS_50__DATA__SHIFT 0x0
3663#define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
3664#define SMU_PM_STATUS_51__DATA__SHIFT 0x0
3665#define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
3666#define SMU_PM_STATUS_52__DATA__SHIFT 0x0
3667#define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
3668#define SMU_PM_STATUS_53__DATA__SHIFT 0x0
3669#define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
3670#define SMU_PM_STATUS_54__DATA__SHIFT 0x0
3671#define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
3672#define SMU_PM_STATUS_55__DATA__SHIFT 0x0
3673#define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
3674#define SMU_PM_STATUS_56__DATA__SHIFT 0x0
3675#define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
3676#define SMU_PM_STATUS_57__DATA__SHIFT 0x0
3677#define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
3678#define SMU_PM_STATUS_58__DATA__SHIFT 0x0
3679#define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
3680#define SMU_PM_STATUS_59__DATA__SHIFT 0x0
3681#define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
3682#define SMU_PM_STATUS_60__DATA__SHIFT 0x0
3683#define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
3684#define SMU_PM_STATUS_61__DATA__SHIFT 0x0
3685#define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
3686#define SMU_PM_STATUS_62__DATA__SHIFT 0x0
3687#define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
3688#define SMU_PM_STATUS_63__DATA__SHIFT 0x0
3689#define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
3690#define SMU_PM_STATUS_64__DATA__SHIFT 0x0
3691#define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
3692#define SMU_PM_STATUS_65__DATA__SHIFT 0x0
3693#define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
3694#define SMU_PM_STATUS_66__DATA__SHIFT 0x0
3695#define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
3696#define SMU_PM_STATUS_67__DATA__SHIFT 0x0
3697#define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
3698#define SMU_PM_STATUS_68__DATA__SHIFT 0x0
3699#define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
3700#define SMU_PM_STATUS_69__DATA__SHIFT 0x0
3701#define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
3702#define SMU_PM_STATUS_70__DATA__SHIFT 0x0
3703#define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
3704#define SMU_PM_STATUS_71__DATA__SHIFT 0x0
3705#define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
3706#define SMU_PM_STATUS_72__DATA__SHIFT 0x0
3707#define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
3708#define SMU_PM_STATUS_73__DATA__SHIFT 0x0
3709#define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
3710#define SMU_PM_STATUS_74__DATA__SHIFT 0x0
3711#define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
3712#define SMU_PM_STATUS_75__DATA__SHIFT 0x0
3713#define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
3714#define SMU_PM_STATUS_76__DATA__SHIFT 0x0
3715#define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
3716#define SMU_PM_STATUS_77__DATA__SHIFT 0x0
3717#define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
3718#define SMU_PM_STATUS_78__DATA__SHIFT 0x0
3719#define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
3720#define SMU_PM_STATUS_79__DATA__SHIFT 0x0
3721#define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
3722#define SMU_PM_STATUS_80__DATA__SHIFT 0x0
3723#define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
3724#define SMU_PM_STATUS_81__DATA__SHIFT 0x0
3725#define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
3726#define SMU_PM_STATUS_82__DATA__SHIFT 0x0
3727#define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
3728#define SMU_PM_STATUS_83__DATA__SHIFT 0x0
3729#define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
3730#define SMU_PM_STATUS_84__DATA__SHIFT 0x0
3731#define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
3732#define SMU_PM_STATUS_85__DATA__SHIFT 0x0
3733#define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
3734#define SMU_PM_STATUS_86__DATA__SHIFT 0x0
3735#define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
3736#define SMU_PM_STATUS_87__DATA__SHIFT 0x0
3737#define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
3738#define SMU_PM_STATUS_88__DATA__SHIFT 0x0
3739#define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
3740#define SMU_PM_STATUS_89__DATA__SHIFT 0x0
3741#define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
3742#define SMU_PM_STATUS_90__DATA__SHIFT 0x0
3743#define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
3744#define SMU_PM_STATUS_91__DATA__SHIFT 0x0
3745#define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
3746#define SMU_PM_STATUS_92__DATA__SHIFT 0x0
3747#define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
3748#define SMU_PM_STATUS_93__DATA__SHIFT 0x0
3749#define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
3750#define SMU_PM_STATUS_94__DATA__SHIFT 0x0
3751#define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
3752#define SMU_PM_STATUS_95__DATA__SHIFT 0x0
3753#define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
3754#define SMU_PM_STATUS_96__DATA__SHIFT 0x0
3755#define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
3756#define SMU_PM_STATUS_97__DATA__SHIFT 0x0
3757#define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
3758#define SMU_PM_STATUS_98__DATA__SHIFT 0x0
3759#define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
3760#define SMU_PM_STATUS_99__DATA__SHIFT 0x0
3761#define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
3762#define SMU_PM_STATUS_100__DATA__SHIFT 0x0
3763#define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
3764#define SMU_PM_STATUS_101__DATA__SHIFT 0x0
3765#define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
3766#define SMU_PM_STATUS_102__DATA__SHIFT 0x0
3767#define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
3768#define SMU_PM_STATUS_103__DATA__SHIFT 0x0
3769#define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
3770#define SMU_PM_STATUS_104__DATA__SHIFT 0x0
3771#define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
3772#define SMU_PM_STATUS_105__DATA__SHIFT 0x0
3773#define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
3774#define SMU_PM_STATUS_106__DATA__SHIFT 0x0
3775#define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
3776#define SMU_PM_STATUS_107__DATA__SHIFT 0x0
3777#define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
3778#define SMU_PM_STATUS_108__DATA__SHIFT 0x0
3779#define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
3780#define SMU_PM_STATUS_109__DATA__SHIFT 0x0
3781#define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
3782#define SMU_PM_STATUS_110__DATA__SHIFT 0x0
3783#define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
3784#define SMU_PM_STATUS_111__DATA__SHIFT 0x0
3785#define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
3786#define SMU_PM_STATUS_112__DATA__SHIFT 0x0
3787#define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
3788#define SMU_PM_STATUS_113__DATA__SHIFT 0x0
3789#define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
3790#define SMU_PM_STATUS_114__DATA__SHIFT 0x0
3791#define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
3792#define SMU_PM_STATUS_115__DATA__SHIFT 0x0
3793#define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
3794#define SMU_PM_STATUS_116__DATA__SHIFT 0x0
3795#define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
3796#define SMU_PM_STATUS_117__DATA__SHIFT 0x0
3797#define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
3798#define SMU_PM_STATUS_118__DATA__SHIFT 0x0
3799#define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
3800#define SMU_PM_STATUS_119__DATA__SHIFT 0x0
3801#define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
3802#define SMU_PM_STATUS_120__DATA__SHIFT 0x0
3803#define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
3804#define SMU_PM_STATUS_121__DATA__SHIFT 0x0
3805#define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
3806#define SMU_PM_STATUS_122__DATA__SHIFT 0x0
3807#define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
3808#define SMU_PM_STATUS_123__DATA__SHIFT 0x0
3809#define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
3810#define SMU_PM_STATUS_124__DATA__SHIFT 0x0
3811#define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
3812#define SMU_PM_STATUS_125__DATA__SHIFT 0x0
3813#define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
3814#define SMU_PM_STATUS_126__DATA__SHIFT 0x0
3815#define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
3816#define SMU_PM_STATUS_127__DATA__SHIFT 0x0
3817#define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
3818#define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
3819#define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
3820#define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
3821#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
3822#define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
3823#define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
3824#define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
3825#define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
3826#define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
3827#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
3828#define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
3829#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
3830#define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
3831#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
3832#define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
3833#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
3834#define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
3835#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
3836#define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
3837#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
3838#define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
3839#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
3840#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
3841#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
3842#define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
3843#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
3844#define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
3845#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
3846#define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
3847#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
3848#define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
3849#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
3850#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
3851#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
3852#define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
3853#define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7
3854#define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0
3855#define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8
3856#define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3
3857#define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0
3858#define CG_THERMAL_CTRL__SPARE__SHIFT 0x4
3859#define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000
3860#define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe
3861#define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000
3862#define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16
3863#define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000
3864#define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19
3865#define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000
3866#define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a
3867#define CG_THERMAL_STATUS__SPARE_MASK 0x1ff
3868#define CG_THERMAL_STATUS__SPARE__SHIFT 0x0
3869#define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00
3870#define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9
3871#define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000
3872#define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11
3873#define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000
3874#define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12
3875#define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff
3876#define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0
3877#define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00
3878#define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8
3879#define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000
3880#define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10
3881#define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000
3882#define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18
3883#define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf
3884#define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0
3885#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0
3886#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4
3887#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200
3888#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9
3889#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000
3890#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14
3891#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000
3892#define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c
3893#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff
3894#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0
3895#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00
3896#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
3897#define THM_TMON2_CTRL__POWER_DOWN_MASK 0x1
3898#define THM_TMON2_CTRL__POWER_DOWN__SHIFT 0x0
3899#define THM_TMON2_CTRL__BGADJ_MASK 0x1fe
3900#define THM_TMON2_CTRL__BGADJ__SHIFT 0x1
3901#define THM_TMON2_CTRL__BGADJ_MODE_MASK 0x200
3902#define THM_TMON2_CTRL__BGADJ_MODE__SHIFT 0x9
3903#define THM_TMON2_CTRL__TMON_PAUSE_MASK 0x400
3904#define THM_TMON2_CTRL__TMON_PAUSE__SHIFT 0xa
3905#define THM_TMON2_CTRL__INT_MEAS_EN_MASK 0x800
3906#define THM_TMON2_CTRL__INT_MEAS_EN__SHIFT 0xb
3907#define THM_TMON2_CTRL__DEBUG_MODE_MASK 0x1000
3908#define THM_TMON2_CTRL__DEBUG_MODE__SHIFT 0xc
3909#define THM_TMON2_CTRL__EN_CFG_SERDES_MASK 0x2000
3910#define THM_TMON2_CTRL__EN_CFG_SERDES__SHIFT 0xd
3911#define THM_TMON2_CTRL2__RDIL_PRESENT_MASK 0xffff
3912#define THM_TMON2_CTRL2__RDIL_PRESENT__SHIFT 0x0
3913#define THM_TMON2_CTRL2__RDIR_PRESENT_MASK 0xffff0000
3914#define THM_TMON2_CTRL2__RDIR_PRESENT__SHIFT 0x10
3915#define THM_TMON2_CSR_WR__CSR_WRITE_MASK 0x1
3916#define THM_TMON2_CSR_WR__CSR_WRITE__SHIFT 0x0
3917#define THM_TMON2_CSR_WR__CSR_READ_MASK 0x2
3918#define THM_TMON2_CSR_WR__CSR_READ__SHIFT 0x1
3919#define THM_TMON2_CSR_WR__CSR_ADDR_MASK 0xffc
3920#define THM_TMON2_CSR_WR__CSR_ADDR__SHIFT 0x2
3921#define THM_TMON2_CSR_WR__WRITE_DATA_MASK 0xfff000
3922#define THM_TMON2_CSR_WR__WRITE_DATA__SHIFT 0xc
3923#define THM_TMON2_CSR_WR__SPARE_MASK 0x1000000
3924#define THM_TMON2_CSR_WR__SPARE__SHIFT 0x18
3925#define THM_TMON2_CSR_RD__READ_DATA_MASK 0xfff
3926#define THM_TMON2_CSR_RD__READ_DATA__SHIFT 0x0
3927#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff
3928#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
3929#define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00
3930#define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8
3931#define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000
3932#define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10
3933#define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000
3934#define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11
3935#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000
3936#define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17
3937#define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000
3938#define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18
3939#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff
3940#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
3941#define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00
3942#define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8
3943#define CG_FDO_CTRL1__M_MASK 0xff0000
3944#define CG_FDO_CTRL1__M__SHIFT 0x10
3945#define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000
3946#define CG_FDO_CTRL1__RESERVED__SHIFT 0x18
3947#define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000
3948#define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e
3949#define CG_FDO_CTRL2__TMIN_MASK 0xff
3950#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
3951#define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700
3952#define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8
3953#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800
3954#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
3955#define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000
3956#define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe
3957#define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000
3958#define CG_FDO_CTRL2__TMAX__SHIFT 0x11
3959#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000
3960#define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19
3961#define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7
3962#define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0
3963#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8
3964#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
3965#define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff
3966#define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0
3967#define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe
3968#define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1
3969#define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00
3970#define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9
3971#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000
3972#define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11
3973#define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000
3974#define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12
3975#define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000
3976#define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15
3977#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000
3978#define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18
3979#define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000
3980#define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19
3981#define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000
3982#define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a
3983#define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000
3984#define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b
3985#define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000
3986#define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c
3987#define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000
3988#define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d
3989#define CC_THM_STRAPS0__UNUSED_MASK 0x80000000
3990#define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f
3991#define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff
3992#define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0
3993#define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800
3994#define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb
3995#define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000
3996#define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc
3997#define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff
3998#define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0
3999#define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800
4000#define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb
4001#define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000
4002#define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc
4003#define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff
4004#define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0
4005#define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800
4006#define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb
4007#define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000
4008#define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc
4009#define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff
4010#define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0
4011#define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800
4012#define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb
4013#define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000
4014#define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc
4015#define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff
4016#define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0
4017#define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800
4018#define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb
4019#define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000
4020#define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc
4021#define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff
4022#define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0
4023#define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800
4024#define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb
4025#define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000
4026#define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc
4027#define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff
4028#define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0
4029#define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800
4030#define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb
4031#define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000
4032#define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc
4033#define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff
4034#define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0
4035#define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800
4036#define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb
4037#define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000
4038#define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc
4039#define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff
4040#define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0
4041#define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800
4042#define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb
4043#define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000
4044#define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc
4045#define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff
4046#define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0
4047#define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800
4048#define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb
4049#define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000
4050#define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc
4051#define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff
4052#define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0
4053#define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800
4054#define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb
4055#define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000
4056#define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc
4057#define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff
4058#define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0
4059#define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800
4060#define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb
4061#define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000
4062#define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc
4063#define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff
4064#define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0
4065#define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800
4066#define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb
4067#define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000
4068#define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc
4069#define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff
4070#define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0
4071#define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800
4072#define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb
4073#define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000
4074#define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc
4075#define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff
4076#define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0
4077#define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800
4078#define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb
4079#define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000
4080#define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc
4081#define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff
4082#define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0
4083#define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800
4084#define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb
4085#define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000
4086#define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc
4087#define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff
4088#define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0
4089#define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800
4090#define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb
4091#define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000
4092#define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc
4093#define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff
4094#define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0
4095#define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800
4096#define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb
4097#define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000
4098#define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc
4099#define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff
4100#define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0
4101#define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800
4102#define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb
4103#define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000
4104#define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc
4105#define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff
4106#define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0
4107#define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800
4108#define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb
4109#define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000
4110#define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc
4111#define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff
4112#define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0
4113#define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800
4114#define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb
4115#define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000
4116#define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc
4117#define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff
4118#define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0
4119#define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800
4120#define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb
4121#define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000
4122#define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc
4123#define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff
4124#define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0
4125#define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800
4126#define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb
4127#define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000
4128#define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc
4129#define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff
4130#define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0
4131#define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800
4132#define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb
4133#define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000
4134#define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc
4135#define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff
4136#define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0
4137#define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800
4138#define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb
4139#define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000
4140#define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc
4141#define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff
4142#define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0
4143#define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800
4144#define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb
4145#define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000
4146#define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc
4147#define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff
4148#define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0
4149#define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800
4150#define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb
4151#define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000
4152#define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc
4153#define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff
4154#define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0
4155#define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800
4156#define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb
4157#define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000
4158#define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc
4159#define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff
4160#define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0
4161#define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800
4162#define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb
4163#define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000
4164#define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc
4165#define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff
4166#define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0
4167#define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800
4168#define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb
4169#define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000
4170#define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc
4171#define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff
4172#define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0
4173#define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800
4174#define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb
4175#define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000
4176#define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc
4177#define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff
4178#define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0
4179#define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800
4180#define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb
4181#define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000
4182#define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc
4183#define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff
4184#define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0
4185#define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800
4186#define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb
4187#define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000
4188#define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc
4189#define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff
4190#define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0
4191#define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800
4192#define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb
4193#define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000
4194#define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc
4195#define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff
4196#define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0
4197#define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800
4198#define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb
4199#define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000
4200#define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc
4201#define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff
4202#define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0
4203#define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800
4204#define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb
4205#define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000
4206#define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc
4207#define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff
4208#define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0
4209#define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800
4210#define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb
4211#define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000
4212#define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc
4213#define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff
4214#define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0
4215#define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800
4216#define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb
4217#define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000
4218#define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc
4219#define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff
4220#define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0
4221#define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800
4222#define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb
4223#define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000
4224#define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc
4225#define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff
4226#define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0
4227#define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800
4228#define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb
4229#define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000
4230#define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc
4231#define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff
4232#define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0
4233#define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800
4234#define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb
4235#define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000
4236#define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc
4237#define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff
4238#define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0
4239#define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800
4240#define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb
4241#define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000
4242#define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc
4243#define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff
4244#define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0
4245#define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800
4246#define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb
4247#define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000
4248#define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc
4249#define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff
4250#define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0
4251#define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800
4252#define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb
4253#define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000
4254#define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc
4255#define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff
4256#define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0
4257#define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800
4258#define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb
4259#define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000
4260#define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc
4261#define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff
4262#define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0
4263#define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800
4264#define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb
4265#define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000
4266#define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc
4267#define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff
4268#define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0
4269#define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800
4270#define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb
4271#define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000
4272#define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc
4273#define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff
4274#define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0
4275#define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800
4276#define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb
4277#define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000
4278#define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc
4279#define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff
4280#define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0
4281#define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800
4282#define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb
4283#define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000
4284#define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc
4285#define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff
4286#define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0
4287#define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800
4288#define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb
4289#define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000
4290#define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc
4291#define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff
4292#define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0
4293#define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800
4294#define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb
4295#define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000
4296#define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc
4297#define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff
4298#define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0
4299#define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800
4300#define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb
4301#define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000
4302#define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc
4303#define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff
4304#define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0
4305#define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800
4306#define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb
4307#define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000
4308#define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc
4309#define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff
4310#define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0
4311#define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800
4312#define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb
4313#define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000
4314#define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc
4315#define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff
4316#define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0
4317#define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800
4318#define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb
4319#define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000
4320#define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc
4321#define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff
4322#define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0
4323#define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800
4324#define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb
4325#define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000
4326#define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc
4327#define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff
4328#define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0
4329#define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800
4330#define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb
4331#define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000
4332#define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc
4333#define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff
4334#define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0
4335#define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800
4336#define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb
4337#define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000
4338#define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc
4339#define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff
4340#define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0
4341#define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800
4342#define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb
4343#define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000
4344#define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc
4345#define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff
4346#define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0
4347#define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800
4348#define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb
4349#define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000
4350#define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc
4351#define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff
4352#define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0
4353#define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800
4354#define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb
4355#define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000
4356#define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc
4357#define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff
4358#define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0
4359#define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800
4360#define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb
4361#define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000
4362#define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc
4363#define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff
4364#define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0
4365#define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800
4366#define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb
4367#define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000
4368#define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc
4369#define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff
4370#define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0
4371#define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800
4372#define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb
4373#define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000
4374#define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc
4375#define THM_TMON2_RDIL0_DATA__Z_MASK 0x7ff
4376#define THM_TMON2_RDIL0_DATA__Z__SHIFT 0x0
4377#define THM_TMON2_RDIL0_DATA__VALID_MASK 0x800
4378#define THM_TMON2_RDIL0_DATA__VALID__SHIFT 0xb
4379#define THM_TMON2_RDIL0_DATA__TEMP_MASK 0xfff000
4380#define THM_TMON2_RDIL0_DATA__TEMP__SHIFT 0xc
4381#define THM_TMON2_RDIL1_DATA__Z_MASK 0x7ff
4382#define THM_TMON2_RDIL1_DATA__Z__SHIFT 0x0
4383#define THM_TMON2_RDIL1_DATA__VALID_MASK 0x800
4384#define THM_TMON2_RDIL1_DATA__VALID__SHIFT 0xb
4385#define THM_TMON2_RDIL1_DATA__TEMP_MASK 0xfff000
4386#define THM_TMON2_RDIL1_DATA__TEMP__SHIFT 0xc
4387#define THM_TMON2_RDIL2_DATA__Z_MASK 0x7ff
4388#define THM_TMON2_RDIL2_DATA__Z__SHIFT 0x0
4389#define THM_TMON2_RDIL2_DATA__VALID_MASK 0x800
4390#define THM_TMON2_RDIL2_DATA__VALID__SHIFT 0xb
4391#define THM_TMON2_RDIL2_DATA__TEMP_MASK 0xfff000
4392#define THM_TMON2_RDIL2_DATA__TEMP__SHIFT 0xc
4393#define THM_TMON2_RDIL3_DATA__Z_MASK 0x7ff
4394#define THM_TMON2_RDIL3_DATA__Z__SHIFT 0x0
4395#define THM_TMON2_RDIL3_DATA__VALID_MASK 0x800
4396#define THM_TMON2_RDIL3_DATA__VALID__SHIFT 0xb
4397#define THM_TMON2_RDIL3_DATA__TEMP_MASK 0xfff000
4398#define THM_TMON2_RDIL3_DATA__TEMP__SHIFT 0xc
4399#define THM_TMON2_RDIL4_DATA__Z_MASK 0x7ff
4400#define THM_TMON2_RDIL4_DATA__Z__SHIFT 0x0
4401#define THM_TMON2_RDIL4_DATA__VALID_MASK 0x800
4402#define THM_TMON2_RDIL4_DATA__VALID__SHIFT 0xb
4403#define THM_TMON2_RDIL4_DATA__TEMP_MASK 0xfff000
4404#define THM_TMON2_RDIL4_DATA__TEMP__SHIFT 0xc
4405#define THM_TMON2_RDIL5_DATA__Z_MASK 0x7ff
4406#define THM_TMON2_RDIL5_DATA__Z__SHIFT 0x0
4407#define THM_TMON2_RDIL5_DATA__VALID_MASK 0x800
4408#define THM_TMON2_RDIL5_DATA__VALID__SHIFT 0xb
4409#define THM_TMON2_RDIL5_DATA__TEMP_MASK 0xfff000
4410#define THM_TMON2_RDIL5_DATA__TEMP__SHIFT 0xc
4411#define THM_TMON2_RDIL6_DATA__Z_MASK 0x7ff
4412#define THM_TMON2_RDIL6_DATA__Z__SHIFT 0x0
4413#define THM_TMON2_RDIL6_DATA__VALID_MASK 0x800
4414#define THM_TMON2_RDIL6_DATA__VALID__SHIFT 0xb
4415#define THM_TMON2_RDIL6_DATA__TEMP_MASK 0xfff000
4416#define THM_TMON2_RDIL6_DATA__TEMP__SHIFT 0xc
4417#define THM_TMON2_RDIL7_DATA__Z_MASK 0x7