1/*
2 * UVD_6_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_6_0_D_H
25#define UVD_6_0_D_H
26
27#define mmUVD_SEMA_ADDR_LOW 0x3bc0
28#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29#define mmUVD_SEMA_CMD 0x3bc2
30#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33#define mmUVD_ENGINE_CNTL 0x3bc6
34#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
37#define mmUVD_POWER_STATUS_U 0x3bfd
38#define mmUVD_NO_OP 0x3bff
39#define mmUVD_RB_BASE_LO2 0x3c21
40#define mmUVD_RB_BASE_HI2 0x3c22
41#define mmUVD_RB_SIZE2 0x3c23
42#define mmUVD_RB_RPTR2 0x3c24
43#define mmUVD_RB_WPTR2 0x3c25
44#define mmUVD_RB_BASE_LO 0x3c26
45#define mmUVD_RB_BASE_HI 0x3c27
46#define mmUVD_RB_SIZE 0x3c28
47#define mmUVD_RB_RPTR 0x3c29
48#define mmUVD_RB_WPTR 0x3c2a
49#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
50#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
51#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
52#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
53#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
54#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
55#define mmUVD_SEMA_CNTL 0x3d00
56#define mmUVD_RB_WPTR3 0x3d1c
57#define mmUVD_RB_RPTR3 0x3d1b
58#define mmUVD_RB_BASE_LO3 0x3d1d
59#define mmUVD_RB_BASE_HI3 0x3d1e
60#define mmUVD_RB_SIZE3 0x3d1f
61#define mmUVD_LMI_EXT40_ADDR 0x3d26
62#define mmUVD_CTX_INDEX 0x3d28
63#define mmUVD_CTX_DATA 0x3d29
64#define mmUVD_CGC_GATE 0x3d2a
65#define mmUVD_CGC_STATUS 0x3d2b
66#define mmUVD_CGC_CTRL 0x3d2c
67#define mmUVD_CGC_UDEC_STATUS 0x3d2d
68#define mmUVD_LMI_CTRL2 0x3d3d
69#define mmUVD_MASTINT_EN 0x3d40
70#define mmUVD_LMI_ADDR_EXT 0x3d65
71#define mmUVD_LMI_CTRL 0x3d66
72#define mmUVD_LMI_STATUS 0x3d67
73#define mmUVD_LMI_SWAP_CNTL 0x3d6d
74#define mmUVD_MP_SWAP_CNTL 0x3d6f
75#define mmUVD_MPC_CNTL 0x3d77
76#define mmUVD_MPC_SET_MUXA0 0x3d79
77#define mmUVD_MPC_SET_MUXA1 0x3d7a
78#define mmUVD_MPC_SET_MUXB0 0x3d7b
79#define mmUVD_MPC_SET_MUXB1 0x3d7c
80#define mmUVD_MPC_SET_MUX 0x3d7d
81#define mmUVD_MPC_SET_ALU 0x3d7e
82#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
83#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
84#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
85#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
86#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
87#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
88#define mmUVD_VCPU_CNTL 0x3d98
89#define mmUVD_SOFT_RESET 0x3da0
90#define mmUVD_LMI_RBC_IB_VMID 0x3da1
91#define mmUVD_RBC_IB_SIZE 0x3da2
92#define mmUVD_LMI_RBC_RB_VMID 0x3da3
93#define mmUVD_RBC_RB_RPTR 0x3da4
94#define mmUVD_RBC_RB_WPTR 0x3da5
95#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
96#define mmUVD_RBC_RB_CNTL 0x3da9
97#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
98#define mmUVD_STATUS 0x3daf
99#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
100#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
101#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
102#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
103#define mmUVD_CONTEXT_ID 0x3dbd
104#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
105#define mmUVD_SUVD_CGC_GATE 0x3be4
106#define mmUVD_SUVD_CGC_STATUS 0x3be5
107#define mmUVD_SUVD_CGC_CTRL 0x3be6
108#define ixUVD_LMI_VMID_INTERNAL 0x99
109#define ixUVD_LMI_VMID_INTERNAL2 0x9a
110#define ixUVD_LMI_CACHE_CTRL 0x9b
111#define ixUVD_LMI_SWAP_CNTL2 0xaa
112#define ixUVD_LMI_ADDR_EXT2 0xab
113#define ixUVD_CGC_MEM_CTRL 0xc0
114#define ixUVD_CGC_CTRL2 0xc1
115#define ixUVD_LMI_VMID_INTERNAL3 0x162
116#define mmUVD_PGFSM_CONFIG 0x38c0
117#define mmUVD_PGFSM_READ_TILE1 0x38c2
118#define mmUVD_PGFSM_READ_TILE2 0x38c3
119#define mmUVD_POWER_STATUS 0x38c4
120#define mmUVD_PGFSM_READ_TILE3 0x38c5
121#define mmUVD_PGFSM_READ_TILE4 0x38c6
122#define mmUVD_PGFSM_READ_TILE5 0x38c8
123#define mmUVD_PGFSM_READ_TILE6 0x38ee
124#define mmUVD_PGFSM_READ_TILE7 0x38ef
125#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992
126#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993
127#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5
128#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4
129#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f
130#define mmUVD_GP_SCRATCH8 0x3c0a
131#define mmUVD_GP_SCRATCH9 0x3c0b
132#define mmUVD_GP_SCRATCH4 0x3d38
133
134#endif /* UVD_6_0_D_H */
135