1 | /* |
2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _uvd_7_0_SH_MASK_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: uvd0_uvd_pg_dec |
26 | //UVD_POWER_STATUS |
27 | #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 |
28 | #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 |
29 | #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 |
30 | #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 |
31 | #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 |
32 | #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 |
33 | #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 |
34 | #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 |
35 | #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa |
36 | #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L |
37 | #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L |
38 | #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x00000008L |
39 | #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x00000010L |
40 | #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x00000020L |
41 | #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0x000000C0L |
42 | #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L |
43 | #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x00000200L |
44 | #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x00000400L |
45 | //UVD_DPG_RBC_RB_CNTL |
46 | #define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
47 | #define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
48 | #define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 |
49 | #define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 |
50 | #define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 |
51 | #define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c |
52 | #define UVD_DPG_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL |
53 | #define UVD_DPG_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L |
54 | #define UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L |
55 | #define UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L |
56 | #define UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L |
57 | #define UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L |
58 | //UVD_DPG_RBC_RB_BASE_LOW |
59 | #define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW__SHIFT 0x0 |
60 | #define UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW_MASK 0xFFFFFFFFL |
61 | //UVD_DPG_RBC_RB_BASE_HIGH |
62 | #define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH__SHIFT 0x0 |
63 | #define UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH_MASK 0xFFFFFFFFL |
64 | //UVD_DPG_RBC_RB_WPTR_CNTL |
65 | #define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 |
66 | #define UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL |
67 | //UVD_DPG_RBC_RB_RPTR |
68 | #define UVD_DPG_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 |
69 | #define UVD_DPG_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
70 | //UVD_DPG_RBC_RB_WPTR |
71 | #define UVD_DPG_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 |
72 | #define UVD_DPG_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
73 | //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW |
74 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
75 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
76 | //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH |
77 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
78 | #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
79 | //UVD_DPG_VCPU_CACHE_OFFSET0 |
80 | #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 |
81 | #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL |
82 | |
83 | |
84 | // addressBlock: uvd0_uvdnpdec |
85 | //UVD_JPEG_ADDR_CONFIG |
86 | #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
87 | #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
88 | #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
89 | #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
90 | #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
91 | #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
92 | #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
93 | #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 |
94 | #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
95 | #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
96 | #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
97 | #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
98 | #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f |
99 | #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
100 | #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
101 | #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
102 | #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
103 | #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
104 | #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
105 | #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
106 | #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L |
107 | #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
108 | #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
109 | #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
110 | #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
111 | #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L |
112 | //UVD_GPCOM_VCPU_CMD |
113 | #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 |
114 | #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 |
115 | #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f |
116 | #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L |
117 | #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL |
118 | #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L |
119 | //UVD_GPCOM_VCPU_DATA0 |
120 | #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 |
121 | #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL |
122 | //UVD_GPCOM_VCPU_DATA1 |
123 | #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 |
124 | #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL |
125 | //UVD_UDEC_ADDR_CONFIG |
126 | #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
127 | #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
128 | #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
129 | #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
130 | #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
131 | #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
132 | #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
133 | #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 |
134 | #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
135 | #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
136 | #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
137 | #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
138 | #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f |
139 | #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
140 | #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
141 | #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
142 | #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
143 | #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
144 | #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
145 | #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
146 | #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L |
147 | #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
148 | #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
149 | #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
150 | #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
151 | #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L |
152 | //UVD_UDEC_DB_ADDR_CONFIG |
153 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
154 | #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
155 | #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
156 | #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
157 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
158 | #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
159 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
160 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 |
161 | #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
162 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
163 | #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
164 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
165 | #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f |
166 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
167 | #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
168 | #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
169 | #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
170 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
171 | #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
172 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
173 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L |
174 | #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
175 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
176 | #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
177 | #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
178 | #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L |
179 | //UVD_UDEC_DBW_ADDR_CONFIG |
180 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
181 | #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
182 | #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
183 | #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
184 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
185 | #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
186 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
187 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 |
188 | #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 |
189 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
190 | #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
191 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
192 | #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f |
193 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
194 | #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
195 | #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
196 | #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
197 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
198 | #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L |
199 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
200 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L |
201 | #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L |
202 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
203 | #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L |
204 | #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L |
205 | #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L |
206 | //UVD_SUVD_CGC_GATE |
207 | #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 |
208 | #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 |
209 | #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 |
210 | #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 |
211 | #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 |
212 | #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 |
213 | #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 |
214 | #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 |
215 | #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 |
216 | #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 |
217 | #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa |
218 | #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb |
219 | #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc |
220 | #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd |
221 | #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe |
222 | #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf |
223 | #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 |
224 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 |
225 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 |
226 | #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L |
227 | #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L |
228 | #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L |
229 | #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L |
230 | #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L |
231 | #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L |
232 | #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L |
233 | #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L |
234 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L |
235 | #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L |
236 | #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L |
237 | #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L |
238 | #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L |
239 | #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L |
240 | #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L |
241 | #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L |
242 | #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L |
243 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L |
244 | #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L |
245 | //UVD_SUVD_CGC_CTRL |
246 | #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 |
247 | #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 |
248 | #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 |
249 | #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 |
250 | #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 |
251 | #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 |
252 | #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 |
253 | #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 |
254 | #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 |
255 | #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L |
256 | #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L |
257 | #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L |
258 | #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L |
259 | #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L |
260 | #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L |
261 | #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L |
262 | #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L |
263 | #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L |
264 | //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW |
265 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
266 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
267 | //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH |
268 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
269 | #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
270 | //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW |
271 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
272 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
273 | //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH |
274 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
275 | #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
276 | //UVD_POWER_STATUS_U |
277 | #define UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT 0x0 |
278 | #define UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK 0x00000003L |
279 | //UVD_NO_OP |
280 | #define UVD_NO_OP__NO_OP__SHIFT 0x0 |
281 | #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL |
282 | //UVD_GP_SCRATCH8 |
283 | #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 |
284 | #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL |
285 | //UVD_RB_BASE_LO2 |
286 | #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 |
287 | #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L |
288 | //UVD_RB_BASE_HI2 |
289 | #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 |
290 | #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL |
291 | //UVD_RB_SIZE2 |
292 | #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 |
293 | #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L |
294 | //UVD_RB_RPTR2 |
295 | #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 |
296 | #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L |
297 | //UVD_RB_WPTR2 |
298 | #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 |
299 | #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L |
300 | //UVD_RB_BASE_LO |
301 | #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 |
302 | #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L |
303 | //UVD_RB_BASE_HI |
304 | #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
305 | #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL |
306 | //UVD_RB_SIZE |
307 | #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 |
308 | #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L |
309 | //UVD_RB_RPTR |
310 | #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 |
311 | #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
312 | //UVD_RB_WPTR |
313 | #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 |
314 | #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
315 | //UVD_JRBC_RB_RPTR |
316 | #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 |
317 | #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
318 | //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH |
319 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
320 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
321 | //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW |
322 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
323 | #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
324 | //UVD_LMI_RBC_IB_64BIT_BAR_HIGH |
325 | #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
326 | #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
327 | //UVD_LMI_RBC_IB_64BIT_BAR_LOW |
328 | #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
329 | #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
330 | //UVD_LMI_RBC_RB_64BIT_BAR_HIGH |
331 | #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 |
332 | #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL |
333 | //UVD_LMI_RBC_RB_64BIT_BAR_LOW |
334 | #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
335 | #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
336 | |
337 | |
338 | // addressBlock: uvd0_uvddec |
339 | //UVD_SEMA_CNTL |
340 | #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 |
341 | #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 |
342 | #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L |
343 | #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L |
344 | //UVD_LMI_JRBC_RB_64BIT_BAR_LOW |
345 | #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 |
346 | #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL |
347 | //UVD_JRBC_RB_WPTR |
348 | #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 |
349 | #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
350 | //UVD_RB_RPTR3 |
351 | #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 |
352 | #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L |
353 | //UVD_RB_WPTR3 |
354 | #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 |
355 | #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L |
356 | //UVD_RB_BASE_LO3 |
357 | #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 |
358 | #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L |
359 | //UVD_RB_BASE_HI3 |
360 | #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 |
361 | #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL |
362 | //UVD_RB_SIZE3 |
363 | #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 |
364 | #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L |
365 | //JPEG_CGC_GATE |
366 | #define JPEG_CGC_GATE__JPEG__SHIFT 0x14 |
367 | #define JPEG_CGC_GATE__JPEG2__SHIFT 0x15 |
368 | #define JPEG_CGC_GATE__JPEG_MASK 0x00100000L |
369 | #define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L |
370 | //UVD_CTX_INDEX |
371 | #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 |
372 | #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL |
373 | //UVD_CTX_DATA |
374 | #define UVD_CTX_DATA__DATA__SHIFT 0x0 |
375 | #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL |
376 | //UVD_CGC_GATE |
377 | #define UVD_CGC_GATE__SYS__SHIFT 0x0 |
378 | #define UVD_CGC_GATE__UDEC__SHIFT 0x1 |
379 | #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 |
380 | #define UVD_CGC_GATE__REGS__SHIFT 0x3 |
381 | #define UVD_CGC_GATE__RBC__SHIFT 0x4 |
382 | #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 |
383 | #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 |
384 | #define UVD_CGC_GATE__IDCT__SHIFT 0x7 |
385 | #define UVD_CGC_GATE__MPRD__SHIFT 0x8 |
386 | #define UVD_CGC_GATE__MPC__SHIFT 0x9 |
387 | #define UVD_CGC_GATE__LBSI__SHIFT 0xa |
388 | #define UVD_CGC_GATE__LRBBM__SHIFT 0xb |
389 | #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc |
390 | #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd |
391 | #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe |
392 | #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf |
393 | #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 |
394 | #define UVD_CGC_GATE__WCB__SHIFT 0x11 |
395 | #define UVD_CGC_GATE__VCPU__SHIFT 0x12 |
396 | #define UVD_CGC_GATE__SCPU__SHIFT 0x13 |
397 | #define UVD_CGC_GATE__SYS_MASK 0x00000001L |
398 | #define UVD_CGC_GATE__UDEC_MASK 0x00000002L |
399 | #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L |
400 | #define UVD_CGC_GATE__REGS_MASK 0x00000008L |
401 | #define UVD_CGC_GATE__RBC_MASK 0x00000010L |
402 | #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L |
403 | #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L |
404 | #define UVD_CGC_GATE__IDCT_MASK 0x00000080L |
405 | #define UVD_CGC_GATE__MPRD_MASK 0x00000100L |
406 | #define UVD_CGC_GATE__MPC_MASK 0x00000200L |
407 | #define UVD_CGC_GATE__LBSI_MASK 0x00000400L |
408 | #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L |
409 | #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L |
410 | #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L |
411 | #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L |
412 | #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L |
413 | #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L |
414 | #define UVD_CGC_GATE__WCB_MASK 0x00020000L |
415 | #define UVD_CGC_GATE__VCPU_MASK 0x00040000L |
416 | #define UVD_CGC_GATE__SCPU_MASK 0x00080000L |
417 | //UVD_CGC_CTRL |
418 | #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 |
419 | #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 |
420 | #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 |
421 | #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb |
422 | #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc |
423 | #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd |
424 | #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe |
425 | #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf |
426 | #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 |
427 | #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 |
428 | #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 |
429 | #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 |
430 | #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 |
431 | #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 |
432 | #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 |
433 | #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 |
434 | #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 |
435 | #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 |
436 | #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a |
437 | #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b |
438 | #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c |
439 | #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d |
440 | #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e |
441 | #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L |
442 | #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL |
443 | #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L |
444 | #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L |
445 | #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L |
446 | #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L |
447 | #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L |
448 | #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L |
449 | #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L |
450 | #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L |
451 | #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L |
452 | #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L |
453 | #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L |
454 | #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L |
455 | #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L |
456 | #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L |
457 | #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L |
458 | #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L |
459 | #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L |
460 | #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L |
461 | #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L |
462 | #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L |
463 | #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L |
464 | //UVD_GP_SCRATCH4 |
465 | #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 |
466 | #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL |
467 | //UVD_LMI_CTRL2 |
468 | #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 |
469 | #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 |
470 | #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 |
471 | #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 |
472 | #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 |
473 | #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 |
474 | #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 |
475 | #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb |
476 | #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L |
477 | #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L |
478 | #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L |
479 | #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L |
480 | #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L |
481 | #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L |
482 | #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L |
483 | #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L |
484 | //UVD_MASTINT_EN |
485 | #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 |
486 | #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 |
487 | #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 |
488 | #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 |
489 | #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L |
490 | #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L |
491 | #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L |
492 | #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L |
493 | //JPEG_CGC_CTRL |
494 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 |
495 | #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 |
496 | #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 |
497 | #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 |
498 | #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f |
499 | #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L |
500 | #define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L |
501 | #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL |
502 | #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L |
503 | #define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L |
504 | //UVD_LMI_CTRL |
505 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 |
506 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 |
507 | #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 |
508 | #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb |
509 | #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc |
510 | #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd |
511 | #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe |
512 | #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf |
513 | #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 |
514 | #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 |
515 | #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 |
516 | #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 |
517 | #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 |
518 | #define UVD_LMI_CTRL__RFU__SHIFT 0x1b |
519 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL |
520 | #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L |
521 | #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L |
522 | #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L |
523 | #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L |
524 | #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L |
525 | #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L |
526 | #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L |
527 | #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L |
528 | #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L |
529 | #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L |
530 | #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L |
531 | #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L |
532 | #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L |
533 | //UVD_LMI_SWAP_CNTL |
534 | #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 |
535 | #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 |
536 | #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 |
537 | #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 |
538 | #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 |
539 | #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa |
540 | #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc |
541 | #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe |
542 | #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 |
543 | #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 |
544 | #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 |
545 | #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 |
546 | #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a |
547 | #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c |
548 | #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e |
549 | #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L |
550 | #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL |
551 | #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L |
552 | #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L |
553 | #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L |
554 | #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L |
555 | #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L |
556 | #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L |
557 | #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L |
558 | #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L |
559 | #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L |
560 | #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L |
561 | #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L |
562 | #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L |
563 | #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L |
564 | //UVD_MP_SWAP_CNTL |
565 | #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 |
566 | #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 |
567 | #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 |
568 | #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 |
569 | #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 |
570 | #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa |
571 | #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc |
572 | #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe |
573 | #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 |
574 | #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 |
575 | #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 |
576 | #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 |
577 | #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 |
578 | #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a |
579 | #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c |
580 | #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e |
581 | #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L |
582 | #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL |
583 | #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L |
584 | #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L |
585 | #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L |
586 | #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L |
587 | #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L |
588 | #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L |
589 | #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L |
590 | #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L |
591 | #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L |
592 | #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L |
593 | #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L |
594 | #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L |
595 | #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L |
596 | #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L |
597 | //UVD_MPC_SET_MUXA0 |
598 | #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 |
599 | #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 |
600 | #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc |
601 | #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 |
602 | #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 |
603 | #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL |
604 | #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L |
605 | #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L |
606 | #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L |
607 | #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L |
608 | //UVD_MPC_SET_MUXA1 |
609 | #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 |
610 | #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 |
611 | #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc |
612 | #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL |
613 | #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L |
614 | #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L |
615 | //UVD_MPC_SET_MUXB0 |
616 | #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 |
617 | #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 |
618 | #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc |
619 | #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 |
620 | #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 |
621 | #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL |
622 | #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L |
623 | #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L |
624 | #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L |
625 | #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L |
626 | //UVD_MPC_SET_MUXB1 |
627 | #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 |
628 | #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 |
629 | #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc |
630 | #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL |
631 | #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L |
632 | #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L |
633 | //UVD_MPC_SET_MUX |
634 | #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 |
635 | #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 |
636 | #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 |
637 | #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L |
638 | #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L |
639 | #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L |
640 | //UVD_MPC_SET_ALU |
641 | #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 |
642 | #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 |
643 | #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L |
644 | #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L |
645 | //UVD_VCPU_CACHE_OFFSET0 |
646 | #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 |
647 | #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL |
648 | //UVD_VCPU_CACHE_SIZE0 |
649 | #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 |
650 | #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL |
651 | //UVD_VCPU_CACHE_OFFSET1 |
652 | #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 |
653 | #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x01FFFFFFL |
654 | //UVD_VCPU_CACHE_SIZE1 |
655 | #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 |
656 | #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL |
657 | //UVD_VCPU_CACHE_OFFSET2 |
658 | #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 |
659 | #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x01FFFFFFL |
660 | //UVD_VCPU_CACHE_SIZE2 |
661 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 |
662 | #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL |
663 | //UVD_VCPU_CNTL |
664 | #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 |
665 | #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L |
666 | //UVD_SOFT_RESET |
667 | #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 |
668 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 |
669 | #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 |
670 | #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 |
671 | #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 |
672 | #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 |
673 | #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 |
674 | #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 |
675 | #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 |
676 | #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa |
677 | #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd |
678 | #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe |
679 | #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf |
680 | #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 |
681 | #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 |
682 | #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 |
683 | #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 |
684 | #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 |
685 | #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 |
686 | #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 |
687 | #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a |
688 | #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b |
689 | #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c |
690 | #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d |
691 | #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e |
692 | #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f |
693 | #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L |
694 | #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L |
695 | #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L |
696 | #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L |
697 | #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L |
698 | #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L |
699 | #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L |
700 | #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L |
701 | #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L |
702 | #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L |
703 | #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L |
704 | #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L |
705 | #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L |
706 | #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L |
707 | #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L |
708 | #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L |
709 | #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L |
710 | #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L |
711 | #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L |
712 | #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L |
713 | #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L |
714 | #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L |
715 | #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L |
716 | #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L |
717 | #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L |
718 | #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L |
719 | //UVD_LMI_RBC_IB_VMID |
720 | #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 |
721 | #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL |
722 | //UVD_RBC_IB_SIZE |
723 | #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 |
724 | #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L |
725 | //UVD_RBC_RB_RPTR |
726 | #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 |
727 | #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L |
728 | //UVD_RBC_RB_WPTR |
729 | #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 |
730 | #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L |
731 | //UVD_RBC_RB_WPTR_CNTL |
732 | #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 |
733 | #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL |
734 | //UVD_RBC_RB_CNTL |
735 | #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
736 | #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
737 | #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 |
738 | #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 |
739 | #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 |
740 | #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c |
741 | #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL |
742 | #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L |
743 | #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L |
744 | #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L |
745 | #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L |
746 | #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L |
747 | //UVD_RBC_RB_RPTR_ADDR |
748 | #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 |
749 | #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL |
750 | //UVD_STATUS |
751 | #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 |
752 | #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 |
753 | #define UVD_STATUS__AVP_BUSY__SHIFT 0x8 |
754 | #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 |
755 | #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb |
756 | #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc |
757 | #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd |
758 | #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe |
759 | #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf |
760 | #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 |
761 | #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f |
762 | #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L |
763 | #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL |
764 | #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L |
765 | #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L |
766 | #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L |
767 | #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L |
768 | #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L |
769 | #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L |
770 | #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L |
771 | #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L |
772 | #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L |
773 | //UVD_SEMA_TIMEOUT_STATUS |
774 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 |
775 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 |
776 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 |
777 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 |
778 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L |
779 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L |
780 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L |
781 | #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L |
782 | //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL |
783 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 |
784 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 |
785 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
786 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L |
787 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL |
788 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
789 | //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL |
790 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 |
791 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 |
792 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
793 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L |
794 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL |
795 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
796 | //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL |
797 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 |
798 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 |
799 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 |
800 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L |
801 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL |
802 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L |
803 | //UVD_CONTEXT_ID |
804 | #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 |
805 | #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL |
806 | //UVD_CONTEXT_ID2 |
807 | #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 |
808 | #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL |
809 | |
810 | //UVD_FW_STATUS |
811 | #define UVD_FW_STATUS__BUSY__SHIFT 0x0 |
812 | #define UVD_FW_STATUS__ACTIVE__SHIFT 0x1 |
813 | #define UVD_FW_STATUS__SEND_EFUSE_REQ__SHIFT 0x2 |
814 | #define UVD_FW_STATUS__DONE__SHIFT 0x8 |
815 | #define UVD_FW_STATUS__PASS__SHIFT 0x10 |
816 | #define UVD_FW_STATUS__FAIL__SHIFT 0x11 |
817 | #define UVD_FW_STATUS__INVALID_LEN__SHIFT 0x12 |
818 | #define UVD_FW_STATUS__INVALID_0_PADDING__SHIFT 0x13 |
819 | #define UVD_FW_STATUS__INVALID_NONCE__SHIFT 0x14 |
820 | #define UVD_FW_STATUS__BUSY_MASK 0x00000001L |
821 | #define UVD_FW_STATUS__ACTIVE_MASK 0x00000002L |
822 | #define UVD_FW_STATUS__SEND_EFUSE_REQ_MASK 0x00000004L |
823 | #define UVD_FW_STATUS__DONE_MASK 0x00000100L |
824 | #define UVD_FW_STATUS__PASS_MASK 0x00010000L |
825 | #define UVD_FW_STATUS__FAIL_MASK 0x00020000L |
826 | #define UVD_FW_STATUS__INVALID_LEN_MASK 0x00040000L |
827 | #define UVD_FW_STATUS__INVALID_0_PADDING_MASK 0x00080000L |
828 | #define UVD_FW_STATUS__INVALID_NONCE_MASK 0x00100000L |
829 | |
830 | |
831 | #endif |
832 | |