| 1 | /* |
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| 2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included |
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| 12 | * in all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | */ |
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| 21 | #ifndef _vce_4_0_OFFSET_HEADER |
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| 22 | #define |
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| 23 | |
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| 24 | |
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| 25 | |
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| 26 | // addressBlock: vce0_vce_dec |
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| 27 | // base address: 0x22000 |
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| 28 | #define mmVCE_STATUS 0x0a01 |
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| 29 | #define mmVCE_STATUS_BASE_IDX 0 |
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| 30 | #define mmVCE_VCPU_CNTL 0x0a05 |
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| 31 | #define mmVCE_VCPU_CNTL_BASE_IDX 0 |
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| 32 | #define mmVCE_VCPU_CACHE_OFFSET0 0x0a09 |
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| 33 | #define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0 |
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| 34 | #define mmVCE_VCPU_CACHE_SIZE0 0x0a0a |
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| 35 | #define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0 |
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| 36 | #define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b |
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| 37 | #define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0 |
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| 38 | #define mmVCE_VCPU_CACHE_SIZE1 0x0a0c |
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| 39 | #define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0 |
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| 40 | #define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d |
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| 41 | #define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0 |
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| 42 | #define mmVCE_VCPU_CACHE_SIZE2 0x0a0e |
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| 43 | #define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0 |
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| 44 | #define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f |
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| 45 | #define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0 |
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| 46 | #define mmVCE_VCPU_CACHE_SIZE3 0x0a10 |
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| 47 | #define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0 |
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| 48 | #define mmVCE_VCPU_CACHE_OFFSET4 0x0a11 |
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| 49 | #define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0 |
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| 50 | #define mmVCE_VCPU_CACHE_SIZE4 0x0a12 |
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| 51 | #define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0 |
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| 52 | #define mmVCE_VCPU_CACHE_OFFSET5 0x0a13 |
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| 53 | #define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0 |
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| 54 | #define mmVCE_VCPU_CACHE_SIZE5 0x0a14 |
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| 55 | #define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0 |
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| 56 | #define mmVCE_VCPU_CACHE_OFFSET6 0x0a15 |
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| 57 | #define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0 |
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| 58 | #define mmVCE_VCPU_CACHE_SIZE6 0x0a16 |
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| 59 | #define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0 |
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| 60 | #define mmVCE_VCPU_CACHE_OFFSET7 0x0a17 |
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| 61 | #define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0 |
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| 62 | #define mmVCE_VCPU_CACHE_SIZE7 0x0a18 |
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| 63 | #define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0 |
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| 64 | #define mmVCE_VCPU_CACHE_OFFSET8 0x0a19 |
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| 65 | #define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0 |
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| 66 | #define mmVCE_VCPU_CACHE_SIZE8 0x0a1a |
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| 67 | #define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0 |
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| 68 | #define mmVCE_SOFT_RESET 0x0a48 |
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| 69 | #define mmVCE_SOFT_RESET_BASE_IDX 0 |
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| 70 | #define mmVCE_RB_BASE_LO2 0x0a5b |
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| 71 | #define mmVCE_RB_BASE_LO2_BASE_IDX 0 |
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| 72 | #define mmVCE_RB_BASE_HI2 0x0a5c |
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| 73 | #define mmVCE_RB_BASE_HI2_BASE_IDX 0 |
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| 74 | #define mmVCE_RB_SIZE2 0x0a5d |
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| 75 | #define mmVCE_RB_SIZE2_BASE_IDX 0 |
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| 76 | #define mmVCE_RB_RPTR2 0x0a5e |
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| 77 | #define mmVCE_RB_RPTR2_BASE_IDX 0 |
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| 78 | #define mmVCE_RB_WPTR2 0x0a5f |
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| 79 | #define mmVCE_RB_WPTR2_BASE_IDX 0 |
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| 80 | #define mmVCE_RB_BASE_LO 0x0a60 |
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| 81 | #define mmVCE_RB_BASE_LO_BASE_IDX 0 |
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| 82 | #define mmVCE_RB_BASE_HI 0x0a61 |
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| 83 | #define mmVCE_RB_BASE_HI_BASE_IDX 0 |
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| 84 | #define mmVCE_RB_SIZE 0x0a62 |
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| 85 | #define mmVCE_RB_SIZE_BASE_IDX 0 |
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| 86 | #define mmVCE_RB_RPTR 0x0a63 |
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| 87 | #define mmVCE_RB_RPTR_BASE_IDX 0 |
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| 88 | #define mmVCE_RB_WPTR 0x0a64 |
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| 89 | #define mmVCE_RB_WPTR_BASE_IDX 0 |
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| 90 | #define mmVCE_RB_ARB_CTRL 0x0a9f |
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| 91 | #define mmVCE_RB_ARB_CTRL_BASE_IDX 0 |
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| 92 | #define mmVCE_CLOCK_GATING_A 0x0abe |
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| 93 | #define mmVCE_CLOCK_GATING_A_BASE_IDX 0 |
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| 94 | #define mmVCE_CLOCK_GATING_B 0x0abf |
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| 95 | #define mmVCE_CLOCK_GATING_B_BASE_IDX 0 |
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| 96 | #define mmVCE_RB_BASE_LO3 0x0ad4 |
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| 97 | #define mmVCE_RB_BASE_LO3_BASE_IDX 0 |
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| 98 | #define mmVCE_RB_BASE_HI3 0x0ad5 |
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| 99 | #define mmVCE_RB_BASE_HI3_BASE_IDX 0 |
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| 100 | #define mmVCE_RB_SIZE3 0x0ad6 |
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| 101 | #define mmVCE_RB_SIZE3_BASE_IDX 0 |
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| 102 | #define mmVCE_RB_RPTR3 0x0ad7 |
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| 103 | #define mmVCE_RB_RPTR3_BASE_IDX 0 |
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| 104 | #define mmVCE_RB_WPTR3 0x0ad8 |
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| 105 | #define mmVCE_RB_WPTR3_BASE_IDX 0 |
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| 106 | #define mmVCE_SYS_INT_EN 0x0b00 |
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| 107 | #define mmVCE_SYS_INT_EN_BASE_IDX 0 |
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| 108 | #define mmVCE_SYS_INT_ACK 0x0b01 |
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| 109 | #define mmVCE_SYS_INT_ACK_BASE_IDX 0 |
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| 110 | #define mmVCE_SYS_INT_STATUS 0x0b01 |
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| 111 | #define mmVCE_SYS_INT_STATUS_BASE_IDX 0 |
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| 112 | |
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| 113 | |
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| 114 | // addressBlock: vce0_ctl_dec |
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| 115 | // base address: 0x22780 |
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| 116 | #define mmVCE_UENC_CLOCK_GATING 0x0bef |
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| 117 | #define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0 |
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| 118 | #define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0 |
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| 119 | #define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0 |
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| 120 | #define mmVCE_UENC_CLOCK_GATING_2 0x0c10 |
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| 121 | #define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0 |
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| 122 | |
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| 123 | |
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| 124 | // addressBlock: vce0_vce_sclk_dec |
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| 125 | // base address: 0x23700 |
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| 126 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc |
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| 127 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0 |
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| 128 | #define mmVCE_LMI_CTRL2 0x0fcf |
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| 129 | #define mmVCE_LMI_CTRL2_BASE_IDX 0 |
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| 130 | #define mmVCE_LMI_SWAP_CNTL3 0x0fd0 |
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| 131 | #define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0 |
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| 132 | #define mmVCE_LMI_CTRL 0x0fd6 |
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| 133 | #define mmVCE_LMI_CTRL_BASE_IDX 0 |
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| 134 | #define mmVCE_LMI_STATUS 0x0fd7 |
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| 135 | #define mmVCE_LMI_STATUS_BASE_IDX 0 |
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| 136 | #define mmVCE_LMI_VM_CTRL 0x0fd8 |
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| 137 | #define mmVCE_LMI_VM_CTRL_BASE_IDX 0 |
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| 138 | #define mmVCE_LMI_SWAP_CNTL 0x0fdd |
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| 139 | #define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0 |
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| 140 | #define mmVCE_LMI_SWAP_CNTL1 0x0fde |
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| 141 | #define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0 |
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| 142 | #define mmVCE_LMI_SWAP_CNTL2 0x0fe2 |
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| 143 | #define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0 |
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| 144 | #define mmVCE_LMI_CACHE_CTRL 0x0fec |
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| 145 | #define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0 |
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| 146 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086 |
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| 147 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0 |
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| 148 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087 |
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| 149 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0 |
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| 150 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088 |
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| 151 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0 |
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| 152 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089 |
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| 153 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0 |
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| 154 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a |
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| 155 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0 |
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| 156 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b |
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| 157 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0 |
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| 158 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c |
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| 159 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0 |
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| 160 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d |
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| 161 | #define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0 |
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| 162 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096 |
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| 163 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0 |
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| 164 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097 |
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| 165 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0 |
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| 166 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098 |
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| 167 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0 |
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| 168 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099 |
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| 169 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0 |
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| 170 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a |
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| 171 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0 |
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| 172 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b |
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| 173 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0 |
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| 174 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c |
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| 175 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0 |
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| 176 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d |
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| 177 | #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0 |
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| 178 | |
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| 179 | |
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| 180 | // addressBlock: vce0_mmsch_dec |
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| 181 | // base address: 0x23b00 |
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| 182 | #define mmVCE_MMSCH_VF_VMID 0x10cb |
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| 183 | #define mmVCE_MMSCH_VF_VMID_BASE_IDX 0 |
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| 184 | #define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc |
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| 185 | #define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0 |
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| 186 | #define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd |
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| 187 | #define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0 |
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| 188 | #define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce |
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| 189 | #define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0 |
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| 190 | #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf |
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| 191 | #define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0 |
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| 192 | #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0 |
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| 193 | #define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0 |
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| 194 | #define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1 |
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| 195 | #define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0 |
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| 196 | #define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2 |
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| 197 | #define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0 |
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| 198 | #define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3 |
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| 199 | #define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0 |
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| 200 | |
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| 201 | |
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| 202 | // addressBlock: vce0_vce_rb_pg_dec |
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| 203 | // base address: 0x23fa0 |
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| 204 | #define mmVCE_HW_VERSION 0x11e8 |
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| 205 | #define mmVCE_HW_VERSION_BASE_IDX 0 |
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| 206 | |
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| 207 | |
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| 208 | #endif |
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| 209 | |
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