1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type{
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60,
183};
184
185enum atom_dp_vs_preemph_def{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
196};
197
198
199/*
200enum atom_string_def{
201asic_bus_type_pcie_string = "PCI_EXPRESS",
202atom_fire_gl_string = "FGL",
203atom_bios_string = "ATOM"
204};
205*/
206
207#pragma pack(1) /* BIOS data must use byte aligment*/
208
209enum atombios_image_offset{
210OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
211OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
212OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
213MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
214OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
215OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
216};
217
218/****************************************************************************
219* Common header for all tables (Data table, Command function).
220* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
221* And the pointer actually points to this header.
222****************************************************************************/
223
224struct atom_common_table_header
225{
226 uint16_t structuresize;
227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
229};
230
231/****************************************************************************
232* Structure stores the ROM header.
233****************************************************************************/
234struct atom_rom_header_v2_2
235{
236 struct atom_common_table_header table_header;
237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
238 uint16_t bios_segment_address;
239 uint16_t protectedmodeoffset;
240 uint16_t configfilenameoffset;
241 uint16_t crc_block_offset;
242 uint16_t vbios_bootupmessageoffset;
243 uint16_t int10_offset;
244 uint16_t pcibusdevinitcode;
245 uint16_t iobaseaddress;
246 uint16_t subsystem_vendor_id;
247 uint16_t subsystem_id;
248 uint16_t pci_info_offset;
249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
251 uint16_t reserved;
252 uint32_t pspdirtableoffset;
253};
254
255/*==============================hw function portion======================================================================*/
256
257
258/****************************************************************************
259* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
260* The real functionality of each function is associated with the parameter structure version when defined
261* For all internal cmd function definitions, please reference to atomstruct.h
262****************************************************************************/
263struct atom_master_list_of_command_functions_v2_1{
264 uint16_t asic_init; //Function
265 uint16_t cmd_function1; //used as an internal one
266 uint16_t cmd_function2; //used as an internal one
267 uint16_t cmd_function3; //used as an internal one
268 uint16_t digxencodercontrol; //Function
269 uint16_t cmd_function5; //used as an internal one
270 uint16_t cmd_function6; //used as an internal one
271 uint16_t cmd_function7; //used as an internal one
272 uint16_t cmd_function8; //used as an internal one
273 uint16_t cmd_function9; //used as an internal one
274 uint16_t setengineclock; //Function
275 uint16_t setmemoryclock; //Function
276 uint16_t setpixelclock; //Function
277 uint16_t enabledisppowergating; //Function
278 uint16_t cmd_function14; //used as an internal one
279 uint16_t cmd_function15; //used as an internal one
280 uint16_t cmd_function16; //used as an internal one
281 uint16_t cmd_function17; //used as an internal one
282 uint16_t cmd_function18; //used as an internal one
283 uint16_t cmd_function19; //used as an internal one
284 uint16_t cmd_function20; //used as an internal one
285 uint16_t cmd_function21; //used as an internal one
286 uint16_t cmd_function22; //used as an internal one
287 uint16_t cmd_function23; //used as an internal one
288 uint16_t cmd_function24; //used as an internal one
289 uint16_t cmd_function25; //used as an internal one
290 uint16_t cmd_function26; //used as an internal one
291 uint16_t cmd_function27; //used as an internal one
292 uint16_t cmd_function28; //used as an internal one
293 uint16_t cmd_function29; //used as an internal one
294 uint16_t cmd_function30; //used as an internal one
295 uint16_t cmd_function31; //used as an internal one
296 uint16_t cmd_function32; //used as an internal one
297 uint16_t cmd_function33; //used as an internal one
298 uint16_t blankcrtc; //Function
299 uint16_t enablecrtc; //Function
300 uint16_t cmd_function36; //used as an internal one
301 uint16_t cmd_function37; //used as an internal one
302 uint16_t cmd_function38; //used as an internal one
303 uint16_t cmd_function39; //used as an internal one
304 uint16_t cmd_function40; //used as an internal one
305 uint16_t getsmuclockinfo; //Function
306 uint16_t selectcrtc_source; //Function
307 uint16_t cmd_function43; //used as an internal one
308 uint16_t cmd_function44; //used as an internal one
309 uint16_t cmd_function45; //used as an internal one
310 uint16_t setdceclock; //Function
311 uint16_t getmemoryclock; //Function
312 uint16_t getengineclock; //Function
313 uint16_t setcrtc_usingdtdtiming; //Function
314 uint16_t externalencodercontrol; //Function
315 uint16_t cmd_function51; //used as an internal one
316 uint16_t cmd_function52; //used as an internal one
317 uint16_t cmd_function53; //used as an internal one
318 uint16_t processi2cchanneltransaction;//Function
319 uint16_t cmd_function55; //used as an internal one
320 uint16_t cmd_function56; //used as an internal one
321 uint16_t cmd_function57; //used as an internal one
322 uint16_t cmd_function58; //used as an internal one
323 uint16_t cmd_function59; //used as an internal one
324 uint16_t computegpuclockparam; //Function
325 uint16_t cmd_function61; //used as an internal one
326 uint16_t cmd_function62; //used as an internal one
327 uint16_t dynamicmemorysettings; //Function function
328 uint16_t memorytraining; //Function function
329 uint16_t cmd_function65; //used as an internal one
330 uint16_t cmd_function66; //used as an internal one
331 uint16_t setvoltage; //Function
332 uint16_t cmd_function68; //used as an internal one
333 uint16_t readefusevalue; //Function
334 uint16_t cmd_function70; //used as an internal one
335 uint16_t cmd_function71; //used as an internal one
336 uint16_t cmd_function72; //used as an internal one
337 uint16_t cmd_function73; //used as an internal one
338 uint16_t cmd_function74; //used as an internal one
339 uint16_t cmd_function75; //used as an internal one
340 uint16_t dig1transmittercontrol; //Function
341 uint16_t cmd_function77; //used as an internal one
342 uint16_t processauxchanneltransaction;//Function
343 uint16_t cmd_function79; //used as an internal one
344 uint16_t getvoltageinfo; //Function
345};
346
347struct atom_master_command_function_v2_1
348{
349 struct atom_common_table_header table_header;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
351};
352
353/****************************************************************************
354* Structures used in every command function
355****************************************************************************/
356struct atom_function_attribute
357{
358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
361};
362
363
364/****************************************************************************
365* Common header for all hw functions.
366* Every function pointed by _master_list_of_hw_function has this common header.
367* And the pointer actually points to this header.
368****************************************************************************/
369struct atom_rom_hw_function_header
370{
371 struct atom_common_table_header func_header;
372 struct atom_function_attribute func_attrib;
373};
374
375
376/*==============================sw data table portion======================================================================*/
377/****************************************************************************
378* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
379* The real name of each table is given when its data structure version is defined
380****************************************************************************/
381struct atom_master_list_of_data_tables_v2_1{
382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
383 uint16_t multimedia_info;
384 uint16_t smc_dpm_info;
385 uint16_t sw_datatable3;
386 uint16_t firmwareinfo; /* Shared by various SW components */
387 uint16_t sw_datatable5;
388 uint16_t lcd_info; /* Shared by various SW components */
389 uint16_t sw_datatable7;
390 uint16_t smu_info;
391 uint16_t sw_datatable9;
392 uint16_t sw_datatable10;
393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
394 uint16_t gpio_pin_lut; /* Shared by various SW components */
395 uint16_t sw_datatable13;
396 uint16_t gfx_info;
397 uint16_t powerplayinfo; /* Shared by various SW components */
398 uint16_t sw_datatable16;
399 uint16_t sw_datatable17;
400 uint16_t sw_datatable18;
401 uint16_t sw_datatable19;
402 uint16_t sw_datatable20;
403 uint16_t sw_datatable21;
404 uint16_t displayobjectinfo; /* Shared by various SW components */
405 uint16_t indirectioaccess; /* used as an internal one */
406 uint16_t umc_info; /* Shared by various SW components */
407 uint16_t sw_datatable25;
408 uint16_t sw_datatable26;
409 uint16_t dce_info; /* Shared by various SW components */
410 uint16_t vram_info; /* Shared by various SW components */
411 uint16_t sw_datatable29;
412 uint16_t integratedsysteminfo; /* Shared by various SW components */
413 uint16_t asic_profiling_info; /* Shared by various SW components */
414 uint16_t voltageobject_info; /* shared by various SW components */
415 uint16_t sw_datatable33;
416 uint16_t sw_datatable34;
417};
418
419
420struct atom_master_data_table_v2_1
421{
422 struct atom_common_table_header table_header;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
424};
425
426
427struct atom_dtd_format
428{
429 uint16_t pixclk;
430 uint16_t h_active;
431 uint16_t h_blanking_time;
432 uint16_t v_active;
433 uint16_t v_blanking_time;
434 uint16_t h_sync_offset;
435 uint16_t h_sync_width;
436 uint16_t v_sync_offset;
437 uint16_t v_syncwidth;
438 uint16_t reserved;
439 uint16_t reserved0;
440 uint8_t h_border;
441 uint8_t v_border;
442 uint16_t miscinfo;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
445};
446
447/* atom_dtd_format.modemiscinfo defintion */
448enum atom_dtd_format_modemiscinfo{
449 ATOM_HSYNC_POLARITY = 0x0002,
450 ATOM_VSYNC_POLARITY = 0x0004,
451 ATOM_H_REPLICATIONBY2 = 0x0010,
452 ATOM_V_REPLICATIONBY2 = 0x0020,
453 ATOM_INTERLACE = 0x0080,
454 ATOM_COMPOSITESYNC = 0x0040,
455};
456
457
458/* utilitypipeline
459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
460 * the location of it can't change
461*/
462
463
464/*
465 ***************************************************************************
466 Data Table firmwareinfo structure
467 ***************************************************************************
468*/
469
470struct atom_firmware_info_v3_1
471{
472 struct atom_common_table_header table_header;
473 uint32_t firmware_revision;
474 uint32_t bootup_sclk_in10khz;
475 uint32_t bootup_mclk_in10khz;
476 uint32_t firmware_capability; // enum atombios_firmware_capability
477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
479 uint16_t bootup_vddc_mv;
480 uint16_t bootup_vddci_mv;
481 uint16_t bootup_mvddc_mv;
482 uint16_t bootup_vddgfx_mv;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1[2];
486 uint32_t mc_baseaddr_high;
487 uint32_t mc_baseaddr_low;
488 uint32_t reserved2[6];
489};
490
491/* Total 32bit cap indication */
492enum atombios_firmware_capability
493{
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
497};
498
499enum atom_cooling_solution_id{
500 AIR_COOLING = 0x00,
501 LIQUID_COOLING = 0x01
502};
503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
530
531/*
532 ***************************************************************************
533 Data Table lcd_info structure
534 ***************************************************************************
535*/
536
537struct lcd_info_v2_1
538{
539 struct atom_common_table_header table_header;
540 struct atom_dtd_format lcd_timing;
541 uint16_t backlight_pwm;
542 uint16_t special_handle_cap;
543 uint16_t panel_misc;
544 uint16_t lvds_max_slink_pclk;
545 uint16_t lvds_ss_percentage;
546 uint16_t lvds_ss_rate_10hz;
547 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
548 uint8_t pwr_on_de_to_vary_bl;
549 uint8_t pwr_down_vary_bloff_to_de;
550 uint8_t pwr_down_de_to_digoff;
551 uint8_t pwr_off_delay;
552 uint8_t pwr_on_vary_bl_to_blon;
553 uint8_t pwr_down_bloff_to_vary_bloff;
554 uint8_t panel_bpc;
555 uint8_t dpcd_edp_config_cap;
556 uint8_t dpcd_max_link_rate;
557 uint8_t dpcd_max_lane_count;
558 uint8_t dpcd_max_downspread;
559 uint8_t min_allowed_bl_level;
560 uint8_t max_allowed_bl_level;
561 uint8_t bootup_bl_level;
562 uint8_t dplvdsrxid;
563 uint32_t reserved1[8];
564};
565
566/* lcd_info_v2_1.panel_misc defintion */
567enum atom_lcd_info_panel_misc{
568 ATOM_PANEL_MISC_FPDI =0x0002,
569};
570
571//uceDPToLVDSRxId
572enum atom_lcd_info_dptolvds_rx_id
573{
574 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
575 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
576 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
577};
578
579
580/*
581 ***************************************************************************
582 Data Table gpio_pin_lut structure
583 ***************************************************************************
584*/
585
586struct atom_gpio_pin_assignment
587{
588 uint32_t data_a_reg_index;
589 uint8_t gpio_bitshift;
590 uint8_t gpio_mask_bitshift;
591 uint8_t gpio_id;
592 uint8_t reserved;
593};
594
595/* atom_gpio_pin_assignment.gpio_id definition */
596enum atom_gpio_pin_assignment_gpio_id {
597 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
598 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
599 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
600
601 /* gpio_id pre-define id for multiple usage */
602 /* GPIO use to control PCIE_VDDC in certain SLT board */
603 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
604 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
605 PP_AC_DC_SWITCH_GPIO_PINID = 60,
606 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
607 VDDC_VRHOT_GPIO_PINID = 61,
608 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
609 VDDC_PCC_GPIO_PINID = 62,
610 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
611 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
612 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
613 DRAM_SELF_REFRESH_GPIO_PINID = 64,
614 /* Thermal interrupt output->system thermal chip GPIO pin */
615 THERMAL_INT_OUTPUT_GPIO_PINID =65,
616};
617
618
619struct atom_gpio_pin_lut_v2_1
620{
621 struct atom_common_table_header table_header;
622 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
623 struct atom_gpio_pin_assignment gpio_pin[8];
624};
625
626
627/*
628 ***************************************************************************
629 Data Table vram_usagebyfirmware structure
630 ***************************************************************************
631*/
632
633struct vram_usagebyfirmware_v2_1
634{
635 struct atom_common_table_header table_header;
636 uint32_t start_address_in_kb;
637 uint16_t used_by_firmware_in_kb;
638 uint16_t used_by_driver_in_kb;
639};
640
641
642/*
643 ***************************************************************************
644 Data Table displayobjectinfo structure
645 ***************************************************************************
646*/
647
648enum atom_object_record_type_id
649{
650 ATOM_I2C_RECORD_TYPE =1,
651 ATOM_HPD_INT_RECORD_TYPE =2,
652 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
653 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
654 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
655 ATOM_ENCODER_CAP_RECORD_TYPE=20,
656 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
657 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
658 ATOM_RECORD_END_TYPE =0xFF,
659};
660
661struct atom_common_record_header
662{
663 uint8_t record_type; //An emun to indicate the record type
664 uint8_t record_size; //The size of the whole record in byte
665};
666
667struct atom_i2c_record
668{
669 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
670 uint8_t i2c_id;
671 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
672};
673
674struct atom_hpd_int_record
675{
676 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
677 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
678 uint8_t plugin_pin_state;
679};
680
681// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
682enum atom_encoder_caps_def
683{
684 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
685 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
686 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
687 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
688 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
689};
690
691struct atom_encoder_caps_record
692{
693 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
694 uint32_t encodercaps;
695};
696
697enum atom_connector_caps_def
698{
699 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
700 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
701};
702
703struct atom_disp_connector_caps_record
704{
705 struct atom_common_record_header record_header;
706 uint32_t connectcaps;
707};
708
709//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
710struct atom_gpio_pin_control_pair
711{
712 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
713 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
714};
715
716struct atom_object_gpio_cntl_record
717{
718 struct atom_common_record_header record_header;
719 uint8_t flag; // Future expnadibility
720 uint8_t number_of_pins; // Number of GPIO pins used to control the object
721 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
722};
723
724//Definitions for GPIO pin state
725enum atom_gpio_pin_control_pinstate_def
726{
727 GPIO_PIN_TYPE_INPUT = 0x00,
728 GPIO_PIN_TYPE_OUTPUT = 0x10,
729 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
730
731//For GPIO_PIN_TYPE_OUTPUT the following is defined
732 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
733 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
734 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
735 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
736};
737
738// Indexes to GPIO array in GLSync record
739// GLSync record is for Frame Lock/Gen Lock feature.
740enum atom_glsync_record_gpio_index_def
741{
742 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
743 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
744 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
745 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
746 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
747 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
748 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
749 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
750 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
751 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
752};
753
754
755struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
756{
757 struct atom_common_record_header record_header;
758 uint8_t hpd_pin_map[8];
759};
760
761struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
762{
763 struct atom_common_record_header record_header;
764 uint8_t aux_ddc_map[8];
765};
766
767struct atom_connector_forced_tmds_cap_record
768{
769 struct atom_common_record_header record_header;
770 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
771 uint8_t maxtmdsclkrate_in2_5mhz;
772 uint8_t reserved;
773};
774
775struct atom_connector_layout_info
776{
777 uint16_t connectorobjid;
778 uint8_t connector_type;
779 uint8_t position;
780};
781
782// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
783enum atom_connector_layout_info_connector_type_def
784{
785 CONNECTOR_TYPE_DVI_D = 1,
786
787 CONNECTOR_TYPE_HDMI = 4,
788 CONNECTOR_TYPE_DISPLAY_PORT = 5,
789 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
790};
791
792struct atom_bracket_layout_record
793{
794 struct atom_common_record_header record_header;
795 uint8_t bracketlen;
796 uint8_t bracketwidth;
797 uint8_t conn_num;
798 uint8_t reserved;
799 struct atom_connector_layout_info conn_info[1];
800};
801
802enum atom_display_device_tag_def{
803 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
804 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
805 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
806 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
807 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
808 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
809 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
810 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
811};
812
813struct atom_display_object_path_v2
814{
815 uint16_t display_objid; //Connector Object ID or Misc Object ID
816 uint16_t disp_recordoffset;
817 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
818 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
819 uint16_t encoder_recordoffset;
820 uint16_t extencoder_recordoffset;
821 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
822 uint8_t priority_id;
823 uint8_t reserved;
824};
825
826struct display_object_info_table_v1_4
827{
828 struct atom_common_table_header table_header;
829 uint16_t supporteddevices;
830 uint8_t number_of_path;
831 uint8_t reserved;
832 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
833};
834
835
836/*
837 ***************************************************************************
838 Data Table dce_info structure
839 ***************************************************************************
840*/
841struct atom_display_controller_info_v4_1
842{
843 struct atom_common_table_header table_header;
844 uint32_t display_caps;
845 uint32_t bootup_dispclk_10khz;
846 uint16_t dce_refclk_10khz;
847 uint16_t i2c_engine_refclk_10khz;
848 uint16_t dvi_ss_percentage; // in unit of 0.001%
849 uint16_t dvi_ss_rate_10hz;
850 uint16_t hdmi_ss_percentage; // in unit of 0.001%
851 uint16_t hdmi_ss_rate_10hz;
852 uint16_t dp_ss_percentage; // in unit of 0.001%
853 uint16_t dp_ss_rate_10hz;
854 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
855 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
856 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
857 uint8_t ss_reserved;
858 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
859 uint8_t reserved1[3];
860 uint16_t dpphy_refclk_10khz;
861 uint16_t reserved2;
862 uint8_t dceip_min_ver;
863 uint8_t dceip_max_ver;
864 uint8_t max_disp_pipe_num;
865 uint8_t max_vbios_active_disp_pipe_num;
866 uint8_t max_ppll_num;
867 uint8_t max_disp_phy_num;
868 uint8_t max_aux_pairs;
869 uint8_t remotedisplayconfig;
870 uint8_t reserved3[8];
871};
872
873
874struct atom_display_controller_info_v4_2
875{
876 struct atom_common_table_header table_header;
877 uint32_t display_caps;
878 uint32_t bootup_dispclk_10khz;
879 uint16_t dce_refclk_10khz;
880 uint16_t i2c_engine_refclk_10khz;
881 uint16_t dvi_ss_percentage; // in unit of 0.001%
882 uint16_t dvi_ss_rate_10hz;
883 uint16_t hdmi_ss_percentage; // in unit of 0.001%
884 uint16_t hdmi_ss_rate_10hz;
885 uint16_t dp_ss_percentage; // in unit of 0.001%
886 uint16_t dp_ss_rate_10hz;
887 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
888 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
889 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t ss_reserved;
891 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
892 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
893 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
894 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
895 uint16_t dpphy_refclk_10khz;
896 uint16_t reserved2;
897 uint8_t dcnip_min_ver;
898 uint8_t dcnip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
906};
907
908
909enum dce_info_caps_def
910{
911 // only for VBIOS
912 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
913 // only for VBIOS
914 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
915 // only for VBIOS
916 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
917
918};
919
920/*
921 ***************************************************************************
922 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
923 ***************************************************************************
924*/
925struct atom_ext_display_path
926{
927 uint16_t device_tag; //A bit vector to show what devices are supported
928 uint16_t device_acpi_enum; //16bit device ACPI id.
929 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
930 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
931 uint8_t hpdlut_index; //An index into external HPD pin LUT
932 uint16_t ext_encoder_objid; //external encoder object id
933 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
934 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
935 uint16_t caps;
936 uint16_t reserved;
937};
938
939//usCaps
940enum ext_display_path_cap_def
941{
942 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
943 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
944 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
945};
946
947struct atom_external_display_connection_info
948{
949 struct atom_common_table_header table_header;
950 uint8_t guid[16]; // a GUID is a 16 byte long string
951 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
952 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
953 uint8_t stereopinid; // use for eDP panel
954 uint8_t remotedisplayconfig;
955 uint8_t edptolvdsrxid;
956 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
957 uint8_t reserved[3]; // for potential expansion
958};
959
960/*
961 ***************************************************************************
962 Data Table integratedsysteminfo structure
963 ***************************************************************************
964*/
965
966struct atom_camera_dphy_timing_param
967{
968 uint8_t profile_id; // SENSOR_PROFILES
969 uint32_t param;
970};
971
972struct atom_camera_dphy_elec_param
973{
974 uint16_t param[3];
975};
976
977struct atom_camera_module_info
978{
979 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
980 uint8_t module_name[8];
981 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
982};
983
984struct atom_camera_flashlight_info
985{
986 uint8_t flashlight_id; // 0: Rear, 1: Front
987 uint8_t name[8];
988};
989
990struct atom_camera_data
991{
992 uint32_t versionCode;
993 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
994 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
995 struct atom_camera_dphy_elec_param dphy_param;
996 uint32_t crc_val; // CRC
997};
998
999
1000struct atom_14nm_dpphy_dvihdmi_tuningset
1001{
1002 uint32_t max_symclk_in10khz;
1003 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1004 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1005 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1006 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1007 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1008 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1009 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1010};
1011
1012struct atom_14nm_dpphy_dp_setting{
1013 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1014 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1015 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1016 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1017};
1018
1019struct atom_14nm_dpphy_dp_tuningset{
1020 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1021 uint8_t version;
1022 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1023 uint16_t reserved;
1024 struct atom_14nm_dpphy_dp_setting dptuning[10];
1025};
1026
1027struct atom_14nm_dig_transmitter_info_header_v4_0{
1028 struct atom_common_table_header table_header;
1029 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1030 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1031 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1032};
1033
1034struct atom_14nm_combphy_tmds_vs_set
1035{
1036 uint8_t sym_clk;
1037 uint8_t dig_mode;
1038 uint8_t phy_sel;
1039 uint16_t common_mar_deemph_nom__margin_deemph_val;
1040 uint8_t common_seldeemph60__deemph_6db_4_val;
1041 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1042 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1043 uint8_t margin_deemph_lane0__deemph_sel_val;
1044};
1045
1046struct atom_i2c_reg_info {
1047 uint8_t ucI2cRegIndex;
1048 uint8_t ucI2cRegVal;
1049};
1050
1051struct atom_hdmi_retimer_redriver_set {
1052 uint8_t HdmiSlvAddr;
1053 uint8_t HdmiRegNum;
1054 uint8_t Hdmi6GRegNum;
1055 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1056 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1057};
1058
1059struct atom_integrated_system_info_v1_11
1060{
1061 struct atom_common_table_header table_header;
1062 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1063 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1064 uint32_t system_config;
1065 uint32_t cpucapinfo;
1066 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1067 uint16_t gpuclk_ss_type;
1068 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1069 uint16_t lvds_ss_rate_10hz;
1070 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1071 uint16_t hdmi_ss_rate_10hz;
1072 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1073 uint16_t dvi_ss_rate_10hz;
1074 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1075 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1076 uint16_t backlight_pwm_hz; // pwm frequency in hz
1077 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1078 uint8_t umachannelnumber; // number of memory channels
1079 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1080 uint8_t pwr_on_de_to_vary_bl;
1081 uint8_t pwr_down_vary_bloff_to_de;
1082 uint8_t pwr_down_de_to_digoff;
1083 uint8_t pwr_off_delay;
1084 uint8_t pwr_on_vary_bl_to_blon;
1085 uint8_t pwr_down_bloff_to_vary_bloff;
1086 uint8_t min_allowed_bl_level;
1087 uint8_t htc_hyst_limit;
1088 uint8_t htc_tmp_limit;
1089 uint8_t reserved1;
1090 uint8_t reserved2;
1091 struct atom_external_display_connection_info extdispconninfo;
1092 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1093 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1094 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1095 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set
1096 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set
1097 struct atom_camera_data camera_info;
1098 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1099 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1100 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1101 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1102 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set
1103 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set
1104 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set
1105 uint32_t reserved[66];
1106};
1107
1108
1109// system_config
1110enum atom_system_vbiosmisc_def{
1111 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1112};
1113
1114
1115// gpucapinfo
1116enum atom_system_gpucapinf_def{
1117 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1118};
1119
1120//dpphy_override
1121enum atom_sysinfo_dpphy_override_def{
1122 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1123 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1124 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1125 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1126 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1127};
1128
1129//lvds_misc
1130enum atom_sys_info_lvds_misc_def
1131{
1132 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1133 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1134 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1135};
1136
1137
1138//memorytype DMI Type 17 offset 12h - Memory Type
1139enum atom_dmi_t17_mem_type_def{
1140 OtherMemType = 0x01, ///< Assign 01 to Other
1141 UnknownMemType, ///< Assign 02 to Unknown
1142 DramMemType, ///< Assign 03 to DRAM
1143 EdramMemType, ///< Assign 04 to EDRAM
1144 VramMemType, ///< Assign 05 to VRAM
1145 SramMemType, ///< Assign 06 to SRAM
1146 RamMemType, ///< Assign 07 to RAM
1147 RomMemType, ///< Assign 08 to ROM
1148 FlashMemType, ///< Assign 09 to Flash
1149 EepromMemType, ///< Assign 10 to EEPROM
1150 FepromMemType, ///< Assign 11 to FEPROM
1151 EpromMemType, ///< Assign 12 to EPROM
1152 CdramMemType, ///< Assign 13 to CDRAM
1153 ThreeDramMemType, ///< Assign 14 to 3DRAM
1154 SdramMemType, ///< Assign 15 to SDRAM
1155 SgramMemType, ///< Assign 16 to SGRAM
1156 RdramMemType, ///< Assign 17 to RDRAM
1157 DdrMemType, ///< Assign 18 to DDR
1158 Ddr2MemType, ///< Assign 19 to DDR2
1159 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1160 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1161 Fbd2MemType, ///< Assign 25 to FBD2
1162 Ddr4MemType, ///< Assign 26 to DDR4
1163 LpDdrMemType, ///< Assign 27 to LPDDR
1164 LpDdr2MemType, ///< Assign 28 to LPDDR2
1165 LpDdr3MemType, ///< Assign 29 to LPDDR3
1166 LpDdr4MemType, ///< Assign 30 to LPDDR4
1167};
1168
1169
1170// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1171struct atom_fusion_system_info_v4
1172{
1173 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1174 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1175};
1176
1177
1178/*
1179 ***************************************************************************
1180 Data Table gfx_info structure
1181 ***************************************************************************
1182*/
1183
1184struct atom_gfx_info_v2_2
1185{
1186 struct atom_common_table_header table_header;
1187 uint8_t gfxip_min_ver;
1188 uint8_t gfxip_max_ver;
1189 uint8_t max_shader_engines;
1190 uint8_t max_tile_pipes;
1191 uint8_t max_cu_per_sh;
1192 uint8_t max_sh_per_se;
1193 uint8_t max_backends_per_se;
1194 uint8_t max_texture_channel_caches;
1195 uint32_t regaddr_cp_dma_src_addr;
1196 uint32_t regaddr_cp_dma_src_addr_hi;
1197 uint32_t regaddr_cp_dma_dst_addr;
1198 uint32_t regaddr_cp_dma_dst_addr_hi;
1199 uint32_t regaddr_cp_dma_command;
1200 uint32_t regaddr_cp_status;
1201 uint32_t regaddr_rlc_gpu_clock_32;
1202 uint32_t rlc_gpu_timer_refclk;
1203};
1204
1205struct atom_gfx_info_v2_3 {
1206 struct atom_common_table_header table_header;
1207 uint8_t gfxip_min_ver;
1208 uint8_t gfxip_max_ver;
1209 uint8_t max_shader_engines;
1210 uint8_t max_tile_pipes;
1211 uint8_t max_cu_per_sh;
1212 uint8_t max_sh_per_se;
1213 uint8_t max_backends_per_se;
1214 uint8_t max_texture_channel_caches;
1215 uint32_t regaddr_cp_dma_src_addr;
1216 uint32_t regaddr_cp_dma_src_addr_hi;
1217 uint32_t regaddr_cp_dma_dst_addr;
1218 uint32_t regaddr_cp_dma_dst_addr_hi;
1219 uint32_t regaddr_cp_dma_command;
1220 uint32_t regaddr_cp_status;
1221 uint32_t regaddr_rlc_gpu_clock_32;
1222 uint32_t rlc_gpu_timer_refclk;
1223 uint8_t active_cu_per_sh;
1224 uint8_t active_rb_per_se;
1225 uint16_t gcgoldenoffset;
1226 uint32_t rm21_sram_vmin_value;
1227};
1228
1229struct atom_gfx_info_v2_4 {
1230 struct atom_common_table_header table_header;
1231 uint8_t gfxip_min_ver;
1232 uint8_t gfxip_max_ver;
1233 uint8_t gc_num_se;
1234 uint8_t max_tile_pipes;
1235 uint8_t gc_num_cu_per_sh;
1236 uint8_t gc_num_sh_per_se;
1237 uint8_t gc_num_rb_per_se;
1238 uint8_t gc_num_tccs;
1239 uint32_t regaddr_cp_dma_src_addr;
1240 uint32_t regaddr_cp_dma_src_addr_hi;
1241 uint32_t regaddr_cp_dma_dst_addr;
1242 uint32_t regaddr_cp_dma_dst_addr_hi;
1243 uint32_t regaddr_cp_dma_command;
1244 uint32_t regaddr_cp_status;
1245 uint32_t regaddr_rlc_gpu_clock_32;
1246 uint32_t rlc_gpu_timer_refclk;
1247 uint8_t active_cu_per_sh;
1248 uint8_t active_rb_per_se;
1249 uint16_t gcgoldenoffset;
1250 uint16_t gc_num_gprs;
1251 uint16_t gc_gsprim_buff_depth;
1252 uint16_t gc_parameter_cache_depth;
1253 uint16_t gc_wave_size;
1254 uint16_t gc_max_waves_per_simd;
1255 uint16_t gc_lds_size;
1256 uint8_t gc_num_max_gs_thds;
1257 uint8_t gc_gs_table_depth;
1258 uint8_t gc_double_offchip_lds_buffer;
1259 uint8_t gc_max_scratch_slots_per_cu;
1260 uint32_t sram_rm_fuses_val;
1261 uint32_t sram_custom_rm_fuses_val;
1262};
1263
1264/*
1265 ***************************************************************************
1266 Data Table smu_info structure
1267 ***************************************************************************
1268*/
1269struct atom_smu_info_v3_1
1270{
1271 struct atom_common_table_header table_header;
1272 uint8_t smuip_min_ver;
1273 uint8_t smuip_max_ver;
1274 uint8_t smu_rsd1;
1275 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1276 uint16_t sclk_ss_percentage;
1277 uint16_t sclk_ss_rate_10hz;
1278 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1279 uint16_t gpuclk_ss_rate_10hz;
1280 uint32_t core_refclk_10khz;
1281 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1282 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1283 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1284 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1285 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1286 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1287 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1288 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1289};
1290
1291struct atom_smu_info_v3_2 {
1292 struct atom_common_table_header table_header;
1293 uint8_t smuip_min_ver;
1294 uint8_t smuip_max_ver;
1295 uint8_t smu_rsd1;
1296 uint8_t gpuclk_ss_mode;
1297 uint16_t sclk_ss_percentage;
1298 uint16_t sclk_ss_rate_10hz;
1299 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1300 uint16_t gpuclk_ss_rate_10hz;
1301 uint32_t core_refclk_10khz;
1302 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1303 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1304 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1305 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1306 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1307 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1308 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1309 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1310 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1311 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1312 uint16_t smugoldenoffset;
1313 uint32_t gpupll_vco_freq_10khz;
1314 uint32_t bootup_smnclk_10khz;
1315 uint32_t bootup_socclk_10khz;
1316 uint32_t bootup_mp0clk_10khz;
1317 uint32_t bootup_mp1clk_10khz;
1318 uint32_t bootup_lclk_10khz;
1319 uint32_t bootup_dcefclk_10khz;
1320 uint32_t ctf_threshold_override_value;
1321 uint32_t reserved[5];
1322};
1323
1324struct atom_smu_info_v3_3 {
1325 struct atom_common_table_header table_header;
1326 uint8_t smuip_min_ver;
1327 uint8_t smuip_max_ver;
1328 uint8_t waflclk_ss_mode;
1329 uint8_t gpuclk_ss_mode;
1330 uint16_t sclk_ss_percentage;
1331 uint16_t sclk_ss_rate_10hz;
1332 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1333 uint16_t gpuclk_ss_rate_10hz;
1334 uint32_t core_refclk_10khz;
1335 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1336 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1337 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1338 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1339 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1340 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1341 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1342 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1343 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1344 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1345 uint16_t smugoldenoffset;
1346 uint32_t gpupll_vco_freq_10khz;
1347 uint32_t bootup_smnclk_10khz;
1348 uint32_t bootup_socclk_10khz;
1349 uint32_t bootup_mp0clk_10khz;
1350 uint32_t bootup_mp1clk_10khz;
1351 uint32_t bootup_lclk_10khz;
1352 uint32_t bootup_dcefclk_10khz;
1353 uint32_t ctf_threshold_override_value;
1354 uint32_t syspll3_0_vco_freq_10khz;
1355 uint32_t syspll3_1_vco_freq_10khz;
1356 uint32_t bootup_fclk_10khz;
1357 uint32_t bootup_waflclk_10khz;
1358 uint32_t smu_info_caps;
1359 uint16_t waflclk_ss_percentage; // in unit of 0.001%
1360 uint16_t smuinitoffset;
1361 uint32_t reserved;
1362};
1363
1364/*
1365 ***************************************************************************
1366 Data Table smc_dpm_info structure
1367 ***************************************************************************
1368 */
1369struct atom_smc_dpm_info_v4_1
1370{
1371 struct atom_common_table_header table_header;
1372 uint8_t liquid1_i2c_address;
1373 uint8_t liquid2_i2c_address;
1374 uint8_t vr_i2c_address;
1375 uint8_t plx_i2c_address;
1376
1377 uint8_t liquid_i2c_linescl;
1378 uint8_t liquid_i2c_linesda;
1379 uint8_t vr_i2c_linescl;
1380 uint8_t vr_i2c_linesda;
1381
1382 uint8_t plx_i2c_linescl;
1383 uint8_t plx_i2c_linesda;
1384 uint8_t vrsensorpresent;
1385 uint8_t liquidsensorpresent;
1386
1387 uint16_t maxvoltagestepgfx;
1388 uint16_t maxvoltagestepsoc;
1389
1390 uint8_t vddgfxvrmapping;
1391 uint8_t vddsocvrmapping;
1392 uint8_t vddmem0vrmapping;
1393 uint8_t vddmem1vrmapping;
1394
1395 uint8_t gfxulvphasesheddingmask;
1396 uint8_t soculvphasesheddingmask;
1397 uint8_t padding8_v[2];
1398
1399 uint16_t gfxmaxcurrent;
1400 uint8_t gfxoffset;
1401 uint8_t padding_telemetrygfx;
1402
1403 uint16_t socmaxcurrent;
1404 uint8_t socoffset;
1405 uint8_t padding_telemetrysoc;
1406
1407 uint16_t mem0maxcurrent;
1408 uint8_t mem0offset;
1409 uint8_t padding_telemetrymem0;
1410
1411 uint16_t mem1maxcurrent;
1412 uint8_t mem1offset;
1413 uint8_t padding_telemetrymem1;
1414
1415 uint8_t acdcgpio;
1416 uint8_t acdcpolarity;
1417 uint8_t vr0hotgpio;
1418 uint8_t vr0hotpolarity;
1419
1420 uint8_t vr1hotgpio;
1421 uint8_t vr1hotpolarity;
1422 uint8_t padding1;
1423 uint8_t padding2;
1424
1425 uint8_t ledpin0;
1426 uint8_t ledpin1;
1427 uint8_t ledpin2;
1428 uint8_t padding8_4;
1429
1430 uint8_t pllgfxclkspreadenabled;
1431 uint8_t pllgfxclkspreadpercent;
1432 uint16_t pllgfxclkspreadfreq;
1433
1434 uint8_t uclkspreadenabled;
1435 uint8_t uclkspreadpercent;
1436 uint16_t uclkspreadfreq;
1437
1438 uint8_t socclkspreadenabled;
1439 uint8_t socclkspreadpercent;
1440 uint16_t socclkspreadfreq;
1441
1442 uint8_t acggfxclkspreadenabled;
1443 uint8_t acggfxclkspreadpercent;
1444 uint16_t acggfxclkspreadfreq;
1445
1446 uint8_t Vr2_I2C_address;
1447 uint8_t padding_vr2[3];
1448
1449 uint32_t boardreserved[9];
1450};
1451
1452/*
1453 ***************************************************************************
1454 Data Table smc_dpm_info structure
1455 ***************************************************************************
1456 */
1457struct atom_smc_dpm_info_v4_3
1458{
1459 struct atom_common_table_header table_header;
1460 uint8_t liquid1_i2c_address;
1461 uint8_t liquid2_i2c_address;
1462 uint8_t vr_i2c_address;
1463 uint8_t plx_i2c_address;
1464
1465 uint8_t liquid_i2c_linescl;
1466 uint8_t liquid_i2c_linesda;
1467 uint8_t vr_i2c_linescl;
1468 uint8_t vr_i2c_linesda;
1469
1470 uint8_t plx_i2c_linescl;
1471 uint8_t plx_i2c_linesda;
1472 uint8_t vrsensorpresent;
1473 uint8_t liquidsensorpresent;
1474
1475 uint16_t maxvoltagestepgfx;
1476 uint16_t maxvoltagestepsoc;
1477
1478 uint8_t vddgfxvrmapping;
1479 uint8_t vddsocvrmapping;
1480 uint8_t vddmem0vrmapping;
1481 uint8_t vddmem1vrmapping;
1482
1483 uint8_t gfxulvphasesheddingmask;
1484 uint8_t soculvphasesheddingmask;
1485 uint8_t externalsensorpresent;
1486 uint8_t padding8_v;
1487
1488 uint16_t gfxmaxcurrent;
1489 uint8_t gfxoffset;
1490 uint8_t padding_telemetrygfx;
1491
1492 uint16_t socmaxcurrent;
1493 uint8_t socoffset;
1494 uint8_t padding_telemetrysoc;
1495
1496 uint16_t mem0maxcurrent;
1497 uint8_t mem0offset;
1498 uint8_t padding_telemetrymem0;
1499
1500 uint16_t mem1maxcurrent;
1501 uint8_t mem1offset;
1502 uint8_t padding_telemetrymem1;
1503
1504 uint8_t acdcgpio;
1505 uint8_t acdcpolarity;
1506 uint8_t vr0hotgpio;
1507 uint8_t vr0hotpolarity;
1508
1509 uint8_t vr1hotgpio;
1510 uint8_t vr1hotpolarity;
1511 uint8_t padding1;
1512 uint8_t padding2;
1513
1514 uint8_t ledpin0;
1515 uint8_t ledpin1;
1516 uint8_t ledpin2;
1517 uint8_t padding8_4;
1518
1519 uint8_t pllgfxclkspreadenabled;
1520 uint8_t pllgfxclkspreadpercent;
1521 uint16_t pllgfxclkspreadfreq;
1522
1523 uint8_t uclkspreadenabled;
1524 uint8_t uclkspreadpercent;
1525 uint16_t uclkspreadfreq;
1526
1527 uint8_t fclkspreadenabled;
1528 uint8_t fclkspreadpercent;
1529 uint16_t fclkspreadfreq;
1530
1531 uint8_t fllgfxclkspreadenabled;
1532 uint8_t fllgfxclkspreadpercent;
1533 uint16_t fllgfxclkspreadfreq;
1534
1535 uint32_t boardreserved[10];
1536};
1537
1538struct smudpm_i2ccontrollerconfig_t {
1539 uint32_t enabled;
1540 uint32_t slaveaddress;
1541 uint32_t controllerport;
1542 uint32_t controllername;
1543 uint32_t thermalthrottler;
1544 uint32_t i2cprotocol;
1545 uint32_t i2cspeed;
1546};
1547
1548struct atom_smc_dpm_info_v4_4
1549{
1550 struct atom_common_table_header table_header;
1551 uint32_t i2c_padding[3];
1552
1553 uint16_t maxvoltagestepgfx;
1554 uint16_t maxvoltagestepsoc;
1555
1556 uint8_t vddgfxvrmapping;
1557 uint8_t vddsocvrmapping;
1558 uint8_t vddmem0vrmapping;
1559 uint8_t vddmem1vrmapping;
1560
1561 uint8_t gfxulvphasesheddingmask;
1562 uint8_t soculvphasesheddingmask;
1563 uint8_t externalsensorpresent;
1564 uint8_t padding8_v;
1565
1566 uint16_t gfxmaxcurrent;
1567 uint8_t gfxoffset;
1568 uint8_t padding_telemetrygfx;
1569
1570 uint16_t socmaxcurrent;
1571 uint8_t socoffset;
1572 uint8_t padding_telemetrysoc;
1573
1574 uint16_t mem0maxcurrent;
1575 uint8_t mem0offset;
1576 uint8_t padding_telemetrymem0;
1577
1578 uint16_t mem1maxcurrent;
1579 uint8_t mem1offset;
1580 uint8_t padding_telemetrymem1;
1581
1582
1583 uint8_t acdcgpio;
1584 uint8_t acdcpolarity;
1585 uint8_t vr0hotgpio;
1586 uint8_t vr0hotpolarity;
1587
1588 uint8_t vr1hotgpio;
1589 uint8_t vr1hotpolarity;
1590 uint8_t padding1;
1591 uint8_t padding2;
1592
1593
1594 uint8_t ledpin0;
1595 uint8_t ledpin1;
1596 uint8_t ledpin2;
1597 uint8_t padding8_4;
1598
1599
1600 uint8_t pllgfxclkspreadenabled;
1601 uint8_t pllgfxclkspreadpercent;
1602 uint16_t pllgfxclkspreadfreq;
1603
1604
1605 uint8_t uclkspreadenabled;
1606 uint8_t uclkspreadpercent;
1607 uint16_t uclkspreadfreq;
1608
1609
1610 uint8_t fclkspreadenabled;
1611 uint8_t fclkspreadpercent;
1612 uint16_t fclkspreadfreq;
1613
1614
1615 uint8_t fllgfxclkspreadenabled;
1616 uint8_t fllgfxclkspreadpercent;
1617 uint16_t fllgfxclkspreadfreq;
1618
1619
1620 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
1621
1622
1623 uint32_t boardreserved[10];
1624};
1625
1626/*
1627 ***************************************************************************
1628 Data Table asic_profiling_info structure
1629 ***************************************************************************
1630*/
1631struct atom_asic_profiling_info_v4_1
1632{
1633 struct atom_common_table_header table_header;
1634 uint32_t maxvddc;
1635 uint32_t minvddc;
1636 uint32_t avfs_meannsigma_acontant0;
1637 uint32_t avfs_meannsigma_acontant1;
1638 uint32_t avfs_meannsigma_acontant2;
1639 uint16_t avfs_meannsigma_dc_tol_sigma;
1640 uint16_t avfs_meannsigma_platform_mean;
1641 uint16_t avfs_meannsigma_platform_sigma;
1642 uint32_t gb_vdroop_table_cksoff_a0;
1643 uint32_t gb_vdroop_table_cksoff_a1;
1644 uint32_t gb_vdroop_table_cksoff_a2;
1645 uint32_t gb_vdroop_table_ckson_a0;
1646 uint32_t gb_vdroop_table_ckson_a1;
1647 uint32_t gb_vdroop_table_ckson_a2;
1648 uint32_t avfsgb_fuse_table_cksoff_m1;
1649 uint32_t avfsgb_fuse_table_cksoff_m2;
1650 uint32_t avfsgb_fuse_table_cksoff_b;
1651 uint32_t avfsgb_fuse_table_ckson_m1;
1652 uint32_t avfsgb_fuse_table_ckson_m2;
1653 uint32_t avfsgb_fuse_table_ckson_b;
1654 uint16_t max_voltage_0_25mv;
1655 uint8_t enable_gb_vdroop_table_cksoff;
1656 uint8_t enable_gb_vdroop_table_ckson;
1657 uint8_t enable_gb_fuse_table_cksoff;
1658 uint8_t enable_gb_fuse_table_ckson;
1659 uint16_t psm_age_comfactor;
1660 uint8_t enable_apply_avfs_cksoff_voltage;
1661 uint8_t reserved;
1662 uint32_t dispclk2gfxclk_a;
1663 uint32_t dispclk2gfxclk_b;
1664 uint32_t dispclk2gfxclk_c;
1665 uint32_t pixclk2gfxclk_a;
1666 uint32_t pixclk2gfxclk_b;
1667 uint32_t pixclk2gfxclk_c;
1668 uint32_t dcefclk2gfxclk_a;
1669 uint32_t dcefclk2gfxclk_b;
1670 uint32_t dcefclk2gfxclk_c;
1671 uint32_t phyclk2gfxclk_a;
1672 uint32_t phyclk2gfxclk_b;
1673 uint32_t phyclk2gfxclk_c;
1674};
1675
1676struct atom_asic_profiling_info_v4_2 {
1677 struct atom_common_table_header table_header;
1678 uint32_t maxvddc;
1679 uint32_t minvddc;
1680 uint32_t avfs_meannsigma_acontant0;
1681 uint32_t avfs_meannsigma_acontant1;
1682 uint32_t avfs_meannsigma_acontant2;
1683 uint16_t avfs_meannsigma_dc_tol_sigma;
1684 uint16_t avfs_meannsigma_platform_mean;
1685 uint16_t avfs_meannsigma_platform_sigma;
1686 uint32_t gb_vdroop_table_cksoff_a0;
1687 uint32_t gb_vdroop_table_cksoff_a1;
1688 uint32_t gb_vdroop_table_cksoff_a2;
1689 uint32_t gb_vdroop_table_ckson_a0;
1690 uint32_t gb_vdroop_table_ckson_a1;
1691 uint32_t gb_vdroop_table_ckson_a2;
1692 uint32_t avfsgb_fuse_table_cksoff_m1;
1693 uint32_t avfsgb_fuse_table_cksoff_m2;
1694 uint32_t avfsgb_fuse_table_cksoff_b;
1695 uint32_t avfsgb_fuse_table_ckson_m1;
1696 uint32_t avfsgb_fuse_table_ckson_m2;
1697 uint32_t avfsgb_fuse_table_ckson_b;
1698 uint16_t max_voltage_0_25mv;
1699 uint8_t enable_gb_vdroop_table_cksoff;
1700 uint8_t enable_gb_vdroop_table_ckson;
1701 uint8_t enable_gb_fuse_table_cksoff;
1702 uint8_t enable_gb_fuse_table_ckson;
1703 uint16_t psm_age_comfactor;
1704 uint8_t enable_apply_avfs_cksoff_voltage;
1705 uint8_t reserved;
1706 uint32_t dispclk2gfxclk_a;
1707 uint32_t dispclk2gfxclk_b;
1708 uint32_t dispclk2gfxclk_c;
1709 uint32_t pixclk2gfxclk_a;
1710 uint32_t pixclk2gfxclk_b;
1711 uint32_t pixclk2gfxclk_c;
1712 uint32_t dcefclk2gfxclk_a;
1713 uint32_t dcefclk2gfxclk_b;
1714 uint32_t dcefclk2gfxclk_c;
1715 uint32_t phyclk2gfxclk_a;
1716 uint32_t phyclk2gfxclk_b;
1717 uint32_t phyclk2gfxclk_c;
1718 uint32_t acg_gb_vdroop_table_a0;
1719 uint32_t acg_gb_vdroop_table_a1;
1720 uint32_t acg_gb_vdroop_table_a2;
1721 uint32_t acg_avfsgb_fuse_table_m1;
1722 uint32_t acg_avfsgb_fuse_table_m2;
1723 uint32_t acg_avfsgb_fuse_table_b;
1724 uint8_t enable_acg_gb_vdroop_table;
1725 uint8_t enable_acg_gb_fuse_table;
1726 uint32_t acg_dispclk2gfxclk_a;
1727 uint32_t acg_dispclk2gfxclk_b;
1728 uint32_t acg_dispclk2gfxclk_c;
1729 uint32_t acg_pixclk2gfxclk_a;
1730 uint32_t acg_pixclk2gfxclk_b;
1731 uint32_t acg_pixclk2gfxclk_c;
1732 uint32_t acg_dcefclk2gfxclk_a;
1733 uint32_t acg_dcefclk2gfxclk_b;
1734 uint32_t acg_dcefclk2gfxclk_c;
1735 uint32_t acg_phyclk2gfxclk_a;
1736 uint32_t acg_phyclk2gfxclk_b;
1737 uint32_t acg_phyclk2gfxclk_c;
1738};
1739
1740/*
1741 ***************************************************************************
1742 Data Table multimedia_info structure
1743 ***************************************************************************
1744*/
1745struct atom_multimedia_info_v2_1
1746{
1747 struct atom_common_table_header table_header;
1748 uint8_t uvdip_min_ver;
1749 uint8_t uvdip_max_ver;
1750 uint8_t vceip_min_ver;
1751 uint8_t vceip_max_ver;
1752 uint16_t uvd_enc_max_input_width_pixels;
1753 uint16_t uvd_enc_max_input_height_pixels;
1754 uint16_t vce_enc_max_input_width_pixels;
1755 uint16_t vce_enc_max_input_height_pixels;
1756 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1757 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1758};
1759
1760
1761/*
1762 ***************************************************************************
1763 Data Table umc_info structure
1764 ***************************************************************************
1765*/
1766struct atom_umc_info_v3_1
1767{
1768 struct atom_common_table_header table_header;
1769 uint32_t ucode_version;
1770 uint32_t ucode_rom_startaddr;
1771 uint32_t ucode_length;
1772 uint16_t umc_reg_init_offset;
1773 uint16_t customer_ucode_name_offset;
1774 uint16_t mclk_ss_percentage;
1775 uint16_t mclk_ss_rate_10hz;
1776 uint8_t umcip_min_ver;
1777 uint8_t umcip_max_ver;
1778 uint8_t vram_type; //enum of atom_dgpu_vram_type
1779 uint8_t umc_config;
1780 uint32_t mem_refclk_10khz;
1781};
1782
1783
1784/*
1785 ***************************************************************************
1786 Data Table vram_info structure
1787 ***************************************************************************
1788*/
1789struct atom_vram_module_v9
1790{
1791 // Design Specific Values
1792 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1793 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
1794 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
1795 uint16_t reserved[3];
1796 uint16_t mem_voltage; // mem_voltage
1797 uint16_t vram_module_size; // Size of atom_vram_module_v9
1798 uint8_t ext_memory_id; // Current memory module ID
1799 uint8_t memory_type; // enum of atom_dgpu_vram_type
1800 uint8_t channel_num; // Number of mem. channels supported in this module
1801 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1802 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1803 uint8_t tunningset_id; // MC phy registers set per.
1804 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
1805 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1806 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
1807 uint8_t vram_rsd2; // reserved
1808 char dram_pnstring[20]; // part number end with '0'.
1809};
1810
1811struct atom_vram_info_header_v2_3
1812{
1813 struct atom_common_table_header table_header;
1814 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1815 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1816 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1817 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
1818 uint16_t dram_data_remap_tbloffset; // reserved for now
1819 uint16_t tmrs_seq_offset; // offset of HBM tmrs
1820 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
1821 uint16_t vram_rsd2;
1822 uint8_t vram_module_num; // indicate number of VRAM module
1823 uint8_t vram_rsd1[2];
1824 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1825 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1826};
1827
1828struct atom_umc_register_addr_info{
1829 uint32_t umc_register_addr:24;
1830 uint32_t umc_reg_type_ind:1;
1831 uint32_t umc_reg_rsvd:7;
1832};
1833
1834//atom_umc_register_addr_info.
1835enum atom_umc_register_addr_info_flag{
1836 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
1837};
1838
1839union atom_umc_register_addr_info_access
1840{
1841 struct atom_umc_register_addr_info umc_reg_addr;
1842 uint32_t u32umc_reg_addr;
1843};
1844
1845struct atom_umc_reg_setting_id_config{
1846 uint32_t memclockrange:24;
1847 uint32_t mem_blk_id:8;
1848};
1849
1850union atom_umc_reg_setting_id_config_access
1851{
1852 struct atom_umc_reg_setting_id_config umc_id_access;
1853 uint32_t u32umc_id_access;
1854};
1855
1856struct atom_umc_reg_setting_data_block{
1857 union atom_umc_reg_setting_id_config_access block_id;
1858 uint32_t u32umc_reg_data[1];
1859};
1860
1861struct atom_umc_init_reg_block{
1862 uint16_t umc_reg_num;
1863 uint16_t reserved;
1864 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
1865 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1866};
1867
1868
1869/*
1870 ***************************************************************************
1871 Data Table voltageobject_info structure
1872 ***************************************************************************
1873*/
1874struct atom_i2c_data_entry
1875{
1876 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
1877 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
1878};
1879
1880struct atom_voltage_object_header_v4{
1881 uint8_t voltage_type; //enum atom_voltage_type
1882 uint8_t voltage_mode; //enum atom_voltage_object_mode
1883 uint16_t object_size; //Size of Object
1884};
1885
1886// atom_voltage_object_header_v4.voltage_mode
1887enum atom_voltage_object_mode
1888{
1889 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1890 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1891 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1892 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1893 VOLTAGE_OBJ_EVV = 8,
1894 VOLTAGE_OBJ_MERGED_POWER = 9,
1895};
1896
1897struct atom_i2c_voltage_object_v4
1898{
1899 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1900 uint8_t regulator_id; //Indicate Voltage Regulator Id
1901 uint8_t i2c_id;
1902 uint8_t i2c_slave_addr;
1903 uint8_t i2c_control_offset;
1904 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
1905 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
1906 uint8_t reserved[2];
1907 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
1908};
1909
1910// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1911enum atom_i2c_voltage_control_flag
1912{
1913 VOLTAGE_DATA_ONE_BYTE = 0,
1914 VOLTAGE_DATA_TWO_BYTE = 1,
1915};
1916
1917
1918struct atom_voltage_gpio_map_lut
1919{
1920 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
1921 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
1922};
1923
1924struct atom_gpio_voltage_object_v4
1925{
1926 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1927 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
1928 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
1929 uint8_t phase_delay_us; // phase delay in unit of micro second
1930 uint8_t reserved;
1931 uint32_t gpio_mask_val; // GPIO Mask value
1932 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1933};
1934
1935struct atom_svid2_voltage_object_v4
1936{
1937 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
1938 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1939 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
1940 uint8_t psi0_enable; //
1941 uint8_t maxvstep;
1942 uint8_t telemetry_offset;
1943 uint8_t telemetry_gain;
1944 uint16_t reserved1;
1945};
1946
1947struct atom_merged_voltage_object_v4
1948{
1949 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1950 uint8_t merged_powerrail_type; //enum atom_voltage_type
1951 uint8_t reserved[3];
1952};
1953
1954union atom_voltage_object_v4{
1955 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1956 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1957 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1958 struct atom_merged_voltage_object_v4 merged_voltage_obj;
1959};
1960
1961struct atom_voltage_objects_info_v4_1
1962{
1963 struct atom_common_table_header table_header;
1964 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
1965};
1966
1967
1968/*
1969 ***************************************************************************
1970 All Command Function structure definition
1971 ***************************************************************************
1972*/
1973
1974/*
1975 ***************************************************************************
1976 Structures used by asic_init
1977 ***************************************************************************
1978*/
1979
1980struct asic_init_engine_parameters
1981{
1982 uint32_t sclkfreqin10khz:24;
1983 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
1984};
1985
1986struct asic_init_mem_parameters
1987{
1988 uint32_t mclkfreqin10khz:24;
1989 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
1990};
1991
1992struct asic_init_parameters_v2_1
1993{
1994 struct asic_init_engine_parameters engineparam;
1995 struct asic_init_mem_parameters memparam;
1996};
1997
1998struct asic_init_ps_allocation_v2_1
1999{
2000 struct asic_init_parameters_v2_1 param;
2001 uint32_t reserved[16];
2002};
2003
2004
2005enum atom_asic_init_engine_flag
2006{
2007 b3NORMAL_ENGINE_INIT = 0,
2008 b3SRIOV_SKIP_ASIC_INIT = 0x02,
2009 b3SRIOV_LOAD_UCODE = 0x40,
2010};
2011
2012enum atom_asic_init_mem_flag
2013{
2014 b3NORMAL_MEM_INIT = 0,
2015 b3DRAM_SELF_REFRESH_EXIT =0x20,
2016};
2017
2018/*
2019 ***************************************************************************
2020 Structures used by setengineclock
2021 ***************************************************************************
2022*/
2023
2024struct set_engine_clock_parameters_v2_1
2025{
2026 uint32_t sclkfreqin10khz:24;
2027 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2028 uint32_t reserved[10];
2029};
2030
2031struct set_engine_clock_ps_allocation_v2_1
2032{
2033 struct set_engine_clock_parameters_v2_1 clockinfo;
2034 uint32_t reserved[10];
2035};
2036
2037
2038enum atom_set_engine_mem_clock_flag
2039{
2040 b3NORMAL_CHANGE_CLOCK = 0,
2041 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
2042 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
2043};
2044
2045/*
2046 ***************************************************************************
2047 Structures used by getengineclock
2048 ***************************************************************************
2049*/
2050struct get_engine_clock_parameter
2051{
2052 uint32_t sclk_10khz; // current engine speed in 10KHz unit
2053 uint32_t reserved;
2054};
2055
2056/*
2057 ***************************************************************************
2058 Structures used by setmemoryclock
2059 ***************************************************************************
2060*/
2061struct set_memory_clock_parameters_v2_1
2062{
2063 uint32_t mclkfreqin10khz:24;
2064 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
2065 uint32_t reserved[10];
2066};
2067
2068struct set_memory_clock_ps_allocation_v2_1
2069{
2070 struct set_memory_clock_parameters_v2_1 clockinfo;
2071 uint32_t reserved[10];
2072};
2073
2074
2075/*
2076 ***************************************************************************
2077 Structures used by getmemoryclock
2078 ***************************************************************************
2079*/
2080struct get_memory_clock_parameter
2081{
2082 uint32_t mclk_10khz; // current engine speed in 10KHz unit
2083 uint32_t reserved;
2084};
2085
2086
2087
2088/*
2089 ***************************************************************************
2090 Structures used by setvoltage
2091 ***************************************************************************
2092*/
2093
2094struct set_voltage_parameters_v1_4
2095{
2096 uint8_t voltagetype; /* enum atom_voltage_type */
2097 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
2098 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
2099};
2100
2101//set_voltage_parameters_v2_1.voltagemode
2102enum atom_set_voltage_command{
2103 ATOM_SET_VOLTAGE = 0,
2104 ATOM_INIT_VOLTAGE_REGULATOR = 3,
2105 ATOM_SET_VOLTAGE_PHASE = 4,
2106 ATOM_GET_LEAKAGE_ID = 8,
2107};
2108
2109struct set_voltage_ps_allocation_v1_4
2110{
2111 struct set_voltage_parameters_v1_4 setvoltageparam;
2112 uint32_t reserved[10];
2113};
2114
2115
2116/*
2117 ***************************************************************************
2118 Structures used by computegpuclockparam
2119 ***************************************************************************
2120*/
2121
2122//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
2123enum atom_gpu_clock_type
2124{
2125 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
2126 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
2127 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
2128};
2129
2130struct compute_gpu_clock_input_parameter_v1_8
2131{
2132 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2133 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
2134 uint32_t reserved[5];
2135};
2136
2137
2138struct compute_gpu_clock_output_parameter_v1_8
2139{
2140 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
2141 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
2142 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
2143 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
2144 uint16_t pll_ss_slew_frac;
2145 uint8_t pll_ss_enable;
2146 uint8_t reserved;
2147 uint32_t reserved1[2];
2148};
2149
2150
2151
2152/*
2153 ***************************************************************************
2154 Structures used by ReadEfuseValue
2155 ***************************************************************************
2156*/
2157
2158struct read_efuse_input_parameters_v3_1
2159{
2160 uint16_t efuse_start_index;
2161 uint8_t reserved;
2162 uint8_t bitslen;
2163};
2164
2165// ReadEfuseValue input/output parameter
2166union read_efuse_value_parameters_v3_1
2167{
2168 struct read_efuse_input_parameters_v3_1 efuse_info;
2169 uint32_t efusevalue;
2170};
2171
2172
2173/*
2174 ***************************************************************************
2175 Structures used by getsmuclockinfo
2176 ***************************************************************************
2177*/
2178struct atom_get_smu_clock_info_parameters_v3_1
2179{
2180 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
2181 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2182 uint8_t command; // enum of atom_get_smu_clock_info_command
2183 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
2184};
2185
2186enum atom_get_smu_clock_info_command
2187{
2188 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
2189 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
2190 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
2191};
2192
2193enum atom_smu9_syspll0_clock_id
2194{
2195 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
2196 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
2197 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2198 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
2199 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
2200 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
2201 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
2202 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
2203 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
2204 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
2205 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
2206};
2207
2208enum atom_smu11_syspll_id {
2209 SMU11_SYSPLL0_ID = 0,
2210 SMU11_SYSPLL1_0_ID = 1,
2211 SMU11_SYSPLL1_1_ID = 2,
2212 SMU11_SYSPLL1_2_ID = 3,
2213 SMU11_SYSPLL2_ID = 4,
2214 SMU11_SYSPLL3_0_ID = 5,
2215 SMU11_SYSPLL3_1_ID = 6,
2216};
2217
2218enum atom_smu11_syspll0_clock_id {
2219 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK
2220 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK
2221 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
2222 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK
2223 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK
2224 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2225};
2226
2227enum atom_smu11_syspll1_0_clock_id {
2228 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2229};
2230
2231enum atom_smu11_syspll1_1_clock_id {
2232 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2233};
2234
2235enum atom_smu11_syspll1_2_clock_id {
2236 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2237};
2238
2239enum atom_smu11_syspll2_clock_id {
2240 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2241};
2242
2243enum atom_smu11_syspll3_0_clock_id {
2244 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2245 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2246 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2247};
2248
2249enum atom_smu11_syspll3_1_clock_id {
2250 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2251 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2252 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2253};
2254
2255struct atom_get_smu_clock_info_output_parameters_v3_1
2256{
2257 union {
2258 uint32_t smu_clock_freq_hz;
2259 uint32_t syspllvcofreq_10khz;
2260 uint32_t sysspllrefclk_10khz;
2261 }atom_smu_outputclkfreq;
2262};
2263
2264
2265
2266/*
2267 ***************************************************************************
2268 Structures used by dynamicmemorysettings
2269 ***************************************************************************
2270*/
2271
2272enum atom_dynamic_memory_setting_command
2273{
2274 COMPUTE_MEMORY_PLL_PARAM = 1,
2275 COMPUTE_ENGINE_PLL_PARAM = 2,
2276 ADJUST_MC_SETTING_PARAM = 3,
2277};
2278
2279/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
2280struct dynamic_mclk_settings_parameters_v2_1
2281{
2282 uint32_t mclk_10khz:24; //Input= target mclk
2283 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2284 uint32_t reserved;
2285};
2286
2287/* when command = COMPUTE_ENGINE_PLL_PARAM */
2288struct dynamic_sclk_settings_parameters_v2_1
2289{
2290 uint32_t sclk_10khz:24; //Input= target mclk
2291 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2292 uint32_t mclk_10khz;
2293 uint32_t reserved;
2294};
2295
2296union dynamic_memory_settings_parameters_v2_1
2297{
2298 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2299 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2300};
2301
2302
2303
2304/*
2305 ***************************************************************************
2306 Structures used by memorytraining
2307 ***************************************************************************
2308*/
2309
2310enum atom_umc6_0_ucode_function_call_enum_id
2311{
2312 UMC60_UCODE_FUNC_ID_REINIT = 0,
2313 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2314 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2315};
2316
2317
2318struct memory_training_parameters_v2_1
2319{
2320 uint8_t ucode_func_id;
2321 uint8_t ucode_reserved[3];
2322 uint32_t reserved[5];
2323};
2324
2325
2326/*
2327 ***************************************************************************
2328 Structures used by setpixelclock
2329 ***************************************************************************
2330*/
2331
2332struct set_pixel_clock_parameter_v1_7
2333{
2334 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2335
2336 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2337 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2338 // indicate which graphic encoder will be used.
2339 uint8_t encoder_mode; // Encoder mode:
2340 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2341 uint8_t crtc_id; // enum of atom_crtc_def
2342 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2343 uint8_t reserved1[2];
2344 uint32_t reserved2;
2345};
2346
2347//ucMiscInfo
2348enum atom_set_pixel_clock_v1_7_misc_info
2349{
2350 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2351 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2352 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2353 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2354 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2355 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2356 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2357 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2358 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2359 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2360 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2361};
2362
2363/* deep_color_ratio */
2364enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2365{
2366 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2367 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2368 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2369 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2370};
2371
2372/*
2373 ***************************************************************************
2374 Structures used by setdceclock
2375 ***************************************************************************
2376*/
2377
2378// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
2379struct set_dce_clock_parameters_v2_1
2380{
2381 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2382 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2383 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2384 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2385 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2386};
2387
2388//ucDCEClkType
2389enum atom_set_dce_clock_clock_type
2390{
2391 DCE_CLOCK_TYPE_DISPCLK = 0,
2392 DCE_CLOCK_TYPE_DPREFCLK = 1,
2393 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2394};
2395
2396//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2397enum atom_set_dce_clock_dprefclk_flag
2398{
2399 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2400 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2401 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2402 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2403 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2404};
2405
2406//ucDCEClkFlag when ucDCEClkType == PIXCLK
2407enum atom_set_dce_clock_pixclk_flag
2408{
2409 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2410 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2411 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2412 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2413 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2414 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2415};
2416
2417struct set_dce_clock_ps_allocation_v2_1
2418{
2419 struct set_dce_clock_parameters_v2_1 param;
2420 uint32_t ulReserved[2];
2421};
2422
2423
2424/****************************************************************************/
2425// Structures used by BlankCRTC
2426/****************************************************************************/
2427struct blank_crtc_parameters
2428{
2429 uint8_t crtc_id; // enum atom_crtc_def
2430 uint8_t blanking; // enum atom_blank_crtc_command
2431 uint16_t reserved;
2432 uint32_t reserved1;
2433};
2434
2435enum atom_blank_crtc_command
2436{
2437 ATOM_BLANKING = 1,
2438 ATOM_BLANKING_OFF = 0,
2439};
2440
2441/****************************************************************************/
2442// Structures used by enablecrtc
2443/****************************************************************************/
2444struct enable_crtc_parameters
2445{
2446 uint8_t crtc_id; // enum atom_crtc_def
2447 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2448 uint8_t padding[2];
2449};
2450
2451
2452/****************************************************************************/
2453// Structure used by EnableDispPowerGating
2454/****************************************************************************/
2455struct enable_disp_power_gating_parameters_v2_1
2456{
2457 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2458 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2459 uint8_t padding[2];
2460};
2461
2462struct enable_disp_power_gating_ps_allocation
2463{
2464 struct enable_disp_power_gating_parameters_v2_1 param;
2465 uint32_t ulReserved[4];
2466};
2467
2468/****************************************************************************/
2469// Structure used in setcrtc_usingdtdtiming
2470/****************************************************************************/
2471struct set_crtc_using_dtd_timing_parameters
2472{
2473 uint16_t h_size;
2474 uint16_t h_blanking_time;
2475 uint16_t v_size;
2476 uint16_t v_blanking_time;
2477 uint16_t h_syncoffset;
2478 uint16_t h_syncwidth;
2479 uint16_t v_syncoffset;
2480 uint16_t v_syncwidth;
2481 uint16_t modemiscinfo;
2482 uint8_t h_border;
2483 uint8_t v_border;
2484 uint8_t crtc_id; // enum atom_crtc_def
2485 uint8_t encoder_mode; // atom_encode_mode_def
2486 uint8_t padding[2];
2487};
2488
2489
2490/****************************************************************************/
2491// Structures used by processi2cchanneltransaction
2492/****************************************************************************/
2493struct process_i2c_channel_transaction_parameters
2494{
2495 uint8_t i2cspeed_khz;
2496 union {
2497 uint8_t regindex;
2498 uint8_t status; /* enum atom_process_i2c_flag */
2499 } regind_status;
2500 uint16_t i2c_data_out;
2501 uint8_t flag; /* enum atom_process_i2c_status */
2502 uint8_t trans_bytes;
2503 uint8_t slave_addr;
2504 uint8_t i2c_id;
2505};
2506
2507//ucFlag
2508enum atom_process_i2c_flag
2509{
2510 HW_I2C_WRITE = 1,
2511 HW_I2C_READ = 0,
2512 I2C_2BYTE_ADDR = 0x02,
2513 HW_I2C_SMBUS_BYTE_WR = 0x04,
2514};
2515
2516//status
2517enum atom_process_i2c_status
2518{
2519 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2520 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2521};
2522
2523
2524/****************************************************************************/
2525// Structures used by processauxchanneltransaction
2526/****************************************************************************/
2527
2528struct process_aux_channel_transaction_parameters_v1_2
2529{
2530 uint16_t aux_request;
2531 uint16_t dataout;
2532 uint8_t channelid;
2533 union {
2534 uint8_t reply_status;
2535 uint8_t aux_delay;
2536 } aux_status_delay;
2537 uint8_t dataout_len;
2538 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2539};
2540
2541
2542/****************************************************************************/
2543// Structures used by selectcrtc_source
2544/****************************************************************************/
2545
2546struct select_crtc_source_parameters_v2_3
2547{
2548 uint8_t crtc_id; // enum atom_crtc_def
2549 uint8_t encoder_id; // enum atom_dig_def
2550 uint8_t encode_mode; // enum atom_encode_mode_def
2551 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2552};
2553
2554
2555/****************************************************************************/
2556// Structures used by digxencodercontrol
2557/****************************************************************************/
2558
2559// ucAction:
2560enum atom_dig_encoder_control_action
2561{
2562 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2563 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2564 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2565 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2566 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2567 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2568 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2569 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2570 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2571 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2572 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2573 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2574 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2575 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2576};
2577
2578//define ucPanelMode
2579enum atom_dig_encoder_control_panelmode
2580{
2581 DP_PANEL_MODE_DISABLE = 0x00,
2582 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2583 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2584};
2585
2586//ucDigId
2587enum atom_dig_encoder_control_v5_digid
2588{
2589 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2590 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2591 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2592 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2593 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2594 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2595 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2596 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2597};
2598
2599struct dig_encoder_stream_setup_parameters_v1_5
2600{
2601 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2602 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2603 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2604 uint8_t lanenum; // Lane number
2605 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2606 uint8_t bitpercolor;
2607 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2608 uint8_t reserved[2];
2609};
2610
2611struct dig_encoder_link_setup_parameters_v1_5
2612{
2613 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2614 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2615 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2616 uint8_t lanenum; // Lane number
2617 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2618 uint8_t hpd_sel;
2619 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2620 uint8_t reserved[2];
2621};
2622
2623struct dp_panel_mode_set_parameters_v1_5
2624{
2625 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2626 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2627 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2628 uint8_t reserved1;
2629 uint32_t reserved2[2];
2630};
2631
2632struct dig_encoder_generic_cmd_parameters_v1_5
2633{
2634 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2635 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2636 uint8_t reserved1[2];
2637 uint32_t reserved2[2];
2638};
2639
2640union dig_encoder_control_parameters_v1_5
2641{
2642 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2643 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2644 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2645 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2646};
2647
2648/*
2649 ***************************************************************************
2650 Structures used by dig1transmittercontrol
2651 ***************************************************************************
2652*/
2653struct dig_transmitter_control_parameters_v1_6
2654{
2655 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2656 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
2657 union {
2658 uint8_t digmode; // enum atom_encode_mode_def
2659 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2660 } mode_laneset;
2661 uint8_t lanenum; // Lane number 1, 2, 4, 8
2662 uint32_t symclk_10khz; // Symbol Clock in 10Khz
2663 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2664 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2665 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
2666 uint8_t reserved;
2667 uint32_t reserved1;
2668};
2669
2670struct dig_transmitter_control_ps_allocation_v1_6
2671{
2672 struct dig_transmitter_control_parameters_v1_6 param;
2673 uint32_t reserved[4];
2674};
2675
2676//ucAction
2677enum atom_dig_transmitter_control_action
2678{
2679 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
2680 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
2681 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
2682 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
2683 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
2684 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
2685 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
2686 ATOM_TRANSMITTER_ACTION_INIT = 7,
2687 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
2688 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
2689 ATOM_TRANSMITTER_ACTION_SETUP = 10,
2690 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
2691 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
2692 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
2693};
2694
2695// digfe_sel
2696enum atom_dig_transmitter_control_digfe_sel
2697{
2698 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
2699 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
2700 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
2701 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
2702 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
2703 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
2704 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
2705};
2706
2707
2708//ucHPDSel
2709enum atom_dig_transmitter_control_hpd_sel
2710{
2711 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
2712 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
2713 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
2714 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
2715 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
2716 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
2717 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
2718};
2719
2720// ucDPLaneSet
2721enum atom_dig_transmitter_control_dplaneset
2722{
2723 DP_LANE_SET__0DB_0_4V = 0x00,
2724 DP_LANE_SET__0DB_0_6V = 0x01,
2725 DP_LANE_SET__0DB_0_8V = 0x02,
2726 DP_LANE_SET__0DB_1_2V = 0x03,
2727 DP_LANE_SET__3_5DB_0_4V = 0x08,
2728 DP_LANE_SET__3_5DB_0_6V = 0x09,
2729 DP_LANE_SET__3_5DB_0_8V = 0x0a,
2730 DP_LANE_SET__6DB_0_4V = 0x10,
2731 DP_LANE_SET__6DB_0_6V = 0x11,
2732 DP_LANE_SET__9_5DB_0_4V = 0x18,
2733};
2734
2735
2736
2737/****************************************************************************/
2738// Structures used by ExternalEncoderControl V2.4
2739/****************************************************************************/
2740
2741struct external_encoder_control_parameters_v2_4
2742{
2743 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2744 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2745 uint8_t action; //
2746 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2747 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2748 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2749 uint8_t hpd_id;
2750};
2751
2752
2753// ucAction
2754enum external_encoder_control_action_def
2755{
2756 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
2757 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
2758 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
2759 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
2760 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
2761 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
2762 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
2763 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
2764};
2765
2766// ucConfig
2767enum external_encoder_control_v2_4_config_def
2768{
2769 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
2770 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
2771 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
2772 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
2773 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
2774 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
2775 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
2776 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
2777 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
2778};
2779
2780struct external_encoder_control_ps_allocation_v2_4
2781{
2782 struct external_encoder_control_parameters_v2_4 sExtEncoder;
2783 uint32_t reserved[2];
2784};
2785
2786
2787/*
2788 ***************************************************************************
2789 AMD ACPI Table
2790
2791 ***************************************************************************
2792*/
2793
2794struct amd_acpi_description_header{
2795 uint32_t signature;
2796 uint32_t tableLength; //Length
2797 uint8_t revision;
2798 uint8_t checksum;
2799 uint8_t oemId[6];
2800 uint8_t oemTableId[8]; //UINT64 OemTableId;
2801 uint32_t oemRevision;
2802 uint32_t creatorId;
2803 uint32_t creatorRevision;
2804};
2805
2806struct uefi_acpi_vfct{
2807 struct amd_acpi_description_header sheader;
2808 uint8_t tableUUID[16]; //0x24
2809 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2810 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2811 uint32_t reserved[4]; //0x3C
2812};
2813
2814struct vfct_image_header{
2815 uint32_t pcibus; //0x4C
2816 uint32_t pcidevice; //0x50
2817 uint32_t pcifunction; //0x54
2818 uint16_t vendorid; //0x58
2819 uint16_t deviceid; //0x5A
2820 uint16_t ssvid; //0x5C
2821 uint16_t ssid; //0x5E
2822 uint32_t revision; //0x60
2823 uint32_t imagelength; //0x64
2824};
2825
2826
2827struct gop_vbios_content {
2828 struct vfct_image_header vbiosheader;
2829 uint8_t vbioscontent[1];
2830};
2831
2832struct gop_lib1_content {
2833 struct vfct_image_header lib1header;
2834 uint8_t lib1content[1];
2835};
2836
2837
2838
2839/*
2840 ***************************************************************************
2841 Scratch Register definitions
2842 Each number below indicates which scratch regiser request, Active and
2843 Connect all share the same definitions as display_device_tag defines
2844 ***************************************************************************
2845*/
2846
2847enum scratch_register_def{
2848 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
2849 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
2850 ATOM_ACTIVE_INFO_DEF = 3,
2851 ATOM_LCD_INFO_DEF = 4,
2852 ATOM_DEVICE_REQ_INFO_DEF = 5,
2853 ATOM_ACC_CHANGE_INFO_DEF = 6,
2854 ATOM_PRE_OS_MODE_INFO_DEF = 7,
2855 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2856 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
2857};
2858
2859enum scratch_device_connect_info_bit_def{
2860 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
2861 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
2862 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
2863 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
2864 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
2865 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
2866 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
2867 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
2868 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
2869};
2870
2871enum scratch_bl_bri_level_info_bit_def{
2872 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
2873#ifndef _H2INC
2874 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
2875 ATOM_DEVICE_DPMS_STATE =0x00010000,
2876#endif
2877};
2878
2879enum scratch_active_info_bits_def{
2880 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
2881 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
2882 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
2883 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
2884 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
2885 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
2886 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
2887 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
2888};
2889
2890enum scratch_device_req_info_bits_def{
2891 ATOM_DISPLAY_LCD1_REQ =0x0002,
2892 ATOM_DISPLAY_DFP1_REQ =0x0008,
2893 ATOM_DISPLAY_DFP2_REQ =0x0080,
2894 ATOM_DISPLAY_DFP3_REQ =0x0200,
2895 ATOM_DISPLAY_DFP4_REQ =0x0400,
2896 ATOM_DISPLAY_DFP5_REQ =0x0800,
2897 ATOM_DISPLAY_DFP6_REQ =0x0040,
2898 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
2899};
2900
2901enum scratch_acc_change_info_bitshift_def{
2902 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
2903 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
2904};
2905
2906enum scratch_acc_change_info_bits_def{
2907 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
2908 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
2909};
2910
2911enum scratch_pre_os_mode_info_bits_def{
2912 ATOM_PRE_OS_MODE_MASK =0x00000003,
2913 ATOM_PRE_OS_MODE_VGA =0x00000000,
2914 ATOM_PRE_OS_MODE_VESA =0x00000001,
2915 ATOM_PRE_OS_MODE_GOP =0x00000002,
2916 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
2917 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2918 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
2919 ATOM_ASIC_INIT_COMPLETE =0x00000200,
2920#ifndef _H2INC
2921 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
2922#endif
2923};
2924
2925
2926
2927/*
2928 ***************************************************************************
2929 ATOM firmware ID header file
2930 !! Please keep it at end of the atomfirmware.h !!
2931 ***************************************************************************
2932*/
2933#include "atomfirmwareid.h"
2934#pragma pack()
2935
2936#endif
2937
2938