1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_COMMON_H
25#define _CGS_COMMON_H
26
27#include "amd_shared.h"
28
29struct cgs_device;
30
31/**
32 * enum cgs_ind_reg - Indirect register spaces
33 */
34enum cgs_ind_reg {
35 CGS_IND_REG__MMIO,
36 CGS_IND_REG__PCIE,
37 CGS_IND_REG__SMC,
38 CGS_IND_REG__UVD_CTX,
39 CGS_IND_REG__DIDT,
40 CGS_IND_REG_GC_CAC,
41 CGS_IND_REG_SE_CAC,
42 CGS_IND_REG__AUDIO_ENDPT
43};
44
45/*
46 * enum cgs_ucode_id - Firmware types for different IPs
47 */
48enum cgs_ucode_id {
49 CGS_UCODE_ID_SMU = 0,
50 CGS_UCODE_ID_SMU_SK,
51 CGS_UCODE_ID_SDMA0,
52 CGS_UCODE_ID_SDMA1,
53 CGS_UCODE_ID_CP_CE,
54 CGS_UCODE_ID_CP_PFP,
55 CGS_UCODE_ID_CP_ME,
56 CGS_UCODE_ID_CP_MEC,
57 CGS_UCODE_ID_CP_MEC_JT1,
58 CGS_UCODE_ID_CP_MEC_JT2,
59 CGS_UCODE_ID_GMCON_RENG,
60 CGS_UCODE_ID_RLC_G,
61 CGS_UCODE_ID_STORAGE,
62 CGS_UCODE_ID_MAXIMUM,
63};
64
65/**
66 * struct cgs_firmware_info - Firmware information
67 */
68struct cgs_firmware_info {
69 uint16_t version;
70 uint16_t fw_version;
71 uint16_t feature_version;
72 uint32_t image_size;
73 uint64_t mc_addr;
74
75 /* only for smc firmware */
76 uint32_t ucode_start_address;
77
78 void *kptr;
79 bool is_kicker;
80};
81
82typedef unsigned long cgs_handle_t;
83
84/**
85 * cgs_read_register() - Read an MMIO register
86 * @cgs_device: opaque device handle
87 * @offset: register offset
88 *
89 * Return: register value
90 */
91typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
92
93/**
94 * cgs_write_register() - Write an MMIO register
95 * @cgs_device: opaque device handle
96 * @offset: register offset
97 * @value: register value
98 */
99typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
100 uint32_t value);
101
102/**
103 * cgs_read_ind_register() - Read an indirect register
104 * @cgs_device: opaque device handle
105 * @offset: register offset
106 *
107 * Return: register value
108 */
109typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
110 unsigned index);
111
112/**
113 * cgs_write_ind_register() - Write an indirect register
114 * @cgs_device: opaque device handle
115 * @offset: register offset
116 * @value: register value
117 */
118typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
119 unsigned index, uint32_t value);
120
121#define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
122#define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK
123
124#define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \
125 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \
126 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
127
128#define CGS_REG_GET_FIELD(value, reg, field) \
129 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field))
130
131#define CGS_WREG32_FIELD(device, reg, field, val) \
132 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
133
134#define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \
135 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field))
136
137typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
138 enum cgs_ucode_id type,
139 struct cgs_firmware_info *info);
140
141struct cgs_ops {
142 /* MMIO access */
143 cgs_read_register_t read_register;
144 cgs_write_register_t write_register;
145 cgs_read_ind_register_t read_ind_register;
146 cgs_write_ind_register_t write_ind_register;
147 /* Firmware Info */
148 cgs_get_firmware_info get_firmware_info;
149};
150
151struct cgs_os_ops; /* To be define in OS-specific CGS header */
152
153struct cgs_device
154{
155 const struct cgs_ops *ops;
156 /* to be embedded at the start of driver private structure */
157};
158
159/* Convenience macros that make CGS indirect function calls look like
160 * normal function calls */
161#define CGS_CALL(func,dev,...) \
162 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
163#define CGS_OS_CALL(func,dev,...) \
164 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
165
166#define cgs_read_register(dev,offset) \
167 CGS_CALL(read_register,dev,offset)
168#define cgs_write_register(dev,offset,value) \
169 CGS_CALL(write_register,dev,offset,value)
170#define cgs_read_ind_register(dev,space,index) \
171 CGS_CALL(read_ind_register,dev,space,index)
172#define cgs_write_ind_register(dev,space,index,value) \
173 CGS_CALL(write_ind_register,dev,space,index,value)
174
175#define cgs_get_firmware_info(dev, type, info) \
176 CGS_CALL(get_firmware_info, dev, type, info)
177
178#endif /* _CGS_COMMON_H */
179