1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/*
24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
26 */
27
28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32#include <linux/bitmap.h>
33#include <linux/dma-fence.h>
34
35struct pci_dev;
36
37#define KGD_MAX_QUEUES 128
38
39struct kfd_dev;
40struct kgd_dev;
41
42struct kgd_mem;
43
44enum kfd_preempt_type {
45 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
46 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
47};
48
49struct kfd_vm_fault_info {
50 uint64_t page_addr;
51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
54 bool prot_valid;
55 bool prot_read;
56 bool prot_write;
57 bool prot_exec;
58};
59
60struct kfd_cu_info {
61 uint32_t num_shader_engines;
62 uint32_t num_shader_arrays_per_engine;
63 uint32_t num_cu_per_sh;
64 uint32_t cu_active_number;
65 uint32_t cu_ao_mask;
66 uint32_t simd_per_cu;
67 uint32_t max_waves_per_simd;
68 uint32_t wave_front_size;
69 uint32_t max_scratch_slots_per_cu;
70 uint32_t lds_size;
71 uint32_t cu_bitmap[4][4];
72};
73
74/* For getting GPU local memory information from KGD */
75struct kfd_local_mem_info {
76 uint64_t local_mem_size_private;
77 uint64_t local_mem_size_public;
78 uint32_t vram_width;
79 uint32_t mem_clk_max;
80};
81
82enum kgd_memory_pool {
83 KGD_POOL_SYSTEM_CACHEABLE = 1,
84 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
85 KGD_POOL_FRAMEBUFFER = 3,
86};
87
88enum kgd_engine_type {
89 KGD_ENGINE_PFP = 1,
90 KGD_ENGINE_ME,
91 KGD_ENGINE_CE,
92 KGD_ENGINE_MEC1,
93 KGD_ENGINE_MEC2,
94 KGD_ENGINE_RLC,
95 KGD_ENGINE_SDMA1,
96 KGD_ENGINE_SDMA2,
97 KGD_ENGINE_MAX
98};
99
100/**
101 * enum kfd_sched_policy
102 *
103 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
104 * scheduling. In this scheduling mode we're using the firmware code to
105 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
106 * the HIQ queue is used as a special queue that dispatches the configuration
107 * to the cp and the user mode queues list that are currently running.
108 * the DIQ queue is a debugging queue that dispatches debugging commands to the
109 * firmware.
110 * in this scheduling mode user mode queues over subscription feature is
111 * enabled.
112 *
113 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
114 * subscription feature disabled.
115 *
116 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
117 * set the command processor registers and sets the queues "manually". This
118 * mode is used *ONLY* for debugging proposes.
119 *
120 */
121enum kfd_sched_policy {
122 KFD_SCHED_POLICY_HWS = 0,
123 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
124 KFD_SCHED_POLICY_NO_HWS
125};
126
127struct kgd2kfd_shared_resources {
128 /* Bit n == 1 means VMID n is available for KFD. */
129 unsigned int compute_vmid_bitmap;
130
131 /* number of pipes per mec */
132 uint32_t num_pipe_per_mec;
133
134 /* number of queues per pipe */
135 uint32_t num_queue_per_pipe;
136
137 /* Bit n == 1 means Queue n is available for KFD */
138 DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES);
139
140 /* SDMA doorbell assignments (SOC15 and later chips only). Only
141 * specific doorbells are routed to each SDMA engine. Others
142 * are routed to IH and VCN. They are not usable by the CP.
143 */
144 uint32_t *sdma_doorbell_idx;
145
146 /* From SOC15 onward, the doorbell index range not usable for CP
147 * queues.
148 */
149 uint32_t non_cp_doorbells_start;
150 uint32_t non_cp_doorbells_end;
151
152 /* Base address of doorbell aperture. */
153 phys_addr_t doorbell_physical_address;
154
155 /* Size in bytes of doorbell aperture. */
156 size_t doorbell_aperture_size;
157
158 /* Number of bytes at start of aperture reserved for KGD. */
159 size_t doorbell_start_offset;
160
161 /* GPUVM address space size in bytes */
162 uint64_t gpuvm_size;
163
164 /* Minor device number of the render node */
165 int drm_render_minor;
166};
167
168struct tile_config {
169 uint32_t *tile_config_ptr;
170 uint32_t *macro_tile_config_ptr;
171 uint32_t num_tile_configs;
172 uint32_t num_macro_tile_configs;
173
174 uint32_t gb_addr_config;
175 uint32_t num_banks;
176 uint32_t num_ranks;
177};
178
179#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
180
181/*
182 * Allocation flag domains
183 * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
184 */
185#define ALLOC_MEM_FLAGS_VRAM (1 << 0)
186#define ALLOC_MEM_FLAGS_GTT (1 << 1)
187#define ALLOC_MEM_FLAGS_USERPTR (1 << 2)
188#define ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
189
190/*
191 * Allocation flags attributes/access options.
192 * NOTE: This must match the corresponding definitions in kfd_ioctl.h.
193 */
194#define ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
195#define ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
196#define ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
197#define ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) /* TODO */
198#define ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
199#define ALLOC_MEM_FLAGS_COHERENT (1 << 26) /* For GFXv9 or later */
200
201/**
202 * struct kfd2kgd_calls
203 *
204 * @program_sh_mem_settings: A function that should initiate the memory
205 * properties such as main aperture memory type (cache / non cached) and
206 * secondary aperture base address, size and memory type.
207 * This function is used only for no cp scheduling mode.
208 *
209 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
210 * scheduling mode. Only used for no cp scheduling mode.
211 *
212 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
213 * sceduling mode.
214 *
215 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
216 * used only for no HWS mode.
217 *
218 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
219 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
220 *
221 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
222 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
223 *
224 * @hqd_is_occupies: Checks if a hqd slot is occupied.
225 *
226 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
227 *
228 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
229 *
230 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
231 * SDMA hqd slot.
232 *
233 * @get_fw_version: Returns FW versions from the header
234 *
235 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
236 * Only used for no cp scheduling mode
237 *
238 * @get_tile_config: Returns GPU-specific tiling mode information
239 *
240 * @set_vm_context_page_table_base: Program page table base for a VMID
241 *
242 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
243 *
244 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
245 *
246 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
247 * IH ring entry. This function allows the KFD ISR to get the VMID
248 * from the fault status register as early as possible.
249 *
250 * @get_hive_id: Returns hive id of current device, 0 if xgmi is not enabled
251 *
252 * This structure contains function pointers to services that the kgd driver
253 * provides to amdkfd driver.
254 *
255 */
256struct kfd2kgd_calls {
257 /* Register access functions */
258 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
259 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
260 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
261
262 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
263 unsigned int vmid);
264
265 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
266
267 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
268 uint32_t queue_id, uint32_t __user *wptr,
269 uint32_t wptr_shift, uint32_t wptr_mask,
270 struct mm_struct *mm);
271
272 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
273 uint32_t __user *wptr, struct mm_struct *mm);
274
275 int (*hqd_dump)(struct kgd_dev *kgd,
276 uint32_t pipe_id, uint32_t queue_id,
277 uint32_t (**dump)[2], uint32_t *n_regs);
278
279 int (*hqd_sdma_dump)(struct kgd_dev *kgd,
280 uint32_t engine_id, uint32_t queue_id,
281 uint32_t (**dump)[2], uint32_t *n_regs);
282
283 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
284 uint32_t pipe_id, uint32_t queue_id);
285
286 int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
287 unsigned int timeout, uint32_t pipe_id,
288 uint32_t queue_id);
289
290 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
291
292 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
293 unsigned int timeout);
294
295 int (*address_watch_disable)(struct kgd_dev *kgd);
296 int (*address_watch_execute)(struct kgd_dev *kgd,
297 unsigned int watch_point_id,
298 uint32_t cntl_val,
299 uint32_t addr_hi,
300 uint32_t addr_lo);
301 int (*wave_control_execute)(struct kgd_dev *kgd,
302 uint32_t gfx_index_val,
303 uint32_t sq_cmd);
304 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
305 unsigned int watch_point_id,
306 unsigned int reg_offset);
307 bool (*get_atc_vmid_pasid_mapping_valid)(
308 struct kgd_dev *kgd,
309 uint8_t vmid);
310 uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
311 struct kgd_dev *kgd,
312 uint8_t vmid);
313
314 uint16_t (*get_fw_version)(struct kgd_dev *kgd,
315 enum kgd_engine_type type);
316 void (*set_scratch_backing_va)(struct kgd_dev *kgd,
317 uint64_t va, uint32_t vmid);
318 int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
319
320 void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
321 uint32_t vmid, uint64_t page_table_base);
322 int (*invalidate_tlbs)(struct kgd_dev *kgd, uint16_t pasid);
323 int (*invalidate_tlbs_vmid)(struct kgd_dev *kgd, uint16_t vmid);
324 uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
325 uint64_t (*get_hive_id)(struct kgd_dev *kgd);
326
327};
328
329#endif /* KGD_KFD_INTERFACE_H_INCLUDED */
330