1 | /* |
2 | * Copyright 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef __KGD_PP_INTERFACE_H__ |
25 | #define __KGD_PP_INTERFACE_H__ |
26 | |
27 | extern const struct amdgpu_ip_block_version pp_smu_ip_block; |
28 | extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; |
29 | extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; |
30 | extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; |
31 | extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; |
32 | |
33 | enum smu_event_type { |
34 | SMU_EVENT_RESET_COMPLETE = 0, |
35 | }; |
36 | |
37 | struct amd_vce_state { |
38 | /* vce clocks */ |
39 | u32 evclk; |
40 | u32 ecclk; |
41 | /* gpu clocks */ |
42 | u32 sclk; |
43 | u32 mclk; |
44 | u8 clk_idx; |
45 | u8 pstate; |
46 | }; |
47 | |
48 | |
49 | enum amd_dpm_forced_level { |
50 | AMD_DPM_FORCED_LEVEL_AUTO = 0x1, |
51 | AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, |
52 | AMD_DPM_FORCED_LEVEL_LOW = 0x4, |
53 | AMD_DPM_FORCED_LEVEL_HIGH = 0x8, |
54 | AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, |
55 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, |
56 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, |
57 | AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, |
58 | AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, |
59 | AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, |
60 | }; |
61 | |
62 | enum amd_pm_state_type { |
63 | /* not used for dpm */ |
64 | POWER_STATE_TYPE_DEFAULT, |
65 | POWER_STATE_TYPE_POWERSAVE, |
66 | /* user selectable states */ |
67 | POWER_STATE_TYPE_BATTERY, |
68 | POWER_STATE_TYPE_BALANCED, |
69 | POWER_STATE_TYPE_PERFORMANCE, |
70 | /* internal states */ |
71 | POWER_STATE_TYPE_INTERNAL_UVD, |
72 | POWER_STATE_TYPE_INTERNAL_UVD_SD, |
73 | POWER_STATE_TYPE_INTERNAL_UVD_HD, |
74 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, |
75 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, |
76 | POWER_STATE_TYPE_INTERNAL_BOOT, |
77 | POWER_STATE_TYPE_INTERNAL_THERMAL, |
78 | POWER_STATE_TYPE_INTERNAL_ACPI, |
79 | POWER_STATE_TYPE_INTERNAL_ULV, |
80 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
81 | }; |
82 | |
83 | #define AMD_MAX_VCE_LEVELS 6 |
84 | |
85 | enum amd_vce_level { |
86 | AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ |
87 | AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ |
88 | AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ |
89 | AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ |
90 | AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ |
91 | AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ |
92 | }; |
93 | |
94 | enum amd_fan_ctrl_mode { |
95 | AMD_FAN_CTRL_NONE = 0, |
96 | AMD_FAN_CTRL_MANUAL = 1, |
97 | AMD_FAN_CTRL_AUTO = 2, |
98 | }; |
99 | |
100 | enum pp_clock_type { |
101 | PP_SCLK, |
102 | PP_MCLK, |
103 | PP_PCIE, |
104 | PP_SOCCLK, |
105 | PP_FCLK, |
106 | PP_DCEFCLK, |
107 | PP_VCLK, |
108 | PP_VCLK1, |
109 | PP_DCLK, |
110 | PP_DCLK1, |
111 | OD_SCLK, |
112 | OD_MCLK, |
113 | OD_VDDC_CURVE, |
114 | OD_RANGE, |
115 | OD_VDDGFX_OFFSET, |
116 | OD_CCLK, |
117 | OD_FAN_CURVE, |
118 | OD_ACOUSTIC_LIMIT, |
119 | OD_ACOUSTIC_TARGET, |
120 | OD_FAN_TARGET_TEMPERATURE, |
121 | OD_FAN_MINIMUM_PWM, |
122 | }; |
123 | |
124 | enum amd_pp_sensors { |
125 | AMDGPU_PP_SENSOR_GFX_SCLK = 0, |
126 | AMDGPU_PP_SENSOR_CPU_CLK, |
127 | AMDGPU_PP_SENSOR_VDDNB, |
128 | AMDGPU_PP_SENSOR_VDDGFX, |
129 | AMDGPU_PP_SENSOR_UVD_VCLK, |
130 | AMDGPU_PP_SENSOR_UVD_DCLK, |
131 | AMDGPU_PP_SENSOR_VCE_ECCLK, |
132 | AMDGPU_PP_SENSOR_GPU_LOAD, |
133 | AMDGPU_PP_SENSOR_MEM_LOAD, |
134 | AMDGPU_PP_SENSOR_GFX_MCLK, |
135 | AMDGPU_PP_SENSOR_GPU_TEMP, |
136 | AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, |
137 | AMDGPU_PP_SENSOR_HOTSPOT_TEMP, |
138 | AMDGPU_PP_SENSOR_MEM_TEMP, |
139 | AMDGPU_PP_SENSOR_VCE_POWER, |
140 | AMDGPU_PP_SENSOR_UVD_POWER, |
141 | AMDGPU_PP_SENSOR_GPU_AVG_POWER, |
142 | AMDGPU_PP_SENSOR_GPU_INPUT_POWER, |
143 | AMDGPU_PP_SENSOR_SS_APU_SHARE, |
144 | AMDGPU_PP_SENSOR_SS_DGPU_SHARE, |
145 | AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, |
146 | AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, |
147 | AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, |
148 | AMDGPU_PP_SENSOR_MIN_FAN_RPM, |
149 | AMDGPU_PP_SENSOR_MAX_FAN_RPM, |
150 | AMDGPU_PP_SENSOR_VCN_POWER_STATE, |
151 | AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, |
152 | AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, |
153 | }; |
154 | |
155 | enum amd_pp_task { |
156 | AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, |
157 | AMD_PP_TASK_ENABLE_USER_STATE, |
158 | AMD_PP_TASK_READJUST_POWER_STATE, |
159 | AMD_PP_TASK_COMPLETE_INIT, |
160 | AMD_PP_TASK_MAX |
161 | }; |
162 | |
163 | enum PP_SMC_POWER_PROFILE { |
164 | PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, |
165 | PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, |
166 | PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, |
167 | PP_SMC_POWER_PROFILE_VIDEO = 0x3, |
168 | PP_SMC_POWER_PROFILE_VR = 0x4, |
169 | PP_SMC_POWER_PROFILE_COMPUTE = 0x5, |
170 | PP_SMC_POWER_PROFILE_CUSTOM = 0x6, |
171 | PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, |
172 | PP_SMC_POWER_PROFILE_CAPPED = 0x8, |
173 | PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, |
174 | PP_SMC_POWER_PROFILE_COUNT, |
175 | }; |
176 | |
177 | extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; |
178 | |
179 | |
180 | |
181 | enum { |
182 | PP_GROUP_UNKNOWN = 0, |
183 | PP_GROUP_GFX = 1, |
184 | PP_GROUP_SYS, |
185 | PP_GROUP_MAX |
186 | }; |
187 | |
188 | enum PP_OD_DPM_TABLE_COMMAND { |
189 | PP_OD_EDIT_SCLK_VDDC_TABLE, |
190 | PP_OD_EDIT_MCLK_VDDC_TABLE, |
191 | PP_OD_EDIT_CCLK_VDDC_TABLE, |
192 | PP_OD_EDIT_VDDC_CURVE, |
193 | PP_OD_RESTORE_DEFAULT_TABLE, |
194 | PP_OD_COMMIT_DPM_TABLE, |
195 | PP_OD_EDIT_VDDGFX_OFFSET, |
196 | PP_OD_EDIT_FAN_CURVE, |
197 | PP_OD_EDIT_ACOUSTIC_LIMIT, |
198 | PP_OD_EDIT_ACOUSTIC_TARGET, |
199 | PP_OD_EDIT_FAN_TARGET_TEMPERATURE, |
200 | PP_OD_EDIT_FAN_MINIMUM_PWM, |
201 | }; |
202 | |
203 | struct pp_states_info { |
204 | uint32_t nums; |
205 | uint32_t states[16]; |
206 | }; |
207 | |
208 | enum PP_HWMON_TEMP { |
209 | PP_TEMP_EDGE = 0, |
210 | PP_TEMP_JUNCTION, |
211 | PP_TEMP_MEM, |
212 | PP_TEMP_MAX |
213 | }; |
214 | |
215 | enum pp_mp1_state { |
216 | PP_MP1_STATE_NONE, |
217 | PP_MP1_STATE_SHUTDOWN, |
218 | PP_MP1_STATE_UNLOAD, |
219 | PP_MP1_STATE_RESET, |
220 | }; |
221 | |
222 | enum pp_df_cstate { |
223 | DF_CSTATE_DISALLOW = 0, |
224 | DF_CSTATE_ALLOW, |
225 | }; |
226 | |
227 | /** |
228 | * DOC: amdgpu_pp_power |
229 | * |
230 | * APU power is managed to system-level requirements through the PPT |
231 | * (package power tracking) feature. PPT is intended to limit power to the |
232 | * requirements of the power source and could be dynamically updated to |
233 | * maximize APU performance within the system power budget. |
234 | * |
235 | * Two types of power measurement can be requested, where supported, with |
236 | * :c:type:`enum pp_power_type <pp_power_type>`. |
237 | */ |
238 | |
239 | /** |
240 | * enum pp_power_limit_level - Used to query the power limits |
241 | * |
242 | * @PP_PWR_LIMIT_MIN: Minimum Power Limit |
243 | * @PP_PWR_LIMIT_CURRENT: Current Power Limit |
244 | * @PP_PWR_LIMIT_DEFAULT: Default Power Limit |
245 | * @PP_PWR_LIMIT_MAX: Maximum Power Limit |
246 | */ |
247 | enum pp_power_limit_level |
248 | { |
249 | PP_PWR_LIMIT_MIN = -1, |
250 | PP_PWR_LIMIT_CURRENT, |
251 | PP_PWR_LIMIT_DEFAULT, |
252 | PP_PWR_LIMIT_MAX, |
253 | }; |
254 | |
255 | /** |
256 | * enum pp_power_type - Used to specify the type of the requested power |
257 | * |
258 | * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant |
259 | * moving average of APU power (default ~5000 ms). |
260 | * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, |
261 | * where supported. |
262 | */ |
263 | enum pp_power_type |
264 | { |
265 | PP_PWR_TYPE_SUSTAINED, |
266 | PP_PWR_TYPE_FAST, |
267 | }; |
268 | |
269 | enum pp_xgmi_plpd_mode { |
270 | XGMI_PLPD_NONE = -1, |
271 | XGMI_PLPD_DISALLOW, |
272 | XGMI_PLPD_DEFAULT, |
273 | XGMI_PLPD_OPTIMIZED, |
274 | XGMI_PLPD_COUNT, |
275 | }; |
276 | |
277 | #define PP_GROUP_MASK 0xF0000000 |
278 | #define PP_GROUP_SHIFT 28 |
279 | |
280 | #define PP_BLOCK_MASK 0x0FFFFF00 |
281 | #define PP_BLOCK_SHIFT 8 |
282 | |
283 | #define PP_BLOCK_GFX_CG 0x01 |
284 | #define PP_BLOCK_GFX_MG 0x02 |
285 | #define PP_BLOCK_GFX_3D 0x04 |
286 | #define PP_BLOCK_GFX_RLC 0x08 |
287 | #define PP_BLOCK_GFX_CP 0x10 |
288 | #define PP_BLOCK_SYS_BIF 0x01 |
289 | #define PP_BLOCK_SYS_MC 0x02 |
290 | #define PP_BLOCK_SYS_ROM 0x04 |
291 | #define PP_BLOCK_SYS_DRM 0x08 |
292 | #define PP_BLOCK_SYS_HDP 0x10 |
293 | #define PP_BLOCK_SYS_SDMA 0x20 |
294 | |
295 | #define PP_STATE_MASK 0x0000000F |
296 | #define PP_STATE_SHIFT 0 |
297 | #define PP_STATE_SUPPORT_MASK 0x000000F0 |
298 | #define PP_STATE_SUPPORT_SHIFT 0 |
299 | |
300 | #define PP_STATE_CG 0x01 |
301 | #define PP_STATE_LS 0x02 |
302 | #define PP_STATE_DS 0x04 |
303 | #define PP_STATE_SD 0x08 |
304 | #define PP_STATE_SUPPORT_CG 0x10 |
305 | #define PP_STATE_SUPPORT_LS 0x20 |
306 | #define PP_STATE_SUPPORT_DS 0x40 |
307 | #define PP_STATE_SUPPORT_SD 0x80 |
308 | |
309 | #define PP_CG_MSG_ID(group, block, support, state) \ |
310 | ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ |
311 | (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) |
312 | |
313 | #define XGMI_MODE_PSTATE_D3 0 |
314 | #define XGMI_MODE_PSTATE_D0 1 |
315 | |
316 | #define NUM_HBM_INSTANCES 4 |
317 | #define NUM_XGMI_LINKS 8 |
318 | #define MAX_GFX_CLKS 8 |
319 | #define MAX_CLKS 4 |
320 | #define NUM_VCN 4 |
321 | |
322 | struct seq_file; |
323 | enum amd_pp_clock_type; |
324 | struct amd_pp_simple_clock_info; |
325 | struct amd_pp_display_configuration; |
326 | struct amd_pp_clock_info; |
327 | struct pp_display_clock_request; |
328 | struct pp_clock_levels_with_voltage; |
329 | struct pp_clock_levels_with_latency; |
330 | struct amd_pp_clocks; |
331 | struct pp_smu_wm_range_sets; |
332 | struct pp_smu_nv_clock_table; |
333 | struct dpm_clocks; |
334 | |
335 | struct amd_pm_funcs { |
336 | /* export for dpm on ci and si */ |
337 | int (*pre_set_power_state)(void *handle); |
338 | int (*set_power_state)(void *handle); |
339 | void (*post_set_power_state)(void *handle); |
340 | void (*display_configuration_changed)(void *handle); |
341 | void (*print_power_state)(void *handle, void *ps); |
342 | bool (*vblank_too_short)(void *handle); |
343 | void (*enable_bapm)(void *handle, bool enable); |
344 | int (*check_state_equal)(void *handle, |
345 | void *cps, |
346 | void *rps, |
347 | bool *equal); |
348 | /* export for sysfs */ |
349 | int (*set_fan_control_mode)(void *handle, u32 mode); |
350 | int (*get_fan_control_mode)(void *handle, u32 *fan_mode); |
351 | int (*set_fan_speed_pwm)(void *handle, u32 speed); |
352 | int (*get_fan_speed_pwm)(void *handle, u32 *speed); |
353 | int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); |
354 | int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); |
355 | int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); |
356 | int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); |
357 | int (*get_sclk_od)(void *handle); |
358 | int (*set_sclk_od)(void *handle, uint32_t value); |
359 | int (*get_mclk_od)(void *handle); |
360 | int (*set_mclk_od)(void *handle, uint32_t value); |
361 | int (*read_sensor)(void *handle, int idx, void *value, int *size); |
362 | int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); |
363 | int (*set_apu_thermal_limit)(void *handle, uint32_t limit); |
364 | enum amd_dpm_forced_level (*get_performance_level)(void *handle); |
365 | enum amd_pm_state_type (*get_current_power_state)(void *handle); |
366 | int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); |
367 | int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); |
368 | int (*get_pp_num_states)(void *handle, struct pp_states_info *data); |
369 | int (*get_pp_table)(void *handle, char **table); |
370 | int (*set_pp_table)(void *handle, const char *buf, size_t size); |
371 | void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); |
372 | int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); |
373 | /* export to amdgpu */ |
374 | struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); |
375 | int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, |
376 | enum amd_pm_state_type *user_state); |
377 | int (*load_firmware)(void *handle); |
378 | int (*wait_for_fw_loading_complete)(void *handle); |
379 | int (*set_powergating_by_smu)(void *handle, |
380 | uint32_t block_type, bool gate); |
381 | int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); |
382 | int (*set_power_limit)(void *handle, uint32_t n); |
383 | int (*get_power_limit)(void *handle, uint32_t *limit, |
384 | enum pp_power_limit_level pp_limit_level, |
385 | enum pp_power_type power_type); |
386 | int (*get_power_profile_mode)(void *handle, char *buf); |
387 | int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); |
388 | int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); |
389 | int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, |
390 | long *input, uint32_t size); |
391 | int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); |
392 | int (*smu_i2c_bus_access)(void *handle, bool acquire); |
393 | int (*gfx_state_change_set)(void *handle, uint32_t state); |
394 | /* export to DC */ |
395 | u32 (*get_sclk)(void *handle, bool low); |
396 | u32 (*get_mclk)(void *handle, bool low); |
397 | int (*display_configuration_change)(void *handle, |
398 | const struct amd_pp_display_configuration *input); |
399 | int (*get_display_power_level)(void *handle, |
400 | struct amd_pp_simple_clock_info *output); |
401 | int (*get_current_clocks)(void *handle, |
402 | struct amd_pp_clock_info *clocks); |
403 | int (*get_clock_by_type)(void *handle, |
404 | enum amd_pp_clock_type type, |
405 | struct amd_pp_clocks *clocks); |
406 | int (*get_clock_by_type_with_latency)(void *handle, |
407 | enum amd_pp_clock_type type, |
408 | struct pp_clock_levels_with_latency *clocks); |
409 | int (*get_clock_by_type_with_voltage)(void *handle, |
410 | enum amd_pp_clock_type type, |
411 | struct pp_clock_levels_with_voltage *clocks); |
412 | int (*set_watermarks_for_clocks_ranges)(void *handle, |
413 | void *clock_ranges); |
414 | int (*display_clock_voltage_request)(void *handle, |
415 | struct pp_display_clock_request *clock); |
416 | int (*get_display_mode_validation_clocks)(void *handle, |
417 | struct amd_pp_simple_clock_info *clocks); |
418 | int (*notify_smu_enable_pwe)(void *handle); |
419 | int (*enable_mgpu_fan_boost)(void *handle); |
420 | int (*set_active_display_count)(void *handle, uint32_t count); |
421 | int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); |
422 | int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); |
423 | int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); |
424 | int (*get_asic_baco_capability)(void *handle, bool *cap); |
425 | int (*get_asic_baco_state)(void *handle, int *state); |
426 | int (*set_asic_baco_state)(void *handle, int state); |
427 | int (*get_ppfeature_status)(void *handle, char *buf); |
428 | int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); |
429 | int (*asic_reset_mode_2)(void *handle); |
430 | int (*asic_reset_enable_gfx_features)(void *handle); |
431 | int (*set_df_cstate)(void *handle, enum pp_df_cstate state); |
432 | int (*set_xgmi_pstate)(void *handle, uint32_t pstate); |
433 | ssize_t (*get_gpu_metrics)(void *handle, void **table); |
434 | int (*set_watermarks_for_clock_ranges)(void *handle, |
435 | struct pp_smu_wm_range_sets *ranges); |
436 | int (*display_disable_memory_clock_switch)(void *handle, |
437 | bool disable_memory_clock_switch); |
438 | int (*get_max_sustainable_clocks_by_dc)(void *handle, |
439 | struct pp_smu_nv_clock_table *max_clocks); |
440 | int (*get_uclk_dpm_states)(void *handle, |
441 | unsigned int *clock_values_in_khz, |
442 | unsigned int *num_states); |
443 | int (*get_dpm_clock_table)(void *handle, |
444 | struct dpm_clocks *clock_table); |
445 | int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); |
446 | void (*pm_compute_clocks)(void *handle); |
447 | }; |
448 | |
449 | struct { |
450 | uint16_t ; |
451 | uint8_t ; |
452 | uint8_t ; |
453 | }; |
454 | |
455 | /* |
456 | * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. |
457 | * Use gpu_metrics_v1_1 or later instead. |
458 | */ |
459 | struct gpu_metrics_v1_0 { |
460 | struct metrics_table_header ; |
461 | |
462 | /* Driver attached timestamp (in ns) */ |
463 | uint64_t system_clock_counter; |
464 | |
465 | /* Temperature */ |
466 | uint16_t temperature_edge; |
467 | uint16_t temperature_hotspot; |
468 | uint16_t temperature_mem; |
469 | uint16_t temperature_vrgfx; |
470 | uint16_t temperature_vrsoc; |
471 | uint16_t temperature_vrmem; |
472 | |
473 | /* Utilization */ |
474 | uint16_t average_gfx_activity; |
475 | uint16_t average_umc_activity; // memory controller |
476 | uint16_t average_mm_activity; // UVD or VCN |
477 | |
478 | /* Power/Energy */ |
479 | uint16_t average_socket_power; |
480 | uint32_t energy_accumulator; |
481 | |
482 | /* Average clocks */ |
483 | uint16_t average_gfxclk_frequency; |
484 | uint16_t average_socclk_frequency; |
485 | uint16_t average_uclk_frequency; |
486 | uint16_t average_vclk0_frequency; |
487 | uint16_t average_dclk0_frequency; |
488 | uint16_t average_vclk1_frequency; |
489 | uint16_t average_dclk1_frequency; |
490 | |
491 | /* Current clocks */ |
492 | uint16_t current_gfxclk; |
493 | uint16_t current_socclk; |
494 | uint16_t current_uclk; |
495 | uint16_t current_vclk0; |
496 | uint16_t current_dclk0; |
497 | uint16_t current_vclk1; |
498 | uint16_t current_dclk1; |
499 | |
500 | /* Throttle status */ |
501 | uint32_t throttle_status; |
502 | |
503 | /* Fans */ |
504 | uint16_t current_fan_speed; |
505 | |
506 | /* Link width/speed */ |
507 | uint8_t pcie_link_width; |
508 | uint8_t pcie_link_speed; // in 0.1 GT/s |
509 | }; |
510 | |
511 | struct gpu_metrics_v1_1 { |
512 | struct metrics_table_header ; |
513 | |
514 | /* Temperature */ |
515 | uint16_t temperature_edge; |
516 | uint16_t temperature_hotspot; |
517 | uint16_t temperature_mem; |
518 | uint16_t temperature_vrgfx; |
519 | uint16_t temperature_vrsoc; |
520 | uint16_t temperature_vrmem; |
521 | |
522 | /* Utilization */ |
523 | uint16_t average_gfx_activity; |
524 | uint16_t average_umc_activity; // memory controller |
525 | uint16_t average_mm_activity; // UVD or VCN |
526 | |
527 | /* Power/Energy */ |
528 | uint16_t average_socket_power; |
529 | uint64_t energy_accumulator; |
530 | |
531 | /* Driver attached timestamp (in ns) */ |
532 | uint64_t system_clock_counter; |
533 | |
534 | /* Average clocks */ |
535 | uint16_t average_gfxclk_frequency; |
536 | uint16_t average_socclk_frequency; |
537 | uint16_t average_uclk_frequency; |
538 | uint16_t average_vclk0_frequency; |
539 | uint16_t average_dclk0_frequency; |
540 | uint16_t average_vclk1_frequency; |
541 | uint16_t average_dclk1_frequency; |
542 | |
543 | /* Current clocks */ |
544 | uint16_t current_gfxclk; |
545 | uint16_t current_socclk; |
546 | uint16_t current_uclk; |
547 | uint16_t current_vclk0; |
548 | uint16_t current_dclk0; |
549 | uint16_t current_vclk1; |
550 | uint16_t current_dclk1; |
551 | |
552 | /* Throttle status */ |
553 | uint32_t throttle_status; |
554 | |
555 | /* Fans */ |
556 | uint16_t current_fan_speed; |
557 | |
558 | /* Link width/speed */ |
559 | uint16_t pcie_link_width; |
560 | uint16_t pcie_link_speed; // in 0.1 GT/s |
561 | |
562 | uint16_t padding; |
563 | |
564 | uint32_t gfx_activity_acc; |
565 | uint32_t mem_activity_acc; |
566 | |
567 | uint16_t temperature_hbm[NUM_HBM_INSTANCES]; |
568 | }; |
569 | |
570 | struct gpu_metrics_v1_2 { |
571 | struct metrics_table_header ; |
572 | |
573 | /* Temperature */ |
574 | uint16_t temperature_edge; |
575 | uint16_t temperature_hotspot; |
576 | uint16_t temperature_mem; |
577 | uint16_t temperature_vrgfx; |
578 | uint16_t temperature_vrsoc; |
579 | uint16_t temperature_vrmem; |
580 | |
581 | /* Utilization */ |
582 | uint16_t average_gfx_activity; |
583 | uint16_t average_umc_activity; // memory controller |
584 | uint16_t average_mm_activity; // UVD or VCN |
585 | |
586 | /* Power/Energy */ |
587 | uint16_t average_socket_power; |
588 | uint64_t energy_accumulator; |
589 | |
590 | /* Driver attached timestamp (in ns) */ |
591 | uint64_t system_clock_counter; |
592 | |
593 | /* Average clocks */ |
594 | uint16_t average_gfxclk_frequency; |
595 | uint16_t average_socclk_frequency; |
596 | uint16_t average_uclk_frequency; |
597 | uint16_t average_vclk0_frequency; |
598 | uint16_t average_dclk0_frequency; |
599 | uint16_t average_vclk1_frequency; |
600 | uint16_t average_dclk1_frequency; |
601 | |
602 | /* Current clocks */ |
603 | uint16_t current_gfxclk; |
604 | uint16_t current_socclk; |
605 | uint16_t current_uclk; |
606 | uint16_t current_vclk0; |
607 | uint16_t current_dclk0; |
608 | uint16_t current_vclk1; |
609 | uint16_t current_dclk1; |
610 | |
611 | /* Throttle status (ASIC dependent) */ |
612 | uint32_t throttle_status; |
613 | |
614 | /* Fans */ |
615 | uint16_t current_fan_speed; |
616 | |
617 | /* Link width/speed */ |
618 | uint16_t pcie_link_width; |
619 | uint16_t pcie_link_speed; // in 0.1 GT/s |
620 | |
621 | uint16_t padding; |
622 | |
623 | uint32_t gfx_activity_acc; |
624 | uint32_t mem_activity_acc; |
625 | |
626 | uint16_t temperature_hbm[NUM_HBM_INSTANCES]; |
627 | |
628 | /* PMFW attached timestamp (10ns resolution) */ |
629 | uint64_t firmware_timestamp; |
630 | }; |
631 | |
632 | struct gpu_metrics_v1_3 { |
633 | struct metrics_table_header ; |
634 | |
635 | /* Temperature */ |
636 | uint16_t temperature_edge; |
637 | uint16_t temperature_hotspot; |
638 | uint16_t temperature_mem; |
639 | uint16_t temperature_vrgfx; |
640 | uint16_t temperature_vrsoc; |
641 | uint16_t temperature_vrmem; |
642 | |
643 | /* Utilization */ |
644 | uint16_t average_gfx_activity; |
645 | uint16_t average_umc_activity; // memory controller |
646 | uint16_t average_mm_activity; // UVD or VCN |
647 | |
648 | /* Power/Energy */ |
649 | uint16_t average_socket_power; |
650 | uint64_t energy_accumulator; |
651 | |
652 | /* Driver attached timestamp (in ns) */ |
653 | uint64_t system_clock_counter; |
654 | |
655 | /* Average clocks */ |
656 | uint16_t average_gfxclk_frequency; |
657 | uint16_t average_socclk_frequency; |
658 | uint16_t average_uclk_frequency; |
659 | uint16_t average_vclk0_frequency; |
660 | uint16_t average_dclk0_frequency; |
661 | uint16_t average_vclk1_frequency; |
662 | uint16_t average_dclk1_frequency; |
663 | |
664 | /* Current clocks */ |
665 | uint16_t current_gfxclk; |
666 | uint16_t current_socclk; |
667 | uint16_t current_uclk; |
668 | uint16_t current_vclk0; |
669 | uint16_t current_dclk0; |
670 | uint16_t current_vclk1; |
671 | uint16_t current_dclk1; |
672 | |
673 | /* Throttle status */ |
674 | uint32_t throttle_status; |
675 | |
676 | /* Fans */ |
677 | uint16_t current_fan_speed; |
678 | |
679 | /* Link width/speed */ |
680 | uint16_t pcie_link_width; |
681 | uint16_t pcie_link_speed; // in 0.1 GT/s |
682 | |
683 | uint16_t padding; |
684 | |
685 | uint32_t gfx_activity_acc; |
686 | uint32_t mem_activity_acc; |
687 | |
688 | uint16_t temperature_hbm[NUM_HBM_INSTANCES]; |
689 | |
690 | /* PMFW attached timestamp (10ns resolution) */ |
691 | uint64_t firmware_timestamp; |
692 | |
693 | /* Voltage (mV) */ |
694 | uint16_t voltage_soc; |
695 | uint16_t voltage_gfx; |
696 | uint16_t voltage_mem; |
697 | |
698 | uint16_t padding1; |
699 | |
700 | /* Throttle status (ASIC independent) */ |
701 | uint64_t indep_throttle_status; |
702 | }; |
703 | |
704 | struct gpu_metrics_v1_4 { |
705 | struct metrics_table_header ; |
706 | |
707 | /* Temperature (Celsius) */ |
708 | uint16_t temperature_hotspot; |
709 | uint16_t temperature_mem; |
710 | uint16_t temperature_vrsoc; |
711 | |
712 | /* Power (Watts) */ |
713 | uint16_t curr_socket_power; |
714 | |
715 | /* Utilization (%) */ |
716 | uint16_t average_gfx_activity; |
717 | uint16_t average_umc_activity; // memory controller |
718 | uint16_t vcn_activity[NUM_VCN]; |
719 | |
720 | /* Energy (15.259uJ (2^-16) units) */ |
721 | uint64_t energy_accumulator; |
722 | |
723 | /* Driver attached timestamp (in ns) */ |
724 | uint64_t system_clock_counter; |
725 | |
726 | /* Throttle status */ |
727 | uint32_t throttle_status; |
728 | |
729 | /* Clock Lock Status. Each bit corresponds to clock instance */ |
730 | uint32_t gfxclk_lock_status; |
731 | |
732 | /* Link width (number of lanes) and speed (in 0.1 GT/s) */ |
733 | uint16_t pcie_link_width; |
734 | uint16_t pcie_link_speed; |
735 | |
736 | /* XGMI bus width and bitrate (in Gbps) */ |
737 | uint16_t xgmi_link_width; |
738 | uint16_t xgmi_link_speed; |
739 | |
740 | /* Utilization Accumulated (%) */ |
741 | uint32_t gfx_activity_acc; |
742 | uint32_t mem_activity_acc; |
743 | |
744 | /*PCIE accumulated bandwidth (GB/sec) */ |
745 | uint64_t pcie_bandwidth_acc; |
746 | |
747 | /*PCIE instantaneous bandwidth (GB/sec) */ |
748 | uint64_t pcie_bandwidth_inst; |
749 | |
750 | /* PCIE L0 to recovery state transition accumulated count */ |
751 | uint64_t pcie_l0_to_recov_count_acc; |
752 | |
753 | /* PCIE replay accumulated count */ |
754 | uint64_t pcie_replay_count_acc; |
755 | |
756 | /* PCIE replay rollover accumulated count */ |
757 | uint64_t pcie_replay_rover_count_acc; |
758 | |
759 | /* XGMI accumulated data transfer size(KiloBytes) */ |
760 | uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; |
761 | uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; |
762 | |
763 | /* PMFW attached timestamp (10ns resolution) */ |
764 | uint64_t firmware_timestamp; |
765 | |
766 | /* Current clocks (Mhz) */ |
767 | uint16_t current_gfxclk[MAX_GFX_CLKS]; |
768 | uint16_t current_socclk[MAX_CLKS]; |
769 | uint16_t current_vclk0[MAX_CLKS]; |
770 | uint16_t current_dclk0[MAX_CLKS]; |
771 | uint16_t current_uclk; |
772 | |
773 | uint16_t padding; |
774 | }; |
775 | |
776 | /* |
777 | * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. |
778 | * Use gpu_metrics_v2_1 or later instead. |
779 | */ |
780 | struct gpu_metrics_v2_0 { |
781 | struct metrics_table_header ; |
782 | |
783 | /* Driver attached timestamp (in ns) */ |
784 | uint64_t system_clock_counter; |
785 | |
786 | /* Temperature */ |
787 | uint16_t temperature_gfx; // gfx temperature on APUs |
788 | uint16_t temperature_soc; // soc temperature on APUs |
789 | uint16_t temperature_core[8]; // CPU core temperature on APUs |
790 | uint16_t temperature_l3[2]; |
791 | |
792 | /* Utilization */ |
793 | uint16_t average_gfx_activity; |
794 | uint16_t average_mm_activity; // UVD or VCN |
795 | |
796 | /* Power/Energy */ |
797 | uint16_t average_socket_power; // dGPU + APU power on A + A platform |
798 | uint16_t average_cpu_power; |
799 | uint16_t average_soc_power; |
800 | uint16_t average_gfx_power; |
801 | uint16_t average_core_power[8]; // CPU core power on APUs |
802 | |
803 | /* Average clocks */ |
804 | uint16_t average_gfxclk_frequency; |
805 | uint16_t average_socclk_frequency; |
806 | uint16_t average_uclk_frequency; |
807 | uint16_t average_fclk_frequency; |
808 | uint16_t average_vclk_frequency; |
809 | uint16_t average_dclk_frequency; |
810 | |
811 | /* Current clocks */ |
812 | uint16_t current_gfxclk; |
813 | uint16_t current_socclk; |
814 | uint16_t current_uclk; |
815 | uint16_t current_fclk; |
816 | uint16_t current_vclk; |
817 | uint16_t current_dclk; |
818 | uint16_t current_coreclk[8]; // CPU core clocks |
819 | uint16_t current_l3clk[2]; |
820 | |
821 | /* Throttle status */ |
822 | uint32_t throttle_status; |
823 | |
824 | /* Fans */ |
825 | uint16_t fan_pwm; |
826 | |
827 | uint16_t padding; |
828 | }; |
829 | |
830 | struct gpu_metrics_v2_1 { |
831 | struct metrics_table_header ; |
832 | |
833 | /* Temperature */ |
834 | uint16_t temperature_gfx; // gfx temperature on APUs |
835 | uint16_t temperature_soc; // soc temperature on APUs |
836 | uint16_t temperature_core[8]; // CPU core temperature on APUs |
837 | uint16_t temperature_l3[2]; |
838 | |
839 | /* Utilization */ |
840 | uint16_t average_gfx_activity; |
841 | uint16_t average_mm_activity; // UVD or VCN |
842 | |
843 | /* Driver attached timestamp (in ns) */ |
844 | uint64_t system_clock_counter; |
845 | |
846 | /* Power/Energy */ |
847 | uint16_t average_socket_power; // dGPU + APU power on A + A platform |
848 | uint16_t average_cpu_power; |
849 | uint16_t average_soc_power; |
850 | uint16_t average_gfx_power; |
851 | uint16_t average_core_power[8]; // CPU core power on APUs |
852 | |
853 | /* Average clocks */ |
854 | uint16_t average_gfxclk_frequency; |
855 | uint16_t average_socclk_frequency; |
856 | uint16_t average_uclk_frequency; |
857 | uint16_t average_fclk_frequency; |
858 | uint16_t average_vclk_frequency; |
859 | uint16_t average_dclk_frequency; |
860 | |
861 | /* Current clocks */ |
862 | uint16_t current_gfxclk; |
863 | uint16_t current_socclk; |
864 | uint16_t current_uclk; |
865 | uint16_t current_fclk; |
866 | uint16_t current_vclk; |
867 | uint16_t current_dclk; |
868 | uint16_t current_coreclk[8]; // CPU core clocks |
869 | uint16_t current_l3clk[2]; |
870 | |
871 | /* Throttle status */ |
872 | uint32_t throttle_status; |
873 | |
874 | /* Fans */ |
875 | uint16_t fan_pwm; |
876 | |
877 | uint16_t padding[3]; |
878 | }; |
879 | |
880 | struct gpu_metrics_v2_2 { |
881 | struct metrics_table_header ; |
882 | |
883 | /* Temperature */ |
884 | uint16_t temperature_gfx; // gfx temperature on APUs |
885 | uint16_t temperature_soc; // soc temperature on APUs |
886 | uint16_t temperature_core[8]; // CPU core temperature on APUs |
887 | uint16_t temperature_l3[2]; |
888 | |
889 | /* Utilization */ |
890 | uint16_t average_gfx_activity; |
891 | uint16_t average_mm_activity; // UVD or VCN |
892 | |
893 | /* Driver attached timestamp (in ns) */ |
894 | uint64_t system_clock_counter; |
895 | |
896 | /* Power/Energy */ |
897 | uint16_t average_socket_power; // dGPU + APU power on A + A platform |
898 | uint16_t average_cpu_power; |
899 | uint16_t average_soc_power; |
900 | uint16_t average_gfx_power; |
901 | uint16_t average_core_power[8]; // CPU core power on APUs |
902 | |
903 | /* Average clocks */ |
904 | uint16_t average_gfxclk_frequency; |
905 | uint16_t average_socclk_frequency; |
906 | uint16_t average_uclk_frequency; |
907 | uint16_t average_fclk_frequency; |
908 | uint16_t average_vclk_frequency; |
909 | uint16_t average_dclk_frequency; |
910 | |
911 | /* Current clocks */ |
912 | uint16_t current_gfxclk; |
913 | uint16_t current_socclk; |
914 | uint16_t current_uclk; |
915 | uint16_t current_fclk; |
916 | uint16_t current_vclk; |
917 | uint16_t current_dclk; |
918 | uint16_t current_coreclk[8]; // CPU core clocks |
919 | uint16_t current_l3clk[2]; |
920 | |
921 | /* Throttle status (ASIC dependent) */ |
922 | uint32_t throttle_status; |
923 | |
924 | /* Fans */ |
925 | uint16_t fan_pwm; |
926 | |
927 | uint16_t padding[3]; |
928 | |
929 | /* Throttle status (ASIC independent) */ |
930 | uint64_t indep_throttle_status; |
931 | }; |
932 | |
933 | struct gpu_metrics_v2_3 { |
934 | struct metrics_table_header ; |
935 | |
936 | /* Temperature */ |
937 | uint16_t temperature_gfx; // gfx temperature on APUs |
938 | uint16_t temperature_soc; // soc temperature on APUs |
939 | uint16_t temperature_core[8]; // CPU core temperature on APUs |
940 | uint16_t temperature_l3[2]; |
941 | |
942 | /* Utilization */ |
943 | uint16_t average_gfx_activity; |
944 | uint16_t average_mm_activity; // UVD or VCN |
945 | |
946 | /* Driver attached timestamp (in ns) */ |
947 | uint64_t system_clock_counter; |
948 | |
949 | /* Power/Energy */ |
950 | uint16_t average_socket_power; // dGPU + APU power on A + A platform |
951 | uint16_t average_cpu_power; |
952 | uint16_t average_soc_power; |
953 | uint16_t average_gfx_power; |
954 | uint16_t average_core_power[8]; // CPU core power on APUs |
955 | |
956 | /* Average clocks */ |
957 | uint16_t average_gfxclk_frequency; |
958 | uint16_t average_socclk_frequency; |
959 | uint16_t average_uclk_frequency; |
960 | uint16_t average_fclk_frequency; |
961 | uint16_t average_vclk_frequency; |
962 | uint16_t average_dclk_frequency; |
963 | |
964 | /* Current clocks */ |
965 | uint16_t current_gfxclk; |
966 | uint16_t current_socclk; |
967 | uint16_t current_uclk; |
968 | uint16_t current_fclk; |
969 | uint16_t current_vclk; |
970 | uint16_t current_dclk; |
971 | uint16_t current_coreclk[8]; // CPU core clocks |
972 | uint16_t current_l3clk[2]; |
973 | |
974 | /* Throttle status (ASIC dependent) */ |
975 | uint32_t throttle_status; |
976 | |
977 | /* Fans */ |
978 | uint16_t fan_pwm; |
979 | |
980 | uint16_t padding[3]; |
981 | |
982 | /* Throttle status (ASIC independent) */ |
983 | uint64_t indep_throttle_status; |
984 | |
985 | /* Average Temperature */ |
986 | uint16_t average_temperature_gfx; // average gfx temperature on APUs |
987 | uint16_t average_temperature_soc; // average soc temperature on APUs |
988 | uint16_t average_temperature_core[8]; // average CPU core temperature on APUs |
989 | uint16_t average_temperature_l3[2]; |
990 | }; |
991 | |
992 | struct gpu_metrics_v2_4 { |
993 | struct metrics_table_header ; |
994 | |
995 | /* Temperature (unit: centi-Celsius) */ |
996 | uint16_t temperature_gfx; |
997 | uint16_t temperature_soc; |
998 | uint16_t temperature_core[8]; |
999 | uint16_t temperature_l3[2]; |
1000 | |
1001 | /* Utilization (unit: centi) */ |
1002 | uint16_t average_gfx_activity; |
1003 | uint16_t average_mm_activity; |
1004 | |
1005 | /* Driver attached timestamp (in ns) */ |
1006 | uint64_t system_clock_counter; |
1007 | |
1008 | /* Power/Energy (unit: mW) */ |
1009 | uint16_t average_socket_power; |
1010 | uint16_t average_cpu_power; |
1011 | uint16_t average_soc_power; |
1012 | uint16_t average_gfx_power; |
1013 | uint16_t average_core_power[8]; |
1014 | |
1015 | /* Average clocks (unit: MHz) */ |
1016 | uint16_t average_gfxclk_frequency; |
1017 | uint16_t average_socclk_frequency; |
1018 | uint16_t average_uclk_frequency; |
1019 | uint16_t average_fclk_frequency; |
1020 | uint16_t average_vclk_frequency; |
1021 | uint16_t average_dclk_frequency; |
1022 | |
1023 | /* Current clocks (unit: MHz) */ |
1024 | uint16_t current_gfxclk; |
1025 | uint16_t current_socclk; |
1026 | uint16_t current_uclk; |
1027 | uint16_t current_fclk; |
1028 | uint16_t current_vclk; |
1029 | uint16_t current_dclk; |
1030 | uint16_t current_coreclk[8]; |
1031 | uint16_t current_l3clk[2]; |
1032 | |
1033 | /* Throttle status (ASIC dependent) */ |
1034 | uint32_t throttle_status; |
1035 | |
1036 | /* Fans */ |
1037 | uint16_t fan_pwm; |
1038 | |
1039 | uint16_t padding[3]; |
1040 | |
1041 | /* Throttle status (ASIC independent) */ |
1042 | uint64_t indep_throttle_status; |
1043 | |
1044 | /* Average Temperature (unit: centi-Celsius) */ |
1045 | uint16_t average_temperature_gfx; |
1046 | uint16_t average_temperature_soc; |
1047 | uint16_t average_temperature_core[8]; |
1048 | uint16_t average_temperature_l3[2]; |
1049 | |
1050 | /* Power/Voltage (unit: mV) */ |
1051 | uint16_t average_cpu_voltage; |
1052 | uint16_t average_soc_voltage; |
1053 | uint16_t average_gfx_voltage; |
1054 | |
1055 | /* Power/Current (unit: mA) */ |
1056 | uint16_t average_cpu_current; |
1057 | uint16_t average_soc_current; |
1058 | uint16_t average_gfx_current; |
1059 | }; |
1060 | |
1061 | struct gpu_metrics_v3_0 { |
1062 | struct metrics_table_header ; |
1063 | |
1064 | /* Temperature */ |
1065 | /* gfx temperature on APUs */ |
1066 | uint16_t temperature_gfx; |
1067 | /* soc temperature on APUs */ |
1068 | uint16_t temperature_soc; |
1069 | /* CPU core temperature on APUs */ |
1070 | uint16_t temperature_core[16]; |
1071 | /* skin temperature on APUs */ |
1072 | uint16_t temperature_skin; |
1073 | |
1074 | /* Utilization */ |
1075 | /* time filtered GFX busy % [0-100] */ |
1076 | uint16_t average_gfx_activity; |
1077 | /* time filtered VCN busy % [0-100] */ |
1078 | uint16_t average_vcn_activity; |
1079 | /* time filtered IPU per-column busy % [0-100] */ |
1080 | uint16_t average_ipu_activity[8]; |
1081 | /* time filtered per-core C0 residency % [0-100]*/ |
1082 | uint16_t average_core_c0_activity[16]; |
1083 | /* time filtered DRAM read bandwidth [MB/sec] */ |
1084 | uint16_t average_dram_reads; |
1085 | /* time filtered DRAM write bandwidth [MB/sec] */ |
1086 | uint16_t average_dram_writes; |
1087 | |
1088 | /* Driver attached timestamp (in ns) */ |
1089 | uint64_t system_clock_counter; |
1090 | |
1091 | /* Power/Energy */ |
1092 | /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ |
1093 | uint32_t average_socket_power; |
1094 | /* time filtered IPU power [mW] */ |
1095 | uint16_t average_ipu_power; |
1096 | /* time filtered APU power [mW] */ |
1097 | uint32_t average_apu_power; |
1098 | /* time filtered GFX power [mW] */ |
1099 | uint32_t average_gfx_power; |
1100 | /* time filtered dGPU power [mW] */ |
1101 | uint32_t average_dgpu_power; |
1102 | /* time filtered sum of core power across all cores in the socket [mW] */ |
1103 | uint32_t average_all_core_power; |
1104 | /* calculated core power [mW] */ |
1105 | uint16_t average_core_power[16]; |
1106 | /* maximum IRM defined STAPM power limit [mW] */ |
1107 | uint16_t stapm_power_limit; |
1108 | /* time filtered STAPM power limit [mW] */ |
1109 | uint16_t current_stapm_power_limit; |
1110 | |
1111 | /* time filtered clocks [MHz] */ |
1112 | uint16_t average_gfxclk_frequency; |
1113 | uint16_t average_socclk_frequency; |
1114 | uint16_t average_vpeclk_frequency; |
1115 | uint16_t average_ipuclk_frequency; |
1116 | uint16_t average_fclk_frequency; |
1117 | uint16_t average_vclk_frequency; |
1118 | |
1119 | /* Current clocks */ |
1120 | /* target core frequency [MHz] */ |
1121 | uint16_t current_coreclk[16]; |
1122 | /* CCLK frequency limit enforced on classic cores [MHz] */ |
1123 | uint16_t current_core_maxfreq; |
1124 | /* GFXCLK frequency limit enforced on GFX [MHz] */ |
1125 | uint16_t current_gfx_maxfreq; |
1126 | |
1127 | /* Metrics table alpha filter time constant [us] */ |
1128 | uint32_t time_filter_alphavalue; |
1129 | }; |
1130 | #endif |
1131 | |