1 | /* |
2 | * Copyright 2012-2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #ifndef V9_STRUCTS_H_ |
25 | #define V9_STRUCTS_H_ |
26 | |
27 | struct v9_sdma_mqd { |
28 | uint32_t sdmax_rlcx_rb_cntl; |
29 | uint32_t sdmax_rlcx_rb_base; |
30 | uint32_t sdmax_rlcx_rb_base_hi; |
31 | uint32_t sdmax_rlcx_rb_rptr; |
32 | uint32_t sdmax_rlcx_rb_rptr_hi; |
33 | uint32_t sdmax_rlcx_rb_wptr; |
34 | uint32_t sdmax_rlcx_rb_wptr_hi; |
35 | uint32_t sdmax_rlcx_rb_wptr_poll_cntl; |
36 | uint32_t sdmax_rlcx_rb_rptr_addr_hi; |
37 | uint32_t sdmax_rlcx_rb_rptr_addr_lo; |
38 | uint32_t sdmax_rlcx_ib_cntl; |
39 | uint32_t sdmax_rlcx_ib_rptr; |
40 | uint32_t sdmax_rlcx_ib_offset; |
41 | uint32_t sdmax_rlcx_ib_base_lo; |
42 | uint32_t sdmax_rlcx_ib_base_hi; |
43 | uint32_t sdmax_rlcx_ib_size; |
44 | uint32_t sdmax_rlcx_skip_cntl; |
45 | uint32_t sdmax_rlcx_context_status; |
46 | uint32_t sdmax_rlcx_doorbell; |
47 | uint32_t sdmax_rlcx_status; |
48 | uint32_t sdmax_rlcx_doorbell_log; |
49 | uint32_t sdmax_rlcx_watermark; |
50 | uint32_t sdmax_rlcx_doorbell_offset; |
51 | uint32_t sdmax_rlcx_csa_addr_lo; |
52 | uint32_t sdmax_rlcx_csa_addr_hi; |
53 | uint32_t sdmax_rlcx_ib_sub_remain; |
54 | uint32_t sdmax_rlcx_preempt; |
55 | uint32_t sdmax_rlcx_dummy_reg; |
56 | uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; |
57 | uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; |
58 | uint32_t sdmax_rlcx_rb_aql_cntl; |
59 | uint32_t sdmax_rlcx_minor_ptr_update; |
60 | uint32_t sdmax_rlcx_midcmd_data0; |
61 | uint32_t sdmax_rlcx_midcmd_data1; |
62 | uint32_t sdmax_rlcx_midcmd_data2; |
63 | uint32_t sdmax_rlcx_midcmd_data3; |
64 | uint32_t sdmax_rlcx_midcmd_data4; |
65 | uint32_t sdmax_rlcx_midcmd_data5; |
66 | uint32_t sdmax_rlcx_midcmd_data6; |
67 | uint32_t sdmax_rlcx_midcmd_data7; |
68 | uint32_t sdmax_rlcx_midcmd_data8; |
69 | uint32_t sdmax_rlcx_midcmd_cntl; |
70 | uint32_t reserved_42; |
71 | uint32_t reserved_43; |
72 | uint32_t reserved_44; |
73 | uint32_t reserved_45; |
74 | uint32_t reserved_46; |
75 | uint32_t reserved_47; |
76 | uint32_t reserved_48; |
77 | uint32_t reserved_49; |
78 | uint32_t reserved_50; |
79 | uint32_t reserved_51; |
80 | uint32_t reserved_52; |
81 | uint32_t reserved_53; |
82 | uint32_t reserved_54; |
83 | uint32_t reserved_55; |
84 | uint32_t reserved_56; |
85 | uint32_t reserved_57; |
86 | uint32_t reserved_58; |
87 | uint32_t reserved_59; |
88 | uint32_t reserved_60; |
89 | uint32_t reserved_61; |
90 | uint32_t reserved_62; |
91 | uint32_t reserved_63; |
92 | uint32_t reserved_64; |
93 | uint32_t reserved_65; |
94 | uint32_t reserved_66; |
95 | uint32_t reserved_67; |
96 | uint32_t reserved_68; |
97 | uint32_t reserved_69; |
98 | uint32_t reserved_70; |
99 | uint32_t reserved_71; |
100 | uint32_t reserved_72; |
101 | uint32_t reserved_73; |
102 | uint32_t reserved_74; |
103 | uint32_t reserved_75; |
104 | uint32_t reserved_76; |
105 | uint32_t reserved_77; |
106 | uint32_t reserved_78; |
107 | uint32_t reserved_79; |
108 | uint32_t reserved_80; |
109 | uint32_t reserved_81; |
110 | uint32_t reserved_82; |
111 | uint32_t reserved_83; |
112 | uint32_t reserved_84; |
113 | uint32_t reserved_85; |
114 | uint32_t reserved_86; |
115 | uint32_t reserved_87; |
116 | uint32_t reserved_88; |
117 | uint32_t reserved_89; |
118 | uint32_t reserved_90; |
119 | uint32_t reserved_91; |
120 | uint32_t reserved_92; |
121 | uint32_t reserved_93; |
122 | uint32_t reserved_94; |
123 | uint32_t reserved_95; |
124 | uint32_t reserved_96; |
125 | uint32_t reserved_97; |
126 | uint32_t reserved_98; |
127 | uint32_t reserved_99; |
128 | uint32_t reserved_100; |
129 | uint32_t reserved_101; |
130 | uint32_t reserved_102; |
131 | uint32_t reserved_103; |
132 | uint32_t reserved_104; |
133 | uint32_t reserved_105; |
134 | uint32_t reserved_106; |
135 | uint32_t reserved_107; |
136 | uint32_t reserved_108; |
137 | uint32_t reserved_109; |
138 | uint32_t reserved_110; |
139 | uint32_t reserved_111; |
140 | uint32_t reserved_112; |
141 | uint32_t reserved_113; |
142 | uint32_t reserved_114; |
143 | uint32_t reserved_115; |
144 | uint32_t reserved_116; |
145 | uint32_t reserved_117; |
146 | uint32_t reserved_118; |
147 | uint32_t reserved_119; |
148 | uint32_t reserved_120; |
149 | uint32_t reserved_121; |
150 | uint32_t reserved_122; |
151 | uint32_t reserved_123; |
152 | uint32_t reserved_124; |
153 | uint32_t reserved_125; |
154 | /* reserved_126,127: repurposed for driver-internal use */ |
155 | uint32_t sdma_engine_id; |
156 | uint32_t sdma_queue_id; |
157 | }; |
158 | |
159 | struct v9_mqd { |
160 | uint32_t ; |
161 | uint32_t compute_dispatch_initiator; |
162 | uint32_t compute_dim_x; |
163 | uint32_t compute_dim_y; |
164 | uint32_t compute_dim_z; |
165 | uint32_t compute_start_x; |
166 | uint32_t compute_start_y; |
167 | uint32_t compute_start_z; |
168 | uint32_t compute_num_thread_x; |
169 | uint32_t compute_num_thread_y; |
170 | uint32_t compute_num_thread_z; |
171 | uint32_t compute_pipelinestat_enable; |
172 | uint32_t compute_perfcount_enable; |
173 | uint32_t compute_pgm_lo; |
174 | uint32_t compute_pgm_hi; |
175 | uint32_t compute_tba_lo; |
176 | uint32_t compute_tba_hi; |
177 | uint32_t compute_tma_lo; |
178 | uint32_t compute_tma_hi; |
179 | uint32_t compute_pgm_rsrc1; |
180 | uint32_t compute_pgm_rsrc2; |
181 | uint32_t compute_vmid; |
182 | uint32_t compute_resource_limits; |
183 | uint32_t compute_static_thread_mgmt_se0; |
184 | uint32_t compute_static_thread_mgmt_se1; |
185 | uint32_t compute_tmpring_size; |
186 | uint32_t compute_static_thread_mgmt_se2; |
187 | uint32_t compute_static_thread_mgmt_se3; |
188 | uint32_t compute_restart_x; |
189 | uint32_t compute_restart_y; |
190 | uint32_t compute_restart_z; |
191 | uint32_t compute_thread_trace_enable; |
192 | uint32_t compute_misc_reserved; |
193 | uint32_t compute_dispatch_id; |
194 | uint32_t compute_threadgroup_id; |
195 | uint32_t compute_relaunch; |
196 | uint32_t compute_wave_restore_addr_lo; |
197 | uint32_t compute_wave_restore_addr_hi; |
198 | uint32_t compute_wave_restore_control; |
199 | union { |
200 | struct { |
201 | uint32_t compute_static_thread_mgmt_se4; |
202 | uint32_t compute_static_thread_mgmt_se5; |
203 | uint32_t compute_static_thread_mgmt_se6; |
204 | uint32_t compute_static_thread_mgmt_se7; |
205 | }; |
206 | struct { |
207 | uint32_t compute_current_logic_xcc_id; // offset: 39 (0x27) |
208 | uint32_t compute_restart_cg_tg_id; // offset: 40 (0x28) |
209 | uint32_t compute_tg_chunk_size; // offset: 41 (0x29) |
210 | uint32_t compute_restore_tg_chunk_size; // offset: 42 (0x2A) |
211 | }; |
212 | }; |
213 | uint32_t reserved_43; |
214 | uint32_t reserved_44; |
215 | uint32_t reserved_45; |
216 | uint32_t reserved_46; |
217 | uint32_t reserved_47; |
218 | uint32_t reserved_48; |
219 | uint32_t reserved_49; |
220 | uint32_t reserved_50; |
221 | uint32_t reserved_51; |
222 | uint32_t reserved_52; |
223 | uint32_t reserved_53; |
224 | uint32_t reserved_54; |
225 | uint32_t reserved_55; |
226 | uint32_t reserved_56; |
227 | uint32_t reserved_57; |
228 | uint32_t reserved_58; |
229 | uint32_t reserved_59; |
230 | uint32_t reserved_60; |
231 | uint32_t reserved_61; |
232 | uint32_t reserved_62; |
233 | uint32_t reserved_63; |
234 | uint32_t reserved_64; |
235 | uint32_t compute_user_data_0; |
236 | uint32_t compute_user_data_1; |
237 | uint32_t compute_user_data_2; |
238 | uint32_t compute_user_data_3; |
239 | uint32_t compute_user_data_4; |
240 | uint32_t compute_user_data_5; |
241 | uint32_t compute_user_data_6; |
242 | uint32_t compute_user_data_7; |
243 | uint32_t compute_user_data_8; |
244 | uint32_t compute_user_data_9; |
245 | uint32_t compute_user_data_10; |
246 | uint32_t compute_user_data_11; |
247 | uint32_t compute_user_data_12; |
248 | uint32_t compute_user_data_13; |
249 | uint32_t compute_user_data_14; |
250 | uint32_t compute_user_data_15; |
251 | uint32_t cp_compute_csinvoc_count_lo; |
252 | uint32_t cp_compute_csinvoc_count_hi; |
253 | uint32_t reserved_83; |
254 | uint32_t reserved_84; |
255 | uint32_t reserved_85; |
256 | uint32_t cp_mqd_query_time_lo; |
257 | uint32_t cp_mqd_query_time_hi; |
258 | uint32_t cp_mqd_connect_start_time_lo; |
259 | uint32_t cp_mqd_connect_start_time_hi; |
260 | uint32_t cp_mqd_connect_end_time_lo; |
261 | uint32_t cp_mqd_connect_end_time_hi; |
262 | uint32_t cp_mqd_connect_end_wf_count; |
263 | uint32_t cp_mqd_connect_end_pq_rptr; |
264 | uint32_t cp_mqd_connect_end_pq_wptr; |
265 | uint32_t cp_mqd_connect_end_ib_rptr; |
266 | uint32_t cp_mqd_readindex_lo; |
267 | uint32_t cp_mqd_readindex_hi; |
268 | uint32_t cp_mqd_save_start_time_lo; |
269 | uint32_t cp_mqd_save_start_time_hi; |
270 | uint32_t cp_mqd_save_end_time_lo; |
271 | uint32_t cp_mqd_save_end_time_hi; |
272 | uint32_t cp_mqd_restore_start_time_lo; |
273 | uint32_t cp_mqd_restore_start_time_hi; |
274 | uint32_t cp_mqd_restore_end_time_lo; |
275 | uint32_t cp_mqd_restore_end_time_hi; |
276 | uint32_t disable_queue; |
277 | uint32_t reserved_107; |
278 | uint32_t gds_cs_ctxsw_cnt0; |
279 | uint32_t gds_cs_ctxsw_cnt1; |
280 | uint32_t gds_cs_ctxsw_cnt2; |
281 | uint32_t gds_cs_ctxsw_cnt3; |
282 | uint32_t reserved_112; |
283 | uint32_t reserved_113; |
284 | uint32_t cp_pq_exe_status_lo; |
285 | uint32_t cp_pq_exe_status_hi; |
286 | uint32_t cp_packet_id_lo; |
287 | uint32_t cp_packet_id_hi; |
288 | uint32_t cp_packet_exe_status_lo; |
289 | uint32_t cp_packet_exe_status_hi; |
290 | uint32_t gds_save_base_addr_lo; |
291 | uint32_t gds_save_base_addr_hi; |
292 | uint32_t gds_save_mask_lo; |
293 | uint32_t gds_save_mask_hi; |
294 | uint32_t ctx_save_base_addr_lo; |
295 | uint32_t ctx_save_base_addr_hi; |
296 | uint32_t dynamic_cu_mask_addr_lo; |
297 | uint32_t dynamic_cu_mask_addr_hi; |
298 | uint32_t cp_mqd_base_addr_lo; |
299 | uint32_t cp_mqd_base_addr_hi; |
300 | uint32_t cp_hqd_active; |
301 | uint32_t cp_hqd_vmid; |
302 | uint32_t cp_hqd_persistent_state; |
303 | uint32_t cp_hqd_pipe_priority; |
304 | uint32_t cp_hqd_queue_priority; |
305 | uint32_t cp_hqd_quantum; |
306 | uint32_t cp_hqd_pq_base_lo; |
307 | uint32_t cp_hqd_pq_base_hi; |
308 | uint32_t cp_hqd_pq_rptr; |
309 | uint32_t cp_hqd_pq_rptr_report_addr_lo; |
310 | uint32_t cp_hqd_pq_rptr_report_addr_hi; |
311 | uint32_t cp_hqd_pq_wptr_poll_addr_lo; |
312 | uint32_t cp_hqd_pq_wptr_poll_addr_hi; |
313 | uint32_t cp_hqd_pq_doorbell_control; |
314 | uint32_t reserved_144; |
315 | uint32_t cp_hqd_pq_control; |
316 | uint32_t cp_hqd_ib_base_addr_lo; |
317 | uint32_t cp_hqd_ib_base_addr_hi; |
318 | uint32_t cp_hqd_ib_rptr; |
319 | uint32_t cp_hqd_ib_control; |
320 | uint32_t cp_hqd_iq_timer; |
321 | uint32_t cp_hqd_iq_rptr; |
322 | uint32_t cp_hqd_dequeue_request; |
323 | uint32_t cp_hqd_dma_offload; |
324 | uint32_t cp_hqd_sema_cmd; |
325 | uint32_t cp_hqd_msg_type; |
326 | uint32_t cp_hqd_atomic0_preop_lo; |
327 | uint32_t cp_hqd_atomic0_preop_hi; |
328 | uint32_t cp_hqd_atomic1_preop_lo; |
329 | uint32_t cp_hqd_atomic1_preop_hi; |
330 | uint32_t cp_hqd_hq_status0; |
331 | uint32_t cp_hqd_hq_control0; |
332 | uint32_t cp_mqd_control; |
333 | uint32_t cp_hqd_hq_status1; |
334 | uint32_t cp_hqd_hq_control1; |
335 | uint32_t cp_hqd_eop_base_addr_lo; |
336 | uint32_t cp_hqd_eop_base_addr_hi; |
337 | uint32_t cp_hqd_eop_control; |
338 | uint32_t cp_hqd_eop_rptr; |
339 | uint32_t cp_hqd_eop_wptr; |
340 | uint32_t cp_hqd_eop_done_events; |
341 | uint32_t cp_hqd_ctx_save_base_addr_lo; |
342 | uint32_t cp_hqd_ctx_save_base_addr_hi; |
343 | uint32_t cp_hqd_ctx_save_control; |
344 | uint32_t cp_hqd_cntl_stack_offset; |
345 | uint32_t cp_hqd_cntl_stack_size; |
346 | uint32_t cp_hqd_wg_state_offset; |
347 | uint32_t cp_hqd_ctx_save_size; |
348 | uint32_t cp_hqd_gds_resource_state; |
349 | uint32_t cp_hqd_error; |
350 | uint32_t cp_hqd_eop_wptr_mem; |
351 | uint32_t cp_hqd_aql_control; |
352 | uint32_t cp_hqd_pq_wptr_lo; |
353 | uint32_t cp_hqd_pq_wptr_hi; |
354 | uint32_t reserved_184; |
355 | uint32_t reserved_185; |
356 | uint32_t reserved_186; |
357 | uint32_t reserved_187; |
358 | uint32_t reserved_188; |
359 | uint32_t reserved_189; |
360 | uint32_t reserved_190; |
361 | uint32_t reserved_191; |
362 | uint32_t ; |
363 | uint32_t iqtimer_pkt_dw0; |
364 | uint32_t iqtimer_pkt_dw1; |
365 | uint32_t iqtimer_pkt_dw2; |
366 | uint32_t iqtimer_pkt_dw3; |
367 | uint32_t iqtimer_pkt_dw4; |
368 | uint32_t iqtimer_pkt_dw5; |
369 | uint32_t iqtimer_pkt_dw6; |
370 | uint32_t iqtimer_pkt_dw7; |
371 | uint32_t iqtimer_pkt_dw8; |
372 | uint32_t iqtimer_pkt_dw9; |
373 | uint32_t iqtimer_pkt_dw10; |
374 | uint32_t iqtimer_pkt_dw11; |
375 | uint32_t iqtimer_pkt_dw12; |
376 | uint32_t iqtimer_pkt_dw13; |
377 | uint32_t iqtimer_pkt_dw14; |
378 | uint32_t iqtimer_pkt_dw15; |
379 | uint32_t iqtimer_pkt_dw16; |
380 | uint32_t iqtimer_pkt_dw17; |
381 | uint32_t iqtimer_pkt_dw18; |
382 | uint32_t iqtimer_pkt_dw19; |
383 | uint32_t iqtimer_pkt_dw20; |
384 | uint32_t iqtimer_pkt_dw21; |
385 | uint32_t iqtimer_pkt_dw22; |
386 | uint32_t iqtimer_pkt_dw23; |
387 | uint32_t iqtimer_pkt_dw24; |
388 | uint32_t iqtimer_pkt_dw25; |
389 | uint32_t iqtimer_pkt_dw26; |
390 | uint32_t iqtimer_pkt_dw27; |
391 | uint32_t iqtimer_pkt_dw28; |
392 | uint32_t iqtimer_pkt_dw29; |
393 | uint32_t iqtimer_pkt_dw30; |
394 | uint32_t iqtimer_pkt_dw31; |
395 | union { |
396 | struct { |
397 | uint32_t reserved_225; |
398 | uint32_t reserved_226; |
399 | }; |
400 | struct { |
401 | uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1) |
402 | uint32_t cp_mqd_stride_size; // offset: 226 (0xE2) |
403 | }; |
404 | }; |
405 | uint32_t reserved_227; |
406 | uint32_t ; |
407 | uint32_t set_resources_dw1; |
408 | uint32_t set_resources_dw2; |
409 | uint32_t set_resources_dw3; |
410 | uint32_t set_resources_dw4; |
411 | uint32_t set_resources_dw5; |
412 | uint32_t set_resources_dw6; |
413 | uint32_t set_resources_dw7; |
414 | uint32_t reserved_236; |
415 | uint32_t reserved_237; |
416 | uint32_t reserved_238; |
417 | uint32_t reserved_239; |
418 | uint32_t queue_doorbell_id0; |
419 | uint32_t queue_doorbell_id1; |
420 | uint32_t queue_doorbell_id2; |
421 | uint32_t queue_doorbell_id3; |
422 | uint32_t queue_doorbell_id4; |
423 | uint32_t queue_doorbell_id5; |
424 | uint32_t queue_doorbell_id6; |
425 | uint32_t queue_doorbell_id7; |
426 | uint32_t queue_doorbell_id8; |
427 | uint32_t queue_doorbell_id9; |
428 | uint32_t queue_doorbell_id10; |
429 | uint32_t queue_doorbell_id11; |
430 | uint32_t queue_doorbell_id12; |
431 | uint32_t queue_doorbell_id13; |
432 | uint32_t queue_doorbell_id14; |
433 | uint32_t queue_doorbell_id15; |
434 | uint32_t reserved_256; |
435 | uint32_t reserved_257; |
436 | uint32_t reserved_258; |
437 | uint32_t reserved_259; |
438 | uint32_t reserved_260; |
439 | uint32_t reserved_261; |
440 | uint32_t reserved_262; |
441 | uint32_t reserved_263; |
442 | uint32_t reserved_264; |
443 | uint32_t reserved_265; |
444 | uint32_t reserved_266; |
445 | uint32_t reserved_267; |
446 | uint32_t reserved_268; |
447 | uint32_t reserved_269; |
448 | uint32_t reserved_270; |
449 | uint32_t reserved_271; |
450 | uint32_t reserved_272; |
451 | uint32_t reserved_273; |
452 | uint32_t reserved_274; |
453 | uint32_t reserved_275; |
454 | uint32_t reserved_276; |
455 | uint32_t reserved_277; |
456 | uint32_t reserved_278; |
457 | uint32_t reserved_279; |
458 | uint32_t reserved_280; |
459 | uint32_t reserved_281; |
460 | uint32_t reserved_282; |
461 | uint32_t reserved_283; |
462 | uint32_t reserved_284; |
463 | uint32_t reserved_285; |
464 | uint32_t reserved_286; |
465 | uint32_t reserved_287; |
466 | uint32_t reserved_288; |
467 | uint32_t reserved_289; |
468 | uint32_t reserved_290; |
469 | uint32_t reserved_291; |
470 | uint32_t reserved_292; |
471 | uint32_t reserved_293; |
472 | uint32_t reserved_294; |
473 | uint32_t reserved_295; |
474 | uint32_t reserved_296; |
475 | uint32_t reserved_297; |
476 | uint32_t reserved_298; |
477 | uint32_t reserved_299; |
478 | uint32_t reserved_300; |
479 | uint32_t reserved_301; |
480 | uint32_t reserved_302; |
481 | uint32_t reserved_303; |
482 | uint32_t reserved_304; |
483 | uint32_t reserved_305; |
484 | uint32_t reserved_306; |
485 | uint32_t reserved_307; |
486 | uint32_t reserved_308; |
487 | uint32_t reserved_309; |
488 | uint32_t reserved_310; |
489 | uint32_t reserved_311; |
490 | uint32_t reserved_312; |
491 | uint32_t reserved_313; |
492 | uint32_t reserved_314; |
493 | uint32_t reserved_315; |
494 | uint32_t reserved_316; |
495 | uint32_t reserved_317; |
496 | uint32_t reserved_318; |
497 | uint32_t reserved_319; |
498 | uint32_t reserved_320; |
499 | uint32_t reserved_321; |
500 | uint32_t reserved_322; |
501 | uint32_t reserved_323; |
502 | uint32_t reserved_324; |
503 | uint32_t reserved_325; |
504 | uint32_t reserved_326; |
505 | uint32_t reserved_327; |
506 | uint32_t reserved_328; |
507 | uint32_t reserved_329; |
508 | uint32_t reserved_330; |
509 | uint32_t reserved_331; |
510 | uint32_t reserved_332; |
511 | uint32_t reserved_333; |
512 | uint32_t reserved_334; |
513 | uint32_t reserved_335; |
514 | uint32_t reserved_336; |
515 | uint32_t reserved_337; |
516 | uint32_t reserved_338; |
517 | uint32_t reserved_339; |
518 | uint32_t reserved_340; |
519 | uint32_t reserved_341; |
520 | uint32_t reserved_342; |
521 | uint32_t reserved_343; |
522 | uint32_t reserved_344; |
523 | uint32_t reserved_345; |
524 | uint32_t reserved_346; |
525 | uint32_t reserved_347; |
526 | uint32_t reserved_348; |
527 | uint32_t reserved_349; |
528 | uint32_t reserved_350; |
529 | uint32_t reserved_351; |
530 | uint32_t reserved_352; |
531 | uint32_t reserved_353; |
532 | uint32_t reserved_354; |
533 | uint32_t reserved_355; |
534 | uint32_t reserved_356; |
535 | uint32_t reserved_357; |
536 | uint32_t reserved_358; |
537 | uint32_t reserved_359; |
538 | uint32_t reserved_360; |
539 | uint32_t reserved_361; |
540 | uint32_t reserved_362; |
541 | uint32_t reserved_363; |
542 | uint32_t reserved_364; |
543 | uint32_t reserved_365; |
544 | uint32_t reserved_366; |
545 | uint32_t reserved_367; |
546 | uint32_t reserved_368; |
547 | uint32_t reserved_369; |
548 | uint32_t reserved_370; |
549 | uint32_t reserved_371; |
550 | uint32_t reserved_372; |
551 | uint32_t reserved_373; |
552 | uint32_t reserved_374; |
553 | uint32_t reserved_375; |
554 | uint32_t reserved_376; |
555 | uint32_t reserved_377; |
556 | uint32_t reserved_378; |
557 | uint32_t reserved_379; |
558 | uint32_t reserved_380; |
559 | uint32_t reserved_381; |
560 | uint32_t reserved_382; |
561 | uint32_t reserved_383; |
562 | uint32_t reserved_384; |
563 | uint32_t reserved_385; |
564 | uint32_t reserved_386; |
565 | uint32_t reserved_387; |
566 | uint32_t reserved_388; |
567 | uint32_t reserved_389; |
568 | uint32_t reserved_390; |
569 | uint32_t reserved_391; |
570 | uint32_t reserved_392; |
571 | uint32_t reserved_393; |
572 | uint32_t reserved_394; |
573 | uint32_t reserved_395; |
574 | uint32_t reserved_396; |
575 | uint32_t reserved_397; |
576 | uint32_t reserved_398; |
577 | uint32_t reserved_399; |
578 | uint32_t reserved_400; |
579 | uint32_t reserved_401; |
580 | uint32_t reserved_402; |
581 | uint32_t reserved_403; |
582 | uint32_t reserved_404; |
583 | uint32_t reserved_405; |
584 | uint32_t reserved_406; |
585 | uint32_t reserved_407; |
586 | uint32_t reserved_408; |
587 | uint32_t reserved_409; |
588 | uint32_t reserved_410; |
589 | uint32_t reserved_411; |
590 | uint32_t reserved_412; |
591 | uint32_t reserved_413; |
592 | uint32_t reserved_414; |
593 | uint32_t reserved_415; |
594 | uint32_t reserved_416; |
595 | uint32_t reserved_417; |
596 | uint32_t reserved_418; |
597 | uint32_t reserved_419; |
598 | uint32_t reserved_420; |
599 | uint32_t reserved_421; |
600 | uint32_t reserved_422; |
601 | uint32_t reserved_423; |
602 | uint32_t reserved_424; |
603 | uint32_t reserved_425; |
604 | uint32_t reserved_426; |
605 | uint32_t reserved_427; |
606 | uint32_t reserved_428; |
607 | uint32_t reserved_429; |
608 | uint32_t reserved_430; |
609 | uint32_t reserved_431; |
610 | uint32_t reserved_432; |
611 | uint32_t reserved_433; |
612 | uint32_t reserved_434; |
613 | uint32_t reserved_435; |
614 | uint32_t reserved_436; |
615 | uint32_t reserved_437; |
616 | uint32_t reserved_438; |
617 | uint32_t reserved_439; |
618 | uint32_t reserved_440; |
619 | uint32_t reserved_441; |
620 | uint32_t reserved_442; |
621 | uint32_t reserved_443; |
622 | uint32_t reserved_444; |
623 | uint32_t reserved_445; |
624 | uint32_t reserved_446; |
625 | uint32_t reserved_447; |
626 | uint32_t reserved_448; |
627 | uint32_t reserved_449; |
628 | uint32_t reserved_450; |
629 | uint32_t reserved_451; |
630 | uint32_t reserved_452; |
631 | uint32_t reserved_453; |
632 | uint32_t reserved_454; |
633 | uint32_t reserved_455; |
634 | uint32_t reserved_456; |
635 | uint32_t reserved_457; |
636 | uint32_t reserved_458; |
637 | uint32_t reserved_459; |
638 | uint32_t reserved_460; |
639 | uint32_t reserved_461; |
640 | uint32_t reserved_462; |
641 | uint32_t reserved_463; |
642 | uint32_t reserved_464; |
643 | uint32_t reserved_465; |
644 | uint32_t reserved_466; |
645 | uint32_t reserved_467; |
646 | uint32_t reserved_468; |
647 | uint32_t reserved_469; |
648 | uint32_t reserved_470; |
649 | uint32_t reserved_471; |
650 | uint32_t reserved_472; |
651 | uint32_t reserved_473; |
652 | uint32_t reserved_474; |
653 | uint32_t reserved_475; |
654 | uint32_t reserved_476; |
655 | uint32_t reserved_477; |
656 | uint32_t reserved_478; |
657 | uint32_t reserved_479; |
658 | uint32_t reserved_480; |
659 | uint32_t reserved_481; |
660 | uint32_t reserved_482; |
661 | uint32_t reserved_483; |
662 | uint32_t reserved_484; |
663 | uint32_t reserved_485; |
664 | uint32_t reserved_486; |
665 | uint32_t reserved_487; |
666 | uint32_t reserved_488; |
667 | uint32_t reserved_489; |
668 | uint32_t reserved_490; |
669 | uint32_t reserved_491; |
670 | uint32_t reserved_492; |
671 | uint32_t reserved_493; |
672 | uint32_t reserved_494; |
673 | uint32_t reserved_495; |
674 | uint32_t reserved_496; |
675 | uint32_t reserved_497; |
676 | uint32_t reserved_498; |
677 | uint32_t reserved_499; |
678 | uint32_t reserved_500; |
679 | uint32_t reserved_501; |
680 | uint32_t reserved_502; |
681 | uint32_t reserved_503; |
682 | uint32_t reserved_504; |
683 | uint32_t reserved_505; |
684 | uint32_t reserved_506; |
685 | uint32_t reserved_507; |
686 | uint32_t reserved_508; |
687 | uint32_t reserved_509; |
688 | uint32_t reserved_510; |
689 | uint32_t reserved_511; |
690 | }; |
691 | |
692 | struct v9_mqd_allocation { |
693 | struct v9_mqd mqd; |
694 | uint32_t wptr_poll_mem; |
695 | uint32_t rptr_report_mem; |
696 | uint32_t dynamic_cu_mask; |
697 | uint32_t dynamic_rb_mask; |
698 | }; |
699 | |
700 | /* from vega10 all CSA format is shifted to chain ib compatible mode */ |
701 | struct v9_ce_ib_state { |
702 | /* section of non chained ib part */ |
703 | uint32_t ce_ib_completion_status; |
704 | uint32_t ce_constegnine_count; |
705 | uint32_t ce_ibOffset_ib1; |
706 | uint32_t ce_ibOffset_ib2; |
707 | |
708 | /* section of chained ib */ |
709 | uint32_t ce_chainib_addrlo_ib1; |
710 | uint32_t ce_chainib_addrlo_ib2; |
711 | uint32_t ce_chainib_addrhi_ib1; |
712 | uint32_t ce_chainib_addrhi_ib2; |
713 | uint32_t ce_chainib_size_ib1; |
714 | uint32_t ce_chainib_size_ib2; |
715 | }; /* total 10 DWORD */ |
716 | |
717 | struct v9_de_ib_state { |
718 | /* section of non chained ib part */ |
719 | uint32_t ib_completion_status; |
720 | uint32_t de_constEngine_count; |
721 | uint32_t ib_offset_ib1; |
722 | uint32_t ib_offset_ib2; |
723 | |
724 | /* section of chained ib */ |
725 | uint32_t chain_ib_addrlo_ib1; |
726 | uint32_t chain_ib_addrlo_ib2; |
727 | uint32_t chain_ib_addrhi_ib1; |
728 | uint32_t chain_ib_addrhi_ib2; |
729 | uint32_t chain_ib_size_ib1; |
730 | uint32_t chain_ib_size_ib2; |
731 | |
732 | /* section of non chained ib part */ |
733 | uint32_t preamble_begin_ib1; |
734 | uint32_t preamble_begin_ib2; |
735 | uint32_t preamble_end_ib1; |
736 | uint32_t preamble_end_ib2; |
737 | |
738 | /* section of chained ib */ |
739 | uint32_t chain_ib_pream_addrlo_ib1; |
740 | uint32_t chain_ib_pream_addrlo_ib2; |
741 | uint32_t chain_ib_pream_addrhi_ib1; |
742 | uint32_t chain_ib_pream_addrhi_ib2; |
743 | |
744 | /* section of non chained ib part */ |
745 | uint32_t draw_indirect_baseLo; |
746 | uint32_t draw_indirect_baseHi; |
747 | uint32_t disp_indirect_baseLo; |
748 | uint32_t disp_indirect_baseHi; |
749 | uint32_t gds_backup_addrlo; |
750 | uint32_t gds_backup_addrhi; |
751 | uint32_t index_base_addrlo; |
752 | uint32_t index_base_addrhi; |
753 | uint32_t sample_cntl; |
754 | }; /* Total of 27 DWORD */ |
755 | |
756 | struct v9_gfx_meta_data { |
757 | /* 10 DWORD, address must be 4KB aligned */ |
758 | struct v9_ce_ib_state ce_payload; |
759 | uint32_t reserved1[54]; |
760 | /* 27 DWORD, address must be 64B aligned */ |
761 | struct v9_de_ib_state de_payload; |
762 | /* PFP IB base address which get pre-empted */ |
763 | uint32_t DeIbBaseAddrLo; |
764 | uint32_t DeIbBaseAddrHi; |
765 | uint32_t reserved2[931]; |
766 | }; /* Total of 4K Bytes */ |
767 | |
768 | #endif /* V9_STRUCTS_H_ */ |
769 | |