1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#if !defined (_vega10_ENUM_HEADER)
22#define _vega10_ENUM_HEADER
23
24#ifndef _DRIVER_BUILD
25#ifndef GL_ZERO
26#define GL__ZERO BLEND_ZERO
27#define GL__ONE BLEND_ONE
28#define GL__SRC_COLOR BLEND_SRC_COLOR
29#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
30#define GL__DST_COLOR BLEND_DST_COLOR
31#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
32#define GL__SRC_ALPHA BLEND_SRC_ALPHA
33#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
34#define GL__DST_ALPHA BLEND_DST_ALPHA
35#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
36#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
37#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
38#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
39#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
40#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
41#endif
42#endif
43
44/*******************************************************
45 * GDS DATA_TYPE Enums
46 *******************************************************/
47
48#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
49#define ENUMS_GDS_PERFCOUNT_SELECT_H
50typedef enum GDS_PERFCOUNT_SELECT {
51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
53 GDS_PERF_SEL_WBUF_FLUSH = 2,
54 GDS_PERF_SEL_WR_COMP = 3,
55 GDS_PERF_SEL_WBUF_WR = 4,
56 GDS_PERF_SEL_RBUF_HIT = 5,
57 GDS_PERF_SEL_RBUF_MISS = 6,
58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
59 GDS_PERF_SEL_SE0_SH0_RET = 8,
60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
73 GDS_PERF_SEL_SE0_SH1_RET = 22,
74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
87 GDS_PERF_SEL_SE1_SH0_RET = 36,
88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
101 GDS_PERF_SEL_SE1_SH1_RET = 50,
102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
115 GDS_PERF_SEL_SE2_SH0_RET = 64,
116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
129 GDS_PERF_SEL_SE2_SH1_RET = 78,
130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
143 GDS_PERF_SEL_SE3_SH0_RET = 92,
144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
157 GDS_PERF_SEL_SE3_SH1_RET = 106,
158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
170 GDS_PERF_SEL_GWS_RELEASED = 119,
171 GDS_PERF_SEL_GWS_BYPASS = 120,
172} GDS_PERFCOUNT_SELECT;
173#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
174
175/*******************************************************
176 * Chip Enums
177 *******************************************************/
178
179/*
180 * MEM_PWR_FORCE_CTRL enum
181 */
182
183typedef enum MEM_PWR_FORCE_CTRL {
184NO_FORCE_REQUEST = 0x00000000,
185FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
186FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
187FORCE_SHUT_DOWN_REQUEST = 0x00000003,
188} MEM_PWR_FORCE_CTRL;
189
190/*
191 * MEM_PWR_FORCE_CTRL2 enum
192 */
193
194typedef enum MEM_PWR_FORCE_CTRL2 {
195NO_FORCE_REQ = 0x00000000,
196FORCE_LIGHT_SLEEP_REQ = 0x00000001,
197} MEM_PWR_FORCE_CTRL2;
198
199/*
200 * MEM_PWR_DIS_CTRL enum
201 */
202
203typedef enum MEM_PWR_DIS_CTRL {
204ENABLE_MEM_PWR_CTRL = 0x00000000,
205DISABLE_MEM_PWR_CTRL = 0x00000001,
206} MEM_PWR_DIS_CTRL;
207
208/*
209 * MEM_PWR_SEL_CTRL enum
210 */
211
212typedef enum MEM_PWR_SEL_CTRL {
213DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
214DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
215DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
216} MEM_PWR_SEL_CTRL;
217
218/*
219 * MEM_PWR_SEL_CTRL2 enum
220 */
221
222typedef enum MEM_PWR_SEL_CTRL2 {
223DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
224DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
225} MEM_PWR_SEL_CTRL2;
226
227/*
228 * RowSize enum
229 */
230
231typedef enum RowSize {
232ADDR_CONFIG_1KB_ROW = 0x00000000,
233ADDR_CONFIG_2KB_ROW = 0x00000001,
234ADDR_CONFIG_4KB_ROW = 0x00000002,
235} RowSize;
236
237/*
238 * SurfaceEndian enum
239 */
240
241typedef enum SurfaceEndian {
242ENDIAN_NONE = 0x00000000,
243ENDIAN_8IN16 = 0x00000001,
244ENDIAN_8IN32 = 0x00000002,
245ENDIAN_8IN64 = 0x00000003,
246} SurfaceEndian;
247
248/*
249 * ArrayMode enum
250 */
251
252typedef enum ArrayMode {
253ARRAY_LINEAR_GENERAL = 0x00000000,
254ARRAY_LINEAR_ALIGNED = 0x00000001,
255ARRAY_1D_TILED_THIN1 = 0x00000002,
256ARRAY_1D_TILED_THICK = 0x00000003,
257ARRAY_2D_TILED_THIN1 = 0x00000004,
258ARRAY_PRT_TILED_THIN1 = 0x00000005,
259ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
260ARRAY_2D_TILED_THICK = 0x00000007,
261ARRAY_2D_TILED_XTHICK = 0x00000008,
262ARRAY_PRT_TILED_THICK = 0x00000009,
263ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
264ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
265ARRAY_3D_TILED_THIN1 = 0x0000000c,
266ARRAY_3D_TILED_THICK = 0x0000000d,
267ARRAY_3D_TILED_XTHICK = 0x0000000e,
268ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
269} ArrayMode;
270
271/*
272 * NumPipes enum
273 */
274
275typedef enum NumPipes {
276ADDR_CONFIG_1_PIPE = 0x00000000,
277ADDR_CONFIG_2_PIPE = 0x00000001,
278ADDR_CONFIG_4_PIPE = 0x00000002,
279ADDR_CONFIG_8_PIPE = 0x00000003,
280ADDR_CONFIG_16_PIPE = 0x00000004,
281ADDR_CONFIG_32_PIPE = 0x00000005,
282} NumPipes;
283
284/*
285 * NumBanksConfig enum
286 */
287
288typedef enum NumBanksConfig {
289ADDR_CONFIG_1_BANK = 0x00000000,
290ADDR_CONFIG_2_BANK = 0x00000001,
291ADDR_CONFIG_4_BANK = 0x00000002,
292ADDR_CONFIG_8_BANK = 0x00000003,
293ADDR_CONFIG_16_BANK = 0x00000004,
294} NumBanksConfig;
295
296/*
297 * PipeInterleaveSize enum
298 */
299
300typedef enum PipeInterleaveSize {
301ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
302ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
303ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
304ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
305} PipeInterleaveSize;
306
307/*
308 * BankInterleaveSize enum
309 */
310
311typedef enum BankInterleaveSize {
312ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
313ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
314ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
315ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
316} BankInterleaveSize;
317
318/*
319 * NumShaderEngines enum
320 */
321
322typedef enum NumShaderEngines {
323ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
324ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
325ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
326ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
327} NumShaderEngines;
328
329/*
330 * NumRbPerShaderEngine enum
331 */
332
333typedef enum NumRbPerShaderEngine {
334ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
335ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
336ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
337} NumRbPerShaderEngine;
338
339/*
340 * NumGPUs enum
341 */
342
343typedef enum NumGPUs {
344ADDR_CONFIG_1_GPU = 0x00000000,
345ADDR_CONFIG_2_GPU = 0x00000001,
346ADDR_CONFIG_4_GPU = 0x00000002,
347ADDR_CONFIG_8_GPU = 0x00000003,
348} NumGPUs;
349
350/*
351 * NumMaxCompressedFragments enum
352 */
353
354typedef enum NumMaxCompressedFragments {
355ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
356ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
357ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
358ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
359} NumMaxCompressedFragments;
360
361/*
362 * ShaderEngineTileSize enum
363 */
364
365typedef enum ShaderEngineTileSize {
366ADDR_CONFIG_SE_TILE_16 = 0x00000000,
367ADDR_CONFIG_SE_TILE_32 = 0x00000001,
368} ShaderEngineTileSize;
369
370/*
371 * MultiGPUTileSize enum
372 */
373
374typedef enum MultiGPUTileSize {
375ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
376ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
377ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
378ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
379} MultiGPUTileSize;
380
381/*
382 * NumLowerPipes enum
383 */
384
385typedef enum NumLowerPipes {
386ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
387ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
388} NumLowerPipes;
389
390/*
391 * ColorTransform enum
392 */
393
394typedef enum ColorTransform {
395DCC_CT_AUTO = 0x00000000,
396DCC_CT_NONE = 0x00000001,
397ABGR_TO_A_BG_G_RB = 0x00000002,
398BGRA_TO_BG_G_RB_A = 0x00000003,
399} ColorTransform;
400
401/*
402 * CompareRef enum
403 */
404
405typedef enum CompareRef {
406REF_NEVER = 0x00000000,
407REF_LESS = 0x00000001,
408REF_EQUAL = 0x00000002,
409REF_LEQUAL = 0x00000003,
410REF_GREATER = 0x00000004,
411REF_NOTEQUAL = 0x00000005,
412REF_GEQUAL = 0x00000006,
413REF_ALWAYS = 0x00000007,
414} CompareRef;
415
416/*
417 * ReadSize enum
418 */
419
420typedef enum ReadSize {
421READ_256_BITS = 0x00000000,
422READ_512_BITS = 0x00000001,
423} ReadSize;
424
425/*
426 * DepthFormat enum
427 */
428
429typedef enum DepthFormat {
430DEPTH_INVALID = 0x00000000,
431DEPTH_16 = 0x00000001,
432DEPTH_X8_24 = 0x00000002,
433DEPTH_8_24 = 0x00000003,
434DEPTH_X8_24_FLOAT = 0x00000004,
435DEPTH_8_24_FLOAT = 0x00000005,
436DEPTH_32_FLOAT = 0x00000006,
437DEPTH_X24_8_32_FLOAT = 0x00000007,
438} DepthFormat;
439
440/*
441 * ZFormat enum
442 */
443
444typedef enum ZFormat {
445Z_INVALID = 0x00000000,
446Z_16 = 0x00000001,
447Z_24 = 0x00000002,
448Z_32_FLOAT = 0x00000003,
449} ZFormat;
450
451/*
452 * StencilFormat enum
453 */
454
455typedef enum StencilFormat {
456STENCIL_INVALID = 0x00000000,
457STENCIL_8 = 0x00000001,
458} StencilFormat;
459
460/*
461 * CmaskMode enum
462 */
463
464typedef enum CmaskMode {
465CMASK_CLEAR_NONE = 0x00000000,
466CMASK_CLEAR_ONE = 0x00000001,
467CMASK_CLEAR_ALL = 0x00000002,
468CMASK_ANY_EXPANDED = 0x00000003,
469CMASK_ALPHA0_FRAG1 = 0x00000004,
470CMASK_ALPHA0_FRAG2 = 0x00000005,
471CMASK_ALPHA0_FRAG4 = 0x00000006,
472CMASK_ALPHA0_FRAGS = 0x00000007,
473CMASK_ALPHA1_FRAG1 = 0x00000008,
474CMASK_ALPHA1_FRAG2 = 0x00000009,
475CMASK_ALPHA1_FRAG4 = 0x0000000a,
476CMASK_ALPHA1_FRAGS = 0x0000000b,
477CMASK_ALPHAX_FRAG1 = 0x0000000c,
478CMASK_ALPHAX_FRAG2 = 0x0000000d,
479CMASK_ALPHAX_FRAG4 = 0x0000000e,
480CMASK_ALPHAX_FRAGS = 0x0000000f,
481} CmaskMode;
482
483/*
484 * QuadExportFormat enum
485 */
486
487typedef enum QuadExportFormat {
488EXPORT_UNUSED = 0x00000000,
489EXPORT_32_R = 0x00000001,
490EXPORT_32_GR = 0x00000002,
491EXPORT_32_AR = 0x00000003,
492EXPORT_FP16_ABGR = 0x00000004,
493EXPORT_UNSIGNED16_ABGR = 0x00000005,
494EXPORT_SIGNED16_ABGR = 0x00000006,
495EXPORT_32_ABGR = 0x00000007,
496EXPORT_32BPP_8PIX = 0x00000008,
497EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
498EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
499EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
500} QuadExportFormat;
501
502/*
503 * QuadExportFormatOld enum
504 */
505
506typedef enum QuadExportFormatOld {
507EXPORT_4P_32BPC_ABGR = 0x00000000,
508EXPORT_4P_16BPC_ABGR = 0x00000001,
509EXPORT_4P_32BPC_GR = 0x00000002,
510EXPORT_4P_32BPC_AR = 0x00000003,
511EXPORT_2P_32BPC_ABGR = 0x00000004,
512EXPORT_8P_32BPC_R = 0x00000005,
513} QuadExportFormatOld;
514
515/*
516 * ColorFormat enum
517 */
518
519typedef enum ColorFormat {
520COLOR_INVALID = 0x00000000,
521COLOR_8 = 0x00000001,
522COLOR_16 = 0x00000002,
523COLOR_8_8 = 0x00000003,
524COLOR_32 = 0x00000004,
525COLOR_16_16 = 0x00000005,
526COLOR_10_11_11 = 0x00000006,
527COLOR_11_11_10 = 0x00000007,
528COLOR_10_10_10_2 = 0x00000008,
529COLOR_2_10_10_10 = 0x00000009,
530COLOR_8_8_8_8 = 0x0000000a,
531COLOR_32_32 = 0x0000000b,
532COLOR_16_16_16_16 = 0x0000000c,
533COLOR_RESERVED_13 = 0x0000000d,
534COLOR_32_32_32_32 = 0x0000000e,
535COLOR_RESERVED_15 = 0x0000000f,
536COLOR_5_6_5 = 0x00000010,
537COLOR_1_5_5_5 = 0x00000011,
538COLOR_5_5_5_1 = 0x00000012,
539COLOR_4_4_4_4 = 0x00000013,
540COLOR_8_24 = 0x00000014,
541COLOR_24_8 = 0x00000015,
542COLOR_X24_8_32_FLOAT = 0x00000016,
543COLOR_RESERVED_23 = 0x00000017,
544COLOR_RESERVED_24 = 0x00000018,
545COLOR_RESERVED_25 = 0x00000019,
546COLOR_RESERVED_26 = 0x0000001a,
547COLOR_RESERVED_27 = 0x0000001b,
548COLOR_RESERVED_28 = 0x0000001c,
549COLOR_RESERVED_29 = 0x0000001d,
550COLOR_RESERVED_30 = 0x0000001e,
551COLOR_2_10_10_10_6E4 = 0x0000001f,
552} ColorFormat;
553
554/*
555 * SurfaceFormat enum
556 */
557
558typedef enum SurfaceFormat {
559FMT_INVALID = 0x00000000,
560FMT_8 = 0x00000001,
561FMT_16 = 0x00000002,
562FMT_8_8 = 0x00000003,
563FMT_32 = 0x00000004,
564FMT_16_16 = 0x00000005,
565FMT_10_11_11 = 0x00000006,
566FMT_11_11_10 = 0x00000007,
567FMT_10_10_10_2 = 0x00000008,
568FMT_2_10_10_10 = 0x00000009,
569FMT_8_8_8_8 = 0x0000000a,
570FMT_32_32 = 0x0000000b,
571FMT_16_16_16_16 = 0x0000000c,
572FMT_32_32_32 = 0x0000000d,
573FMT_32_32_32_32 = 0x0000000e,
574FMT_RESERVED_4 = 0x0000000f,
575FMT_5_6_5 = 0x00000010,
576FMT_1_5_5_5 = 0x00000011,
577FMT_5_5_5_1 = 0x00000012,
578FMT_4_4_4_4 = 0x00000013,
579FMT_8_24 = 0x00000014,
580FMT_24_8 = 0x00000015,
581FMT_X24_8_32_FLOAT = 0x00000016,
582FMT_RESERVED_33 = 0x00000017,
583FMT_11_11_10_FLOAT = 0x00000018,
584FMT_16_FLOAT = 0x00000019,
585FMT_32_FLOAT = 0x0000001a,
586FMT_16_16_FLOAT = 0x0000001b,
587FMT_8_24_FLOAT = 0x0000001c,
588FMT_24_8_FLOAT = 0x0000001d,
589FMT_32_32_FLOAT = 0x0000001e,
590FMT_10_11_11_FLOAT = 0x0000001f,
591FMT_16_16_16_16_FLOAT = 0x00000020,
592FMT_3_3_2 = 0x00000021,
593FMT_6_5_5 = 0x00000022,
594FMT_32_32_32_32_FLOAT = 0x00000023,
595FMT_RESERVED_36 = 0x00000024,
596FMT_1 = 0x00000025,
597FMT_1_REVERSED = 0x00000026,
598FMT_GB_GR = 0x00000027,
599FMT_BG_RG = 0x00000028,
600FMT_32_AS_8 = 0x00000029,
601FMT_32_AS_8_8 = 0x0000002a,
602FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
603FMT_8_8_8 = 0x0000002c,
604FMT_16_16_16 = 0x0000002d,
605FMT_16_16_16_FLOAT = 0x0000002e,
606FMT_4_4 = 0x0000002f,
607FMT_32_32_32_FLOAT = 0x00000030,
608FMT_BC1 = 0x00000031,
609FMT_BC2 = 0x00000032,
610FMT_BC3 = 0x00000033,
611FMT_BC4 = 0x00000034,
612FMT_BC5 = 0x00000035,
613FMT_BC6 = 0x00000036,
614FMT_BC7 = 0x00000037,
615FMT_32_AS_32_32_32_32 = 0x00000038,
616FMT_APC3 = 0x00000039,
617FMT_APC4 = 0x0000003a,
618FMT_APC5 = 0x0000003b,
619FMT_APC6 = 0x0000003c,
620FMT_APC7 = 0x0000003d,
621FMT_CTX1 = 0x0000003e,
622FMT_RESERVED_63 = 0x0000003f,
623} SurfaceFormat;
624
625/*
626 * BUF_DATA_FORMAT enum
627 */
628
629typedef enum BUF_DATA_FORMAT {
630BUF_DATA_FORMAT_INVALID = 0x00000000,
631BUF_DATA_FORMAT_8 = 0x00000001,
632BUF_DATA_FORMAT_16 = 0x00000002,
633BUF_DATA_FORMAT_8_8 = 0x00000003,
634BUF_DATA_FORMAT_32 = 0x00000004,
635BUF_DATA_FORMAT_16_16 = 0x00000005,
636BUF_DATA_FORMAT_10_11_11 = 0x00000006,
637BUF_DATA_FORMAT_11_11_10 = 0x00000007,
638BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
639BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
640BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
641BUF_DATA_FORMAT_32_32 = 0x0000000b,
642BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
643BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
644BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
645BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
646} BUF_DATA_FORMAT;
647
648/*
649 * IMG_DATA_FORMAT enum
650 */
651
652typedef enum IMG_DATA_FORMAT {
653IMG_DATA_FORMAT_INVALID = 0x00000000,
654IMG_DATA_FORMAT_8 = 0x00000001,
655IMG_DATA_FORMAT_16 = 0x00000002,
656IMG_DATA_FORMAT_8_8 = 0x00000003,
657IMG_DATA_FORMAT_32 = 0x00000004,
658IMG_DATA_FORMAT_16_16 = 0x00000005,
659IMG_DATA_FORMAT_10_11_11 = 0x00000006,
660IMG_DATA_FORMAT_11_11_10 = 0x00000007,
661IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
662IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
663IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
664IMG_DATA_FORMAT_32_32 = 0x0000000b,
665IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
666IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
667IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
668IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
669IMG_DATA_FORMAT_5_6_5 = 0x00000010,
670IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
671IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
672IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
673IMG_DATA_FORMAT_8_24 = 0x00000014,
674IMG_DATA_FORMAT_24_8 = 0x00000015,
675IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
676IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x00000017,
677IMG_DATA_FORMAT_ETC2_RGB = 0x00000018,
678IMG_DATA_FORMAT_ETC2_RGBA = 0x00000019,
679IMG_DATA_FORMAT_ETC2_R = 0x0000001a,
680IMG_DATA_FORMAT_ETC2_RG = 0x0000001b,
681IMG_DATA_FORMAT_ETC2_RGBA1 = 0x0000001c,
682IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
683IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
684IMG_DATA_FORMAT_6E4 = 0x0000001f,
685IMG_DATA_FORMAT_GB_GR = 0x00000020,
686IMG_DATA_FORMAT_BG_RG = 0x00000021,
687IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
688IMG_DATA_FORMAT_BC1 = 0x00000023,
689IMG_DATA_FORMAT_BC2 = 0x00000024,
690IMG_DATA_FORMAT_BC3 = 0x00000025,
691IMG_DATA_FORMAT_BC4 = 0x00000026,
692IMG_DATA_FORMAT_BC5 = 0x00000027,
693IMG_DATA_FORMAT_BC6 = 0x00000028,
694IMG_DATA_FORMAT_BC7 = 0x00000029,
695IMG_DATA_FORMAT_16_AS_32_32 = 0x0000002a,
696IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x0000002b,
697IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x0000002c,
698IMG_DATA_FORMAT_FMASK = 0x0000002d,
699IMG_DATA_FORMAT_ASTC_2D_LDR = 0x0000002e,
700IMG_DATA_FORMAT_ASTC_2D_HDR = 0x0000002f,
701IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB = 0x00000030,
702IMG_DATA_FORMAT_ASTC_3D_LDR = 0x00000031,
703IMG_DATA_FORMAT_ASTC_3D_HDR = 0x00000032,
704IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB = 0x00000033,
705IMG_DATA_FORMAT_N_IN_16 = 0x00000034,
706IMG_DATA_FORMAT_N_IN_16_16 = 0x00000035,
707IMG_DATA_FORMAT_N_IN_16_16_16_16 = 0x00000036,
708IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16 = 0x00000037,
709IMG_DATA_FORMAT_RESERVED_56 = 0x00000038,
710IMG_DATA_FORMAT_4_4 = 0x00000039,
711IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
712IMG_DATA_FORMAT_RESERVED_59 = 0x0000003b,
713IMG_DATA_FORMAT_RESERVED_60 = 0x0000003c,
714IMG_DATA_FORMAT_8_AS_32 = 0x0000003d,
715IMG_DATA_FORMAT_8_AS_32_32 = 0x0000003e,
716IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
717} IMG_DATA_FORMAT;
718
719/*
720 * BUF_NUM_FORMAT enum
721 */
722
723typedef enum BUF_NUM_FORMAT {
724BUF_NUM_FORMAT_UNORM = 0x00000000,
725BUF_NUM_FORMAT_SNORM = 0x00000001,
726BUF_NUM_FORMAT_USCALED = 0x00000002,
727BUF_NUM_FORMAT_SSCALED = 0x00000003,
728BUF_NUM_FORMAT_UINT = 0x00000004,
729BUF_NUM_FORMAT_SINT = 0x00000005,
730BUF_NUM_FORMAT_UNORM_UINT = 0x00000006,
731BUF_NUM_FORMAT_FLOAT = 0x00000007,
732} BUF_NUM_FORMAT;
733
734/*
735 * IMG_NUM_FORMAT enum
736 */
737
738typedef enum IMG_NUM_FORMAT {
739IMG_NUM_FORMAT_UNORM = 0x00000000,
740IMG_NUM_FORMAT_SNORM = 0x00000001,
741IMG_NUM_FORMAT_USCALED = 0x00000002,
742IMG_NUM_FORMAT_SSCALED = 0x00000003,
743IMG_NUM_FORMAT_UINT = 0x00000004,
744IMG_NUM_FORMAT_SINT = 0x00000005,
745IMG_NUM_FORMAT_UNORM_UINT = 0x00000006,
746IMG_NUM_FORMAT_FLOAT = 0x00000007,
747IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
748IMG_NUM_FORMAT_SRGB = 0x00000009,
749IMG_NUM_FORMAT_RESERVED_10 = 0x0000000a,
750IMG_NUM_FORMAT_RESERVED_11 = 0x0000000b,
751IMG_NUM_FORMAT_RESERVED_12 = 0x0000000c,
752IMG_NUM_FORMAT_RESERVED_13 = 0x0000000d,
753IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
754IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
755} IMG_NUM_FORMAT;
756
757/*
758 * IMG_NUM_FORMAT_FMASK enum
759 */
760
761typedef enum IMG_NUM_FORMAT_FMASK {
762IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
763IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
764IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
765IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
766IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
767IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
768IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
769IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
770IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
771IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
772IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
773IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
774IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
775IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
776IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
777IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
778} IMG_NUM_FORMAT_FMASK;
779
780/*
781 * IMG_NUM_FORMAT_N_IN_16 enum
782 */
783
784typedef enum IMG_NUM_FORMAT_N_IN_16 {
785IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
786IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
787IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
788IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
789IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
790IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
791IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
792IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
793IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
794IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
795IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
796IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
797IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
798IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
799IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
800IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
801} IMG_NUM_FORMAT_N_IN_16;
802
803/*
804 * IMG_NUM_FORMAT_ASTC_2D enum
805 */
806
807typedef enum IMG_NUM_FORMAT_ASTC_2D {
808IMG_NUM_FORMAT_ASTC_2D_4x4 = 0x00000000,
809IMG_NUM_FORMAT_ASTC_2D_5x4 = 0x00000001,
810IMG_NUM_FORMAT_ASTC_2D_5x5 = 0x00000002,
811IMG_NUM_FORMAT_ASTC_2D_6x5 = 0x00000003,
812IMG_NUM_FORMAT_ASTC_2D_6x6 = 0x00000004,
813IMG_NUM_FORMAT_ASTC_2D_8x5 = 0x00000005,
814IMG_NUM_FORMAT_ASTC_2D_8x6 = 0x00000006,
815IMG_NUM_FORMAT_ASTC_2D_8x8 = 0x00000007,
816IMG_NUM_FORMAT_ASTC_2D_10x5 = 0x00000008,
817IMG_NUM_FORMAT_ASTC_2D_10x6 = 0x00000009,
818IMG_NUM_FORMAT_ASTC_2D_10x8 = 0x0000000a,
819IMG_NUM_FORMAT_ASTC_2D_10x10 = 0x0000000b,
820IMG_NUM_FORMAT_ASTC_2D_12x10 = 0x0000000c,
821IMG_NUM_FORMAT_ASTC_2D_12x12 = 0x0000000d,
822IMG_NUM_FORMAT_ASTC_2D_RESERVED_14 = 0x0000000e,
823IMG_NUM_FORMAT_ASTC_2D_RESERVED_15 = 0x0000000f,
824} IMG_NUM_FORMAT_ASTC_2D;
825
826/*
827 * IMG_NUM_FORMAT_ASTC_3D enum
828 */
829
830typedef enum IMG_NUM_FORMAT_ASTC_3D {
831IMG_NUM_FORMAT_ASTC_3D_3x3x3 = 0x00000000,
832IMG_NUM_FORMAT_ASTC_3D_4x3x3 = 0x00000001,
833IMG_NUM_FORMAT_ASTC_3D_4x4x3 = 0x00000002,
834IMG_NUM_FORMAT_ASTC_3D_4x4x4 = 0x00000003,
835IMG_NUM_FORMAT_ASTC_3D_5x4x4 = 0x00000004,
836IMG_NUM_FORMAT_ASTC_3D_5x5x4 = 0x00000005,
837IMG_NUM_FORMAT_ASTC_3D_5x5x5 = 0x00000006,
838IMG_NUM_FORMAT_ASTC_3D_6x5x5 = 0x00000007,
839IMG_NUM_FORMAT_ASTC_3D_6x6x5 = 0x00000008,
840IMG_NUM_FORMAT_ASTC_3D_6x6x6 = 0x00000009,
841IMG_NUM_FORMAT_ASTC_3D_RESERVED_10 = 0x0000000a,
842IMG_NUM_FORMAT_ASTC_3D_RESERVED_11 = 0x0000000b,
843IMG_NUM_FORMAT_ASTC_3D_RESERVED_12 = 0x0000000c,
844IMG_NUM_FORMAT_ASTC_3D_RESERVED_13 = 0x0000000d,
845IMG_NUM_FORMAT_ASTC_3D_RESERVED_14 = 0x0000000e,
846IMG_NUM_FORMAT_ASTC_3D_RESERVED_15 = 0x0000000f,
847} IMG_NUM_FORMAT_ASTC_3D;
848
849/*
850 * TileType enum
851 */
852
853typedef enum TileType {
854ARRAY_COLOR_TILE = 0x00000000,
855ARRAY_DEPTH_TILE = 0x00000001,
856} TileType;
857
858/*
859 * NonDispTilingOrder enum
860 */
861
862typedef enum NonDispTilingOrder {
863ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
864ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
865} NonDispTilingOrder;
866
867/*
868 * MicroTileMode enum
869 */
870
871typedef enum MicroTileMode {
872ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
873ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
874ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
875ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
876ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
877} MicroTileMode;
878
879/*
880 * TileSplit enum
881 */
882
883typedef enum TileSplit {
884ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
885ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
886ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
887ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
888ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
889ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
890ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
891} TileSplit;
892
893/*
894 * SampleSplit enum
895 */
896
897typedef enum SampleSplit {
898ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
899ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
900ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
901ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
902} SampleSplit;
903
904/*
905 * PipeConfig enum
906 */
907
908typedef enum PipeConfig {
909ADDR_SURF_P2 = 0x00000000,
910ADDR_SURF_P2_RESERVED0 = 0x00000001,
911ADDR_SURF_P2_RESERVED1 = 0x00000002,
912ADDR_SURF_P2_RESERVED2 = 0x00000003,
913ADDR_SURF_P4_8x16 = 0x00000004,
914ADDR_SURF_P4_16x16 = 0x00000005,
915ADDR_SURF_P4_16x32 = 0x00000006,
916ADDR_SURF_P4_32x32 = 0x00000007,
917ADDR_SURF_P8_16x16_8x16 = 0x00000008,
918ADDR_SURF_P8_16x32_8x16 = 0x00000009,
919ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
920ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
921ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
922ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
923ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
924ADDR_SURF_P8_RESERVED0 = 0x0000000f,
925ADDR_SURF_P16_32x32_8x16 = 0x00000010,
926ADDR_SURF_P16_32x32_16x16 = 0x00000011,
927} PipeConfig;
928
929/*
930 * SeEnable enum
931 */
932
933typedef enum SeEnable {
934ADDR_CONFIG_DISABLE_SE = 0x00000000,
935ADDR_CONFIG_ENABLE_SE = 0x00000001,
936} SeEnable;
937
938/*
939 * NumBanks enum
940 */
941
942typedef enum NumBanks {
943ADDR_SURF_2_BANK = 0x00000000,
944ADDR_SURF_4_BANK = 0x00000001,
945ADDR_SURF_8_BANK = 0x00000002,
946ADDR_SURF_16_BANK = 0x00000003,
947} NumBanks;
948
949/*
950 * BankWidth enum
951 */
952
953typedef enum BankWidth {
954ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
955ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
956ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
957ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
958} BankWidth;
959
960/*
961 * BankHeight enum
962 */
963
964typedef enum BankHeight {
965ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
966ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
967ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
968ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
969} BankHeight;
970
971/*
972 * BankWidthHeight enum
973 */
974
975typedef enum BankWidthHeight {
976ADDR_SURF_BANK_WH_1 = 0x00000000,
977ADDR_SURF_BANK_WH_2 = 0x00000001,
978ADDR_SURF_BANK_WH_4 = 0x00000002,
979ADDR_SURF_BANK_WH_8 = 0x00000003,
980} BankWidthHeight;
981
982/*
983 * MacroTileAspect enum
984 */
985
986typedef enum MacroTileAspect {
987ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
988ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
989ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
990ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
991} MacroTileAspect;
992
993/*
994 * GATCL1RequestType enum
995 */
996
997typedef enum GATCL1RequestType {
998GATCL1_TYPE_NORMAL = 0x00000000,
999GATCL1_TYPE_SHOOTDOWN = 0x00000001,
1000GATCL1_TYPE_BYPASS = 0x00000002,
1001} GATCL1RequestType;
1002
1003/*
1004 * UTCL1RequestType enum
1005 */
1006
1007typedef enum UTCL1RequestType {
1008UTCL1_TYPE_NORMAL = 0x00000000,
1009UTCL1_TYPE_SHOOTDOWN = 0x00000001,
1010UTCL1_TYPE_BYPASS = 0x00000002,
1011} UTCL1RequestType;
1012
1013/*
1014 * UTCL1FaultType enum
1015 */
1016
1017typedef enum UTCL1FaultType {
1018UTCL1_XNACK_SUCCESS = 0x00000000,
1019UTCL1_XNACK_RETRY = 0x00000001,
1020UTCL1_XNACK_PRT = 0x00000002,
1021UTCL1_XNACK_NO_RETRY = 0x00000003,
1022} UTCL1FaultType;
1023
1024/*
1025 * TCC_CACHE_POLICIES enum
1026 */
1027
1028typedef enum TCC_CACHE_POLICIES {
1029TCC_CACHE_POLICY_LRU = 0x00000000,
1030TCC_CACHE_POLICY_STREAM = 0x00000001,
1031} TCC_CACHE_POLICIES;
1032
1033/*
1034 * MTYPE enum
1035 */
1036
1037typedef enum MTYPE {
1038MTYPE_NC = 0x00000000,
1039MTYPE_WC = 0x00000001,
1040MTYPE_CC = 0x00000002,
1041MTYPE_UC = 0x00000003,
1042} MTYPE;
1043
1044/*
1045 * RMI_CID enum
1046 */
1047
1048typedef enum RMI_CID {
1049RMI_CID_CC = 0x00000000,
1050RMI_CID_FC = 0x00000001,
1051RMI_CID_CM = 0x00000002,
1052RMI_CID_DC = 0x00000003,
1053RMI_CID_Z = 0x00000004,
1054RMI_CID_S = 0x00000005,
1055RMI_CID_TILE = 0x00000006,
1056RMI_CID_ZPCPSD = 0x00000007,
1057} RMI_CID;
1058
1059/*
1060 * PERFMON_COUNTER_MODE enum
1061 */
1062
1063typedef enum PERFMON_COUNTER_MODE {
1064PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
1065PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
1066PERFMON_COUNTER_MODE_MAX = 0x00000002,
1067PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
1068PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
1069PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
1070PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
1071PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
1072PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
1073PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
1074PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
1075} PERFMON_COUNTER_MODE;
1076
1077/*
1078 * PERFMON_SPM_MODE enum
1079 */
1080
1081typedef enum PERFMON_SPM_MODE {
1082PERFMON_SPM_MODE_OFF = 0x00000000,
1083PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
1084PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
1085PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
1086PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
1087PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
1088PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
1089PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
1090PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
1091PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
1092PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
1093} PERFMON_SPM_MODE;
1094
1095/*
1096 * SurfaceTiling enum
1097 */
1098
1099typedef enum SurfaceTiling {
1100ARRAY_LINEAR = 0x00000000,
1101ARRAY_TILED = 0x00000001,
1102} SurfaceTiling;
1103
1104/*
1105 * SurfaceArray enum
1106 */
1107
1108typedef enum SurfaceArray {
1109ARRAY_1D = 0x00000000,
1110ARRAY_2D = 0x00000001,
1111ARRAY_3D = 0x00000002,
1112ARRAY_3D_SLICE = 0x00000003,
1113} SurfaceArray;
1114
1115/*
1116 * ColorArray enum
1117 */
1118
1119typedef enum ColorArray {
1120ARRAY_2D_ALT_COLOR = 0x00000000,
1121ARRAY_2D_COLOR = 0x00000001,
1122ARRAY_3D_SLICE_COLOR = 0x00000003,
1123} ColorArray;
1124
1125/*
1126 * DepthArray enum
1127 */
1128
1129typedef enum DepthArray {
1130ARRAY_2D_ALT_DEPTH = 0x00000000,
1131ARRAY_2D_DEPTH = 0x00000001,
1132} DepthArray;
1133
1134/*
1135 * ENUM_NUM_SIMD_PER_CU enum
1136 */
1137
1138typedef enum ENUM_NUM_SIMD_PER_CU {
1139NUM_SIMD_PER_CU = 0x00000004,
1140} ENUM_NUM_SIMD_PER_CU;
1141
1142/*
1143 * DSM_ENABLE_ERROR_INJECT enum
1144 */
1145
1146typedef enum DSM_ENABLE_ERROR_INJECT {
1147DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
1148DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
1149DSM_ENABLE_ERROR_INJECT_DOUBLE = 0x00000002,
1150DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED = 0x00000003,
1151} DSM_ENABLE_ERROR_INJECT;
1152
1153/*
1154 * DSM_SELECT_INJECT_DELAY enum
1155 */
1156
1157typedef enum DSM_SELECT_INJECT_DELAY {
1158DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
1159DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
1160} DSM_SELECT_INJECT_DELAY;
1161
1162/*
1163 * SWIZZLE_TYPE_ENUM enum
1164 */
1165
1166typedef enum SWIZZLE_TYPE_ENUM {
1167SW_Z = 0x00000000,
1168SW_S = 0x00000001,
1169SW_D = 0x00000002,
1170SW_R = 0x00000003,
1171SW_L = 0x00000004,
1172} SWIZZLE_TYPE_ENUM;
1173
1174/*
1175 * TC_MICRO_TILE_MODE enum
1176 */
1177
1178typedef enum TC_MICRO_TILE_MODE {
1179MICRO_TILE_MODE_LINEAR = 0x00000000,
1180MICRO_TILE_MODE_ROTATED = 0x00000001,
1181MICRO_TILE_MODE_STD_2D = 0x00000002,
1182MICRO_TILE_MODE_STD_3D = 0x00000003,
1183MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
1184MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
1185MICRO_TILE_MODE_Z_2D = 0x00000006,
1186MICRO_TILE_MODE_Z_3D = 0x00000007,
1187} TC_MICRO_TILE_MODE;
1188
1189/*
1190 * SWIZZLE_MODE_ENUM enum
1191 */
1192
1193typedef enum SWIZZLE_MODE_ENUM {
1194SW_LINEAR = 0x00000000,
1195SW_256B_S = 0x00000001,
1196SW_256B_D = 0x00000002,
1197SW_256B_R = 0x00000003,
1198SW_4KB_Z = 0x00000004,
1199SW_4KB_S = 0x00000005,
1200SW_4KB_D = 0x00000006,
1201SW_4KB_R = 0x00000007,
1202SW_64KB_Z = 0x00000008,
1203SW_64KB_S = 0x00000009,
1204SW_64KB_D = 0x0000000a,
1205SW_64KB_R = 0x0000000b,
1206SW_VAR_Z = 0x0000000c,
1207SW_VAR_S = 0x0000000d,
1208SW_VAR_D = 0x0000000e,
1209SW_VAR_R = 0x0000000f,
1210SW_RESERVED_16 = 0x00000010,
1211SW_RESERVED_17 = 0x00000011,
1212SW_RESERVED_18 = 0x00000012,
1213SW_RESERVED_19 = 0x00000013,
1214SW_4KB_Z_X = 0x00000014,
1215SW_4KB_S_X = 0x00000015,
1216SW_4KB_D_X = 0x00000016,
1217SW_4KB_R_X = 0x00000017,
1218SW_64KB_Z_X = 0x00000018,
1219SW_64KB_S_X = 0x00000019,
1220SW_64KB_D_X = 0x0000001a,
1221SW_64KB_R_X = 0x0000001b,
1222SW_VAR_Z_X = 0x0000001c,
1223SW_VAR_S_X = 0x0000001d,
1224SW_VAR_D_X = 0x0000001e,
1225SW_VAR_R_X = 0x0000001f,
1226SW_RESERVED_12 = 0x00000020,
1227SW_RESERVED_13 = 0x00000021,
1228SW_RESERVED_14 = 0x00000022,
1229SW_RESERVED_15 = 0x00000023,
1230} SWIZZLE_MODE_ENUM;
1231
1232/*
1233 * PipeTiling enum
1234 */
1235
1236typedef enum PipeTiling {
1237CONFIG_1_PIPE = 0x00000000,
1238CONFIG_2_PIPE = 0x00000001,
1239CONFIG_4_PIPE = 0x00000002,
1240CONFIG_8_PIPE = 0x00000003,
1241} PipeTiling;
1242
1243/*
1244 * BankTiling enum
1245 */
1246
1247typedef enum BankTiling {
1248CONFIG_4_BANK = 0x00000000,
1249CONFIG_8_BANK = 0x00000001,
1250} BankTiling;
1251
1252/*
1253 * GroupInterleave enum
1254 */
1255
1256typedef enum GroupInterleave {
1257CONFIG_256B_GROUP = 0x00000000,
1258CONFIG_512B_GROUP = 0x00000001,
1259} GroupInterleave;
1260
1261/*
1262 * RowTiling enum
1263 */
1264
1265typedef enum RowTiling {
1266CONFIG_1KB_ROW = 0x00000000,
1267CONFIG_2KB_ROW = 0x00000001,
1268CONFIG_4KB_ROW = 0x00000002,
1269CONFIG_8KB_ROW = 0x00000003,
1270CONFIG_1KB_ROW_OPT = 0x00000004,
1271CONFIG_2KB_ROW_OPT = 0x00000005,
1272CONFIG_4KB_ROW_OPT = 0x00000006,
1273CONFIG_8KB_ROW_OPT = 0x00000007,
1274} RowTiling;
1275
1276/*
1277 * BankSwapBytes enum
1278 */
1279
1280typedef enum BankSwapBytes {
1281CONFIG_128B_SWAPS = 0x00000000,
1282CONFIG_256B_SWAPS = 0x00000001,
1283CONFIG_512B_SWAPS = 0x00000002,
1284CONFIG_1KB_SWAPS = 0x00000003,
1285} BankSwapBytes;
1286
1287/*
1288 * SampleSplitBytes enum
1289 */
1290
1291typedef enum SampleSplitBytes {
1292CONFIG_1KB_SPLIT = 0x00000000,
1293CONFIG_2KB_SPLIT = 0x00000001,
1294CONFIG_4KB_SPLIT = 0x00000002,
1295CONFIG_8KB_SPLIT = 0x00000003,
1296} SampleSplitBytes;
1297
1298/*******************************************************
1299 * AZSTREAM Enums
1300 *******************************************************/
1301
1302/*
1303 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1304 */
1305
1306typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1307OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
1308OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
1309} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1310
1311/*
1312 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1313 */
1314
1315typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1316OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
1317OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
1318} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1319
1320/*
1321 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1322 */
1323
1324typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1325OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
1326OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
1327} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1328
1329/*
1330 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1331 */
1332
1333typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1334OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
1335OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
1336} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1337
1338/*
1339 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1340 */
1341
1342typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1343OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
1344OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
1345} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1346
1347/*
1348 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1349 */
1350
1351typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1352OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
1353OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
1354} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1355
1356/*
1357 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1358 */
1359
1360typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1361OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
1362OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
1363} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1364
1365/*
1366 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1367 */
1368
1369typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1370OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
1371OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
1372} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1373
1374/*
1375 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1376 */
1377
1378typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1379OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
1380OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
1381} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1382
1383/*
1384 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1385 */
1386
1387typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1388OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
1389OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
1390} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1391
1392/*
1393 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1394 */
1395
1396typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1397OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
1398OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
1399OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
1400OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
1401OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
1402} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1403
1404/*
1405 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1406 */
1407
1408typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1409OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
1410OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
1411OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
1412OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
1413OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
1414OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
1415OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
1416OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
1417} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1418
1419/*
1420 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1421 */
1422
1423typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1424OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
1425OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
1426OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
1427OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
1428OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
1429OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
1430} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1431
1432/*
1433 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1434 */
1435
1436typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1437OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
1438OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
1439OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
1440OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
1441OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
1442OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
1443OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
1444OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
1445OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
1446OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
1447OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
1448OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
1449OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
1450OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
1451OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
1452OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
1453} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1454
1455/*******************************************************
1456 * BLNDV Enums
1457 *******************************************************/
1458
1459/*
1460 * BLNDV_CONTROL_BLND_MODE enum
1461 */
1462
1463typedef enum BLNDV_CONTROL_BLND_MODE {
1464BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1465BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY = 0x00000001,
1466BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1467BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1468} BLNDV_CONTROL_BLND_MODE;
1469
1470/*
1471 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1472 */
1473
1474typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1475BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1476BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1477BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1478BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED = 0x00000003,
1479} BLNDV_CONTROL_BLND_STEREO_TYPE;
1480
1481/*
1482 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1483 */
1484
1485typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1486BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW = 0x00000000,
1487BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH = 0x00000001,
1488} BLNDV_CONTROL_BLND_STEREO_POLARITY;
1489
1490/*
1491 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1492 */
1493
1494typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1495BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE = 0x00000000,
1496BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE = 0x00000001,
1497} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1498
1499/*
1500 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1501 */
1502
1503typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1504BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1505BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1506BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1507BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED = 0x00000003,
1508} BLNDV_CONTROL_BLND_ALPHA_MODE;
1509
1510/*
1511 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1512 */
1513
1514typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1515BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
1516BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
1517} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1518
1519/*
1520 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1521 */
1522
1523typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1524BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1525BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE = 0x00000001,
1526} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1527
1528/*
1529 * BLNDV_SM_CONTROL2_SM_MODE enum
1530 */
1531
1532typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1533BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE = 0x00000000,
1534BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1535BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1536BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1537} BLNDV_SM_CONTROL2_SM_MODE;
1538
1539/*
1540 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1541 */
1542
1543typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1544BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1545BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1546} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1547
1548/*
1549 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1550 */
1551
1552typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1553BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1554BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1555} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1556
1557/*
1558 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1559 */
1560
1561typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1562BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1563BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1564BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1565BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1566} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1567
1568/*
1569 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1570 */
1571
1572typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1573BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1574BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1575BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1576BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1577} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1578
1579/*
1580 * BLNDV_CONTROL2_PTI_ENABLE enum
1581 */
1582
1583typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1584BLNDV_CONTROL2_PTI_ENABLE_FALSE = 0x00000000,
1585BLNDV_CONTROL2_PTI_ENABLE_TRUE = 0x00000001,
1586} BLNDV_CONTROL2_PTI_ENABLE;
1587
1588/*
1589 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1590 */
1591
1592typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1593BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1594BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1595} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1596
1597/*
1598 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1599 */
1600
1601typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1602BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1603BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1604} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1605
1606/*
1607 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1608 */
1609
1610typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1611BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1612BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1613} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1614
1615/*
1616 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1617 */
1618
1619typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1620BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1621BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1622} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1623
1624/*
1625 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1626 */
1627
1628typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1629BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1630BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1631} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1632
1633/*
1634 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1635 */
1636
1637typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1638BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1639BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1640} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1641
1642/*
1643 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1644 */
1645
1646typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1647BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1648BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1649} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1650
1651/*
1652 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1653 */
1654
1655typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1656BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1657BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1658} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1659
1660/*
1661 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1662 */
1663
1664typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1665BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1666BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1667} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1668
1669/*
1670 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1671 */
1672
1673typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1674BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1675BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1676} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1677
1678/*
1679 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1680 */
1681
1682typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1683BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1684BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1685} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1686
1687/*
1688 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1689 */
1690
1691typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1692BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW = 0x00000000,
1693BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH = 0x00000001,
1694} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1695
1696/*
1697 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1698 */
1699
1700typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1701BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1702BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1703} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1704
1705/*******************************************************
1706 * LBV Enums
1707 *******************************************************/
1708
1709/*
1710 * LBV_PIXEL_DEPTH enum
1711 */
1712
1713typedef enum LBV_PIXEL_DEPTH {
1714PIXEL_DEPTH_30BPP = 0x00000000,
1715PIXEL_DEPTH_24BPP = 0x00000001,
1716PIXEL_DEPTH_18BPP = 0x00000002,
1717PIXEL_DEPTH_38BPP = 0x00000003,
1718} LBV_PIXEL_DEPTH;
1719
1720/*
1721 * LBV_PIXEL_EXPAN_MODE enum
1722 */
1723
1724typedef enum LBV_PIXEL_EXPAN_MODE {
1725PIXEL_EXPAN_MODE_ZERO_EXP = 0x00000000,
1726PIXEL_EXPAN_MODE_DYN_EXP = 0x00000001,
1727} LBV_PIXEL_EXPAN_MODE;
1728
1729/*
1730 * LBV_INTERLEAVE_EN enum
1731 */
1732
1733typedef enum LBV_INTERLEAVE_EN {
1734INTERLEAVE_DIS = 0x00000000,
1735INTERLEAVE_EN = 0x00000001,
1736} LBV_INTERLEAVE_EN;
1737
1738/*
1739 * LBV_PIXEL_REDUCE_MODE enum
1740 */
1741
1742typedef enum LBV_PIXEL_REDUCE_MODE {
1743PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
1744PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
1745} LBV_PIXEL_REDUCE_MODE;
1746
1747/*
1748 * LBV_DYNAMIC_PIXEL_DEPTH enum
1749 */
1750
1751typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1752DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
1753DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
1754} LBV_DYNAMIC_PIXEL_DEPTH;
1755
1756/*
1757 * LBV_DITHER_EN enum
1758 */
1759
1760typedef enum LBV_DITHER_EN {
1761DITHER_DIS = 0x00000000,
1762DITHER_EN = 0x00000001,
1763} LBV_DITHER_EN;
1764
1765/*
1766 * LBV_DOWNSCALE_PREFETCH_EN enum
1767 */
1768
1769typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1770DOWNSCALE_PREFETCH_DIS = 0x00000000,
1771DOWNSCALE_PREFETCH_EN = 0x00000001,
1772} LBV_DOWNSCALE_PREFETCH_EN;
1773
1774/*
1775 * LBV_MEMORY_CONFIG enum
1776 */
1777
1778typedef enum LBV_MEMORY_CONFIG {
1779MEMORY_CONFIG_0 = 0x00000000,
1780MEMORY_CONFIG_1 = 0x00000001,
1781MEMORY_CONFIG_2 = 0x00000002,
1782MEMORY_CONFIG_3 = 0x00000003,
1783} LBV_MEMORY_CONFIG;
1784
1785/*
1786 * LBV_SYNC_RESET_SEL2 enum
1787 */
1788
1789typedef enum LBV_SYNC_RESET_SEL2 {
1790SYNC_RESET_SEL2_VBLANK = 0x00000000,
1791SYNC_RESET_SEL2_VSYNC = 0x00000001,
1792} LBV_SYNC_RESET_SEL2;
1793
1794/*
1795 * LBV_SYNC_DURATION enum
1796 */
1797
1798typedef enum LBV_SYNC_DURATION {
1799SYNC_DURATION_16 = 0x00000000,
1800SYNC_DURATION_32 = 0x00000001,
1801SYNC_DURATION_64 = 0x00000002,
1802SYNC_DURATION_128 = 0x00000003,
1803} LBV_SYNC_DURATION;
1804
1805/*******************************************************
1806 * CRTC Enums
1807 *******************************************************/
1808
1809/*
1810 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1811 */
1812
1813typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1814CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1815CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x00000001,
1816} CRTC_CONTROL_CRTC_START_POINT_CNTL;
1817
1818/*
1819 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1820 */
1821
1822typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1823CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1824CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x00000001,
1825} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1826
1827/*
1828 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1829 */
1830
1831typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1832CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
1833CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
1834CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
1835CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
1836} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1837
1838/*
1839 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1840 */
1841
1842typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1843CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
1844CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
1845} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1846
1847/*
1848 * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1849 */
1850
1851typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1852CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
1853CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
1854} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1855
1856/*
1857 * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1858 */
1859
1860typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1861CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE = 0x00000000,
1862CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x00000001,
1863} CRTC_CONTROL_CRTC_SOF_PULL_EN;
1864
1865/*
1866 * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1867 */
1868
1869typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1870CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE = 0x00000000,
1871CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x00000001,
1872} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1873
1874/*
1875 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1876 */
1877
1878typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1879CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
1880CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
1881} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1882
1883/*
1884 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1885 */
1886
1887typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1888CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
1889CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
1890} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1891
1892/*
1893 * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1894 */
1895
1896typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1897CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
1898CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
1899} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1900
1901/*
1902 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1903 */
1904
1905typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1906CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1907CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
1908} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1909
1910/*
1911 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1912 */
1913
1914typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1915CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1916CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
1917} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1918
1919/*
1920 * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1921 */
1922
1923typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1924CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1925CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
1926} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1927
1928/*
1929 * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1930 */
1931
1932typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1933CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1934CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
1935} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1936
1937/*
1938 * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1939 */
1940
1941typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1942CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE = 0x00000000,
1943CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE = 0x00000001,
1944} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1945
1946/*
1947 * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1948 */
1949
1950typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1951CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE = 0x00000000,
1952CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE = 0x00000001,
1953} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1954
1955/*
1956 * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1957 */
1958
1959typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1960CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
1961CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
1962CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF = 0x00000005,
1963CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE = 0x00000006,
1964CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA = 0x00000007,
1965CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA = 0x00000008,
1966CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB = 0x00000009,
1967CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB = 0x0000000a,
1968CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
1969CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
1970CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD = 0x0000000d,
1971CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC = 0x0000000e,
1972CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0 = 0x00000010,
1973CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1 = 0x00000011,
1974CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2 = 0x00000012,
1975CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON = 0x00000013,
1976CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA = 0x00000014,
1977CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB = 0x00000015,
1978CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
1979CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
1980} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1981
1982/*
1983 * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1984 */
1985
1986typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1987CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
1988CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
1989CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
1990CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
1991CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB = 0x00000005,
1992CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x00000006,
1993CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC = 0x00000007,
1994} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1995
1996/*
1997 * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
1998 */
1999
2000typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2001CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2002CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2003} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2004
2005/*
2006 * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2007 */
2008
2009typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2010CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE = 0x00000000,
2011CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE = 0x00000001,
2012} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2013
2014/*
2015 * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2016 */
2017
2018typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2019CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER = 0x00000001,
2020CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER = 0x00000002,
2021CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF = 0x00000005,
2022CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE = 0x00000006,
2023CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA = 0x00000007,
2024CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA = 0x00000008,
2025CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB = 0x00000009,
2026CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB = 0x0000000a,
2027CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
2028CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
2029CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD = 0x0000000d,
2030CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC = 0x0000000e,
2031CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0 = 0x00000010,
2032CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1 = 0x00000011,
2033CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2 = 0x00000012,
2034CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON = 0x00000013,
2035CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA = 0x00000014,
2036CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB = 0x00000015,
2037CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW = 0x00000016,
2038CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW = 0x00000017,
2039} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2040
2041/*
2042 * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2043 */
2044
2045typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2046CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
2047CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
2048CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
2049CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
2050CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB = 0x00000005,
2051CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x00000006,
2052CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC = 0x00000007,
2053} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2054
2055/*
2056 * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2057 */
2058
2059typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2060CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
2061CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
2062} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2063
2064/*
2065 * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2066 */
2067
2068typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2069CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE = 0x00000000,
2070CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE = 0x00000001,
2071} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2072
2073/*
2074 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2075 */
2076
2077typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2078CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
2079CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
2080CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
2081CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
2082} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2083
2084/*
2085 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2086 */
2087
2088typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2089CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
2090CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
2091} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2092
2093/*
2094 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2095 */
2096
2097typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2098CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
2099CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
2100} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2101
2102/*
2103 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2104 */
2105
2106typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2107CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2108CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
2109} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2110
2111/*
2112 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2113 */
2114
2115typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2116CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
2117CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000001,
2118CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000002,
2119CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000003,
2120CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000004,
2121CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x00000005,
2122CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x00000006,
2123CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x00000007,
2124CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x00000008,
2125CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK = 0x00000009,
2126CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL = 0x0000000a,
2127CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x0000000b,
2128CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x0000000c,
2129CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x0000000d,
2130CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x0000000e,
2131CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x0000000f,
2132} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2133
2134/*
2135 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2136 */
2137
2138typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2139CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
2140CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
2141} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2142
2143/*
2144 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2145 */
2146
2147typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2148CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
2149CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
2150} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2151
2152/*
2153 * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2154 */
2155
2156typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2157CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
2158CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
2159CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
2160CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
2161} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2162
2163/*
2164 * CRTC_CONTROL_CRTC_MASTER_EN enum
2165 */
2166
2167typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2168CRTC_CONTROL_CRTC_MASTER_EN_FALSE = 0x00000000,
2169CRTC_CONTROL_CRTC_MASTER_EN_TRUE = 0x00000001,
2170} CRTC_CONTROL_CRTC_MASTER_EN;
2171
2172/*
2173 * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2174 */
2175
2176typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2177CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE = 0x00000000,
2178CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE = 0x00000001,
2179} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2180
2181/*
2182 * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2183 */
2184
2185typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2186CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE = 0x00000000,
2187CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE = 0x00000001,
2188} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2189
2190/*
2191 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2192 */
2193
2194typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2195CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE = 0x00000000,
2196CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE = 0x00000001,
2197} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2198
2199/*
2200 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2201 */
2202
2203typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2204CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
2205CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD = 0x00000001,
2206CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN = 0x00000002,
2207CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
2208} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2209
2210/*
2211 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2212 */
2213
2214typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2215CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
2216CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
2217} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2218
2219/*
2220 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2221 */
2222
2223typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2224CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE = 0x00000000,
2225CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE = 0x00000001,
2226} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2227
2228/*
2229 * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2230 */
2231
2232typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2233CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
2234CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
2235} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2236
2237/*
2238 * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2239 */
2240
2241typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2242CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2243CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
2244} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2245
2246/*
2247 * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2248 */
2249
2250typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2251CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2252CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
2253} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2254
2255/*
2256 * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2257 */
2258
2259typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2260CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
2261CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
2262CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
2263CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
2264} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2265
2266/*
2267 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2268 */
2269
2270typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2271CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
2272CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
2273} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2274
2275/*
2276 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2277 */
2278
2279typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2280CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE = 0x00000000,
2281CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE = 0x00000001,
2282} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2283
2284/*
2285 * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2286 */
2287
2288typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2289CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
2290CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
2291} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2292
2293/*
2294 * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2295 */
2296
2297typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2298CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE = 0x00000000,
2299CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE = 0x00000001,
2300} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2301
2302/*
2303 * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2304 */
2305
2306typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2307CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2308CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE = 0x00000001,
2309} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2310
2311/*
2312 * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2313 */
2314
2315typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2316CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
2317CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
2318CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
2319CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
2320} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2321
2322/*
2323 * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2324 */
2325
2326typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2327CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2328CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
2329} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2330
2331/*
2332 * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2333 */
2334
2335typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2336CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2337CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
2338} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2339
2340/*
2341 * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2342 */
2343
2344typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2345CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
2346CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
2347} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2348
2349/*
2350 * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2351 */
2352
2353typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2354CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE = 0x00000000,
2355CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE = 0x00000001,
2356} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2357
2358/*
2359 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2360 */
2361
2362typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2363CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
2364CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
2365} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2366
2367/*
2368 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2369 */
2370
2371typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2372CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
2373CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
2374} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2375
2376/*
2377 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2378 */
2379
2380typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2381CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE = 0x00000000,
2382CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE = 0x00000001,
2383} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2384
2385/*
2386 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2387 */
2388
2389typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2390CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
2391CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
2392} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2393
2394/*
2395 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2396 */
2397
2398typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2399CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
2400CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
2401} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2402
2403/*
2404 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2405 */
2406
2407typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2408CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
2409CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
2410} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2411
2412/*
2413 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2414 */
2415
2416typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2417CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
2418CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
2419} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2420
2421/*
2422 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2423 */
2424
2425typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2426CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
2427CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
2428} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2429
2430/*
2431 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2432 */
2433
2434typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2435CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE = 0x00000000,
2436CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE = 0x00000001,
2437} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2438
2439/*
2440 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2441 */
2442
2443typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2444CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x00000000,
2445CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE = 0x00000001,
2446} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2447
2448/*
2449 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2450 */
2451
2452typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2453CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE = 0x00000000,
2454CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE = 0x00000001,
2455} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2456
2457/*
2458 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2459 */
2460
2461typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2462CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x00000000,
2463CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE = 0x00000001,
2464} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2465
2466/*
2467 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2468 */
2469
2470typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2471CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
2472CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
2473} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2474
2475/*
2476 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2477 */
2478
2479typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2480CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
2481CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
2482} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2483
2484/*
2485 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2486 */
2487
2488typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2489CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
2490CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
2491} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2492
2493/*
2494 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2495 */
2496
2497typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2498CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
2499CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
2500} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2501
2502/*
2503 * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2504 */
2505
2506typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2507CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE = 0x00000000,
2508CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE = 0x00000001,
2509} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2510
2511/*
2512 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2513 */
2514
2515typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2516CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE = 0x00000000,
2517CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE = 0x00000001,
2518} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2519
2520/*
2521 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2522 */
2523
2524typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2525CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
2526CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
2527} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2528
2529/*
2530 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2531 */
2532
2533typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2534CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
2535CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
2536} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2537
2538/*
2539 * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2540 */
2541
2542typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2543CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
2544CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
2545} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2546
2547/*
2548 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2549 */
2550
2551typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2552CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE = 0x00000000,
2553CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE = 0x00000001,
2554} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2555
2556/*
2557 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2558 */
2559
2560typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2561CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB = 0x00000000,
2562CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601 = 0x00000001,
2563CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709 = 0x00000002,
2564CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS = 0x00000003,
2565CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS = 0x00000004,
2566CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB = 0x00000005,
2567CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB = 0x00000006,
2568CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS = 0x00000007,
2569} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2570
2571/*
2572 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2573 */
2574
2575typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2576CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE = 0x00000000,
2577CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE = 0x00000001,
2578} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2579
2580/*
2581 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2582 */
2583
2584typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2585CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC = 0x00000000,
2586CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC = 0x00000001,
2587CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC = 0x00000002,
2588CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED = 0x00000003,
2589} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2590
2591/*
2592 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2593 */
2594
2595typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2596MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2597MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2598} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2599
2600/*
2601 * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2602 */
2603
2604typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2605MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
2606MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
2607} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2608
2609/*
2610 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2611 */
2612
2613typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2614MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
2615MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
2616} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2617
2618/*
2619 * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2620 */
2621
2622typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2623MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN = 0x00000000,
2624MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA = 0x00000001,
2625MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA = 0x00000002,
2626MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE = 0x00000003,
2627} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2628
2629/*
2630 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2631 */
2632
2633typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2634MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
2635MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN = 0x00000001,
2636MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD = 0x00000002,
2637MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
2638} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2639
2640/*
2641 * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2642 */
2643
2644typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2645CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
2646CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
2647CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
2648} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2649
2650/*
2651 * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2652 */
2653
2654typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2655CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2656CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE = 0x00000001,
2657} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2658
2659/*
2660 * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2661 */
2662
2663typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2664CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2665CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
2666} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2667
2668/*
2669 * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2670 */
2671
2672typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2673CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2674CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
2675} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2676
2677/*
2678 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2679 */
2680
2681typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2682CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
2683CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
2684} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2685
2686/*
2687 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2688 */
2689
2690typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2691CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2692CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
2693} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2694
2695/*
2696 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2697 */
2698
2699typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2700CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2701CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
2702} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2703
2704/*
2705 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2706 */
2707
2708typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2709CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
2710CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
2711} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2712
2713/*
2714 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2715 */
2716
2717typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2718CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2719CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
2720} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2721
2722/*
2723 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2724 */
2725
2726typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2727CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2728CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
2729} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2730
2731/*
2732 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2733 */
2734
2735typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2736CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
2737CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
2738} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2739
2740/*
2741 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2742 */
2743
2744typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2745CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2746CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
2747} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2748
2749/*
2750 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2751 */
2752
2753typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2754CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2755CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
2756} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2757
2758/*
2759 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2760 */
2761
2762typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2763CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
2764CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
2765} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2766
2767/*
2768 * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2769 */
2770
2771typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2772CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE = 0x00000000,
2773CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE = 0x00000001,
2774} CRTC_CRC_CNTL_CRTC_CRC_EN;
2775
2776/*
2777 * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2778 */
2779
2780typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2781CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE = 0x00000000,
2782CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE = 0x00000001,
2783} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2784
2785/*
2786 * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2787 */
2788
2789typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2790CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT = 0x00000000,
2791CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2792CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
2793CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
2794} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2795
2796/*
2797 * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2798 */
2799
2800typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2801CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2802CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2803CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
2804CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
2805} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2806
2807/*
2808 * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2809 */
2810
2811typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2812CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2813CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
2814} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2815
2816/*
2817 * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2818 */
2819
2820typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2821CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB = 0x00000000,
2822CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B = 0x00000001,
2823CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB = 0x00000002,
2824CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B = 0x00000003,
2825CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB = 0x00000004,
2826CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B = 0x00000005,
2827CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB = 0x00000006,
2828CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B = 0x00000007,
2829} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2830
2831/*
2832 * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2833 */
2834
2835typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2836CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB = 0x00000000,
2837CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B = 0x00000001,
2838CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB = 0x00000002,
2839CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B = 0x00000003,
2840CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB = 0x00000004,
2841CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B = 0x00000005,
2842CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB = 0x00000006,
2843CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B = 0x00000007,
2844} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2845
2846/*
2847 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2848 */
2849
2850typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2851CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
2852CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
2853CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
2854CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
2855} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2856
2857/*
2858 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2859 */
2860
2861typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2862CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
2863CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
2864} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2865
2866/*
2867 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2868 */
2869
2870typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2871CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
2872CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
2873} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2874
2875/*
2876 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2877 */
2878
2879typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2880CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
2881CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
2882CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
2883CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
2884} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2885
2886/*
2887 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2888 */
2889
2890typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2891CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
2892CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
2893} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2894
2895/*
2896 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2897 */
2898
2899typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2900CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2901CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
2902} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2903
2904/*
2905 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2906 */
2907
2908typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2909CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
2910CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
2911} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2912
2913/*
2914 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2915 */
2916
2917typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2918CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
2919CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
2920} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2921
2922/*
2923 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2924 */
2925
2926typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2927CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
2928CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
2929} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2930
2931/*
2932 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2933 */
2934
2935typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2936CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
2937CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
2938} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2939
2940/*
2941 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2942 */
2943
2944typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2945CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2946CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
2947} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2948
2949/*
2950 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2951 */
2952
2953typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2954CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
2955CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
2956} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2957
2958/*
2959 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2960 */
2961
2962typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2963CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
2964CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
2965CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
2966CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
2967CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
2968CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
2969CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
2970CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
2971} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2972
2973/*
2974 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2975 */
2976
2977typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2978CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
2979CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
2980} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2981
2982/*
2983 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2984 */
2985
2986typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2987CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2988CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
2989} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2990
2991/*
2992 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2993 */
2994
2995typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2996CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
2997CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
2998} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
2999
3000/*
3001 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3002 */
3003
3004typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3005CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
3006CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
3007} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3008
3009/*
3010 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3011 */
3012
3013typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3014CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3015CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
3016} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3017
3018/*
3019 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3020 */
3021
3022typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3023CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
3024CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
3025} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3026
3027/*
3028 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3029 */
3030
3031typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3032CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
3033CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
3034} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3035
3036/*
3037 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3038 */
3039
3040typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3041CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3042CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
3043} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3044
3045/*
3046 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3047 */
3048
3049typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3050CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE = 0x00000000,
3051CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE = 0x00000001,
3052} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3053
3054/*
3055 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3056 */
3057
3058typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3059CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
3060CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
3061} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3062
3063/*
3064 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3065 */
3066
3067typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3068CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
3069CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
3070} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3071
3072/*
3073 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3074 */
3075
3076typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3077CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE = 0x00000000,
3078CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE = 0x00000001,
3079} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3080
3081/*
3082 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3083 */
3084
3085typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3086CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3087CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3088} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3089
3090/*
3091 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3092 */
3093
3094typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3095CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3096CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3097CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3098CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3099} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3100
3101/*
3102 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3103 */
3104
3105typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3106CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3107CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3108} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3109
3110/*
3111 * CRTC_V_SYNC_A_POL enum
3112 */
3113
3114typedef enum CRTC_V_SYNC_A_POL {
3115CRTC_V_SYNC_A_POL_HIGH = 0x00000000,
3116CRTC_V_SYNC_A_POL_LOW = 0x00000001,
3117} CRTC_V_SYNC_A_POL;
3118
3119/*
3120 * CRTC_H_SYNC_A_POL enum
3121 */
3122
3123typedef enum CRTC_H_SYNC_A_POL {
3124CRTC_H_SYNC_A_POL_HIGH = 0x00000000,
3125CRTC_H_SYNC_A_POL_LOW = 0x00000001,
3126} CRTC_H_SYNC_A_POL;
3127
3128/*
3129 * CRTC_HORZ_REPETITION_COUNT enum
3130 */
3131
3132typedef enum CRTC_HORZ_REPETITION_COUNT {
3133CRTC_HORZ_REPETITION_COUNT_0 = 0x00000000,
3134CRTC_HORZ_REPETITION_COUNT_1 = 0x00000001,
3135CRTC_HORZ_REPETITION_COUNT_2 = 0x00000002,
3136CRTC_HORZ_REPETITION_COUNT_3 = 0x00000003,
3137CRTC_HORZ_REPETITION_COUNT_4 = 0x00000004,
3138CRTC_HORZ_REPETITION_COUNT_5 = 0x00000005,
3139CRTC_HORZ_REPETITION_COUNT_6 = 0x00000006,
3140CRTC_HORZ_REPETITION_COUNT_7 = 0x00000007,
3141CRTC_HORZ_REPETITION_COUNT_8 = 0x00000008,
3142CRTC_HORZ_REPETITION_COUNT_9 = 0x00000009,
3143CRTC_HORZ_REPETITION_COUNT_10 = 0x0000000a,
3144CRTC_HORZ_REPETITION_COUNT_11 = 0x0000000b,
3145CRTC_HORZ_REPETITION_COUNT_12 = 0x0000000c,
3146CRTC_HORZ_REPETITION_COUNT_13 = 0x0000000d,
3147CRTC_HORZ_REPETITION_COUNT_14 = 0x0000000e,
3148CRTC_HORZ_REPETITION_COUNT_15 = 0x0000000f,
3149} CRTC_HORZ_REPETITION_COUNT;
3150
3151/*
3152 * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3153 */
3154
3155typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3156CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE = 0x00000000,
3157CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL = 0x00000001,
3158CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF = 0x00000002,
3159CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF = 0x00000003,
3160} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3161
3162/*******************************************************
3163 * FMT Enums
3164 *******************************************************/
3165
3166/*
3167 * FMT_CONTROL_PIXEL_ENCODING enum
3168 */
3169
3170typedef enum FMT_CONTROL_PIXEL_ENCODING {
3171FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3172FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3173FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3174FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3175} FMT_CONTROL_PIXEL_ENCODING;
3176
3177/*
3178 * FMT_CONTROL_SUBSAMPLING_MODE enum
3179 */
3180
3181typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3182FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3183FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3184FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3185FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3186} FMT_CONTROL_SUBSAMPLING_MODE;
3187
3188/*
3189 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3190 */
3191
3192typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3193FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3194FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3195} FMT_CONTROL_SUBSAMPLING_ORDER;
3196
3197/*
3198 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3199 */
3200
3201typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3202FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3203FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3204} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3205
3206/*
3207 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3208 */
3209
3210typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3211FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3212FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3213} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3214
3215/*
3216 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3217 */
3218
3219typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3220FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3221FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3222FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3223} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3224
3225/*
3226 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3227 */
3228
3229typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3230FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3231FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3232FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3233} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3234
3235/*
3236 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3237 */
3238
3239typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3240FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3241FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3242FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3243} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3244
3245/*
3246 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3247 */
3248
3249typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3250FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3251FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3252} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3253
3254/*
3255 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3256 */
3257
3258typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3259FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3260FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3261FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3262FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3263} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3264
3265/*
3266 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3267 */
3268
3269typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3270FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3271FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3272FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3273FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3274} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3275
3276/*
3277 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3278 */
3279
3280typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3281FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3282FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3283FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3284FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3285} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3286
3287/*
3288 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3289 */
3290
3291typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3292FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN = 0x00000000,
3293FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN = 0x00000001,
3294} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3295
3296/*
3297 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3298 */
3299
3300typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3301FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3302FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3303} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3304
3305/*
3306 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3307 */
3308
3309typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3310FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3311FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3312FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3313FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3314FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3315FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3316FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3317FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3318} FMT_CLAMP_CNTL_COLOR_FORMAT;
3319
3320/*
3321 * FMT_CRC_CNTL_CONT_EN enum
3322 */
3323
3324typedef enum FMT_CRC_CNTL_CONT_EN {
3325FMT_CRC_CNTL_CONT_EN_ONE_SHOT = 0x00000000,
3326FMT_CRC_CNTL_CONT_EN_CONT = 0x00000001,
3327} FMT_CRC_CNTL_CONT_EN;
3328
3329/*
3330 * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3331 */
3332
3333typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3334FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE = 0x00000000,
3335FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE = 0x00000001,
3336} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3337
3338/*
3339 * FMT_CRC_CNTL_ONLY_BLANKB enum
3340 */
3341
3342typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3343FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD = 0x00000000,
3344FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK = 0x00000001,
3345} FMT_CRC_CNTL_ONLY_BLANKB;
3346
3347/*
3348 * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3349 */
3350
3351typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3352FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL = 0x00000000,
3353FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC = 0x00000001,
3354} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3355
3356/*
3357 * FMT_CRC_CNTL_INTERLACE_MODE enum
3358 */
3359
3360typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3361FMT_CRC_CNTL_INTERLACE_MODE_TOP = 0x00000000,
3362FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM = 0x00000001,
3363FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
3364FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH = 0x00000003,
3365} FMT_CRC_CNTL_INTERLACE_MODE;
3366
3367/*
3368 * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3369 */
3370
3371typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3372FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL = 0x00000000,
3373FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN = 0x00000001,
3374} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3375
3376/*
3377 * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3378 */
3379
3380typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3381FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN = 0x00000000,
3382FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD = 0x00000001,
3383} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3384
3385/*
3386 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3387 */
3388
3389typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3390FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3391FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3392FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3393FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3394} FMT_DEBUG_CNTL_COLOR_SELECT;
3395
3396/*
3397 * FMT_SPATIAL_DITHER_MODE enum
3398 */
3399
3400typedef enum FMT_SPATIAL_DITHER_MODE {
3401FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3402FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3403FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3404FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3405} FMT_SPATIAL_DITHER_MODE;
3406
3407/*
3408 * FMT_STEREOSYNC_OVR_POL enum
3409 */
3410
3411typedef enum FMT_STEREOSYNC_OVR_POL {
3412FMT_STEREOSYNC_OVR_POL_INVERTED = 0x00000000,
3413FMT_STEREOSYNC_OVR_POL_NOT_INVERTED = 0x00000001,
3414} FMT_STEREOSYNC_OVR_POL;
3415
3416/*
3417 * FMT_DYNAMIC_EXP_MODE enum
3418 */
3419
3420typedef enum FMT_DYNAMIC_EXP_MODE {
3421FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3422FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3423} FMT_DYNAMIC_EXP_MODE;
3424
3425/*******************************************************
3426 * HPD Enums
3427 *******************************************************/
3428
3429/*
3430 * HPD_INT_CONTROL_ACK enum
3431 */
3432
3433typedef enum HPD_INT_CONTROL_ACK {
3434HPD_INT_CONTROL_ACK_0 = 0x00000000,
3435HPD_INT_CONTROL_ACK_1 = 0x00000001,
3436} HPD_INT_CONTROL_ACK;
3437
3438/*
3439 * HPD_INT_CONTROL_POLARITY enum
3440 */
3441
3442typedef enum HPD_INT_CONTROL_POLARITY {
3443HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
3444HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
3445} HPD_INT_CONTROL_POLARITY;
3446
3447/*
3448 * HPD_INT_CONTROL_RX_INT_ACK enum
3449 */
3450
3451typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3452HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
3453HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
3454} HPD_INT_CONTROL_RX_INT_ACK;
3455
3456/*******************************************************
3457 * LB Enums
3458 *******************************************************/
3459
3460/*
3461 * LB_DATA_FORMAT_PIXEL_DEPTH enum
3462 */
3463
3464typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3465LB_DATA_FORMAT_PIXEL_DEPTH_30BPP = 0x00000000,
3466LB_DATA_FORMAT_PIXEL_DEPTH_24BPP = 0x00000001,
3467LB_DATA_FORMAT_PIXEL_DEPTH_18BPP = 0x00000002,
3468LB_DATA_FORMAT_PIXEL_DEPTH_36BPP = 0x00000003,
3469} LB_DATA_FORMAT_PIXEL_DEPTH;
3470
3471/*
3472 * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3473 */
3474
3475typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3476LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3477LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3478} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3479
3480/*
3481 * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3482 */
3483
3484typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3485LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3486LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3487} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3488
3489/*
3490 * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3491 */
3492
3493typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3494LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3495LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3496} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3497
3498/*
3499 * LB_DATA_FORMAT_INTERLEAVE_EN enum
3500 */
3501
3502typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3503LB_DATA_FORMAT_INTERLEAVE_DISABLE = 0x00000000,
3504LB_DATA_FORMAT_INTERLEAVE_ENABLE = 0x00000001,
3505} LB_DATA_FORMAT_INTERLEAVE_EN;
3506
3507/*
3508 * LB_DATA_FORMAT_REQUEST_MODE enum
3509 */
3510
3511typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3512LB_DATA_FORMAT_REQUEST_MODE_NORMAL = 0x00000000,
3513LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE = 0x00000001,
3514} LB_DATA_FORMAT_REQUEST_MODE;
3515
3516/*
3517 * LB_DATA_FORMAT_ALPHA_EN enum
3518 */
3519
3520typedef enum LB_DATA_FORMAT_ALPHA_EN {
3521LB_DATA_FORMAT_ALPHA_DISABLE = 0x00000000,
3522LB_DATA_FORMAT_ALPHA_ENABLE = 0x00000001,
3523} LB_DATA_FORMAT_ALPHA_EN;
3524
3525/*
3526 * LB_VLINE_START_END_VLINE_INV enum
3527 */
3528
3529typedef enum LB_VLINE_START_END_VLINE_INV {
3530LB_VLINE_START_END_VLINE_NORMAL = 0x00000000,
3531LB_VLINE_START_END_VLINE_INVERSE = 0x00000001,
3532} LB_VLINE_START_END_VLINE_INV;
3533
3534/*
3535 * LB_VLINE2_START_END_VLINE2_INV enum
3536 */
3537
3538typedef enum LB_VLINE2_START_END_VLINE2_INV {
3539LB_VLINE2_START_END_VLINE2_NORMAL = 0x00000000,
3540LB_VLINE2_START_END_VLINE2_INVERSE = 0x00000001,
3541} LB_VLINE2_START_END_VLINE2_INV;
3542
3543/*
3544 * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3545 */
3546
3547typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3548LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3549LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3550} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3551
3552/*
3553 * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3554 */
3555
3556typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3557LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3558LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3559} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3560
3561/*
3562 * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3563 */
3564
3565typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3566LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3567LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3568} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3569
3570/*
3571 * LB_VLINE_STATUS_VLINE_ACK enum
3572 */
3573
3574typedef enum LB_VLINE_STATUS_VLINE_ACK {
3575LB_VLINE_STATUS_VLINE_NORMAL = 0x00000000,
3576LB_VLINE_STATUS_VLINE_CLEAR = 0x00000001,
3577} LB_VLINE_STATUS_VLINE_ACK;
3578
3579/*
3580 * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3581 */
3582
3583typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3584LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3585LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3586} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3587
3588/*
3589 * LB_VLINE2_STATUS_VLINE2_ACK enum
3590 */
3591
3592typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3593LB_VLINE2_STATUS_VLINE2_NORMAL = 0x00000000,
3594LB_VLINE2_STATUS_VLINE2_CLEAR = 0x00000001,
3595} LB_VLINE2_STATUS_VLINE2_ACK;
3596
3597/*
3598 * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3599 */
3600
3601typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3602LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3603LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3604} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3605
3606/*
3607 * LB_VBLANK_STATUS_VBLANK_ACK enum
3608 */
3609
3610typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3611LB_VBLANK_STATUS_VBLANK_NORMAL = 0x00000000,
3612LB_VBLANK_STATUS_VBLANK_CLEAR = 0x00000001,
3613} LB_VBLANK_STATUS_VBLANK_ACK;
3614
3615/*
3616 * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3617 */
3618
3619typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3620LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
3621LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
3622} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3623
3624/*
3625 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3626 */
3627
3628typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3629LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE = 0x00000000,
3630LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK = 0x00000001,
3631LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET = 0x00000002,
3632LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET = 0x00000003,
3633} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3634
3635/*
3636 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3637 */
3638
3639typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3640LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK = 0x00000000,
3641LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC = 0x00000001,
3642} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3643
3644/*
3645 * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3646 */
3647
3648typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3649LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3650LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3651LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3652LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3653} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3654
3655/*
3656 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3657 */
3658
3659typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3660LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3661LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3662} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3663
3664/*
3665 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3666 */
3667
3668typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3669LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3670LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3671} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3672
3673/*
3674 * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3675 */
3676
3677typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3678LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL = 0x00000000,
3679LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET = 0x00000001,
3680} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3681
3682/*
3683 * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3684 */
3685
3686typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3687LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL = 0x00000000,
3688LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET = 0x00000001,
3689} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3690
3691/*
3692 * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3693 */
3694
3695typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3696LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x00000002,
3697LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP = 0x00000003,
3698} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3699
3700/*
3701 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3702 */
3703
3704typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3705LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3706LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE = 0x00000001,
3707} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3708
3709/*
3710 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3711 */
3712
3713typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3714LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3715LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3716} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3717
3718/*
3719 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3720 */
3721
3722typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3723LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT = 0x00000000,
3724LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG = 0x00000001,
3725LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE = 0x00000002,
3726} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3727
3728/*
3729 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3730 */
3731
3732typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3733LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE = 0x00000000,
3734LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN = 0x00000001,
3735} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3736
3737/*
3738 * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3739 */
3740
3741typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3742ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER = 0x00000001,
3743ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE = 0x00000002,
3744} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3745
3746/*
3747 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3748 */
3749
3750typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3751LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3752LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3753} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3754
3755/*
3756 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3757 */
3758
3759typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3760LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3761LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE = 0x00000001,
3762} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3763
3764/*
3765 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3766 */
3767
3768typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3769LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3770LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO = 0x00000001,
3771} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3772
3773/*
3774 * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3775 */
3776
3777typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3778LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3779LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3780} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3781
3782/*******************************************************
3783 * DIG Enums
3784 *******************************************************/
3785
3786/*
3787 * HDMI_KEEPOUT_MODE enum
3788 */
3789
3790typedef enum HDMI_KEEPOUT_MODE {
3791HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
3792HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
3793} HDMI_KEEPOUT_MODE;
3794
3795/*
3796 * HDMI_DATA_SCRAMBLE_EN enum
3797 */
3798
3799typedef enum HDMI_DATA_SCRAMBLE_EN {
3800HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
3801HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
3802} HDMI_DATA_SCRAMBLE_EN;
3803
3804/*
3805 * HDMI_CLOCK_CHANNEL_RATE enum
3806 */
3807
3808typedef enum HDMI_CLOCK_CHANNEL_RATE {
3809HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
3810HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
3811} HDMI_CLOCK_CHANNEL_RATE;
3812
3813/*
3814 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3815 */
3816
3817typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3818HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
3819HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
3820} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3821
3822/*
3823 * HDMI_PACKET_GEN_VERSION enum
3824 */
3825
3826typedef enum HDMI_PACKET_GEN_VERSION {
3827HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
3828HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
3829} HDMI_PACKET_GEN_VERSION;
3830
3831/*
3832 * HDMI_ERROR_ACK enum
3833 */
3834
3835typedef enum HDMI_ERROR_ACK {
3836HDMI_ERROR_ACK_INT = 0x00000000,
3837HDMI_ERROR_NOT_ACK = 0x00000001,
3838} HDMI_ERROR_ACK;
3839
3840/*
3841 * HDMI_ERROR_MASK enum
3842 */
3843
3844typedef enum HDMI_ERROR_MASK {
3845HDMI_ERROR_MASK_INT = 0x00000000,
3846HDMI_ERROR_NOT_MASK = 0x00000001,
3847} HDMI_ERROR_MASK;
3848
3849/*
3850 * HDMI_DEEP_COLOR_DEPTH enum
3851 */
3852
3853typedef enum HDMI_DEEP_COLOR_DEPTH {
3854HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
3855HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
3856HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
3857HDMI_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
3858} HDMI_DEEP_COLOR_DEPTH;
3859
3860/*
3861 * HDMI_AUDIO_DELAY_EN enum
3862 */
3863
3864typedef enum HDMI_AUDIO_DELAY_EN {
3865HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
3866HDMI_AUDIO_DELAY_58CLK = 0x00000001,
3867HDMI_AUDIO_DELAY_56CLK = 0x00000002,
3868HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
3869} HDMI_AUDIO_DELAY_EN;
3870
3871/*
3872 * HDMI_AUDIO_SEND_MAX_PACKETS enum
3873 */
3874
3875typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3876HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
3877HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
3878} HDMI_AUDIO_SEND_MAX_PACKETS;
3879
3880/*
3881 * HDMI_ACR_SEND enum
3882 */
3883
3884typedef enum HDMI_ACR_SEND {
3885HDMI_ACR_NOT_SEND = 0x00000000,
3886HDMI_ACR_PKT_SEND = 0x00000001,
3887} HDMI_ACR_SEND;
3888
3889/*
3890 * HDMI_ACR_CONT enum
3891 */
3892
3893typedef enum HDMI_ACR_CONT {
3894HDMI_ACR_CONT_DISABLE = 0x00000000,
3895HDMI_ACR_CONT_ENABLE = 0x00000001,
3896} HDMI_ACR_CONT;
3897
3898/*
3899 * HDMI_ACR_SELECT enum
3900 */
3901
3902typedef enum HDMI_ACR_SELECT {
3903HDMI_ACR_SELECT_HW = 0x00000000,
3904HDMI_ACR_SELECT_32K = 0x00000001,
3905HDMI_ACR_SELECT_44K = 0x00000002,
3906HDMI_ACR_SELECT_48K = 0x00000003,
3907} HDMI_ACR_SELECT;
3908
3909/*
3910 * HDMI_ACR_SOURCE enum
3911 */
3912
3913typedef enum HDMI_ACR_SOURCE {
3914HDMI_ACR_SOURCE_HW = 0x00000000,
3915HDMI_ACR_SOURCE_SW = 0x00000001,
3916} HDMI_ACR_SOURCE;
3917
3918/*
3919 * HDMI_ACR_N_MULTIPLE enum
3920 */
3921
3922typedef enum HDMI_ACR_N_MULTIPLE {
3923HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
3924HDMI_ACR_1_MULTIPLE = 0x00000001,
3925HDMI_ACR_2_MULTIPLE = 0x00000002,
3926HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
3927HDMI_ACR_4_MULTIPLE = 0x00000004,
3928HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
3929HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
3930HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
3931} HDMI_ACR_N_MULTIPLE;
3932
3933/*
3934 * HDMI_ACR_AUDIO_PRIORITY enum
3935 */
3936
3937typedef enum HDMI_ACR_AUDIO_PRIORITY {
3938HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
3939HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
3940} HDMI_ACR_AUDIO_PRIORITY;
3941
3942/*
3943 * HDMI_NULL_SEND enum
3944 */
3945
3946typedef enum HDMI_NULL_SEND {
3947HDMI_NULL_NOT_SEND = 0x00000000,
3948HDMI_NULL_PKT_SEND = 0x00000001,
3949} HDMI_NULL_SEND;
3950
3951/*
3952 * HDMI_GC_SEND enum
3953 */
3954
3955typedef enum HDMI_GC_SEND {
3956HDMI_GC_NOT_SEND = 0x00000000,
3957HDMI_GC_PKT_SEND = 0x00000001,
3958} HDMI_GC_SEND;
3959
3960/*
3961 * HDMI_GC_CONT enum
3962 */
3963
3964typedef enum HDMI_GC_CONT {
3965HDMI_GC_CONT_DISABLE = 0x00000000,
3966HDMI_GC_CONT_ENABLE = 0x00000001,
3967} HDMI_GC_CONT;
3968
3969/*
3970 * HDMI_ISRC_SEND enum
3971 */
3972
3973typedef enum HDMI_ISRC_SEND {
3974HDMI_ISRC_NOT_SEND = 0x00000000,
3975HDMI_ISRC_PKT_SEND = 0x00000001,
3976} HDMI_ISRC_SEND;
3977
3978/*
3979 * HDMI_ISRC_CONT enum
3980 */
3981
3982typedef enum HDMI_ISRC_CONT {
3983HDMI_ISRC_CONT_DISABLE = 0x00000000,
3984HDMI_ISRC_CONT_ENABLE = 0x00000001,
3985} HDMI_ISRC_CONT;
3986
3987/*
3988 * HDMI_AVI_INFO_SEND enum
3989 */
3990
3991typedef enum HDMI_AVI_INFO_SEND {
3992HDMI_AVI_INFO_NOT_SEND = 0x00000000,
3993HDMI_AVI_INFO_PKT_SEND = 0x00000001,
3994} HDMI_AVI_INFO_SEND;
3995
3996/*
3997 * HDMI_AVI_INFO_CONT enum
3998 */
3999
4000typedef enum HDMI_AVI_INFO_CONT {
4001HDMI_AVI_INFO_CONT_DISABLE = 0x00000000,
4002HDMI_AVI_INFO_CONT_ENABLE = 0x00000001,
4003} HDMI_AVI_INFO_CONT;
4004
4005/*
4006 * HDMI_AUDIO_INFO_SEND enum
4007 */
4008
4009typedef enum HDMI_AUDIO_INFO_SEND {
4010HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
4011HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
4012} HDMI_AUDIO_INFO_SEND;
4013
4014/*
4015 * HDMI_AUDIO_INFO_CONT enum
4016 */
4017
4018typedef enum HDMI_AUDIO_INFO_CONT {
4019HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
4020HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
4021} HDMI_AUDIO_INFO_CONT;
4022
4023/*
4024 * HDMI_MPEG_INFO_SEND enum
4025 */
4026
4027typedef enum HDMI_MPEG_INFO_SEND {
4028HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
4029HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
4030} HDMI_MPEG_INFO_SEND;
4031
4032/*
4033 * HDMI_MPEG_INFO_CONT enum
4034 */
4035
4036typedef enum HDMI_MPEG_INFO_CONT {
4037HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
4038HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
4039} HDMI_MPEG_INFO_CONT;
4040
4041/*
4042 * HDMI_GENERIC0_SEND enum
4043 */
4044
4045typedef enum HDMI_GENERIC0_SEND {
4046HDMI_GENERIC0_NOT_SEND = 0x00000000,
4047HDMI_GENERIC0_PKT_SEND = 0x00000001,
4048} HDMI_GENERIC0_SEND;
4049
4050/*
4051 * HDMI_GENERIC0_CONT enum
4052 */
4053
4054typedef enum HDMI_GENERIC0_CONT {
4055HDMI_GENERIC0_CONT_DISABLE = 0x00000000,
4056HDMI_GENERIC0_CONT_ENABLE = 0x00000001,
4057} HDMI_GENERIC0_CONT;
4058
4059/*
4060 * HDMI_GENERIC1_SEND enum
4061 */
4062
4063typedef enum HDMI_GENERIC1_SEND {
4064HDMI_GENERIC1_NOT_SEND = 0x00000000,
4065HDMI_GENERIC1_PKT_SEND = 0x00000001,
4066} HDMI_GENERIC1_SEND;
4067
4068/*
4069 * HDMI_GENERIC1_CONT enum
4070 */
4071
4072typedef enum HDMI_GENERIC1_CONT {
4073HDMI_GENERIC1_CONT_DISABLE = 0x00000000,
4074HDMI_GENERIC1_CONT_ENABLE = 0x00000001,
4075} HDMI_GENERIC1_CONT;
4076
4077/*
4078 * HDMI_GC_AVMUTE_CONT enum
4079 */
4080
4081typedef enum HDMI_GC_AVMUTE_CONT {
4082HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
4083HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
4084} HDMI_GC_AVMUTE_CONT;
4085
4086/*
4087 * HDMI_PACKING_PHASE_OVERRIDE enum
4088 */
4089
4090typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4091HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
4092HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
4093} HDMI_PACKING_PHASE_OVERRIDE;
4094
4095/*
4096 * HDMI_GENERIC2_SEND enum
4097 */
4098
4099typedef enum HDMI_GENERIC2_SEND {
4100HDMI_GENERIC2_NOT_SEND = 0x00000000,
4101HDMI_GENERIC2_PKT_SEND = 0x00000001,
4102} HDMI_GENERIC2_SEND;
4103
4104/*
4105 * HDMI_GENERIC2_CONT enum
4106 */
4107
4108typedef enum HDMI_GENERIC2_CONT {
4109HDMI_GENERIC2_CONT_DISABLE = 0x00000000,
4110HDMI_GENERIC2_CONT_ENABLE = 0x00000001,
4111} HDMI_GENERIC2_CONT;
4112
4113/*
4114 * HDMI_GENERIC3_SEND enum
4115 */
4116
4117typedef enum HDMI_GENERIC3_SEND {
4118HDMI_GENERIC3_NOT_SEND = 0x00000000,
4119HDMI_GENERIC3_PKT_SEND = 0x00000001,
4120} HDMI_GENERIC3_SEND;
4121
4122/*
4123 * HDMI_GENERIC3_CONT enum
4124 */
4125
4126typedef enum HDMI_GENERIC3_CONT {
4127HDMI_GENERIC3_CONT_DISABLE = 0x00000000,
4128HDMI_GENERIC3_CONT_ENABLE = 0x00000001,
4129} HDMI_GENERIC3_CONT;
4130
4131/*
4132 * TMDS_PIXEL_ENCODING enum
4133 */
4134
4135typedef enum TMDS_PIXEL_ENCODING {
4136TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
4137TMDS_PIXEL_ENCODING_422 = 0x00000001,
4138} TMDS_PIXEL_ENCODING;
4139
4140/*
4141 * TMDS_COLOR_FORMAT enum
4142 */
4143
4144typedef enum TMDS_COLOR_FORMAT {
4145TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
4146TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
4147TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
4148TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
4149} TMDS_COLOR_FORMAT;
4150
4151/*
4152 * TMDS_STEREOSYNC_CTL_SEL_REG enum
4153 */
4154
4155typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4156TMDS_STEREOSYNC_CTL0 = 0x00000000,
4157TMDS_STEREOSYNC_CTL1 = 0x00000001,
4158TMDS_STEREOSYNC_CTL2 = 0x00000002,
4159TMDS_STEREOSYNC_CTL3 = 0x00000003,
4160} TMDS_STEREOSYNC_CTL_SEL_REG;
4161
4162/*
4163 * TMDS_CTL0_DATA_SEL enum
4164 */
4165
4166typedef enum TMDS_CTL0_DATA_SEL {
4167TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
4168TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4169TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
4170TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
4171TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
4172TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4173TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
4174TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
4175} TMDS_CTL0_DATA_SEL;
4176
4177/*
4178 * TMDS_CTL0_DATA_INVERT enum
4179 */
4180
4181typedef enum TMDS_CTL0_DATA_INVERT {
4182TMDS_CTL0_DATA_NORMAL = 0x00000000,
4183TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
4184} TMDS_CTL0_DATA_INVERT;
4185
4186/*
4187 * TMDS_CTL0_DATA_MODULATION enum
4188 */
4189
4190typedef enum TMDS_CTL0_DATA_MODULATION {
4191TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
4192TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
4193TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
4194TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
4195} TMDS_CTL0_DATA_MODULATION;
4196
4197/*
4198 * TMDS_CTL0_PATTERN_OUT_EN enum
4199 */
4200
4201typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4202TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
4203TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
4204} TMDS_CTL0_PATTERN_OUT_EN;
4205
4206/*
4207 * TMDS_CTL1_DATA_SEL enum
4208 */
4209
4210typedef enum TMDS_CTL1_DATA_SEL {
4211TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
4212TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4213TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
4214TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
4215TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
4216TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4217TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
4218TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4219} TMDS_CTL1_DATA_SEL;
4220
4221/*
4222 * TMDS_CTL1_DATA_INVERT enum
4223 */
4224
4225typedef enum TMDS_CTL1_DATA_INVERT {
4226TMDS_CTL1_DATA_NORMAL = 0x00000000,
4227TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
4228} TMDS_CTL1_DATA_INVERT;
4229
4230/*
4231 * TMDS_CTL1_DATA_MODULATION enum
4232 */
4233
4234typedef enum TMDS_CTL1_DATA_MODULATION {
4235TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
4236TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
4237TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
4238TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
4239} TMDS_CTL1_DATA_MODULATION;
4240
4241/*
4242 * TMDS_CTL1_PATTERN_OUT_EN enum
4243 */
4244
4245typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4246TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
4247TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
4248} TMDS_CTL1_PATTERN_OUT_EN;
4249
4250/*
4251 * TMDS_CTL2_DATA_SEL enum
4252 */
4253
4254typedef enum TMDS_CTL2_DATA_SEL {
4255TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
4256TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4257TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
4258TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
4259TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
4260TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4261TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
4262TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4263} TMDS_CTL2_DATA_SEL;
4264
4265/*
4266 * TMDS_CTL2_DATA_INVERT enum
4267 */
4268
4269typedef enum TMDS_CTL2_DATA_INVERT {
4270TMDS_CTL2_DATA_NORMAL = 0x00000000,
4271TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
4272} TMDS_CTL2_DATA_INVERT;
4273
4274/*
4275 * TMDS_CTL2_DATA_MODULATION enum
4276 */
4277
4278typedef enum TMDS_CTL2_DATA_MODULATION {
4279TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
4280TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
4281TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
4282TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
4283} TMDS_CTL2_DATA_MODULATION;
4284
4285/*
4286 * TMDS_CTL2_PATTERN_OUT_EN enum
4287 */
4288
4289typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4290TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
4291TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
4292} TMDS_CTL2_PATTERN_OUT_EN;
4293
4294/*
4295 * TMDS_CTL3_DATA_INVERT enum
4296 */
4297
4298typedef enum TMDS_CTL3_DATA_INVERT {
4299TMDS_CTL3_DATA_NORMAL = 0x00000000,
4300TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
4301} TMDS_CTL3_DATA_INVERT;
4302
4303/*
4304 * TMDS_CTL3_DATA_MODULATION enum
4305 */
4306
4307typedef enum TMDS_CTL3_DATA_MODULATION {
4308TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
4309TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
4310TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
4311TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
4312} TMDS_CTL3_DATA_MODULATION;
4313
4314/*
4315 * TMDS_CTL3_PATTERN_OUT_EN enum
4316 */
4317
4318typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4319TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
4320TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
4321} TMDS_CTL3_PATTERN_OUT_EN;
4322
4323/*
4324 * TMDS_CTL3_DATA_SEL enum
4325 */
4326
4327typedef enum TMDS_CTL3_DATA_SEL {
4328TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
4329TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
4330TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
4331TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
4332TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
4333TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
4334TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
4335TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
4336} TMDS_CTL3_DATA_SEL;
4337
4338/*
4339 * DIG_FE_CNTL_SOURCE_SELECT enum
4340 */
4341
4342typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4343DIG_FE_SOURCE_FROM_FMT0 = 0x00000000,
4344DIG_FE_SOURCE_FROM_FMT1 = 0x00000001,
4345DIG_FE_SOURCE_FROM_FMT2 = 0x00000002,
4346DIG_FE_SOURCE_FROM_FMT3 = 0x00000003,
4347DIG_FE_SOURCE_FROM_FMT4 = 0x00000004,
4348DIG_FE_SOURCE_FROM_FMT5 = 0x00000005,
4349} DIG_FE_CNTL_SOURCE_SELECT;
4350
4351/*
4352 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4353 */
4354
4355typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4356DIG_FE_STEREOSYNC_FROM_FMT0 = 0x00000000,
4357DIG_FE_STEREOSYNC_FROM_FMT1 = 0x00000001,
4358DIG_FE_STEREOSYNC_FROM_FMT2 = 0x00000002,
4359DIG_FE_STEREOSYNC_FROM_FMT3 = 0x00000003,
4360DIG_FE_STEREOSYNC_FROM_FMT4 = 0x00000004,
4361DIG_FE_STEREOSYNC_FROM_FMT5 = 0x00000005,
4362} DIG_FE_CNTL_STEREOSYNC_SELECT;
4363
4364/*
4365 * DIG_FIFO_READ_CLOCK_SRC enum
4366 */
4367
4368typedef enum DIG_FIFO_READ_CLOCK_SRC {
4369DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
4370DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
4371} DIG_FIFO_READ_CLOCK_SRC;
4372
4373/*
4374 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4375 */
4376
4377typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4378DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
4379DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
4380} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4381
4382/*
4383 * DIG_OUTPUT_CRC_DATA_SEL enum
4384 */
4385
4386typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4387DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
4388DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
4389DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
4390DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
4391} DIG_OUTPUT_CRC_DATA_SEL;
4392
4393/*
4394 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4395 */
4396
4397typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4398DIG_IN_NORMAL_OPERATION = 0x00000000,
4399DIG_IN_DEBUG_MODE = 0x00000001,
4400} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4401
4402/*
4403 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4404 */
4405
4406typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4407DIG_10BIT_TEST_PATTERN = 0x00000000,
4408DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
4409} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4410
4411/*
4412 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4413 */
4414
4415typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4416DIG_TEST_PATTERN_NORMAL = 0x00000000,
4417DIG_TEST_PATTERN_RANDOM = 0x00000001,
4418} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4419
4420/*
4421 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4422 */
4423
4424typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4425DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
4426DIG_RANDOM_PATTERN_RESETED = 0x00000001,
4427} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4428
4429/*
4430 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4431 */
4432
4433typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4434DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
4435DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
4436} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4437
4438/*
4439 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4440 */
4441
4442typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4443DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
4444DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
4445} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4446
4447/*
4448 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4449 */
4450
4451typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4452DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
4453DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
4454} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4455
4456/*
4457 * DIG_FIFO_ERROR_ACK enum
4458 */
4459
4460typedef enum DIG_FIFO_ERROR_ACK {
4461DIG_FIFO_ERROR_ACK_INT = 0x00000000,
4462DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
4463} DIG_FIFO_ERROR_ACK;
4464
4465/*
4466 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4467 */
4468
4469typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4470DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
4471DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
4472} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4473
4474/*
4475 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4476 */
4477
4478typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4479DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
4480DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
4481} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4482
4483/*
4484 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4485 */
4486
4487typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4488AFMT_INTERRUPT_DISABLE = 0x00000000,
4489AFMT_INTERRUPT_ENABLE = 0x00000001,
4490} AFMT_INTERRUPT_STATUS_CHG_MASK;
4491
4492/*
4493 * HDMI_GC_AVMUTE enum
4494 */
4495
4496typedef enum HDMI_GC_AVMUTE {
4497HDMI_GC_AVMUTE_SET = 0x00000000,
4498HDMI_GC_AVMUTE_UNSET = 0x00000001,
4499} HDMI_GC_AVMUTE;
4500
4501/*
4502 * HDMI_DEFAULT_PAHSE enum
4503 */
4504
4505typedef enum HDMI_DEFAULT_PAHSE {
4506HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
4507HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
4508} HDMI_DEFAULT_PAHSE;
4509
4510/*
4511 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4512 */
4513
4514typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4515AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
4516AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
4517} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4518
4519/*
4520 * AUDIO_LAYOUT_SELECT enum
4521 */
4522
4523typedef enum AUDIO_LAYOUT_SELECT {
4524AUDIO_LAYOUT_0 = 0x00000000,
4525AUDIO_LAYOUT_1 = 0x00000001,
4526} AUDIO_LAYOUT_SELECT;
4527
4528/*
4529 * AFMT_AUDIO_CRC_CONTROL_CONT enum
4530 */
4531
4532typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4533AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
4534AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
4535} AFMT_AUDIO_CRC_CONTROL_CONT;
4536
4537/*
4538 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4539 */
4540
4541typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4542AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
4543AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
4544} AFMT_AUDIO_CRC_CONTROL_SOURCE;
4545
4546/*
4547 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4548 */
4549
4550typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4551AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
4552AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
4553AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
4554AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
4555AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
4556AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
4557AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
4558AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
4559AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
4560AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
4561AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
4562AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
4563AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
4564AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
4565AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
4566AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
4567} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4568
4569/*
4570 * AFMT_RAMP_CONTROL0_SIGN enum
4571 */
4572
4573typedef enum