1 | /* |
2 | * Copyright (C) 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _vega20_ip_offset_HEADER |
22 | #define |
23 | |
24 | #define MAX_INSTANCE 6 |
25 | #define MAX_SEGMENT 6 |
26 | |
27 | |
28 | struct IP_BASE_INSTANCE |
29 | { |
30 | unsigned int segment[MAX_SEGMENT]; |
31 | }; |
32 | |
33 | struct IP_BASE |
34 | { |
35 | struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; |
36 | } __maybe_unused; |
37 | |
38 | |
39 | static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } }, |
40 | { { 0, 0, 0, 0, 0, 0 } }, |
41 | { { 0, 0, 0, 0, 0, 0 } }, |
42 | { { 0, 0, 0, 0, 0, 0 } }, |
43 | { { 0, 0, 0, 0, 0, 0 } }, |
44 | { { 0, 0, 0, 0, 0, 0 } } } }; |
45 | static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, |
46 | { { 0, 0, 0, 0, 0, 0 } }, |
47 | { { 0, 0, 0, 0, 0, 0 } }, |
48 | { { 0, 0, 0, 0, 0, 0 } }, |
49 | { { 0, 0, 0, 0, 0, 0 } }, |
50 | { { 0, 0, 0, 0, 0, 0 } } } }; |
51 | static const struct IP_BASE DCE_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, |
52 | { { 0, 0, 0, 0, 0, 0 } }, |
53 | { { 0, 0, 0, 0, 0, 0 } }, |
54 | { { 0, 0, 0, 0, 0, 0 } }, |
55 | { { 0, 0, 0, 0, 0, 0 } }, |
56 | { { 0, 0, 0, 0, 0, 0 } } } }; |
57 | static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, |
58 | { { 0, 0, 0, 0, 0, 0 } }, |
59 | { { 0, 0, 0, 0, 0, 0 } }, |
60 | { { 0, 0, 0, 0, 0, 0 } }, |
61 | { { 0, 0, 0, 0, 0, 0 } }, |
62 | { { 0, 0, 0, 0, 0, 0 } } } }; |
63 | static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, |
64 | { { 0, 0, 0, 0, 0, 0 } }, |
65 | { { 0, 0, 0, 0, 0, 0 } }, |
66 | { { 0, 0, 0, 0, 0, 0 } }, |
67 | { { 0, 0, 0, 0, 0, 0 } }, |
68 | { { 0, 0, 0, 0, 0, 0 } } } }; |
69 | static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } }, |
70 | { { 0, 0, 0, 0, 0, 0 } }, |
71 | { { 0, 0, 0, 0, 0, 0 } }, |
72 | { { 0, 0, 0, 0, 0, 0 } }, |
73 | { { 0, 0, 0, 0, 0, 0 } }, |
74 | { { 0, 0, 0, 0, 0, 0 } } } }; |
75 | static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, |
76 | { { 0, 0, 0, 0, 0, 0 } }, |
77 | { { 0, 0, 0, 0, 0, 0 } }, |
78 | { { 0, 0, 0, 0, 0, 0 } }, |
79 | { { 0, 0, 0, 0, 0, 0 } }, |
80 | { { 0, 0, 0, 0, 0, 0 } } } }; |
81 | static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, |
82 | { { 0, 0, 0, 0, 0, 0 } }, |
83 | { { 0, 0, 0, 0, 0, 0 } }, |
84 | { { 0, 0, 0, 0, 0, 0 } }, |
85 | { { 0, 0, 0, 0, 0, 0 } }, |
86 | { { 0, 0, 0, 0, 0, 0 } } } }; |
87 | static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, |
88 | { { 0, 0, 0, 0, 0, 0 } }, |
89 | { { 0, 0, 0, 0, 0, 0 } }, |
90 | { { 0, 0, 0, 0, 0, 0 } }, |
91 | { { 0, 0, 0, 0, 0, 0 } }, |
92 | { { 0, 0, 0, 0, 0, 0 } } } }; |
93 | static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, |
94 | { { 0, 0, 0, 0, 0, 0 } }, |
95 | { { 0, 0, 0, 0, 0, 0 } }, |
96 | { { 0, 0, 0, 0, 0, 0 } }, |
97 | { { 0, 0, 0, 0, 0, 0 } }, |
98 | { { 0, 0, 0, 0, 0, 0 } } } }; |
99 | static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, |
100 | { { 0, 0, 0, 0, 0, 0 } }, |
101 | { { 0, 0, 0, 0, 0, 0 } }, |
102 | { { 0, 0, 0, 0, 0, 0 } }, |
103 | { { 0, 0, 0, 0, 0, 0 } }, |
104 | { { 0, 0, 0, 0, 0, 0 } } } }; |
105 | static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, |
106 | { { 0, 0, 0, 0, 0, 0 } }, |
107 | { { 0, 0, 0, 0, 0, 0 } }, |
108 | { { 0, 0, 0, 0, 0, 0 } }, |
109 | { { 0, 0, 0, 0, 0, 0 } }, |
110 | { { 0, 0, 0, 0, 0, 0 } } } }; |
111 | static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0, 0, 0, 0, 0 } }, |
112 | { { 0, 0, 0, 0, 0, 0 } }, |
113 | { { 0, 0, 0, 0, 0, 0 } }, |
114 | { { 0, 0, 0, 0, 0, 0 } }, |
115 | { { 0, 0, 0, 0, 0, 0 } }, |
116 | { { 0, 0, 0, 0, 0, 0 } } } }; |
117 | static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0, 0, 0, 0, 0 } }, |
118 | { { 0, 0, 0, 0, 0, 0 } }, |
119 | { { 0, 0, 0, 0, 0, 0 } }, |
120 | { { 0, 0, 0, 0, 0, 0 } }, |
121 | { { 0, 0, 0, 0, 0, 0 } }, |
122 | { { 0, 0, 0, 0, 0, 0 } } } }; |
123 | static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, |
124 | { { 0, 0, 0, 0, 0, 0 } }, |
125 | { { 0, 0, 0, 0, 0, 0 } }, |
126 | { { 0, 0, 0, 0, 0, 0 } }, |
127 | { { 0, 0, 0, 0, 0, 0 } }, |
128 | { { 0, 0, 0, 0, 0, 0 } } } }; |
129 | static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, |
130 | { { 0, 0, 0, 0, 0, 0 } }, |
131 | { { 0, 0, 0, 0, 0, 0 } }, |
132 | { { 0, 0, 0, 0, 0, 0 } }, |
133 | { { 0, 0, 0, 0, 0, 0 } }, |
134 | { { 0, 0, 0, 0, 0, 0 } } } }; |
135 | static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, |
136 | { { 0, 0, 0, 0, 0, 0 } }, |
137 | { { 0, 0, 0, 0, 0, 0 } }, |
138 | { { 0, 0, 0, 0, 0, 0 } }, |
139 | { { 0, 0, 0, 0, 0, 0 } }, |
140 | { { 0, 0, 0, 0, 0, 0 } } } }; |
141 | static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, |
142 | { { 0, 0x00009000, 0, 0, 0, 0 } }, |
143 | { { 0, 0, 0, 0, 0, 0 } }, |
144 | { { 0, 0, 0, 0, 0, 0 } }, |
145 | { { 0, 0, 0, 0, 0, 0 } }, |
146 | { { 0, 0, 0, 0, 0, 0 } } } }; |
147 | /* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/ |
148 | static const struct IP_BASE VCE_BASE ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } }, |
149 | { { 0, 0, 0, 0, 0, 0 } }, |
150 | { { 0, 0, 0, 0, 0, 0 } }, |
151 | { { 0, 0, 0, 0, 0, 0 } }, |
152 | { { 0, 0, 0, 0, 0, 0 } }, |
153 | { { 0, 0, 0, 0, 0, 0 } } } }; |
154 | static const struct IP_BASE XDMA_BASE ={ { { { 0x00003400, 0, 0, 0, 0, 0 } }, |
155 | { { 0, 0, 0, 0, 0, 0 } }, |
156 | { { 0, 0, 0, 0, 0, 0 } }, |
157 | { { 0, 0, 0, 0, 0, 0 } }, |
158 | { { 0, 0, 0, 0, 0, 0 } }, |
159 | { { 0, 0, 0, 0, 0, 0 } } } }; |
160 | static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, |
161 | { { 0, 0, 0, 0, 0, 0 } }, |
162 | { { 0, 0, 0, 0, 0, 0 } }, |
163 | { { 0, 0, 0, 0, 0, 0 } }, |
164 | { { 0, 0, 0, 0, 0, 0 } }, |
165 | { { 0, 0, 0, 0, 0, 0 } } } }; |
166 | |
167 | |
168 | #define ATHUB_BASE__INST0_SEG0 0x00000C20 |
169 | #define ATHUB_BASE__INST0_SEG1 0 |
170 | #define ATHUB_BASE__INST0_SEG2 0 |
171 | #define ATHUB_BASE__INST0_SEG3 0 |
172 | #define ATHUB_BASE__INST0_SEG4 0 |
173 | #define ATHUB_BASE__INST0_SEG5 0 |
174 | |
175 | #define ATHUB_BASE__INST1_SEG0 0 |
176 | #define ATHUB_BASE__INST1_SEG1 0 |
177 | #define ATHUB_BASE__INST1_SEG2 0 |
178 | #define ATHUB_BASE__INST1_SEG3 0 |
179 | #define ATHUB_BASE__INST1_SEG4 0 |
180 | #define ATHUB_BASE__INST1_SEG5 0 |
181 | |
182 | #define ATHUB_BASE__INST2_SEG0 0 |
183 | #define ATHUB_BASE__INST2_SEG1 0 |
184 | #define ATHUB_BASE__INST2_SEG2 0 |
185 | #define ATHUB_BASE__INST2_SEG3 0 |
186 | #define ATHUB_BASE__INST2_SEG4 0 |
187 | #define ATHUB_BASE__INST2_SEG5 0 |
188 | |
189 | #define ATHUB_BASE__INST3_SEG0 0 |
190 | #define ATHUB_BASE__INST3_SEG1 0 |
191 | #define ATHUB_BASE__INST3_SEG2 0 |
192 | #define ATHUB_BASE__INST3_SEG3 0 |
193 | #define ATHUB_BASE__INST3_SEG4 0 |
194 | #define ATHUB_BASE__INST3_SEG5 0 |
195 | |
196 | #define ATHUB_BASE__INST4_SEG0 0 |
197 | #define ATHUB_BASE__INST4_SEG1 0 |
198 | #define ATHUB_BASE__INST4_SEG2 0 |
199 | #define ATHUB_BASE__INST4_SEG3 0 |
200 | #define ATHUB_BASE__INST4_SEG4 0 |
201 | #define ATHUB_BASE__INST4_SEG5 0 |
202 | |
203 | #define ATHUB_BASE__INST5_SEG0 0 |
204 | #define ATHUB_BASE__INST5_SEG1 0 |
205 | #define ATHUB_BASE__INST5_SEG2 0 |
206 | #define ATHUB_BASE__INST5_SEG3 0 |
207 | #define ATHUB_BASE__INST5_SEG4 0 |
208 | #define ATHUB_BASE__INST5_SEG5 0 |
209 | |
210 | #define CLK_BASE__INST0_SEG0 0x00016C00 |
211 | #define CLK_BASE__INST0_SEG1 0x00016E00 |
212 | #define CLK_BASE__INST0_SEG2 0x00017000 |
213 | #define CLK_BASE__INST0_SEG3 0x00017200 |
214 | #define CLK_BASE__INST0_SEG4 0x0001B000 |
215 | #define CLK_BASE__INST0_SEG5 0x0001B200 |
216 | |
217 | #define CLK_BASE__INST1_SEG0 0 |
218 | #define CLK_BASE__INST1_SEG1 0 |
219 | #define CLK_BASE__INST1_SEG2 0 |
220 | #define CLK_BASE__INST1_SEG3 0 |
221 | #define CLK_BASE__INST1_SEG4 0 |
222 | #define CLK_BASE__INST1_SEG5 0 |
223 | |
224 | #define CLK_BASE__INST2_SEG0 0 |
225 | #define CLK_BASE__INST2_SEG1 0 |
226 | #define CLK_BASE__INST2_SEG2 0 |
227 | #define CLK_BASE__INST2_SEG3 0 |
228 | #define CLK_BASE__INST2_SEG4 0 |
229 | #define CLK_BASE__INST2_SEG5 0 |
230 | |
231 | #define CLK_BASE__INST3_SEG0 0 |
232 | #define CLK_BASE__INST3_SEG1 0 |
233 | #define CLK_BASE__INST3_SEG2 0 |
234 | #define CLK_BASE__INST3_SEG3 0 |
235 | #define CLK_BASE__INST3_SEG4 0 |
236 | #define CLK_BASE__INST3_SEG5 0 |
237 | |
238 | #define CLK_BASE__INST4_SEG0 0 |
239 | #define CLK_BASE__INST4_SEG1 0 |
240 | #define CLK_BASE__INST4_SEG2 0 |
241 | #define CLK_BASE__INST4_SEG3 0 |
242 | #define CLK_BASE__INST4_SEG4 0 |
243 | #define CLK_BASE__INST4_SEG5 0 |
244 | |
245 | #define CLK_BASE__INST5_SEG0 0 |
246 | #define CLK_BASE__INST5_SEG1 0 |
247 | #define CLK_BASE__INST5_SEG2 0 |
248 | #define CLK_BASE__INST5_SEG3 0 |
249 | #define CLK_BASE__INST5_SEG4 0 |
250 | #define CLK_BASE__INST5_SEG5 0 |
251 | |
252 | #define DCE_BASE__INST0_SEG0 0x00000012 |
253 | #define DCE_BASE__INST0_SEG1 0x000000C0 |
254 | #define DCE_BASE__INST0_SEG2 0x000034C0 |
255 | #define DCE_BASE__INST0_SEG3 0 |
256 | #define DCE_BASE__INST0_SEG4 0 |
257 | #define DCE_BASE__INST0_SEG5 0 |
258 | |
259 | #define DCE_BASE__INST1_SEG0 0 |
260 | #define DCE_BASE__INST1_SEG1 0 |
261 | #define DCE_BASE__INST1_SEG2 0 |
262 | #define DCE_BASE__INST1_SEG3 0 |
263 | #define DCE_BASE__INST1_SEG4 0 |
264 | #define DCE_BASE__INST1_SEG5 0 |
265 | |
266 | #define DCE_BASE__INST2_SEG0 0 |
267 | #define DCE_BASE__INST2_SEG1 0 |
268 | #define DCE_BASE__INST2_SEG2 0 |
269 | #define DCE_BASE__INST2_SEG3 0 |
270 | #define DCE_BASE__INST2_SEG4 0 |
271 | #define DCE_BASE__INST2_SEG5 0 |
272 | |
273 | #define DCE_BASE__INST3_SEG0 0 |
274 | #define DCE_BASE__INST3_SEG1 0 |
275 | #define DCE_BASE__INST3_SEG2 0 |
276 | #define DCE_BASE__INST3_SEG3 0 |
277 | #define DCE_BASE__INST3_SEG4 0 |
278 | #define DCE_BASE__INST3_SEG5 0 |
279 | |
280 | #define DCE_BASE__INST4_SEG0 0 |
281 | #define DCE_BASE__INST4_SEG1 0 |
282 | #define DCE_BASE__INST4_SEG2 0 |
283 | #define DCE_BASE__INST4_SEG3 0 |
284 | #define DCE_BASE__INST4_SEG4 0 |
285 | #define DCE_BASE__INST4_SEG5 0 |
286 | |
287 | #define DCE_BASE__INST5_SEG0 0 |
288 | #define DCE_BASE__INST5_SEG1 0 |
289 | #define DCE_BASE__INST5_SEG2 0 |
290 | #define DCE_BASE__INST5_SEG3 0 |
291 | #define DCE_BASE__INST5_SEG4 0 |
292 | #define DCE_BASE__INST5_SEG5 0 |
293 | |
294 | #define DF_BASE__INST0_SEG0 0x00007000 |
295 | #define DF_BASE__INST0_SEG1 0 |
296 | #define DF_BASE__INST0_SEG2 0 |
297 | #define DF_BASE__INST0_SEG3 0 |
298 | #define DF_BASE__INST0_SEG4 0 |
299 | #define DF_BASE__INST0_SEG5 0 |
300 | |
301 | #define DF_BASE__INST1_SEG0 0 |
302 | #define DF_BASE__INST1_SEG1 0 |
303 | #define DF_BASE__INST1_SEG2 0 |
304 | #define DF_BASE__INST1_SEG3 0 |
305 | #define DF_BASE__INST1_SEG4 0 |
306 | #define DF_BASE__INST1_SEG5 0 |
307 | |
308 | #define DF_BASE__INST2_SEG0 0 |
309 | #define DF_BASE__INST2_SEG1 0 |
310 | #define DF_BASE__INST2_SEG2 0 |
311 | #define DF_BASE__INST2_SEG3 0 |
312 | #define DF_BASE__INST2_SEG4 0 |
313 | #define DF_BASE__INST2_SEG5 0 |
314 | |
315 | #define DF_BASE__INST3_SEG0 0 |
316 | #define DF_BASE__INST3_SEG1 0 |
317 | #define DF_BASE__INST3_SEG2 0 |
318 | #define DF_BASE__INST3_SEG3 0 |
319 | #define DF_BASE__INST3_SEG4 0 |
320 | #define DF_BASE__INST3_SEG5 0 |
321 | |
322 | #define DF_BASE__INST4_SEG0 0 |
323 | #define DF_BASE__INST4_SEG1 0 |
324 | #define DF_BASE__INST4_SEG2 0 |
325 | #define DF_BASE__INST4_SEG3 0 |
326 | #define DF_BASE__INST4_SEG4 0 |
327 | #define DF_BASE__INST4_SEG5 0 |
328 | |
329 | #define DF_BASE__INST5_SEG0 0 |
330 | #define DF_BASE__INST5_SEG1 0 |
331 | #define DF_BASE__INST5_SEG2 0 |
332 | #define DF_BASE__INST5_SEG3 0 |
333 | #define DF_BASE__INST5_SEG4 0 |
334 | #define DF_BASE__INST5_SEG5 0 |
335 | |
336 | #define FUSE_BASE__INST0_SEG0 0x00017400 |
337 | #define FUSE_BASE__INST0_SEG1 0 |
338 | #define FUSE_BASE__INST0_SEG2 0 |
339 | #define FUSE_BASE__INST0_SEG3 0 |
340 | #define FUSE_BASE__INST0_SEG4 0 |
341 | #define FUSE_BASE__INST0_SEG5 0 |
342 | |
343 | #define FUSE_BASE__INST1_SEG0 0 |
344 | #define FUSE_BASE__INST1_SEG1 0 |
345 | #define FUSE_BASE__INST1_SEG2 0 |
346 | #define FUSE_BASE__INST1_SEG3 0 |
347 | #define FUSE_BASE__INST1_SEG4 0 |
348 | #define FUSE_BASE__INST1_SEG5 0 |
349 | |
350 | #define FUSE_BASE__INST2_SEG0 0 |
351 | #define FUSE_BASE__INST2_SEG1 0 |
352 | #define FUSE_BASE__INST2_SEG2 0 |
353 | #define FUSE_BASE__INST2_SEG3 0 |
354 | #define FUSE_BASE__INST2_SEG4 0 |
355 | #define FUSE_BASE__INST2_SEG5 0 |
356 | |
357 | #define FUSE_BASE__INST3_SEG0 0 |
358 | #define FUSE_BASE__INST3_SEG1 0 |
359 | #define FUSE_BASE__INST3_SEG2 0 |
360 | #define FUSE_BASE__INST3_SEG3 0 |
361 | #define FUSE_BASE__INST3_SEG4 0 |
362 | #define FUSE_BASE__INST3_SEG5 0 |
363 | |
364 | #define FUSE_BASE__INST4_SEG0 0 |
365 | #define FUSE_BASE__INST4_SEG1 0 |
366 | #define FUSE_BASE__INST4_SEG2 0 |
367 | #define FUSE_BASE__INST4_SEG3 0 |
368 | #define FUSE_BASE__INST4_SEG4 0 |
369 | #define FUSE_BASE__INST4_SEG5 0 |
370 | |
371 | #define FUSE_BASE__INST5_SEG0 0 |
372 | #define FUSE_BASE__INST5_SEG1 0 |
373 | #define FUSE_BASE__INST5_SEG2 0 |
374 | #define FUSE_BASE__INST5_SEG3 0 |
375 | #define FUSE_BASE__INST5_SEG4 0 |
376 | #define FUSE_BASE__INST5_SEG5 0 |
377 | |
378 | #define GC_BASE__INST0_SEG0 0x00002000 |
379 | #define GC_BASE__INST0_SEG1 0x0000A000 |
380 | #define GC_BASE__INST0_SEG2 0 |
381 | #define GC_BASE__INST0_SEG3 0 |
382 | #define GC_BASE__INST0_SEG4 0 |
383 | #define GC_BASE__INST0_SEG5 0 |
384 | |
385 | #define GC_BASE__INST1_SEG0 0 |
386 | #define GC_BASE__INST1_SEG1 0 |
387 | #define GC_BASE__INST1_SEG2 0 |
388 | #define GC_BASE__INST1_SEG3 0 |
389 | #define GC_BASE__INST1_SEG4 0 |
390 | #define GC_BASE__INST1_SEG5 0 |
391 | |
392 | #define GC_BASE__INST2_SEG0 0 |
393 | #define GC_BASE__INST2_SEG1 0 |
394 | #define GC_BASE__INST2_SEG2 0 |
395 | #define GC_BASE__INST2_SEG3 0 |
396 | #define GC_BASE__INST2_SEG4 0 |
397 | #define GC_BASE__INST2_SEG5 0 |
398 | |
399 | #define GC_BASE__INST3_SEG0 0 |
400 | #define GC_BASE__INST3_SEG1 0 |
401 | #define GC_BASE__INST3_SEG2 0 |
402 | #define GC_BASE__INST3_SEG3 0 |
403 | #define GC_BASE__INST3_SEG4 0 |
404 | #define GC_BASE__INST3_SEG5 0 |
405 | |
406 | #define GC_BASE__INST4_SEG0 0 |
407 | #define GC_BASE__INST4_SEG1 0 |
408 | #define GC_BASE__INST4_SEG2 0 |
409 | #define GC_BASE__INST4_SEG3 0 |
410 | #define GC_BASE__INST4_SEG4 0 |
411 | #define GC_BASE__INST4_SEG5 0 |
412 | |
413 | #define GC_BASE__INST5_SEG0 0 |
414 | #define GC_BASE__INST5_SEG1 0 |
415 | #define GC_BASE__INST5_SEG2 0 |
416 | #define GC_BASE__INST5_SEG3 0 |
417 | #define GC_BASE__INST5_SEG4 0 |
418 | #define GC_BASE__INST5_SEG5 0 |
419 | |
420 | #define HDP_BASE__INST0_SEG0 0x00000F20 |
421 | #define HDP_BASE__INST0_SEG1 0 |
422 | #define HDP_BASE__INST0_SEG2 0 |
423 | #define HDP_BASE__INST0_SEG3 0 |
424 | #define HDP_BASE__INST0_SEG4 0 |
425 | #define HDP_BASE__INST0_SEG5 0 |
426 | |
427 | #define HDP_BASE__INST1_SEG0 0 |
428 | #define HDP_BASE__INST1_SEG1 0 |
429 | #define HDP_BASE__INST1_SEG2 0 |
430 | #define HDP_BASE__INST1_SEG3 0 |
431 | #define HDP_BASE__INST1_SEG4 0 |
432 | #define HDP_BASE__INST1_SEG5 0 |
433 | |
434 | #define HDP_BASE__INST2_SEG0 0 |
435 | #define HDP_BASE__INST2_SEG1 0 |
436 | #define HDP_BASE__INST2_SEG2 0 |
437 | #define HDP_BASE__INST2_SEG3 0 |
438 | #define HDP_BASE__INST2_SEG4 0 |
439 | #define HDP_BASE__INST2_SEG5 0 |
440 | |
441 | #define HDP_BASE__INST3_SEG0 0 |
442 | #define HDP_BASE__INST3_SEG1 0 |
443 | #define HDP_BASE__INST3_SEG2 0 |
444 | #define HDP_BASE__INST3_SEG3 0 |
445 | #define HDP_BASE__INST3_SEG4 0 |
446 | #define HDP_BASE__INST3_SEG5 0 |
447 | |
448 | #define HDP_BASE__INST4_SEG0 0 |
449 | #define HDP_BASE__INST4_SEG1 0 |
450 | #define HDP_BASE__INST4_SEG2 0 |
451 | #define HDP_BASE__INST4_SEG3 0 |
452 | #define HDP_BASE__INST4_SEG4 0 |
453 | #define HDP_BASE__INST4_SEG5 0 |
454 | |
455 | #define HDP_BASE__INST5_SEG0 0 |
456 | #define HDP_BASE__INST5_SEG1 0 |
457 | #define HDP_BASE__INST5_SEG2 0 |
458 | #define HDP_BASE__INST5_SEG3 0 |
459 | #define HDP_BASE__INST5_SEG4 0 |
460 | #define HDP_BASE__INST5_SEG5 0 |
461 | |
462 | #define MMHUB_BASE__INST0_SEG0 0x0001A000 |
463 | #define MMHUB_BASE__INST0_SEG1 0 |
464 | #define MMHUB_BASE__INST0_SEG2 0 |
465 | #define MMHUB_BASE__INST0_SEG3 0 |
466 | #define MMHUB_BASE__INST0_SEG4 0 |
467 | #define MMHUB_BASE__INST0_SEG5 0 |
468 | |
469 | #define MMHUB_BASE__INST1_SEG0 0 |
470 | #define MMHUB_BASE__INST1_SEG1 0 |
471 | #define MMHUB_BASE__INST1_SEG2 0 |
472 | #define MMHUB_BASE__INST1_SEG3 0 |
473 | #define MMHUB_BASE__INST1_SEG4 0 |
474 | #define MMHUB_BASE__INST1_SEG5 0 |
475 | |
476 | #define MMHUB_BASE__INST2_SEG0 0 |
477 | #define MMHUB_BASE__INST2_SEG1 0 |
478 | #define MMHUB_BASE__INST2_SEG2 0 |
479 | #define MMHUB_BASE__INST2_SEG3 0 |
480 | #define MMHUB_BASE__INST2_SEG4 0 |
481 | #define MMHUB_BASE__INST2_SEG5 0 |
482 | |
483 | #define MMHUB_BASE__INST3_SEG0 0 |
484 | #define MMHUB_BASE__INST3_SEG1 0 |
485 | #define MMHUB_BASE__INST3_SEG2 0 |
486 | #define MMHUB_BASE__INST3_SEG3 0 |
487 | #define MMHUB_BASE__INST3_SEG4 0 |
488 | #define MMHUB_BASE__INST3_SEG5 0 |
489 | |
490 | #define MMHUB_BASE__INST4_SEG0 0 |
491 | #define MMHUB_BASE__INST4_SEG1 0 |
492 | #define MMHUB_BASE__INST4_SEG2 0 |
493 | #define MMHUB_BASE__INST4_SEG3 0 |
494 | #define MMHUB_BASE__INST4_SEG4 0 |
495 | #define MMHUB_BASE__INST4_SEG5 0 |
496 | |
497 | #define MMHUB_BASE__INST5_SEG0 0 |
498 | #define MMHUB_BASE__INST5_SEG1 0 |
499 | #define MMHUB_BASE__INST5_SEG2 0 |
500 | #define MMHUB_BASE__INST5_SEG3 0 |
501 | #define MMHUB_BASE__INST5_SEG4 0 |
502 | #define MMHUB_BASE__INST5_SEG5 0 |
503 | |
504 | #define MP0_BASE__INST0_SEG0 0x00016000 |
505 | #define MP0_BASE__INST0_SEG1 0 |
506 | #define MP0_BASE__INST0_SEG2 0 |
507 | #define MP0_BASE__INST0_SEG3 0 |
508 | #define MP0_BASE__INST0_SEG4 0 |
509 | #define MP0_BASE__INST0_SEG5 0 |
510 | |
511 | #define MP0_BASE__INST1_SEG0 0 |
512 | #define MP0_BASE__INST1_SEG1 0 |
513 | #define MP0_BASE__INST1_SEG2 0 |
514 | #define MP0_BASE__INST1_SEG3 0 |
515 | #define MP0_BASE__INST1_SEG4 0 |
516 | #define MP0_BASE__INST1_SEG5 0 |
517 | |
518 | #define MP0_BASE__INST2_SEG0 0 |
519 | #define MP0_BASE__INST2_SEG1 0 |
520 | #define MP0_BASE__INST2_SEG2 0 |
521 | #define MP0_BASE__INST2_SEG3 0 |
522 | #define MP0_BASE__INST2_SEG4 0 |
523 | #define MP0_BASE__INST2_SEG5 0 |
524 | |
525 | #define MP0_BASE__INST3_SEG0 0 |
526 | #define MP0_BASE__INST3_SEG1 0 |
527 | #define MP0_BASE__INST3_SEG2 0 |
528 | #define MP0_BASE__INST3_SEG3 0 |
529 | #define MP0_BASE__INST3_SEG4 0 |
530 | #define MP0_BASE__INST3_SEG5 0 |
531 | |
532 | #define MP0_BASE__INST4_SEG0 0 |
533 | #define MP0_BASE__INST4_SEG1 0 |
534 | #define MP0_BASE__INST4_SEG2 0 |
535 | #define MP0_BASE__INST4_SEG3 0 |
536 | #define MP0_BASE__INST4_SEG4 0 |
537 | #define MP0_BASE__INST4_SEG5 0 |
538 | |
539 | #define MP0_BASE__INST5_SEG0 0 |
540 | #define MP0_BASE__INST5_SEG1 0 |
541 | #define MP0_BASE__INST5_SEG2 0 |
542 | #define MP0_BASE__INST5_SEG3 0 |
543 | #define MP0_BASE__INST5_SEG4 0 |
544 | #define MP0_BASE__INST5_SEG5 0 |
545 | |
546 | #define MP1_BASE__INST0_SEG0 0x00016000 |
547 | #define MP1_BASE__INST0_SEG1 0 |
548 | #define MP1_BASE__INST0_SEG2 0 |
549 | #define MP1_BASE__INST0_SEG3 0 |
550 | #define MP1_BASE__INST0_SEG4 0 |
551 | #define MP1_BASE__INST0_SEG5 0 |
552 | |
553 | #define MP1_BASE__INST1_SEG0 0 |
554 | #define MP1_BASE__INST1_SEG1 0 |
555 | #define MP1_BASE__INST1_SEG2 0 |
556 | #define MP1_BASE__INST1_SEG3 0 |
557 | #define MP1_BASE__INST1_SEG4 0 |
558 | #define MP1_BASE__INST1_SEG5 0 |
559 | |
560 | #define MP1_BASE__INST2_SEG0 0 |
561 | #define MP1_BASE__INST2_SEG1 0 |
562 | #define MP1_BASE__INST2_SEG2 0 |
563 | #define MP1_BASE__INST2_SEG3 0 |
564 | #define MP1_BASE__INST2_SEG4 0 |
565 | #define MP1_BASE__INST2_SEG5 0 |
566 | |
567 | #define MP1_BASE__INST3_SEG0 0 |
568 | #define MP1_BASE__INST3_SEG1 0 |
569 | #define MP1_BASE__INST3_SEG2 0 |
570 | #define MP1_BASE__INST3_SEG3 0 |
571 | #define MP1_BASE__INST3_SEG4 0 |
572 | #define MP1_BASE__INST3_SEG5 0 |
573 | |
574 | #define MP1_BASE__INST4_SEG0 0 |
575 | #define MP1_BASE__INST4_SEG1 0 |
576 | #define MP1_BASE__INST4_SEG2 0 |
577 | #define MP1_BASE__INST4_SEG3 0 |
578 | #define MP1_BASE__INST4_SEG4 0 |
579 | #define MP1_BASE__INST4_SEG5 0 |
580 | |
581 | #define MP1_BASE__INST5_SEG0 0 |
582 | #define MP1_BASE__INST5_SEG1 0 |
583 | #define MP1_BASE__INST5_SEG2 0 |
584 | #define MP1_BASE__INST5_SEG3 0 |
585 | #define MP1_BASE__INST5_SEG4 0 |
586 | #define MP1_BASE__INST5_SEG5 0 |
587 | |
588 | #define NBIO_BASE__INST0_SEG0 0x00000000 |
589 | #define NBIO_BASE__INST0_SEG1 0x00000014 |
590 | #define NBIO_BASE__INST0_SEG2 0x00000D20 |
591 | #define NBIO_BASE__INST0_SEG3 0x00010400 |
592 | #define NBIO_BASE__INST0_SEG4 0 |
593 | #define NBIO_BASE__INST0_SEG5 0 |
594 | |
595 | #define NBIO_BASE__INST1_SEG0 0 |
596 | #define NBIO_BASE__INST1_SEG1 0 |
597 | #define NBIO_BASE__INST1_SEG2 0 |
598 | #define NBIO_BASE__INST1_SEG3 0 |
599 | #define NBIO_BASE__INST1_SEG4 0 |
600 | #define NBIO_BASE__INST1_SEG5 0 |
601 | |
602 | #define NBIO_BASE__INST2_SEG0 0 |
603 | #define NBIO_BASE__INST2_SEG1 0 |
604 | #define NBIO_BASE__INST2_SEG2 0 |
605 | #define NBIO_BASE__INST2_SEG3 0 |
606 | #define NBIO_BASE__INST2_SEG4 0 |
607 | #define NBIO_BASE__INST2_SEG5 0 |
608 | |
609 | #define NBIO_BASE__INST3_SEG0 0 |
610 | #define NBIO_BASE__INST3_SEG1 0 |
611 | #define NBIO_BASE__INST3_SEG2 0 |
612 | #define NBIO_BASE__INST3_SEG3 0 |
613 | #define NBIO_BASE__INST3_SEG4 0 |
614 | #define NBIO_BASE__INST3_SEG5 0 |
615 | |
616 | #define NBIO_BASE__INST4_SEG0 0 |
617 | #define NBIO_BASE__INST4_SEG1 0 |
618 | #define NBIO_BASE__INST4_SEG2 0 |
619 | #define NBIO_BASE__INST4_SEG3 0 |
620 | #define NBIO_BASE__INST4_SEG4 0 |
621 | #define NBIO_BASE__INST4_SEG5 0 |
622 | |
623 | #define NBIO_BASE__INST5_SEG0 0 |
624 | #define NBIO_BASE__INST5_SEG1 0 |
625 | #define NBIO_BASE__INST5_SEG2 0 |
626 | #define NBIO_BASE__INST5_SEG3 0 |
627 | #define NBIO_BASE__INST5_SEG4 0 |
628 | #define NBIO_BASE__INST5_SEG5 0 |
629 | |
630 | #define OSSSYS_BASE__INST0_SEG0 0x000010A0 |
631 | #define OSSSYS_BASE__INST0_SEG1 0 |
632 | #define OSSSYS_BASE__INST0_SEG2 0 |
633 | #define OSSSYS_BASE__INST0_SEG3 0 |
634 | #define OSSSYS_BASE__INST0_SEG4 0 |
635 | #define OSSSYS_BASE__INST0_SEG5 0 |
636 | |
637 | #define OSSSYS_BASE__INST1_SEG0 0 |
638 | #define OSSSYS_BASE__INST1_SEG1 0 |
639 | #define OSSSYS_BASE__INST1_SEG2 0 |
640 | #define OSSSYS_BASE__INST1_SEG3 0 |
641 | #define OSSSYS_BASE__INST1_SEG4 0 |
642 | #define OSSSYS_BASE__INST1_SEG5 0 |
643 | |
644 | #define OSSSYS_BASE__INST2_SEG0 0 |
645 | #define OSSSYS_BASE__INST2_SEG1 0 |
646 | #define OSSSYS_BASE__INST2_SEG2 0 |
647 | #define OSSSYS_BASE__INST2_SEG3 0 |
648 | #define OSSSYS_BASE__INST2_SEG4 0 |
649 | #define OSSSYS_BASE__INST2_SEG5 0 |
650 | |
651 | #define OSSSYS_BASE__INST3_SEG0 0 |
652 | #define OSSSYS_BASE__INST3_SEG1 0 |
653 | #define OSSSYS_BASE__INST3_SEG2 0 |
654 | #define OSSSYS_BASE__INST3_SEG3 0 |
655 | #define OSSSYS_BASE__INST3_SEG4 0 |
656 | #define OSSSYS_BASE__INST3_SEG5 0 |
657 | |
658 | #define OSSSYS_BASE__INST4_SEG0 0 |
659 | #define OSSSYS_BASE__INST4_SEG1 0 |
660 | #define OSSSYS_BASE__INST4_SEG2 0 |
661 | #define OSSSYS_BASE__INST4_SEG3 0 |
662 | #define OSSSYS_BASE__INST4_SEG4 0 |
663 | #define OSSSYS_BASE__INST4_SEG5 0 |
664 | |
665 | #define OSSSYS_BASE__INST5_SEG0 0 |
666 | #define OSSSYS_BASE__INST5_SEG1 0 |
667 | #define OSSSYS_BASE__INST5_SEG2 0 |
668 | #define OSSSYS_BASE__INST5_SEG3 0 |
669 | #define OSSSYS_BASE__INST5_SEG4 0 |
670 | #define OSSSYS_BASE__INST5_SEG5 0 |
671 | |
672 | #define SDMA0_BASE__INST0_SEG0 0x00001260 |
673 | #define SDMA0_BASE__INST0_SEG1 0 |
674 | #define SDMA0_BASE__INST0_SEG2 0 |
675 | #define SDMA0_BASE__INST0_SEG3 0 |
676 | #define SDMA0_BASE__INST0_SEG4 0 |
677 | #define SDMA0_BASE__INST0_SEG5 0 |
678 | |
679 | #define SDMA0_BASE__INST1_SEG0 0 |
680 | #define SDMA0_BASE__INST1_SEG1 0 |
681 | #define SDMA0_BASE__INST1_SEG2 0 |
682 | #define SDMA0_BASE__INST1_SEG3 0 |
683 | #define SDMA0_BASE__INST1_SEG4 0 |
684 | #define SDMA0_BASE__INST1_SEG5 0 |
685 | |
686 | #define SDMA0_BASE__INST2_SEG0 0 |
687 | #define SDMA0_BASE__INST2_SEG1 0 |
688 | #define SDMA0_BASE__INST2_SEG2 0 |
689 | #define SDMA0_BASE__INST2_SEG3 0 |
690 | #define SDMA0_BASE__INST2_SEG4 0 |
691 | #define SDMA0_BASE__INST2_SEG5 0 |
692 | |
693 | #define SDMA0_BASE__INST3_SEG0 0 |
694 | #define SDMA0_BASE__INST3_SEG1 0 |
695 | #define SDMA0_BASE__INST3_SEG2 0 |
696 | #define SDMA0_BASE__INST3_SEG3 0 |
697 | #define SDMA0_BASE__INST3_SEG4 0 |
698 | #define SDMA0_BASE__INST3_SEG5 0 |
699 | |
700 | #define SDMA0_BASE__INST4_SEG0 0 |
701 | #define SDMA0_BASE__INST4_SEG1 0 |
702 | #define SDMA0_BASE__INST4_SEG2 0 |
703 | #define SDMA0_BASE__INST4_SEG3 0 |
704 | #define SDMA0_BASE__INST4_SEG4 0 |
705 | #define SDMA0_BASE__INST4_SEG5 0 |
706 | |
707 | #define SDMA0_BASE__INST5_SEG0 0 |
708 | #define SDMA0_BASE__INST5_SEG1 0 |
709 | #define SDMA0_BASE__INST5_SEG2 0 |
710 | #define SDMA0_BASE__INST5_SEG3 0 |
711 | #define SDMA0_BASE__INST5_SEG4 0 |
712 | #define SDMA0_BASE__INST5_SEG5 0 |
713 | |
714 | #define SDMA1_BASE__INST0_SEG0 0x00001860 |
715 | #define SDMA1_BASE__INST0_SEG1 0 |
716 | #define SDMA1_BASE__INST0_SEG2 0 |
717 | #define SDMA1_BASE__INST0_SEG3 0 |
718 | #define SDMA1_BASE__INST0_SEG4 0 |
719 | #define SDMA1_BASE__INST0_SEG5 0 |
720 | |
721 | #define SDMA1_BASE__INST1_SEG0 0 |
722 | #define SDMA1_BASE__INST1_SEG1 0 |
723 | #define SDMA1_BASE__INST1_SEG2 0 |
724 | #define SDMA1_BASE__INST1_SEG3 0 |
725 | #define SDMA1_BASE__INST1_SEG4 0 |
726 | #define SDMA1_BASE__INST1_SEG5 0 |
727 | |
728 | #define SDMA1_BASE__INST2_SEG0 0 |
729 | #define SDMA1_BASE__INST2_SEG1 0 |
730 | #define SDMA1_BASE__INST2_SEG2 0 |
731 | #define SDMA1_BASE__INST2_SEG3 0 |
732 | #define SDMA1_BASE__INST2_SEG4 0 |
733 | #define SDMA1_BASE__INST2_SEG5 0 |
734 | |
735 | #define SDMA1_BASE__INST3_SEG0 0 |
736 | #define SDMA1_BASE__INST3_SEG1 0 |
737 | #define SDMA1_BASE__INST3_SEG2 0 |
738 | #define SDMA1_BASE__INST3_SEG3 0 |
739 | #define SDMA1_BASE__INST3_SEG4 0 |
740 | #define SDMA1_BASE__INST3_SEG5 0 |
741 | |
742 | #define SDMA1_BASE__INST4_SEG0 0 |
743 | #define SDMA1_BASE__INST4_SEG1 0 |
744 | #define SDMA1_BASE__INST4_SEG2 0 |
745 | #define SDMA1_BASE__INST4_SEG3 0 |
746 | #define SDMA1_BASE__INST4_SEG4 0 |
747 | #define SDMA1_BASE__INST4_SEG5 0 |
748 | |
749 | #define SDMA1_BASE__INST5_SEG0 0 |
750 | #define SDMA1_BASE__INST5_SEG1 0 |
751 | #define SDMA1_BASE__INST5_SEG2 0 |
752 | #define SDMA1_BASE__INST5_SEG3 0 |
753 | #define SDMA1_BASE__INST5_SEG4 0 |
754 | #define SDMA1_BASE__INST5_SEG5 0 |
755 | |
756 | #define SMUIO_BASE__INST0_SEG0 0x00016800 |
757 | #define SMUIO_BASE__INST0_SEG1 0x00016A00 |
758 | #define SMUIO_BASE__INST0_SEG2 0 |
759 | #define SMUIO_BASE__INST0_SEG3 0 |
760 | #define SMUIO_BASE__INST0_SEG4 0 |
761 | #define SMUIO_BASE__INST0_SEG5 0 |
762 | |
763 | #define SMUIO_BASE__INST1_SEG0 0 |
764 | #define SMUIO_BASE__INST1_SEG1 0 |
765 | #define SMUIO_BASE__INST1_SEG2 0 |
766 | #define SMUIO_BASE__INST1_SEG3 0 |
767 | #define SMUIO_BASE__INST1_SEG4 0 |
768 | #define SMUIO_BASE__INST1_SEG5 0 |
769 | |
770 | #define SMUIO_BASE__INST2_SEG0 0 |
771 | #define SMUIO_BASE__INST2_SEG1 0 |
772 | #define SMUIO_BASE__INST2_SEG2 0 |
773 | #define SMUIO_BASE__INST2_SEG3 0 |
774 | #define SMUIO_BASE__INST2_SEG4 0 |
775 | #define SMUIO_BASE__INST2_SEG5 0 |
776 | |
777 | #define SMUIO_BASE__INST3_SEG0 0 |
778 | #define SMUIO_BASE__INST3_SEG1 0 |
779 | #define SMUIO_BASE__INST3_SEG2 0 |
780 | #define SMUIO_BASE__INST3_SEG3 0 |
781 | #define SMUIO_BASE__INST3_SEG4 0 |
782 | #define SMUIO_BASE__INST3_SEG5 0 |
783 | |
784 | #define SMUIO_BASE__INST4_SEG0 0 |
785 | #define SMUIO_BASE__INST4_SEG1 0 |
786 | #define SMUIO_BASE__INST4_SEG2 0 |
787 | #define SMUIO_BASE__INST4_SEG3 0 |
788 | #define SMUIO_BASE__INST4_SEG4 0 |
789 | #define SMUIO_BASE__INST4_SEG5 0 |
790 | |
791 | #define SMUIO_BASE__INST5_SEG0 0 |
792 | #define SMUIO_BASE__INST5_SEG1 0 |
793 | #define SMUIO_BASE__INST5_SEG2 0 |
794 | #define SMUIO_BASE__INST5_SEG3 0 |
795 | #define SMUIO_BASE__INST5_SEG4 0 |
796 | #define SMUIO_BASE__INST5_SEG5 0 |
797 | |
798 | #define THM_BASE__INST0_SEG0 0x00016600 |
799 | #define THM_BASE__INST0_SEG1 0 |
800 | #define THM_BASE__INST0_SEG2 0 |
801 | #define THM_BASE__INST0_SEG3 0 |
802 | #define THM_BASE__INST0_SEG4 0 |
803 | #define THM_BASE__INST0_SEG5 0 |
804 | |
805 | #define THM_BASE__INST1_SEG0 0 |
806 | #define THM_BASE__INST1_SEG1 0 |
807 | #define THM_BASE__INST1_SEG2 0 |
808 | #define THM_BASE__INST1_SEG3 0 |
809 | #define THM_BASE__INST1_SEG4 0 |
810 | #define THM_BASE__INST1_SEG5 0 |
811 | |
812 | #define THM_BASE__INST2_SEG0 0 |
813 | #define THM_BASE__INST2_SEG1 0 |
814 | #define THM_BASE__INST2_SEG2 0 |
815 | #define THM_BASE__INST2_SEG3 0 |
816 | #define THM_BASE__INST2_SEG4 0 |
817 | #define THM_BASE__INST2_SEG5 0 |
818 | |
819 | #define THM_BASE__INST3_SEG0 0 |
820 | #define THM_BASE__INST3_SEG1 0 |
821 | #define THM_BASE__INST3_SEG2 0 |
822 | #define THM_BASE__INST3_SEG3 0 |
823 | #define THM_BASE__INST3_SEG4 0 |
824 | #define THM_BASE__INST3_SEG5 0 |
825 | |
826 | #define THM_BASE__INST4_SEG0 0 |
827 | #define THM_BASE__INST4_SEG1 0 |
828 | #define THM_BASE__INST4_SEG2 0 |
829 | #define THM_BASE__INST4_SEG3 0 |
830 | #define THM_BASE__INST4_SEG4 0 |
831 | #define THM_BASE__INST4_SEG5 0 |
832 | |
833 | #define THM_BASE__INST5_SEG0 0 |
834 | #define THM_BASE__INST5_SEG1 0 |
835 | #define THM_BASE__INST5_SEG2 0 |
836 | #define THM_BASE__INST5_SEG3 0 |
837 | #define THM_BASE__INST5_SEG4 0 |
838 | #define THM_BASE__INST5_SEG5 0 |
839 | |
840 | #define UMC_BASE__INST0_SEG0 0x00014000 |
841 | #define UMC_BASE__INST0_SEG1 0 |
842 | #define UMC_BASE__INST0_SEG2 0 |
843 | #define UMC_BASE__INST0_SEG3 0 |
844 | #define UMC_BASE__INST0_SEG4 0 |
845 | #define UMC_BASE__INST0_SEG5 0 |
846 | |
847 | #define UMC_BASE__INST1_SEG0 0 |
848 | #define UMC_BASE__INST1_SEG1 0 |
849 | #define UMC_BASE__INST1_SEG2 0 |
850 | #define UMC_BASE__INST1_SEG3 0 |
851 | #define UMC_BASE__INST1_SEG4 0 |
852 | #define UMC_BASE__INST1_SEG5 0 |
853 | |
854 | #define UMC_BASE__INST2_SEG0 0 |
855 | #define UMC_BASE__INST2_SEG1 0 |
856 | #define UMC_BASE__INST2_SEG2 0 |
857 | #define UMC_BASE__INST2_SEG3 0 |
858 | #define UMC_BASE__INST2_SEG4 0 |
859 | #define UMC_BASE__INST2_SEG5 0 |
860 | |
861 | #define UMC_BASE__INST3_SEG0 0 |
862 | #define UMC_BASE__INST3_SEG1 0 |
863 | #define UMC_BASE__INST3_SEG2 0 |
864 | #define UMC_BASE__INST3_SEG3 0 |
865 | #define UMC_BASE__INST3_SEG4 0 |
866 | #define UMC_BASE__INST3_SEG5 0 |
867 | |
868 | #define UMC_BASE__INST4_SEG0 0 |
869 | #define UMC_BASE__INST4_SEG1 0 |
870 | #define UMC_BASE__INST4_SEG2 0 |
871 | #define UMC_BASE__INST4_SEG3 0 |
872 | #define UMC_BASE__INST4_SEG4 0 |
873 | #define UMC_BASE__INST4_SEG5 0 |
874 | |
875 | #define UMC_BASE__INST5_SEG0 0 |
876 | #define UMC_BASE__INST5_SEG1 0 |
877 | #define UMC_BASE__INST5_SEG2 0 |
878 | #define UMC_BASE__INST5_SEG3 0 |
879 | #define UMC_BASE__INST5_SEG4 0 |
880 | #define UMC_BASE__INST5_SEG5 0 |
881 | |
882 | #define UVD_BASE__INST0_SEG0 0x00007800 |
883 | #define UVD_BASE__INST0_SEG1 0x00007E00 |
884 | #define UVD_BASE__INST0_SEG2 0 |
885 | #define UVD_BASE__INST0_SEG3 0 |
886 | #define UVD_BASE__INST0_SEG4 0 |
887 | #define UVD_BASE__INST0_SEG5 0 |
888 | |
889 | #define UVD_BASE__INST1_SEG0 0 |
890 | #define UVD_BASE__INST1_SEG1 0x00009000 |
891 | #define UVD_BASE__INST1_SEG2 0 |
892 | #define UVD_BASE__INST1_SEG3 0 |
893 | #define UVD_BASE__INST1_SEG4 0 |
894 | #define UVD_BASE__INST1_SEG5 0 |
895 | |
896 | #define UVD_BASE__INST2_SEG0 0 |
897 | #define UVD_BASE__INST2_SEG1 0 |
898 | #define UVD_BASE__INST2_SEG2 0 |
899 | #define UVD_BASE__INST2_SEG3 0 |
900 | #define UVD_BASE__INST2_SEG4 0 |
901 | #define UVD_BASE__INST2_SEG5 0 |
902 | |
903 | #define UVD_BASE__INST3_SEG0 0 |
904 | #define UVD_BASE__INST3_SEG1 0 |
905 | #define UVD_BASE__INST3_SEG2 0 |
906 | #define UVD_BASE__INST3_SEG3 0 |
907 | #define UVD_BASE__INST3_SEG4 0 |
908 | #define UVD_BASE__INST3_SEG5 0 |
909 | |
910 | #define UVD_BASE__INST4_SEG0 0 |
911 | #define UVD_BASE__INST4_SEG1 0 |
912 | #define UVD_BASE__INST4_SEG2 0 |
913 | #define UVD_BASE__INST4_SEG3 0 |
914 | #define UVD_BASE__INST4_SEG4 0 |
915 | #define UVD_BASE__INST4_SEG5 0 |
916 | |
917 | #define UVD_BASE__INST5_SEG0 0 |
918 | #define UVD_BASE__INST5_SEG1 0 |
919 | #define UVD_BASE__INST5_SEG2 0 |
920 | #define UVD_BASE__INST5_SEG3 0 |
921 | #define UVD_BASE__INST5_SEG4 0 |
922 | #define UVD_BASE__INST5_SEG5 0 |
923 | |
924 | #define VCE_BASE__INST0_SEG0 0x00008800 |
925 | #define VCE_BASE__INST0_SEG1 0 |
926 | #define VCE_BASE__INST0_SEG2 0 |
927 | #define VCE_BASE__INST0_SEG3 0 |
928 | #define VCE_BASE__INST0_SEG4 0 |
929 | #define VCE_BASE__INST0_SEG5 0 |
930 | |
931 | #define VCE_BASE__INST1_SEG0 0 |
932 | #define VCE_BASE__INST1_SEG1 0 |
933 | #define VCE_BASE__INST1_SEG2 0 |
934 | #define VCE_BASE__INST1_SEG3 0 |
935 | #define VCE_BASE__INST1_SEG4 0 |
936 | #define VCE_BASE__INST1_SEG5 0 |
937 | |
938 | #define VCE_BASE__INST2_SEG0 0 |
939 | #define VCE_BASE__INST2_SEG1 0 |
940 | #define VCE_BASE__INST2_SEG2 0 |
941 | #define VCE_BASE__INST2_SEG3 0 |
942 | #define VCE_BASE__INST2_SEG4 0 |
943 | #define VCE_BASE__INST2_SEG5 0 |
944 | |
945 | #define VCE_BASE__INST3_SEG0 0 |
946 | #define VCE_BASE__INST3_SEG1 0 |
947 | #define VCE_BASE__INST3_SEG2 0 |
948 | #define VCE_BASE__INST3_SEG3 0 |
949 | #define VCE_BASE__INST3_SEG4 0 |
950 | #define VCE_BASE__INST3_SEG5 0 |
951 | |
952 | #define VCE_BASE__INST4_SEG0 0 |
953 | #define VCE_BASE__INST4_SEG1 0 |
954 | #define VCE_BASE__INST4_SEG2 0 |
955 | #define VCE_BASE__INST4_SEG3 0 |
956 | #define VCE_BASE__INST4_SEG4 0 |
957 | #define VCE_BASE__INST4_SEG5 0 |
958 | |
959 | #define VCE_BASE__INST5_SEG0 0 |
960 | #define VCE_BASE__INST5_SEG1 0 |
961 | #define VCE_BASE__INST5_SEG2 0 |
962 | #define VCE_BASE__INST5_SEG3 0 |
963 | #define VCE_BASE__INST5_SEG4 0 |
964 | #define VCE_BASE__INST5_SEG5 0 |
965 | |
966 | #define XDMA_BASE__INST0_SEG0 0x00003400 |
967 | #define XDMA_BASE__INST0_SEG1 0 |
968 | #define XDMA_BASE__INST0_SEG2 0 |
969 | #define XDMA_BASE__INST0_SEG3 0 |
970 | #define XDMA_BASE__INST0_SEG4 0 |
971 | #define XDMA_BASE__INST0_SEG5 0 |
972 | |
973 | #define XDMA_BASE__INST1_SEG0 0 |
974 | #define XDMA_BASE__INST1_SEG1 0 |
975 | #define XDMA_BASE__INST1_SEG2 0 |
976 | #define XDMA_BASE__INST1_SEG3 0 |
977 | #define XDMA_BASE__INST1_SEG4 0 |
978 | #define XDMA_BASE__INST1_SEG5 0 |
979 | |
980 | #define XDMA_BASE__INST2_SEG0 0 |
981 | #define XDMA_BASE__INST2_SEG1 0 |
982 | #define XDMA_BASE__INST2_SEG2 0 |
983 | #define XDMA_BASE__INST2_SEG3 0 |
984 | #define XDMA_BASE__INST2_SEG4 0 |
985 | #define XDMA_BASE__INST2_SEG5 0 |
986 | |
987 | #define XDMA_BASE__INST3_SEG0 0 |
988 | #define XDMA_BASE__INST3_SEG1 0 |
989 | #define XDMA_BASE__INST3_SEG2 0 |
990 | #define XDMA_BASE__INST3_SEG3 0 |
991 | #define XDMA_BASE__INST3_SEG4 0 |
992 | #define XDMA_BASE__INST3_SEG5 0 |
993 | |
994 | #define XDMA_BASE__INST4_SEG0 0 |
995 | #define XDMA_BASE__INST4_SEG1 0 |
996 | #define XDMA_BASE__INST4_SEG2 0 |
997 | #define XDMA_BASE__INST4_SEG3 0 |
998 | #define XDMA_BASE__INST4_SEG4 0 |
999 | #define XDMA_BASE__INST4_SEG5 0 |
1000 | |
1001 | #define XDMA_BASE__INST5_SEG0 0 |
1002 | #define XDMA_BASE__INST5_SEG1 0 |
1003 | #define XDMA_BASE__INST5_SEG2 0 |
1004 | #define XDMA_BASE__INST5_SEG3 0 |
1005 | #define XDMA_BASE__INST5_SEG4 0 |
1006 | #define XDMA_BASE__INST5_SEG5 0 |
1007 | |
1008 | #define RSMU_BASE__INST0_SEG0 0x00012000 |
1009 | #define RSMU_BASE__INST0_SEG1 0 |
1010 | #define RSMU_BASE__INST0_SEG2 0 |
1011 | #define RSMU_BASE__INST0_SEG3 0 |
1012 | #define RSMU_BASE__INST0_SEG4 0 |
1013 | #define RSMU_BASE__INST0_SEG5 0 |
1014 | |
1015 | #define RSMU_BASE__INST1_SEG0 0 |
1016 | #define RSMU_BASE__INST1_SEG1 0 |
1017 | #define RSMU_BASE__INST1_SEG2 0 |
1018 | #define RSMU_BASE__INST1_SEG3 0 |
1019 | #define RSMU_BASE__INST1_SEG4 0 |
1020 | #define RSMU_BASE__INST1_SEG5 0 |
1021 | |
1022 | #define RSMU_BASE__INST2_SEG0 0 |
1023 | #define RSMU_BASE__INST2_SEG1 0 |
1024 | #define RSMU_BASE__INST2_SEG2 0 |
1025 | #define RSMU_BASE__INST2_SEG3 0 |
1026 | #define RSMU_BASE__INST2_SEG4 0 |
1027 | #define RSMU_BASE__INST2_SEG5 0 |
1028 | |
1029 | #define RSMU_BASE__INST3_SEG0 0 |
1030 | #define RSMU_BASE__INST3_SEG1 0 |
1031 | #define RSMU_BASE__INST3_SEG2 0 |
1032 | #define RSMU_BASE__INST3_SEG3 0 |
1033 | #define RSMU_BASE__INST3_SEG4 0 |
1034 | #define RSMU_BASE__INST3_SEG5 0 |
1035 | |
1036 | #define RSMU_BASE__INST4_SEG0 0 |
1037 | #define RSMU_BASE__INST4_SEG1 0 |
1038 | #define RSMU_BASE__INST4_SEG2 0 |
1039 | #define RSMU_BASE__INST4_SEG3 0 |
1040 | #define RSMU_BASE__INST4_SEG4 0 |
1041 | #define RSMU_BASE__INST4_SEG5 0 |
1042 | |
1043 | #define RSMU_BASE__INST5_SEG0 0 |
1044 | #define RSMU_BASE__INST5_SEG1 0 |
1045 | #define RSMU_BASE__INST5_SEG2 0 |
1046 | #define RSMU_BASE__INST5_SEG3 0 |
1047 | #define RSMU_BASE__INST5_SEG4 0 |
1048 | #define RSMU_BASE__INST5_SEG5 0 |
1049 | |
1050 | #endif |
1051 | |
1052 | |