1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "hardwaremanager.h"
29#include "hwmgr_ppt.h"
30#include "ppatomctrl.h"
31#include "power_state.h"
32#include "smu_helper.h"
33
34struct pp_hwmgr;
35struct phm_fan_speed_info;
36struct pp_atomctrl_voltage_table;
37
38#define VOLTAGE_SCALE 4
39#define VOLTAGE_VID_OFFSET_SCALE1 625
40#define VOLTAGE_VID_OFFSET_SCALE2 100
41
42enum DISPLAY_GAP {
43 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */
44 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */
45 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
46 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */
47};
48typedef enum DISPLAY_GAP DISPLAY_GAP;
49
50enum BACO_STATE {
51 BACO_STATE_OUT = 0,
52 BACO_STATE_IN,
53};
54
55struct vi_dpm_level {
56 bool enabled;
57 uint32_t value;
58 uint32_t param1;
59};
60
61struct vi_dpm_table {
62 uint32_t count;
63 struct vi_dpm_level dpm_level[1];
64};
65
66#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
67#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
68#define PCIE_PERF_REQ_GEN1 2
69#define PCIE_PERF_REQ_GEN2 3
70#define PCIE_PERF_REQ_GEN3 4
71
72enum PHM_BackEnd_Magic {
73 PHM_Dummy_Magic = 0xAA5555AA,
74 PHM_RV770_Magic = 0xDCBAABCD,
75 PHM_Kong_Magic = 0x239478DF,
76 PHM_NIslands_Magic = 0x736C494E,
77 PHM_Sumo_Magic = 0x8339FA11,
78 PHM_SIslands_Magic = 0x369431AC,
79 PHM_Trinity_Magic = 0x96751873,
80 PHM_CIslands_Magic = 0x38AC78B0,
81 PHM_Kv_Magic = 0xDCBBABC0,
82 PHM_VIslands_Magic = 0x20130307,
83 PHM_Cz_Magic = 0x67DCBA25,
84 PHM_Rv_Magic = 0x20161121
85};
86
87struct phm_set_power_state_input {
88 const struct pp_hw_power_state *pcurrent_state;
89 const struct pp_hw_power_state *pnew_state;
90};
91
92struct phm_clock_array {
93 uint32_t count;
94 uint32_t values[1];
95};
96
97struct phm_clock_voltage_dependency_record {
98 uint32_t clk;
99 uint32_t v;
100};
101
102struct phm_vceclock_voltage_dependency_record {
103 uint32_t ecclk;
104 uint32_t evclk;
105 uint32_t v;
106};
107
108struct phm_uvdclock_voltage_dependency_record {
109 uint32_t vclk;
110 uint32_t dclk;
111 uint32_t v;
112};
113
114struct phm_samuclock_voltage_dependency_record {
115 uint32_t samclk;
116 uint32_t v;
117};
118
119struct phm_acpclock_voltage_dependency_record {
120 uint32_t acpclk;
121 uint32_t v;
122};
123
124struct phm_clock_voltage_dependency_table {
125 uint32_t count; /* Number of entries. */
126 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
127};
128
129struct phm_phase_shedding_limits_record {
130 uint32_t Voltage;
131 uint32_t Sclk;
132 uint32_t Mclk;
133};
134
135struct phm_uvd_clock_voltage_dependency_record {
136 uint32_t vclk;
137 uint32_t dclk;
138 uint32_t v;
139};
140
141struct phm_uvd_clock_voltage_dependency_table {
142 uint8_t count;
143 struct phm_uvd_clock_voltage_dependency_record entries[1];
144};
145
146struct phm_acp_clock_voltage_dependency_record {
147 uint32_t acpclk;
148 uint32_t v;
149};
150
151struct phm_acp_clock_voltage_dependency_table {
152 uint32_t count;
153 struct phm_acp_clock_voltage_dependency_record entries[1];
154};
155
156struct phm_vce_clock_voltage_dependency_record {
157 uint32_t ecclk;
158 uint32_t evclk;
159 uint32_t v;
160};
161
162struct phm_phase_shedding_limits_table {
163 uint32_t count;
164 struct phm_phase_shedding_limits_record entries[1];
165};
166
167struct phm_vceclock_voltage_dependency_table {
168 uint8_t count; /* Number of entries. */
169 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
170};
171
172struct phm_uvdclock_voltage_dependency_table {
173 uint8_t count; /* Number of entries. */
174 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
175};
176
177struct phm_samuclock_voltage_dependency_table {
178 uint8_t count; /* Number of entries. */
179 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
180};
181
182struct phm_acpclock_voltage_dependency_table {
183 uint32_t count; /* Number of entries. */
184 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
185};
186
187struct phm_vce_clock_voltage_dependency_table {
188 uint8_t count;
189 struct phm_vce_clock_voltage_dependency_record entries[1];
190};
191
192struct pp_smumgr_func {
193 int (*smu_init)(struct pp_hwmgr *hwmgr);
194 int (*smu_fini)(struct pp_hwmgr *hwmgr);
195 int (*start_smu)(struct pp_hwmgr *hwmgr);
196 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
197 uint32_t firmware);
198 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
199 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
200 uint32_t firmware);
201 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
202 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
203 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
204 uint16_t msg, uint32_t parameter);
205 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
206 void **table);
207 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
208 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
209 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
210 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
211 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
212 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
213 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
214 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
215 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
216 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
217 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
218 uint32_t (*get_mac_definition)(uint32_t value);
219 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
220 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
221 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
222 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
223};
224
225struct pp_hwmgr_func {
226 int (*backend_init)(struct pp_hwmgr *hw_mgr);
227 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
228 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
229 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
230
231 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
232 struct pp_power_state *prequest_ps,
233 const struct pp_power_state *pcurrent_ps);
234
235 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
236
237 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
238 enum amd_dpm_forced_level level);
239
240 int (*dynamic_state_management_enable)(
241 struct pp_hwmgr *hw_mgr);
242 int (*dynamic_state_management_disable)(
243 struct pp_hwmgr *hw_mgr);
244
245 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
246 struct pp_hw_power_state *hw_ps);
247
248 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
249 unsigned long, struct pp_power_state *);
250 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
251 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
252 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
253 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
254 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
255 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
256 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
257 int (*power_state_set)(struct pp_hwmgr *hwmgr,
258 const void *state);
259 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
260 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
261 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
262 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
263 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
264 const uint32_t *msg_id);
265 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
266 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
267 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
268 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
269 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
270 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
271 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
272 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
273 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
274 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
275 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
276 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
277 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
278 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
279 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
280 const struct pp_hw_power_state *pstate1,
281 const struct pp_hw_power_state *pstate2,
282 bool *equal);
283 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
284 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
285 bool cc6_disable, bool pstate_disable,
286 bool pstate_switch_disable);
287 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
288 struct amd_pp_simple_clock_info *info);
289 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
290 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
291 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
292 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
293 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
294 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
295 enum amd_pp_clock_type type,
296 struct pp_clock_levels_with_latency *clocks);
297 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
298 enum amd_pp_clock_type type,
299 struct pp_clock_levels_with_voltage *clocks);
300 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
301 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
302 struct pp_display_clock_request *clock);
303 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
304 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
305 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
306 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
307 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
308 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
309 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
310 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
311 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
312 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
313 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
314 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
315 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
316 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
317 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
318 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
319 uint32_t virtual_addr_low,
320 uint32_t virtual_addr_hi,
321 uint32_t mc_addr_low,
322 uint32_t mc_addr_hi,
323 uint32_t size);
324 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
325 bool enable,
326 bool lock);
327 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
328 struct PP_TemperatureRange *range);
329 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
330 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
331 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
332 enum PP_OD_DPM_TABLE_COMMAND type,
333 long *input, uint32_t size);
334 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
335 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
336 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
337 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
338 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
339 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
340 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
341 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
342 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
343 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
344 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
345 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
346};
347
348struct pp_table_func {
349 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
350 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
351 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
352 int (*pptable_get_vce_state_table_entry)(
353 struct pp_hwmgr *hwmgr,
354 unsigned long i,
355 struct amd_vce_state *vce_state,
356 void **clock_info,
357 unsigned long *flag);
358};
359
360union phm_cac_leakage_record {
361 struct {
362 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */
363 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */
364 };
365 struct {
366 uint16_t Vddc1;
367 uint16_t Vddc2;
368 uint16_t Vddc3;
369 };
370};
371
372struct phm_cac_leakage_table {
373 uint32_t count;
374 union phm_cac_leakage_record entries[1];
375};
376
377struct phm_samu_clock_voltage_dependency_record {
378 uint32_t samclk;
379 uint32_t v;
380};
381
382
383struct phm_samu_clock_voltage_dependency_table {
384 uint8_t count;
385 struct phm_samu_clock_voltage_dependency_record entries[1];
386};
387
388struct phm_cac_tdp_table {
389 uint16_t usTDP;
390 uint16_t usConfigurableTDP;
391 uint16_t usTDC;
392 uint16_t usBatteryPowerLimit;
393 uint16_t usSmallPowerLimit;
394 uint16_t usLowCACLeakage;
395 uint16_t usHighCACLeakage;
396 uint16_t usMaximumPowerDeliveryLimit;
397 uint16_t usEDCLimit;
398 uint16_t usOperatingTempMinLimit;
399 uint16_t usOperatingTempMaxLimit;
400 uint16_t usOperatingTempStep;
401 uint16_t usOperatingTempHyst;
402 uint16_t usDefaultTargetOperatingTemp;
403 uint16_t usTargetOperatingTemp;
404 uint16_t usPowerTuneDataSetID;
405 uint16_t usSoftwareShutdownTemp;
406 uint16_t usClockStretchAmount;
407 uint16_t usTemperatureLimitHotspot;
408 uint16_t usTemperatureLimitLiquid1;
409 uint16_t usTemperatureLimitLiquid2;
410 uint16_t usTemperatureLimitVrVddc;
411 uint16_t usTemperatureLimitVrMvdd;
412 uint16_t usTemperatureLimitPlx;
413 uint8_t ucLiquid1_I2C_address;
414 uint8_t ucLiquid2_I2C_address;
415 uint8_t ucLiquid_I2C_Line;
416 uint8_t ucVr_I2C_address;
417 uint8_t ucVr_I2C_Line;
418 uint8_t ucPlx_I2C_address;
419 uint8_t ucPlx_I2C_Line;
420 uint32_t usBoostPowerLimit;
421 uint8_t ucCKS_LDO_REFSEL;
422};
423
424struct phm_tdp_table {
425 uint16_t usTDP;
426 uint16_t usConfigurableTDP;
427 uint16_t usTDC;
428 uint16_t usBatteryPowerLimit;
429 uint16_t usSmallPowerLimit;
430 uint16_t usLowCACLeakage;
431 uint16_t usHighCACLeakage;
432 uint16_t usMaximumPowerDeliveryLimit;
433 uint16_t usEDCLimit;
434 uint16_t usOperatingTempMinLimit;
435 uint16_t usOperatingTempMaxLimit;
436 uint16_t usOperatingTempStep;
437 uint16_t usOperatingTempHyst;
438 uint16_t usDefaultTargetOperatingTemp;
439 uint16_t usTargetOperatingTemp;
440 uint16_t usPowerTuneDataSetID;
441 uint16_t usSoftwareShutdownTemp;
442 uint16_t usClockStretchAmount;
443 uint16_t usTemperatureLimitTedge;
444 uint16_t usTemperatureLimitHotspot;
445 uint16_t usTemperatureLimitLiquid1;
446 uint16_t usTemperatureLimitLiquid2;
447 uint16_t usTemperatureLimitHBM;
448 uint16_t usTemperatureLimitVrVddc;
449 uint16_t usTemperatureLimitVrMvdd;
450 uint16_t usTemperatureLimitPlx;
451 uint8_t ucLiquid1_I2C_address;
452 uint8_t ucLiquid2_I2C_address;
453 uint8_t ucLiquid_I2C_Line;
454 uint8_t ucVr_I2C_address;
455 uint8_t ucVr_I2C_Line;
456 uint8_t ucPlx_I2C_address;
457 uint8_t ucPlx_I2C_Line;
458 uint8_t ucLiquid_I2C_LineSDA;
459 uint8_t ucVr_I2C_LineSDA;
460 uint8_t ucPlx_I2C_LineSDA;
461 uint32_t usBoostPowerLimit;
462 uint16_t usBoostStartTemperature;
463 uint16_t usBoostStopTemperature;
464 uint32_t ulBoostClock;
465};
466
467struct phm_ppm_table {
468 uint8_t ppm_design;
469 uint16_t cpu_core_number;
470 uint32_t platform_tdp;
471 uint32_t small_ac_platform_tdp;
472 uint32_t platform_tdc;
473 uint32_t small_ac_platform_tdc;
474 uint32_t apu_tdp;
475 uint32_t dgpu_tdp;
476 uint32_t dgpu_ulv_power;
477 uint32_t tj_max;
478};
479
480struct phm_vq_budgeting_record {
481 uint32_t ulCUs;
482 uint32_t ulSustainableSOCPowerLimitLow;
483 uint32_t ulSustainableSOCPowerLimitHigh;
484 uint32_t ulMinSclkLow;
485 uint32_t ulMinSclkHigh;
486 uint8_t ucDispConfig;
487 uint32_t ulDClk;
488 uint32_t ulEClk;
489 uint32_t ulSustainableSclk;
490 uint32_t ulSustainableCUs;
491};
492
493struct phm_vq_budgeting_table {
494 uint8_t numEntries;
495 struct phm_vq_budgeting_record entries[1];
496};
497
498struct phm_clock_and_voltage_limits {
499 uint32_t sclk;
500 uint32_t mclk;
501 uint32_t gfxclk;
502 uint16_t vddc;
503 uint16_t vddci;
504 uint16_t vddgfx;
505 uint16_t vddmem;
506};
507
508/* Structure to hold PPTable information */
509
510struct phm_ppt_v1_information {
511 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
512 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
513 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
514 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
515 struct phm_clock_array *valid_sclk_values;
516 struct phm_clock_array *valid_mclk_values;
517 struct phm_clock_array *valid_socclk_values;
518 struct phm_clock_array *valid_dcefclk_values;
519 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
520 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
521 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
522 struct phm_ppm_table *ppm_parameter_table;
523 struct phm_cac_tdp_table *cac_dtp_table;
524 struct phm_tdp_table *tdp_table;
525 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
526 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
527 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
528 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
529 struct phm_ppt_v1_pcie_table *pcie_table;
530 struct phm_ppt_v1_gpio_table *gpio_table;
531 uint16_t us_ulv_voltage_offset;
532 uint16_t us_ulv_smnclk_did;
533 uint16_t us_ulv_mp1clk_did;
534 uint16_t us_ulv_gfxclk_bypass;
535 uint16_t us_gfxclk_slew_rate;
536 uint16_t us_min_gfxclk_freq_limit;
537};
538
539struct phm_ppt_v2_information {
540 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
541 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
542 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
543 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
544 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
545 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
546 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
547 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
548
549 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
550
551 struct phm_clock_array *valid_sclk_values;
552 struct phm_clock_array *valid_mclk_values;
553 struct phm_clock_array *valid_socclk_values;
554 struct phm_clock_array *valid_dcefclk_values;
555
556 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
557 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
558
559 struct phm_ppm_table *ppm_parameter_table;
560 struct phm_cac_tdp_table *cac_dtp_table;
561 struct phm_tdp_table *tdp_table;
562
563 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
564 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
565 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
566 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
567
568 struct phm_ppt_v1_pcie_table *pcie_table;
569
570 uint16_t us_ulv_voltage_offset;
571 uint16_t us_ulv_smnclk_did;
572 uint16_t us_ulv_mp1clk_did;
573 uint16_t us_ulv_gfxclk_bypass;
574 uint16_t us_gfxclk_slew_rate;
575 uint16_t us_min_gfxclk_freq_limit;
576
577 uint8_t uc_gfx_dpm_voltage_mode;
578 uint8_t uc_soc_dpm_voltage_mode;
579 uint8_t uc_uclk_dpm_voltage_mode;
580 uint8_t uc_uvd_dpm_voltage_mode;
581 uint8_t uc_vce_dpm_voltage_mode;
582 uint8_t uc_mp0_dpm_voltage_mode;
583 uint8_t uc_dcef_dpm_voltage_mode;
584};
585
586struct phm_ppt_v3_information
587{
588 uint8_t uc_thermal_controller_type;
589
590 uint16_t us_small_power_limit1;
591 uint16_t us_small_power_limit2;
592 uint16_t us_boost_power_limit;
593
594 uint16_t us_od_turbo_power_limit;
595 uint16_t us_od_powersave_power_limit;
596 uint16_t us_software_shutdown_temp;
597
598 uint32_t *power_saving_clock_max;
599 uint32_t *power_saving_clock_min;
600
601 uint8_t *od_feature_capabilities;
602 uint32_t *od_settings_max;
603 uint32_t *od_settings_min;
604
605 void *smc_pptable;
606};
607
608struct phm_dynamic_state_info {
609 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
610 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
611 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
612 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
613 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
614 struct phm_clock_array *valid_sclk_values;
615 struct phm_clock_array *valid_mclk_values;
616 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
617 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
618 uint32_t mclk_sclk_ratio;
619 uint32_t sclk_mclk_delta;
620 uint32_t vddc_vddci_delta;
621 uint32_t min_vddc_for_pcie_gen2;
622 struct phm_cac_leakage_table *cac_leakage_table;
623 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
624
625 struct phm_vce_clock_voltage_dependency_table
626 *vce_clock_voltage_dependency_table;
627 struct phm_uvd_clock_voltage_dependency_table
628 *uvd_clock_voltage_dependency_table;
629 struct phm_acp_clock_voltage_dependency_table
630 *acp_clock_voltage_dependency_table;
631 struct phm_samu_clock_voltage_dependency_table
632 *samu_clock_voltage_dependency_table;
633
634 struct phm_ppm_table *ppm_parameter_table;
635 struct phm_cac_tdp_table *cac_dtp_table;
636 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
637};
638
639struct pp_fan_info {
640 bool bNoFan;
641 uint8_t ucTachometerPulsesPerRevolution;
642 uint32_t ulMinRPM;
643 uint32_t ulMaxRPM;
644};
645
646struct pp_advance_fan_control_parameters {
647 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
648 uint16_t usTMed; /* The middle temperature where we change slopes. */
649 uint16_t usTHigh; /* The high temperature for setting the second slope. */
650 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
651 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */
652 uint16_t usPWMHigh; /* The PWM value at THigh. */
653 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */
654 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */
655 uint16_t usTMax; /* The max temperature */
656 uint8_t ucFanControlMode;
657 uint16_t usFanPWMMinLimit;
658 uint16_t usFanPWMMaxLimit;
659 uint16_t usFanPWMStep;
660 uint16_t usDefaultMaxFanPWM;
661 uint16_t usFanOutputSensitivity;
662 uint16_t usDefaultFanOutputSensitivity;
663 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */
664 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
665 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */
666 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */
667 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
668 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
669 uint16_t usFanCurrentLow; /* Low current */
670 uint16_t usFanCurrentHigh; /* High current */
671 uint16_t usFanRPMLow; /* Low RPM */
672 uint16_t usFanRPMHigh; /* High RPM */
673 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
674 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */
675 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */
676 uint16_t usFanGainEdge; /* The following is added for Fiji */
677 uint16_t usFanGainHotspot;
678 uint16_t usFanGainLiquid;
679 uint16_t usFanGainVrVddc;
680 uint16_t usFanGainVrMvdd;
681 uint16_t usFanGainPlx;
682 uint16_t usFanGainHbm;
683 uint8_t ucEnableZeroRPM;
684 uint8_t ucFanStopTemperature;
685 uint8_t ucFanStartTemperature;
686 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
687 uint32_t ulTargetGfxClk;
688 uint16_t usZeroRPMStartTemperature;
689 uint16_t usZeroRPMStopTemperature;
690 uint16_t usMGpuThrottlingRPMLimit;
691};
692
693struct pp_thermal_controller_info {
694 uint8_t ucType;
695 uint8_t ucI2cLine;
696 uint8_t ucI2cAddress;
697 struct pp_fan_info fanInfo;
698 struct pp_advance_fan_control_parameters advanceFanControlParameters;
699};
700
701struct phm_microcode_version_info {
702 uint32_t SMC;
703 uint32_t DMCU;
704 uint32_t MC;
705 uint32_t NB;
706};
707
708enum PP_TABLE_VERSION {
709 PP_TABLE_V0 = 0,
710 PP_TABLE_V1,
711 PP_TABLE_V2,
712 PP_TABLE_MAX
713};
714
715/**
716 * The main hardware manager structure.
717 */
718#define Workload_Policy_Max 6
719
720struct pp_hwmgr {
721 void *adev;
722 uint32_t chip_family;
723 uint32_t chip_id;
724 uint32_t smu_version;
725 bool not_vf;
726 bool pm_en;
727 struct mutex smu_lock;
728
729 uint32_t pp_table_version;
730 void *device;
731 struct pp_smumgr *smumgr;
732 const void *soft_pp_table;
733 uint32_t soft_pp_table_size;
734 void *hardcode_pp_table;
735 bool need_pp_table_upload;
736
737 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
738 uint32_t num_vce_state_tables;
739
740 enum amd_dpm_forced_level dpm_level;
741 enum amd_dpm_forced_level saved_dpm_level;
742 enum amd_dpm_forced_level request_dpm_level;
743 uint32_t usec_timeout;
744 void *pptable;
745 struct phm_platform_descriptor platform_descriptor;
746 void *backend;
747
748 void *smu_backend;
749 const struct pp_smumgr_func *smumgr_funcs;
750 bool is_kicker;
751
752 enum PP_DAL_POWERLEVEL dal_power_level;
753 struct phm_dynamic_state_info dyn_state;
754 const struct pp_hwmgr_func *hwmgr_func;
755 const struct pp_table_func *pptable_func;
756
757 struct pp_power_state *ps;
758 uint32_t num_ps;
759 struct pp_thermal_controller_info thermal_controller;
760 bool fan_ctrl_is_in_default_mode;
761 uint32_t fan_ctrl_default_mode;
762 bool fan_ctrl_enabled;
763 uint32_t tmin;
764 struct phm_microcode_version_info microcode_version_info;
765 uint32_t ps_size;
766 struct pp_power_state *current_ps;
767 struct pp_power_state *request_ps;
768 struct pp_power_state *boot_ps;
769 struct pp_power_state *uvd_ps;
770 const struct amd_pp_display_configuration *display_config;
771 uint32_t feature_mask;
772 bool avfs_supported;
773 /* UMD Pstate */
774 bool en_umd_pstate;
775 uint32_t power_profile_mode;
776 uint32_t default_power_profile_mode;
777 uint32_t pstate_sclk;
778 uint32_t pstate_mclk;
779 bool od_enabled;
780 uint32_t power_limit;
781 uint32_t default_power_limit;
782 uint32_t workload_mask;
783 uint32_t workload_prority[Workload_Policy_Max];
784 uint32_t workload_setting[Workload_Policy_Max];
785};
786
787int hwmgr_early_init(struct pp_hwmgr *hwmgr);
788int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
789int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
790int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
791int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
792int hwmgr_suspend(struct pp_hwmgr *hwmgr);
793int hwmgr_resume(struct pp_hwmgr *hwmgr);
794
795int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
796 enum amd_pp_task task_id,
797 enum amd_pm_state_type *user_state);
798
799
800#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
801
802
803#endif /* _HWMGR_H_ */
804