1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "pp_debug.h"
25#include "smumgr.h"
26#include "smu7_dyn_defaults.h"
27#include "smu73.h"
28#include "smu_ucode_xfer_vi.h"
29#include "fiji_smumgr.h"
30#include "fiji_ppsmc.h"
31#include "smu73_discrete.h"
32#include "ppatomctrl.h"
33#include "smu/smu_7_1_3_d.h"
34#include "smu/smu_7_1_3_sh_mask.h"
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37#include "oss/oss_3_0_d.h"
38#include "gca/gfx_8_0_d.h"
39#include "bif/bif_5_0_d.h"
40#include "bif/bif_5_0_sh_mask.h"
41#include "dce/dce_10_0_d.h"
42#include "dce/dce_10_0_sh_mask.h"
43#include "hardwaremanager.h"
44#include "cgs_common.h"
45#include "atombios.h"
46#include "pppcielanes.h"
47#include "hwmgr.h"
48#include "smu7_hwmgr.h"
49
50
51#define AVFS_EN_MSB 1568
52#define AVFS_EN_LSB 1568
53
54#define FIJI_SMC_SIZE 0x20000
55
56#define POWERTUNE_DEFAULT_SET_MAX 1
57#define VDDC_VDDCI_DELTA 300
58#define MC_CG_ARB_FREQ_F1 0x0b
59
60/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
61 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
62 */
63static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = {
64 {600, 1050, 3, 0}, {600, 1050, 6, 1} };
65
66/* [FF, SS] type, [] 4 voltage ranges, and
67 * [Floor Freq, Boundary Freq, VID min , VID max]
68 */
69static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {
70 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
71 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
72
73/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
74 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
75 */
76static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {
77 {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
78
79static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
80 /*sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
81 {1, 0xF, 0xFD,
82 /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
83 0x19, 5, 45}
84};
85
86static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
87 /* Min Sclk pcie DeepSleep Activity CgSpll CgSpll spllSpread SpllSpread CcPwr CcPwr Sclk Display Enabled Enabled Voltage Power */
88 /* Voltage, Frequency, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, Spectrum, Spectrum2, DynRm, DynRm1 Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
89 { 0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000, 0, 0, 0x16, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
90 { 0xa00fd047, 0x409c0000, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000, 0, 0, 0x16, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
91 { 0x0410d047, 0x50c30000, 0x01, 0x00, 0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000, 0, 0, 0x0e, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
92 { 0x6810d047, 0x60ea0000, 0x01, 0x00, 0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000, 0, 0, 0x0c, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
93 { 0xcc10d047, 0xe8fd0000, 0x01, 0x00, 0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000, 0, 0, 0x0c, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
94 { 0x3011d047, 0x70110100, 0x01, 0x00, 0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000, 0, 0, 0x0c, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
95 { 0x9411d047, 0xf8240100, 0x01, 0x00, 0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000, 0, 0, 0x0c, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 },
96 { 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
97};
98
99static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
100{
101 int result = 0;
102
103 /* Wait for smc boot up */
104 /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
105 RCU_UC_EVENTS, boot_seq_done, 0); */
106
107 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
108 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
109
110 result = smu7_upload_smu_firmware_image(hwmgr);
111 if (result)
112 return result;
113
114 /* Clear status */
115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
116 ixSMU_STATUS, 0);
117
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
120
121 /* De-assert reset */
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
123 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
124
125 /* Wait for ROM firmware to initialize interrupt hendler */
126 /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
127 SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
128
129 /* Set SMU Auto Start */
130 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
131 SMU_INPUT_DATA, AUTO_START, 1);
132
133 /* Clear firmware interrupt enable flag */
134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
135 ixFIRMWARE_FLAGS, 0);
136
137 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
138 INTERRUPTS_ENABLED, 1);
139
140 cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
141 cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
142 PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
143
144 /* Wait for done bit to be set */
145 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
146 SMU_STATUS, SMU_DONE, 0);
147
148 /* Check pass/failed indicator */
149 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
150 SMU_STATUS, SMU_PASS) != 1) {
151 PP_ASSERT_WITH_CODE(false,
152 "SMU Firmware start failed!", return -1);
153 }
154
155 /* Wait for firmware to initialize */
156 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
157 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
158
159 return result;
160}
161
162static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
163{
164 int result = 0;
165
166 /* wait for smc boot up */
167 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
168 RCU_UC_EVENTS, boot_seq_done, 0);
169
170 /* Clear firmware interrupt enable flag */
171 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
172 ixFIRMWARE_FLAGS, 0);
173
174 /* Assert reset */
175 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
176 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
177
178 result = smu7_upload_smu_firmware_image(hwmgr);
179 if (result)
180 return result;
181
182 /* Set smc instruct start point at 0x0 */
183 smu7_program_jump_on_start(hwmgr);
184
185 /* Enable clock */
186 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
187 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
188
189 /* De-assert reset */
190 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
191 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
192
193 /* Wait for firmware to initialize */
194 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
195 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
196
197 return result;
198}
199
200static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
201{
202 int result = 0;
203 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
204
205 if (0 != smu_data->avfs_btc_param) {
206 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
207 PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
208 pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
209 result = -EINVAL;
210 }
211 }
212 /* Soft-Reset to reset the engine before loading uCode */
213 /* halt */
214 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
215 /* reset everything */
216 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
217 /* clear reset */
218 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
219
220 return result;
221}
222
223static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
224{
225 int32_t vr_config;
226 uint32_t table_start;
227 uint32_t level_addr, vr_config_addr;
228 uint32_t level_size = sizeof(avfs_graphics_level);
229
230 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
231 SMU7_FIRMWARE_HEADER_LOCATION +
232 offsetof(SMU73_Firmware_Header, DpmTable),
233 &table_start, 0x40000),
234 "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not "
235 "communicate starting address of DPM table",
236 return -1;);
237
238 /* Default value for vr_config =
239 * VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
240 vr_config = 0x01000500; /* Real value:0x50001 */
241
242 vr_config_addr = table_start +
243 offsetof(SMU73_Discrete_DpmTable, VRConfig);
244
245 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
246 (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
247 "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
248 "vr_config value over to SMC",
249 return -1;);
250
251 level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
252
253 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
254 (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
255 "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
256 return -1;);
257
258 return 0;
259}
260
261static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr)
262{
263 if (!hwmgr->avfs_supported)
264 return 0;
265
266 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
267 "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
268 " table over to SMU",
269 return -EINVAL);
270 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
271 "[AVFS][fiji_avfs_event_mgr] Could not setup "
272 "Pwr Virus for AVFS ",
273 return -EINVAL);
274 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
275 "[AVFS][fiji_avfs_event_mgr] Failure at "
276 "fiji_start_avfs_btc. AVFS Disabled",
277 return -EINVAL);
278
279 return 0;
280}
281
282static int fiji_start_smu(struct pp_hwmgr *hwmgr)
283{
284 int result = 0;
285 struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
286
287 /* Only start SMC if SMC RAM is not running */
288 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
289 /* Check if SMU is running in protected mode */
290 if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
291 CGS_IND_REG__SMC,
292 SMU_FIRMWARE, SMU_MODE)) {
293 result = fiji_start_smu_in_non_protection_mode(hwmgr);
294 if (result)
295 return result;
296 } else {
297 result = fiji_start_smu_in_protection_mode(hwmgr);
298 if (result)
299 return result;
300 }
301 if (fiji_avfs_event_mgr(hwmgr))
302 hwmgr->avfs_supported = false;
303 }
304
305 /* Setup SoftRegsStart here for register lookup in case
306 * DummyBackEnd is used and ProcessFirmwareHeader is not executed
307 */
308 smu7_read_smc_sram_dword(hwmgr,
309 SMU7_FIRMWARE_HEADER_LOCATION +
310 offsetof(SMU73_Firmware_Header, SoftRegisters),
311 &(priv->smu7_data.soft_regs_start), 0x40000);
312
313 result = smu7_request_smu_load_fw(hwmgr);
314
315 return result;
316}
317
318static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
319{
320
321 uint32_t efuse = 0;
322 uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
323
324 if (!hwmgr->not_vf)
325 return false;
326
327 if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB,
328 mask, &efuse)) {
329 if (efuse)
330 return true;
331 }
332 return false;
333}
334
335static int fiji_smu_init(struct pp_hwmgr *hwmgr)
336{
337 struct fiji_smumgr *fiji_priv = NULL;
338
339 fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
340
341 if (fiji_priv == NULL)
342 return -ENOMEM;
343
344 hwmgr->smu_backend = fiji_priv;
345
346 if (smu7_init(hwmgr)) {
347 kfree(fiji_priv);
348 return -EINVAL;
349 }
350
351 return 0;
352}
353
354static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
355 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
356 uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
357{
358 uint32_t i;
359 uint16_t vddci;
360 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
361 *voltage = *mvdd = 0;
362
363
364 /* clock - voltage dependency table is empty table */
365 if (dep_table->count == 0)
366 return -EINVAL;
367
368 for (i = 0; i < dep_table->count; i++) {
369 /* find first sclk bigger than request */
370 if (dep_table->entries[i].clk >= clock) {
371 *voltage |= (dep_table->entries[i].vddc *
372 VOLTAGE_SCALE) << VDDC_SHIFT;
373 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
374 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
375 VOLTAGE_SCALE) << VDDCI_SHIFT;
376 else if (dep_table->entries[i].vddci)
377 *voltage |= (dep_table->entries[i].vddci *
378 VOLTAGE_SCALE) << VDDCI_SHIFT;
379 else {
380 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
381 (dep_table->entries[i].vddc -
382 VDDC_VDDCI_DELTA));
383 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
384 }
385
386 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
387 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
388 VOLTAGE_SCALE;
389 else if (dep_table->entries[i].mvdd)
390 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
391 VOLTAGE_SCALE;
392
393 *voltage |= 1 << PHASES_SHIFT;
394 return 0;
395 }
396 }
397
398 /* sclk is bigger than max sclk in the dependence table */
399 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
400
401 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
402 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
403 VOLTAGE_SCALE) << VDDCI_SHIFT;
404 else if (dep_table->entries[i-1].vddci) {
405 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
406 (dep_table->entries[i].vddc -
407 VDDC_VDDCI_DELTA));
408 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
409 }
410
411 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
412 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
413 else if (dep_table->entries[i].mvdd)
414 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
415
416 return 0;
417}
418
419
420static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
421{
422 uint32_t tmp;
423 tmp = raw_setting * 4096 / 100;
424 return (uint16_t)tmp;
425}
426
427static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
428{
429 switch (line) {
430 case SMU7_I2CLineID_DDC1:
431 *scl = SMU7_I2C_DDC1CLK;
432 *sda = SMU7_I2C_DDC1DATA;
433 break;
434 case SMU7_I2CLineID_DDC2:
435 *scl = SMU7_I2C_DDC2CLK;
436 *sda = SMU7_I2C_DDC2DATA;
437 break;
438 case SMU7_I2CLineID_DDC3:
439 *scl = SMU7_I2C_DDC3CLK;
440 *sda = SMU7_I2C_DDC3DATA;
441 break;
442 case SMU7_I2CLineID_DDC4:
443 *scl = SMU7_I2C_DDC4CLK;
444 *sda = SMU7_I2C_DDC4DATA;
445 break;
446 case SMU7_I2CLineID_DDC5:
447 *scl = SMU7_I2C_DDC5CLK;
448 *sda = SMU7_I2C_DDC5DATA;
449 break;
450 case SMU7_I2CLineID_DDC6:
451 *scl = SMU7_I2C_DDC6CLK;
452 *sda = SMU7_I2C_DDC6DATA;
453 break;
454 case SMU7_I2CLineID_SCLSDA:
455 *scl = SMU7_I2C_SCL;
456 *sda = SMU7_I2C_SDA;
457 break;
458 case SMU7_I2CLineID_DDCVGA:
459 *scl = SMU7_I2C_DDCVGACLK;
460 *sda = SMU7_I2C_DDCVGADATA;
461 break;
462 default:
463 *scl = 0;
464 *sda = 0;
465 break;
466 }
467}
468
469static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
470{
471 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
472 struct phm_ppt_v1_information *table_info =
473 (struct phm_ppt_v1_information *)(hwmgr->pptable);
474
475 if (table_info &&
476 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
477 table_info->cac_dtp_table->usPowerTuneDataSetID)
478 smu_data->power_tune_defaults =
479 &fiji_power_tune_data_set_array
480 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
481 else
482 smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
483
484}
485
486static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
487{
488
489 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
490 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
491
492 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
493
494 struct phm_ppt_v1_information *table_info =
495 (struct phm_ppt_v1_information *)(hwmgr->pptable);
496 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
497 struct pp_advance_fan_control_parameters *fan_table =
498 &hwmgr->thermal_controller.advanceFanControlParameters;
499 uint8_t uc_scl, uc_sda;
500
501 /* TDP number of fraction bits are changed from 8 to 7 for Fiji
502 * as requested by SMC team
503 */
504 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
505 (uint16_t)(cac_dtp_table->usTDP * 128));
506 dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
507 (uint16_t)(cac_dtp_table->usTDP * 128));
508
509 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
510 "Target Operating Temp is out of Range!",
511 );
512
513 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
514 dpm_table->GpuTjHyst = 8;
515
516 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
517
518 /* The following are for new Fiji Multi-input fan/thermal control */
519 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
520 cac_dtp_table->usTargetOperatingTemp * 256);
521 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
522 cac_dtp_table->usTemperatureLimitHotspot * 256);
523 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
524 cac_dtp_table->usTemperatureLimitLiquid1 * 256);
525 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
526 cac_dtp_table->usTemperatureLimitLiquid2 * 256);
527 dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
528 cac_dtp_table->usTemperatureLimitVrVddc * 256);
529 dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
530 cac_dtp_table->usTemperatureLimitVrMvdd * 256);
531 dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
532 cac_dtp_table->usTemperatureLimitPlx * 256);
533
534 dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
535 scale_fan_gain_settings(fan_table->usFanGainEdge));
536 dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
537 scale_fan_gain_settings(fan_table->usFanGainHotspot));
538 dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
539 scale_fan_gain_settings(fan_table->usFanGainLiquid));
540 dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
541 scale_fan_gain_settings(fan_table->usFanGainVrVddc));
542 dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
543 scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
544 dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
545 scale_fan_gain_settings(fan_table->usFanGainPlx));
546 dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
547 scale_fan_gain_settings(fan_table->usFanGainHbm));
548
549 dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
550 dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
551 dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
552 dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
553
554 get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
555 dpm_table->Liquid_I2C_LineSCL = uc_scl;
556 dpm_table->Liquid_I2C_LineSDA = uc_sda;
557
558 get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
559 dpm_table->Vr_I2C_LineSCL = uc_scl;
560 dpm_table->Vr_I2C_LineSDA = uc_sda;
561
562 get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
563 dpm_table->Plx_I2C_LineSCL = uc_scl;
564 dpm_table->Plx_I2C_LineSDA = uc_sda;
565
566 return 0;
567}
568
569
570static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
571{
572 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
573 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
574
575 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
576 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
577 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
578 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
579
580 return 0;
581}
582
583
584static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
585{
586 uint16_t tdc_limit;
587 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
588 struct phm_ppt_v1_information *table_info =
589 (struct phm_ppt_v1_information *)(hwmgr->pptable);
590 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
591
592 /* TDC number of fraction bits are changed from 8 to 7
593 * for Fiji as requested by SMC team
594 */
595 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
596 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
597 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
598 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
599 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
600 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
601
602 return 0;
603}
604
605static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
606{
607 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
608 const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
609 uint32_t temp;
610
611 if (smu7_read_smc_sram_dword(hwmgr,
612 fuse_table_offset +
613 offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
614 (uint32_t *)&temp, SMC_RAM_END))
615 PP_ASSERT_WITH_CODE(false,
616 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
617 return -EINVAL);
618 else {
619 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
620 smu_data->power_tune_table.LPMLTemperatureMin =
621 (uint8_t)((temp >> 16) & 0xff);
622 smu_data->power_tune_table.LPMLTemperatureMax =
623 (uint8_t)((temp >> 8) & 0xff);
624 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
625 }
626 return 0;
627}
628
629static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
630{
631 int i;
632 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
633
634 /* Currently not used. Set all to zero. */
635 for (i = 0; i < 16; i++)
636 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
637
638 return 0;
639}
640
641static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
642{
643 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
644
645 if ((hwmgr->thermal_controller.advanceFanControlParameters.
646 usFanOutputSensitivity & (1 << 15)) ||
647 0 == hwmgr->thermal_controller.advanceFanControlParameters.
648 usFanOutputSensitivity)
649 hwmgr->thermal_controller.advanceFanControlParameters.
650 usFanOutputSensitivity = hwmgr->thermal_controller.
651 advanceFanControlParameters.usDefaultFanOutputSensitivity;
652
653 smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
654 PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
655 advanceFanControlParameters.usFanOutputSensitivity);
656 return 0;
657}
658
659static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
660{
661 int i;
662 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
663
664 /* Currently not used. Set all to zero. */
665 for (i = 0; i < 16; i++)
666 smu_data->power_tune_table.GnbLPML[i] = 0;
667
668 return 0;
669}
670
671static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
672{
673 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
674 struct phm_ppt_v1_information *table_info =
675 (struct phm_ppt_v1_information *)(hwmgr->pptable);
676 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
677 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
678 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
679
680 HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
681 LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
682
683 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
684 CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
685 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
686 CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
687
688 return 0;
689}
690
691static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
692{
693 uint32_t pm_fuse_table_offset;
694 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
695
696 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
697 PHM_PlatformCaps_PowerContainment)) {
698 if (smu7_read_smc_sram_dword(hwmgr,
699 SMU7_FIRMWARE_HEADER_LOCATION +
700 offsetof(SMU73_Firmware_Header, PmFuseTable),
701 &pm_fuse_table_offset, SMC_RAM_END))
702 PP_ASSERT_WITH_CODE(false,
703 "Attempt to get pm_fuse_table_offset Failed!",
704 return -EINVAL);
705
706 /* DW6 */
707 if (fiji_populate_svi_load_line(hwmgr))
708 PP_ASSERT_WITH_CODE(false,
709 "Attempt to populate SviLoadLine Failed!",
710 return -EINVAL);
711 /* DW7 */
712 if (fiji_populate_tdc_limit(hwmgr))
713 PP_ASSERT_WITH_CODE(false,
714 "Attempt to populate TDCLimit Failed!", return -EINVAL);
715 /* DW8 */
716 if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
717 PP_ASSERT_WITH_CODE(false,
718 "Attempt to populate TdcWaterfallCtl, "
719 "LPMLTemperature Min and Max Failed!",
720 return -EINVAL);
721
722 /* DW9-DW12 */
723 if (0 != fiji_populate_temperature_scaler(hwmgr))
724 PP_ASSERT_WITH_CODE(false,
725 "Attempt to populate LPMLTemperatureScaler Failed!",
726 return -EINVAL);
727
728 /* DW13-DW14 */
729 if (fiji_populate_fuzzy_fan(hwmgr))
730 PP_ASSERT_WITH_CODE(false,
731 "Attempt to populate Fuzzy Fan Control parameters Failed!",
732 return -EINVAL);
733
734 /* DW15-DW18 */
735 if (fiji_populate_gnb_lpml(hwmgr))
736 PP_ASSERT_WITH_CODE(false,
737 "Attempt to populate GnbLPML Failed!",
738 return -EINVAL);
739
740 /* DW20 */
741 if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
742 PP_ASSERT_WITH_CODE(false,
743 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
744 "Sidd Failed!", return -EINVAL);
745
746 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
747 (uint8_t *)&smu_data->power_tune_table,
748 sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
749 PP_ASSERT_WITH_CODE(false,
750 "Attempt to download PmFuseTable Failed!",
751 return -EINVAL);
752 }
753 return 0;
754}
755
756static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
757 struct SMU73_Discrete_DpmTable *table)
758{
759 uint32_t count;
760 uint8_t index;
761 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
762 struct phm_ppt_v1_information *table_info =
763 (struct phm_ppt_v1_information *)(hwmgr->pptable);
764 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
765 table_info->vddc_lookup_table;
766 /* tables is already swapped, so in order to use the value from it,
767 * we need to swap it back.
768 * We are populating vddc CAC data to BapmVddc table
769 * in split and merged mode
770 */
771
772 for (count = 0; count < lookup_table->count; count++) {
773 index = phm_get_voltage_index(lookup_table,
774 data->vddc_voltage_table.entries[count].value);
775 table->BapmVddcVidLoSidd[count] =
776 convert_to_vid(lookup_table->entries[index].us_cac_low);
777 table->BapmVddcVidHiSidd[count] =
778 convert_to_vid(lookup_table->entries[index].us_cac_high);
779 }
780
781 return 0;
782}
783
784static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
785 struct SMU73_Discrete_DpmTable *table)
786{
787 int result;
788
789 result = fiji_populate_cac_table(hwmgr, table);
790 PP_ASSERT_WITH_CODE(0 == result,
791 "can not populate CAC voltage tables to SMC",
792 return -EINVAL);
793
794 return 0;
795}
796
797static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
798 struct SMU73_Discrete_Ulv *state)
799{
800 int result = 0;
801
802 struct phm_ppt_v1_information *table_info =
803 (struct phm_ppt_v1_information *)(hwmgr->pptable);
804
805 state->CcPwrDynRm = 0;
806 state->CcPwrDynRm1 = 0;
807
808 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
809 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
810 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
811
812 state->VddcPhase = 1;
813
814 if (!result) {
815 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
816 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
817 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
818 }
819 return result;
820}
821
822static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
823 struct SMU73_Discrete_DpmTable *table)
824{
825 return fiji_populate_ulv_level(hwmgr, &table->Ulv);
826}
827
828static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
829 struct SMU73_Discrete_DpmTable *table)
830{
831 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
832 struct smu7_dpm_table *dpm_table = &data->dpm_table;
833 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
834 int i;
835
836 /* Index (dpm_table->pcie_speed_table.count)
837 * is reserved for PCIE boot level. */
838 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
839 table->LinkLevel[i].PcieGenSpeed =
840 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
841 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
842 dpm_table->pcie_speed_table.dpm_levels[i].param1);
843 table->LinkLevel[i].EnabledForActivity = 1;
844 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
845 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
846 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
847 }
848
849 smu_data->smc_state_table.LinkLevelCount =
850 (uint8_t)dpm_table->pcie_speed_table.count;
851 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
852 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
853
854 return 0;
855}
856
857static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
858 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
859{
860 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
861 struct pp_atomctrl_clock_dividers_vi dividers;
862 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
863 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
864 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
865 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
866 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
867 uint32_t ref_clock;
868 uint32_t ref_divider;
869 uint32_t fbdiv;
870 int result;
871
872 /* get the engine clock dividers for this clock value */
873 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
874
875 PP_ASSERT_WITH_CODE(result == 0,
876 "Error retrieving Engine Clock dividers from VBIOS.",
877 return result);
878
879 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
880 ref_clock = atomctrl_get_reference_clock(hwmgr);
881 ref_divider = 1 + dividers.uc_pll_ref_div;
882
883 /* low 14 bits is fraction and high 12 bits is divider */
884 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
885
886 /* SPLL_FUNC_CNTL setup */
887 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
888 SPLL_REF_DIV, dividers.uc_pll_ref_div);
889 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
890 SPLL_PDIV_A, dividers.uc_pll_post_div);
891
892 /* SPLL_FUNC_CNTL_3 setup*/
893 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
894 SPLL_FB_DIV, fbdiv);
895
896 /* set to use fractional accumulation*/
897 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
898 SPLL_DITHEN, 1);
899
900 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
901 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
902 struct pp_atomctrl_internal_ss_info ssInfo;
903
904 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
905 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
906 vco_freq, &ssInfo)) {
907 /*
908 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
909 * ss_info.speed_spectrum_rate -- in unit of khz
910 *
911 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
912 */
913 uint32_t clk_s = ref_clock * 5 /
914 (ref_divider * ssInfo.speed_spectrum_rate);
915 /* clkv = 2 * D * fbdiv / NS */
916 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
917 fbdiv / (clk_s * 10000);
918
919 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
920 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
921 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
922 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
923 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
924 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
925 }
926 }
927
928 sclk->SclkFrequency = clock;
929 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
930 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
931 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
932 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
933 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
934
935 return 0;
936}
937
938static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
939 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)
940{
941 int result;
942 /* PP_Clocks minClocks; */
943 uint32_t threshold, mvdd;
944 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
945 struct phm_ppt_v1_information *table_info =
946 (struct phm_ppt_v1_information *)(hwmgr->pptable);
947 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
948
949 result = fiji_calculate_sclk_params(hwmgr, clock, level);
950
951 if (hwmgr->od_enabled)
952 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
953 else
954 vdd_dep_table = table_info->vdd_dep_on_sclk;
955
956 /* populate graphics levels */
957 result = fiji_get_dependency_volt_by_clk(hwmgr,
958 vdd_dep_table, clock,
959 (uint32_t *)(&level->MinVoltage), &mvdd);
960 PP_ASSERT_WITH_CODE((0 == result),
961 "can not find VDDC voltage value for "
962 "VDDC engine clock dependency table",
963 return result);
964
965 level->SclkFrequency = clock;
966 level->ActivityLevel = data->current_profile_setting.sclk_activity;
967 level->CcPwrDynRm = 0;
968 level->CcPwrDynRm1 = 0;
969 level->EnabledForActivity = 0;
970 level->EnabledForThrottle = 1;
971 level->UpHyst = data->current_profile_setting.sclk_up_hyst;
972 level->DownHyst = data->current_profile_setting.sclk_down_hyst;
973 level->VoltageDownHyst = 0;
974 level->PowerThrottle = 0;
975
976 threshold = clock * data->fast_watermark_threshold / 100;
977
978 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
979
980 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
981 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
982 hwmgr->display_config->min_core_set_clock_in_sr);
983
984
985 /* Default to slow, highest DPM level will be
986 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
987 */
988 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
989
990 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
991 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
992 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
993 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
994 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
995 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
996 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
997 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
998 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
999
1000 return 0;
1001}
1002
1003static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1004{
1005 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1006 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1007
1008 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1009 struct phm_ppt_v1_information *table_info =
1010 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1011 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1012 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1013 int result = 0;
1014 uint32_t array = smu_data->smu7_data.dpm_table_start +
1015 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1016 uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1017 SMU73_MAX_LEVELS_GRAPHICS;
1018 struct SMU73_Discrete_GraphicsLevel *levels =
1019 smu_data->smc_state_table.GraphicsLevel;
1020 uint32_t i, max_entry;
1021 uint8_t hightest_pcie_level_enabled = 0,
1022 lowest_pcie_level_enabled = 0,
1023 mid_pcie_level_enabled = 0,
1024 count = 0;
1025
1026 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1027 result = fiji_populate_single_graphic_level(hwmgr,
1028 dpm_table->sclk_table.dpm_levels[i].value,
1029 &levels[i]);
1030 if (result)
1031 return result;
1032
1033 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1034 if (i > 1)
1035 levels[i].DeepSleepDivId = 0;
1036 }
1037
1038 /* Only enable level 0 for now.*/
1039 levels[0].EnabledForActivity = 1;
1040
1041 /* set highest level watermark to high */
1042 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1043 PPSMC_DISPLAY_WATERMARK_HIGH;
1044
1045 smu_data->smc_state_table.GraphicsDpmLevelCount =
1046 (uint8_t)dpm_table->sclk_table.count;
1047 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1048 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1049
1050 if (pcie_table != NULL) {
1051 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1052 "There must be 1 or more PCIE levels defined in PPTable.",
1053 return -EINVAL);
1054 max_entry = pcie_entry_cnt - 1;
1055 for (i = 0; i < dpm_table->sclk_table.count; i++)
1056 levels[i].pcieDpmLevel =
1057 (uint8_t) ((i < max_entry) ? i : max_entry);
1058 } else {
1059 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1060 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1061 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1062 hightest_pcie_level_enabled++;
1063
1064 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1065 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1066 (1 << lowest_pcie_level_enabled)) == 0))
1067 lowest_pcie_level_enabled++;
1068
1069 while ((count < hightest_pcie_level_enabled) &&
1070 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1071 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1072 count++;
1073
1074 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1075 hightest_pcie_level_enabled ?
1076 (lowest_pcie_level_enabled + 1 + count) :
1077 hightest_pcie_level_enabled;
1078
1079 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1080 for (i = 2; i < dpm_table->sclk_table.count; i++)
1081 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1082
1083 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1084 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1085
1086 /* set pcieDpmLevel to mid_pcie_level_enabled */
1087 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1088 }
1089 /* level count will send to smc once at init smc table and never change */
1090 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1091 (uint32_t)array_size, SMC_RAM_END);
1092
1093 return result;
1094}
1095
1096
1097/**
1098 * MCLK Frequency Ratio
1099 * SEQ_CG_RESP Bit[31:24] - 0x0
1100 * Bit[27:24] \96 DDR3 Frequency ratio
1101 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
1102 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
1103 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
1104 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
1105 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
1106 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
1107 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
1108 * 400 < 0x7 <= 450MHz, 800 < 0xF
1109 */
1110static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
1111{
1112 if (mem_clock <= 10000)
1113 return 0x0;
1114 if (mem_clock <= 15000)
1115 return 0x1;
1116 if (mem_clock <= 20000)
1117 return 0x2;
1118 if (mem_clock <= 25000)
1119 return 0x3;
1120 if (mem_clock <= 30000)
1121 return 0x4;
1122 if (mem_clock <= 35000)
1123 return 0x5;
1124 if (mem_clock <= 40000)
1125 return 0x6;
1126 if (mem_clock <= 45000)
1127 return 0x7;
1128 if (mem_clock <= 50000)
1129 return 0x8;
1130 if (mem_clock <= 55000)
1131 return 0x9;
1132 if (mem_clock <= 60000)
1133 return 0xa;
1134 if (mem_clock <= 65000)
1135 return 0xb;
1136 if (mem_clock <= 70000)
1137 return 0xc;
1138 if (mem_clock <= 75000)
1139 return 0xd;
1140 if (mem_clock <= 80000)
1141 return 0xe;
1142 /* mem_clock > 800MHz */
1143 return 0xf;
1144}
1145
1146static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
1147 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
1148{
1149 struct pp_atomctrl_memory_clock_param mem_param;
1150 int result;
1151
1152 result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
1153 PP_ASSERT_WITH_CODE((0 == result),
1154 "Failed to get Memory PLL Dividers.",
1155 );
1156
1157 /* Save the result data to outpupt memory level structure */
1158 mclk->MclkFrequency = clock;
1159 mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
1160 mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
1161
1162 return result;
1163}
1164
1165static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1166 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
1167{
1168 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1169 struct phm_ppt_v1_information *table_info =
1170 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1171 int result = 0;
1172 uint32_t mclk_stutter_mode_threshold = 60000;
1173 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1174
1175 if (hwmgr->od_enabled)
1176 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1177 else
1178 vdd_dep_table = table_info->vdd_dep_on_mclk;
1179
1180 if (vdd_dep_table) {
1181 result = fiji_get_dependency_volt_by_clk(hwmgr,
1182 vdd_dep_table, clock,
1183 (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
1184 PP_ASSERT_WITH_CODE((0 == result),
1185 "can not find MinVddc voltage value from memory "
1186 "VDDC voltage dependency table", return result);
1187 }
1188
1189 mem_level->EnabledForThrottle = 1;
1190 mem_level->EnabledForActivity = 0;
1191 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1192 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1193 mem_level->VoltageDownHyst = 0;
1194 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1195 mem_level->StutterEnable = false;
1196
1197 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1198
1199 /* enable stutter mode if all the follow condition applied
1200 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
1201 * &(data->DisplayTiming.numExistingDisplays));
1202 */
1203 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1204 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1205
1206 if (mclk_stutter_mode_threshold &&
1207 (clock <= mclk_stutter_mode_threshold) &&
1208 (!data->is_uvd_enabled) &&
1209 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1210 STUTTER_ENABLE) & 0x1))
1211 mem_level->StutterEnable = true;
1212
1213 result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
1214 if (!result) {
1215 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1216 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1217 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1218 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1219 }
1220 return result;
1221}
1222
1223static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1224{
1225 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1226 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1227 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1228 int result;
1229 /* populate MCLK dpm table to SMU7 */
1230 uint32_t array = smu_data->smu7_data.dpm_table_start +
1231 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
1232 uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
1233 SMU73_MAX_LEVELS_MEMORY;
1234 struct SMU73_Discrete_MemoryLevel *levels =
1235 smu_data->smc_state_table.MemoryLevel;
1236 uint32_t i;
1237
1238 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1239 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1240 "can not populate memory level as memory clock is zero",
1241 return -EINVAL);
1242 result = fiji_populate_single_memory_level(hwmgr,
1243 dpm_table->mclk_table.dpm_levels[i].value,
1244 &levels[i]);
1245 if (result)
1246 return result;
1247 }
1248
1249 /* Only enable level 0 for now. */
1250 levels[0].EnabledForActivity = 1;
1251
1252 /* in order to prevent MC activity from stutter mode to push DPM up.
1253 * the UVD change complements this by putting the MCLK in
1254 * a higher state by default such that we are not effected by
1255 * up threshold or and MCLK DPM latency.
1256 */
1257 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1258 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1259
1260 smu_data->smc_state_table.MemoryDpmLevelCount =
1261 (uint8_t)dpm_table->mclk_table.count;
1262 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1263 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1264 /* set highest level watermark to high */
1265 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1266 PPSMC_DISPLAY_WATERMARK_HIGH;
1267
1268 /* level count will send to smc once at init smc table and never change */
1269 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1270 (uint32_t)array_size, SMC_RAM_END);
1271
1272 return result;
1273}
1274
1275static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1276 uint32_t mclk, SMIO_Pattern *smio_pat)
1277{
1278 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1279 struct phm_ppt_v1_information *table_info =
1280 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1281 uint32_t i = 0;
1282
1283 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1284 /* find mvdd value which clock is more than request */
1285 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1286 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1287 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1288 break;
1289 }
1290 }
1291 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1292 "MVDD Voltage is outside the supported range.",
1293 return -EINVAL);
1294 } else
1295 return -EINVAL;
1296
1297 return 0;
1298}
1299
1300static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1301 SMU73_Discrete_DpmTable *table)
1302{
1303 int result = 0;
1304 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1305 struct phm_ppt_v1_information *table_info =
1306 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1307 struct pp_atomctrl_clock_dividers_vi dividers;
1308 SMIO_Pattern vol_level;
1309 uint32_t mvdd;
1310 uint16_t us_mvdd;
1311 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1312 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1313
1314 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1315
1316 if (!data->sclk_dpm_key_disabled) {
1317 /* Get MinVoltage and Frequency from DPM0,
1318 * already converted to SMC_UL */
1319 table->ACPILevel.SclkFrequency =
1320 data->dpm_table.sclk_table.dpm_levels[0].value;
1321 result = fiji_get_dependency_volt_by_clk(hwmgr,
1322 table_info->vdd_dep_on_sclk,
1323 table->ACPILevel.SclkFrequency,
1324 (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
1325 PP_ASSERT_WITH_CODE((0 == result),
1326 "Cannot find ACPI VDDC voltage value " \
1327 "in Clock Dependency Table",
1328 );
1329 } else {
1330 table->ACPILevel.SclkFrequency =
1331 data->vbios_boot_state.sclk_bootup_value;
1332 table->ACPILevel.MinVoltage =
1333 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1334 }
1335
1336 /* get the engine clock dividers for this clock value */
1337 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1338 table->ACPILevel.SclkFrequency, &dividers);
1339 PP_ASSERT_WITH_CODE(result == 0,
1340 "Error retrieving Engine Clock dividers from VBIOS.",
1341 return result);
1342
1343 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1344 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1345 table->ACPILevel.DeepSleepDivId = 0;
1346
1347 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1348 SPLL_PWRON, 0);
1349 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1350 SPLL_RESET, 1);
1351 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1352 SCLK_MUX_SEL, 4);
1353
1354 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1355 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1356 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1357 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1358 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1359 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1360 table->ACPILevel.CcPwrDynRm = 0;
1361 table->ACPILevel.CcPwrDynRm1 = 0;
1362
1363 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1364 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1365 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1366 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1367 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1368 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1369 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1370 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1371 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1372 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1373 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1374
1375 if (!data->mclk_dpm_key_disabled) {
1376 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1377 table->MemoryACPILevel.MclkFrequency =
1378 data->dpm_table.mclk_table.dpm_levels[0].value;
1379 result = fiji_get_dependency_volt_by_clk(hwmgr,
1380 table_info->vdd_dep_on_mclk,
1381 table->MemoryACPILevel.MclkFrequency,
1382 (uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);
1383 PP_ASSERT_WITH_CODE((0 == result),
1384 "Cannot find ACPI VDDCI voltage value in Clock Dependency Table",
1385 );
1386 } else {
1387 table->MemoryACPILevel.MclkFrequency =
1388 data->vbios_boot_state.mclk_bootup_value;
1389 table->MemoryACPILevel.MinVoltage =
1390 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1391 }
1392
1393 us_mvdd = 0;
1394 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1395 (data->mclk_dpm_key_disabled))
1396 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1397 else {
1398 if (!fiji_populate_mvdd_value(hwmgr,
1399 data->dpm_table.mclk_table.dpm_levels[0].value,
1400 &vol_level))
1401 us_mvdd = vol_level.Voltage;
1402 }
1403
1404 table->MemoryACPILevel.MinMvdd =
1405 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
1406
1407 table->MemoryACPILevel.EnabledForThrottle = 0;
1408 table->MemoryACPILevel.EnabledForActivity = 0;
1409 table->MemoryACPILevel.UpHyst = 0;
1410 table->MemoryACPILevel.DownHyst = 100;
1411 table->MemoryACPILevel.VoltageDownHyst = 0;
1412 table->MemoryACPILevel.ActivityLevel =
1413 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1414
1415 table->MemoryACPILevel.StutterEnable = false;
1416 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1417 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1418
1419 return result;
1420}
1421
1422static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1423 SMU73_Discrete_DpmTable *table)
1424{
1425 int result = -EINVAL;
1426 uint8_t count;
1427 struct pp_atomctrl_clock_dividers_vi dividers;
1428 struct phm_ppt_v1_information *table_info =
1429 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1430 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1431 table_info->mm_dep_table;
1432
1433 table->VceLevelCount = (uint8_t)(mm_table->count);
1434 table->VceBootLevel = 0;
1435
1436 for (count = 0; count < table->VceLevelCount; count++) {
1437 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1438 table->VceLevel[count].MinVoltage = 0;
1439 table->VceLevel[count].MinVoltage |=
1440 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1441 table->VceLevel[count].MinVoltage |=
1442 ((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) *
1443 VOLTAGE_SCALE) << VDDCI_SHIFT;
1444 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1445
1446 /*retrieve divider value for VBIOS */
1447 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1448 table->VceLevel[count].Frequency, &dividers);
1449 PP_ASSERT_WITH_CODE((0 == result),
1450 "can not find divide id for VCE engine clock",
1451 return result);
1452
1453 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1454
1455 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1456 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1457 }
1458 return result;
1459}
1460
1461static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1462 SMU73_Discrete_DpmTable *table)
1463{
1464 int result = -EINVAL;
1465 uint8_t count;
1466 struct pp_atomctrl_clock_dividers_vi dividers;
1467 struct phm_ppt_v1_information *table_info =
1468 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1469 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1470 table_info->mm_dep_table;
1471
1472 table->AcpLevelCount = (uint8_t)(mm_table->count);
1473 table->AcpBootLevel = 0;
1474
1475 for (count = 0; count < table->AcpLevelCount; count++) {
1476 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
1477 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1478 VOLTAGE_SCALE) << VDDC_SHIFT;
1479 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1480 VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1481 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1482
1483 /* retrieve divider value for VBIOS */
1484 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1485 table->AcpLevel[count].Frequency, &dividers);
1486 PP_ASSERT_WITH_CODE((0 == result),
1487 "can not find divide id for engine clock", return result);
1488
1489 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1490
1491 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1492 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
1493 }
1494 return result;
1495}
1496
1497static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1498 int32_t eng_clock, int32_t mem_clock,
1499 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
1500{
1501 uint32_t dram_timing;
1502 uint32_t dram_timing2;
1503 uint32_t burstTime;
1504 ULONG state, trrds, trrdl;
1505 int result;
1506
1507 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1508 eng_clock, mem_clock);
1509 PP_ASSERT_WITH_CODE(result == 0,
1510 "Error calling VBIOS to set DRAM_TIMING.", return result);
1511
1512 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1513 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1514 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1515
1516 state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
1517 trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
1518 trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
1519
1520 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1521 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1522 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1523 arb_regs->TRRDS = (uint8_t)trrds;
1524 arb_regs->TRRDL = (uint8_t)trrdl;
1525
1526 return 0;
1527}
1528
1529static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1530{
1531 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1532 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1533 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
1534 uint32_t i, j;
1535 int result = 0;
1536
1537 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1538 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1539 result = fiji_populate_memory_timing_parameters(hwmgr,
1540 data->dpm_table.sclk_table.dpm_levels[i].value,
1541 data->dpm_table.mclk_table.dpm_levels[j].value,
1542 &arb_regs.entries[i][j]);
1543 if (result)
1544 break;
1545 }
1546 }
1547
1548 if (!result)
1549 result = smu7_copy_bytes_to_smc(
1550 hwmgr,
1551 smu_data->smu7_data.arb_table_start,
1552 (uint8_t *)&arb_regs,
1553 sizeof(SMU73_Discrete_MCArbDramTimingTable),
1554 SMC_RAM_END);
1555 return result;
1556}
1557
1558static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1559 struct SMU73_Discrete_DpmTable *table)
1560{
1561 int result = -EINVAL;
1562 uint8_t count;
1563 struct pp_atomctrl_clock_dividers_vi dividers;
1564 struct phm_ppt_v1_information *table_info =
1565 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1566 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1567 table_info->mm_dep_table;
1568
1569 table->UvdLevelCount = (uint8_t)(mm_table->count);
1570 table->UvdBootLevel = 0;
1571
1572 for (count = 0; count < table->UvdLevelCount; count++) {
1573 table->UvdLevel[count].MinVoltage = 0;
1574 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1575 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1576 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1577 VOLTAGE_SCALE) << VDDC_SHIFT;
1578 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1579 VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1580 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1581
1582 /* retrieve divider value for VBIOS */
1583 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1584 table->UvdLevel[count].VclkFrequency, &dividers);
1585 PP_ASSERT_WITH_CODE((0 == result),
1586 "can not find divide id for Vclk clock", return result);
1587
1588 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1589
1590 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1591 table->UvdLevel[count].DclkFrequency, &dividers);
1592 PP_ASSERT_WITH_CODE((0 == result),
1593 "can not find divide id for Dclk clock", return result);
1594
1595 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1596
1597 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1598 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1599 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1600
1601 }
1602 return result;
1603}
1604
1605static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1606 struct SMU73_Discrete_DpmTable *table)
1607{
1608 int result = 0;
1609 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1610
1611 table->GraphicsBootLevel = 0;
1612 table->MemoryBootLevel = 0;
1613
1614 /* find boot level from dpm table */
1615 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1616 data->vbios_boot_state.sclk_bootup_value,
1617 (uint32_t *)&(table->GraphicsBootLevel));
1618
1619 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1620 data->vbios_boot_state.mclk_bootup_value,
1621 (uint32_t *)&(table->MemoryBootLevel));
1622
1623 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1624 VOLTAGE_SCALE;
1625 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1626 VOLTAGE_SCALE;
1627 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1628 VOLTAGE_SCALE;
1629
1630 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1631 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1632 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1633
1634 return 0;
1635}
1636
1637static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1638{
1639 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1640 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1641 struct phm_ppt_v1_information *table_info =
1642 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1643 uint8_t count, level;
1644
1645 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1646 for (level = 0; level < count; level++) {
1647 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1648 data->vbios_boot_state.sclk_bootup_value) {
1649 smu_data->smc_state_table.GraphicsBootLevel = level;
1650 break;
1651 }
1652 }
1653
1654 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1655 for (level = 0; level < count; level++) {
1656 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1657 data->vbios_boot_state.mclk_bootup_value) {
1658 smu_data->smc_state_table.MemoryBootLevel = level;
1659 break;
1660 }
1661 }
1662
1663 return 0;
1664}
1665
1666static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1667{
1668 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1669 volt_with_cks, value;
1670 uint16_t clock_freq_u16;
1671 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1672 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1673 volt_offset = 0;
1674 struct phm_ppt_v1_information *table_info =
1675 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1676 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1677 table_info->vdd_dep_on_sclk;
1678
1679 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1680
1681 /* Read SMU_Eefuse to read and calculate RO and determine
1682 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1683 */
1684 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1685 ixSMU_EFUSE_0 + (146 * 4));
1686 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1687 ixSMU_EFUSE_0 + (148 * 4));
1688 efuse &= 0xFF000000;
1689 efuse = efuse >> 24;
1690 efuse2 &= 0xF;
1691
1692 if (efuse2 == 1)
1693 ro = (2300 - 1350) * efuse / 255 + 1350;
1694 else
1695 ro = (2500 - 1000) * efuse / 255 + 1000;
1696
1697 if (ro >= 1660)
1698 type = 0;
1699 else
1700 type = 1;
1701
1702 /* Populate Stretch amount */
1703 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1704
1705 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1706 for (i = 0; i < sclk_table->count; i++) {
1707 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1708 sclk_table->entries[i].cks_enable << i;
1709 volt_without_cks = (uint32_t)((14041 *
1710 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1711 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1712 volt_with_cks = (uint32_t)((13946 *
1713 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1714 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1715 if (volt_without_cks >= volt_with_cks)
1716 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1717 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1718 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1719 }
1720
1721 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1722 STRETCH_ENABLE, 0x0);
1723 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1724 masterReset, 0x1);
1725 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1726 staticEnable, 0x1);
1727 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1728 masterReset, 0x0);
1729
1730 /* Populate CKS Lookup Table */
1731 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1732 stretch_amount2 = 0;
1733 else if (stretch_amount == 3 || stretch_amount == 4)
1734 stretch_amount2 = 1;
1735 else {
1736 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1737 PHM_PlatformCaps_ClockStretcher);
1738 PP_ASSERT_WITH_CODE(false,
1739 "Stretch Amount in PPTable not supported",
1740 return -EINVAL);
1741 }
1742
1743 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1744 ixPWR_CKS_CNTL);
1745 value &= 0xFFC2FF87;
1746 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1747 fiji_clock_stretcher_lookup_table[stretch_amount2][0];
1748 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1749 fiji_clock_stretcher_lookup_table[stretch_amount2][1];
1750 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
1751 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1752 SclkFrequency) / 100);
1753 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
1754 clock_freq_u16 &&
1755 fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
1756 clock_freq_u16) {
1757 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1758 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1759 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1760 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1761 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1762 value |= (fiji_clock_stretch_amount_conversion
1763 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
1764 [stretch_amount]) << 3;
1765 }
1766 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1767 CKS_LOOKUPTableEntry[0].minFreq);
1768 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1769 CKS_LOOKUPTableEntry[0].maxFreq);
1770 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1771 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1772 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1773 (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1774
1775 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1776 ixPWR_CKS_CNTL, value);
1777
1778 /* Populate DDT Lookup Table */
1779 for (i = 0; i < 4; i++) {
1780 /* Assign the minimum and maximum VID stored
1781 * in the last row of Clock Stretcher Voltage Table.
1782 */
1783 smu_data->smc_state_table.ClockStretcherDataTable.
1784 ClockStretcherDataTableEntry[i].minVID =
1785 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
1786 smu_data->smc_state_table.ClockStretcherDataTable.
1787 ClockStretcherDataTableEntry[i].maxVID =
1788 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
1789 /* Loop through each SCLK and check the frequency
1790 * to see if it lies within the frequency for clock stretcher.
1791 */
1792 for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
1793 cks_setting = 0;
1794 clock_freq = PP_SMC_TO_HOST_UL(
1795 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
1796 /* Check the allowed frequency against the sclk level[j].
1797 * Sclk's endianness has already been converted,
1798 * and it's in 10Khz unit,
1799 * as opposed to Data table, which is in Mhz unit.
1800 */
1801 if (clock_freq >=
1802 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
1803 cks_setting |= 0x2;
1804 if (clock_freq <
1805 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
1806 cks_setting |= 0x1;
1807 }
1808 smu_data->smc_state_table.ClockStretcherDataTable.
1809 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1810 }
1811 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
1812 ClockStretcherDataTable.
1813 ClockStretcherDataTableEntry[i].setting);
1814 }
1815
1816 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1817 value &= 0xFFFFFFFE;
1818 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1819
1820 return 0;
1821}
1822
1823static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
1824 struct SMU73_Discrete_DpmTable *table)
1825{
1826 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1827 uint16_t config;
1828
1829 config = VR_MERGED_WITH_VDDC;
1830 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1831
1832 /* Set Vddc Voltage Controller */
1833 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1834 config = VR_SVI2_PLANE_1;
1835 table->VRConfig |= config;
1836 } else {
1837 PP_ASSERT_WITH_CODE(false,
1838 "VDDC should be on SVI2 control in merged mode!",
1839 );
1840 }
1841 /* Set Vddci Voltage Controller */
1842 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1843 config = VR_SVI2_PLANE_2; /* only in merged mode */
1844 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1845 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1846 config = VR_SMIO_PATTERN_1;
1847 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1848 } else {
1849 config = VR_STATIC_VOLTAGE;
1850 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1851 }
1852 /* Set Mvdd Voltage Controller */
1853 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1854 config = VR_SVI2_PLANE_2;
1855 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1856 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1857 config = VR_SMIO_PATTERN_2;
1858 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1859 } else {
1860 config = VR_STATIC_VOLTAGE;
1861 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1862 }
1863
1864 return 0;
1865}
1866
1867static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
1868{
1869 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1870 uint32_t tmp;
1871 int result;
1872
1873 /* This is a read-modify-write on the first byte of the ARB table.
1874 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1875 * is the field 'current'.
1876 * This solution is ugly, but we never write the whole table only
1877 * individual fields in it.
1878 * In reality this field should not be in that structure
1879 * but in a soft register.
1880 */
1881 result = smu7_read_smc_sram_dword(hwmgr,
1882 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1883
1884 if (result)
1885 return result;
1886
1887 tmp &= 0x00FFFFFF;
1888 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1889
1890 return smu7_write_smc_sram_dword(hwmgr,
1891 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1892}
1893
1894static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
1895{
1896 pp_atomctrl_voltage_table param_led_dpm;
1897 int result = 0;
1898 u32 mask = 0;
1899
1900 result = atomctrl_get_voltage_table_v3(hwmgr,
1901 VOLTAGE_TYPE_LEDDPM, VOLTAGE_OBJ_GPIO_LUT,
1902 &param_led_dpm);
1903 if (result == 0) {
1904 int i, j;
1905 u32 tmp = param_led_dpm.mask_low;
1906
1907 for (i = 0, j = 0; i < 32; i++) {
1908 if (tmp & 1) {
1909 mask |= (i << (8 * j));
1910 if (++j >= 3)
1911 break;
1912 }
1913 tmp >>= 1;
1914 }
1915 }
1916 if (mask)
1917 smum_send_msg_to_smc_with_parameter(hwmgr,
1918 PPSMC_MSG_LedConfig,
1919 mask);
1920 return 0;
1921}
1922
1923static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
1924{
1925 int result;
1926 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1927 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1928 struct phm_ppt_v1_information *table_info =
1929 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1930 struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1931 uint8_t i;
1932 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1933
1934 fiji_initialize_power_tune_defaults(hwmgr);
1935
1936 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
1937 fiji_populate_smc_voltage_tables(hwmgr, table);
1938
1939 table->SystemFlags = 0;
1940
1941 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1942 PHM_PlatformCaps_AutomaticDCTransition))
1943 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1944
1945 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1946 PHM_PlatformCaps_StepVddc))
1947 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1948
1949 if (data->is_memory_gddr5)
1950 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1951
1952 if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
1953 result = fiji_populate_ulv_state(hwmgr, table);
1954 PP_ASSERT_WITH_CODE(0 == result,
1955 "Failed to initialize ULV state!", return result);
1956 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1957 ixCG_ULV_PARAMETER, 0x40035);
1958 }
1959
1960 result = fiji_populate_smc_link_level(hwmgr, table);
1961 PP_ASSERT_WITH_CODE(0 == result,
1962 "Failed to initialize Link Level!", return result);
1963
1964 result = fiji_populate_all_graphic_levels(hwmgr);
1965 PP_ASSERT_WITH_CODE(0 == result,
1966 "Failed to initialize Graphics Level!", return result);
1967
1968 result = fiji_populate_all_memory_levels(hwmgr);
1969 PP_ASSERT_WITH_CODE(0 == result,
1970 "Failed to initialize Memory Level!", return result);
1971
1972 result = fiji_populate_smc_acpi_level(hwmgr, table);
1973 PP_ASSERT_WITH_CODE(0 == result,
1974 "Failed to initialize ACPI Level!", return result);
1975
1976 result = fiji_populate_smc_vce_level(hwmgr, table);
1977 PP_ASSERT_WITH_CODE(0 == result,
1978 "Failed to initialize VCE Level!", return result);
1979
1980 result = fiji_populate_smc_acp_level(hwmgr, table);
1981 PP_ASSERT_WITH_CODE(0 == result,
1982 "Failed to initialize ACP Level!", return result);
1983
1984 /* Since only the initial state is completely set up at this point
1985 * (the other states are just copies of the boot state) we only
1986 * need to populate the ARB settings for the initial state.
1987 */
1988 result = fiji_program_memory_timing_parameters(hwmgr);
1989 PP_ASSERT_WITH_CODE(0 == result,
1990 "Failed to Write ARB settings for the initial state.", return result);
1991
1992 result = fiji_populate_smc_uvd_level(hwmgr, table);
1993 PP_ASSERT_WITH_CODE(0 == result,
1994 "Failed to initialize UVD Level!", return result);
1995
1996 result = fiji_populate_smc_boot_level(hwmgr, table);
1997 PP_ASSERT_WITH_CODE(0 == result,
1998 "Failed to initialize Boot Level!", return result);
1999
2000 result = fiji_populate_smc_initailial_state(hwmgr);
2001 PP_ASSERT_WITH_CODE(0 == result,
2002 "Failed to initialize Boot State!", return result);
2003
2004 result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2005 PP_ASSERT_WITH_CODE(0 == result,
2006 "Failed to populate BAPM Parameters!", return result);
2007
2008 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2009 PHM_PlatformCaps_ClockStretcher)) {
2010 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2011 PP_ASSERT_WITH_CODE(0 == result,
2012 "Failed to populate Clock Stretcher Data Table!",
2013 return result);
2014 }
2015
2016 table->GraphicsVoltageChangeEnable = 1;
2017 table->GraphicsThermThrottleEnable = 1;
2018 table->GraphicsInterval = 1;
2019 table->VoltageInterval = 1;
2020 table->ThermalInterval = 1;
2021 table->TemperatureLimitHigh =
2022 table_info->cac_dtp_table->usTargetOperatingTemp *
2023 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2024 table->TemperatureLimitLow =
2025 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2026 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2027 table->MemoryVoltageChangeEnable = 1;
2028 table->MemoryInterval = 1;
2029 table->VoltageResponseTime = 0;
2030 table->PhaseResponseTime = 0;
2031 table->MemoryThermThrottleEnable = 1;
2032 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2033 table->PCIeGenInterval = 1;
2034 table->VRConfig = 0;
2035
2036 result = fiji_populate_vr_config(hwmgr, table);
2037 PP_ASSERT_WITH_CODE(0 == result,
2038 "Failed to populate VRConfig setting!", return result);
2039 data->vr_config = table->VRConfig;
2040 table->ThermGpio = 17;
2041 table->SclkStepSize = 0x4000;
2042
2043 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2044 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2045 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2046 PHM_PlatformCaps_RegulatorHot);
2047 } else {
2048 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2049 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2050 PHM_PlatformCaps_RegulatorHot);
2051 }
2052
2053 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2054 &gpio_pin)) {
2055 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2056 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2057 PHM_PlatformCaps_AutomaticDCTransition);
2058 } else {
2059 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2060 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2061 PHM_PlatformCaps_AutomaticDCTransition);
2062 }
2063
2064 /* Thermal Output GPIO */
2065 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2066 &gpio_pin)) {
2067 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2068 PHM_PlatformCaps_ThermalOutGPIO);
2069
2070 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2071
2072 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2073 * since VBIOS will program this register to set 'inactive state',
2074 * driver can then determine 'active state' from this and
2075 * program SMU with correct polarity
2076 */
2077 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2078 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2079 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2080
2081 /* if required, combine VRHot/PCC with thermal out GPIO */
2082 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2083 PHM_PlatformCaps_RegulatorHot) &&
2084 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2085 PHM_PlatformCaps_CombinePCCWithThermalSignal))
2086 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2087 } else {
2088 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2089 PHM_PlatformCaps_ThermalOutGPIO);
2090 table->ThermOutGpio = 17;
2091 table->ThermOutPolarity = 1;
2092 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2093 }
2094
2095 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
2096 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2097
2098 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2099 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2100 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2101 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2102 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2103 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2104 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2105 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2106 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2107
2108 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2109 result = smu7_copy_bytes_to_smc(hwmgr,
2110 smu_data->smu7_data.dpm_table_start +
2111 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
2112 (uint8_t *)&(table->SystemFlags),
2113 sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
2114 SMC_RAM_END);
2115 PP_ASSERT_WITH_CODE(0 == result,
2116 "Failed to upload dpm data to SMC memory!", return result);
2117
2118 result = fiji_init_arb_table_index(hwmgr);
2119 PP_ASSERT_WITH_CODE(0 == result,
2120 "Failed to upload arb data to SMC memory!", return result);
2121
2122 result = fiji_populate_pm_fuses(hwmgr);
2123 PP_ASSERT_WITH_CODE(0 == result,
2124 "Failed to populate PM fuses to SMC memory!", return result);
2125
2126 result = fiji_setup_dpm_led_config(hwmgr);
2127 PP_ASSERT_WITH_CODE(0 == result,
2128 "Failed to setup dpm led config", return result);
2129
2130 return 0;
2131}
2132
2133static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2134{
2135 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2136
2137 SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2138 uint32_t duty100;
2139 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2140 uint16_t fdo_min, slope1, slope2;
2141 uint32_t reference_clock;
2142 int res;
2143 uint64_t tmp64;
2144
2145 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2147 PHM_PlatformCaps_MicrocodeFanControl);
2148 return 0;
2149 }
2150
2151 if (smu_data->smu7_data.fan_table_start == 0) {
2152 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2153 PHM_PlatformCaps_MicrocodeFanControl);
2154 return 0;
2155 }
2156
2157 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2158 CG_FDO_CTRL1, FMAX_DUTY100);
2159
2160 if (duty100 == 0) {
2161 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2162 PHM_PlatformCaps_MicrocodeFanControl);
2163 return 0;
2164 }
2165
2166 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2167 usPWMMin * duty100;
2168 do_div(tmp64, 10000);
2169 fdo_min = (uint16_t)tmp64;
2170
2171 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2172 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2173 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2174 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2175
2176 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2177 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2178 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2179 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2180
2181 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2182 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2183
2184 fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2185 thermal_controller.advanceFanControlParameters.usTMin) / 100);
2186 fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2187 thermal_controller.advanceFanControlParameters.usTMed) / 100);
2188 fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2189 thermal_controller.advanceFanControlParameters.usTMax) / 100);
2190
2191 fan_table.Slope1 = cpu_to_be16(slope1);
2192 fan_table.Slope2 = cpu_to_be16(slope2);
2193
2194 fan_table.FdoMin = cpu_to_be16(fdo_min);
2195
2196 fan_table.HystDown = cpu_to_be16(hwmgr->
2197 thermal_controller.advanceFanControlParameters.ucTHyst);
2198
2199 fan_table.HystUp = cpu_to_be16(1);
2200
2201 fan_table.HystSlope = cpu_to_be16(1);
2202
2203 fan_table.TempRespLim = cpu_to_be16(5);
2204
2205 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2206
2207 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2208 thermal_controller.advanceFanControlParameters.ulCycleDelay *
2209 reference_clock) / 1600);
2210
2211 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2212
2213 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2214 hwmgr->device, CGS_IND_REG__SMC,
2215 CG_MULT_THERMAL_CTRL, TEMP_SEL);
2216
2217 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2218 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2219 SMC_RAM_END);
2220
2221 if (!res && hwmgr->thermal_controller.
2222 advanceFanControlParameters.ucMinimumPWMLimit)
2223 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2224 PPSMC_MSG_SetFanMinPwm,
2225 hwmgr->thermal_controller.
2226 advanceFanControlParameters.ucMinimumPWMLimit);
2227
2228 if (!res && hwmgr->thermal_controller.
2229 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2230 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2231 PPSMC_MSG_SetFanSclkTarget,
2232 hwmgr->thermal_controller.
2233 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
2234
2235 if (res)
2236 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2237 PHM_PlatformCaps_MicrocodeFanControl);
2238
2239 return 0;
2240}
2241
2242
2243static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2244{
2245 if (!hwmgr->avfs_supported)
2246 return 0;
2247
2248 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2249
2250 return 0;
2251}
2252
2253static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2254{
2255 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2256
2257 if (data->need_update_smu7_dpm_table &
2258 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2259 return fiji_program_memory_timing_parameters(hwmgr);
2260
2261 return 0;
2262}
2263
2264static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2265{
2266 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2267 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2268
2269 int result = 0;
2270 uint32_t low_sclk_interrupt_threshold = 0;
2271
2272 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2273 PHM_PlatformCaps_SclkThrottleLowNotification)
2274 && (data->low_sclk_interrupt_threshold != 0)) {
2275 low_sclk_interrupt_threshold =
2276 data->low_sclk_interrupt_threshold;
2277
2278 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2279
2280 result = smu7_copy_bytes_to_smc(
2281 hwmgr,
2282 smu_data->smu7_data.dpm_table_start +
2283 offsetof(SMU73_Discrete_DpmTable,
2284 LowSclkInterruptThreshold),
2285 (uint8_t *)&low_sclk_interrupt_threshold,
2286 sizeof(uint32_t),
2287 SMC_RAM_END);
2288 }
2289 result = fiji_program_mem_timing_parameters(hwmgr);
2290 PP_ASSERT_WITH_CODE((result == 0),
2291 "Failed to program memory timing parameters!",
2292 );
2293 return result;
2294}
2295
2296static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
2297{
2298 switch (type) {
2299 case SMU_SoftRegisters:
2300 switch (member) {
2301 case HandshakeDisables:
2302 return offsetof(SMU73_SoftRegisters, HandshakeDisables);
2303 case VoltageChangeTimeout:
2304 return offsetof(SMU73_SoftRegisters, VoltageChangeTimeout);
2305 case AverageGraphicsActivity:
2306 return offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
2307 case PreVBlankGap:
2308 return offsetof(SMU73_SoftRegisters, PreVBlankGap);
2309 case VBlankTimeout:
2310 return offsetof(SMU73_SoftRegisters, VBlankTimeout);
2311 case UcodeLoadStatus:
2312 return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
2313 case DRAM_LOG_ADDR_H:
2314 return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
2315 case DRAM_LOG_ADDR_L:
2316 return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
2317 case DRAM_LOG_PHY_ADDR_H:
2318 return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2319 case DRAM_LOG_PHY_ADDR_L:
2320 return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2321 case DRAM_LOG_BUFF_SIZE:
2322 return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2323 }
2324 break;
2325 case SMU_Discrete_DpmTable:
2326 switch (member) {
2327 case UvdBootLevel:
2328 return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
2329 case VceBootLevel:
2330 return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2331 case LowSclkInterruptThreshold:
2332 return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
2333 }
2334 break;
2335 }
2336 pr_warn("can't get the offset of type %x member %x\n", type, member);
2337 return 0;
2338}
2339
2340static uint32_t fiji_get_mac_definition(uint32_t value)
2341{
2342 switch (value) {
2343 case SMU_MAX_LEVELS_GRAPHICS:
2344 return SMU73_MAX_LEVELS_GRAPHICS;
2345 case SMU_MAX_LEVELS_MEMORY:
2346 return SMU73_MAX_LEVELS_MEMORY;
2347 case SMU_MAX_LEVELS_LINK:
2348 return SMU73_MAX_LEVELS_LINK;
2349 case SMU_MAX_ENTRIES_SMIO:
2350 return SMU73_MAX_ENTRIES_SMIO;
2351 case SMU_MAX_LEVELS_VDDC:
2352 return SMU73_MAX_LEVELS_VDDC;
2353 case SMU_MAX_LEVELS_VDDGFX:
2354 return SMU73_MAX_LEVELS_VDDGFX;
2355 case SMU_MAX_LEVELS_VDDCI:
2356 return SMU73_MAX_LEVELS_VDDCI;
2357 case SMU_MAX_LEVELS_MVDD:
2358 return SMU73_MAX_LEVELS_MVDD;
2359 }
2360
2361 pr_warn("can't get the mac of %x\n", value);
2362 return 0;
2363}
2364
2365
2366static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2367{
2368 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2369 uint32_t mm_boot_level_offset, mm_boot_level_value;
2370 struct phm_ppt_v1_information *table_info =
2371 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2372
2373 smu_data->smc_state_table.UvdBootLevel = 0;
2374 if (table_info->mm_dep_table->count > 0)
2375 smu_data->smc_state_table.UvdBootLevel =
2376 (uint8_t) (table_info->mm_dep_table->count - 1);
2377 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
2378 UvdBootLevel);
2379 mm_boot_level_offset /= 4;
2380 mm_boot_level_offset *= 4;
2381 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2382 CGS_IND_REG__SMC, mm_boot_level_offset);
2383 mm_boot_level_value &= 0x00FFFFFF;
2384 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2385 cgs_write_ind_register(hwmgr->device,
2386 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2387
2388 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2389 PHM_PlatformCaps_UVDDPM) ||
2390 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2391 PHM_PlatformCaps_StablePState))
2392 smum_send_msg_to_smc_with_parameter(hwmgr,
2393 PPSMC_MSG_UVDDPM_SetEnabledMask,
2394 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2395 return 0;
2396}
2397
2398static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2399{
2400 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2401 uint32_t mm_boot_level_offset, mm_boot_level_value;
2402 struct phm_ppt_v1_information *table_info =
2403 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2404
2405 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2406 PHM_PlatformCaps_StablePState))
2407 smu_data->smc_state_table.VceBootLevel =
2408 (uint8_t) (table_info->mm_dep_table->count - 1);
2409 else
2410 smu_data->smc_state_table.VceBootLevel = 0;
2411
2412 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2413 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2414 mm_boot_level_offset /= 4;
2415 mm_boot_level_offset *= 4;
2416 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2417 CGS_IND_REG__SMC, mm_boot_level_offset);
2418 mm_boot_level_value &= 0xFF00FFFF;
2419 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2420 cgs_write_ind_register(hwmgr->device,
2421 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2422
2423 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2424 smum_send_msg_to_smc_with_parameter(hwmgr,
2425 PPSMC_MSG_VCEDPM_SetEnabledMask,
2426 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2427 return 0;
2428}
2429
2430static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2431{
2432 switch (type) {
2433 case SMU_UVD_TABLE:
2434 fiji_update_uvd_smc_table(hwmgr);
2435 break;
2436 case SMU_VCE_TABLE:
2437 fiji_update_vce_smc_table(hwmgr);
2438 break;
2439 default:
2440 break;
2441 }
2442 return 0;
2443}
2444
2445static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2446{
2447 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2448 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2449 uint32_t tmp;
2450 int result;
2451 bool error = false;
2452
2453 result = smu7_read_smc_sram_dword(hwmgr,
2454 SMU7_FIRMWARE_HEADER_LOCATION +
2455 offsetof(SMU73_Firmware_Header, DpmTable),
2456 &tmp, SMC_RAM_END);
2457
2458 if (0 == result)
2459 smu_data->smu7_data.dpm_table_start = tmp;
2460
2461 error |= (0 != result);
2462
2463 result = smu7_read_smc_sram_dword(hwmgr,
2464 SMU7_FIRMWARE_HEADER_LOCATION +
2465 offsetof(SMU73_Firmware_Header, SoftRegisters),
2466 &tmp, SMC_RAM_END);
2467
2468 if (!result) {
2469 data->soft_regs_start = tmp;
2470 smu_data->smu7_data.soft_regs_start = tmp;
2471 }
2472
2473 error |= (0 != result);
2474
2475 result = smu7_read_smc_sram_dword(hwmgr,
2476 SMU7_FIRMWARE_HEADER_LOCATION +
2477 offsetof(SMU73_Firmware_Header, mcRegisterTable),
2478 &tmp, SMC_RAM_END);
2479
2480 if (!result)
2481 smu_data->smu7_data.mc_reg_table_start = tmp;
2482
2483 result = smu7_read_smc_sram_dword(hwmgr,
2484 SMU7_FIRMWARE_HEADER_LOCATION +
2485 offsetof(SMU73_Firmware_Header, FanTable),
2486 &tmp, SMC_RAM_END);
2487
2488 if (!result)
2489 smu_data->smu7_data.fan_table_start = tmp;
2490
2491 error |= (0 != result);
2492
2493 result = smu7_read_smc_sram_dword(hwmgr,
2494 SMU7_FIRMWARE_HEADER_LOCATION +
2495 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
2496 &tmp, SMC_RAM_END);
2497
2498 if (!result)
2499 smu_data->smu7_data.arb_table_start = tmp;
2500
2501 error |= (0 != result);
2502
2503 result = smu7_read_smc_sram_dword(hwmgr,
2504 SMU7_FIRMWARE_HEADER_LOCATION +
2505 offsetof(SMU73_Firmware_Header, Version),
2506 &tmp, SMC_RAM_END);
2507
2508 if (!result)
2509 hwmgr->microcode_version_info.SMC = tmp;
2510
2511 error |= (0 != result);
2512
2513 return error ? -1 : 0;
2514}
2515
2516static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2517{
2518
2519 /* Program additional LP registers
2520 * that are no longer programmed by VBIOS
2521 */
2522 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
2523 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2524 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
2525 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2526 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
2527 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2528 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
2529 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2530 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
2531 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2532 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
2533 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2534 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
2535 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2536
2537 return 0;
2538}
2539
2540static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
2541{
2542 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2543 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2544 ? true : false;
2545}
2546
2547static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
2548 void *profile_setting)
2549{
2550 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2551 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
2552 (hwmgr->smu_backend);
2553 struct profile_mode_setting *setting;
2554 struct SMU73_Discrete_GraphicsLevel *levels =
2555 smu_data->smc_state_table.GraphicsLevel;
2556 uint32_t array = smu_data->smu7_data.dpm_table_start +
2557 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
2558
2559 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2560 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2561 struct SMU73_Discrete_MemoryLevel *mclk_levels =
2562 smu_data->smc_state_table.MemoryLevel;
2563 uint32_t i;
2564 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2565
2566 if (profile_setting == NULL)
2567 return -EINVAL;
2568
2569 setting = (struct profile_mode_setting *)profile_setting;
2570
2571 if (setting->bupdate_sclk) {
2572 if (!data->sclk_dpm_key_disabled)
2573 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
2574 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2575 if (levels[i].ActivityLevel !=
2576 cpu_to_be16(setting->sclk_activity)) {
2577 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2578
2579 clk_activity_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2580 + offsetof(SMU73_Discrete_GraphicsLevel, ActivityLevel);
2581 offset = clk_activity_offset & ~0x3;
2582 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2583 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2584 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2585
2586 }
2587 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2588 levels[i].DownHyst != setting->sclk_down_hyst) {
2589 levels[i].UpHyst = setting->sclk_up_hyst;
2590 levels[i].DownHyst = setting->sclk_down_hyst;
2591 up_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2592 + offsetof(SMU73_Discrete_GraphicsLevel, UpHyst);
2593 down_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2594 + offsetof(SMU73_Discrete_GraphicsLevel, DownHyst);
2595 offset = up_hyst_offset & ~0x3;
2596 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2597 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2598 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2599 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2600 }
2601 }
2602 if (!data->sclk_dpm_key_disabled)
2603 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
2604 }
2605
2606 if (setting->bupdate_mclk) {
2607 if (!data->mclk_dpm_key_disabled)
2608 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
2609 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2610 if (mclk_levels[i].ActivityLevel !=
2611 cpu_to_be16(setting->mclk_activity)) {
2612 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2613
2614 clk_activity_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2615 + offsetof(SMU73_Discrete_MemoryLevel, ActivityLevel);
2616 offset = clk_activity_offset & ~0x3;
2617 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2618 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2619 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2620
2621 }
2622 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2623 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2624 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2625 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2626 up_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2627 + offsetof(SMU73_Discrete_MemoryLevel, UpHyst);
2628 down_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2629 + offsetof(SMU73_Discrete_MemoryLevel, DownHyst);
2630 offset = up_hyst_offset & ~0x3;
2631 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2632 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2633 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2635 }
2636 }
2637 if (!data->mclk_dpm_key_disabled)
2638 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
2639 }
2640 return 0;
2641}
2642
2643const struct pp_smumgr_func fiji_smu_funcs = {
2644 .smu_init = &fiji_smu_init,
2645 .smu_fini = &smu7_smu_fini,
2646 .start_smu = &fiji_start_smu,
2647 .check_fw_load_finish = &smu7_check_fw_load_finish,
2648 .request_smu_load_fw = &smu7_reload_firmware,
2649 .request_smu_load_specific_fw = NULL,
2650 .send_msg_to_smc = &smu7_send_msg_to_smc,
2651 .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2652 .download_pptable_settings = NULL,
2653 .upload_pptable_settings = NULL,
2654 .update_smc_table = fiji_update_smc_table,
2655 .get_offsetof = fiji_get_offsetof,
2656 .process_firmware_header = fiji_process_firmware_header,
2657 .init_smc_table = fiji_init_smc_table,
2658 .update_sclk_threshold = fiji_update_sclk_threshold,
2659 .