1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui <ray.huang@amd.com>
23 *
24 */
25#include "pp_debug.h"
26#include <linux/types.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/gfp.h>
30
31#include "smumgr.h"
32#include "iceland_smumgr.h"
33
34#include "ppsmc.h"
35
36#include "cgs_common.h"
37
38#include "smu7_dyn_defaults.h"
39#include "smu7_hwmgr.h"
40#include "hardwaremanager.h"
41#include "ppatomctrl.h"
42#include "atombios.h"
43#include "pppcielanes.h"
44#include "pp_endian.h"
45#include "processpptables.h"
46
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50#include "smu71_discrete.h"
51
52#include "smu_ucode_xfer_vi.h"
53#include "gmc/gmc_8_1_d.h"
54#include "gmc/gmc_8_1_sh_mask.h"
55#include "bif/bif_5_0_d.h"
56#include "bif/bif_5_0_sh_mask.h"
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60
61#define ICELAND_SMC_SIZE 0x20000
62
63#define POWERTUNE_DEFAULT_SET_MAX 1
64#define MC_CG_ARB_FREQ_F1 0x0b
65#define VDDC_VDDCI_DELTA 200
66
67#define DEVICE_ID_VI_ICELAND_M_6900 0x6900
68#define DEVICE_ID_VI_ICELAND_M_6901 0x6901
69#define DEVICE_ID_VI_ICELAND_M_6902 0x6902
70#define DEVICE_ID_VI_ICELAND_M_6903 0x6903
71
72static const struct iceland_pt_defaults defaults_iceland = {
73 /*
74 * sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc,
75 * TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT
76 */
77 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
78 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
79 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
80};
81
82/* 35W - XT, XTL */
83static const struct iceland_pt_defaults defaults_icelandxt = {
84 /*
85 * sviLoadLIneEn, SviLoadLineVddC,
86 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
87 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
88 * BAPM_TEMP_GRADIENT
89 */
90 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
91 { 0xA7, 0x0, 0x0, 0xB5, 0x0, 0x0, 0x9F, 0x0, 0x0, 0xD6, 0x0, 0x0, 0xD7, 0x0, 0x0},
92 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
93};
94
95/* 25W - PRO, LE */
96static const struct iceland_pt_defaults defaults_icelandpro = {
97 /*
98 * sviLoadLIneEn, SviLoadLineVddC,
99 * TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
100 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac,
101 * BAPM_TEMP_GRADIENT
102 */
103 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x0,
104 { 0xB7, 0x0, 0x0, 0xC3, 0x0, 0x0, 0xB5, 0x0, 0x0, 0xEA, 0x0, 0x0, 0xE6, 0x0, 0x0},
105 { 0x1EA, 0x0, 0x0, 0x224, 0x0, 0x0, 0x25E, 0x0, 0x0, 0x28E, 0x0, 0x0, 0x2AB, 0x0, 0x0}
106};
107
108static int iceland_start_smc(struct pp_hwmgr *hwmgr)
109{
110 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
111 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
112
113 return 0;
114}
115
116static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
117{
118 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
119 SMC_SYSCON_RESET_CNTL,
120 rst_reg, 1);
121}
122
123
124static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
125{
126 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
127 SMC_SYSCON_CLOCK_CNTL_0,
128 ck_disable, 1);
129}
130
131static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
132{
133 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
134 SMC_SYSCON_CLOCK_CNTL_0,
135 ck_disable, 0);
136}
137
138static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
139{
140 /* set smc instruct start point at 0x0 */
141 smu7_program_jump_on_start(hwmgr);
142
143 /* enable smc clock */
144 iceland_start_smc_clock(hwmgr);
145
146 /* de-assert reset */
147 iceland_start_smc(hwmgr);
148
149 PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
150 INTERRUPTS_ENABLED, 1);
151
152 return 0;
153}
154
155
156static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
157 uint32_t length, const uint8_t *src,
158 uint32_t limit, uint32_t start_addr)
159{
160 uint32_t byte_count = length;
161 uint32_t data;
162
163 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
164
165 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
166 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
167
168 while (byte_count >= 4) {
169 data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
171 src += 4;
172 byte_count -= 4;
173 }
174
175 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
176
177 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
178
179 return 0;
180}
181
182
183static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
184{
185 uint32_t val;
186 struct cgs_firmware_info info = {0};
187
188 if (hwmgr == NULL || hwmgr->device == NULL)
189 return -EINVAL;
190
191 /* load SMC firmware */
192 cgs_get_firmware_info(hwmgr->device,
193 smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
194
195 if (info.image_size & 3) {
196 pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
197 return -EINVAL;
198 }
199
200 if (info.image_size > ICELAND_SMC_SIZE) {
201 pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
202 return -EINVAL;
203 }
204 hwmgr->smu_version = info.version;
205 /* wait for smc boot up */
206 PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
207 RCU_UC_EVENTS, boot_seq_done, 0);
208
209 /* clear firmware interrupt enable flag */
210 val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
211 ixSMC_SYSCON_MISC_CNTL);
212 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
213 ixSMC_SYSCON_MISC_CNTL, val | 1);
214
215 /* stop smc clock */
216 iceland_stop_smc_clock(hwmgr);
217
218 /* reset smc */
219 iceland_reset_smc(hwmgr);
220 iceland_upload_smc_firmware_data(hwmgr, info.image_size,
221 (uint8_t *)info.kptr, ICELAND_SMC_SIZE,
222 info.ucode_start_address);
223
224 return 0;
225}
226
227static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
228 uint32_t firmwareType)
229{
230 return 0;
231}
232
233static int iceland_start_smu(struct pp_hwmgr *hwmgr)
234{
235 struct iceland_smumgr *priv = hwmgr->smu_backend;
236 int result;
237
238 if (!smu7_is_smc_ram_running(hwmgr)) {
239 result = iceland_smu_upload_firmware_image(hwmgr);
240 if (result)
241 return result;
242
243 iceland_smu_start_smc(hwmgr);
244 }
245
246 /* Setup SoftRegsStart here to visit the register UcodeLoadStatus
247 * to check fw loading state
248 */
249 smu7_read_smc_sram_dword(hwmgr,
250 SMU71_FIRMWARE_HEADER_LOCATION +
251 offsetof(SMU71_Firmware_Header, SoftRegisters),
252 &(priv->smu7_data.soft_regs_start), 0x40000);
253
254 result = smu7_request_smu_load_fw(hwmgr);
255
256 return result;
257}
258
259static int iceland_smu_init(struct pp_hwmgr *hwmgr)
260{
261 struct iceland_smumgr *iceland_priv = NULL;
262
263 iceland_priv = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
264
265 if (iceland_priv == NULL)
266 return -ENOMEM;
267
268 hwmgr->smu_backend = iceland_priv;
269
270 if (smu7_init(hwmgr)) {
271 kfree(iceland_priv);
272 return -EINVAL;
273 }
274
275 return 0;
276}
277
278
279static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
280{
281 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
282 struct amdgpu_device *adev = hwmgr->adev;
283 uint32_t dev_id;
284
285 dev_id = adev->pdev->device;
286
287 switch (dev_id) {
288 case DEVICE_ID_VI_ICELAND_M_6900:
289 case DEVICE_ID_VI_ICELAND_M_6903:
290 smu_data->power_tune_defaults = &defaults_icelandxt;
291 break;
292
293 case DEVICE_ID_VI_ICELAND_M_6901:
294 case DEVICE_ID_VI_ICELAND_M_6902:
295 smu_data->power_tune_defaults = &defaults_icelandpro;
296 break;
297 default:
298 smu_data->power_tune_defaults = &defaults_iceland;
299 pr_warn("Unknown V.I. Device ID.\n");
300 break;
301 }
302 return;
303}
304
305static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
306{
307 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
308 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
309
310 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
311 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddc;
312 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
313 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
314
315 return 0;
316}
317
318static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
319{
320 uint16_t tdc_limit;
321 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
322 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
323
324 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
325 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
326 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
327 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
328 defaults->tdc_vddc_throttle_release_limit_perc;
329 smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
330
331 return 0;
332}
333
334static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
335{
336 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
337 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
338 uint32_t temp;
339
340 if (smu7_read_smc_sram_dword(hwmgr,
341 fuse_table_offset +
342 offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
343 (uint32_t *)&temp, SMC_RAM_END))
344 PP_ASSERT_WITH_CODE(false,
345 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
346 return -EINVAL);
347 else
348 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
349
350 return 0;
351}
352
353static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
354{
355 return 0;
356}
357
358static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
359{
360 int i;
361 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
362
363 /* Currently not used. Set all to zero. */
364 for (i = 0; i < 8; i++)
365 smu_data->power_tune_table.GnbLPML[i] = 0;
366
367 return 0;
368}
369
370static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
371{
372 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
373 uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
374 uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
375 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
376
377 HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
378 LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
379
380 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
381 CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
382 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
383 CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
384
385 return 0;
386}
387
388static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
389{
390 int i;
391 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
392 uint8_t *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;
393 uint8_t *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;
394
395 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
396 "The CAC Leakage table does not exist!", return -EINVAL);
397 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
398 "There should never be more than 8 entries for BapmVddcVid!!!", return -EINVAL);
399 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
400 "CACLeakageTable->count and VddcDependencyOnSCLk->count not equal", return -EINVAL);
401
402 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
403 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
404 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
405 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
406 }
407 } else {
408 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
409 }
410
411 return 0;
412}
413
414static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
415{
416 int i;
417 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
418 uint8_t *vid = smu_data->power_tune_table.VddCVid;
419 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
420
421 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
422 "There should never be more than 8 entries for VddcVid!!!",
423 return -EINVAL);
424
425 for (i = 0; i < (int)data->vddc_voltage_table.count; i++) {
426 vid[i] = convert_to_vid(data->vddc_voltage_table.entries[i].value);
427 }
428
429 return 0;
430}
431
432
433
434static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
435{
436 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
437 uint32_t pm_fuse_table_offset;
438
439 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
440 PHM_PlatformCaps_PowerContainment)) {
441 if (smu7_read_smc_sram_dword(hwmgr,
442 SMU71_FIRMWARE_HEADER_LOCATION +
443 offsetof(SMU71_Firmware_Header, PmFuseTable),
444 &pm_fuse_table_offset, SMC_RAM_END))
445 PP_ASSERT_WITH_CODE(false,
446 "Attempt to get pm_fuse_table_offset Failed!",
447 return -EINVAL);
448
449 /* DW0 - DW3 */
450 if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
451 PP_ASSERT_WITH_CODE(false,
452 "Attempt to populate bapm vddc vid Failed!",
453 return -EINVAL);
454
455 /* DW4 - DW5 */
456 if (iceland_populate_vddc_vid(hwmgr))
457 PP_ASSERT_WITH_CODE(false,
458 "Attempt to populate vddc vid Failed!",
459 return -EINVAL);
460
461 /* DW6 */
462 if (iceland_populate_svi_load_line(hwmgr))
463 PP_ASSERT_WITH_CODE(false,
464 "Attempt to populate SviLoadLine Failed!",
465 return -EINVAL);
466 /* DW7 */
467 if (iceland_populate_tdc_limit(hwmgr))
468 PP_ASSERT_WITH_CODE(false,
469 "Attempt to populate TDCLimit Failed!", return -EINVAL);
470 /* DW8 */
471 if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
472 PP_ASSERT_WITH_CODE(false,
473 "Attempt to populate TdcWaterfallCtl, "
474 "LPMLTemperature Min and Max Failed!",
475 return -EINVAL);
476
477 /* DW9-DW12 */
478 if (0 != iceland_populate_temperature_scaler(hwmgr))
479 PP_ASSERT_WITH_CODE(false,
480 "Attempt to populate LPMLTemperatureScaler Failed!",
481 return -EINVAL);
482
483 /* DW13-DW16 */
484 if (iceland_populate_gnb_lpml(hwmgr))
485 PP_ASSERT_WITH_CODE(false,
486 "Attempt to populate GnbLPML Failed!",
487 return -EINVAL);
488
489 /* DW18 */
490 if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
491 PP_ASSERT_WITH_CODE(false,
492 "Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
493 return -EINVAL);
494
495 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
496 (uint8_t *)&smu_data->power_tune_table,
497 sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
498 PP_ASSERT_WITH_CODE(false,
499 "Attempt to download PmFuseTable Failed!",
500 return -EINVAL);
501 }
502 return 0;
503}
504
505static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
506 struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
507 uint32_t clock, uint32_t *vol)
508{
509 uint32_t i = 0;
510
511 /* clock - voltage dependency table is empty table */
512 if (allowed_clock_voltage_table->count == 0)
513 return -EINVAL;
514
515 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
516 /* find first sclk bigger than request */
517 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
518 *vol = allowed_clock_voltage_table->entries[i].v;
519 return 0;
520 }
521 }
522
523 /* sclk is bigger than max sclk in the dependence table */
524 *vol = allowed_clock_voltage_table->entries[i - 1].v;
525
526 return 0;
527}
528
529static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
530 pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
531 uint16_t *lo)
532{
533 uint16_t v_index;
534 bool vol_found = false;
535 *hi = tab->value * VOLTAGE_SCALE;
536 *lo = tab->value * VOLTAGE_SCALE;
537
538 /* SCLK/VDDC Dependency Table has to exist. */
539 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
540 "The SCLK/VDDC Dependency Table does not exist.",
541 return -EINVAL);
542
543 if (NULL == hwmgr->dyn_state.cac_leakage_table) {
544 pr_warn("CAC Leakage Table does not exist, using vddc.\n");
545 return 0;
546 }
547
548 /*
549 * Since voltage in the sclk/vddc dependency table is not
550 * necessarily in ascending order because of ELB voltage
551 * patching, loop through entire list to find exact voltage.
552 */
553 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
554 if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
555 vol_found = true;
556 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
557 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
558 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
559 } else {
560 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum index from CAC table.\n");
561 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
562 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
563 }
564 break;
565 }
566 }
567
568 /*
569 * If voltage is not found in the first pass, loop again to
570 * find the best match, equal or higher value.
571 */
572 if (!vol_found) {
573 for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
574 if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
575 vol_found = true;
576 if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
577 *lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
578 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
579 } else {
580 pr_warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using maximum index from CAC table.");
581 *lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
582 *hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
583 }
584 break;
585 }
586 }
587
588 if (!vol_found)
589 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n");
590 }
591
592 return 0;
593}
594
595static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
596 pp_atomctrl_voltage_table_entry *tab,
597 SMU71_Discrete_VoltageLevel *smc_voltage_tab)
598{
599 int result;
600
601 result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
602 &smc_voltage_tab->StdVoltageHiSidd,
603 &smc_voltage_tab->StdVoltageLoSidd);
604 if (0 != result) {
605 smc_voltage_tab->StdVoltageHiSidd = tab->value * VOLTAGE_SCALE;
606 smc_voltage_tab->StdVoltageLoSidd = tab->value * VOLTAGE_SCALE;
607 }
608
609 smc_voltage_tab->Voltage = PP_HOST_TO_SMC_US(tab->value * VOLTAGE_SCALE);
610 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
611 CONVERT_FROM_HOST_TO_SMC_US(smc_voltage_tab->StdVoltageHiSidd);
612
613 return 0;
614}
615
616static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
617 SMU71_Discrete_DpmTable *table)
618{
619 unsigned int count;
620 int result;
621 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
622
623 table->VddcLevelCount = data->vddc_voltage_table.count;
624 for (count = 0; count < table->VddcLevelCount; count++) {
625 result = iceland_populate_smc_voltage_table(hwmgr,
626 &(data->vddc_voltage_table.entries[count]),
627 &(table->VddcLevel[count]));
628 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
629
630 /* GPIO voltage control */
631 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control)
632 table->VddcLevel[count].Smio |= data->vddc_voltage_table.entries[count].smio_low;
633 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
634 table->VddcLevel[count].Smio = 0;
635 }
636
637 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
638
639 return 0;
640}
641
642static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
643 SMU71_Discrete_DpmTable *table)
644{
645 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
646 uint32_t count;
647 int result;
648
649 table->VddciLevelCount = data->vddci_voltage_table.count;
650
651 for (count = 0; count < table->VddciLevelCount; count++) {
652 result = iceland_populate_smc_voltage_table(hwmgr,
653 &(data->vddci_voltage_table.entries[count]),
654 &(table->VddciLevel[count]));
655 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
656 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
657 table->VddciLevel[count].Smio |= data->vddci_voltage_table.entries[count].smio_low;
658 else
659 table->VddciLevel[count].Smio |= 0;
660 }
661
662 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
663
664 return 0;
665}
666
667static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
668 SMU71_Discrete_DpmTable *table)
669{
670 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
671 uint32_t count;
672 int result;
673
674 table->MvddLevelCount = data->mvdd_voltage_table.count;
675
676 for (count = 0; count < table->VddciLevelCount; count++) {
677 result = iceland_populate_smc_voltage_table(hwmgr,
678 &(data->mvdd_voltage_table.entries[count]),
679 &table->MvddLevel[count]);
680 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL);
681 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control)
682 table->MvddLevel[count].Smio |= data->mvdd_voltage_table.entries[count].smio_low;
683 else
684 table->MvddLevel[count].Smio |= 0;
685 }
686
687 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
688
689 return 0;
690}
691
692
693static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
694 SMU71_Discrete_DpmTable *table)
695{
696 int result;
697
698 result = iceland_populate_smc_vddc_table(hwmgr, table);
699 PP_ASSERT_WITH_CODE(0 == result,
700 "can not populate VDDC voltage table to SMC", return -EINVAL);
701
702 result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
703 PP_ASSERT_WITH_CODE(0 == result,
704 "can not populate VDDCI voltage table to SMC", return -EINVAL);
705
706 result = iceland_populate_smc_mvdd_table(hwmgr, table);
707 PP_ASSERT_WITH_CODE(0 == result,
708 "can not populate MVDD voltage table to SMC", return -EINVAL);
709
710 return 0;
711}
712
713static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
714 struct SMU71_Discrete_Ulv *state)
715{
716 uint32_t voltage_response_time, ulv_voltage;
717 int result;
718 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
719
720 state->CcPwrDynRm = 0;
721 state->CcPwrDynRm1 = 0;
722
723 result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
724 PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;);
725
726 if (ulv_voltage == 0) {
727 data->ulv_supported = false;
728 return 0;
729 }
730
731 if (data->voltage_control != SMU7_VOLTAGE_CONTROL_BY_SVID2) {
732 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
733 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
734 state->VddcOffset = 0;
735 else
736 /* used in SMIO Mode. not implemented for now. this is backup only for CI. */
737 state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
738 } else {
739 /* use minimum voltage if ulv voltage in pptable is bigger than minimum voltage */
740 if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
741 state->VddcOffsetVid = 0;
742 else /* used in SVI2 Mode */
743 state->VddcOffsetVid = (uint8_t)(
744 (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
745 * VOLTAGE_VID_OFFSET_SCALE2
746 / VOLTAGE_VID_OFFSET_SCALE1);
747 }
748 state->VddcPhase = 1;
749
750 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
751 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
752 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
753
754 return 0;
755}
756
757static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
758 SMU71_Discrete_Ulv *ulv_level)
759{
760 return iceland_populate_ulv_level(hwmgr, ulv_level);
761}
762
763static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
764{
765 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
766 struct smu7_dpm_table *dpm_table = &data->dpm_table;
767 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
768 uint32_t i;
769
770 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
771 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
772 table->LinkLevel[i].PcieGenSpeed =
773 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
774 table->LinkLevel[i].PcieLaneCount =
775 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
776 table->LinkLevel[i].EnabledForActivity =
777 1;
778 table->LinkLevel[i].SPC =
779 (uint8_t)(data->pcie_spc_cap & 0xff);
780 table->LinkLevel[i].DownThreshold =
781 PP_HOST_TO_SMC_UL(5);
782 table->LinkLevel[i].UpThreshold =
783 PP_HOST_TO_SMC_UL(30);
784 }
785
786 smu_data->smc_state_table.LinkLevelCount =
787 (uint8_t)dpm_table->pcie_speed_table.count;
788 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
789 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
790
791 return 0;
792}
793
794static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
795 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk)
796{
797 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
798 pp_atomctrl_clock_dividers_vi dividers;
799 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
800 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
801 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
802 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
803 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
804 uint32_t reference_clock;
805 uint32_t reference_divider;
806 uint32_t fbdiv;
807 int result;
808
809 /* get the engine clock dividers for this clock value*/
810 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
811
812 PP_ASSERT_WITH_CODE(result == 0,
813 "Error retrieving Engine Clock dividers from VBIOS.", return result);
814
815 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
816 reference_clock = atomctrl_get_reference_clock(hwmgr);
817
818 reference_divider = 1 + dividers.uc_pll_ref_div;
819
820 /* low 14 bits is fraction and high 12 bits is divider*/
821 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
822
823 /* SPLL_FUNC_CNTL setup*/
824 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
825 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
826 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
827 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
828
829 /* SPLL_FUNC_CNTL_3 setup*/
830 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
831 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
832
833 /* set to use fractional accumulation*/
834 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
835 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
836
837 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
838 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
839 pp_atomctrl_internal_ss_info ss_info;
840
841 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
842 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
843 /*
844 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
845 * ss_info.speed_spectrum_rate -- in unit of khz
846 */
847 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
848 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
849
850 /* clkv = 2 * D * fbdiv / NS */
851 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
852
853 cg_spll_spread_spectrum =
854 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
855 cg_spll_spread_spectrum =
856 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
857 cg_spll_spread_spectrum_2 =
858 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
859 }
860 }
861
862 sclk->SclkFrequency = engine_clock;
863 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
864 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
865 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
866 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
867 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
868
869 return 0;
870}
871
872static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
873 const struct phm_phase_shedding_limits_table *pl,
874 uint32_t sclk, uint32_t *p_shed)
875{
876 unsigned int i;
877
878 /* use the minimum phase shedding */
879 *p_shed = 1;
880
881 for (i = 0; i < pl->count; i++) {
882 if (sclk < pl->entries[i].Sclk) {
883 *p_shed = i;
884 break;
885 }
886 }
887 return 0;
888}
889
890static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
891 uint32_t engine_clock,
892 SMU71_Discrete_GraphicsLevel *graphic_level)
893{
894 int result;
895 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
896
897 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
898
899 /* populate graphics levels*/
900 result = iceland_get_dependency_volt_by_clk(hwmgr,
901 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
902 &graphic_level->MinVddc);
903 PP_ASSERT_WITH_CODE((0 == result),
904 "can not find VDDC voltage value for VDDC engine clock dependency table", return result);
905
906 /* SCLK frequency in units of 10KHz*/
907 graphic_level->SclkFrequency = engine_clock;
908 graphic_level->MinVddcPhases = 1;
909
910 if (data->vddc_phase_shed_control)
911 iceland_populate_phase_value_based_on_sclk(hwmgr,
912 hwmgr->dyn_state.vddc_phase_shed_limits_table,
913 engine_clock,
914 &graphic_level->MinVddcPhases);
915
916 /* Indicates maximum activity level for this performance level. 50% for now*/
917 graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity;
918
919 graphic_level->CcPwrDynRm = 0;
920 graphic_level->CcPwrDynRm1 = 0;
921 /* this level can be used if activity is high enough.*/
922 graphic_level->EnabledForActivity = 0;
923 /* this level can be used for throttling.*/
924 graphic_level->EnabledForThrottle = 1;
925 graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst;
926 graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst;
927 graphic_level->VoltageDownHyst = 0;
928 graphic_level->PowerThrottle = 0;
929
930 data->display_timing.min_clock_in_sr =
931 hwmgr->display_config->min_core_set_clock_in_sr;
932
933 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
934 PHM_PlatformCaps_SclkDeepSleep))
935 graphic_level->DeepSleepDivId =
936 smu7_get_sleep_divider_id_from_clock(engine_clock,
937 data->display_timing.min_clock_in_sr);
938
939 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
940 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
941
942 if (0 == result) {
943 graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
944 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);
945 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
946 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
947 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
948 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
949 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
950 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
951 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
952 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
953 }
954
955 return result;
956}
957
958static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
959{
960 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
961 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
962 struct smu7_dpm_table *dpm_table = &data->dpm_table;
963 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start +
964 offsetof(SMU71_Discrete_DpmTable, GraphicsLevel);
965
966 uint32_t level_array_size = sizeof(SMU71_Discrete_GraphicsLevel) *
967 SMU71_MAX_LEVELS_GRAPHICS;
968
969 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel;
970
971 uint32_t i;
972 uint8_t highest_pcie_level_enabled = 0;
973 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0;
974 uint8_t count = 0;
975 int result = 0;
976
977 memset(levels, 0x00, level_array_size);
978
979 for (i = 0; i < dpm_table->sclk_table.count; i++) {
980 result = iceland_populate_single_graphic_level(hwmgr,
981 dpm_table->sclk_table.dpm_levels[i].value,
982 &(smu_data->smc_state_table.GraphicsLevel[i]));
983 if (result != 0)
984 return result;
985
986 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
987 if (i > 1)
988 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
989 }
990
991 /* Only enable level 0 for now. */
992 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
993
994 /* set highest level watermark to high */
995 if (dpm_table->sclk_table.count > 1)
996 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
997 PPSMC_DISPLAY_WATERMARK_HIGH;
998
999 smu_data->smc_state_table.GraphicsDpmLevelCount =
1000 (uint8_t)dpm_table->sclk_table.count;
1001 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1002 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1003
1004 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1005 (1 << (highest_pcie_level_enabled + 1))) != 0) {
1006 highest_pcie_level_enabled++;
1007 }
1008
1009 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1010 (1 << lowest_pcie_level_enabled)) == 0) {
1011 lowest_pcie_level_enabled++;
1012 }
1013
1014 while ((count < highest_pcie_level_enabled) &&
1015 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1016 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) {
1017 count++;
1018 }
1019
1020 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
1021 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
1022
1023
1024 /* set pcieDpmLevel to highest_pcie_level_enabled*/
1025 for (i = 2; i < dpm_table->sclk_table.count; i++) {
1026 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
1027 }
1028
1029 /* set pcieDpmLevel to lowest_pcie_level_enabled*/
1030 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
1031
1032 /* set pcieDpmLevel to mid_pcie_level_enabled*/
1033 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
1034
1035 /* level count will send to smc once at init smc table and never change*/
1036 result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
1037 (uint8_t *)levels, (uint32_t)level_array_size,
1038 SMC_RAM_END);
1039
1040 return result;
1041}
1042
1043static int iceland_calculate_mclk_params(
1044 struct pp_hwmgr *hwmgr,
1045 uint32_t memory_clock,
1046 SMU71_Discrete_MemoryLevel *mclk,
1047 bool strobe_mode,
1048 bool dllStateOn
1049 )
1050{
1051 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1052
1053 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1054 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1055 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
1056 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
1057 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
1058 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
1059 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
1060 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
1061 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1062
1063 pp_atomctrl_memory_clock_param mpll_param;
1064 int result;
1065
1066 result = atomctrl_get_memory_pll_dividers_si(hwmgr,
1067 memory_clock, &mpll_param, strobe_mode);
1068 PP_ASSERT_WITH_CODE(0 == result,
1069 "Error retrieving Memory Clock Parameters from VBIOS.", return result);
1070
1071 /* MPLL_FUNC_CNTL setup*/
1072 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
1073
1074 /* MPLL_FUNC_CNTL_1 setup*/
1075 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1076 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
1077 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1078 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
1079 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
1080 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
1081
1082 /* MPLL_AD_FUNC_CNTL setup*/
1083 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
1084 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1085
1086 if (data->is_memory_gddr5) {
1087 /* MPLL_DQ_FUNC_CNTL setup*/
1088 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1089 MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
1090 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
1091 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
1092 }
1093
1094 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1095 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
1096 /*
1097 ************************************
1098 Fref = Reference Frequency
1099 NF = Feedback divider ratio
1100 NR = Reference divider ratio
1101 Fnom = Nominal VCO output frequency = Fref * NF / NR
1102 Fs = Spreading Rate
1103 D = Percentage down-spread / 2
1104 Fint = Reference input frequency to PFD = Fref / NR
1105 NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
1106 CLKS = NS - 1 = ISS_STEP_NUM[11:0]
1107 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
1108 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
1109 *************************************
1110 */
1111 pp_atomctrl_internal_ss_info ss_info;
1112 uint32_t freq_nom;
1113 uint32_t tmp;
1114 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
1115
1116 /* for GDDR5 for all modes and DDR3 */
1117 if (1 == mpll_param.qdr)
1118 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
1119 else
1120 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
1121
1122 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
1123 tmp = (freq_nom / reference_clock);
1124 tmp = tmp * tmp;
1125
1126 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
1127 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
1128 /* ss.Info.speed_spectrum_rate -- in unit of khz */
1129 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
1130 /* = reference_clock * 5 / speed_spectrum_rate */
1131 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
1132
1133 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
1134 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
1135 uint32_t clkv =
1136 (uint32_t)((((131 * ss_info.speed_spectrum_percentage *
1137 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
1138
1139 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
1140 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
1141 }
1142 }
1143
1144 /* MCLK_PWRMGT_CNTL setup */
1145 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1146 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1147 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1148 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1149 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1150 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1151
1152
1153 /* Save the result data to outpupt memory level structure */
1154 mclk->MclkFrequency = memory_clock;
1155 mclk->MpllFuncCntl = mpll_func_cntl;
1156 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
1157 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
1158 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
1159 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
1160 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
1161 mclk->DllCntl = dll_cntl;
1162 mclk->MpllSs1 = mpll_ss1;
1163 mclk->MpllSs2 = mpll_ss2;
1164
1165 return 0;
1166}
1167
1168static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock,
1169 bool strobe_mode)
1170{
1171 uint8_t mc_para_index;
1172
1173 if (strobe_mode) {
1174 if (memory_clock < 12500) {
1175 mc_para_index = 0x00;
1176 } else if (memory_clock > 47500) {
1177 mc_para_index = 0x0f;
1178 } else {
1179 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
1180 }
1181 } else {
1182 if (memory_clock < 65000) {
1183 mc_para_index = 0x00;
1184 } else if (memory_clock > 135000) {
1185 mc_para_index = 0x0f;
1186 } else {
1187 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
1188 }
1189 }
1190
1191 return mc_para_index;
1192}
1193
1194static uint8_t iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
1195{
1196 uint8_t mc_para_index;
1197
1198 if (memory_clock < 10000) {
1199 mc_para_index = 0;
1200 } else if (memory_clock >= 80000) {
1201 mc_para_index = 0x0f;
1202 } else {
1203 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
1204 }
1205
1206 return mc_para_index;
1207}
1208
1209static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
1210 uint32_t memory_clock, uint32_t *p_shed)
1211{
1212 unsigned int i;
1213
1214 *p_shed = 1;
1215
1216 for (i = 0; i < pl->count; i++) {
1217 if (memory_clock < pl->entries[i].Mclk) {
1218 *p_shed = i;
1219 break;
1220 }
1221 }
1222
1223 return 0;
1224}
1225
1226static int iceland_populate_single_memory_level(
1227 struct pp_hwmgr *hwmgr,
1228 uint32_t memory_clock,
1229 SMU71_Discrete_MemoryLevel *memory_level
1230 )
1231{
1232 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1233 int result = 0;
1234 bool dll_state_on;
1235 uint32_t mclk_edc_wr_enable_threshold = 40000;
1236 uint32_t mclk_edc_enable_threshold = 40000;
1237 uint32_t mclk_strobe_mode_threshold = 40000;
1238
1239 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
1240 result = iceland_get_dependency_volt_by_clk(hwmgr,
1241 hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
1242 PP_ASSERT_WITH_CODE((0 == result),
1243 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
1244 }
1245
1246 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
1247 memory_level->MinVddci = memory_level->MinVddc;
1248 } else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
1249 result = iceland_get_dependency_volt_by_clk(hwmgr,
1250 hwmgr->dyn_state.vddci_dependency_on_mclk,
1251 memory_clock,
1252 &memory_level->MinVddci);
1253 PP_ASSERT_WITH_CODE((0 == result),
1254 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result);
1255 }
1256
1257 memory_level->MinVddcPhases = 1;
1258
1259 if (data->vddc_phase_shed_control) {
1260 iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
1261 memory_clock, &memory_level->MinVddcPhases);
1262 }
1263
1264 memory_level->EnabledForThrottle = 1;
1265 memory_level->EnabledForActivity = 0;
1266 memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1267 memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1268 memory_level->VoltageDownHyst = 0;
1269
1270 /* Indicates maximum activity level for this performance level.*/
1271 memory_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1272 memory_level->StutterEnable = 0;
1273 memory_level->StrobeEnable = 0;
1274 memory_level->EdcReadEnable = 0;
1275 memory_level->EdcWriteEnable = 0;
1276 memory_level->RttEnable = 0;
1277
1278 /* default set to low watermark. Highest level will be set to high later.*/
1279 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1280
1281 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1282 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1283
1284 /* stutter mode not support on iceland */
1285
1286 /* decide strobe mode*/
1287 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) &&
1288 (memory_clock <= mclk_strobe_mode_threshold);
1289
1290 /* decide EDC mode and memory clock ratio*/
1291 if (data->is_memory_gddr5) {
1292 memory_level->StrobeRatio = iceland_get_mclk_frequency_ratio(memory_clock,
1293 memory_level->StrobeEnable);
1294
1295 if ((mclk_edc_enable_threshold != 0) &&
1296 (memory_clock > mclk_edc_enable_threshold)) {
1297 memory_level->EdcReadEnable = 1;
1298 }
1299
1300 if ((mclk_edc_wr_enable_threshold != 0) &&
1301 (memory_clock > mclk_edc_wr_enable_threshold)) {
1302 memory_level->EdcWriteEnable = 1;
1303 }
1304
1305 if (memory_level->StrobeEnable) {
1306 if (iceland_get_mclk_frequency_ratio(memory_clock, 1) >=
1307 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
1308 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1309 else
1310 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
1311 } else
1312 dll_state_on = data->dll_default_on;
1313 } else {
1314 memory_level->StrobeRatio =
1315 iceland_get_ddr3_mclk_frequency_ratio(memory_clock);
1316 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
1317 }
1318
1319 result = iceland_calculate_mclk_params(hwmgr,
1320 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
1321
1322 if (0 == result) {
1323 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1324 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinVddcPhases);
1325 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1326 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1327 /* MCLK frequency in units of 10KHz*/
1328 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
1329 /* Indicates maximum activity level for this performance level.*/
1330 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
1331 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
1332 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
1333 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
1334 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
1335 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
1336 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
1337 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
1338 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
1339 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
1340 }
1341
1342 return result;
1343}
1344
1345static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1346{
1347 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1348 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1349 struct smu7_dpm_table *dpm_table = &data->dpm_table;
1350 int result;
1351
1352 /* populate MCLK dpm table to SMU7 */
1353 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel);
1354 uint32_t level_array_size = sizeof(SMU71_Discrete_MemoryLevel) * SMU71_MAX_LEVELS_MEMORY;
1355 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel;
1356 uint32_t i;
1357
1358 memset(levels, 0x00, level_array_size);
1359
1360 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1361 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1362 "can not populate memory level as memory clock is zero", return -EINVAL);
1363 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1364 &(smu_data->smc_state_table.MemoryLevel[i]));
1365 if (0 != result) {
1366 return result;
1367 }
1368 }
1369
1370 /* Only enable level 0 for now.*/
1371 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
1372
1373 /*
1374 * in order to prevent MC activity from stutter mode to push DPM up.
1375 * the UVD change complements this by putting the MCLK in a higher state
1376 * by default such that we are not effected by up threshold or and MCLK DPM latency.
1377 */
1378 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F;
1379 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel);
1380
1381 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1382 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1383 /* set highest level watermark to high*/
1384 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1385
1386 /* level count will send to smc once at init smc table and never change*/
1387 result = smu7_copy_bytes_to_smc(hwmgr,
1388 level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
1389 SMC_RAM_END);
1390
1391 return result;
1392}
1393
1394static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
1395 SMU71_Discrete_VoltageLevel *voltage)
1396{
1397 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1398
1399 uint32_t i = 0;
1400
1401 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1402 /* find mvdd value which clock is more than request */
1403 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
1404 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
1405 /* Always round to higher voltage. */
1406 voltage->Voltage = data->mvdd_voltage_table.entries[i].value;
1407 break;
1408 }
1409 }
1410
1411 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
1412 "MVDD Voltage is outside the supported range.", return -EINVAL);
1413
1414 } else {
1415 return -EINVAL;
1416 }
1417
1418 return 0;
1419}
1420
1421static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1422 SMU71_Discrete_DpmTable *table)
1423{
1424 int result = 0;
1425 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1426 struct pp_atomctrl_clock_dividers_vi dividers;
1427 uint32_t vddc_phase_shed_control = 0;
1428
1429 SMU71_Discrete_VoltageLevel voltage_level;
1430 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1431 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1432 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
1433 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
1434
1435
1436 /* The ACPI state should not do DPM on DC (or ever).*/
1437 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1438
1439 if (data->acpi_vddc)
1440 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1441 else
1442 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1443
1444 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1;
1445 /* assign zero for now*/
1446 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1447
1448 /* get the engine clock dividers for this clock value*/
1449 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1450 table->ACPILevel.SclkFrequency, &dividers);
1451
1452 PP_ASSERT_WITH_CODE(result == 0,
1453 "Error retrieving Engine Clock dividers from VBIOS.", return result);
1454
1455 /* divider ID for required SCLK*/
1456 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1457 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1458 table->ACPILevel.DeepSleepDivId = 0;
1459
1460 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1461 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
1462 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
1463 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
1464 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
1465 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
1466
1467 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1468 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1469 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1470 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1471 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1472 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1473 table->ACPILevel.CcPwrDynRm = 0;
1474 table->ACPILevel.CcPwrDynRm1 = 0;
1475
1476
1477 /* For various features to be enabled/disabled while this level is active.*/
1478 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1479 /* SCLK frequency in units of 10KHz*/
1480 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1481 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1482 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1483 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1484 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1485 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1486 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1487 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1488 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1489
1490 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1491 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
1492 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
1493
1494 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1495 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc;
1496 else {
1497 if (data->acpi_vddci != 0)
1498 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1499 else
1500 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE);
1501 }
1502
1503 if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
1504 table->MemoryACPILevel.MinMvdd =
1505 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1506 else
1507 table->MemoryACPILevel.MinMvdd = 0;
1508
1509 /* Force reset on DLL*/
1510 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1511 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1512 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1513 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1514
1515 /* Disable DLL in ACPIState*/
1516 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1517 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1518 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
1519 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
1520
1521 /* Enable DLL bypass signal*/
1522 dll_cntl = PHM_SET_FIELD(dll_cntl,
1523 DLL_CNTL, MRDCK0_BYPASS, 0);
1524 dll_cntl = PHM_SET_FIELD(dll_cntl,
1525 DLL_CNTL, MRDCK1_BYPASS, 0);
1526
1527 table->MemoryACPILevel.DllCntl =
1528 PP_HOST_TO_SMC_UL(dll_cntl);
1529 table->MemoryACPILevel.MclkPwrmgtCntl =
1530 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1531 table->MemoryACPILevel.MpllAdFuncCntl =
1532 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1533 table->MemoryACPILevel.MpllDqFuncCntl =
1534 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1535 table->MemoryACPILevel.MpllFuncCntl =
1536 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1537 table->MemoryACPILevel.MpllFuncCntl_1 =
1538 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1539 table->MemoryACPILevel.MpllFuncCntl_2 =
1540 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
1541 table->MemoryACPILevel.MpllSs1 =
1542 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
1543 table->MemoryACPILevel.MpllSs2 =
1544 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
1545
1546 table->MemoryACPILevel.EnabledForThrottle = 0;
1547 table->MemoryACPILevel.EnabledForActivity = 0;
1548 table->MemoryACPILevel.UpHyst = 0;
1549 table->MemoryACPILevel.DownHyst = 100;
1550 table->MemoryACPILevel.VoltageDownHyst = 0;
1551 /* Indicates maximum activity level for this performance level.*/
1552 table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1553
1554 table->MemoryACPILevel.StutterEnable = 0;
1555 table->MemoryACPILevel.StrobeEnable = 0;
1556 table->MemoryACPILevel.EdcReadEnable = 0;
1557 table->MemoryACPILevel.EdcWriteEnable = 0;
1558 table->MemoryACPILevel.RttEnable = 0;
1559
1560 return result;
1561}
1562
1563static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1564 SMU71_Discrete_DpmTable *table)
1565{
1566 return 0;
1567}
1568
1569static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1570 SMU71_Discrete_DpmTable *table)
1571{
1572 return 0;
1573}
1574
1575static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1576 SMU71_Discrete_DpmTable *table)
1577{
1578 return 0;
1579}
1580
1581static int iceland_populate_memory_timing_parameters(
1582 struct pp_hwmgr *hwmgr,
1583 uint32_t engine_clock,
1584 uint32_t memory_clock,
1585 struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs
1586 )
1587{
1588 uint32_t dramTiming;
1589 uint32_t dramTiming2;
1590 uint32_t burstTime;
1591 int result;
1592
1593 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1594 engine_clock, memory_clock);
1595
1596 PP_ASSERT_WITH_CODE(result == 0,
1597 "Error calling VBIOS to set DRAM_TIMING.", return result);
1598
1599 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1600 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1601 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1602
1603 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
1604 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
1605 arb_regs->McArbBurstTime = (uint8_t)burstTime;
1606
1607 return 0;
1608}
1609
1610static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1611{
1612 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1613 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1614 int result = 0;
1615 SMU71_Discrete_MCArbDramTimingTable arb_regs;
1616 uint32_t i, j;
1617
1618 memset(&arb_regs, 0x00, sizeof(SMU71_Discrete_MCArbDramTimingTable));
1619
1620 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1621 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1622 result = iceland_populate_memory_timing_parameters
1623 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1624 data->dpm_table.mclk_table.dpm_levels[j].value,
1625 &arb_regs.entries[i][j]);
1626
1627 if (0 != result) {
1628 break;
1629 }
1630 }
1631 }
1632
1633 if (0 == result) {
1634 result = smu7_copy_bytes_to_smc(
1635 hwmgr,
1636 smu_data->smu7_data.arb_table_start,
1637 (uint8_t *)&arb_regs,
1638 sizeof(SMU71_Discrete_MCArbDramTimingTable),
1639 SMC_RAM_END
1640 );
1641 }
1642
1643 return result;
1644}
1645
1646static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1647 SMU71_Discrete_DpmTable *table)
1648{
1649 int result = 0;
1650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1651 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1652 table->GraphicsBootLevel = 0;
1653 table->MemoryBootLevel = 0;
1654
1655 /* find boot level from dpm table*/
1656 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1657 data->vbios_boot_state.sclk_bootup_value,
1658 (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel));
1659
1660 if (0 != result) {
1661 smu_data->smc_state_table.GraphicsBootLevel = 0;
1662 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
1663 result = 0;
1664 }
1665
1666 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1667 data->vbios_boot_state.mclk_bootup_value,
1668 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel));
1669
1670 if (0 != result) {
1671 smu_data->smc_state_table.MemoryBootLevel = 0;
1672 pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
1673 result = 0;
1674 }
1675
1676 table->BootVddc = data->vbios_boot_state.vddc_bootup_value;
1677 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
1678 table->BootVddci = table->BootVddc;
1679 else
1680 table->BootVddci = data->vbios_boot_state.vddci_bootup_value;
1681
1682 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1683
1684 return result;
1685}
1686
1687static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
1688 SMU71_Discrete_MCRegisters *mc_reg_table)
1689{
1690 const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
1691
1692 uint32_t i, j;
1693
1694 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) {
1695 if (smu_data->mc_reg_table.validflag & 1<<j) {
1696 PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE,
1697 "Index of mc_reg_table->address[] array out of boundary", return -EINVAL);
1698 mc_reg_table->address[i].s0 =
1699 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0);
1700 mc_reg_table->address[i].s1 =
1701 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1);
1702 i++;
1703 }
1704 }
1705
1706 mc_reg_table->last = (uint8_t)i;
1707
1708 return 0;
1709}
1710
1711/*convert register values from driver to SMC format */
1712static void iceland_convert_mc_registers(
1713 const struct iceland_mc_reg_entry *entry,
1714 SMU71_Discrete_MCRegisterSet *data,
1715 uint32_t num_entries, uint32_t valid_flag)
1716{
1717 uint32_t i, j;
1718
1719 for (i = 0, j = 0; j < num_entries; j++) {
1720 if (valid_flag & 1<<j) {
1721 data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]);
1722 i++;
1723 }
1724 }
1725}
1726
1727static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
1728 const uint32_t memory_clock,
1729 SMU71_Discrete_MCRegisterSet *mc_reg_table_data
1730 )
1731{
1732 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1733 uint32_t i = 0;
1734
1735 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
1736 if (memory_clock <=
1737 smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) {
1738 break;
1739 }
1740 }
1741
1742 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0))
1743 --i;
1744
1745 iceland_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i],
1746 mc_reg_table_data, smu_data->mc_reg_table.last,
1747 smu_data->mc_reg_table.validflag);
1748
1749 return 0;
1750}
1751
1752static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
1753 SMU71_Discrete_MCRegisters *mc_regs)
1754{
1755 int result = 0;
1756 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1757 int res;
1758 uint32_t i;
1759
1760 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1761 res = iceland_convert_mc_reg_table_entry_to_smc(
1762 hwmgr,
1763 data->dpm_table.mclk_table.dpm_levels[i].value,
1764 &mc_regs->data[i]
1765 );
1766
1767 if (0 != res)
1768 result = res;
1769 }
1770
1771 return result;
1772}
1773
1774static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
1775{
1776 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1777 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1778 uint32_t address;
1779 int32_t result;
1780
1781 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
1782 return 0;
1783
1784
1785 memset(&smu_data->mc_regs, 0, sizeof(SMU71_Discrete_MCRegisters));
1786
1787 result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
1788
1789 if (result != 0)
1790 return result;
1791
1792
1793 address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
1794
1795 return smu7_copy_bytes_to_smc(hwmgr, address,
1796 (uint8_t *)&smu_data->mc_regs.data[0],
1797 sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
1798 SMC_RAM_END);
1799}
1800
1801static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
1802{
1803 int result;
1804 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1805
1806 memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
1807 result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
1808 PP_ASSERT_WITH_CODE(0 == result,
1809 "Failed to initialize MCRegTable for the MC register addresses!", return result;);
1810
1811 result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
1812 PP_ASSERT_WITH_CODE(0 == result,
1813 "Failed to initialize MCRegTable for driver state!", return result;);
1814
1815 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
1816 (uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
1817}
1818
1819static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1820{
1821 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1822 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1823 uint8_t count, level;
1824
1825 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
1826
1827 for (level = 0; level < count; level++) {
1828 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
1829 >= data->vbios_boot_state.sclk_bootup_value) {
1830 smu_data->smc_state_table.GraphicsBootLevel = level;
1831 break;
1832 }
1833 }
1834
1835 count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
1836
1837 for (level = 0; level < count; level++) {
1838 if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
1839 >= data->vbios_boot_state.mclk_bootup_value) {
1840 smu_data->smc_state_table.MemoryBootLevel = level;
1841 break;
1842 }
1843 }
1844
1845 return 0;
1846}
1847
1848static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1849{
1850 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1851 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1852 const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
1853 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table);
1854 struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
1855 struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
1856 const uint16_t *def1, *def2;
1857 int i, j, k;
1858
1859
1860 /*
1861 * TDP number of fraction bits are changed from 8 to 7 for Iceland
1862 * as requested by SMC team
1863 */
1864
1865 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
1866 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
1867
1868
1869 dpm_table->DTETjOffset = 0;
1870
1871 dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
1872 dpm_table->GpuTjHyst = 8;
1873
1874 dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
1875
1876 /* The following are for new Iceland Multi-input fan/thermal control */
1877 if (NULL != ppm) {
1878 dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
1879 dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
1880 } else {
1881 dpm_table->PPM_PkgPwrLimit = 0;
1882 dpm_table->PPM_TemperatureLimit = 0;
1883 }
1884
1885 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
1886 CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
1887
1888 dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1889 def1 = defaults->bapmti_r;
1890 def2 = defaults->bapmti_rc;
1891
1892 for (i = 0; i < SMU71_DTE_ITERATIONS; i++) {
1893 for (j = 0; j < SMU71_DTE_SOURCES; j++) {
1894 for (k = 0; k < SMU71_DTE_SINKS; k++) {
1895 dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
1896 dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
1897 def1++;
1898 def2++;
1899 }
1900 }
1901 }
1902
1903 return 0;
1904}
1905
1906static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
1907 SMU71_Discrete_DpmTable *tab)
1908{
1909 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1910
1911 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control)
1912 tab->SVI2Enable |= VDDC_ON_SVI2;
1913
1914 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1915 tab->SVI2Enable |= VDDCI_ON_SVI2;
1916 else
1917 tab->MergedVddci = 1;
1918
1919 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control)
1920 tab->SVI2Enable |= MVDD_ON_SVI2;
1921
1922 PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) &&
1923 (tab->SVI2Enable & VDDC_ON_SVI2), "SVI2 domain configuration is incorrect!", return -EINVAL);
1924
1925 return 0;
1926}
1927
1928static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
1929{
1930 int result;
1931 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1932 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
1933 SMU71_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1934
1935
1936 iceland_initialize_power_tune_defaults(hwmgr);
1937 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table));
1938
1939 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) {
1940 iceland_populate_smc_voltage_tables(hwmgr, table);
1941 }
1942
1943 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1944 PHM_PlatformCaps_AutomaticDCTransition))
1945 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1946
1947
1948 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1949 PHM_PlatformCaps_StepVddc))
1950 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1951
1952 if (data->is_memory_gddr5)
1953 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1954
1955
1956 if (data->ulv_supported) {
1957 result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
1958 PP_ASSERT_WITH_CODE(0 == result,
1959 "Failed to initialize ULV state!", return result;);
1960
1961 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1962 ixCG_ULV_PARAMETER, 0x40035);
1963 }
1964
1965 result = iceland_populate_smc_link_level(hwmgr, table);
1966 PP_ASSERT_WITH_CODE(0 == result,
1967 "Failed to initialize Link Level!", return result;);
1968
1969 result = iceland_populate_all_graphic_levels(hwmgr);
1970 PP_ASSERT_WITH_CODE(0 == result,
1971 "Failed to initialize Graphics Level!", return result;);
1972
1973 result = iceland_populate_all_memory_levels(hwmgr);
1974 PP_ASSERT_WITH_CODE(0 == result,
1975 "Failed to initialize Memory Level!", return result;);
1976
1977 result = iceland_populate_smc_acpi_level(hwmgr, table);
1978 PP_ASSERT_WITH_CODE(0 == result,
1979 "Failed to initialize ACPI Level!", return result;);
1980
1981 result = iceland_populate_smc_vce_level(hwmgr, table);
1982 PP_ASSERT_WITH_CODE(0 == result,
1983 "Failed to initialize VCE Level!", return result;);
1984
1985 result = iceland_populate_smc_acp_level(hwmgr, table);
1986 PP_ASSERT_WITH_CODE(0 == result,
1987 "Failed to initialize ACP Level!", return result;);
1988
1989 /* Since only the initial state is completely set up at this point (the other states are just copies of the boot state) we only */
1990 /* need to populate the ARB settings for the initial state. */
1991 result = iceland_program_memory_timing_parameters(hwmgr);
1992 PP_ASSERT_WITH_CODE(0 == result,
1993 "Failed to Write ARB settings for the initial state.", return result;);
1994
1995 result = iceland_populate_smc_uvd_level(hwmgr, table);
1996 PP_ASSERT_WITH_CODE(0 == result,
1997 "Failed to initialize UVD Level!", return result;);
1998
1999 table->GraphicsBootLevel = 0;
2000 table->MemoryBootLevel = 0;
2001
2002 result = iceland_populate_smc_boot_level(hwmgr, table);
2003 PP_ASSERT_WITH_CODE(0 == result,
2004 "Failed to initialize Boot Level!", return result;);
2005
2006 result = iceland_populate_smc_initial_state(hwmgr);
2007 PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result);
2008
2009 result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
2010 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result);
2011
2012 table->GraphicsVoltageChangeEnable = 1;
2013 table->GraphicsThermThrottleEnable = 1;
2014 table->GraphicsInterval = 1;
2015 table->VoltageInterval = 1;
2016 table->ThermalInterval = 1;
2017
2018 table->TemperatureLimitHigh =
2019 (data->thermal_temp_setting.temperature_high *
2020 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2021 table->TemperatureLimitLow =
2022 (data->thermal_temp_setting.temperature_low *
2023 SMU7_Q88_FORMAT_CONVERSION_UNIT) / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2024
2025 table->MemoryVoltageChangeEnable = 1;
2026 table->MemoryInterval = 1;
2027 table->VoltageResponseTime = 0;
2028 table->PhaseResponseTime = 0;
2029 table->MemoryThermThrottleEnable = 1;
2030 table->PCIeBootLinkLevel = 0;
2031 table->PCIeGenInterval = 1;
2032
2033 result = iceland_populate_smc_svi2_config(hwmgr, table);
2034 PP_ASSERT_WITH_CODE(0 == result,
2035 "Failed to populate SVI2 setting!", return result);
2036
2037 table->ThermGpio = 17;
2038 table->SclkStepSize = 0x4000;
2039
2040 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2041 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid);
2042 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase);
2043 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid);
2044 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid);
2045 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2046 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2047 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2048 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2049 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2050
2051 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE);
2052 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE);
2053 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
2054
2055 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2056 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
2057 offsetof(SMU71_Discrete_DpmTable, SystemFlags),
2058 (uint8_t *)&(table->SystemFlags),
2059 sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
2060 SMC_RAM_END);
2061
2062 PP_ASSERT_WITH_CODE(0 == result,
2063 "Failed to upload dpm data to SMC memory!", return result;);
2064
2065 /* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
2066 result = smu7_copy_bytes_to_smc(hwmgr,
2067 smu_data->smu7_data.ulv_setting_starts,
2068 (uint8_t *)&(smu_data->ulv_setting),
2069 sizeof(SMU71_Discrete_Ulv),
2070 SMC_RAM_END);
2071
2072
2073 result = iceland_populate_initial_mc_reg_table(hwmgr);
2074 PP_ASSERT_WITH_CODE((0 == result),
2075 "Failed to populate initialize MC Reg table!", return result);
2076
2077 result = iceland_populate_pm_fuses(hwmgr);
2078 PP_ASSERT_WITH_CODE(0 == result,
2079 "Failed to populate PM fuses to SMC memory!", return result);
2080
2081 return 0;
2082}
2083
2084int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2085{
2086 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2087 SMU71_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2088 uint32_t duty100;
2089 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2090 uint16_t fdo_min, slope1, slope2;
2091 uint32_t reference_clock;
2092 int res;
2093 uint64_t tmp64;
2094
2095 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2096 return 0;
2097
2098 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2099 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2100 PHM_PlatformCaps_MicrocodeFanControl);
2101 return 0;
2102 }
2103
2104 if (0 == smu7_data->fan_table_start) {
2105 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2106 return 0;
2107 }
2108
2109 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
2110
2111 if (0 == duty100) {
2112 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2113 return 0;
2114 }
2115
2116 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
2117 do_div(tmp64, 10000);
2118 fdo_min = (uint16_t)tmp64;
2119
2120 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2121 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2122
2123 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2124 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2125
2126 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2127 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2128
2129 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
2130 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
2131 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
2132
2133 fan_table.Slope1 = cpu_to_be16(slope1);
2134 fan_table.Slope2 = cpu_to_be16(slope2);
2135
2136 fan_table.FdoMin = cpu_to_be16(fdo_min);
2137
2138 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
2139
2140 fan_table.HystUp = cpu_to_be16(1);
2141
2142 fan_table.HystSlope = cpu_to_be16(1);
2143
2144 fan_table.TempRespLim = cpu_to_be16(5);
2145
2146 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2147
2148 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
2149
2150 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2151
2152 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
2153
2154 /* fan_table.FanControl_GL_Flag = 1; */
2155
2156 res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
2157
2158 return 0;
2159}
2160
2161
2162static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2163{
2164 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2165
2166 if (data->need_update_smu7_dpm_table &
2167 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2168 return iceland_program_memory_timing_parameters(hwmgr);
2169
2170 return 0;
2171}
2172
2173static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2174{
2175 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2176 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2177
2178 int result = 0;
2179 uint32_t low_sclk_interrupt_threshold = 0;
2180
2181 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2182 PHM_PlatformCaps_SclkThrottleLowNotification)
2183 && (data->low_sclk_interrupt_threshold != 0)) {
2184 low_sclk_interrupt_threshold =
2185 data->low_sclk_interrupt_threshold;
2186
2187 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2188
2189 result = smu7_copy_bytes_to_smc(
2190 hwmgr,
2191 smu_data->smu7_data.dpm_table_start +
2192 offsetof(SMU71_Discrete_DpmTable,
2193 LowSclkInterruptThreshold),
2194 (uint8_t *)&low_sclk_interrupt_threshold,
2195 sizeof(uint32_t),
2196 SMC_RAM_END);
2197 }
2198
2199 result = iceland_update_and_upload_mc_reg_table(hwmgr);
2200
2201 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result);
2202
2203 result = iceland_program_mem_timing_parameters(hwmgr);
2204 PP_ASSERT_WITH_CODE((result == 0),
2205 "Failed to program memory timing parameters!",
2206 );
2207
2208 return result;
2209}
2210
2211static uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
2212{
2213 switch (type) {
2214 case SMU_SoftRegisters:
2215 switch (member) {
2216 case HandshakeDisables:
2217 return offsetof(SMU71_SoftRegisters, HandshakeDisables);
2218 case VoltageChangeTimeout:
2219 return offsetof(SMU71_SoftRegisters, VoltageChangeTimeout);
2220 case AverageGraphicsActivity:
2221 return offsetof(SMU71_SoftRegisters, AverageGraphicsActivity);
2222 case PreVBlankGap:
2223 return offsetof(SMU71_SoftRegisters, PreVBlankGap);
2224 case VBlankTimeout:
2225 return offsetof(SMU71_SoftRegisters, VBlankTimeout);
2226 case UcodeLoadStatus:
2227 return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
2228 case DRAM_LOG_ADDR_H:
2229 return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
2230 case DRAM_LOG_ADDR_L:
2231 return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
2232 case DRAM_LOG_PHY_ADDR_H:
2233 return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2234 case DRAM_LOG_PHY_ADDR_L:
2235 return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2236 case DRAM_LOG_BUFF_SIZE:
2237 return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2238 }
2239 break;
2240 case SMU_Discrete_DpmTable:
2241 switch (member) {
2242 case LowSclkInterruptThreshold:
2243 return offsetof(SMU71_Discrete_DpmTable, LowSclkInterruptThreshold);
2244 }
2245 break;
2246 }
2247 pr_warn("can't get the offset of type %x member %x\n", type, member);
2248 return 0;
2249}
2250
2251static uint32_t iceland_get_mac_definition(uint32_t value)
2252{
2253 switch (value) {
2254 case SMU_MAX_LEVELS_GRAPHICS:
2255 return SMU71_MAX_LEVELS_GRAPHICS;
2256 case SMU_MAX_LEVELS_MEMORY:
2257 return SMU71_MAX_LEVELS_MEMORY;
2258 case SMU_MAX_LEVELS_LINK:
2259 return SMU71_MAX_LEVELS_LINK;
2260 case SMU_MAX_ENTRIES_SMIO:
2261 return SMU71_MAX_ENTRIES_SMIO;
2262 case SMU_MAX_LEVELS_VDDC:
2263 return SMU71_MAX_LEVELS_VDDC;
2264 case SMU_MAX_LEVELS_VDDCI:
2265 return SMU71_MAX_LEVELS_VDDCI;
2266 case SMU_MAX_LEVELS_MVDD:
2267 return SMU71_MAX_LEVELS_MVDD;
2268 }
2269
2270 pr_warn("can't get the mac of %x\n", value);
2271 return 0;
2272}
2273
2274static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
2275{
2276 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2277 struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2278
2279 uint32_t tmp;
2280 int result;
2281 bool error = false;
2282
2283 result = smu7_read_smc_sram_dword(hwmgr,
2284 SMU71_FIRMWARE_HEADER_LOCATION +
2285 offsetof(SMU71_Firmware_Header, DpmTable),
2286 &tmp, SMC_RAM_END);
2287
2288 if (0 == result) {
2289 smu7_data->dpm_table_start = tmp;
2290 }
2291
2292 error |= (0 != result);
2293
2294 result = smu7_read_smc_sram_dword(hwmgr,
2295 SMU71_FIRMWARE_HEADER_LOCATION +
2296 offsetof(SMU71_Firmware_Header, SoftRegisters),
2297 &tmp, SMC_RAM_END);
2298
2299 if (0 == result) {
2300 data->soft_regs_start = tmp;
2301 smu7_data->soft_regs_start = tmp;
2302 }
2303
2304 error |= (0 != result);
2305
2306
2307 result = smu7_read_smc_sram_dword(hwmgr,
2308 SMU71_FIRMWARE_HEADER_LOCATION +
2309 offsetof(SMU71_Firmware_Header, mcRegisterTable),
2310 &tmp, SMC_RAM_END);
2311
2312 if (0 == result) {
2313 smu7_data->mc_reg_table_start = tmp;
2314 }
2315
2316 result = smu7_read_smc_sram_dword(hwmgr,
2317 SMU71_FIRMWARE_HEADER_LOCATION +
2318 offsetof(SMU71_Firmware_Header, FanTable),
2319 &tmp, SMC_RAM_END);
2320
2321 if (0 == result) {
2322 smu7_data->fan_table_start = tmp;
2323 }
2324
2325 error |= (0 != result);
2326
2327 result = smu7_read_smc_sram_dword(hwmgr,
2328 SMU71_FIRMWARE_HEADER_LOCATION +
2329 offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
2330 &tmp, SMC_RAM_END);
2331
2332 if (0 == result) {
2333 smu7_data->arb_table_start = tmp;
2334 }
2335
2336 error |= (0 != result);
2337
2338
2339 result = smu7_read_smc_sram_dword(hwmgr,
2340 SMU71_FIRMWARE_HEADER_LOCATION +
2341 offsetof(SMU71_Firmware_Header, Version),
2342 &tmp, SMC_RAM_END);
2343
2344 if (0 == result) {
2345 hwmgr->microcode_version_info.SMC = tmp;
2346 }
2347
2348 error |= (0 != result);
2349
2350 result = smu7_read_smc_sram_dword(hwmgr,
2351 SMU71_FIRMWARE_HEADER_LOCATION +
2352 offsetof(SMU71_Firmware_Header, UlvSettings),
2353 &tmp, SMC_RAM_END);
2354
2355 if (0 == result) {
2356 smu7_data->ulv_setting_starts = tmp;
2357 }
2358
2359 error |= (0 != result);
2360
2361 return error ? 1 : 0;
2362}
2363
2364/*---------------------------MC----------------------------*/
2365
2366static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2367{
2368 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2369}
2370
2371static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
2372{
2373 bool result = true;
2374
2375 switch (in_reg) {
2376 case mmMC_SEQ_RAS_TIMING:
2377 *out_reg = mmMC_SEQ_RAS_TIMING_LP;
2378 break;
2379
2380 case mmMC_SEQ_DLL_STBY:
2381 *out_reg = mmMC_SEQ_DLL_STBY_LP;
2382 break;
2383
2384 case mmMC_SEQ_G5PDX_CMD0:
2385 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
2386 break;
2387
2388 case mmMC_SEQ_G5PDX_CMD1:
2389 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
2390 break;
2391
2392 case mmMC_SEQ_G5PDX_CTRL:
2393 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
2394 break;
2395
2396 case mmMC_SEQ_CAS_TIMING:
2397 *out_reg = mmMC_SEQ_CAS_TIMING_LP;
2398 break;
2399
2400 case mmMC_SEQ_MISC_TIMING:
2401 *out_reg = mmMC_SEQ_MISC_TIMING_LP;
2402 break;
2403
2404 case mmMC_SEQ_MISC_TIMING2:
2405 *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
2406 break;
2407
2408 case mmMC_SEQ_PMG_DVS_CMD:
2409 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
2410 break;
2411
2412 case mmMC_SEQ_PMG_DVS_CTL:
2413 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
2414 break;
2415
2416 case mmMC_SEQ_RD_CTL_D0:
2417 *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
2418 break;
2419
2420 case mmMC_SEQ_RD_CTL_D1:
2421 *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
2422 break;
2423
2424 case mmMC_SEQ_WR_CTL_D0:
2425 *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
2426 break;
2427
2428 case mmMC_SEQ_WR_CTL_D1:
2429 *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
2430 break;
2431
2432 case mmMC_PMG_CMD_EMRS:
2433 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
2434 break;
2435
2436 case mmMC_PMG_CMD_MRS:
2437 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
2438 break;
2439
2440 case mmMC_PMG_CMD_MRS1:
2441 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
2442 break;
2443
2444 case mmMC_SEQ_PMG_TIMING:
2445 *out_reg = mmMC_SEQ_PMG_TIMING_LP;
2446 break;
2447
2448 case mmMC_PMG_CMD_MRS2:
2449 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
2450 break;
2451
2452 case mmMC_SEQ_WR_CTL_2:
2453 *out_reg = mmMC_SEQ_WR_CTL_2_LP;
2454 break;
2455
2456 default:
2457 result = false;
2458 break;
2459 }
2460
2461 return result;
2462}
2463
2464static int iceland_set_s0_mc_reg_index(struct iceland_mc_reg_table *table)
2465{
2466 uint32_t i;
2467 uint16_t address;
2468
2469 for (i = 0; i < table->last; i++) {
2470 table->mc_reg_address[i].s0 =
2471 iceland_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address)
2472 ? address : table->mc_reg_address[i].s1;
2473 }
2474 return 0;
2475}
2476
2477static int iceland_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2478 struct iceland_mc_reg_table *ni_table)
2479{
2480 uint8_t i, j;
2481
2482 PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2483 "Invalid VramInfo table.", return -EINVAL);
2484 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2485 "Invalid VramInfo table.", return -EINVAL);
2486
2487 for (i = 0; i < table->last; i++) {
2488 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2489 }
2490 ni_table->last = table->last;
2491
2492 for (i = 0; i < table->num_entries; i++) {
2493 ni_table->mc_reg_table_entry[i].mclk_max =
2494 table->mc_reg_table_entry[i].mclk_max;
2495 for (j = 0; j < table->last; j++) {
2496 ni_table->mc_reg_table_entry[i].mc_data[j] =
2497 table->mc_reg_table_entry[i].mc_data[j];
2498 }
2499 }
2500
2501 ni_table->num_entries = table->num_entries;
2502
2503 return 0;
2504}
2505
2506static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
2507 struct iceland_mc_reg_table *table)
2508{
2509 uint8_t i, j, k;
2510 uint32_t temp_reg;
2511 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2512
2513 for (i = 0, j = table->last; i < table->last; i++) {
2514 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2515 "Invalid VramInfo table.", return -EINVAL);
2516
2517 switch (table->mc_reg_address[i].s1) {
2518
2519 case mmMC_SEQ_MISC1:
2520 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
2521 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2522 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2523 for (k = 0; k < table->num_entries; k++) {
2524 table->mc_reg_table_entry[k].mc_data[j] =
2525 ((temp_reg & 0xffff0000)) |
2526 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2527 }
2528 j++;
2529
2530 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2531 "Invalid VramInfo table.", return -EINVAL);
2532 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
2533 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
2534 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
2535 for (k = 0; k < table->num_entries; k++) {
2536 table->mc_reg_table_entry[k].mc_data[j] =
2537 (temp_reg & 0xffff0000) |
2538 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2539
2540 if (!data->is_memory_gddr5) {
2541 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2542 }
2543 }
2544 j++;
2545
2546 if (!data->is_memory_gddr5) {
2547 PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2548 "Invalid VramInfo table.", return -EINVAL);
2549 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
2550 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
2551 for (k = 0; k < table->num_entries; k++) {
2552 table->mc_reg_table_entry[k].mc_data[j] =
2553 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
2554 }
2555 j++;
2556 }
2557
2558 break;
2559
2560 case mmMC_SEQ_RESERVE_M:
2561 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
2562 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
2563 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
2564 for (k = 0; k < table->num_entries; k++) {
2565 table->mc_reg_table_entry[k].mc_data[j] =
2566 (temp_reg & 0xffff0000) |
2567 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2568 }
2569 j++;
2570 break;
2571
2572 default:
2573 break;
2574 }
2575
2576 }
2577
2578 table->last = j;
2579
2580 return 0;
2581}
2582
2583static int iceland_set_valid_flag(struct iceland_mc_reg_table *table)
2584{
2585 uint8_t i, j;
2586 for (i = 0; i < table->last; i++) {
2587 for (j = 1; j < table->num_entries; j++) {
2588 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
2589 table->mc_reg_table_entry[j].mc_data[i]) {
2590 table->validflag |= (1<<i);
2591 break;
2592 }
2593 }
2594 }
2595
2596 return 0;
2597}
2598
2599static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2600{
2601 int result;
2602 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
2603 pp_atomctrl_mc_reg_table *table;
2604 struct iceland_mc_reg_table *ni_table = &smu_data->mc_reg_table;
2605 uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
2606
2607 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
2608
2609 if (NULL == table)
2610 return -ENOMEM;
2611
2612 /* Program additional LP registers that are no longer programmed by VBIOS */
2613 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2614 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2615 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
2616 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
2617 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
2618 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
2619 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
2620 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
2621 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
2622 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2623 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
2624 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
2625 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
2626 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
2627 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2628 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2629 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2630 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2631 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
2632 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
2633
2634 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table));
2635
2636 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
2637
2638 if (0 == result)
2639 result = iceland_copy_vbios_smc_reg_table(table, ni_table);
2640
2641 if (0 == result) {
2642 iceland_set_s0_mc_reg_index(ni_table);
2643 result = iceland_set_mc_special_registers(hwmgr, ni_table);
2644 }
2645
2646 if (0 == result)
2647 iceland_set_valid_flag(ni_table);
2648
2649 kfree(table);
2650
2651 return result;
2652}
2653
2654static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
2655{
2656 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2657 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2658 ? true : false;
2659}
2660
2661const struct pp_smumgr_func iceland_smu_funcs = {
2662 .smu_init = &iceland_smu_init,
2663 .smu_fini = &smu7_smu_fini,
2664 .start_smu = &iceland_start_smu,
2665 .check_fw_load_finish = &smu7_check_fw_load_finish,
2666 .request_smu_load_fw = &smu7_request_smu_load_fw,
2667 .request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
2668 .send_msg_to_smc = &smu7_send_msg_to_smc,
2669 .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2670 .download_pptable_settings = NULL,
2671 .upload_pptable_settings = NULL,
2672 .get_offsetof = iceland_get_offsetof,
2673 .process_firmware_header = iceland_process_firmware_header,
2674 .init_smc_table = iceland_init_smc_table,
2675 .update_sclk_threshold = iceland_update_sclk_threshold,
2676 .thermal_setup_fan_table = iceland_thermal_setup_fan_table,
2677 .populate_all_graphic_levels = iceland_populate_all_graphic_levels,
2678 .populate_all_memory_levels = iceland_populate_all_memory_levels,
2679 .get_mac_definition = iceland_get_mac_definition,
2680 .initialize_mc_reg_table = iceland_initialize_mc_reg_table,
2681 .is_dpm_running = iceland_is_dpm_running,
2682};
2683
2684