1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _VEGAM_SMUMANAGER_H
25#define _VEGAM_SMUMANAGER_H
26
27
28#include <pp_endian.h>
29#include "smu75_discrete.h"
30#include "smu7_smumgr.h"
31
32#define SMC_RAM_END 0x40000
33
34#define DPMTuning_Uphyst_Shift 0
35#define DPMTuning_Downhyst_Shift 8
36#define DPMTuning_Activity_Shift 16
37
38#define GraphicsDPMTuning_VEGAM 0x001e6400
39#define MemoryDPMTuning_VEGAM 0x000f3c0a
40#define SclkDPMTuning_VEGAM 0x002d000a
41#define MclkDPMTuning_VEGAM 0x001f100a
42
43
44struct vegam_pt_defaults {
45 uint8_t SviLoadLineEn;
46 uint8_t SviLoadLineVddC;
47 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
48 uint8_t TDC_MAWt;
49 uint8_t TdcWaterfallCtl;
50 uint8_t DTEAmbientTempBase;
51
52 uint32_t DisplayCac;
53 uint32_t BAPM_TEMP_GRADIENT;
54 uint16_t BAPMTI_R[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
55 uint16_t BAPMTI_RC[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
56};
57
58struct vegam_range_table {
59 uint32_t trans_lower_frequency; /* in 10khz */
60 uint32_t trans_upper_frequency;
61};
62
63struct vegam_smumgr {
64 struct smu7_smumgr smu7_data;
65 uint8_t protected_mode;
66 SMU75_Discrete_DpmTable smc_state_table;
67 struct SMU75_Discrete_Ulv ulv_setting;
68 struct SMU75_Discrete_PmFuses power_tune_table;
69 struct vegam_range_table range_table[NUM_SCLK_RANGE];
70 const struct vegam_pt_defaults *power_tune_defaults;
71 uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK];
72};
73
74
75#endif
76