1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/acpi.h>
31#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/vt.h>
42#include <acpi/video.h>
43
44#include <drm/drm_atomic_helper.h>
45#include <drm/drm_ioctl.h>
46#include <drm/drm_irq.h>
47#include <drm/drm_probe_helper.h>
48#include <drm/i915_drm.h>
49
50#include "i915_drv.h"
51#include "i915_trace.h"
52#include "i915_pmu.h"
53#include "i915_reset.h"
54#include "i915_query.h"
55#include "i915_vgpu.h"
56#include "intel_drv.h"
57#include "intel_uc.h"
58#include "intel_workarounds.h"
59
60static struct drm_driver driver;
61
62#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
63static unsigned int i915_load_fail_count;
64
65bool __i915_inject_load_failure(const char *func, int line)
66{
67 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
68 return false;
69
70 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
71 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
72 i915_modparams.inject_load_failure, func, line);
73 i915_modparams.inject_load_failure = 0;
74 return true;
75 }
76
77 return false;
78}
79
80bool i915_error_injected(void)
81{
82 return i915_load_fail_count && !i915_modparams.inject_load_failure;
83}
84
85#endif
86
87#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
88#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
89 "providing the dmesg log by booting with drm.debug=0xf"
90
91void
92__i915_printk(struct drm_i915_private *dev_priv, const char *level,
93 const char *fmt, ...)
94{
95 static bool shown_bug_once;
96 struct device *kdev = dev_priv->drm.dev;
97 bool is_error = level[1] <= KERN_ERR[1];
98 bool is_debug = level[1] == KERN_DEBUG[1];
99 struct va_format vaf;
100 va_list args;
101
102 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
103 return;
104
105 va_start(args, fmt);
106
107 vaf.fmt = fmt;
108 vaf.va = &args;
109
110 if (is_error)
111 dev_printk(level, kdev, "%pV", &vaf);
112 else
113 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
114 __builtin_return_address(0), &vaf);
115
116 va_end(args);
117
118 if (is_error && !shown_bug_once) {
119 /*
120 * Ask the user to file a bug report for the error, except
121 * if they may have caused the bug by fiddling with unsafe
122 * module parameters.
123 */
124 if (!test_taint(TAINT_USER))
125 dev_notice(kdev, "%s", FDO_BUG_MSG);
126 shown_bug_once = true;
127 }
128}
129
130/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
131static enum intel_pch
132intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
133{
134 switch (id) {
135 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
136 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
137 WARN_ON(!IS_GEN(dev_priv, 5));
138 return PCH_IBX;
139 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
140 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
141 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
142 return PCH_CPT;
143 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
144 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
145 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
146 /* PantherPoint is CPT compatible */
147 return PCH_CPT;
148 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
149 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
150 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
151 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
152 return PCH_LPT;
153 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
154 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
155 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
156 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
157 return PCH_LPT;
158 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
159 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
160 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
161 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
162 /* WildcatPoint is LPT compatible */
163 return PCH_LPT;
164 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
165 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
166 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
167 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
168 /* WildcatPoint is LPT compatible */
169 return PCH_LPT;
170 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
171 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
172 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
173 return PCH_SPT;
174 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
175 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
176 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
177 return PCH_SPT;
178 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
179 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
180 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
181 !IS_COFFEELAKE(dev_priv));
182 return PCH_KBP;
183 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
184 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
185 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
186 return PCH_CNP;
187 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
188 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
189 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
190 return PCH_CNP;
191 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
192 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
193 WARN_ON(!IS_ICELAKE(dev_priv));
194 return PCH_ICP;
195 default:
196 return PCH_NONE;
197 }
198}
199
200static bool intel_is_virt_pch(unsigned short id,
201 unsigned short svendor, unsigned short sdevice)
202{
203 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
204 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
205 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
206 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
207 sdevice == PCI_SUBDEVICE_ID_QEMU));
208}
209
210static unsigned short
211intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
212{
213 unsigned short id = 0;
214
215 /*
216 * In a virtualized passthrough environment we can be in a
217 * setup where the ISA bridge is not able to be passed through.
218 * In this case, a south bridge can be emulated and we have to
219 * make an educated guess as to which PCH is really there.
220 */
221
222 if (IS_GEN(dev_priv, 5))
223 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
224 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
225 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
226 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
227 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
228 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
229 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
230 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
231 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
232 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
233 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
234 else if (IS_ICELAKE(dev_priv))
235 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
236
237 if (id)
238 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
239 else
240 DRM_DEBUG_KMS("Assuming no PCH\n");
241
242 return id;
243}
244
245static void intel_detect_pch(struct drm_i915_private *dev_priv)
246{
247 struct pci_dev *pch = NULL;
248
249 /*
250 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
251 * make graphics device passthrough work easy for VMM, that only
252 * need to expose ISA bridge to let driver know the real hardware
253 * underneath. This is a requirement from virtualization team.
254 *
255 * In some virtualized environments (e.g. XEN), there is irrelevant
256 * ISA bridge in the system. To work reliably, we should scan trhough
257 * all the ISA bridge devices and check for the first match, instead
258 * of only checking the first one.
259 */
260 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
261 unsigned short id;
262 enum intel_pch pch_type;
263
264 if (pch->vendor != PCI_VENDOR_ID_INTEL)
265 continue;
266
267 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
268
269 pch_type = intel_pch_type(dev_priv, id);
270 if (pch_type != PCH_NONE) {
271 dev_priv->pch_type = pch_type;
272 dev_priv->pch_id = id;
273 break;
274 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
275 pch->subsystem_device)) {
276 id = intel_virt_detect_pch(dev_priv);
277 pch_type = intel_pch_type(dev_priv, id);
278
279 /* Sanity check virtual PCH id */
280 if (WARN_ON(id && pch_type == PCH_NONE))
281 id = 0;
282
283 dev_priv->pch_type = pch_type;
284 dev_priv->pch_id = id;
285 break;
286 }
287 }
288
289 /*
290 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
291 * display.
292 */
293 if (pch && !HAS_DISPLAY(dev_priv)) {
294 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
295 dev_priv->pch_type = PCH_NOP;
296 dev_priv->pch_id = 0;
297 }
298
299 if (!pch)
300 DRM_DEBUG_KMS("No PCH found.\n");
301
302 pci_dev_put(pch);
303}
304
305static int i915_getparam_ioctl(struct drm_device *dev, void *data,
306 struct drm_file *file_priv)
307{
308 struct drm_i915_private *dev_priv = to_i915(dev);
309 struct pci_dev *pdev = dev_priv->drm.pdev;
310 drm_i915_getparam_t *param = data;
311 int value;
312
313 switch (param->param) {
314 case I915_PARAM_IRQ_ACTIVE:
315 case I915_PARAM_ALLOW_BATCHBUFFER:
316 case I915_PARAM_LAST_DISPATCH:
317 case I915_PARAM_HAS_EXEC_CONSTANTS:
318 /* Reject all old ums/dri params. */
319 return -ENODEV;
320 case I915_PARAM_CHIPSET_ID:
321 value = pdev->device;
322 break;
323 case I915_PARAM_REVISION:
324 value = pdev->revision;
325 break;
326 case I915_PARAM_NUM_FENCES_AVAIL:
327 value = dev_priv->num_fence_regs;
328 break;
329 case I915_PARAM_HAS_OVERLAY:
330 value = dev_priv->overlay ? 1 : 0;
331 break;
332 case I915_PARAM_HAS_BSD:
333 value = !!dev_priv->engine[VCS];
334 break;
335 case I915_PARAM_HAS_BLT:
336 value = !!dev_priv->engine[BCS];
337 break;
338 case I915_PARAM_HAS_VEBOX:
339 value = !!dev_priv->engine[VECS];
340 break;
341 case I915_PARAM_HAS_BSD2:
342 value = !!dev_priv->engine[VCS2];
343 break;
344 case I915_PARAM_HAS_LLC:
345 value = HAS_LLC(dev_priv);
346 break;
347 case I915_PARAM_HAS_WT:
348 value = HAS_WT(dev_priv);
349 break;
350 case I915_PARAM_HAS_ALIASING_PPGTT:
351 value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
352 break;
353 case I915_PARAM_HAS_SEMAPHORES:
354 value = 0;
355 break;
356 case I915_PARAM_HAS_SECURE_BATCHES:
357 value = capable(CAP_SYS_ADMIN);
358 break;
359 case I915_PARAM_CMD_PARSER_VERSION:
360 value = i915_cmd_parser_get_version(dev_priv);
361 break;
362 case I915_PARAM_SUBSLICE_TOTAL:
363 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
364 if (!value)
365 return -ENODEV;
366 break;
367 case I915_PARAM_EU_TOTAL:
368 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
369 if (!value)
370 return -ENODEV;
371 break;
372 case I915_PARAM_HAS_GPU_RESET:
373 value = i915_modparams.enable_hangcheck &&
374 intel_has_gpu_reset(dev_priv);
375 if (value && intel_has_reset_engine(dev_priv))
376 value = 2;
377 break;
378 case I915_PARAM_HAS_RESOURCE_STREAMER:
379 value = 0;
380 break;
381 case I915_PARAM_HAS_POOLED_EU:
382 value = HAS_POOLED_EU(dev_priv);
383 break;
384 case I915_PARAM_MIN_EU_IN_POOL:
385 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
386 break;
387 case I915_PARAM_HUC_STATUS:
388 value = intel_huc_check_status(&dev_priv->huc);
389 if (value < 0)
390 return value;
391 break;
392 case I915_PARAM_MMAP_GTT_VERSION:
393 /* Though we've started our numbering from 1, and so class all
394 * earlier versions as 0, in effect their value is undefined as
395 * the ioctl will report EINVAL for the unknown param!
396 */
397 value = i915_gem_mmap_gtt_version();
398 break;
399 case I915_PARAM_HAS_SCHEDULER:
400 value = dev_priv->caps.scheduler;
401 break;
402
403 case I915_PARAM_MMAP_VERSION:
404 /* Remember to bump this if the version changes! */
405 case I915_PARAM_HAS_GEM:
406 case I915_PARAM_HAS_PAGEFLIPPING:
407 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
408 case I915_PARAM_HAS_RELAXED_FENCING:
409 case I915_PARAM_HAS_COHERENT_RINGS:
410 case I915_PARAM_HAS_RELAXED_DELTA:
411 case I915_PARAM_HAS_GEN7_SOL_RESET:
412 case I915_PARAM_HAS_WAIT_TIMEOUT:
413 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
414 case I915_PARAM_HAS_PINNED_BATCHES:
415 case I915_PARAM_HAS_EXEC_NO_RELOC:
416 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
417 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
418 case I915_PARAM_HAS_EXEC_SOFTPIN:
419 case I915_PARAM_HAS_EXEC_ASYNC:
420 case I915_PARAM_HAS_EXEC_FENCE:
421 case I915_PARAM_HAS_EXEC_CAPTURE:
422 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
423 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
424 /* For the time being all of these are always true;
425 * if some supported hardware does not have one of these
426 * features this value needs to be provided from
427 * INTEL_INFO(), a feature macro, or similar.
428 */
429 value = 1;
430 break;
431 case I915_PARAM_HAS_CONTEXT_ISOLATION:
432 value = intel_engines_has_context_isolation(dev_priv);
433 break;
434 case I915_PARAM_SLICE_MASK:
435 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
436 if (!value)
437 return -ENODEV;
438 break;
439 case I915_PARAM_SUBSLICE_MASK:
440 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
441 if (!value)
442 return -ENODEV;
443 break;
444 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
445 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
446 break;
447 case I915_PARAM_MMAP_GTT_COHERENT:
448 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
449 break;
450 default:
451 DRM_DEBUG("Unknown parameter %d\n", param->param);
452 return -EINVAL;
453 }
454
455 if (put_user(value, param->value))
456 return -EFAULT;
457
458 return 0;
459}
460
461static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
462{
463 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
464
465 dev_priv->bridge_dev =
466 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
467 if (!dev_priv->bridge_dev) {
468 DRM_ERROR("bridge device not found\n");
469 return -1;
470 }
471 return 0;
472}
473
474/* Allocate space for the MCH regs if needed, return nonzero on error */
475static int
476intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
477{
478 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
479 u32 temp_lo, temp_hi = 0;
480 u64 mchbar_addr;
481 int ret;
482
483 if (INTEL_GEN(dev_priv) >= 4)
484 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
485 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
486 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
487
488 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
489#ifdef CONFIG_PNP
490 if (mchbar_addr &&
491 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
492 return 0;
493#endif
494
495 /* Get some space for it */
496 dev_priv->mch_res.name = "i915 MCHBAR";
497 dev_priv->mch_res.flags = IORESOURCE_MEM;
498 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
499 &dev_priv->mch_res,
500 MCHBAR_SIZE, MCHBAR_SIZE,
501 PCIBIOS_MIN_MEM,
502 0, pcibios_align_resource,
503 dev_priv->bridge_dev);
504 if (ret) {
505 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
506 dev_priv->mch_res.start = 0;
507 return ret;
508 }
509
510 if (INTEL_GEN(dev_priv) >= 4)
511 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
512 upper_32_bits(dev_priv->mch_res.start));
513
514 pci_write_config_dword(dev_priv->bridge_dev, reg,
515 lower_32_bits(dev_priv->mch_res.start));
516 return 0;
517}
518
519/* Setup MCHBAR if possible, return true if we should disable it again */
520static void
521intel_setup_mchbar(struct drm_i915_private *dev_priv)
522{
523 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
524 u32 temp;
525 bool enabled;
526
527 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
528 return;
529
530 dev_priv->mchbar_need_disable = false;
531
532 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
533 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
534 enabled = !!(temp & DEVEN_MCHBAR_EN);
535 } else {
536 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
537 enabled = temp & 1;
538 }
539
540 /* If it's already enabled, don't have to do anything */
541 if (enabled)
542 return;
543
544 if (intel_alloc_mchbar_resource(dev_priv))
545 return;
546
547 dev_priv->mchbar_need_disable = true;
548
549 /* Space is allocated or reserved, so enable it. */
550 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
551 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
552 temp | DEVEN_MCHBAR_EN);
553 } else {
554 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
555 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
556 }
557}
558
559static void
560intel_teardown_mchbar(struct drm_i915_private *dev_priv)
561{
562 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
563
564 if (dev_priv->mchbar_need_disable) {
565 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
566 u32 deven_val;
567
568 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
569 &deven_val);
570 deven_val &= ~DEVEN_MCHBAR_EN;
571 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
572 deven_val);
573 } else {
574 u32 mchbar_val;
575
576 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
577 &mchbar_val);
578 mchbar_val &= ~1;
579 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
580 mchbar_val);
581 }
582 }
583
584 if (dev_priv->mch_res.start)
585 release_resource(&dev_priv->mch_res);
586}
587
588/* true = enable decode, false = disable decoder */
589static unsigned int i915_vga_set_decode(void *cookie, bool state)
590{
591 struct drm_i915_private *dev_priv = cookie;
592
593 intel_modeset_vga_set_state(dev_priv, state);
594 if (state)
595 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
596 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
597 else
598 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
599}
600
601static int i915_resume_switcheroo(struct drm_device *dev);
602static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
603
604static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
605{
606 struct drm_device *dev = pci_get_drvdata(pdev);
607 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
608
609 if (state == VGA_SWITCHEROO_ON) {
610 pr_info("switched on\n");
611 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
612 /* i915 resume handler doesn't set to D0 */
613 pci_set_power_state(pdev, PCI_D0);
614 i915_resume_switcheroo(dev);
615 dev->switch_power_state = DRM_SWITCH_POWER_ON;
616 } else {
617 pr_info("switched off\n");
618 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
619 i915_suspend_switcheroo(dev, pmm);
620 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
621 }
622}
623
624static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
625{
626 struct drm_device *dev = pci_get_drvdata(pdev);
627
628 /*
629 * FIXME: open_count is protected by drm_global_mutex but that would lead to
630 * locking inversion with the driver load path. And the access here is
631 * completely racy anyway. So don't bother with locking for now.
632 */
633 return dev->open_count == 0;
634}
635
636static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
637 .set_gpu_state = i915_switcheroo_set_state,
638 .reprobe = NULL,
639 .can_switch = i915_switcheroo_can_switch,
640};
641
642static int i915_load_modeset_init(struct drm_device *dev)
643{
644 struct drm_i915_private *dev_priv = to_i915(dev);
645 struct pci_dev *pdev = dev_priv->drm.pdev;
646 int ret;
647
648 if (i915_inject_load_failure())
649 return -ENODEV;
650
651 if (HAS_DISPLAY(dev_priv)) {
652 ret = drm_vblank_init(&dev_priv->drm,
653 INTEL_INFO(dev_priv)->num_pipes);
654 if (ret)
655 goto out;
656 }
657
658 intel_bios_init(dev_priv);
659
660 /* If we have > 1 VGA cards, then we need to arbitrate access
661 * to the common VGA resources.
662 *
663 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
664 * then we do not take part in VGA arbitration and the
665 * vga_client_register() fails with -ENODEV.
666 */
667 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
668 if (ret && ret != -ENODEV)
669 goto out;
670
671 intel_register_dsm_handler();
672
673 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
674 if (ret)
675 goto cleanup_vga_client;
676
677 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
678 intel_update_rawclk(dev_priv);
679
680 intel_power_domains_init_hw(dev_priv, false);
681
682 intel_csr_ucode_init(dev_priv);
683
684 ret = intel_irq_install(dev_priv);
685 if (ret)
686 goto cleanup_csr;
687
688 intel_setup_gmbus(dev_priv);
689
690 /* Important: The output setup functions called by modeset_init need
691 * working irqs for e.g. gmbus and dp aux transfers. */
692 ret = intel_modeset_init(dev);
693 if (ret)
694 goto cleanup_irq;
695
696 ret = i915_gem_init(dev_priv);
697 if (ret)
698 goto cleanup_modeset;
699
700 intel_overlay_setup(dev_priv);
701
702 if (!HAS_DISPLAY(dev_priv))
703 return 0;
704
705 ret = intel_fbdev_init(dev);
706 if (ret)
707 goto cleanup_gem;
708
709 /* Only enable hotplug handling once the fbdev is fully set up. */
710 intel_hpd_init(dev_priv);
711
712 intel_init_ipc(dev_priv);
713
714 return 0;
715
716cleanup_gem:
717 if (i915_gem_suspend(dev_priv))
718 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
719 i915_gem_fini(dev_priv);
720cleanup_modeset:
721 intel_modeset_cleanup(dev);
722cleanup_irq:
723 drm_irq_uninstall(dev);
724 intel_teardown_gmbus(dev_priv);
725cleanup_csr:
726 intel_csr_ucode_fini(dev_priv);
727 intel_power_domains_fini_hw(dev_priv);
728 vga_switcheroo_unregister_client(pdev);
729cleanup_vga_client:
730 vga_client_register(pdev, NULL, NULL, NULL);
731out:
732 return ret;
733}
734
735static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
736{
737 struct apertures_struct *ap;
738 struct pci_dev *pdev = dev_priv->drm.pdev;
739 struct i915_ggtt *ggtt = &dev_priv->ggtt;
740 bool primary;
741 int ret;
742
743 ap = alloc_apertures(1);
744 if (!ap)
745 return -ENOMEM;
746
747 ap->ranges[0].base = ggtt->gmadr.start;
748 ap->ranges[0].size = ggtt->mappable_end;
749
750 primary =
751 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
752
753 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
754
755 kfree(ap);
756
757 return ret;
758}
759
760static void intel_init_dpio(struct drm_i915_private *dev_priv)
761{
762 /*
763 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
764 * CHV x1 PHY (DP/HDMI D)
765 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
766 */
767 if (IS_CHERRYVIEW(dev_priv)) {
768 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
769 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
770 } else if (IS_VALLEYVIEW(dev_priv)) {
771 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
772 }
773}
774
775static int i915_workqueues_init(struct drm_i915_private *dev_priv)
776{
777 /*
778 * The i915 workqueue is primarily used for batched retirement of
779 * requests (and thus managing bo) once the task has been completed
780 * by the GPU. i915_retire_requests() is called directly when we
781 * need high-priority retirement, such as waiting for an explicit
782 * bo.
783 *
784 * It is also used for periodic low-priority events, such as
785 * idle-timers and recording error state.
786 *
787 * All tasks on the workqueue are expected to acquire the dev mutex
788 * so there is no point in running more than one instance of the
789 * workqueue at any time. Use an ordered one.
790 */
791 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
792 if (dev_priv->wq == NULL)
793 goto out_err;
794
795 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
796 if (dev_priv->hotplug.dp_wq == NULL)
797 goto out_free_wq;
798
799 return 0;
800
801out_free_wq:
802 destroy_workqueue(dev_priv->wq);
803out_err:
804 DRM_ERROR("Failed to allocate workqueues.\n");
805
806 return -ENOMEM;
807}
808
809static void i915_engines_cleanup(struct drm_i915_private *i915)
810{
811 struct intel_engine_cs *engine;
812 enum intel_engine_id id;
813
814 for_each_engine(engine, i915, id)
815 kfree(engine);
816}
817
818static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
819{
820 destroy_workqueue(dev_priv->hotplug.dp_wq);
821 destroy_workqueue(dev_priv->wq);
822}
823
824/*
825 * We don't keep the workarounds for pre-production hardware, so we expect our
826 * driver to fail on these machines in one way or another. A little warning on
827 * dmesg may help both the user and the bug triagers.
828 *
829 * Our policy for removing pre-production workarounds is to keep the
830 * current gen workarounds as a guide to the bring-up of the next gen
831 * (workarounds have a habit of persisting!). Anything older than that
832 * should be removed along with the complications they introduce.
833 */
834static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
835{
836 bool pre = false;
837
838 pre |= IS_HSW_EARLY_SDV(dev_priv);
839 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
840 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
841 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
842
843 if (pre) {
844 DRM_ERROR("This is a pre-production stepping. "
845 "It may not be fully functional.\n");
846 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
847 }
848}
849
850/**
851 * i915_driver_init_early - setup state not requiring device access
852 * @dev_priv: device private
853 *
854 * Initialize everything that is a "SW-only" state, that is state not
855 * requiring accessing the device or exposing the driver via kernel internal
856 * or userspace interfaces. Example steps belonging here: lock initialization,
857 * system memory allocation, setting up device specific attributes and
858 * function hooks not requiring accessing the device.
859 */
860static int i915_driver_init_early(struct drm_i915_private *dev_priv)
861{
862 int ret = 0;
863
864 if (i915_inject_load_failure())
865 return -ENODEV;
866
867 spin_lock_init(&dev_priv->irq_lock);
868 spin_lock_init(&dev_priv->gpu_error.lock);
869 mutex_init(&dev_priv->backlight_lock);
870 spin_lock_init(&dev_priv->uncore.lock);
871
872 mutex_init(&dev_priv->sb_lock);
873 mutex_init(&dev_priv->av_mutex);
874 mutex_init(&dev_priv->wm.wm_mutex);
875 mutex_init(&dev_priv->pps_mutex);
876
877 i915_memcpy_init_early(dev_priv);
878 intel_runtime_pm_init_early(dev_priv);
879
880 ret = i915_workqueues_init(dev_priv);
881 if (ret < 0)
882 goto err_engines;
883
884 ret = i915_gem_init_early(dev_priv);
885 if (ret < 0)
886 goto err_workqueues;
887
888 /* This must be called before any calls to HAS_PCH_* */
889 intel_detect_pch(dev_priv);
890
891 intel_wopcm_init_early(&dev_priv->wopcm);
892 intel_uc_init_early(dev_priv);
893 intel_pm_setup(dev_priv);
894 intel_init_dpio(dev_priv);
895 ret = intel_power_domains_init(dev_priv);
896 if (ret < 0)
897 goto err_uc;
898 intel_irq_init(dev_priv);
899 intel_hangcheck_init(dev_priv);
900 intel_init_display_hooks(dev_priv);
901 intel_init_clock_gating_hooks(dev_priv);
902 intel_init_audio_hooks(dev_priv);
903 intel_display_crc_init(dev_priv);
904
905 intel_detect_preproduction_hw(dev_priv);
906
907 return 0;
908
909err_uc:
910 intel_uc_cleanup_early(dev_priv);
911 i915_gem_cleanup_early(dev_priv);
912err_workqueues:
913 i915_workqueues_cleanup(dev_priv);
914err_engines:
915 i915_engines_cleanup(dev_priv);
916 return ret;
917}
918
919/**
920 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
921 * @dev_priv: device private
922 */
923static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
924{
925 intel_irq_fini(dev_priv);
926 intel_power_domains_cleanup(dev_priv);
927 intel_uc_cleanup_early(dev_priv);
928 i915_gem_cleanup_early(dev_priv);
929 i915_workqueues_cleanup(dev_priv);
930 i915_engines_cleanup(dev_priv);
931}
932
933static int i915_mmio_setup(struct drm_i915_private *dev_priv)
934{
935 struct pci_dev *pdev = dev_priv->drm.pdev;
936 int mmio_bar;
937 int mmio_size;
938
939 mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
940 /*
941 * Before gen4, the registers and the GTT are behind different BARs.
942 * However, from gen4 onwards, the registers and the GTT are shared
943 * in the same BAR, so we want to restrict this ioremap from
944 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
945 * the register BAR remains the same size for all the earlier
946 * generations up to Ironlake.
947 */
948 if (INTEL_GEN(dev_priv) < 5)
949 mmio_size = 512 * 1024;
950 else
951 mmio_size = 2 * 1024 * 1024;
952 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
953 if (dev_priv->regs == NULL) {
954 DRM_ERROR("failed to map registers\n");
955
956 return -EIO;
957 }
958
959 /* Try to make sure MCHBAR is enabled before poking at it */
960 intel_setup_mchbar(dev_priv);
961
962 return 0;
963}
964
965static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
966{
967 struct pci_dev *pdev = dev_priv->drm.pdev;
968
969 intel_teardown_mchbar(dev_priv);
970 pci_iounmap(pdev, dev_priv->regs);
971}
972
973/**
974 * i915_driver_init_mmio - setup device MMIO
975 * @dev_priv: device private
976 *
977 * Setup minimal device state necessary for MMIO accesses later in the
978 * initialization sequence. The setup here should avoid any other device-wide
979 * side effects or exposing the driver via kernel internal or user space
980 * interfaces.
981 */
982static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
983{
984 int ret;
985
986 if (i915_inject_load_failure())
987 return -ENODEV;
988
989 if (i915_get_bridge_dev(dev_priv))
990 return -EIO;
991
992 ret = i915_mmio_setup(dev_priv);
993 if (ret < 0)
994 goto err_bridge;
995
996 intel_uncore_init(dev_priv);
997
998 intel_device_info_init_mmio(dev_priv);
999
1000 intel_uncore_prune(dev_priv);
1001
1002 intel_uc_init_mmio(dev_priv);
1003
1004 ret = intel_engines_init_mmio(dev_priv);
1005 if (ret)
1006 goto err_uncore;
1007
1008 i915_gem_init_mmio(dev_priv);
1009
1010 return 0;
1011
1012err_uncore:
1013 intel_uncore_fini(dev_priv);
1014 i915_mmio_cleanup(dev_priv);
1015err_bridge:
1016 pci_dev_put(dev_priv->bridge_dev);
1017
1018 return ret;
1019}
1020
1021/**
1022 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1023 * @dev_priv: device private
1024 */
1025static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1026{
1027 intel_uncore_fini(dev_priv);
1028 i915_mmio_cleanup(dev_priv);
1029 pci_dev_put(dev_priv->bridge_dev);
1030}
1031
1032static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1033{
1034 intel_gvt_sanitize_options(dev_priv);
1035}
1036
1037static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1038{
1039 if (size == 0)
1040 return I915_DRAM_RANK_INVALID;
1041 if (rank == SKL_DRAM_RANK_SINGLE)
1042 return I915_DRAM_RANK_SINGLE;
1043 else if (rank == SKL_DRAM_RANK_DUAL)
1044 return I915_DRAM_RANK_DUAL;
1045
1046 return I915_DRAM_RANK_INVALID;
1047}
1048
1049static bool
1050skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1051{
1052 if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1053 return true;
1054 else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1055 return true;
1056 else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1057 return true;
1058 else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1059 return true;
1060
1061 return false;
1062}
1063
1064static int
1065skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1066{
1067 u32 tmp_l, tmp_s;
1068 u32 s_val = val >> SKL_DRAM_S_SHIFT;
1069
1070 if (!val)
1071 return -EINVAL;
1072
1073 tmp_l = val & SKL_DRAM_SIZE_MASK;
1074 tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1075
1076 if (tmp_l == 0 && tmp_s == 0)
1077 return -EINVAL;
1078
1079 ch->l_info.size = tmp_l;
1080 ch->s_info.size = tmp_s;
1081
1082 tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1083 tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1084 ch->l_info.width = (1 << tmp_l) * 8;
1085 ch->s_info.width = (1 << tmp_s) * 8;
1086
1087 tmp_l = val & SKL_DRAM_RANK_MASK;
1088 tmp_s = s_val & SKL_DRAM_RANK_MASK;
1089 ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1090 ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1091
1092 if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1093 ch->s_info.rank == I915_DRAM_RANK_DUAL)
1094 ch->rank = I915_DRAM_RANK_DUAL;
1095 else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1096 ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1097 ch->rank = I915_DRAM_RANK_DUAL;
1098 else
1099 ch->rank = I915_DRAM_RANK_SINGLE;
1100
1101 ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1102 ch->l_info.width) ||
1103 skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1104 ch->s_info.width);
1105
1106 DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1107 ch->l_info.size, ch->l_info.width,
1108 ch->l_info.rank ? "dual" : "single",
1109 ch->s_info.size, ch->s_info.width,
1110 ch->s_info.rank ? "dual" : "single");
1111
1112 return 0;
1113}
1114
1115static bool
1116intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1117 struct dram_channel_info *ch0)
1118{
1119 return (val_ch0 == val_ch1 &&
1120 (ch0->s_info.size == 0 ||
1121 (ch0->l_info.size == ch0->s_info.size &&
1122 ch0->l_info.width == ch0->s_info.width &&
1123 ch0->l_info.rank == ch0->s_info.rank)));
1124}
1125
1126static int
1127skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1128{
1129 struct dram_info *dram_info = &dev_priv->dram_info;
1130 struct dram_channel_info ch0, ch1;
1131 u32 val_ch0, val_ch1;
1132 int ret;
1133
1134 val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1135 ret = skl_dram_get_channel_info(&ch0, val_ch0);
1136 if (ret == 0)
1137 dram_info->num_channels++;
1138
1139 val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1140 ret = skl_dram_get_channel_info(&ch1, val_ch1);
1141 if (ret == 0)
1142 dram_info->num_channels++;
1143
1144 if (dram_info->num_channels == 0) {
1145 DRM_INFO("Number of memory channels is zero\n");
1146 return -EINVAL;
1147 }
1148
1149 /*
1150 * If any of the channel is single rank channel, worst case output
1151 * will be same as if single rank memory, so consider single rank
1152 * memory.
1153 */
1154 if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1155 ch1.rank == I915_DRAM_RANK_SINGLE)
1156 dram_info->rank = I915_DRAM_RANK_SINGLE;
1157 else
1158 dram_info->rank = max(ch0.rank, ch1.rank);
1159
1160 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1161 DRM_INFO("couldn't get memory rank information\n");
1162 return -EINVAL;
1163 }
1164
1165 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1166
1167 dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1168 val_ch1,
1169 &ch0);
1170
1171 DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1172 dev_priv->dram_info.symmetric_memory ? "" : "not ");
1173 return 0;
1174}
1175
1176static int
1177skl_get_dram_info(struct drm_i915_private *dev_priv)
1178{
1179 struct dram_info *dram_info = &dev_priv->dram_info;
1180 u32 mem_freq_khz, val;
1181 int ret;
1182
1183 ret = skl_dram_get_channels_info(dev_priv);
1184 if (ret)
1185 return ret;
1186
1187 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1188 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1189 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1190
1191 dram_info->bandwidth_kbps = dram_info->num_channels *
1192 mem_freq_khz * 8;
1193
1194 if (dram_info->bandwidth_kbps == 0) {
1195 DRM_INFO("Couldn't get system memory bandwidth\n");
1196 return -EINVAL;
1197 }
1198
1199 dram_info->valid = true;
1200 return 0;
1201}
1202
1203static int
1204bxt_get_dram_info(struct drm_i915_private *dev_priv)
1205{
1206 struct dram_info *dram_info = &dev_priv->dram_info;
1207 u32 dram_channels;
1208 u32 mem_freq_khz, val;
1209 u8 num_active_channels;
1210 int i;
1211
1212 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1213 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1214 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1215
1216 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1217 num_active_channels = hweight32(dram_channels);
1218
1219 /* Each active bit represents 4-byte channel */
1220 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1221
1222 if (dram_info->bandwidth_kbps == 0) {
1223 DRM_INFO("Couldn't get system memory bandwidth\n");
1224 return -EINVAL;
1225 }
1226
1227 /*
1228 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1229 */
1230 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1231 u8 size, width;
1232 enum dram_rank rank;
1233 u32 tmp;
1234
1235 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1236 if (val == 0xFFFFFFFF)
1237 continue;
1238
1239 dram_info->num_channels++;
1240 tmp = val & BXT_DRAM_RANK_MASK;
1241
1242 if (tmp == BXT_DRAM_RANK_SINGLE)
1243 rank = I915_DRAM_RANK_SINGLE;
1244 else if (tmp == BXT_DRAM_RANK_DUAL)
1245 rank = I915_DRAM_RANK_DUAL;
1246 else
1247 rank = I915_DRAM_RANK_INVALID;
1248
1249 tmp = val & BXT_DRAM_SIZE_MASK;
1250 if (tmp == BXT_DRAM_SIZE_4GB)
1251 size = 4;
1252 else if (tmp == BXT_DRAM_SIZE_6GB)
1253 size = 6;
1254 else if (tmp == BXT_DRAM_SIZE_8GB)
1255 size = 8;
1256 else if (tmp == BXT_DRAM_SIZE_12GB)
1257 size = 12;
1258 else if (tmp == BXT_DRAM_SIZE_16GB)
1259 size = 16;
1260 else
1261 size = 0;
1262
1263 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1264 width = (1 << tmp) * 8;
1265 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1266 width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1267 rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1268
1269 /*
1270 * If any of the channel is single rank channel,
1271 * worst case output will be same as if single rank
1272 * memory, so consider single rank memory.
1273 */
1274 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1275 dram_info->rank = rank;
1276 else if (rank == I915_DRAM_RANK_SINGLE)
1277 dram_info->rank = I915_DRAM_RANK_SINGLE;
1278 }
1279
1280 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1281 DRM_INFO("couldn't get memory rank information\n");
1282 return -EINVAL;
1283 }
1284
1285 dram_info->valid = true;
1286 return 0;
1287}
1288
1289static void
1290intel_get_dram_info(struct drm_i915_private *dev_priv)
1291{
1292 struct dram_info *dram_info = &dev_priv->dram_info;
1293 char bandwidth_str[32];
1294 int ret;
1295
1296 dram_info->valid = false;
1297 dram_info->rank = I915_DRAM_RANK_INVALID;
1298 dram_info->bandwidth_kbps = 0;
1299 dram_info->num_channels = 0;
1300
1301 /*
1302 * Assume 16Gb DIMMs are present until proven otherwise.
1303 * This is only used for the level 0 watermark latency
1304 * w/a which does not apply to bxt/glk.
1305 */
1306 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1307
1308 if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
1309 return;
1310
1311 /* Need to calculate bandwidth only for Gen9 */
1312 if (IS_BROXTON(dev_priv))
1313 ret = bxt_get_dram_info(dev_priv);
1314 else if (IS_GEN(dev_priv, 9))
1315 ret = skl_get_dram_info(dev_priv);
1316 else
1317 ret = skl_dram_get_channels_info(dev_priv);
1318 if (ret)
1319 return;
1320
1321 if (dram_info->bandwidth_kbps)
1322 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1323 else
1324 sprintf(bandwidth_str, "unknown");
1325 DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1326 bandwidth_str, dram_info->num_channels);
1327 DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
1328 (dram_info->rank == I915_DRAM_RANK_DUAL) ?
1329 "dual" : "single", yesno(dram_info->is_16gb_dimm));
1330}
1331
1332/**
1333 * i915_driver_init_hw - setup state requiring device access
1334 * @dev_priv: device private
1335 *
1336 * Setup state that requires accessing the device, but doesn't require
1337 * exposing the driver via kernel internal or userspace interfaces.
1338 */
1339static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1340{
1341 struct pci_dev *pdev = dev_priv->drm.pdev;
1342 int ret;
1343
1344 if (i915_inject_load_failure())
1345 return -ENODEV;
1346
1347 intel_device_info_runtime_init(dev_priv);
1348
1349 if (HAS_PPGTT(dev_priv)) {
1350 if (intel_vgpu_active(dev_priv) &&
1351 !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
1352 i915_report_error(dev_priv,
1353 "incompatible vGPU found, support for isolated ppGTT required\n");
1354 return -ENXIO;
1355 }
1356 }
1357
1358 if (HAS_EXECLISTS(dev_priv)) {
1359 /*
1360 * Older GVT emulation depends upon intercepting CSB mmio,
1361 * which we no longer use, preferring to use the HWSP cache
1362 * instead.
1363 */
1364 if (intel_vgpu_active(dev_priv) &&
1365 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1366 i915_report_error(dev_priv,
1367 "old vGPU host found, support for HWSP emulation required\n");
1368 return -ENXIO;
1369 }
1370 }
1371
1372 intel_sanitize_options(dev_priv);
1373
1374 i915_perf_init(dev_priv);
1375
1376 ret = i915_ggtt_probe_hw(dev_priv);
1377 if (ret)
1378 goto err_perf;
1379
1380 /*
1381 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1382 * otherwise the vga fbdev driver falls over.
1383 */
1384 ret = i915_kick_out_firmware_fb(dev_priv);
1385 if (ret) {
1386 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1387 goto err_ggtt;
1388 }
1389
1390 ret = vga_remove_vgacon(pdev);
1391 if (ret) {
1392 DRM_ERROR("failed to remove conflicting VGA console\n");
1393 goto err_ggtt;
1394 }
1395
1396 ret = i915_ggtt_init_hw(dev_priv);
1397 if (ret)
1398 goto err_ggtt;
1399
1400 ret = i915_ggtt_enable_hw(dev_priv);
1401 if (ret) {
1402 DRM_ERROR("failed to enable GGTT\n");
1403 goto err_ggtt;
1404 }
1405
1406 pci_set_master(pdev);
1407
1408 /* overlay on gen2 is broken and can't address above 1G */
1409 if (IS_GEN(dev_priv, 2)) {
1410 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1411 if (ret) {
1412 DRM_ERROR("failed to set DMA mask\n");
1413
1414 goto err_ggtt;
1415 }
1416 }
1417
1418 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1419 * using 32bit addressing, overwriting memory if HWS is located
1420 * above 4GB.
1421 *
1422 * The documentation also mentions an issue with undefined
1423 * behaviour if any general state is accessed within a page above 4GB,
1424 * which also needs to be handled carefully.
1425 */
1426 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1427 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1428
1429 if (ret) {
1430 DRM_ERROR("failed to set DMA mask\n");
1431
1432 goto err_ggtt;
1433 }
1434 }
1435
1436 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1437 PM_QOS_DEFAULT_VALUE);
1438
1439 intel_uncore_sanitize(dev_priv);
1440
1441 intel_gt_init_workarounds(dev_priv);
1442 i915_gem_load_init_fences(dev_priv);
1443
1444 /* On the 945G/GM, the chipset reports the MSI capability on the
1445 * integrated graphics even though the support isn't actually there
1446 * according to the published specs. It doesn't appear to function
1447 * correctly in testing on 945G.
1448 * This may be a side effect of MSI having been made available for PEG
1449 * and the registers being closely associated.
1450 *
1451 * According to chipset errata, on the 965GM, MSI interrupts may
1452 * be lost or delayed, and was defeatured. MSI interrupts seem to
1453 * get lost on g4x as well, and interrupt delivery seems to stay
1454 * properly dead afterwards. So we'll just disable them for all
1455 * pre-gen5 chipsets.
1456 *
1457 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1458 * interrupts even when in MSI mode. This results in spurious
1459 * interrupt warnings if the legacy irq no. is shared with another
1460 * device. The kernel then disables that interrupt source and so
1461 * prevents the other device from working properly.
1462 */
1463 if (INTEL_GEN(dev_priv) >= 5) {
1464 if (pci_enable_msi(pdev) < 0)
1465 DRM_DEBUG_DRIVER("can't enable MSI");
1466 }
1467
1468 ret = intel_gvt_init(dev_priv);
1469 if (ret)
1470 goto err_msi;
1471
1472 intel_opregion_setup(dev_priv);
1473 /*
1474 * Fill the dram structure to get the system raw bandwidth and
1475 * dram info. This will be used for memory latency calculation.
1476 */
1477 intel_get_dram_info(dev_priv);
1478
1479
1480 return 0;
1481
1482err_msi:
1483 if (pdev->msi_enabled)
1484 pci_disable_msi(pdev);
1485 pm_qos_remove_request(&dev_priv->pm_qos);
1486err_ggtt:
1487 i915_ggtt_cleanup_hw(dev_priv);
1488err_perf:
1489 i915_perf_fini(dev_priv);
1490 return ret;
1491}
1492
1493/**
1494 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1495 * @dev_priv: device private
1496 */
1497static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1498{
1499 struct pci_dev *pdev = dev_priv->drm.pdev;
1500
1501 i915_perf_fini(dev_priv);
1502
1503 if (pdev->msi_enabled)
1504 pci_disable_msi(pdev);
1505
1506 pm_qos_remove_request(&dev_priv->pm_qos);
1507 i915_ggtt_cleanup_hw(dev_priv);
1508}
1509
1510/**
1511 * i915_driver_register - register the driver with the rest of the system
1512 * @dev_priv: device private
1513 *
1514 * Perform any steps necessary to make the driver available via kernel
1515 * internal or userspace interfaces.
1516 */
1517static void i915_driver_register(struct drm_i915_private *dev_priv)
1518{
1519 struct drm_device *dev = &dev_priv->drm;
1520
1521 i915_gem_shrinker_register(dev_priv);
1522 i915_pmu_register(dev_priv);
1523
1524 /*
1525 * Notify a valid surface after modesetting,
1526 * when running inside a VM.
1527 */
1528 if (intel_vgpu_active(dev_priv))
1529 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1530
1531 /* Reveal our presence to userspace */
1532 if (drm_dev_register(dev, 0) == 0) {
1533 i915_debugfs_register(dev_priv);
1534 i915_setup_sysfs(dev_priv);
1535
1536 /* Depends on sysfs having been initialized */
1537 i915_perf_register(dev_priv);
1538 } else
1539 DRM_ERROR("Failed to register driver for userspace access!\n");
1540
1541 if (HAS_DISPLAY(dev_priv)) {
1542 /* Must be done after probing outputs */
1543 intel_opregion_register(dev_priv);
1544 acpi_video_register();
1545 }
1546
1547 if (IS_GEN(dev_priv, 5))
1548 intel_gpu_ips_init(dev_priv);
1549
1550 intel_audio_init(dev_priv);
1551
1552 /*
1553 * Some ports require correctly set-up hpd registers for detection to
1554 * work properly (leading to ghost connected connector status), e.g. VGA
1555 * on gm45. Hence we can only set up the initial fbdev config after hpd
1556 * irqs are fully enabled. We do it last so that the async config
1557 * cannot run before the connectors are registered.
1558 */
1559 intel_fbdev_initial_config_async(dev);
1560
1561 /*
1562 * We need to coordinate the hotplugs with the asynchronous fbdev
1563 * configuration, for which we use the fbdev->async_cookie.
1564 */
1565 if (HAS_DISPLAY(dev_priv))
1566 drm_kms_helper_poll_init(dev);
1567
1568 intel_power_domains_enable(dev_priv);
1569 intel_runtime_pm_enable(dev_priv);
1570}
1571
1572/**
1573 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1574 * @dev_priv: device private
1575 */
1576static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1577{
1578 intel_runtime_pm_disable(dev_priv);
1579 intel_power_domains_disable(dev_priv);
1580
1581 intel_fbdev_unregister(dev_priv);
1582 intel_audio_deinit(dev_priv);
1583
1584 /*
1585 * After flushing the fbdev (incl. a late async config which will
1586 * have delayed queuing of a hotplug event), then flush the hotplug
1587 * events.
1588 */
1589 drm_kms_helper_poll_fini(&dev_priv->drm);
1590
1591 intel_gpu_ips_teardown();
1592 acpi_video_unregister();
1593 intel_opregion_unregister(dev_priv);
1594
1595 i915_perf_unregister(dev_priv);
1596 i915_pmu_unregister(dev_priv);
1597
1598 i915_teardown_sysfs(dev_priv);
1599 drm_dev_unregister(&dev_priv->drm);
1600
1601 i915_gem_shrinker_unregister(dev_priv);
1602}
1603
1604static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1605{
1606 if (drm_debug & DRM_UT_DRIVER) {
1607 struct drm_printer p = drm_debug_printer("i915 device info:");
1608
1609 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1610 INTEL_DEVID(dev_priv),
1611 INTEL_REVID(dev_priv),
1612 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1613 INTEL_GEN(dev_priv));
1614
1615 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1616 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1617 }
1618
1619 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1620 DRM_INFO("DRM_I915_DEBUG enabled\n");
1621 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1622 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1623 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1624 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1625}
1626
1627static struct drm_i915_private *
1628i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1629{
1630 const struct intel_device_info *match_info =
1631 (struct intel_device_info *)ent->driver_data;
1632 struct intel_device_info *device_info;
1633 struct drm_i915_private *i915;
1634 int err;
1635
1636 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1637 if (!i915)
1638 return ERR_PTR(-ENOMEM);
1639
1640 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1641 if (err) {
1642 kfree(i915);
1643 return ERR_PTR(err);
1644 }
1645
1646 i915->drm.pdev = pdev;
1647 i915->drm.dev_private = i915;
1648 pci_set_drvdata(pdev, &i915->drm);
1649
1650 /* Setup the write-once "constant" device info */
1651 device_info = mkwrite_device_info(i915);
1652 memcpy(device_info, match_info, sizeof(*device_info));
1653 RUNTIME_INFO(i915)->device_id = pdev->device;
1654
1655 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1656 BITS_PER_TYPE(device_info->platform_mask));
1657 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1658
1659 return i915;
1660}
1661
1662static void i915_driver_destroy(struct drm_i915_private *i915)
1663{
1664 struct pci_dev *pdev = i915->drm.pdev;
1665
1666 drm_dev_fini(&i915->drm);
1667 kfree(i915);
1668
1669 /* And make sure we never chase our dangling pointer from pci_dev */
1670 pci_set_drvdata(pdev, NULL);
1671}
1672
1673/**
1674 * i915_driver_load - setup chip and create an initial config
1675 * @pdev: PCI device
1676 * @ent: matching PCI ID entry
1677 *
1678 * The driver load routine has to do several things:
1679 * - drive output discovery via intel_modeset_init()
1680 * - initialize the memory manager
1681 * - allocate initial config memory
1682 * - setup the DRM framebuffer with the allocated memory
1683 */
1684int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1685{
1686 const struct intel_device_info *match_info =
1687 (struct intel_device_info *)ent->driver_data;
1688 struct drm_i915_private *dev_priv;
1689 int ret;
1690
1691 dev_priv = i915_driver_create(pdev, ent);
1692 if (IS_ERR(dev_priv))
1693 return PTR_ERR(dev_priv);
1694
1695 /* Disable nuclear pageflip by default on pre-ILK */
1696 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1697 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1698
1699 ret = pci_enable_device(pdev);
1700 if (ret)
1701 goto out_fini;
1702
1703 ret = i915_driver_init_early(dev_priv);
1704 if (ret < 0)
1705 goto out_pci_disable;
1706
1707 disable_rpm_wakeref_asserts(dev_priv);
1708
1709 ret = i915_driver_init_mmio(dev_priv);
1710 if (ret < 0)
1711 goto out_runtime_pm_put;
1712
1713 ret = i915_driver_init_hw(dev_priv);
1714 if (ret < 0)
1715 goto out_cleanup_mmio;
1716
1717 ret = i915_load_modeset_init(&dev_priv->drm);
1718 if (ret < 0)
1719 goto out_cleanup_hw;
1720
1721 i915_driver_register(dev_priv);
1722
1723 enable_rpm_wakeref_asserts(dev_priv);
1724
1725 i915_welcome_messages(dev_priv);
1726
1727 return 0;
1728
1729out_cleanup_hw:
1730 i915_driver_cleanup_hw(dev_priv);
1731out_cleanup_mmio:
1732 i915_driver_cleanup_mmio(dev_priv);
1733out_runtime_pm_put:
1734 enable_rpm_wakeref_asserts(dev_priv);
1735 i915_driver_cleanup_early(dev_priv);
1736out_pci_disable:
1737 pci_disable_device(pdev);
1738out_fini:
1739 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1740 i915_driver_destroy(dev_priv);
1741 return ret;
1742}
1743
1744void i915_driver_unload(struct drm_device *dev)
1745{
1746 struct drm_i915_private *dev_priv = to_i915(dev);
1747 struct pci_dev *pdev = dev_priv->drm.pdev;
1748
1749 disable_rpm_wakeref_asserts(dev_priv);
1750
1751 i915_driver_unregister(dev_priv);
1752
1753 /* Flush any external code that still may be under the RCU lock */
1754 synchronize_rcu();
1755
1756 if (i915_gem_suspend(dev_priv))
1757 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1758
1759 drm_atomic_helper_shutdown(dev);
1760
1761 intel_gvt_cleanup(dev_priv);
1762
1763 intel_modeset_cleanup(dev);
1764
1765 intel_bios_cleanup(dev_priv);
1766
1767 vga_switcheroo_unregister_client(pdev);
1768 vga_client_register(pdev, NULL, NULL, NULL);
1769
1770 intel_csr_ucode_fini(dev_priv);
1771
1772 /* Free error state after interrupts are fully disabled. */
1773 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1774 i915_reset_error_state(dev_priv);
1775
1776 i915_gem_fini(dev_priv);
1777
1778 intel_power_domains_fini_hw(dev_priv);
1779
1780 i915_driver_cleanup_hw(dev_priv);
1781 i915_driver_cleanup_mmio(dev_priv);
1782
1783 enable_rpm_wakeref_asserts(dev_priv);
1784 intel_runtime_pm_cleanup(dev_priv);
1785}
1786
1787static void i915_driver_release(struct drm_device *dev)
1788{
1789 struct drm_i915_private *dev_priv = to_i915(dev);
1790
1791 i915_driver_cleanup_early(dev_priv);
1792 i915_driver_destroy(dev_priv);
1793}
1794
1795static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1796{
1797 struct drm_i915_private *i915 = to_i915(dev);
1798 int ret;
1799
1800 ret = i915_gem_open(i915, file);
1801 if (ret)
1802 return ret;
1803
1804 return 0;
1805}
1806
1807/**
1808 * i915_driver_lastclose - clean up after all DRM clients have exited
1809 * @dev: DRM device
1810 *
1811 * Take care of cleaning up after all DRM clients have exited. In the
1812 * mode setting case, we want to restore the kernel's initial mode (just
1813 * in case the last client left us in a bad state).
1814 *
1815 * Additionally, in the non-mode setting case, we'll tear down the GTT
1816 * and DMA structures, since the kernel won't be using them, and clea
1817 * up any GEM state.
1818 */
1819static void i915_driver_lastclose(struct drm_device *dev)
1820{
1821 intel_fbdev_restore_mode(dev);
1822 vga_switcheroo_process_delayed_switch();
1823}
1824
1825static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1826{
1827 struct drm_i915_file_private *file_priv = file->driver_priv;
1828
1829 mutex_lock(&dev->struct_mutex);
1830 i915_gem_context_close(file);
1831 i915_gem_release(dev, file);
1832 mutex_unlock(&dev->struct_mutex);
1833
1834 kfree(file_priv);
1835}
1836
1837static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1838{
1839 struct drm_device *dev = &dev_priv->drm;
1840 struct intel_encoder *encoder;
1841
1842 drm_modeset_lock_all(dev);
1843 for_each_intel_encoder(dev, encoder)
1844 if (encoder->suspend)
1845 encoder->suspend(encoder);
1846 drm_modeset_unlock_all(dev);
1847}
1848
1849static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1850 bool rpm_resume);
1851static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1852
1853static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1854{
1855#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1856 if (acpi_target_system_state() < ACPI_STATE_S3)
1857 return true;
1858#endif
1859 return false;
1860}
1861
1862static int i915_drm_prepare(struct drm_device *dev)
1863{
1864 struct drm_i915_private *i915 = to_i915(dev);
1865 int err;
1866
1867 /*
1868 * NB intel_display_suspend() may issue new requests after we've
1869 * ostensibly marked the GPU as ready-to-sleep here. We need to
1870 * split out that work and pull it forward so that after point,
1871 * the GPU is not woken again.
1872 */
1873 err = i915_gem_suspend(i915);
1874 if (err)
1875 dev_err(&i915->drm.pdev->dev,
1876 "GEM idle failed, suspend/resume might fail\n");
1877
1878 return err;
1879}
1880
1881static int i915_drm_suspend(struct drm_device *dev)
1882{
1883 struct drm_i915_private *dev_priv = to_i915(dev);
1884 struct pci_dev *pdev = dev_priv->drm.pdev;
1885 pci_power_t opregion_target_state;
1886
1887 disable_rpm_wakeref_asserts(dev_priv);
1888
1889 /* We do a lot of poking in a lot of registers, make sure they work
1890 * properly. */
1891 intel_power_domains_disable(dev_priv);
1892
1893 drm_kms_helper_poll_disable(dev);
1894
1895 pci_save_state(pdev);
1896
1897 intel_display_suspend(dev);
1898
1899 intel_dp_mst_suspend(dev_priv);
1900
1901 intel_runtime_pm_disable_interrupts(dev_priv);
1902 intel_hpd_cancel_work(dev_priv);
1903
1904 intel_suspend_encoders(dev_priv);
1905
1906 intel_suspend_hw(dev_priv);
1907
1908 i915_gem_suspend_gtt_mappings(dev_priv);
1909
1910 i915_save_state(dev_priv);
1911
1912 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1913 intel_opregion_suspend(dev_priv, opregion_target_state);
1914
1915 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1916
1917 dev_priv->suspend_count++;
1918
1919 intel_csr_ucode_suspend(dev_priv);
1920
1921 enable_rpm_wakeref_asserts(dev_priv);
1922
1923 return 0;
1924}
1925
1926static enum i915_drm_suspend_mode
1927get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1928{
1929 if (hibernate)
1930 return I915_DRM_SUSPEND_HIBERNATE;
1931
1932 if (suspend_to_idle(dev_priv))
1933 return I915_DRM_SUSPEND_IDLE;
1934
1935 return I915_DRM_SUSPEND_MEM;
1936}
1937
1938static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1939{
1940 struct drm_i915_private *dev_priv = to_i915(dev);
1941 struct pci_dev *pdev = dev_priv->drm.pdev;
1942 int ret;
1943
1944 disable_rpm_wakeref_asserts(dev_priv);
1945
1946 i915_gem_suspend_late(dev_priv);
1947
1948 intel_uncore_suspend(dev_priv);
1949
1950 intel_power_domains_suspend(dev_priv,
1951 get_suspend_mode(dev_priv, hibernation));
1952
1953 ret = 0;
1954 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
1955 bxt_enable_dc9(dev_priv);
1956 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1957 hsw_enable_pc8(dev_priv);
1958 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1959 ret = vlv_suspend_complete(dev_priv);
1960
1961 if (ret) {
1962 DRM_ERROR("Suspend complete failed: %d\n", ret);
1963 intel_power_domains_resume(dev_priv);
1964
1965 goto out;
1966 }
1967
1968 pci_disable_device(pdev);
1969 /*
1970 * During hibernation on some platforms the BIOS may try to access
1971 * the device even though it's already in D3 and hang the machine. So
1972 * leave the device in D0 on those platforms and hope the BIOS will
1973 * power down the device properly. The issue was seen on multiple old
1974 * GENs with different BIOS vendors, so having an explicit blacklist
1975 * is inpractical; apply the workaround on everything pre GEN6. The
1976 * platforms where the issue was seen:
1977 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1978 * Fujitsu FSC S7110
1979 * Acer Aspire 1830T
1980 */
1981 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1982 pci_set_power_state(pdev, PCI_D3hot);
1983
1984out:
1985 enable_rpm_wakeref_asserts(dev_priv);
1986 if (!dev_priv->uncore.user_forcewake.count)
1987 intel_runtime_pm_cleanup(dev_priv);
1988
1989 return ret;
1990}
1991
1992static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1993{
1994 int error;
1995
1996 if (!dev) {
1997 DRM_ERROR("dev: %p\n", dev);
1998 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1999 return -ENODEV;
2000 }
2001
2002 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2003 state.event != PM_EVENT_FREEZE))
2004 return -EINVAL;
2005
2006 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2007 return 0;
2008
2009 error = i915_drm_suspend(dev);
2010 if (error)
2011 return error;
2012
2013 return i915_drm_suspend_late(dev, false);
2014}
2015
2016static int i915_drm_resume(struct drm_device *dev)
2017{
2018 struct drm_i915_private *dev_priv = to_i915(dev);
2019 int ret;
2020
2021 disable_rpm_wakeref_asserts(dev_priv);
2022 intel_sanitize_gt_powersave(dev_priv);
2023
2024 i915_gem_sanitize(dev_priv);
2025
2026 ret = i915_ggtt_enable_hw(dev_priv);
2027 if (ret)
2028 DRM_ERROR("failed to re-enable GGTT\n");
2029
2030 intel_csr_ucode_resume(dev_priv);
2031
2032 i915_restore_state(dev_priv);
2033 intel_pps_unlock_regs_wa(dev_priv);
2034
2035 intel_init_pch_refclk(dev_priv);
2036
2037 /*
2038 * Interrupts have to be enabled before any batches are run. If not the
2039 * GPU will hang. i915_gem_init_hw() will initiate batches to
2040 * update/restore the context.
2041 *
2042 * drm_mode_config_reset() needs AUX interrupts.
2043 *
2044 * Modeset enabling in intel_modeset_init_hw() also needs working
2045 * interrupts.
2046 */
2047 intel_runtime_pm_enable_interrupts(dev_priv);
2048
2049 drm_mode_config_reset(dev);
2050
2051 i915_gem_resume(dev_priv);
2052
2053 intel_modeset_init_hw(dev);
2054 intel_init_clock_gating(dev_priv);
2055
2056 spin_lock_irq(&dev_priv->irq_lock);
2057 if (dev_priv->display.hpd_irq_setup)
2058 dev_priv->display.hpd_irq_setup(dev_priv);
2059 spin_unlock_irq(&dev_priv->irq_lock);
2060
2061 intel_dp_mst_resume(dev_priv);
2062
2063 intel_display_resume(dev);
2064
2065 drm_kms_helper_poll_enable(dev);
2066
2067 /*
2068 * ... but also need to make sure that hotplug processing
2069 * doesn't cause havoc. Like in the driver load code we don't
2070 * bother with the tiny race here where we might lose hotplug
2071 * notifications.
2072 * */
2073 intel_hpd_init(dev_priv);
2074
2075 intel_opregion_resume(dev_priv);
2076
2077 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2078
2079 intel_power_domains_enable(dev_priv);
2080
2081 enable_rpm_wakeref_asserts(dev_priv);
2082
2083 return 0;
2084}
2085
2086static int i915_drm_resume_early(struct drm_device *dev)
2087{
2088 struct drm_i915_private *dev_priv = to_i915(dev);
2089 struct pci_dev *pdev = dev_priv->drm.pdev;
2090 int ret;
2091
2092 /*
2093 * We have a resume ordering issue with the snd-hda driver also
2094 * requiring our device to be power up. Due to the lack of a
2095 * parent/child relationship we currently solve this with an early
2096 * resume hook.
2097 *
2098 * FIXME: This should be solved with a special hdmi sink device or
2099 * similar so that power domains can be employed.
2100 */
2101
2102 /*
2103 * Note that we need to set the power state explicitly, since we
2104 * powered off the device during freeze and the PCI core won't power
2105 * it back up for us during thaw. Powering off the device during
2106 * freeze is not a hard requirement though, and during the
2107 * suspend/resume phases the PCI core makes sure we get here with the
2108 * device powered on. So in case we change our freeze logic and keep
2109 * the device powered we can also remove the following set power state
2110 * call.
2111 */
2112 ret = pci_set_power_state(pdev, PCI_D0);
2113 if (ret) {
2114 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2115 return ret;
2116 }
2117
2118 /*
2119 * Note that pci_enable_device() first enables any parent bridge
2120 * device and only then sets the power state for this device. The
2121 * bridge enabling is a nop though, since bridge devices are resumed
2122 * first. The order of enabling power and enabling the device is
2123 * imposed by the PCI core as described above, so here we preserve the
2124 * same order for the freeze/thaw phases.
2125 *
2126 * TODO: eventually we should remove pci_disable_device() /
2127 * pci_enable_enable_device() from suspend/resume. Due to how they
2128 * depend on the device enable refcount we can't anyway depend on them
2129 * disabling/enabling the device.
2130 */
2131 if (pci_enable_device(pdev))
2132 return -EIO;
2133
2134 pci_set_master(pdev);
2135
2136 disable_rpm_wakeref_asserts(dev_priv);
2137
2138 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2139 ret = vlv_resume_prepare(dev_priv, false);
2140 if (ret)
2141 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2142 ret);
2143
2144 intel_uncore_resume_early(dev_priv);
2145
2146 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2147 gen9_sanitize_dc_state(dev_priv);
2148 bxt_disable_dc9(dev_priv);
2149 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2150 hsw_disable_pc8(dev_priv);
2151 }
2152
2153 intel_uncore_sanitize(dev_priv);
2154
2155 intel_power_domains_resume(dev_priv);
2156
2157 intel_engines_sanitize(dev_priv, true);
2158
2159 enable_rpm_wakeref_asserts(dev_priv);
2160
2161 return ret;
2162}
2163
2164static int i915_resume_switcheroo(struct drm_device *dev)
2165{
2166 int ret;
2167
2168 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2169 return 0;
2170
2171 ret = i915_drm_resume_early(dev);
2172 if (ret)
2173 return ret;
2174
2175 return i915_drm_resume(dev);
2176}
2177
2178static int i915_pm_prepare(struct device *kdev)
2179{
2180 struct pci_dev *pdev = to_pci_dev(kdev);
2181 struct drm_device *dev = pci_get_drvdata(pdev);
2182
2183 if (!dev) {
2184 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2185 return -ENODEV;
2186 }
2187
2188 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2189 return 0;
2190
2191 return i915_drm_prepare(dev);
2192}
2193
2194static int i915_pm_suspend(struct device *kdev)
2195{
2196 struct pci_dev *pdev = to_pci_dev(kdev);
2197 struct drm_device *dev = pci_get_drvdata(pdev);
2198
2199 if (!dev) {
2200 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2201 return -ENODEV;
2202 }
2203
2204 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2205 return 0;
2206
2207 return i915_drm_suspend(dev);
2208}
2209
2210static int i915_pm_suspend_late(struct device *kdev)
2211{
2212 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2213
2214 /*
2215 * We have a suspend ordering issue with the snd-hda driver also
2216 * requiring our device to be power up. Due to the lack of a
2217 * parent/child relationship we currently solve this with an late
2218 * suspend hook.
2219 *
2220 * FIXME: This should be solved with a special hdmi sink device or
2221 * similar so that power domains can be employed.
2222 */
2223 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2224 return 0;
2225
2226 return i915_drm_suspend_late(dev, false);
2227}
2228
2229static int i915_pm_poweroff_late(struct device *kdev)
2230{
2231 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2232
2233 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2234 return 0;
2235
2236 return i915_drm_suspend_late(dev, true);
2237}
2238
2239static int i915_pm_resume_early(struct device *kdev)
2240{
2241 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2242
2243 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2244 return 0;
2245
2246 return i915_drm_resume_early(dev);
2247}
2248
2249static int i915_pm_resume(struct device *kdev)
2250{
2251 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2252
2253 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2254 return 0;
2255
2256 return i915_drm_resume(dev);
2257}
2258
2259/* freeze: before creating the hibernation_image */
2260static int i915_pm_freeze(struct device *kdev)
2261{
2262 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2263 int ret;
2264
2265 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2266 ret = i915_drm_suspend(dev);
2267 if (ret)
2268 return ret;
2269 }
2270
2271 ret = i915_gem_freeze(kdev_to_i915(kdev));
2272 if (ret)
2273 return ret;
2274
2275 return 0;
2276}
2277
2278static int i915_pm_freeze_late(struct device *kdev)
2279{
2280 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2281 int ret;
2282
2283 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2284 ret = i915_drm_suspend_late(dev, true);
2285 if (ret)
2286 return ret;
2287 }
2288
2289 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2290 if (ret)
2291 return ret;
2292
2293 return 0;
2294}
2295
2296/* thaw: called after creating the hibernation image, but before turning off. */
2297static int i915_pm_thaw_early(struct device *kdev)
2298{
2299 return i915_pm_resume_early(kdev);
2300}
2301
2302static int i915_pm_thaw(struct device *kdev)
2303{
2304 return i915_pm_resume(kdev);
2305}
2306
2307/* restore: called after loading the hibernation image. */
2308static int i915_pm_restore_early(struct device *kdev)
2309{
2310 return i915_pm_resume_early(kdev);
2311}
2312
2313static int i915_pm_restore(struct device *kdev)
2314{
2315 return i915_pm_resume(kdev);
2316}
2317
2318/*
2319 * Save all Gunit registers that may be lost after a D3 and a subsequent
2320 * S0i[R123] transition. The list of registers needing a save/restore is
2321 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2322 * registers in the following way:
2323 * - Driver: saved/restored by the driver
2324 * - Punit : saved/restored by the Punit firmware
2325 * - No, w/o marking: no need to save/restore, since the register is R/O or
2326 * used internally by the HW in a way that doesn't depend
2327 * keeping the content across a suspend/resume.
2328 * - Debug : used for debugging
2329 *
2330 * We save/restore all registers marked with 'Driver', with the following
2331 * exceptions:
2332 * - Registers out of use, including also registers marked with 'Debug'.
2333 * These have no effect on the driver's operation, so we don't save/restore
2334 * them to reduce the overhead.
2335 * - Registers that are fully setup by an initialization function called from
2336 * the resume path. For example many clock gating and RPS/RC6 registers.
2337 * - Registers that provide the right functionality with their reset defaults.
2338 *
2339 * TODO: Except for registers that based on the above 3 criteria can be safely
2340 * ignored, we save/restore all others, practically treating the HW context as
2341 * a black-box for the driver. Further investigation is needed to reduce the
2342 * saved/restored registers even further, by following the same 3 criteria.
2343 */
2344static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2345{
2346 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2347 int i;
2348
2349 /* GAM 0x4000-0x4770 */
2350 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2351 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2352 s->arb_mode = I915_READ(ARB_MODE);
2353 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2354 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2355
2356 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2357 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2358
2359 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2360 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2361
2362 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2363 s->ecochk = I915_READ(GAM_ECOCHK);
2364 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2365 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2366
2367 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2368
2369 /* MBC 0x9024-0x91D0, 0x8500 */
2370 s->g3dctl = I915_READ(VLV_G3DCTL);
2371 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2372 s->mbctl = I915_READ(GEN6_MBCTL);
2373
2374 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2375 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2376 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2377 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2378 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2379 s->rstctl = I915_READ(GEN6_RSTCTL);
2380 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2381
2382 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2383 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2384 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2385 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2386 s->ecobus = I915_READ(ECOBUS);
2387 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2388 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2389 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2390 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2391 s->rcedata = I915_READ(VLV_RCEDATA);
2392 s->spare2gh = I915_READ(VLV_SPAREG2H);
2393
2394 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2395 s->gt_imr = I915_READ(GTIMR);
2396 s->gt_ier = I915_READ(GTIER);
2397 s->pm_imr = I915_READ(GEN6_PMIMR);
2398 s->pm_ier = I915_READ(GEN6_PMIER);
2399
2400 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2401 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2402
2403 /* GT SA CZ domain, 0x100000-0x138124 */
2404 s->tilectl = I915_READ(TILECTL);
2405 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2406 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2407 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2408 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2409
2410 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2411 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2412 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
2413 s->pcbr = I915_READ(VLV_PCBR);
2414 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2415
2416 /*
2417 * Not saving any of:
2418 * DFT, 0x9800-0x9EC0
2419 * SARB, 0xB000-0xB1FC
2420 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2421 * PCI CFG
2422 */
2423}
2424
2425static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2426{
2427 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2428 u32 val;
2429 int i;
2430
2431 /* GAM 0x4000-0x4770 */
2432 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2433 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2434 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2435 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2436 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2437
2438 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2439 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2440
2441 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2442 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2443
2444 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2445 I915_WRITE(GAM_ECOCHK, s->ecochk);
2446 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2447 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2448
2449 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2450
2451 /* MBC 0x9024-0x91D0, 0x8500 */
2452 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2453 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2454 I915_WRITE(GEN6_MBCTL, s->mbctl);
2455
2456 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2457 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2458 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2459 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2460 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2461 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2462 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2463
2464 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2465 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2466 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2467 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2468 I915_WRITE(ECOBUS, s->ecobus);
2469 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2470 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2471 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2472 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2473 I915_WRITE(VLV_RCEDATA, s->rcedata);
2474 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2475
2476 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2477 I915_WRITE(GTIMR, s->gt_imr);
2478 I915_WRITE(GTIER, s->gt_ier);
2479 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2480 I915_WRITE(GEN6_PMIER, s->pm_ier);
2481
2482 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2483 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2484
2485 /* GT SA CZ domain, 0x100000-0x138124 */
2486 I915_WRITE(TILECTL, s->tilectl);
2487 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2488 /*
2489 * Preserve the GT allow wake and GFX force clock bit, they are not
2490 * be restored, as they are used to control the s0ix suspend/resume
2491 * sequence by the caller.
2492 */
2493 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2494 val &= VLV_GTLC_ALLOWWAKEREQ;
2495 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2496 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2497
2498 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2499 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2500 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2501 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2502
2503 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2504
2505 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2506 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2507 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
2508 I915_WRITE(VLV_PCBR, s->pcbr);
2509 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2510}
2511
2512static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2513 u32 mask, u32 val)
2514{
2515 i915_reg_t reg = VLV_GTLC_PW_STATUS;
2516 u32 reg_value;
2517 int ret;
2518
2519 /* The HW does not like us polling for PW_STATUS frequently, so
2520 * use the sleeping loop rather than risk the busy spin within
2521 * intel_wait_for_register().
2522 *
2523 * Transitioning between RC6 states should be at most 2ms (see
2524 * valleyview_enable_rps) so use a 3ms timeout.
2525 */
2526 ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2527
2528 /* just trace the final value */
2529 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2530
2531 return ret;
2532}
2533
2534int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2535{
2536 u32 val;
2537 int err;
2538
2539 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2540 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2541 if (force_on)
2542 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2543 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2544
2545 if (!force_on)
2546 return 0;
2547
2548 err = intel_wait_for_register(dev_priv,
2549 VLV_GTLC_SURVIVABILITY_REG,
2550 VLV_GFX_CLK_STATUS_BIT,
2551 VLV_GFX_CLK_STATUS_BIT,
2552 20);
2553 if (err)
2554 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2555 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2556
2557 return err;
2558}
2559
2560static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2561{
2562 u32 mask;
2563 u32 val;
2564 int err;
2565
2566 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2567 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2568 if (allow)
2569 val |= VLV_GTLC_ALLOWWAKEREQ;
2570 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2571 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2572
2573 mask = VLV_GTLC_ALLOWWAKEACK;
2574 val = allow ? mask : 0;
2575
2576 err = vlv_wait_for_pw_status(dev_priv, mask, val);
2577 if (err)
2578 DRM_ERROR("timeout disabling GT waking\n");
2579
2580 return err;
2581}
2582
2583static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2584 bool wait_for_on)
2585{
2586 u32 mask;
2587 u32 val;
2588
2589 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2590 val = wait_for_on ? mask : 0;
2591
2592 /*
2593 * RC6 transitioning can be delayed up to 2 msec (see
2594 * valleyview_enable_rps), use 3 msec for safety.
2595 *
2596 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2597 * reset and we are trying to force the machine to sleep.
2598 */
2599 if (vlv_wait_for_pw_status(dev_priv, mask, val))
2600 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2601 onoff(wait_for_on));
2602}
2603
2604static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2605{
2606 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2607 return;
2608
2609 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2610 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2611}
2612
2613static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2614{
2615 u32 mask;
2616 int err;
2617
2618 /*
2619 * Bspec defines the following GT well on flags as debug only, so
2620 * don't treat them as hard failures.
2621 */
2622 vlv_wait_for_gt_wells(dev_priv, false);
2623
2624 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2625 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2626
2627 vlv_check_no_gt_access(dev_priv);
2628
2629 err = vlv_force_gfx_clock(dev_priv, true);
2630 if (err)
2631 goto err1;
2632
2633 err = vlv_allow_gt_wake(dev_priv, false);
2634 if (err)
2635 goto err2;
2636
2637 if (!IS_CHERRYVIEW(dev_priv))
2638 vlv_save_gunit_s0ix_state(dev_priv);
2639
2640 err = vlv_force_gfx_clock(dev_priv, false);
2641 if (err)
2642 goto err2;
2643
2644 return 0;
2645
2646err2:
2647 /* For safety always re-enable waking and disable gfx clock forcing */
2648 vlv_allow_gt_wake(dev_priv, true);
2649err1:
2650 vlv_force_gfx_clock(dev_priv, false);
2651
2652 return err;
2653}
2654
2655static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2656 bool rpm_resume)
2657{
2658 int err;
2659 int ret;
2660
2661 /*
2662 * If any of the steps fail just try to continue, that's the best we
2663 * can do at this point. Return the first error code (which will also
2664 * leave RPM permanently disabled).
2665 */
2666 ret = vlv_force_gfx_clock(dev_priv, true);
2667
2668 if (!IS_CHERRYVIEW(dev_priv))
2669 vlv_restore_gunit_s0ix_state(dev_priv);
2670
2671 err = vlv_allow_gt_wake(dev_priv, true);
2672 if (!ret)
2673 ret = err;
2674
2675 err = vlv_force_gfx_clock(dev_priv, false);
2676 if (!ret)
2677 ret = err;
2678
2679 vlv_check_no_gt_access(dev_priv);
2680
2681 if (rpm_resume)
2682 intel_init_clock_gating(dev_priv);
2683
2684 return ret;
2685}
2686
2687static int intel_runtime_suspend(struct device *kdev)
2688{
2689 struct pci_dev *pdev = to_pci_dev(kdev);
2690 struct drm_device *dev = pci_get_drvdata(pdev);
2691 struct drm_i915_private *dev_priv = to_i915(dev);
2692 int ret;
2693
2694 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2695 return -ENODEV;
2696
2697 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2698 return -ENODEV;
2699
2700 DRM_DEBUG_KMS("Suspending device\n");
2701
2702 disable_rpm_wakeref_asserts(dev_priv);
2703
2704 /*
2705 * We are safe here against re-faults, since the fault handler takes
2706 * an RPM reference.
2707 */
2708 i915_gem_runtime_suspend(dev_priv);
2709
2710 intel_uc_suspend(dev_priv);
2711
2712 intel_runtime_pm_disable_interrupts(dev_priv);
2713
2714 intel_uncore_suspend(dev_priv);
2715
2716 ret = 0;
2717 if (INTEL_GEN(dev_priv) >= 11) {
2718 icl_display_core_uninit(dev_priv);
2719 bxt_enable_dc9(dev_priv);
2720 } else if (IS_GEN9_LP(dev_priv)) {
2721 bxt_display_core_uninit(dev_priv);
2722 bxt_enable_dc9(dev_priv);
2723 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2724 hsw_enable_pc8(dev_priv);
2725 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2726 ret = vlv_suspend_complete(dev_priv);
2727 }
2728
2729 if (ret) {
2730 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2731 intel_uncore_runtime_resume(dev_priv);
2732
2733 intel_runtime_pm_enable_interrupts(dev_priv);
2734
2735 intel_uc_resume(dev_priv);
2736
2737 i915_gem_init_swizzling(dev_priv);
2738 i915_gem_restore_fences(dev_priv);
2739
2740 enable_rpm_wakeref_asserts(dev_priv);
2741
2742 return ret;
2743 }
2744
2745 enable_rpm_wakeref_asserts(dev_priv);
2746 intel_runtime_pm_cleanup(dev_priv);
2747
2748 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2749 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2750
2751 dev_priv->runtime_pm.suspended = true;
2752
2753 /*
2754 * FIXME: We really should find a document that references the arguments
2755 * used below!
2756 */
2757 if (IS_BROADWELL(dev_priv)) {
2758 /*
2759 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2760 * being detected, and the call we do at intel_runtime_resume()
2761 * won't be able to restore them. Since PCI_D3hot matches the
2762 * actual specification and appears to be working, use it.
2763 */
2764 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2765 } else {
2766 /*
2767 * current versions of firmware which depend on this opregion
2768 * notification have repurposed the D1 definition to mean
2769 * "runtime suspended" vs. what you would normally expect (D3)
2770 * to distinguish it from notifications that might be sent via
2771 * the suspend path.
2772 */
2773 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2774 }
2775
2776 assert_forcewakes_inactive(dev_priv);
2777
2778 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2779 intel_hpd_poll_init(dev_priv);
2780
2781 DRM_DEBUG_KMS("Device suspended\n");
2782 return 0;
2783}
2784
2785static int intel_runtime_resume(struct device *kdev)
2786{
2787 struct pci_dev *pdev = to_pci_dev(kdev);
2788 struct drm_device *dev = pci_get_drvdata(pdev);
2789 struct drm_i915_private *dev_priv = to_i915(dev);
2790 int ret = 0;
2791
2792 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2793 return -ENODEV;
2794
2795 DRM_DEBUG_KMS("Resuming device\n");
2796
2797 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2798 disable_rpm_wakeref_asserts(dev_priv);
2799
2800 intel_opregion_notify_adapter(dev_priv, PCI_D0);
2801 dev_priv->runtime_pm.suspended = false;
2802 if (intel_uncore_unclaimed_mmio(dev_priv))
2803 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2804
2805 if (INTEL_GEN(dev_priv) >= 11) {
2806 bxt_disable_dc9(dev_priv);
2807 icl_display_core_init(dev_priv, true);
2808 if (dev_priv->csr.dmc_payload) {
2809 if (dev_priv->csr.allowed_dc_mask &
2810 DC_STATE_EN_UPTO_DC6)
2811 skl_enable_dc6(dev_priv);
2812 else if (dev_priv->csr.allowed_dc_mask &
2813 DC_STATE_EN_UPTO_DC5)
2814 gen9_enable_dc5(dev_priv);
2815 }
2816 } else if (IS_GEN9_LP(dev_priv)) {
2817 bxt_disable_dc9(dev_priv);
2818 bxt_display_core_init(dev_priv, true);
2819 if (dev_priv->csr.dmc_payload &&
2820 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2821 gen9_enable_dc5(dev_priv);
2822 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2823 hsw_disable_pc8(dev_priv);
2824 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2825 ret = vlv_resume_prepare(dev_priv, true);
2826 }
2827
2828 intel_uncore_runtime_resume(dev_priv);
2829
2830 intel_runtime_pm_enable_interrupts(dev_priv);
2831
2832 intel_uc_resume(dev_priv);
2833
2834 /*
2835 * No point of rolling back things in case of an error, as the best
2836 * we can do is to hope that things will still work (and disable RPM).
2837 */
2838 i915_gem_init_swizzling(dev_priv);
2839 i915_gem_restore_fences(dev_priv);
2840
2841 /*
2842 * On VLV/CHV display interrupts are part of the display
2843 * power well, so hpd is reinitialized from there. For
2844 * everyone else do it here.
2845 */
2846 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2847 intel_hpd_init(dev_priv);
2848
2849 intel_enable_ipc(dev_priv);
2850
2851 enable_rpm_wakeref_asserts(dev_priv);
2852
2853 if (ret)
2854 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2855 else
2856 DRM_DEBUG_KMS("Device resumed\n");
2857
2858 return ret;
2859}
2860
2861const struct dev_pm_ops i915_pm_ops = {
2862 /*
2863 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2864 * PMSG_RESUME]
2865 */
2866 .prepare = i915_pm_prepare,
2867 .suspend = i915_pm_suspend,
2868 .suspend_late = i915_pm_suspend_late,
2869 .resume_early = i915_pm_resume_early,
2870 .resume = i915_pm_resume,
2871
2872 /*
2873 * S4 event handlers
2874 * @freeze, @freeze_late : called (1) before creating the
2875 * hibernation image [PMSG_FREEZE] and
2876 * (2) after rebooting, before restoring
2877 * the image [PMSG_QUIESCE]
2878 * @thaw, @thaw_early : called (1) after creating the hibernation
2879 * image, before writing it [PMSG_THAW]
2880 * and (2) after failing to create or
2881 * restore the image [PMSG_RECOVER]
2882 * @poweroff, @poweroff_late: called after writing the hibernation
2883 * image, before rebooting [PMSG_HIBERNATE]
2884 * @restore, @restore_early : called after rebooting and restoring the
2885 * hibernation image [PMSG_RESTORE]
2886 */
2887 .freeze = i915_pm_freeze,
2888 .freeze_late = i915_pm_freeze_late,
2889 .thaw_early = i915_pm_thaw_early,
2890 .thaw = i915_pm_thaw,
2891 .poweroff = i915_pm_suspend,
2892 .poweroff_late = i915_pm_poweroff_late,
2893 .restore_early = i915_pm_restore_early,
2894 .restore = i915_pm_restore,
2895
2896 /* S0ix (via runtime suspend) event handlers */
2897 .runtime_suspend = intel_runtime_suspend,
2898 .runtime_resume = intel_runtime_resume,
2899};
2900
2901static const struct vm_operations_struct i915_gem_vm_ops = {
2902 .fault = i915_gem_fault,
2903 .open = drm_gem_vm_open,
2904 .close = drm_gem_vm_close,
2905};
2906
2907static const struct file_operations i915_driver_fops = {
2908 .owner = THIS_MODULE,
2909 .open = drm_open,
2910 .release = drm_release,
2911 .unlocked_ioctl = drm_ioctl,
2912 .mmap = drm_gem_mmap,
2913 .poll = drm_poll,
2914 .read = drm_read,
2915 .compat_ioctl = i915_compat_ioctl,
2916 .llseek = noop_llseek,
2917};
2918
2919static int
2920i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2921 struct drm_file *file)
2922{
2923 return -ENODEV;
2924}
2925
2926static const struct drm_ioctl_desc i915_ioctls[] = {
2927 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2928 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2929 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2930 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2931 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2932 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2933 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2934 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2935 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2936 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2937 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2938 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2939 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2940 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2941 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2942 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2943 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2944 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2945 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2946 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2947 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2948 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2949 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2950 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2951 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2952 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2953 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2954 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2955 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2956 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2957 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2958 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2959 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2960 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2961 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2962 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2963 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
2964 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2965 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
2966 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2967 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2968 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
2969 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
2970 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
2971 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2972 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2973 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2974 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2975 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2976 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2977 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2978 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2979 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
2980 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2981 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2982 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2983};
2984
2985static struct drm_driver driver = {
2986 /* Don't use MTRRs here; the Xserver or userspace app should
2987 * deal with them for Intel hardware.
2988 */
2989 .driver_features =
2990 DRIVER_GEM | DRIVER_PRIME |
2991 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
2992 .release = i915_driver_release,
2993 .open = i915_driver_open,
2994 .lastclose = i915_driver_lastclose,
2995 .postclose = i915_driver_postclose,
2996
2997 .gem_close_object = i915_gem_close_object,
2998 .gem_free_object_unlocked = i915_gem_free_object,
2999 .gem_vm_ops = &i915_gem_vm_ops,
3000
3001 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3002 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3003 .gem_prime_export = i915_gem_prime_export,
3004 .gem_prime_import = i915_gem_prime_import,
3005
3006 .dumb_create = i915_gem_dumb_create,
3007 .dumb_map_offset = i915_gem_mmap_gtt,
3008 .ioctls = i915_ioctls,
3009 .num_ioctls = ARRAY_SIZE(i915_ioctls),
3010 .fops = &i915_driver_fops,
3011 .name = DRIVER_NAME,
3012 .desc = DRIVER_DESC,
3013 .date = DRIVER_DATE,
3014 .major = DRIVER_MAJOR,
3015 .minor = DRIVER_MINOR,
3016 .patchlevel = DRIVER_PATCHLEVEL,
3017};
3018
3019#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3020#include "selftests/mock_drm.c"
3021#endif
3022