1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright © 2020 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef __I915_GEM_GTT_H__ |
7 | #define __I915_GEM_GTT_H__ |
8 | |
9 | #include <linux/io-mapping.h> |
10 | #include <linux/types.h> |
11 | |
12 | #include <drm/drm_mm.h> |
13 | |
14 | #include "gt/intel_gtt.h" |
15 | #include "i915_scatterlist.h" |
16 | |
17 | struct drm_i915_gem_object; |
18 | struct i915_address_space; |
19 | struct i915_gem_ww_ctx; |
20 | |
21 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |
22 | |
23 | int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
24 | struct sg_table *pages); |
25 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
26 | struct sg_table *pages); |
27 | |
28 | int i915_gem_gtt_reserve(struct i915_address_space *vm, |
29 | struct i915_gem_ww_ctx *ww, |
30 | struct drm_mm_node *node, |
31 | u64 size, u64 offset, unsigned long color, |
32 | unsigned int flags); |
33 | |
34 | int i915_gem_gtt_insert(struct i915_address_space *vm, |
35 | struct i915_gem_ww_ctx *ww, |
36 | struct drm_mm_node *node, |
37 | u64 size, u64 alignment, unsigned long color, |
38 | u64 start, u64 end, unsigned int flags); |
39 | |
40 | /* Flags used by pin/bind&friends. */ |
41 | #define PIN_NOEVICT BIT_ULL(0) |
42 | #define PIN_NOSEARCH BIT_ULL(1) |
43 | #define PIN_NONBLOCK BIT_ULL(2) |
44 | #define PIN_MAPPABLE BIT_ULL(3) |
45 | #define PIN_ZONE_4G BIT_ULL(4) |
46 | #define PIN_HIGH BIT_ULL(5) |
47 | #define PIN_OFFSET_BIAS BIT_ULL(6) |
48 | #define PIN_OFFSET_FIXED BIT_ULL(7) |
49 | #define PIN_OFFSET_GUARD BIT_ULL(8) |
50 | #define PIN_VALIDATE BIT_ULL(9) /* validate placement only, no need to call unpin() */ |
51 | |
52 | #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */ |
53 | #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */ |
54 | |
55 | #define PIN_OFFSET_MASK I915_GTT_PAGE_MASK |
56 | |
57 | #endif |
58 | |