1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX drm driver - LVDS display bridge
4 *
5 * Copyright (C) 2012 Sascha Hauer, Pengutronix
6 */
7
8#include <linux/module.h>
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <drm/drmP.h>
12#include <drm/drm_atomic.h>
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_fb_helper.h>
15#include <drm/drm_of.h>
16#include <drm/drm_panel.h>
17#include <drm/drm_probe_helper.h>
18#include <linux/mfd/syscon.h>
19#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20#include <linux/of_device.h>
21#include <linux/of_graph.h>
22#include <video/of_display_timing.h>
23#include <video/of_videomode.h>
24#include <linux/regmap.h>
25#include <linux/videodev2.h>
26
27#include "imx-drm.h"
28
29#define DRIVER_NAME "imx-ldb"
30
31#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
32#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
33#define LDB_CH0_MODE_EN_MASK (3 << 0)
34#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
35#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
36#define LDB_CH1_MODE_EN_MASK (3 << 2)
37#define LDB_SPLIT_MODE_EN (1 << 4)
38#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
39#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
40#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
41#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
42#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
43#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
44#define LDB_BGREF_RMODE_INT (1 << 15)
45
46struct imx_ldb;
47
48struct imx_ldb_channel {
49 struct imx_ldb *ldb;
50 struct drm_connector connector;
51 struct drm_encoder encoder;
52
53 /* Defines what is connected to the ldb, only one at a time */
54 struct drm_panel *panel;
55 struct drm_bridge *bridge;
56
57 struct device_node *child;
58 struct i2c_adapter *ddc;
59 int chno;
60 void *edid;
61 int edid_len;
62 struct drm_display_mode mode;
63 int mode_valid;
64 u32 bus_format;
65 u32 bus_flags;
66};
67
68static inline struct imx_ldb_channel *con_to_imx_ldb_ch(struct drm_connector *c)
69{
70 return container_of(c, struct imx_ldb_channel, connector);
71}
72
73static inline struct imx_ldb_channel *enc_to_imx_ldb_ch(struct drm_encoder *e)
74{
75 return container_of(e, struct imx_ldb_channel, encoder);
76}
77
78struct bus_mux {
79 int reg;
80 int shift;
81 int mask;
82};
83
84struct imx_ldb {
85 struct regmap *regmap;
86 struct device *dev;
87 struct imx_ldb_channel channel[2];
88 struct clk *clk[2]; /* our own clock */
89 struct clk *clk_sel[4]; /* parent of display clock */
90 struct clk *clk_parent[4]; /* original parent of clk_sel */
91 struct clk *clk_pll[2]; /* upstream clock we can adjust */
92 u32 ldb_ctrl;
93 const struct bus_mux *lvds_mux;
94};
95
96static void imx_ldb_ch_set_bus_format(struct imx_ldb_channel *imx_ldb_ch,
97 u32 bus_format)
98{
99 struct imx_ldb *ldb = imx_ldb_ch->ldb;
100 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
101
102 switch (bus_format) {
103 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
104 break;
105 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
106 if (imx_ldb_ch->chno == 0 || dual)
107 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
108 if (imx_ldb_ch->chno == 1 || dual)
109 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
110 break;
111 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
112 if (imx_ldb_ch->chno == 0 || dual)
113 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
114 LDB_BIT_MAP_CH0_JEIDA;
115 if (imx_ldb_ch->chno == 1 || dual)
116 ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
117 LDB_BIT_MAP_CH1_JEIDA;
118 break;
119 }
120}
121
122static int imx_ldb_connector_get_modes(struct drm_connector *connector)
123{
124 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
125 int num_modes = 0;
126
127 if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
128 imx_ldb_ch->panel->funcs->get_modes) {
129 num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
130 if (num_modes > 0)
131 return num_modes;
132 }
133
134 if (!imx_ldb_ch->edid && imx_ldb_ch->ddc)
135 imx_ldb_ch->edid = drm_get_edid(connector, imx_ldb_ch->ddc);
136
137 if (imx_ldb_ch->edid) {
138 drm_connector_update_edid_property(connector,
139 imx_ldb_ch->edid);
140 num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
141 }
142
143 if (imx_ldb_ch->mode_valid) {
144 struct drm_display_mode *mode;
145
146 mode = drm_mode_create(connector->dev);
147 if (!mode)
148 return -EINVAL;
149 drm_mode_copy(mode, &imx_ldb_ch->mode);
150 mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
151 drm_mode_probed_add(connector, mode);
152 num_modes++;
153 }
154
155 return num_modes;
156}
157
158static struct drm_encoder *imx_ldb_connector_best_encoder(
159 struct drm_connector *connector)
160{
161 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
162
163 return &imx_ldb_ch->encoder;
164}
165
166static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
167 unsigned long serial_clk, unsigned long di_clk)
168{
169 int ret;
170
171 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
172 clk_get_rate(ldb->clk_pll[chno]), serial_clk);
173 clk_set_rate(ldb->clk_pll[chno], serial_clk);
174
175 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
176 clk_get_rate(ldb->clk_pll[chno]));
177
178 dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
179 clk_get_rate(ldb->clk[chno]),
180 (long int)di_clk);
181 clk_set_rate(ldb->clk[chno], di_clk);
182
183 dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
184 clk_get_rate(ldb->clk[chno]));
185
186 /* set display clock mux to LDB input clock */
187 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
188 if (ret)
189 dev_err(ldb->dev,
190 "unable to set di%d parent clock to ldb_di%d\n", mux,
191 chno);
192}
193
194static void imx_ldb_encoder_enable(struct drm_encoder *encoder)
195{
196 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
197 struct imx_ldb *ldb = imx_ldb_ch->ldb;
198 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
199 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
200
201 drm_panel_prepare(imx_ldb_ch->panel);
202
203 if (dual) {
204 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]);
205 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]);
206
207 clk_prepare_enable(ldb->clk[0]);
208 clk_prepare_enable(ldb->clk[1]);
209 } else {
210 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]);
211 }
212
213 if (imx_ldb_ch == &ldb->channel[0] || dual) {
214 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
215 if (mux == 0 || ldb->lvds_mux)
216 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
217 else if (mux == 1)
218 ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
219 }
220 if (imx_ldb_ch == &ldb->channel[1] || dual) {
221 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
222 if (mux == 1 || ldb->lvds_mux)
223 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
224 else if (mux == 0)
225 ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
226 }
227
228 if (ldb->lvds_mux) {
229 const struct bus_mux *lvds_mux = NULL;
230
231 if (imx_ldb_ch == &ldb->channel[0])
232 lvds_mux = &ldb->lvds_mux[0];
233 else if (imx_ldb_ch == &ldb->channel[1])
234 lvds_mux = &ldb->lvds_mux[1];
235
236 regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
237 mux << lvds_mux->shift);
238 }
239
240 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
241
242 drm_panel_enable(imx_ldb_ch->panel);
243}
244
245static void
246imx_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
247 struct drm_crtc_state *crtc_state,
248 struct drm_connector_state *connector_state)
249{
250 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
251 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
252 struct imx_ldb *ldb = imx_ldb_ch->ldb;
253 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
254 unsigned long serial_clk;
255 unsigned long di_clk = mode->clock * 1000;
256 int mux = drm_of_encoder_active_port_id(imx_ldb_ch->child, encoder);
257 u32 bus_format = imx_ldb_ch->bus_format;
258
259 if (mode->clock > 170000) {
260 dev_warn(ldb->dev,
261 "%s: mode exceeds 170 MHz pixel clock\n", __func__);
262 }
263 if (mode->clock > 85000 && !dual) {
264 dev_warn(ldb->dev,
265 "%s: mode exceeds 85 MHz pixel clock\n", __func__);
266 }
267
268 if (dual) {
269 serial_clk = 3500UL * mode->clock;
270 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
271 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
272 } else {
273 serial_clk = 7000UL * mode->clock;
274 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
275 di_clk);
276 }
277
278 /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
279 if (imx_ldb_ch == &ldb->channel[0] || dual) {
280 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
281 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
282 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
283 ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
284 }
285 if (imx_ldb_ch == &ldb->channel[1] || dual) {
286 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
287 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
288 else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
289 ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
290 }
291
292 if (!bus_format) {
293 struct drm_connector *connector = connector_state->connector;
294 struct drm_display_info *di = &connector->display_info;
295
296 if (di->num_bus_formats)
297 bus_format = di->bus_formats[0];
298 }
299 imx_ldb_ch_set_bus_format(imx_ldb_ch, bus_format);
300}
301
302static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
303{
304 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
305 struct imx_ldb *ldb = imx_ldb_ch->ldb;
306 int mux, ret;
307
308 drm_panel_disable(imx_ldb_ch->panel);
309
310 if (imx_ldb_ch == &ldb->channel[0])
311 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
312 else if (imx_ldb_ch == &ldb->channel[1])
313 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
314
315 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
316
317 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
318 clk_disable_unprepare(ldb->clk[0]);
319 clk_disable_unprepare(ldb->clk[1]);
320 }
321
322 if (ldb->lvds_mux) {
323 const struct bus_mux *lvds_mux = NULL;
324
325 if (imx_ldb_ch == &ldb->channel[0])
326 lvds_mux = &ldb->lvds_mux[0];
327 else if (imx_ldb_ch == &ldb->channel[1])
328 lvds_mux = &ldb->lvds_mux[1];
329
330 regmap_read(ldb->regmap, lvds_mux->reg, &mux);
331 mux &= lvds_mux->mask;
332 mux >>= lvds_mux->shift;
333 } else {
334 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
335 }
336
337 /* set display clock mux back to original input clock */
338 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
339 if (ret)
340 dev_err(ldb->dev,
341 "unable to set di%d parent clock to original parent\n",
342 mux);
343
344 drm_panel_unprepare(imx_ldb_ch->panel);
345}
346
347static int imx_ldb_encoder_atomic_check(struct drm_encoder *encoder,
348 struct drm_crtc_state *crtc_state,
349 struct drm_connector_state *conn_state)
350{
351 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
352 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
353 struct drm_display_info *di = &conn_state->connector->display_info;
354 u32 bus_format = imx_ldb_ch->bus_format;
355
356 /* Bus format description in DT overrides connector display info. */
357 if (!bus_format && di->num_bus_formats) {
358 bus_format = di->bus_formats[0];
359 imx_crtc_state->bus_flags = di->bus_flags;
360 } else {
361 bus_format = imx_ldb_ch->bus_format;
362 imx_crtc_state->bus_flags = imx_ldb_ch->bus_flags;
363 }
364 switch (bus_format) {
365 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
366 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
367 break;
368 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
369 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
370 imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
371 break;
372 default:
373 return -EINVAL;
374 }
375
376 imx_crtc_state->di_hsync_pin = 2;
377 imx_crtc_state->di_vsync_pin = 3;
378
379 return 0;
380}
381
382
383static const struct drm_connector_funcs imx_ldb_connector_funcs = {
384 .fill_modes = drm_helper_probe_single_connector_modes,
385 .destroy = imx_drm_connector_destroy,
386 .reset = drm_atomic_helper_connector_reset,
387 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
388 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
389};
390
391static const struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
392 .get_modes = imx_ldb_connector_get_modes,
393 .best_encoder = imx_ldb_connector_best_encoder,
394};
395
396static const struct drm_encoder_funcs imx_ldb_encoder_funcs = {
397 .destroy = imx_drm_encoder_destroy,
398};
399
400static const struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
401 .atomic_mode_set = imx_ldb_encoder_atomic_mode_set,
402 .enable = imx_ldb_encoder_enable,
403 .disable = imx_ldb_encoder_disable,
404 .atomic_check = imx_ldb_encoder_atomic_check,
405};
406
407static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
408{
409 char clkname[16];
410
411 snprintf(clkname, sizeof(clkname), "di%d", chno);
412 ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
413 if (IS_ERR(ldb->clk[chno]))
414 return PTR_ERR(ldb->clk[chno]);
415
416 snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
417 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
418
419 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
420}
421
422static int imx_ldb_register(struct drm_device *drm,
423 struct imx_ldb_channel *imx_ldb_ch)
424{
425 struct imx_ldb *ldb = imx_ldb_ch->ldb;
426 struct drm_encoder *encoder = &imx_ldb_ch->encoder;
427 int ret;
428
429 ret = imx_drm_encoder_parse_of(drm, encoder, imx_ldb_ch->child);
430 if (ret)
431 return ret;
432
433 ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
434 if (ret)
435 return ret;
436
437 if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
438 ret = imx_ldb_get_clk(ldb, 1);
439 if (ret)
440 return ret;
441 }
442
443 drm_encoder_helper_add(encoder, &imx_ldb_encoder_helper_funcs);
444 drm_encoder_init(drm, encoder, &imx_ldb_encoder_funcs,
445 DRM_MODE_ENCODER_LVDS, NULL);
446
447 if (imx_ldb_ch->bridge) {
448 ret = drm_bridge_attach(&imx_ldb_ch->encoder,
449 imx_ldb_ch->bridge, NULL);
450 if (ret) {
451 DRM_ERROR("Failed to initialize bridge with drm\n");
452 return ret;
453 }
454 } else {
455 /*
456 * We want to add the connector whenever there is no bridge
457 * that brings its own, not only when there is a panel. For
458 * historical reasons, the ldb driver can also work without
459 * a panel.
460 */
461 drm_connector_helper_add(&imx_ldb_ch->connector,
462 &imx_ldb_connector_helper_funcs);
463 drm_connector_init(drm, &imx_ldb_ch->connector,
464 &imx_ldb_connector_funcs,
465 DRM_MODE_CONNECTOR_LVDS);
466 drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
467 }
468
469 if (imx_ldb_ch->panel) {
470 ret = drm_panel_attach(imx_ldb_ch->panel,
471 &imx_ldb_ch->connector);
472 if (ret)
473 return ret;
474 }
475
476 return 0;
477}
478
479enum {
480 LVDS_BIT_MAP_SPWG,
481 LVDS_BIT_MAP_JEIDA
482};
483
484struct imx_ldb_bit_mapping {
485 u32 bus_format;
486 u32 datawidth;
487 const char * const mapping;
488};
489
490static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
491 { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
492 { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
493 { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
494};
495
496static u32 of_get_bus_format(struct device *dev, struct device_node *np)
497{
498 const char *bm;
499 u32 datawidth = 0;
500 int ret, i;
501
502 ret = of_property_read_string(np, "fsl,data-mapping", &bm);
503 if (ret < 0)
504 return ret;
505
506 of_property_read_u32(np, "fsl,data-width", &datawidth);
507
508 for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
509 if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
510 datawidth == imx_ldb_bit_mappings[i].datawidth)
511 return imx_ldb_bit_mappings[i].bus_format;
512 }
513
514 dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
515
516 return -ENOENT;
517}
518
519static struct bus_mux imx6q_lvds_mux[2] = {
520 {
521 .reg = IOMUXC_GPR3,
522 .shift = 6,
523 .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
524 }, {
525 .reg = IOMUXC_GPR3,
526 .shift = 8,
527 .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
528 }
529};
530
531/*
532 * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
533 * of_match_device will walk through this list and take the first entry
534 * matching any of its compatible values. Therefore, the more generic
535 * entries (in this case fsl,imx53-ldb) need to be ordered last.
536 */
537static const struct of_device_id imx_ldb_dt_ids[] = {
538 { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
539 { .compatible = "fsl,imx53-ldb", .data = NULL, },
540 { }
541};
542MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
543
544static int imx_ldb_panel_ddc(struct device *dev,
545 struct imx_ldb_channel *channel, struct device_node *child)
546{
547 struct device_node *ddc_node;
548 const u8 *edidp;
549 int ret;
550
551 ddc_node = of_parse_phandle(child, "ddc-i2c-bus", 0);
552 if (ddc_node) {
553 channel->ddc = of_find_i2c_adapter_by_node(ddc_node);
554 of_node_put(ddc_node);
555 if (!channel->ddc) {
556 dev_warn(dev, "failed to get ddc i2c adapter\n");
557 return -EPROBE_DEFER;
558 }
559 }
560
561 if (!channel->ddc) {
562 /* if no DDC available, fallback to hardcoded EDID */
563 dev_dbg(dev, "no ddc available\n");
564
565 edidp = of_get_property(child, "edid",
566 &channel->edid_len);
567 if (edidp) {
568 channel->edid = kmemdup(edidp,
569 channel->edid_len,
570 GFP_KERNEL);
571 } else if (!channel->panel) {
572 /* fallback to display-timings node */
573 ret = of_get_drm_display_mode(child,
574 &channel->mode,
575 &channel->bus_flags,
576 OF_USE_NATIVE_MODE);
577 if (!ret)
578 channel->mode_valid = 1;
579 }
580 }
581 return 0;
582}
583
584static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
585{
586 struct drm_device *drm = data;
587 struct device_node *np = dev->of_node;
588 const struct of_device_id *of_id =
589 of_match_device(imx_ldb_dt_ids, dev);
590 struct device_node *child;
591 struct imx_ldb *imx_ldb;
592 int dual;
593 int ret;
594 int i;
595
596 imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
597 if (!imx_ldb)
598 return -ENOMEM;
599
600 imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
601 if (IS_ERR(imx_ldb->regmap)) {
602 dev_err(dev, "failed to get parent regmap\n");
603 return PTR_ERR(imx_ldb->regmap);
604 }
605
606 /* disable LDB by resetting the control register to POR default */
607 regmap_write(imx_ldb->regmap, IOMUXC_GPR2, 0);
608
609 imx_ldb->dev = dev;
610
611 if (of_id)
612 imx_ldb->lvds_mux = of_id->data;
613
614 dual = of_property_read_bool(np, "fsl,dual-channel");
615 if (dual)
616 imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
617
618 /*
619 * There are three different possible clock mux configurations:
620 * i.MX53: ipu1_di0_sel, ipu1_di1_sel
621 * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
622 * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
623 * Map them all to di0_sel...di3_sel.
624 */
625 for (i = 0; i < 4; i++) {
626 char clkname[16];
627
628 sprintf(clkname, "di%d_sel", i);
629 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
630 if (IS_ERR(imx_ldb->clk_sel[i])) {
631 ret = PTR_ERR(imx_ldb->clk_sel[i]);
632 imx_ldb->clk_sel[i] = NULL;
633 break;
634 }
635
636 imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
637 }
638 if (i == 0)
639 return ret;
640
641 for_each_child_of_node(np, child) {
642 struct imx_ldb_channel *channel;
643 int bus_format;
644
645 ret = of_property_read_u32(child, "reg", &i);
646 if (ret || i < 0 || i > 1) {
647 ret = -EINVAL;
648 goto free_child;
649 }
650
651 if (!of_device_is_available(child))
652 continue;
653
654 if (dual && i > 0) {
655 dev_warn(dev, "dual-channel mode, ignoring second output\n");
656 continue;
657 }
658
659 channel = &imx_ldb->channel[i];
660 channel->ldb = imx_ldb;
661 channel->chno = i;
662
663 /*
664 * The output port is port@4 with an external 4-port mux or
665 * port@2 with the internal 2-port mux.
666 */
667 ret = drm_of_find_panel_or_bridge(child,
668 imx_ldb->lvds_mux ? 4 : 2, 0,
669 &channel->panel, &channel->bridge);
670 if (ret && ret != -ENODEV)
671 goto free_child;
672
673 /* panel ddc only if there is no bridge */
674 if (!channel->bridge) {
675 ret = imx_ldb_panel_ddc(dev, channel, child);
676 if (ret)
677 goto free_child;
678 }
679
680 bus_format = of_get_bus_format(dev, child);
681 if (bus_format == -EINVAL) {
682 /*
683 * If no bus format was specified in the device tree,
684 * we can still get it from the connected panel later.
685 */
686 if (channel->panel && channel->panel->funcs &&
687 channel->panel->funcs->get_modes)
688 bus_format = 0;
689 }
690 if (bus_format < 0) {
691 dev_err(dev, "could not determine data mapping: %d\n",
692 bus_format);
693 ret = bus_format;
694 goto free_child;
695 }
696 channel->bus_format = bus_format;
697 channel->child = child;
698
699 ret = imx_ldb_register(drm, channel);
700 if (ret) {
701 channel->child = NULL;
702 goto free_child;
703 }
704 }
705
706 dev_set_drvdata(dev, imx_ldb);
707
708 return 0;
709
710free_child:
711 of_node_put(child);
712 return ret;
713}
714
715static void imx_ldb_unbind(struct device *dev, struct device *master,
716 void *data)
717{
718 struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
719 int i;
720
721 for (i = 0; i < 2; i++) {
722 struct imx_ldb_channel *channel = &imx_ldb->channel[i];
723
724 if (channel->panel)
725 drm_panel_detach(channel->panel);
726
727 kfree(channel->edid);
728 i2c_put_adapter(channel->ddc);
729 }
730}
731
732static const struct component_ops imx_ldb_ops = {
733 .bind = imx_ldb_bind,
734 .unbind = imx_ldb_unbind,
735};
736
737static int imx_ldb_probe(struct platform_device *pdev)
738{
739 return component_add(&pdev->dev, &imx_ldb_ops);
740}
741
742static int imx_ldb_remove(struct platform_device *pdev)
743{
744 component_del(&pdev->dev, &imx_ldb_ops);
745 return 0;
746}
747
748static struct platform_driver imx_ldb_driver = {
749 .probe = imx_ldb_probe,
750 .remove = imx_ldb_remove,
751 .driver = {
752 .of_match_table = imx_ldb_dt_ids,
753 .name = DRIVER_NAME,
754 },
755};
756
757module_platform_driver(imx_ldb_driver);
758
759MODULE_DESCRIPTION("i.MX LVDS driver");
760MODULE_AUTHOR("Sascha Hauer, Pengutronix");
761MODULE_LICENSE("GPL");
762MODULE_ALIAS("platform:" DRIVER_NAME);
763