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1/* SPDX-License-Identifier: MIT */
2#ifndef __NVIF_CLASS_H__
3#define __NVIF_CLASS_H__
4
5/* these class numbers are made up by us, and not nvidia-assigned */
6#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
7
8#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
9
10#define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
11#define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
12
13#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
14#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
15#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
16#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
17
18#define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
19#define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
20#define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
21#define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
22
23#define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
24#define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
25#define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
26#define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
27
28#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
29#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
30#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
31#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
32#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
33#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
34
35#define NVIF_CLASS_EVENT /* if000e.h */ 0x8000000e
36
37#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010
38#define NVIF_CLASS_CONN /* if0011.h */ 0x80000011
39#define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012
40#define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013
41#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014
42
43#define NVIF_CLASS_CHAN /* if0020.h */ 0x80000020
44#define NVIF_CLASS_CGRP /* if0021.h */ 0x80000021
45
46/* the below match nvidia-assigned (either in hw, or sw) class numbers */
47#define NV_NULL_CLASS 0x00000030
48
49#define NV_DEVICE /* cl0080.h */ 0x00000080
50
51#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
52#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
53#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
54
55#define NV50_TWOD 0x0000502d
56#define FERMI_TWOD_A 0x0000902d
57
58#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
59#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
60
61#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
62#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
63
64#define NV04_DISP /* cl0046.h */ 0x00000046
65
66#define VOLTA_USERMODE_A 0x0000c361
67#define TURING_USERMODE_A 0x0000c461
68#define AMPERE_USERMODE_A 0x0000c561
69
70#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
71#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
72
73#define NV03_CHANNEL_DMA /* if0020.h */ 0x0000006b
74#define NV10_CHANNEL_DMA /* if0020.h */ 0x0000006e
75#define NV17_CHANNEL_DMA /* if0020.h */ 0x0000176e
76#define NV40_CHANNEL_DMA /* if0020.h */ 0x0000406e
77
78#define KEPLER_CHANNEL_GROUP_A /* if0021.h */ 0x0000a06c
79
80#define NV50_CHANNEL_GPFIFO /* if0020.h */ 0x0000506f
81#define G82_CHANNEL_GPFIFO /* if0020.h */ 0x0000826f
82#define FERMI_CHANNEL_GPFIFO /* if0020.h */ 0x0000906f
83#define KEPLER_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000a06f
84#define KEPLER_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000a16f
85#define MAXWELL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000b06f
86#define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f
87#define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f
88#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
89#define AMPERE_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c56f
90#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
91
92#define NV50_DISP /* if0010.h */ 0x00005070
93#define G82_DISP /* if0010.h */ 0x00008270
94#define GT200_DISP /* if0010.h */ 0x00008370
95#define GT214_DISP /* if0010.h */ 0x00008570
96#define GT206_DISP /* if0010.h */ 0x00008870
97#define GF110_DISP /* if0010.h */ 0x00009070
98#define GK104_DISP /* if0010.h */ 0x00009170
99#define GK110_DISP /* if0010.h */ 0x00009270
100#define GM107_DISP /* if0010.h */ 0x00009470
101#define GM200_DISP /* if0010.h */ 0x00009570
102#define GP100_DISP /* if0010.h */ 0x00009770
103#define GP102_DISP /* if0010.h */ 0x00009870
104#define GV100_DISP /* if0010.h */ 0x0000c370
105#define TU102_DISP /* if0010.h */ 0x0000c570
106#define GA102_DISP /* if0010.h */ 0x0000c670
107#define AD102_DISP /* if0010.h */ 0x0000c770
108
109#define GV100_DISP_CAPS 0x0000c373
110
111#define NV31_MPEG 0x00003174
112#define G82_MPEG 0x00008274
113
114#define NV74_VP2 0x00007476
115
116#define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a
117#define G82_DISP_CURSOR /* if0014.h */ 0x0000827a
118#define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a
119#define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a
120#define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a
121#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
122#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
123#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
124
125#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
126#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
127#define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b
128#define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b
129#define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b
130
131#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
132#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
133#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
134
135#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
136#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
137#define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c
138#define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c
139#define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c
140#define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c
141#define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c
142
143#define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d
144#define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d
145#define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d
146#define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d
147#define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d
148#define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d
149#define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d
150#define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d
151#define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d
152#define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d
153#define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d
154#define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d
155#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d
156#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
157#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
158#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
159
160#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
161#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
162#define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e
163#define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e
164#define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e
165#define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e
166
167#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
168#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
169#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
170
171#define NV50_TESLA 0x00005097
172#define G82_TESLA 0x00008297
173#define GT200_TESLA 0x00008397
174#define GT214_TESLA 0x00008597
175#define GT21A_TESLA 0x00008697
176
177#define FERMI_A /* cl9097.h */ 0x00009097
178#define FERMI_B /* cl9097.h */ 0x00009197
179#define FERMI_C /* cl9097.h */ 0x00009297
180
181#define KEPLER_A /* cl9097.h */ 0x0000a097
182#define KEPLER_B /* cl9097.h */ 0x0000a197
183#define KEPLER_C /* cl9097.h */ 0x0000a297
184
185#define MAXWELL_A /* cl9097.h */ 0x0000b097
186#define MAXWELL_B /* cl9097.h */ 0x0000b197
187
188#define PASCAL_A /* cl9097.h */ 0x0000c097
189#define PASCAL_B /* cl9097.h */ 0x0000c197
190
191#define VOLTA_A /* cl9097.h */ 0x0000c397
192
193#define TURING_A /* cl9097.h */ 0x0000c597
194
195#define AMPERE_B /* cl9097.h */ 0x0000c797
196
197#define ADA_A /* cl9097.h */ 0x0000c997
198
199#define NV74_BSP 0x000074b0
200
201#define NVC4B0_VIDEO_DECODER 0x0000c4b0
202#define NVC6B0_VIDEO_DECODER 0x0000c6b0
203#define NVC7B0_VIDEO_DECODER 0x0000c7b0
204#define NVC9B0_VIDEO_DECODER 0x0000c9b0
205
206#define GT212_MSVLD 0x000085b1
207#define IGT21A_MSVLD 0x000086b1
208#define G98_MSVLD 0x000088b1
209#define GF100_MSVLD 0x000090b1
210#define GK104_MSVLD 0x000095b1
211
212#define GT212_MSPDEC 0x000085b2
213#define G98_MSPDEC 0x000088b2
214#define GF100_MSPDEC 0x000090b2
215#define GK104_MSPDEC 0x000095b2
216
217#define GT212_MSPPP 0x000085b3
218#define G98_MSPPP 0x000088b3
219#define GF100_MSPPP 0x000090b3
220
221#define G98_SEC 0x000088b4
222
223#define GT212_DMA 0x000085b5
224#define FERMI_DMA 0x000090b5
225#define KEPLER_DMA_COPY_A 0x0000a0b5
226#define MAXWELL_DMA_COPY_A 0x0000b0b5
227#define PASCAL_DMA_COPY_A 0x0000c0b5
228#define PASCAL_DMA_COPY_B 0x0000c1b5
229#define VOLTA_DMA_COPY_A 0x0000c3b5
230#define TURING_DMA_COPY_A 0x0000c5b5
231#define AMPERE_DMA_COPY_A 0x0000c6b5
232#define AMPERE_DMA_COPY_B 0x0000c7b5
233
234#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
235#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
236#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
237
238#define FERMI_DECOMPRESS 0x000090b8
239
240#define NV50_COMPUTE 0x000050c0
241#define GT214_COMPUTE 0x000085c0
242#define FERMI_COMPUTE_A 0x000090c0
243#define FERMI_COMPUTE_B 0x000091c0
244#define KEPLER_COMPUTE_A 0x0000a0c0
245#define KEPLER_COMPUTE_B 0x0000a1c0
246#define MAXWELL_COMPUTE_A 0x0000b0c0
247#define MAXWELL_COMPUTE_B 0x0000b1c0
248#define PASCAL_COMPUTE_A 0x0000c0c0
249#define PASCAL_COMPUTE_B 0x0000c1c0
250#define VOLTA_COMPUTE_A 0x0000c3c0
251#define TURING_COMPUTE_A 0x0000c5c0
252#define AMPERE_COMPUTE_B 0x0000c7c0
253#define ADA_COMPUTE_A 0x0000c9c0
254
255#define NV74_CIPHER 0x000074c1
256
257#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
258#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
259
260#define NVC6FA_VIDEO_OFA 0x0000c6fa
261#define NVC7FA_VIDEO_OFA 0x0000c7fa
262#define NVC9FA_VIDEO_OFA 0x0000c9fa
263#endif
264

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/drivers/gpu/drm/nouveau/include/nvif/class.h