1/*
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23
24/****************************************************************************/
25/*Portion I: Definitions shared between VBIOS and Driver */
26/****************************************************************************/
27
28
29#ifndef _ATOMBIOS_H
30#define _ATOMBIOS_H
31
32#define ATOM_VERSION_MAJOR 0x00020000
33#define ATOM_VERSION_MINOR 0x00000002
34
35#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
36
37/* Endianness should be specified before inclusion,
38 * default to little endian
39 */
40#ifndef ATOM_BIG_ENDIAN
41#error Endian not specified
42#endif
43
44#ifdef _H2INC
45 #ifndef ULONG
46 typedef unsigned long ULONG;
47 #endif
48
49 #ifndef UCHAR
50 typedef unsigned char UCHAR;
51 #endif
52
53 #ifndef USHORT
54 typedef unsigned short USHORT;
55 #endif
56#endif
57
58#define ATOM_DAC_A 0
59#define ATOM_DAC_B 1
60#define ATOM_EXT_DAC 2
61
62#define ATOM_CRTC1 0
63#define ATOM_CRTC2 1
64#define ATOM_CRTC3 2
65#define ATOM_CRTC4 3
66#define ATOM_CRTC5 4
67#define ATOM_CRTC6 5
68#define ATOM_CRTC_INVALID 0xFF
69
70#define ATOM_DIGA 0
71#define ATOM_DIGB 1
72
73#define ATOM_PPLL1 0
74#define ATOM_PPLL2 1
75#define ATOM_DCPLL 2
76#define ATOM_PPLL0 2
77#define ATOM_PPLL3 3
78
79#define ATOM_EXT_PLL1 8
80#define ATOM_EXT_PLL2 9
81#define ATOM_EXT_CLOCK 10
82#define ATOM_PPLL_INVALID 0xFF
83
84#define ENCODER_REFCLK_SRC_P1PLL 0
85#define ENCODER_REFCLK_SRC_P2PLL 1
86#define ENCODER_REFCLK_SRC_DCPLL 2
87#define ENCODER_REFCLK_SRC_EXTCLK 3
88#define ENCODER_REFCLK_SRC_INVALID 0xFF
89
90#define ATOM_SCALER1 0
91#define ATOM_SCALER2 1
92
93#define ATOM_SCALER_DISABLE 0
94#define ATOM_SCALER_CENTER 1
95#define ATOM_SCALER_EXPANSION 2
96#define ATOM_SCALER_MULTI_EX 3
97
98#define ATOM_DISABLE 0
99#define ATOM_ENABLE 1
100#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
101#define ATOM_LCD_BLON (ATOM_ENABLE+2)
102#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
103#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
104#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
105#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
106#define ATOM_INIT (ATOM_DISABLE+7)
107#define ATOM_GET_STATUS (ATOM_DISABLE+8)
108
109#define ATOM_BLANKING 1
110#define ATOM_BLANKING_OFF 0
111
112#define ATOM_CURSOR1 0
113#define ATOM_CURSOR2 1
114
115#define ATOM_ICON1 0
116#define ATOM_ICON2 1
117
118#define ATOM_CRT1 0
119#define ATOM_CRT2 1
120
121#define ATOM_TV_NTSC 1
122#define ATOM_TV_NTSCJ 2
123#define ATOM_TV_PAL 3
124#define ATOM_TV_PALM 4
125#define ATOM_TV_PALCN 5
126#define ATOM_TV_PALN 6
127#define ATOM_TV_PAL60 7
128#define ATOM_TV_SECAM 8
129#define ATOM_TV_CV 16
130
131#define ATOM_DAC1_PS2 1
132#define ATOM_DAC1_CV 2
133#define ATOM_DAC1_NTSC 3
134#define ATOM_DAC1_PAL 4
135
136#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
137#define ATOM_DAC2_CV ATOM_DAC1_CV
138#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
139#define ATOM_DAC2_PAL ATOM_DAC1_PAL
140
141#define ATOM_PM_ON 0
142#define ATOM_PM_STANDBY 1
143#define ATOM_PM_SUSPEND 2
144#define ATOM_PM_OFF 3
145
146/* Bit0:{=0:single, =1:dual},
147 Bit1 {=0:666RGB, =1:888RGB},
148 Bit2:3:{Grey level}
149 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
150
151#define ATOM_PANEL_MISC_DUAL 0x00000001
152#define ATOM_PANEL_MISC_888RGB 0x00000002
153#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
154#define ATOM_PANEL_MISC_FPDI 0x00000010
155#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
156#define ATOM_PANEL_MISC_SPATIAL 0x00000020
157#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
158#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
159
160
161#define MEMTYPE_DDR1 "DDR1"
162#define MEMTYPE_DDR2 "DDR2"
163#define MEMTYPE_DDR3 "DDR3"
164#define MEMTYPE_DDR4 "DDR4"
165
166#define ASIC_BUS_TYPE_PCI "PCI"
167#define ASIC_BUS_TYPE_AGP "AGP"
168#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
169
170/* Maximum size of that FireGL flag string */
171
172#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
173#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
174
175#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
176#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
177
178#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
179#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
180
181#define HW_ASSISTED_I2C_STATUS_FAILURE 2
182#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
183
184#pragma pack(1) /* BIOS data must use byte alignment */
185
186/* Define offset to location of ROM header. */
187
188#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
189#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
190
191#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
192#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */
193#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
194#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
195
196/* Common header for all ROM Data tables.
197 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
198 And the pointer actually points to this header. */
199
200typedef struct _ATOM_COMMON_TABLE_HEADER
201{
202 USHORT usStructureSize;
203 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
204 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
205 /*Image can't be updated, while Driver needs to carry the new table! */
206}ATOM_COMMON_TABLE_HEADER;
207
208/****************************************************************************/
209// Structure stores the ROM header.
210/****************************************************************************/
211typedef struct _ATOM_ROM_HEADER
212{
213 ATOM_COMMON_TABLE_HEADER sHeader;
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
215 atombios should init it as "ATOM", don't change the position */
216 USHORT usBiosRuntimeSegmentAddress;
217 USHORT usProtectedModeInfoOffset;
218 USHORT usConfigFilenameOffset;
219 USHORT usCRC_BlockOffset;
220 USHORT usBIOS_BootupMessageOffset;
221 USHORT usInt10Offset;
222 USHORT usPciBusDevInitCode;
223 USHORT usIoBaseAddress;
224 USHORT usSubsystemVendorID;
225 USHORT usSubsystemID;
226 USHORT usPCI_InfoOffset;
227 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
228 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
229 UCHAR ucExtendedFunctionCode;
230 UCHAR ucReserved;
231}ATOM_ROM_HEADER;
232
233/*==============================Command Table Portion==================================== */
234
235#ifdef UEFI_BUILD
236 #define UTEMP USHORT
237 #define USHORT void*
238#endif
239
240/****************************************************************************/
241// Structures used in Command.mtb
242/****************************************************************************/
243typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
244 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
245 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
246 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
247 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
248 USHORT DIGxEncoderControl; //Only used by Bios
249 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
250 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
251 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
252 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
253 USHORT GPIOPinControl; //Atomic Table, only used by Bios
254 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
255 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
256 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
257 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
258 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
259 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
260 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
261 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
262 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
263 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
264 USHORT SetUniphyInstance; //Atomic Table, only used by Bios
265 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
266 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
267 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
268 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
269 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
270 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
271 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
272 USHORT GetConditionalGoldenSetting; //Only used by Bios
273 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1
274 USHORT PatchMCSetting; //only used by BIOS
275 USHORT MC_SEQ_Control; //only used by BIOS
276 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
277 USHORT EnableScaler; //Atomic Table, used only by Bios
278 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
279 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
280 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
281 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
282 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
283 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
284 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
285 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios
286 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
287 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
288 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
289 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
290 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios
291 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
292 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
293 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
294 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
295 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
296 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
297 USHORT MemoryCleanUp; //Atomic Table, only used by Bios
298 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
299 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
300 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
301 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
302 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
303 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
304 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
305 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
306 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
307 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
308 USHORT MemoryTraining; //Atomic Table, used only by Bios
309 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
310 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
311 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
312 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
313 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
314 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
315 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
316 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
317 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
318 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
319 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
320 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
321 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
322 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
323 USHORT DPEncoderService; //Function Table,only used by Bios
324 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
325}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
326
327// For backward compatible
328#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
329#define DPTranslatorControl DIG2EncoderControl
330#define UNIPHYTransmitterControl DIG1TransmitterControl
331#define LVTMATransmitterControl DIG2TransmitterControl
332#define SetCRTC_DPM_State GetConditionalGoldenSetting
333#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance
334#define HPDInterruptService ReadHWAssistedI2CStatus
335#define EnableVGA_Access GetSCLKOverMCLKRatio
336#define EnableYUV GetDispObjectInfo
337#define DynamicClockGating EnableDispPowerGating
338#define SetupHWAssistedI2CStatus ComputeMemoryClockParam
339
340#define TMDSAEncoderControl PatchMCSetting
341#define LVDSEncoderControl MC_SEQ_Control
342#define LCD1OutputControl HW_Misc_Operation
343#define TV1OutputControl Gfx_Harvesting
344
345typedef struct _ATOM_MASTER_COMMAND_TABLE
346{
347 ATOM_COMMON_TABLE_HEADER sHeader;
348 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
349}ATOM_MASTER_COMMAND_TABLE;
350
351/****************************************************************************/
352// Structures used in every command table
353/****************************************************************************/
354typedef struct _ATOM_TABLE_ATTRIBUTE
355{
356#if ATOM_BIG_ENDIAN
357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
358 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
360#else
361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
362 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
363 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
364#endif
365}ATOM_TABLE_ATTRIBUTE;
366
367typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
368{
369 ATOM_TABLE_ATTRIBUTE sbfAccess;
370 USHORT susAccess;
371}ATOM_TABLE_ATTRIBUTE_ACCESS;
372
373/****************************************************************************/
374// Common header for all command tables.
375// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
376// And the pointer actually points to this header.
377/****************************************************************************/
378typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
379{
380 ATOM_COMMON_TABLE_HEADER CommonHeader;
381 ATOM_TABLE_ATTRIBUTE TableAttribute;
382}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
383
384/****************************************************************************/
385// Structures used by ComputeMemoryEnginePLLTable
386/****************************************************************************/
387#define COMPUTE_MEMORY_PLL_PARAM 1
388#define COMPUTE_ENGINE_PLL_PARAM 2
389#define ADJUST_MC_SETTING_PARAM 3
390
391/****************************************************************************/
392// Structures used by AdjustMemoryControllerTable
393/****************************************************************************/
394typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
395{
396#if ATOM_BIG_ENDIAN
397 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
399 ULONG ulClockFreq:24;
400#else
401 ULONG ulClockFreq:24;
402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
403 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
404#endif
405}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
406#define POINTER_RETURN_FLAG 0x80
407
408typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
409{
410 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
412 UCHAR ucReserved; //may expand to return larger Fbdiv later
413 UCHAR ucFbDiv; //return value
414 UCHAR ucPostDiv; //return value
415}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
416
417typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
418{
419 ULONG ulClock; //When return, [23:0] return real clock
420 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
421 USHORT usFbDiv; //return Feedback value to be written to register
422 UCHAR ucPostDiv; //return post div to be written to register
423}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
424#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
425
426
427#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
428#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
429#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
430#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
431#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
432#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
433#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
434
435#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
436#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
437#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
438#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
439#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
440
441typedef struct _ATOM_COMPUTE_CLOCK_FREQ
442{
443#if ATOM_BIG_ENDIAN
444 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
445 ULONG ulClockFreq:24; // in unit of 10kHz
446#else
447 ULONG ulClockFreq:24; // in unit of 10kHz
448 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
449#endif
450}ATOM_COMPUTE_CLOCK_FREQ;
451
452typedef struct _ATOM_S_MPLL_FB_DIVIDER
453{
454 USHORT usFbDivFrac;
455 USHORT usFbDiv;
456}ATOM_S_MPLL_FB_DIVIDER;
457
458typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
459{
460 union
461 {
462 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
463 ULONG ulClockParams; //ULONG access for BE
464 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
465 };
466 UCHAR ucRefDiv; //Output Parameter
467 UCHAR ucPostDiv; //Output Parameter
468 UCHAR ucCntlFlag; //Output Parameter
469 UCHAR ucReserved;
470}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
471
472// ucCntlFlag
473#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
474#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
475#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
476#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
477
478
479// V4 are only used for APU which PLL outside GPU
480typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
481{
482#if ATOM_BIG_ENDIAN
483 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
484 ULONG ulClock:24; //Input= target clock, output = actual clock
485#else
486 ULONG ulClock:24; //Input= target clock, output = actual clock
487 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
488#endif
489}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
490
491typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
492{
493 union
494 {
495 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
496 ULONG ulClockParams; //ULONG access for BE
497 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
498 };
499 UCHAR ucRefDiv; //Output Parameter
500 UCHAR ucPostDiv; //Output Parameter
501 union
502 {
503 UCHAR ucCntlFlag; //Output Flags
504 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
505 };
506 UCHAR ucReserved;
507}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
508
509
510typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
511{
512 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
513 ULONG ulReserved[2];
514}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
515
516//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
517#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
518#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
519#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
520
521typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
522{
523 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
524 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
525 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
526 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
527 UCHAR ucPllCntlFlag; //Output Flags: control flag
528 UCHAR ucReserved;
529}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
530
531//ucPllCntlFlag
532#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
533
534
535// ucInputFlag
536#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
537
538// use for ComputeMemoryClockParamTable
539typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
540{
541 union
542 {
543 ULONG ulClock;
544 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
545 };
546 UCHAR ucDllSpeed; //Output
547 UCHAR ucPostDiv; //Output
548 union{
549 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
550 UCHAR ucPllCntlFlag; //Output:
551 };
552 UCHAR ucBWCntl;
553}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
554
555// definition of ucInputFlag
556#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
557// definition of ucPllCntlFlag
558#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
559#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
560#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
561#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
562
563//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
564#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
565
566typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
567{
568 ATOM_COMPUTE_CLOCK_FREQ ulClock;
569 ULONG ulReserved[2];
570}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
571
572typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
573{
574 ATOM_COMPUTE_CLOCK_FREQ ulClock;
575 ULONG ulMemoryClock;
576 ULONG ulReserved;
577}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
578
579/****************************************************************************/
580// Structures used by SetEngineClockTable
581/****************************************************************************/
582typedef struct _SET_ENGINE_CLOCK_PARAMETERS
583{
584 ULONG ulTargetEngineClock; //In 10Khz unit
585}SET_ENGINE_CLOCK_PARAMETERS;
586
587typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
588{
589 ULONG ulTargetEngineClock; //In 10Khz unit
590 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
591}SET_ENGINE_CLOCK_PS_ALLOCATION;
592
593/****************************************************************************/
594// Structures used by SetMemoryClockTable
595/****************************************************************************/
596typedef struct _SET_MEMORY_CLOCK_PARAMETERS
597{
598 ULONG ulTargetMemoryClock; //In 10Khz unit
599}SET_MEMORY_CLOCK_PARAMETERS;
600
601typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
602{
603 ULONG ulTargetMemoryClock; //In 10Khz unit
604 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
605}SET_MEMORY_CLOCK_PS_ALLOCATION;
606
607/****************************************************************************/
608// Structures used by ASIC_Init.ctb
609/****************************************************************************/
610typedef struct _ASIC_INIT_PARAMETERS
611{
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
614}ASIC_INIT_PARAMETERS;
615
616typedef struct _ASIC_INIT_PS_ALLOCATION
617{
618 ASIC_INIT_PARAMETERS sASICInitClocks;
619 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
620}ASIC_INIT_PS_ALLOCATION;
621
622/****************************************************************************/
623// Structure used by DynamicClockGatingTable.ctb
624/****************************************************************************/
625typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
626{
627 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
628 UCHAR ucPadding[3];
629}DYNAMIC_CLOCK_GATING_PARAMETERS;
630#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
631
632/****************************************************************************/
633// Structure used by EnableDispPowerGatingTable.ctb
634/****************************************************************************/
635typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
636{
637 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
638 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
639 UCHAR ucPadding[2];
640}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
641
642/****************************************************************************/
643// Structure used by EnableASIC_StaticPwrMgtTable.ctb
644/****************************************************************************/
645typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
646{
647 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
648 UCHAR ucPadding[3];
649}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
650#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
651
652/****************************************************************************/
653// Structures used by DAC_LoadDetectionTable.ctb
654/****************************************************************************/
655typedef struct _DAC_LOAD_DETECTION_PARAMETERS
656{
657 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
658 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
659 UCHAR ucMisc; //Valid only when table revision =1.3 and above
660}DAC_LOAD_DETECTION_PARAMETERS;
661
662// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
663#define DAC_LOAD_MISC_YPrPb 0x01
664
665typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
666{
667 DAC_LOAD_DETECTION_PARAMETERS sDacload;
668 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
669}DAC_LOAD_DETECTION_PS_ALLOCATION;
670
671/****************************************************************************/
672// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
673/****************************************************************************/
674typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
675{
676 USHORT usPixelClock; // in 10KHz; for bios convenient
677 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
678 UCHAR ucAction; // 0: turn off encoder
679 // 1: setup and turn on encoder
680 // 7: ATOM_ENCODER_INIT Initialize DAC
681}DAC_ENCODER_CONTROL_PARAMETERS;
682
683#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
684
685/****************************************************************************/
686// Structures used by DIG1EncoderControlTable
687// DIG2EncoderControlTable
688// ExternalEncoderControlTable
689/****************************************************************************/
690typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
691{
692 USHORT usPixelClock; // in 10KHz; for bios convenient
693 UCHAR ucConfig;
694 // [2] Link Select:
695 // =0: PHY linkA if bfLane<3
696 // =1: PHY linkB if bfLanes<3
697 // =0: PHY linkA+B if bfLanes=3
698 // [3] Transmitter Sel
699 // =0: UNIPHY or PCIEPHY
700 // =1: LVTMA
701 UCHAR ucAction; // =0: turn off encoder
702 // =1: turn on encoder
703 UCHAR ucEncoderMode;
704 // =0: DP encoder
705 // =1: LVDS encoder
706 // =2: DVI encoder
707 // =3: HDMI encoder
708 // =4: SDVO encoder
709 UCHAR ucLaneNum; // how many lanes to enable
710 UCHAR ucReserved[2];
711}DIG_ENCODER_CONTROL_PARAMETERS;
712#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
713#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
714
715//ucConfig
716#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
717#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
718#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
719#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
720#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
721#define ATOM_ENCODER_CONFIG_LINKA 0x00
722#define ATOM_ENCODER_CONFIG_LINKB 0x04
723#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
724#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
725#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
726#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
727#define ATOM_ENCODER_CONFIG_LVTMA 0x08
728#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
729#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
730#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
731// ucAction
732// ATOM_ENABLE: Enable Encoder
733// ATOM_DISABLE: Disable Encoder
734
735//ucEncoderMode
736#define ATOM_ENCODER_MODE_DP 0
737#define ATOM_ENCODER_MODE_LVDS 1
738#define ATOM_ENCODER_MODE_DVI 2
739#define ATOM_ENCODER_MODE_HDMI 3
740#define ATOM_ENCODER_MODE_SDVO 4
741#define ATOM_ENCODER_MODE_DP_AUDIO 5
742#define ATOM_ENCODER_MODE_TV 13
743#define ATOM_ENCODER_MODE_CV 14
744#define ATOM_ENCODER_MODE_CRT 15
745#define ATOM_ENCODER_MODE_DVO 16
746#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
747#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
748
749typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
750{
751#if ATOM_BIG_ENDIAN
752 UCHAR ucReserved1:2;
753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
754 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
755 UCHAR ucReserved:1;
756 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
757#else
758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
759 UCHAR ucReserved:1;
760 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
762 UCHAR ucReserved1:2;
763#endif
764}ATOM_DIG_ENCODER_CONFIG_V2;
765
766
767typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
768{
769 USHORT usPixelClock; // in 10KHz; for bios convenient
770 ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
771 UCHAR ucAction;
772 UCHAR ucEncoderMode;
773 // =0: DP encoder
774 // =1: LVDS encoder
775 // =2: DVI encoder
776 // =3: HDMI encoder
777 // =4: SDVO encoder
778 UCHAR ucLaneNum; // how many lanes to enable
779 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
780 UCHAR ucReserved;
781}DIG_ENCODER_CONTROL_PARAMETERS_V2;
782
783//ucConfig
784#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
785#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
786#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
787#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
788#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
789#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
790#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
791#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
792#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
793#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
794
795// ucAction:
796// ATOM_DISABLE
797// ATOM_ENABLE
798#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
799#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
800#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
801#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
802#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
803#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
804#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
805#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
806#define ATOM_ENCODER_CMD_SETUP 0x0f
807#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
808
809// ucStatus
810#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
811#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
812
813//ucTableFormatRevision=1
814//ucTableContentRevision=3
815// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
816typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
817{
818#if ATOM_BIG_ENDIAN
819 UCHAR ucReserved1:1;
820 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
821 UCHAR ucReserved:3;
822 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
823#else
824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
825 UCHAR ucReserved:3;
826 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
827 UCHAR ucReserved1:1;
828#endif
829}ATOM_DIG_ENCODER_CONFIG_V3;
830
831#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
832#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
833#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
834#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
835#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
836#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
837#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
838#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
839#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
840#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
841
842typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
843{
844 USHORT usPixelClock; // in 10KHz; for bios convenient
845 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
846 UCHAR ucAction;
847 union {
848 UCHAR ucEncoderMode;
849 // =0: DP encoder
850 // =1: LVDS encoder
851 // =2: DVI encoder
852 // =3: HDMI encoder
853 // =4: SDVO encoder
854 // =5: DP audio
855 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
856 // =0: external DP
857 // =1: internal DP2
858 // =0x11: internal DP1 for NutMeg/Travis DP translator
859 };
860 UCHAR ucLaneNum; // how many lanes to enable
861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
862 UCHAR ucReserved;
863}DIG_ENCODER_CONTROL_PARAMETERS_V3;
864
865//ucTableFormatRevision=1
866//ucTableContentRevision=4
867// start from NI
868// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
869typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
870{
871#if ATOM_BIG_ENDIAN
872 UCHAR ucReserved1:1;
873 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
874 UCHAR ucReserved:2;
875 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
876#else
877 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
878 UCHAR ucReserved:2;
879 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
880 UCHAR ucReserved1:1;
881#endif
882}ATOM_DIG_ENCODER_CONFIG_V4;
883
884#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
885#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
886#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
887#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
888#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
889#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
890#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
891#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
892#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
893#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
894#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
895#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
896#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
897
898typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
899{
900 USHORT usPixelClock; // in 10KHz; for bios convenient
901 union{
902 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
903 UCHAR ucConfig;
904 };
905 UCHAR ucAction;
906 union {
907 UCHAR ucEncoderMode;
908 // =0: DP encoder
909 // =1: LVDS encoder
910 // =2: DVI encoder
911 // =3: HDMI encoder
912 // =4: SDVO encoder
913 // =5: DP audio
914 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
915 // =0: external DP
916 // =1: internal DP2
917 // =0x11: internal DP1 for NutMeg/Travis DP translator
918 };
919 UCHAR ucLaneNum; // how many lanes to enable
920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
921 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
922}DIG_ENCODER_CONTROL_PARAMETERS_V4;
923
924// define ucBitPerColor:
925#define PANEL_BPC_UNDEFINE 0x00
926#define PANEL_6BIT_PER_COLOR 0x01
927#define PANEL_8BIT_PER_COLOR 0x02
928#define PANEL_10BIT_PER_COLOR 0x03
929#define PANEL_12BIT_PER_COLOR 0x04
930#define PANEL_16BIT_PER_COLOR 0x05
931
932//define ucPanelMode
933#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
934#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
935#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
936
937/****************************************************************************/
938// Structures used by UNIPHYTransmitterControlTable
939// LVTMATransmitterControlTable
940// DVOOutputControlTable
941/****************************************************************************/
942typedef struct _ATOM_DP_VS_MODE
943{
944 UCHAR ucLaneSel;
945 UCHAR ucLaneSet;
946}ATOM_DP_VS_MODE;
947
948typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
949{
950 union
951 {
952 USHORT usPixelClock; // in 10KHz; for bios convenient
953 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
954 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
955 };
956 UCHAR ucConfig;
957 // [0]=0: 4 lane Link,
958 // =1: 8 lane Link ( Dual Links TMDS )
959 // [1]=0: InCoherent mode
960 // =1: Coherent Mode
961 // [2] Link Select:
962 // =0: PHY linkA if bfLane<3
963 // =1: PHY linkB if bfLanes<3
964 // =0: PHY linkA+B if bfLanes=3
965 // [5:4]PCIE lane Sel
966 // =0: lane 0~3 or 0~7
967 // =1: lane 4~7
968 // =2: lane 8~11 or 8~15
969 // =3: lane 12~15
970 UCHAR ucAction; // =0: turn off encoder
971 // =1: turn on encoder
972 UCHAR ucReserved[4];
973}DIG_TRANSMITTER_CONTROL_PARAMETERS;
974
975#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
976
977//ucInitInfo
978#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
979
980//ucConfig
981#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
982#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
983#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
984#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
985#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
986#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
987#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
988
989#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
990#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
991#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
992
993#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
994#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
995#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
996#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
997#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
998#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
999#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
1000#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
1001#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
1002#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
1003#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
1004
1005//ucAction
1006#define ATOM_TRANSMITTER_ACTION_DISABLE 0
1007#define ATOM_TRANSMITTER_ACTION_ENABLE 1
1008#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
1009#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
1010#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
1011#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
1012#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
1013#define ATOM_TRANSMITTER_ACTION_INIT 7
1014#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
1015#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
1016#define ATOM_TRANSMITTER_ACTION_SETUP 10
1017#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
1018#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
1019#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
1020
1021// Following are used for DigTransmitterControlTable ver1.2
1022typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
1023{
1024#if ATOM_BIG_ENDIAN
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1026 // =1 Dig Transmitter 2 ( Uniphy CD )
1027 // =2 Dig Transmitter 3 ( Uniphy EF )
1028 UCHAR ucReserved:1;
1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1030 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1031 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1032 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1033
1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1036#else
1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1039 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1040 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1041 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1043 UCHAR ucReserved:1;
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1045 // =1 Dig Transmitter 2 ( Uniphy CD )
1046 // =2 Dig Transmitter 3 ( Uniphy EF )
1047#endif
1048}ATOM_DIG_TRANSMITTER_CONFIG_V2;
1049
1050//ucConfig
1051//Bit0
1052#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1053
1054//Bit1
1055#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1056
1057//Bit2
1058#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1059#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1060#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1061
1062// Bit3
1063#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1064#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1065#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1066
1067// Bit4
1068#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1069
1070// Bit7:6
1071#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1072#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1073#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1074#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1075
1076typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1077{
1078 union
1079 {
1080 USHORT usPixelClock; // in 10KHz; for bios convenient
1081 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1082 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1083 };
1084 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1085 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1086 UCHAR ucReserved[4];
1087}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1088
1089typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1090{
1091#if ATOM_BIG_ENDIAN
1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1093 // =1 Dig Transmitter 2 ( Uniphy CD )
1094 // =2 Dig Transmitter 3 ( Uniphy EF )
1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1096 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1097 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1098 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1101#else
1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1104 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1105 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1106 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1109 // =1 Dig Transmitter 2 ( Uniphy CD )
1110 // =2 Dig Transmitter 3 ( Uniphy EF )
1111#endif
1112}ATOM_DIG_TRANSMITTER_CONFIG_V3;
1113
1114
1115typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1116{
1117 union
1118 {
1119 USHORT usPixelClock; // in 10KHz; for bios convenient
1120 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1121 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1122 };
1123 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1124 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1125 UCHAR ucLaneNum;
1126 UCHAR ucReserved[3];
1127}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1128
1129//ucConfig
1130//Bit0
1131#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1132
1133//Bit1
1134#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1135
1136//Bit2
1137#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1138#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1139#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1140
1141// Bit3
1142#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1143#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1144#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1145
1146// Bit5:4
1147#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1148#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1149#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1150#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1151
1152// Bit7:6
1153#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1154#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1155#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1156#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1157
1158
1159/****************************************************************************/
1160// Structures used by UNIPHYTransmitterControlTable V1.4
1161// ASIC Families: NI
1162// ucTableFormatRevision=1
1163// ucTableContentRevision=4
1164/****************************************************************************/
1165typedef struct _ATOM_DP_VS_MODE_V4
1166{
1167 UCHAR ucLaneSel;
1168 union
1169 {
1170 UCHAR ucLaneSet;
1171 struct {
1172#if ATOM_BIG_ENDIAN
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1176#else
1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1180#endif
1181 };
1182 };
1183}ATOM_DP_VS_MODE_V4;
1184
1185typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1186{
1187#if ATOM_BIG_ENDIAN
1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1189 // =1 Dig Transmitter 2 ( Uniphy CD )
1190 // =2 Dig Transmitter 3 ( Uniphy EF )
1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1192 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1193 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1194 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1197#else
1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1200 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1201 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1202 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1205 // =1 Dig Transmitter 2 ( Uniphy CD )
1206 // =2 Dig Transmitter 3 ( Uniphy EF )
1207#endif
1208}ATOM_DIG_TRANSMITTER_CONFIG_V4;
1209
1210typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1211{
1212 union
1213 {
1214 USHORT usPixelClock; // in 10KHz; for bios convenient
1215 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1216 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1217 };
1218 union
1219 {
1220 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1221 UCHAR ucConfig;
1222 };
1223 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1224 UCHAR ucLaneNum;
1225 UCHAR ucReserved[3];
1226}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1227
1228//ucConfig
1229//Bit0
1230#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1231//Bit1
1232#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1233//Bit2
1234#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1235#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1236#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1237// Bit3
1238#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1239#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1240#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1241// Bit5:4
1242#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1243#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1244#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1245#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1246#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1247// Bit7:6
1248#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1249#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1250#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1251#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1252
1253
1254typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1255{
1256#if ATOM_BIG_ENDIAN
1257 UCHAR ucReservd1:1;
1258 UCHAR ucHPDSel:3;
1259 UCHAR ucPhyClkSrcId:2;
1260 UCHAR ucCoherentMode:1;
1261 UCHAR ucReserved:1;
1262#else
1263 UCHAR ucReserved:1;
1264 UCHAR ucCoherentMode:1;
1265 UCHAR ucPhyClkSrcId:2;
1266 UCHAR ucHPDSel:3;
1267 UCHAR ucReservd1:1;
1268#endif
1269}ATOM_DIG_TRANSMITTER_CONFIG_V5;
1270
1271typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1272{
1273 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1274 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1275 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1277 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1278 UCHAR ucDigMode; // indicate DIG mode
1279 union{
1280 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1281 UCHAR ucConfig;
1282 };
1283 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1284 UCHAR ucDPLaneSet;
1285 UCHAR ucReserved;
1286 UCHAR ucReserved1;
1287}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1288
1289//ucPhyId
1290#define ATOM_PHY_ID_UNIPHYA 0
1291#define ATOM_PHY_ID_UNIPHYB 1
1292#define ATOM_PHY_ID_UNIPHYC 2
1293#define ATOM_PHY_ID_UNIPHYD 3
1294#define ATOM_PHY_ID_UNIPHYE 4
1295#define ATOM_PHY_ID_UNIPHYF 5
1296#define ATOM_PHY_ID_UNIPHYG 6
1297
1298// ucDigEncoderSel
1299#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1300#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1301#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1302#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1303#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1304#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1305#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1306
1307// ucDigMode
1308#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1309#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1310#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1311#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1312#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1313#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1314
1315// ucDPLaneSet
1316#define DP_LANE_SET__0DB_0_4V 0x00
1317#define DP_LANE_SET__0DB_0_6V 0x01
1318#define DP_LANE_SET__0DB_0_8V 0x02
1319#define DP_LANE_SET__0DB_1_2V 0x03
1320#define DP_LANE_SET__3_5DB_0_4V 0x08
1321#define DP_LANE_SET__3_5DB_0_6V 0x09
1322#define DP_LANE_SET__3_5DB_0_8V 0x0a
1323#define DP_LANE_SET__6DB_0_4V 0x10
1324#define DP_LANE_SET__6DB_0_6V 0x11
1325#define DP_LANE_SET__9_5DB_0_4V 0x18
1326
1327// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1328// Bit1
1329#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1330
1331// Bit3:2
1332#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1333#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1334
1335#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1336#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1337#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1338#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1339// Bit6:4
1340#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1341#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1342
1343#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1344#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1345#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1346#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1347#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1348#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1349#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1350
1351#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1352
1353
1354/****************************************************************************/
1355// Structures used by ExternalEncoderControlTable V1.3
1356// ASIC Families: Evergreen, Llano, NI
1357// ucTableFormatRevision=1
1358// ucTableContentRevision=3
1359/****************************************************************************/
1360
1361typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1362{
1363 union{
1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1365 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1366 };
1367 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1368 UCHAR ucAction; //
1369 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1370 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1371 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1372 UCHAR ucReserved;
1373}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1374
1375// ucAction
1376#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1377#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1378#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1379#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1380#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1381#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1382#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1383#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1384
1385// ucConfig
1386#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1387#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1388#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1389#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1390#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70
1391#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1392#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1393#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1394
1395typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1396{
1397 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1398 ULONG ulReserved[2];
1399}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1400
1401
1402/****************************************************************************/
1403// Structures used by DAC1OuputControlTable
1404// DAC2OuputControlTable
1405// LVTMAOutputControlTable (Before DEC30)
1406// TMDSAOutputControlTable (Before DEC30)
1407/****************************************************************************/
1408typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1409{
1410 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1411 // When the display is LCD, in addition to above:
1412 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1413 // ATOM_LCD_SELFTEST_STOP
1414
1415 UCHAR aucPadding[3]; // padding to DWORD aligned
1416}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1417
1418#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1419
1420
1421#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1422#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1423
1424#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1425#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1426
1427#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1428#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1429
1430#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1431#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1432
1433#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1434#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1435
1436#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1437#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1438
1439#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1440#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1441
1442#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1443#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1444#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1445
1446/****************************************************************************/
1447// Structures used by BlankCRTCTable
1448/****************************************************************************/
1449typedef struct _BLANK_CRTC_PARAMETERS
1450{
1451 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1452 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1453 USHORT usBlackColorRCr;
1454 USHORT usBlackColorGY;
1455 USHORT usBlackColorBCb;
1456}BLANK_CRTC_PARAMETERS;
1457#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1458
1459/****************************************************************************/
1460// Structures used by EnableCRTCTable
1461// EnableCRTCMemReqTable
1462// UpdateCRTC_DoubleBufferRegistersTable
1463/****************************************************************************/
1464typedef struct _ENABLE_CRTC_PARAMETERS
1465{
1466 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1467 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1468 UCHAR ucPadding[2];
1469}ENABLE_CRTC_PARAMETERS;
1470#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1471
1472/****************************************************************************/
1473// Structures used by SetCRTC_OverScanTable
1474/****************************************************************************/
1475typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1476{
1477 USHORT usOverscanRight; // right
1478 USHORT usOverscanLeft; // left
1479 USHORT usOverscanBottom; // bottom
1480 USHORT usOverscanTop; // top
1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1482 UCHAR ucPadding[3];
1483}SET_CRTC_OVERSCAN_PARAMETERS;
1484#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1485
1486/****************************************************************************/
1487// Structures used by SetCRTC_ReplicationTable
1488/****************************************************************************/
1489typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1490{
1491 UCHAR ucH_Replication; // horizontal replication
1492 UCHAR ucV_Replication; // vertical replication
1493 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1494 UCHAR ucPadding;
1495}SET_CRTC_REPLICATION_PARAMETERS;
1496#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1497
1498/****************************************************************************/
1499// Structures used by SelectCRTC_SourceTable
1500/****************************************************************************/
1501typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1502{
1503 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1504 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1505 UCHAR ucPadding[2];
1506}SELECT_CRTC_SOURCE_PARAMETERS;
1507#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1508
1509typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1510{
1511 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1512 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1513 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1514 UCHAR ucPadding;
1515}SELECT_CRTC_SOURCE_PARAMETERS_V2;
1516
1517//ucEncoderID
1518//#define ASIC_INT_DAC1_ENCODER_ID 0x00
1519//#define ASIC_INT_TV_ENCODER_ID 0x02
1520//#define ASIC_INT_DIG1_ENCODER_ID 0x03
1521//#define ASIC_INT_DAC2_ENCODER_ID 0x04
1522//#define ASIC_EXT_TV_ENCODER_ID 0x06
1523//#define ASIC_INT_DVO_ENCODER_ID 0x07
1524//#define ASIC_INT_DIG2_ENCODER_ID 0x09
1525//#define ASIC_EXT_DIG_ENCODER_ID 0x05
1526
1527//ucEncodeMode
1528//#define ATOM_ENCODER_MODE_DP 0
1529//#define ATOM_ENCODER_MODE_LVDS 1
1530//#define ATOM_ENCODER_MODE_DVI 2
1531//#define ATOM_ENCODER_MODE_HDMI 3
1532//#define ATOM_ENCODER_MODE_SDVO 4
1533//#define ATOM_ENCODER_MODE_TV 13
1534//#define ATOM_ENCODER_MODE_CV 14
1535//#define ATOM_ENCODER_MODE_CRT 15
1536
1537/****************************************************************************/
1538// Structures used by SetPixelClockTable
1539// GetPixelClockTable
1540/****************************************************************************/
1541//Major revision=1., Minor revision=1
1542typedef struct _PIXEL_CLOCK_PARAMETERS
1543{
1544 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1545 // 0 means disable PPLL
1546 USHORT usRefDiv; // Reference divider
1547 USHORT usFbDiv; // feedback divider
1548 UCHAR ucPostDiv; // post divider
1549 UCHAR ucFracFbDiv; // fractional feedback divider
1550 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1551 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1552 UCHAR ucCRTC; // Which CRTC uses this Ppll
1553 UCHAR ucPadding;
1554}PIXEL_CLOCK_PARAMETERS;
1555
1556//Major revision=1., Minor revision=2, add ucMiscIfno
1557//ucMiscInfo:
1558#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1559#define MISC_DEVICE_INDEX_MASK 0xF0
1560#define MISC_DEVICE_INDEX_SHIFT 4
1561
1562typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1563{
1564 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1565 // 0 means disable PPLL
1566 USHORT usRefDiv; // Reference divider
1567 USHORT usFbDiv; // feedback divider
1568 UCHAR ucPostDiv; // post divider
1569 UCHAR ucFracFbDiv; // fractional feedback divider
1570 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1571 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1572 UCHAR ucCRTC; // Which CRTC uses this Ppll
1573 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1574}PIXEL_CLOCK_PARAMETERS_V2;
1575
1576//Major revision=1., Minor revision=3, structure/definition change
1577//ucEncoderMode:
1578//ATOM_ENCODER_MODE_DP
1579//ATOM_ENOCDER_MODE_LVDS
1580//ATOM_ENOCDER_MODE_DVI
1581//ATOM_ENOCDER_MODE_HDMI
1582//ATOM_ENOCDER_MODE_SDVO
1583//ATOM_ENCODER_MODE_TV 13
1584//ATOM_ENCODER_MODE_CV 14
1585//ATOM_ENCODER_MODE_CRT 15
1586
1587//ucDVOConfig
1588//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1589//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1590//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1591//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1592//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1593//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1594//#define DVO_ENCODER_CONFIG_24BIT 0x08
1595
1596//ucMiscInfo: also changed, see below
1597#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1598#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1599#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1600#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1601#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1602#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1603#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1604// V1.4 for RoadRunner
1605#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1606#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1607
1608
1609typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1610{
1611 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1612 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1613 USHORT usRefDiv; // Reference divider
1614 USHORT usFbDiv; // feedback divider
1615 UCHAR ucPostDiv; // post divider
1616 UCHAR ucFracFbDiv; // fractional feedback divider
1617 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1618 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1619 union
1620 {
1621 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1622 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1623 };
1624 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1625 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1626 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1627}PIXEL_CLOCK_PARAMETERS_V3;
1628
1629#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1630#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1631
1632typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1633{
1634 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1635 // drive the pixel clock. not used for DCPLL case.
1636 union{
1637 UCHAR ucReserved;
1638 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1639 };
1640 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1641 // 0 means disable PPLL/DCPLL.
1642 USHORT usFbDiv; // feedback divider integer part.
1643 UCHAR ucPostDiv; // post divider.
1644 UCHAR ucRefDiv; // Reference divider
1645 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1646 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1647 // indicate which graphic encoder will be used.
1648 UCHAR ucEncoderMode; // Encoder mode:
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1650 // bit[1]= when VGA timing is used.
1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1652 // bit[4]= RefClock source for PPLL.
1653 // =0: XTLAIN( default mode )
1654 // =1: other external clock source, which is pre-defined
1655 // by VBIOS depend on the feature required.
1656 // bit[7:5]: reserved.
1657 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1658
1659}PIXEL_CLOCK_PARAMETERS_V5;
1660
1661#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1662#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1663#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1664#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1665#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1666#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1667#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1668
1669typedef struct _CRTC_PIXEL_CLOCK_FREQ
1670{
1671#if ATOM_BIG_ENDIAN
1672 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1673 // drive the pixel clock. not used for DCPLL case.
1674 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1675 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1676#else
1677 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1678 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1679 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1680 // drive the pixel clock. not used for DCPLL case.
1681#endif
1682}CRTC_PIXEL_CLOCK_FREQ;
1683
1684typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1685{
1686 union{
1687 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1688 ULONG ulDispEngClkFreq; // dispclk frequency
1689 };
1690 USHORT usFbDiv; // feedback divider integer part.
1691 UCHAR ucPostDiv; // post divider.
1692 UCHAR ucRefDiv; // Reference divider
1693 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1694 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1695 // indicate which graphic encoder will be used.
1696 UCHAR ucEncoderMode; // Encoder mode:
1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1698 // bit[1]= when VGA timing is used.
1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1700 // bit[4]= RefClock source for PPLL.
1701 // =0: XTLAIN( default mode )
1702 // =1: other external clock source, which is pre-defined
1703 // by VBIOS depend on the feature required.
1704 // bit[7:5]: reserved.
1705 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1706
1707}PIXEL_CLOCK_PARAMETERS_V6;
1708
1709#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1710#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1711#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1712#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1713#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1714#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1715#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1716#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1717#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1718#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1719#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
1720
1721typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1722{
1723 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1724}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1725
1726typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1727{
1728 UCHAR ucStatus;
1729 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1730 UCHAR ucReserved[2];
1731}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1732
1733typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1734{
1735 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1736}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1737
1738/****************************************************************************/
1739// Structures used by AdjustDisplayPllTable
1740/****************************************************************************/
1741typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1742{
1743 USHORT usPixelClock;
1744 UCHAR ucTransmitterID;
1745 UCHAR ucEncodeMode;
1746 union
1747 {
1748 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1749 UCHAR ucConfig; //if none DVO, not defined yet
1750 };
1751 UCHAR ucReserved[3];
1752}ADJUST_DISPLAY_PLL_PARAMETERS;
1753
1754#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
1755#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
1756
1757typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1758{
1759 USHORT usPixelClock; // target pixel clock
1760 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1762 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1763 UCHAR ucExtTransmitterID; // external encoder id.
1764 UCHAR ucReserved[2];
1765}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1766
1767// usDispPllConfig v1.2 for RoadRunner
1768#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
1769#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
1770#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
1771#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
1772#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
1773#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
1774#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
1775#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
1776#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
1777#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
1778
1779
1780typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1781{
1782 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1783 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1784 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1785 UCHAR ucReserved[2];
1786}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1787
1788typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1789{
1790 union
1791 {
1792 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
1793 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1794 };
1795} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1796
1797/****************************************************************************/
1798// Structures used by EnableYUVTable
1799/****************************************************************************/
1800typedef struct _ENABLE_YUV_PARAMETERS
1801{
1802 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1803 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1804 UCHAR ucPadding[2];
1805}ENABLE_YUV_PARAMETERS;
1806#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1807
1808/****************************************************************************/
1809// Structures used by GetMemoryClockTable
1810/****************************************************************************/
1811typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1812{
1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1814} GET_MEMORY_CLOCK_PARAMETERS;
1815#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
1816
1817/****************************************************************************/
1818// Structures used by GetEngineClockTable
1819/****************************************************************************/
1820typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1821{
1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1823} GET_ENGINE_CLOCK_PARAMETERS;
1824#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
1825
1826/****************************************************************************/
1827// Following Structures and constant may be obsolete
1828/****************************************************************************/
1829//Maxium 8 bytes,the data read in will be placed in the parameter space.
1830//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1831typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1832{
1833 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1834 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID
1835 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
1836 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
1837 UCHAR ucSlaveAddr; //Read from which slave
1838 UCHAR ucLineNumber; //Read from which HW assisted line
1839}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1840#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1841
1842
1843#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
1844#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
1845#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
1846#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
1847#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
1848
1849typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1850{
1851 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1852 USHORT usByteOffset; //Write to which byte
1853 //Upper portion of usByteOffset is Format of data
1854 //1bytePS+offsetPS
1855 //2bytesPS+offsetPS
1856 //blockID+offsetPS
1857 //blockID+offsetID
1858 //blockID+counterID+offsetID
1859 UCHAR ucData; //PS data1
1860 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1861 UCHAR ucSlaveAddr; //Write to which slave
1862 UCHAR ucLineNumber; //Write from which HW assisted line
1863}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1864
1865#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1866
1867typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1868{
1869 USHORT usPrescale; //Ratio between Engine clock and I2C clock
1870 UCHAR ucSlaveAddr; //Write to which slave
1871 UCHAR ucLineNumber; //Write from which HW assisted line
1872}SET_UP_HW_I2C_DATA_PARAMETERS;
1873
1874
1875/**************************************************************************/
1876#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1877
1878
1879/****************************************************************************/
1880// Structures used by PowerConnectorDetectionTable
1881/****************************************************************************/
1882typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
1883{
1884 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1885 UCHAR ucPwrBehaviorId;
1886 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1887}POWER_CONNECTOR_DETECTION_PARAMETERS;
1888
1889typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1890{
1891 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1892 UCHAR ucReserved;
1893 USHORT usPwrBudget; //how much power currently boot to in unit of watt
1894 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
1895}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1896
1897/****************************LVDS SS Command Table Definitions**********************/
1898
1899/****************************************************************************/
1900// Structures used by EnableSpreadSpectrumOnPPLLTable
1901/****************************************************************************/
1902typedef struct _ENABLE_LVDS_SS_PARAMETERS
1903{
1904 USHORT usSpreadSpectrumPercentage;
1905 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1907 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1908 UCHAR ucPadding[3];
1909}ENABLE_LVDS_SS_PARAMETERS;
1910
1911//ucTableFormatRevision=1,ucTableContentRevision=2
1912typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
1913{
1914 USHORT usSpreadSpectrumPercentage;
1915 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1916 UCHAR ucSpreadSpectrumStep; //
1917 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1918 UCHAR ucSpreadSpectrumDelay;
1919 UCHAR ucSpreadSpectrumRange;
1920 UCHAR ucPadding;
1921}ENABLE_LVDS_SS_PARAMETERS_V2;
1922
1923//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1924typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1925{
1926 USHORT usSpreadSpectrumPercentage;
1927 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1928 UCHAR ucSpreadSpectrumStep; //
1929 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1930 UCHAR ucSpreadSpectrumDelay;
1931 UCHAR ucSpreadSpectrumRange;
1932 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1933}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1934
1935typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1936{
1937 USHORT usSpreadSpectrumPercentage;
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1940 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1941 // Bits[7:4] reserved
1942 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1943 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1944 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1945}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1946
1947#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
1948#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
1949#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
1950#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
1951#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
1952#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
1953#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
1954#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
1955#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
1956#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
1957#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1958
1959// Used by DCE5.0
1960 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
1961{
1962 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
1965 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1966 // Bits[7:4] reserved
1967 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1968 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1969 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
1970}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
1971
1972#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
1973#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
1974#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
1975#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
1976#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
1977#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
1978#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
1979#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
1980#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
1981#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
1982#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
1983#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
1984
1985#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
1986
1987/**************************************************************************/
1988
1989typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
1990{
1991 PIXEL_CLOCK_PARAMETERS sPCLKInput;
1992 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
1993}SET_PIXEL_CLOCK_PS_ALLOCATION;
1994
1995#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
1996
1997/****************************************************************************/
1998// Structures used by ###
1999/****************************************************************************/
2000typedef struct _MEMORY_TRAINING_PARAMETERS
2001{
2002 ULONG ulTargetMemoryClock; //In 10Khz unit
2003}MEMORY_TRAINING_PARAMETERS;
2004#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
2005
2006
2007/****************************LVDS and other encoder command table definitions **********************/
2008
2009
2010/****************************************************************************/
2011// Structures used by LVDSEncoderControlTable (Before DCE30)
2012// LVTMAEncoderControlTable (Before DCE30)
2013// TMDSAEncoderControlTable (Before DCE30)
2014/****************************************************************************/
2015typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
2016{
2017 USHORT usPixelClock; // in 10KHz; for bios convenient
2018 UCHAR ucMisc; // bit0=0: Enable single link
2019 // =1: Enable dual link
2020 // Bit1=0: 666RGB
2021 // =1: 888RGB
2022 UCHAR ucAction; // 0: turn off encoder
2023 // 1: setup and turn on encoder
2024}LVDS_ENCODER_CONTROL_PARAMETERS;
2025
2026#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
2027
2028#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
2029#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2030
2031#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
2032#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2033
2034
2035//ucTableFormatRevision=1,ucTableContentRevision=2
2036typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2037{
2038 USHORT usPixelClock; // in 10KHz; for bios convenient
2039 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2040 UCHAR ucAction; // 0: turn off encoder
2041 // 1: setup and turn on encoder
2042 UCHAR ucTruncate; // bit0=0: Disable truncate
2043 // =1: Enable truncate
2044 // bit4=0: 666RGB
2045 // =1: 888RGB
2046 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2047 // =1: Enable spatial dithering
2048 // bit4=0: 666RGB
2049 // =1: 888RGB
2050 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2051 // =1: Enable temporal dithering
2052 // bit4=0: 666RGB
2053 // =1: 888RGB
2054 // bit5=0: Gray level 2
2055 // =1: Gray level 4
2056 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2057 // =1: 25FRC_SEL pattern F
2058 // bit6:5=0: 50FRC_SEL pattern A
2059 // =1: 50FRC_SEL pattern B
2060 // =2: 50FRC_SEL pattern C
2061 // =3: 50FRC_SEL pattern D
2062 // bit7=0: 75FRC_SEL pattern E
2063 // =1: 75FRC_SEL pattern F
2064}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2065
2066#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2067
2068#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2069#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2070
2071#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2072#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2073
2074#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2075#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2076
2077#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2078#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2079
2080#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2081#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2082
2083/****************************************************************************/
2084// Structures used by ###
2085/****************************************************************************/
2086typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2087{
2088 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2089 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2090 UCHAR ucPadding[2];
2091}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2092
2093typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2094{
2095 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
2096 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2097}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2098
2099#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2100
2101typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2102{
2103 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
2104 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2105}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2106
2107typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2108{
2109 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
2110 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2111}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2112
2113/****************************************************************************/
2114// Structures used by DVOEncoderControlTable
2115/****************************************************************************/
2116//ucTableFormatRevision=1,ucTableContentRevision=3
2117
2118//ucDVOConfig:
2119#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2120#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2121#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2122#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2123#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2124#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2125#define DVO_ENCODER_CONFIG_24BIT 0x08
2126
2127typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2128{
2129 USHORT usPixelClock;
2130 UCHAR ucDVOConfig;
2131 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2132 UCHAR ucReseved[4];
2133}DVO_ENCODER_CONTROL_PARAMETERS_V3;
2134#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2135
2136typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2137{
2138 USHORT usPixelClock;
2139 UCHAR ucDVOConfig;
2140 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2141 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2142 UCHAR ucReseved[3];
2143}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
2144#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2145
2146
2147//ucTableFormatRevision=1
2148//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2149// bit1=0: non-coherent mode
2150// =1: coherent mode
2151
2152//==========================================================================================
2153//Only change is here next time when changing encoder parameter definitions again!
2154#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2155#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2156
2157#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2158#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2159
2160#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2161#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2162
2163#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2164#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2165
2166//==========================================================================================
2167#define PANEL_ENCODER_MISC_DUAL 0x01
2168#define PANEL_ENCODER_MISC_COHERENT 0x02
2169#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2170#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2171
2172#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2173#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2174#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2175
2176#define PANEL_ENCODER_TRUNCATE_EN 0x01
2177#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2178#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2179#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2180#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2181#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2182#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2183#define PANEL_ENCODER_25FRC_MASK 0x10
2184#define PANEL_ENCODER_25FRC_E 0x00
2185#define PANEL_ENCODER_25FRC_F 0x10
2186#define PANEL_ENCODER_50FRC_MASK 0x60
2187#define PANEL_ENCODER_50FRC_A 0x00
2188#define PANEL_ENCODER_50FRC_B 0x20
2189#define PANEL_ENCODER_50FRC_C 0x40
2190#define PANEL_ENCODER_50FRC_D 0x60
2191#define PANEL_ENCODER_75FRC_MASK 0x80
2192#define PANEL_ENCODER_75FRC_E 0x00
2193#define PANEL_ENCODER_75FRC_F 0x80
2194
2195/****************************************************************************/
2196// Structures used by SetVoltageTable
2197/****************************************************************************/
2198#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2199#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2200#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2201#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2202#define SET_VOLTAGE_INIT_MODE 5
2203#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2204
2205#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2206#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2207#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2208
2209#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2210#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2211#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2212
2213typedef struct _SET_VOLTAGE_PARAMETERS
2214{
2215 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2216 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2217 UCHAR ucVoltageIndex; // An index to tell which voltage level
2218 UCHAR ucReserved;
2219}SET_VOLTAGE_PARAMETERS;
2220
2221typedef struct _SET_VOLTAGE_PARAMETERS_V2
2222{
2223 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2224 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2225 USHORT usVoltageLevel; // real voltage level
2226}SET_VOLTAGE_PARAMETERS_V2;
2227
2228// used by both SetVoltageTable v1.3 and v1.4
2229typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2230{
2231 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2232 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2233 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2234}SET_VOLTAGE_PARAMETERS_V1_3;
2235
2236//ucVoltageType
2237#define VOLTAGE_TYPE_VDDC 1
2238#define VOLTAGE_TYPE_MVDDC 2
2239#define VOLTAGE_TYPE_MVDDQ 3
2240#define VOLTAGE_TYPE_VDDCI 4
2241
2242//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2243#define ATOM_SET_VOLTAGE 0 //Set voltage Level
2244#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2245#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator
2246#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3
2247#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2248#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2249
2250// define vitual voltage id in usVoltageLevel
2251#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2252#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2253#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2254#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2255#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05
2256#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06
2257#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07
2258#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08
2259
2260typedef struct _SET_VOLTAGE_PS_ALLOCATION
2261{
2262 SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2263 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2264}SET_VOLTAGE_PS_ALLOCATION;
2265
2266// New Added from SI for GetVoltageInfoTable, input parameter structure
2267typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2268{
2269 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2270 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2271 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2272 ULONG ulReserved;
2273}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2274
2275// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2276typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2277{
2278 ULONG ulVotlageGpioState;
2279 ULONG ulVoltageGPioMask;
2280}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2281
2282// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2283typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2284{
2285 USHORT usVoltageLevel;
2286 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2287 ULONG ulReseved;
2288}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2289
2290
2291// GetVoltageInfo v1.1 ucVoltageMode
2292#define ATOM_GET_VOLTAGE_VID 0x00
2293#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2294#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2295#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
2296
2297// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2298#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2299// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2300#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2301
2302#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2303#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2304
2305// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2306typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
2307{
2308 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2309 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2310 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2311 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2312}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
2313
2314// New in GetVoltageInfo v1.2 ucVoltageMode
2315#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
2316
2317// New Added from CI Hawaii for EVV feature
2318typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
2319{
2320 USHORT usVoltageLevel; // real voltage level in unit of mv
2321 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2322 ULONG ulReseved;
2323}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
2324
2325/****************************************************************************/
2326// Structures used by TVEncoderControlTable
2327/****************************************************************************/
2328typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2329{
2330 USHORT usPixelClock; // in 10KHz; for bios convenient
2331 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2332 UCHAR ucAction; // 0: turn off encoder
2333 // 1: setup and turn on encoder
2334}TV_ENCODER_CONTROL_PARAMETERS;
2335
2336typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2337{
2338 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2339 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
2340}TV_ENCODER_CONTROL_PS_ALLOCATION;
2341
2342//==============================Data Table Portion====================================
2343
2344/****************************************************************************/
2345// Structure used in Data.mtb
2346/****************************************************************************/
2347typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2348{
2349 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2350 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2351 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2352 USHORT StandardVESA_Timing; // Only used by Bios
2353 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2354 USHORT PaletteData; // Only used by BIOS
2355 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2356 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2357 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1
2358 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2359 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2360 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2361 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2362 USHORT VESA_ToInternalModeLUT; // Only used by Bios
2363 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600
2364 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2365 USHORT CompassionateData; // Will be obsolete from R600
2366 USHORT SaveRestoreInfo; // Only used by Bios
2367 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2368 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2369 USHORT XTMDS_Info; // Will be obsolete from R600
2370 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2371 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2372 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2373 USHORT MC_InitParameter; // Only used by command table
2374 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2375 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2376 USHORT TV_VideoMode; // Only used by command table
2377 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2378 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2379 USHORT IntegratedSystemInfo; // Shared by various SW components
2380 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2381 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2382 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2383}ATOM_MASTER_LIST_OF_DATA_TABLES;
2384
2385typedef struct _ATOM_MASTER_DATA_TABLE
2386{
2387 ATOM_COMMON_TABLE_HEADER sHeader;
2388 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
2389}ATOM_MASTER_DATA_TABLE;
2390
2391// For backward compatible
2392#define LVDS_Info LCD_Info
2393#define DAC_Info PaletteData
2394#define TMDS_Info DIGTransmitterInfo
2395
2396/****************************************************************************/
2397// Structure used in MultimediaCapabilityInfoTable
2398/****************************************************************************/
2399typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2400{
2401 ATOM_COMMON_TABLE_HEADER sHeader;
2402 ULONG ulSignature; // HW info table signature string "$ATI"
2403 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2404 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2405 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2406 UCHAR ucHostPortInfo; // Provides host port configuration information
2407}ATOM_MULTIMEDIA_CAPABILITY_INFO;
2408
2409/****************************************************************************/
2410// Structure used in MultimediaConfigInfoTable
2411/****************************************************************************/
2412typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2413{
2414 ATOM_COMMON_TABLE_HEADER sHeader;
2415 ULONG ulSignature; // MM info table signature sting "$MMT"
2416 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2417 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2418 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2419 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2420 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2421 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2422 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2423 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2424 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2425 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2426 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2427 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2428}ATOM_MULTIMEDIA_CONFIG_INFO;
2429
2430
2431/****************************************************************************/
2432// Structures used in FirmwareInfoTable
2433/****************************************************************************/
2434
2435// usBIOSCapability Definition:
2436// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2437// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2438// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2439// Others: Reserved
2440#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2441#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2442#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2443#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2444#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2445#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2446#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2447#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2448#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2449#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2450#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2451#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2452#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2453#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2454
2455#ifndef _H2INC
2456
2457//Please don't add or expand this bitfield structure below, this one will retire soon.!
2458typedef struct _ATOM_FIRMWARE_CAPABILITY
2459{
2460#if ATOM_BIG_ENDIAN
2461 USHORT Reserved:1;
2462 USHORT SCL2Redefined:1;
2463 USHORT PostWithoutModeSet:1;
2464 USHORT HyperMemory_Size:4;
2465 USHORT HyperMemory_Support:1;
2466 USHORT PPMode_Assigned:1;
2467 USHORT WMI_SUPPORT:1;
2468 USHORT GPUControlsBL:1;
2469 USHORT EngineClockSS_Support:1;
2470 USHORT MemoryClockSS_Support:1;
2471 USHORT ExtendedDesktopSupport:1;
2472 USHORT DualCRTC_Support:1;
2473 USHORT FirmwarePosted:1;
2474#else
2475 USHORT FirmwarePosted:1;
2476 USHORT DualCRTC_Support:1;
2477 USHORT ExtendedDesktopSupport:1;
2478 USHORT MemoryClockSS_Support:1;
2479 USHORT EngineClockSS_Support:1;
2480 USHORT GPUControlsBL:1;
2481 USHORT WMI_SUPPORT:1;
2482 USHORT PPMode_Assigned:1;
2483 USHORT HyperMemory_Support:1;
2484 USHORT HyperMemory_Size:4;
2485 USHORT PostWithoutModeSet:1;
2486 USHORT SCL2Redefined:1;
2487 USHORT Reserved:1;
2488#endif
2489}ATOM_FIRMWARE_CAPABILITY;
2490
2491typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2492{
2493 ATOM_FIRMWARE_CAPABILITY sbfAccess;
2494 USHORT susAccess;
2495}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2496
2497#else
2498
2499typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2500{
2501 USHORT susAccess;
2502}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2503
2504#endif
2505
2506typedef struct _ATOM_FIRMWARE_INFO
2507{
2508 ATOM_COMMON_TABLE_HEADER sHeader;
2509 ULONG ulFirmwareRevision;
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2519 UCHAR ucASICMaxTemperature;
2520 UCHAR ucPadding[3]; //Don't use them
2521 ULONG aulReservedForBIOS[3]; //Don't use them
2522 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2523 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2524 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2525 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2526 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2527 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2529 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2530 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2531 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2532 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2533 USHORT usReferenceClock; //In 10Khz unit
2534 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2535 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2536 UCHAR ucDesign_ID; //Indicate what is the board design
2537 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2538}ATOM_FIRMWARE_INFO;
2539
2540typedef struct _ATOM_FIRMWARE_INFO_V1_2
2541{
2542 ATOM_COMMON_TABLE_HEADER sHeader;
2543 ULONG ulFirmwareRevision;
2544 ULONG ulDefaultEngineClock; //In 10Khz unit
2545 ULONG ulDefaultMemoryClock; //In 10Khz unit
2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2551 ULONG ulASICMaxEngineClock; //In 10Khz unit
2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2553 UCHAR ucASICMaxTemperature;
2554 UCHAR ucMinAllowedBL_Level;
2555 UCHAR ucPadding[2]; //Don't use them
2556 ULONG aulReservedForBIOS[2]; //Don't use them
2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2558 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2559 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2560 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2561 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2562 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2563 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2565 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2566 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2567 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2568 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2569 USHORT usReferenceClock; //In 10Khz unit
2570 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2571 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2572 UCHAR ucDesign_ID; //Indicate what is the board design
2573 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2574}ATOM_FIRMWARE_INFO_V1_2;
2575
2576typedef struct _ATOM_FIRMWARE_INFO_V1_3
2577{
2578 ATOM_COMMON_TABLE_HEADER sHeader;
2579 ULONG ulFirmwareRevision;
2580 ULONG ulDefaultEngineClock; //In 10Khz unit
2581 ULONG ulDefaultMemoryClock; //In 10Khz unit
2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2587 ULONG ulASICMaxEngineClock; //In 10Khz unit
2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2589 UCHAR ucASICMaxTemperature;
2590 UCHAR ucMinAllowedBL_Level;
2591 UCHAR ucPadding[2]; //Don't use them
2592 ULONG aulReservedForBIOS; //Don't use them
2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2595 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2596 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2597 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2598 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2599 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2600 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2602 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2603 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2604 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2605 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2606 USHORT usReferenceClock; //In 10Khz unit
2607 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2608 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2609 UCHAR ucDesign_ID; //Indicate what is the board design
2610 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2611}ATOM_FIRMWARE_INFO_V1_3;
2612
2613typedef struct _ATOM_FIRMWARE_INFO_V1_4
2614{
2615 ATOM_COMMON_TABLE_HEADER sHeader;
2616 ULONG ulFirmwareRevision;
2617 ULONG ulDefaultEngineClock; //In 10Khz unit
2618 ULONG ulDefaultMemoryClock; //In 10Khz unit
2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2624 ULONG ulASICMaxEngineClock; //In 10Khz unit
2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2626 UCHAR ucASICMaxTemperature;
2627 UCHAR ucMinAllowedBL_Level;
2628 USHORT usBootUpVDDCVoltage; //In MV unit
2629 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2630 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2633 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2634 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2635 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2636 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2637 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2638 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2640 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2641 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2642 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2643 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2644 USHORT usReferenceClock; //In 10Khz unit
2645 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2646 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2647 UCHAR ucDesign_ID; //Indicate what is the board design
2648 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2649}ATOM_FIRMWARE_INFO_V1_4;
2650
2651//the structure below to be used from Cypress
2652typedef struct _ATOM_FIRMWARE_INFO_V2_1
2653{
2654 ATOM_COMMON_TABLE_HEADER sHeader;
2655 ULONG ulFirmwareRevision;
2656 ULONG ulDefaultEngineClock; //In 10Khz unit
2657 ULONG ulDefaultMemoryClock; //In 10Khz unit
2658 ULONG ulReserved1;
2659 ULONG ulReserved2;
2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2663 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2665 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2666 UCHAR ucMinAllowedBL_Level;
2667 USHORT usBootUpVDDCVoltage; //In MV unit
2668 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2669 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2670 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2672 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2673 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2674 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2675 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2676 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2677 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2679 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2680 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2681 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2682 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2683 USHORT usCoreReferenceClock; //In 10Khz unit
2684 USHORT usMemoryReferenceClock; //In 10Khz unit
2685 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2686 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2687 UCHAR ucReserved4[3];
2688}ATOM_FIRMWARE_INFO_V2_1;
2689
2690//the structure below to be used from NI
2691//ucTableFormatRevision=2
2692//ucTableContentRevision=2
2693typedef struct _ATOM_FIRMWARE_INFO_V2_2
2694{
2695 ATOM_COMMON_TABLE_HEADER sHeader;
2696 ULONG ulFirmwareRevision;
2697 ULONG ulDefaultEngineClock; //In 10Khz unit
2698 ULONG ulDefaultMemoryClock; //In 10Khz unit
2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2701 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2702 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2704 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
2705 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2706 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2707 UCHAR ucMinAllowedBL_Level;
2708 USHORT usBootUpVDDCVoltage; //In MV unit
2709 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
2710 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
2711 ULONG ulReserved4; //Was ulAsicMaximumVoltage
2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2713 UCHAR ucRemoteDisplayConfig;
2714 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2715 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2716 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2717 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
2718 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2719 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2720 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2721 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2722 USHORT usCoreReferenceClock; //In 10Khz unit
2723 USHORT usMemoryReferenceClock; //In 10Khz unit
2724 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2725 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2726 UCHAR ucReserved9[3];
2727 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
2728 USHORT usReserved12;
2729 ULONG ulReserved10[3]; // New added comparing to previous version
2730}ATOM_FIRMWARE_INFO_V2_2;
2731
2732#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
2733
2734
2735// definition of ucRemoteDisplayConfig
2736#define REMOTE_DISPLAY_DISABLE 0x00
2737#define REMOTE_DISPLAY_ENABLE 0x01
2738
2739/****************************************************************************/
2740// Structures used in IntegratedSystemInfoTable
2741/****************************************************************************/
2742#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
2743#define IGP_CAP_FLAG_AC_CARD 0x4
2744#define IGP_CAP_FLAG_SDVO_CARD 0x8
2745#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
2746
2747typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2748{
2749 ATOM_COMMON_TABLE_HEADER sHeader;
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2754 UCHAR ucNumberOfCyclesInPeriodHi;
2755 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2756 USHORT usReserved1;
2757 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
2758 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
2759 ULONG ulReserved[2];
2760
2761 USHORT usFSBClock; //In MHz unit
2762 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2763 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2765 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2766 USHORT usK8MemoryClock; //in MHz unit
2767 USHORT usK8SyncStartDelay; //in 0.01 us unit
2768 USHORT usK8DataReturnTime; //in 0.01 us unit
2769 UCHAR ucMaxNBVoltage;
2770 UCHAR ucMinNBVoltage;
2771 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2772 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2773 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2775 UCHAR ucMaxNBVoltageHigh;
2776 UCHAR ucMinNBVoltageHigh;
2777}ATOM_INTEGRATED_SYSTEM_INFO;
2778
2779/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2780ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
2781 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2782ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2783 For AMD IGP,for now this can be 0
2784ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2785 For AMD IGP,for now this can be 0
2786
2787usFSBClock: For Intel IGP,it's FSB Freq
2788 For AMD IGP,it's HT Link Speed
2789
2790usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
2791usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2792usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
2793
2794VC:Voltage Control
2795ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2796ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2797
2798ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2799ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2800
2801ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2802ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2803
2804
2805usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2806usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2807*/
2808
2809
2810/*
2811The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2812Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2813The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2814
2815SW components can access the IGP system infor structure in the same way as before
2816*/
2817
2818
2819typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2820{
2821 ATOM_COMMON_TABLE_HEADER sHeader;
2822 ULONG ulBootUpEngineClock; //in 10kHz unit
2823 ULONG ulReserved1[2]; //must be 0x0 for the reserved
2824 ULONG ulBootUpUMAClock; //in 10kHz unit
2825 ULONG ulBootUpSidePortClock; //in 10kHz unit
2826 ULONG ulMinSidePortClock; //in 10kHz unit
2827 ULONG ulReserved2[6]; //must be 0x0 for the reserved
2828 ULONG ulSystemConfig; //see explanation below
2829 ULONG ulBootUpReqDisplayVector;
2830 ULONG ulOtherDisplayMisc;
2831 ULONG ulDDISlot1Config;
2832 ULONG ulDDISlot2Config;
2833 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2834 UCHAR ucUMAChannelNumber;
2835 UCHAR ucDockingPinBit;
2836 UCHAR ucDockingPinPolarity;
2837 ULONG ulDockingPinCFGInfo;
2838 ULONG ulCPUCapInfo;
2839 USHORT usNumberOfCyclesInPeriod;
2840 USHORT usMaxNBVoltage;
2841 USHORT usMinNBVoltage;
2842 USHORT usBootUpNBVoltage;
2843 ULONG ulHTLinkFreq; //in 10Khz
2844 USHORT usMinHTLinkWidth;
2845 USHORT usMaxHTLinkWidth;
2846 USHORT usUMASyncStartDelay;
2847 USHORT usUMADataReturnTime;
2848 USHORT usLinkStatusZeroTime;
2849 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2852 USHORT usMaxUpStreamHTLinkWidth;
2853 USHORT usMaxDownStreamHTLinkWidth;
2854 USHORT usMinUpStreamHTLinkWidth;
2855 USHORT usMinDownStreamHTLinkWidth;
2856 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2857 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2858 ULONG ulReserved3[96]; //must be 0x0
2859}ATOM_INTEGRATED_SYSTEM_INFO_V2;
2860
2861/*
2862ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2865
2866ulSystemConfig:
2867Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2869 =0: system boots up at driver control state. Power state depends on PowerPlay table.
2870Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2871Bit[3]=1: Only one power state(Performance) will be supported.
2872 =0: Multiple power states supported from PowerPlay table.
2873Bit[4]=1: CLMC is supported and enabled on current system.
2874 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2875Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2876 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2877Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2878 =0: Voltage settings is determined by powerplay table.
2879Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2880 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2881Bit[8]=1: CDLF is supported and enabled on current system.
2882 =0: CDLF is not supported or enabled on current system.
2883Bit[9]=1: DLL Shut Down feature is enabled on current system.
2884 =0: DLL Shut Down feature is not enabled or supported on current system.
2885
2886ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2887
2888ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2890
2891ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2892 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2893 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2894 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2895 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2896 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2897
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2900 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2901 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2902 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2903 CONNECTOR_OBJECT_ID_DISPLAYPORT
2904 CONNECTOR_OBJECT_ID_eDP
2905 [31:24]- Reserved
2906
2907ulDDISlot2Config: Same as Slot1.
2908ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2909For IGP, Hypermemory is the only memory type showed in CCC.
2910
2911ucUMAChannelNumber: how many channels for the UMA;
2912
2913ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2914ucDockingPinBit: which bit in this register to read the pin status;
2915ucDockingPinPolarity:Polarity of the pin when docked;
2916
2917ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2918
2919usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2920
2921usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2922usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2923 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2924 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2925 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2926
2927usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2928
2929ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2930usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
2931 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2932usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
2933 If CDLW enabled, both upstream and downstream width should be the same during bootup.
2934
2935usUMASyncStartDelay: Memory access latency, required for watermark calculation
2936usUMADataReturnTime: Memory access latency, required for watermark calculation
2937usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
2938for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2939 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2940 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2941 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2942 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2943
2944ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2945 This must be less than or equal to ulHTLinkFreq(bootup frequency).
2946ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2947 This must be less than or equal to ulHighVoltageHTLinkFreq.
2948
2949usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2950usMaxDownStreamHTLinkWidth: same as above.
2951usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2952usMinDownStreamHTLinkWidth: same as above.
2953*/
2954
2955// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
2956#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
2957#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2958#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
2959#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
2960#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
2961#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
2962
2963#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
2964
2965#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
2966#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
2967#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
2968#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
2969#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
2970#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
2971#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
2972#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
2973#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
2974#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
2975
2976#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
2977
2978#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
2979#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
2980#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
2981#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
2982#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
2983#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
2984
2985#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
2986#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
2987#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
2988
2989#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
2990
2991// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2992typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
2993{
2994 ATOM_COMMON_TABLE_HEADER sHeader;
2995 ULONG ulBootUpEngineClock; //in 10kHz unit
2996 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2997 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2998 ULONG ulBootUpUMAClock; //in 10kHz unit
2999 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3000 ULONG ulBootUpReqDisplayVector;
3001 ULONG ulOtherDisplayMisc;
3002 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3003 ULONG ulSystemConfig; //TBD
3004 ULONG ulCPUCapInfo; //TBD
3005 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3006 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3007 USHORT usBootUpNBVoltage; //boot up NB voltage
3008 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3009 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3010 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3011 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3012 ULONG ulDDISlot2Config;
3013 ULONG ulDDISlot3Config;
3014 ULONG ulDDISlot4Config;
3015 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3016 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3017 UCHAR ucUMAChannelNumber;
3018 USHORT usReserved;
3019 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3020 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3021 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3022 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3023 ULONG ulReserved6[61]; //must be 0x0
3024}ATOM_INTEGRATED_SYSTEM_INFO_V5;
3025
3026#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
3027#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
3028#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
3029#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
3030#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
3031#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
3032#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
3033#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
3034#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
3035#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
3036#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
3037#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
3038#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
3039#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
3040
3041// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3042#define ASIC_INT_DAC1_ENCODER_ID 0x00
3043#define ASIC_INT_TV_ENCODER_ID 0x02
3044#define ASIC_INT_DIG1_ENCODER_ID 0x03
3045#define ASIC_INT_DAC2_ENCODER_ID 0x04
3046#define ASIC_EXT_TV_ENCODER_ID 0x06
3047#define ASIC_INT_DVO_ENCODER_ID 0x07
3048#define ASIC_INT_DIG2_ENCODER_ID 0x09
3049#define ASIC_EXT_DIG_ENCODER_ID 0x05
3050#define ASIC_EXT_DIG2_ENCODER_ID 0x08
3051#define ASIC_INT_DIG3_ENCODER_ID 0x0a
3052#define ASIC_INT_DIG4_ENCODER_ID 0x0b
3053#define ASIC_INT_DIG5_ENCODER_ID 0x0c
3054#define ASIC_INT_DIG6_ENCODER_ID 0x0d
3055#define ASIC_INT_DIG7_ENCODER_ID 0x0e
3056
3057//define Encoder attribute
3058#define ATOM_ANALOG_ENCODER 0
3059#define ATOM_DIGITAL_ENCODER 1
3060#define ATOM_DP_ENCODER 2
3061
3062#define ATOM_ENCODER_ENUM_MASK 0x70
3063#define ATOM_ENCODER_ENUM_ID1 0x00
3064#define ATOM_ENCODER_ENUM_ID2 0x10
3065#define ATOM_ENCODER_ENUM_ID3 0x20
3066#define ATOM_ENCODER_ENUM_ID4 0x30
3067#define ATOM_ENCODER_ENUM_ID5 0x40
3068#define ATOM_ENCODER_ENUM_ID6 0x50
3069
3070#define ATOM_DEVICE_CRT1_INDEX 0x00000000
3071#define ATOM_DEVICE_LCD1_INDEX 0x00000001
3072#define ATOM_DEVICE_TV1_INDEX 0x00000002
3073#define ATOM_DEVICE_DFP1_INDEX 0x00000003
3074#define ATOM_DEVICE_CRT2_INDEX 0x00000004
3075#define ATOM_DEVICE_LCD2_INDEX 0x00000005
3076#define ATOM_DEVICE_DFP6_INDEX 0x00000006
3077#define ATOM_DEVICE_DFP2_INDEX 0x00000007
3078#define ATOM_DEVICE_CV_INDEX 0x00000008
3079#define ATOM_DEVICE_DFP3_INDEX 0x00000009
3080#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3081#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3082
3083#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3084#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3085#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3086#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3087#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3088#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3089#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3090
3091#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3092
3093#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3094#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3095#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3096#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3097#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3098#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3099#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3100#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3101#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3102#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3103#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3104#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3105
3106#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3107#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3108#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT)
3109#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3110
3111#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3112#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3113#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3114#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3115#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3116#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3117#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3118#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3119#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3120#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3121#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3122#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3123#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3124#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3125#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3126
3127
3128#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3129#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3130#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3131#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3132#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3133#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3134
3135#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3136
3137#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3138#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3139
3140#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3141#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3142#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3143#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3144#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3145#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3146
3147#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3148#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3149#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3150#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3151
3152// usDeviceSupport:
3153// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161// Bit 8 = 0 - no CV support= 1- CV is supported
3162// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3165//
3166//
3167
3168/****************************************************************************/
3169/* Structure used in MclkSS_InfoTable */
3170/****************************************************************************/
3171// ucI2C_ConfigID
3172// [7:0] - I2C LINE Associate ID
3173// = 0 - no I2C
3174// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3175// = 0, [6:0]=SW assisted I2C ID
3176// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3177// = 2, HW engine for Multimedia use
3178// = 3-7 Reserved for future I2C engines
3179// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3180
3181typedef struct _ATOM_I2C_ID_CONFIG
3182{
3183#if ATOM_BIG_ENDIAN
3184 UCHAR bfHW_Capable:1;
3185 UCHAR bfHW_EngineID:3;
3186 UCHAR bfI2C_LineMux:4;
3187#else
3188 UCHAR bfI2C_LineMux:4;
3189 UCHAR bfHW_EngineID:3;
3190 UCHAR bfHW_Capable:1;
3191#endif
3192}ATOM_I2C_ID_CONFIG;
3193
3194typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3195{
3196 ATOM_I2C_ID_CONFIG sbfAccess;
3197 UCHAR ucAccess;
3198}ATOM_I2C_ID_CONFIG_ACCESS;
3199
3200
3201/****************************************************************************/
3202// Structure used in GPIO_I2C_InfoTable
3203/****************************************************************************/
3204typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3205{
3206 USHORT usClkMaskRegisterIndex;
3207 USHORT usClkEnRegisterIndex;
3208 USHORT usClkY_RegisterIndex;
3209 USHORT usClkA_RegisterIndex;
3210 USHORT usDataMaskRegisterIndex;
3211 USHORT usDataEnRegisterIndex;
3212 USHORT usDataY_RegisterIndex;
3213 USHORT usDataA_RegisterIndex;
3214 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3215 UCHAR ucClkMaskShift;
3216 UCHAR ucClkEnShift;
3217 UCHAR ucClkY_Shift;
3218 UCHAR ucClkA_Shift;
3219 UCHAR ucDataMaskShift;
3220 UCHAR ucDataEnShift;
3221 UCHAR ucDataY_Shift;
3222 UCHAR ucDataA_Shift;
3223 UCHAR ucReserved1;
3224 UCHAR ucReserved2;
3225}ATOM_GPIO_I2C_ASSIGMENT;
3226
3227typedef struct _ATOM_GPIO_I2C_INFO
3228{
3229 ATOM_COMMON_TABLE_HEADER sHeader;
3230 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3231}ATOM_GPIO_I2C_INFO;
3232
3233/****************************************************************************/
3234// Common Structure used in other structures
3235/****************************************************************************/
3236
3237#ifndef _H2INC
3238
3239//Please don't add or expand this bitfield structure below, this one will retire soon.!
3240typedef struct _ATOM_MODE_MISC_INFO
3241{
3242#if ATOM_BIG_ENDIAN
3243 USHORT Reserved:6;
3244 USHORT RGB888:1;
3245 USHORT DoubleClock:1;
3246 USHORT Interlace:1;
3247 USHORT CompositeSync:1;
3248 USHORT V_ReplicationBy2:1;
3249 USHORT H_ReplicationBy2:1;
3250 USHORT VerticalCutOff:1;
3251 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3252 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3253 USHORT HorizontalCutOff:1;
3254#else
3255 USHORT HorizontalCutOff:1;
3256 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3257 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3258 USHORT VerticalCutOff:1;
3259 USHORT H_ReplicationBy2:1;
3260 USHORT V_ReplicationBy2:1;
3261 USHORT CompositeSync:1;
3262 USHORT Interlace:1;
3263 USHORT DoubleClock:1;
3264 USHORT RGB888:1;
3265 USHORT Reserved:6;
3266#endif
3267}ATOM_MODE_MISC_INFO;
3268
3269typedef union _ATOM_MODE_MISC_INFO_ACCESS
3270{
3271 ATOM_MODE_MISC_INFO sbfAccess;
3272 USHORT usAccess;
3273}ATOM_MODE_MISC_INFO_ACCESS;
3274
3275#else
3276
3277typedef union _ATOM_MODE_MISC_INFO_ACCESS
3278{
3279 USHORT usAccess;
3280}ATOM_MODE_MISC_INFO_ACCESS;
3281
3282#endif
3283
3284// usModeMiscInfo-
3285#define ATOM_H_CUTOFF 0x01
3286#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3287#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3288#define ATOM_V_CUTOFF 0x08
3289#define ATOM_H_REPLICATIONBY2 0x10
3290#define ATOM_V_REPLICATIONBY2 0x20
3291#define ATOM_COMPOSITESYNC 0x40
3292#define ATOM_INTERLACE 0x80
3293#define ATOM_DOUBLE_CLOCK_MODE 0x100
3294#define ATOM_RGB888_MODE 0x200
3295
3296//usRefreshRate-
3297#define ATOM_REFRESH_43 43
3298#define ATOM_REFRESH_47 47
3299#define ATOM_REFRESH_56 56
3300#define ATOM_REFRESH_60 60
3301#define ATOM_REFRESH_65 65
3302#define ATOM_REFRESH_70 70
3303#define ATOM_REFRESH_72 72
3304#define ATOM_REFRESH_75 75
3305#define ATOM_REFRESH_85 85
3306
3307// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3308// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3309//
3310// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3311// = EDID_HA + EDID_HBL
3312// VESA_HDISP = VESA_ACTIVE = EDID_HA
3313// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3314// = EDID_HA + EDID_HSO
3315// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3316// VESA_BORDER = EDID_BORDER
3317
3318/****************************************************************************/
3319// Structure used in SetCRTC_UsingDTDTimingTable
3320/****************************************************************************/
3321typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3322{
3323 USHORT usH_Size;
3324 USHORT usH_Blanking_Time;
3325 USHORT usV_Size;
3326 USHORT usV_Blanking_Time;
3327 USHORT usH_SyncOffset;
3328 USHORT usH_SyncWidth;
3329 USHORT usV_SyncOffset;
3330 USHORT usV_SyncWidth;
3331 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3332 UCHAR ucH_Border; // From DFP EDID
3333 UCHAR ucV_Border;
3334 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3335 UCHAR ucPadding[3];
3336}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3337
3338/****************************************************************************/
3339// Structure used in SetCRTC_TimingTable
3340/****************************************************************************/
3341typedef struct _SET_CRTC_TIMING_PARAMETERS
3342{
3343 USHORT usH_Total; // horizontal total
3344 USHORT usH_Disp; // horizontal display
3345 USHORT usH_SyncStart; // horozontal Sync start
3346 USHORT usH_SyncWidth; // horizontal Sync width
3347 USHORT usV_Total; // vertical total
3348 USHORT usV_Disp; // vertical display
3349 USHORT usV_SyncStart; // vertical Sync start
3350 USHORT usV_SyncWidth; // vertical Sync width
3351 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3352 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3353 UCHAR ucOverscanRight; // right
3354 UCHAR ucOverscanLeft; // left
3355 UCHAR ucOverscanBottom; // bottom
3356 UCHAR ucOverscanTop; // top
3357 UCHAR ucReserved;
3358}SET_CRTC_TIMING_PARAMETERS;
3359#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3360
3361/****************************************************************************/
3362// Structure used in StandardVESA_TimingTable
3363// AnalogTV_InfoTable
3364// ComponentVideoInfoTable
3365/****************************************************************************/
3366typedef struct _ATOM_MODE_TIMING
3367{
3368 USHORT usCRTC_H_Total;
3369 USHORT usCRTC_H_Disp;
3370 USHORT usCRTC_H_SyncStart;
3371 USHORT usCRTC_H_SyncWidth;
3372 USHORT usCRTC_V_Total;
3373 USHORT usCRTC_V_Disp;
3374 USHORT usCRTC_V_SyncStart;
3375 USHORT usCRTC_V_SyncWidth;
3376 USHORT usPixelClock; //in 10Khz unit
3377 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3378 USHORT usCRTC_OverscanRight;
3379 USHORT usCRTC_OverscanLeft;
3380 USHORT usCRTC_OverscanBottom;
3381 USHORT usCRTC_OverscanTop;
3382 USHORT usReserve;
3383 UCHAR ucInternalModeNumber;
3384 UCHAR ucRefreshRate;
3385}ATOM_MODE_TIMING;
3386
3387typedef struct _ATOM_DTD_FORMAT
3388{
3389 USHORT usPixClk;
3390 USHORT usHActive;
3391 USHORT usHBlanking_Time;
3392 USHORT usVActive;
3393 USHORT usVBlanking_Time;
3394 USHORT usHSyncOffset;
3395 USHORT usHSyncWidth;
3396 USHORT usVSyncOffset;
3397 USHORT usVSyncWidth;
3398 USHORT usImageHSize;
3399 USHORT usImageVSize;
3400 UCHAR ucHBorder;
3401 UCHAR ucVBorder;
3402 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3403 UCHAR ucInternalModeNumber;
3404 UCHAR ucRefreshRate;
3405}ATOM_DTD_FORMAT;
3406
3407/****************************************************************************/
3408// Structure used in LVDS_InfoTable
3409// * Need a document to describe this table
3410/****************************************************************************/
3411#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3412#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3413#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3414#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3415
3416//ucTableFormatRevision=1
3417//ucTableContentRevision=1
3418typedef struct _ATOM_LVDS_INFO
3419{
3420 ATOM_COMMON_TABLE_HEADER sHeader;
3421 ATOM_DTD_FORMAT sLCDTiming;
3422 USHORT usModePatchTableOffset;
3423 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3424 USHORT usOffDelayInMs;
3425 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3426 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3427 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3428 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3429 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3430 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3431 UCHAR ucPanelDefaultRefreshRate;
3432 UCHAR ucPanelIdentification;
3433 UCHAR ucSS_Id;
3434}ATOM_LVDS_INFO;
3435
3436//ucTableFormatRevision=1
3437//ucTableContentRevision=2
3438typedef struct _ATOM_LVDS_INFO_V12
3439{
3440 ATOM_COMMON_TABLE_HEADER sHeader;
3441 ATOM_DTD_FORMAT sLCDTiming;
3442 USHORT usExtInfoTableOffset;
3443 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3444 USHORT usOffDelayInMs;
3445 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3446 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3447 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3448 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3449 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3450 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3451 UCHAR ucPanelDefaultRefreshRate;
3452 UCHAR ucPanelIdentification;
3453 UCHAR ucSS_Id;
3454 USHORT usLCDVenderID;
3455 USHORT usLCDProductID;
3456 UCHAR ucLCDPanel_SpecialHandlingCap;
3457 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3458 UCHAR ucReserved[2];
3459}ATOM_LVDS_INFO_V12;
3460
3461//Definitions for ucLCDPanel_SpecialHandlingCap:
3462
3463//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3464//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3465#define LCDPANEL_CAP_READ_EDID 0x1
3466
3467//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3468//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3469//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3470#define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3471
3472//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3473#define LCDPANEL_CAP_eDP 0x4
3474
3475
3476//Color Bit Depth definition in EDID V1.4 @BYTE 14h
3477//Bit 6 5 4
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3486
3487#define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3488
3489// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3490#define PANEL_RANDOM_DITHER 0x80
3491#define PANEL_RANDOM_DITHER_MASK 0x80
3492
3493#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3494
3495/****************************************************************************/
3496// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3497// ASIC Families: NI
3498// ucTableFormatRevision=1
3499// ucTableContentRevision=3
3500/****************************************************************************/
3501typedef struct _ATOM_LCD_INFO_V13
3502{
3503 ATOM_COMMON_TABLE_HEADER sHeader;
3504 ATOM_DTD_FORMAT sLCDTiming;
3505 USHORT usExtInfoTableOffset;
3506 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3507 ULONG ulReserved0;
3508 UCHAR ucLCD_Misc; // Reorganized in V13
3509 // Bit0: {=0:single, =1:dual},
3510 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3511 // Bit3:2: {Grey level}
3512 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3513 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3514 UCHAR ucPanelDefaultRefreshRate;
3515 UCHAR ucPanelIdentification;
3516 UCHAR ucSS_Id;
3517 USHORT usLCDVenderID;
3518 USHORT usLCDProductID;
3519 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3520 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3521 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3522 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3523 // Bit7-3: Reserved
3524 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3525 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
3526
3527 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3528 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3529 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3530 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3531
3532 UCHAR ucOffDelay_in4Ms;
3533 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3534 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3535 UCHAR ucReserved1;
3536
3537 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3538 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3539 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3540 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3541
3542 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
3543 UCHAR uceDPToLVDSRxId;
3544 UCHAR ucLcdReservd;
3545 ULONG ulReserved[2];
3546}ATOM_LCD_INFO_V13;
3547
3548#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
3549
3550//Definitions for ucLCD_Misc
3551#define ATOM_PANEL_MISC_V13_DUAL 0x00000001
3552#define ATOM_PANEL_MISC_V13_FPDI 0x00000002
3553#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
3554#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
3555#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
3556#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
3557#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
3558
3559//Color Bit Depth definition in EDID V1.4 @BYTE 14h
3560//Bit 6 5 4
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3569
3570//Definitions for ucLCDPanel_SpecialHandlingCap:
3571
3572//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3573//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3574#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3575
3576//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3577//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3578//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3579#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
3580
3581//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3582#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
3583
3584//uceDPToLVDSRxId
3585#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
3587#define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
3588
3589typedef struct _ATOM_PATCH_RECORD_MODE
3590{
3591 UCHAR ucRecordType;
3592 USHORT usHDisp;
3593 USHORT usVDisp;
3594}ATOM_PATCH_RECORD_MODE;
3595
3596typedef struct _ATOM_LCD_RTS_RECORD
3597{
3598 UCHAR ucRecordType;
3599 UCHAR ucRTSValue;
3600}ATOM_LCD_RTS_RECORD;
3601
3602//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
3603// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
3604typedef struct _ATOM_LCD_MODE_CONTROL_CAP
3605{
3606 UCHAR ucRecordType;
3607 USHORT usLCDCap;
3608}ATOM_LCD_MODE_CONTROL_CAP;
3609
3610#define LCD_MODE_CAP_BL_OFF 1
3611#define LCD_MODE_CAP_CRTC_OFF 2
3612#define LCD_MODE_CAP_PANEL_OFF 4
3613
3614typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
3615{
3616 UCHAR ucRecordType;
3617 UCHAR ucFakeEDIDLength;
3618 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3619} ATOM_FAKE_EDID_PATCH_RECORD;
3620
3621typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
3622{
3623 UCHAR ucRecordType;
3624 USHORT usHSize;
3625 USHORT usVSize;
3626}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
3627
3628#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
3629#define LCD_RTS_RECORD_TYPE 2
3630#define LCD_CAP_RECORD_TYPE 3
3631#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
3632#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
3633#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
3634#define ATOM_RECORD_END_TYPE 0xFF
3635
3636/****************************Spread Spectrum Info Table Definitions **********************/
3637
3638//ucTableFormatRevision=1
3639//ucTableContentRevision=2
3640typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
3641{
3642 USHORT usSpreadSpectrumPercentage;
3643 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
3644 UCHAR ucSS_Step;
3645 UCHAR ucSS_Delay;
3646 UCHAR ucSS_Id;
3647 UCHAR ucRecommendedRef_Div;
3648 UCHAR ucSS_Range; //it was reserved for V11
3649}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
3650
3651#define ATOM_MAX_SS_ENTRY 16
3652#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3653#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3654#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
3655#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
3656
3657
3658#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
3659#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
3660#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
3661#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
3662#define ATOM_INTERNAL_SS_MASK 0x00000000
3663#define ATOM_EXTERNAL_SS_MASK 0x00000002
3664#define EXEC_SS_STEP_SIZE_SHIFT 2
3665#define EXEC_SS_DELAY_SHIFT 4
3666#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
3667
3668typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3669{
3670 ATOM_COMMON_TABLE_HEADER sHeader;
3671 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
3672}ATOM_SPREAD_SPECTRUM_INFO;
3673
3674/****************************************************************************/
3675// Structure used in AnalogTV_InfoTable (Top level)
3676/****************************************************************************/
3677//ucTVBootUpDefaultStd definition:
3678
3679//ATOM_TV_NTSC 1
3680//ATOM_TV_NTSCJ 2
3681//ATOM_TV_PAL 3
3682//ATOM_TV_PALM 4
3683//ATOM_TV_PALCN 5
3684//ATOM_TV_PALN 6
3685//ATOM_TV_PAL60 7
3686//ATOM_TV_SECAM 8
3687
3688//ucTVSupportedStd definition:
3689#define NTSC_SUPPORT 0x1
3690#define NTSCJ_SUPPORT 0x2
3691
3692#define PAL_SUPPORT 0x4
3693#define PALM_SUPPORT 0x8
3694#define PALCN_SUPPORT 0x10
3695#define PALN_SUPPORT 0x20
3696#define PAL60_SUPPORT 0x40
3697#define SECAM_SUPPORT 0x80
3698
3699#define MAX_SUPPORTED_TV_TIMING 2
3700
3701typedef struct _ATOM_ANALOG_TV_INFO
3702{
3703 ATOM_COMMON_TABLE_HEADER sHeader;
3704 UCHAR ucTV_SupportedStandard;
3705 UCHAR ucTV_BootUpDefaultStandard;
3706 UCHAR ucExt_TV_ASIC_ID;
3707 UCHAR ucExt_TV_ASIC_SlaveAddr;
3708 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
3709 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
3710}ATOM_ANALOG_TV_INFO;
3711
3712#define MAX_SUPPORTED_TV_TIMING_V1_2 3
3713
3714typedef struct _ATOM_ANALOG_TV_INFO_V1_2
3715{
3716 ATOM_COMMON_TABLE_HEADER sHeader;
3717 UCHAR ucTV_SupportedStandard;
3718 UCHAR ucTV_BootUpDefaultStandard;
3719 UCHAR ucExt_TV_ASIC_ID;
3720 UCHAR ucExt_TV_ASIC_SlaveAddr;
3721 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
3722}ATOM_ANALOG_TV_INFO_V1_2;
3723
3724typedef struct _ATOM_DPCD_INFO
3725{
3726 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3727 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3729 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3730}ATOM_DPCD_INFO;
3731
3732#define ATOM_DPCD_MAX_LANE_MASK 0x1F
3733
3734/**************************************************************************/
3735// VRAM usage and their defintions
3736
3737// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
3738// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
3739// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
3740// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
3741// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3742
3743#ifndef VESA_MEMORY_IN_64K_BLOCK
3744#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
3745#endif
3746
3747#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
3748#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
3749#define ATOM_HWICON_INFOTABLE_SIZE 32
3750#define MAX_DTD_MODE_IN_VRAM 6
3751#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
3752#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
3753//20 bytes for Encoder Type and DPCD in STD EDID area
3754#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3755#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
3756
3757#define ATOM_HWICON1_SURFACE_ADDR 0
3758#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3759#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3760#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
3761#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3762#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3763
3764#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3765#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3766#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3767
3768#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3769
3770#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3771#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3772#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3773
3774#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3775#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3776#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3777
3778#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3779#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3780#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3781
3782#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3783#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3784#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3785
3786#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3787#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3788#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3789
3790#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3791#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3792#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3793
3794#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3795#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3796#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3797
3798#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3799#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3800#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3801
3802#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3803#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3804#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3805
3806#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3807
3808#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3809#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
3810
3811//The size below is in Kb!
3812#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3813
3814#define ATOM_VRAM_RESERVE_V2_SIZE 32
3815
3816#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
3817#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
3818#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
3819#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
3820
3821/***********************************************************************************/
3822// Structure used in VRAM_UsageByFirmwareTable
3823// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
3824// at running time.
3825// note2: From RV770, the memory is more than 32bit addressable, so we will change
3826// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
3827// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
3828// (in offset to start of memory address) is KB aligned instead of byte aligend.
3829/***********************************************************************************/
3830// Note3:
3831/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
3832for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
3833
3834If (ulStartAddrUsedByFirmware!=0)
3835FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3836Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
3837else //Non VGA case
3838 if (FB_Size<=2Gb)
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3840 else
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3842
3843CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
3844
3845/***********************************************************************************/
3846#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
3847
3848typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
3849{
3850 ULONG ulStartAddrUsedByFirmware;
3851 USHORT usFirmwareUseInKb;
3852 USHORT usReserved;
3853}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
3854
3855typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
3856{
3857 ATOM_COMMON_TABLE_HEADER sHeader;
3858 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3859}ATOM_VRAM_USAGE_BY_FIRMWARE;
3860
3861// change verion to 1.5, when allow driver to allocate the vram area for command table access.
3862typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
3863{
3864 ULONG ulStartAddrUsedByFirmware;
3865 USHORT usFirmwareUseInKb;
3866 USHORT usFBUsedByDrvInKb;
3867}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
3868
3869typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
3870{
3871 ATOM_COMMON_TABLE_HEADER sHeader;
3872 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3873}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
3874
3875/****************************************************************************/
3876// Structure used in GPIO_Pin_LUTTable
3877/****************************************************************************/
3878typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3879{
3880 USHORT usGpioPin_AIndex;
3881 UCHAR ucGpioPinBitShift;
3882 UCHAR ucGPIO_ID;
3883}ATOM_GPIO_PIN_ASSIGNMENT;
3884
3885//ucGPIO_ID pre-define id for multiple usage
3886//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
3887#define PP_AC_DC_SWITCH_GPIO_PINID 60
3888//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
3889#define VDDC_VRHOT_GPIO_PINID 61
3890//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
3891#define VDDC_PCC_GPIO_PINID 62
3892
3893typedef struct _ATOM_GPIO_PIN_LUT
3894{
3895 ATOM_COMMON_TABLE_HEADER sHeader;
3896 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
3897}ATOM_GPIO_PIN_LUT;
3898
3899/****************************************************************************/
3900// Structure used in ComponentVideoInfoTable
3901/****************************************************************************/
3902#define GPIO_PIN_ACTIVE_HIGH 0x1
3903
3904#define MAX_SUPPORTED_CV_STANDARDS 5
3905
3906// definitions for ATOM_D_INFO.ucSettings
3907#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
3908#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
3909#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
3910
3911typedef struct _ATOM_GPIO_INFO
3912{
3913 USHORT usAOffset;
3914 UCHAR ucSettings;
3915 UCHAR ucReserved;
3916}ATOM_GPIO_INFO;
3917
3918// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
3919#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
3920
3921// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
3922#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
3923#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
3924
3925// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
3926//Line 3 out put 5V.
3927#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
3928#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
3929#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
3930
3931//Line 3 out put 2.2V
3932#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
3933#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
3934#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
3935
3936//Line 3 out put 0V
3937#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
3938#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
3939#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
3940
3941#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
3942
3943#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
3944
3945//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3946#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3947#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3948
3949
3950typedef struct _ATOM_COMPONENT_VIDEO_INFO
3951{
3952 ATOM_COMMON_TABLE_HEADER sHeader;
3953 USHORT usMask_PinRegisterIndex;
3954 USHORT usEN_PinRegisterIndex;
3955 USHORT usY_PinRegisterIndex;
3956 USHORT usA_PinRegisterIndex;
3957 UCHAR ucBitShift;
3958 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3959 ATOM_DTD_FORMAT sReserved; // must be zeroed out
3960 UCHAR ucMiscInfo;
3961 UCHAR uc480i;
3962 UCHAR uc480p;
3963 UCHAR uc720p;
3964 UCHAR uc1080i;
3965 UCHAR ucLetterBoxMode;
3966 UCHAR ucReserved[3];
3967 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3968 ATOM_GPIO_INFO