1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "radeon.h"
27#include "radeon_asic.h"
28#include "radeon_ucode.h"
29#include "cikd.h"
30#include "r600_dpm.h"
31#include "ci_dpm.h"
32#include "atom.h"
33#include <linux/seq_file.h>
34
35#define MC_CG_ARB_FREQ_F0 0x0a
36#define MC_CG_ARB_FREQ_F1 0x0b
37#define MC_CG_ARB_FREQ_F2 0x0c
38#define MC_CG_ARB_FREQ_F3 0x0d
39
40#define SMC_RAM_END 0x40000
41
42#define VOLTAGE_SCALE 4
43#define VOLTAGE_VID_OFFSET_SCALE1 625
44#define VOLTAGE_VID_OFFSET_SCALE2 100
45
46static const struct ci_pt_defaults defaults_hawaii_xt =
47{
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
51};
52
53static const struct ci_pt_defaults defaults_hawaii_pro =
54{
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
58};
59
60static const struct ci_pt_defaults defaults_bonaire_xt =
61{
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65};
66
67static const struct ci_pt_defaults defaults_bonaire_pro =
68{
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
72};
73
74static const struct ci_pt_defaults defaults_saturn_xt =
75{
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
79};
80
81static const struct ci_pt_defaults defaults_saturn_pro =
82{
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
86};
87
88static const struct ci_pt_config_reg didt_config_ci[] =
89{
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0xFFFFFFFF }
163};
164
165extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175extern int ci_mc_load_microcode(struct radeon_device *rdev);
176extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
178
179static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
184 u32 target_tdp);
185static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
186
187static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
188static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
189 PPSMC_Msg msg, u32 parameter);
190
191static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
192static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
193
194static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
195{
196 struct ci_power_info *pi = rdev->pm.dpm.priv;
197
198 return pi;
199}
200
201static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
202{
203 struct ci_ps *ps = rps->ps_priv;
204
205 return ps;
206}
207
208static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
209{
210 struct ci_power_info *pi = ci_get_pi(rdev);
211
212 switch (rdev->pdev->device) {
213 case 0x6649:
214 case 0x6650:
215 case 0x6651:
216 case 0x6658:
217 case 0x665C:
218 case 0x665D:
219 default:
220 pi->powertune_defaults = &defaults_bonaire_xt;
221 break;
222 case 0x6640:
223 case 0x6641:
224 case 0x6646:
225 case 0x6647:
226 pi->powertune_defaults = &defaults_saturn_xt;
227 break;
228 case 0x67B8:
229 case 0x67B0:
230 pi->powertune_defaults = &defaults_hawaii_xt;
231 break;
232 case 0x67BA:
233 case 0x67B1:
234 pi->powertune_defaults = &defaults_hawaii_pro;
235 break;
236 case 0x67A0:
237 case 0x67A1:
238 case 0x67A2:
239 case 0x67A8:
240 case 0x67A9:
241 case 0x67AA:
242 case 0x67B9:
243 case 0x67BE:
244 pi->powertune_defaults = &defaults_bonaire_xt;
245 break;
246 }
247
248 pi->dte_tj_offset = 0;
249
250 pi->caps_power_containment = true;
251 pi->caps_cac = false;
252 pi->caps_sq_ramping = false;
253 pi->caps_db_ramping = false;
254 pi->caps_td_ramping = false;
255 pi->caps_tcp_ramping = false;
256
257 if (pi->caps_power_containment) {
258 pi->caps_cac = true;
259 if (rdev->family == CHIP_HAWAII)
260 pi->enable_bapm_feature = false;
261 else
262 pi->enable_bapm_feature = true;
263 pi->enable_tdc_limit_feature = true;
264 pi->enable_pkg_pwr_tracking_feature = true;
265 }
266}
267
268static u8 ci_convert_to_vid(u16 vddc)
269{
270 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
271}
272
273static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
274{
275 struct ci_power_info *pi = ci_get_pi(rdev);
276 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
277 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
278 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
279 u32 i;
280
281 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
282 return -EINVAL;
283 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
284 return -EINVAL;
285 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
286 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
287 return -EINVAL;
288
289 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
290 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
291 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
292 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
293 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
294 } else {
295 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
296 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
297 }
298 }
299 return 0;
300}
301
302static int ci_populate_vddc_vid(struct radeon_device *rdev)
303{
304 struct ci_power_info *pi = ci_get_pi(rdev);
305 u8 *vid = pi->smc_powertune_table.VddCVid;
306 u32 i;
307
308 if (pi->vddc_voltage_table.count > 8)
309 return -EINVAL;
310
311 for (i = 0; i < pi->vddc_voltage_table.count; i++)
312 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
313
314 return 0;
315}
316
317static int ci_populate_svi_load_line(struct radeon_device *rdev)
318{
319 struct ci_power_info *pi = ci_get_pi(rdev);
320 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
321
322 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
323 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
324 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
325 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
326
327 return 0;
328}
329
330static int ci_populate_tdc_limit(struct radeon_device *rdev)
331{
332 struct ci_power_info *pi = ci_get_pi(rdev);
333 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
334 u16 tdc_limit;
335
336 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
337 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
338 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
339 pt_defaults->tdc_vddc_throttle_release_limit_perc;
340 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
341
342 return 0;
343}
344
345static int ci_populate_dw8(struct radeon_device *rdev)
346{
347 struct ci_power_info *pi = ci_get_pi(rdev);
348 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
349 int ret;
350
351 ret = ci_read_smc_sram_dword(rdev,
352 SMU7_FIRMWARE_HEADER_LOCATION +
353 offsetof(SMU7_Firmware_Header, PmFuseTable) +
354 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
355 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
356 pi->sram_end);
357 if (ret)
358 return -EINVAL;
359 else
360 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
361
362 return 0;
363}
364
365static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
366{
367 struct ci_power_info *pi = ci_get_pi(rdev);
368
369 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
370 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
371 rdev->pm.dpm.fan.fan_output_sensitivity =
372 rdev->pm.dpm.fan.default_fan_output_sensitivity;
373
374 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
375 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
376
377 return 0;
378}
379
380static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
381{
382 struct ci_power_info *pi = ci_get_pi(rdev);
383 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
384 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
385 int i, min, max;
386
387 min = max = hi_vid[0];
388 for (i = 0; i < 8; i++) {
389 if (0 != hi_vid[i]) {
390 if (min > hi_vid[i])
391 min = hi_vid[i];
392 if (max < hi_vid[i])
393 max = hi_vid[i];
394 }
395
396 if (0 != lo_vid[i]) {
397 if (min > lo_vid[i])
398 min = lo_vid[i];
399 if (max < lo_vid[i])
400 max = lo_vid[i];
401 }
402 }
403
404 if ((min == 0) || (max == 0))
405 return -EINVAL;
406 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
407 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
408
409 return 0;
410}
411
412static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
413{
414 struct ci_power_info *pi = ci_get_pi(rdev);
415 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
416 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
417 struct radeon_cac_tdp_table *cac_tdp_table =
418 rdev->pm.dpm.dyn_state.cac_tdp_table;
419
420 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
421 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
422
423 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
424 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
425
426 return 0;
427}
428
429static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
430{
431 struct ci_power_info *pi = ci_get_pi(rdev);
432 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
433 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
434 struct radeon_cac_tdp_table *cac_tdp_table =
435 rdev->pm.dpm.dyn_state.cac_tdp_table;
436 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
437 int i, j, k;
438 const u16 *def1;
439 const u16 *def2;
440
441 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
442 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
443
444 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
445 dpm_table->GpuTjMax =
446 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
447 dpm_table->GpuTjHyst = 8;
448
449 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
450
451 if (ppm) {
452 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
453 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
454 } else {
455 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
456 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
457 }
458
459 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
460 def1 = pt_defaults->bapmti_r;
461 def2 = pt_defaults->bapmti_rc;
462
463 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
464 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
465 for (k = 0; k < SMU7_DTE_SINKS; k++) {
466 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
467 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
468 def1++;
469 def2++;
470 }
471 }
472 }
473
474 return 0;
475}
476
477static int ci_populate_pm_base(struct radeon_device *rdev)
478{
479 struct ci_power_info *pi = ci_get_pi(rdev);
480 u32 pm_fuse_table_offset;
481 int ret;
482
483 if (pi->caps_power_containment) {
484 ret = ci_read_smc_sram_dword(rdev,
485 SMU7_FIRMWARE_HEADER_LOCATION +
486 offsetof(SMU7_Firmware_Header, PmFuseTable),
487 &pm_fuse_table_offset, pi->sram_end);
488 if (ret)
489 return ret;
490 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
491 if (ret)
492 return ret;
493 ret = ci_populate_vddc_vid(rdev);
494 if (ret)
495 return ret;
496 ret = ci_populate_svi_load_line(rdev);
497 if (ret)
498 return ret;
499 ret = ci_populate_tdc_limit(rdev);
500 if (ret)
501 return ret;
502 ret = ci_populate_dw8(rdev);
503 if (ret)
504 return ret;
505 ret = ci_populate_fuzzy_fan(rdev);
506 if (ret)
507 return ret;
508 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
509 if (ret)
510 return ret;
511 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
512 if (ret)
513 return ret;
514 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
515 (u8 *)&pi->smc_powertune_table,
516 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
517 if (ret)
518 return ret;
519 }
520
521 return 0;
522}
523
524static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
525{
526 struct ci_power_info *pi = ci_get_pi(rdev);
527 u32 data;
528
529 if (pi->caps_sq_ramping) {
530 data = RREG32_DIDT(DIDT_SQ_CTRL0);
531 if (enable)
532 data |= DIDT_CTRL_EN;
533 else
534 data &= ~DIDT_CTRL_EN;
535 WREG32_DIDT(DIDT_SQ_CTRL0, data);
536 }
537
538 if (pi->caps_db_ramping) {
539 data = RREG32_DIDT(DIDT_DB_CTRL0);
540 if (enable)
541 data |= DIDT_CTRL_EN;
542 else
543 data &= ~DIDT_CTRL_EN;
544 WREG32_DIDT(DIDT_DB_CTRL0, data);
545 }
546
547 if (pi->caps_td_ramping) {
548 data = RREG32_DIDT(DIDT_TD_CTRL0);
549 if (enable)
550 data |= DIDT_CTRL_EN;
551 else
552 data &= ~DIDT_CTRL_EN;
553 WREG32_DIDT(DIDT_TD_CTRL0, data);
554 }
555
556 if (pi->caps_tcp_ramping) {
557 data = RREG32_DIDT(DIDT_TCP_CTRL0);
558 if (enable)
559 data |= DIDT_CTRL_EN;
560 else
561 data &= ~DIDT_CTRL_EN;
562 WREG32_DIDT(DIDT_TCP_CTRL0, data);
563 }
564}
565
566static int ci_program_pt_config_registers(struct radeon_device *rdev,
567 const struct ci_pt_config_reg *cac_config_regs)
568{
569 const struct ci_pt_config_reg *config_regs = cac_config_regs;
570 u32 data;
571 u32 cache = 0;
572
573 if (config_regs == NULL)
574 return -EINVAL;
575
576 while (config_regs->offset != 0xFFFFFFFF) {
577 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
578 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
579 } else {
580 switch (config_regs->type) {
581 case CISLANDS_CONFIGREG_SMC_IND:
582 data = RREG32_SMC(config_regs->offset);
583 break;
584 case CISLANDS_CONFIGREG_DIDT_IND:
585 data = RREG32_DIDT(config_regs->offset);
586 break;
587 default:
588 data = RREG32(config_regs->offset << 2);
589 break;
590 }
591
592 data &= ~config_regs->mask;
593 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
594 data |= cache;
595
596 switch (config_regs->type) {
597 case CISLANDS_CONFIGREG_SMC_IND:
598 WREG32_SMC(config_regs->offset, data);
599 break;
600 case CISLANDS_CONFIGREG_DIDT_IND:
601 WREG32_DIDT(config_regs->offset, data);
602 break;
603 default:
604 WREG32(config_regs->offset << 2, data);
605 break;
606 }
607 cache = 0;
608 }
609 config_regs++;
610 }
611 return 0;
612}
613
614static int ci_enable_didt(struct radeon_device *rdev, bool enable)
615{
616 struct ci_power_info *pi = ci_get_pi(rdev);
617 int ret;
618
619 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
620 pi->caps_td_ramping || pi->caps_tcp_ramping) {
621 cik_enter_rlc_safe_mode(rdev);
622
623 if (enable) {
624 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
625 if (ret) {
626 cik_exit_rlc_safe_mode(rdev);
627 return ret;
628 }
629 }
630
631 ci_do_enable_didt(rdev, enable);
632
633 cik_exit_rlc_safe_mode(rdev);
634 }
635
636 return 0;
637}
638
639static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
640{
641 struct ci_power_info *pi = ci_get_pi(rdev);
642 PPSMC_Result smc_result;
643 int ret = 0;
644
645 if (enable) {
646 pi->power_containment_features = 0;
647 if (pi->caps_power_containment) {
648 if (pi->enable_bapm_feature) {
649 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
650 if (smc_result != PPSMC_Result_OK)
651 ret = -EINVAL;
652 else
653 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
654 }
655
656 if (pi->enable_tdc_limit_feature) {
657 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
658 if (smc_result != PPSMC_Result_OK)
659 ret = -EINVAL;
660 else
661 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
662 }
663
664 if (pi->enable_pkg_pwr_tracking_feature) {
665 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
666 if (smc_result != PPSMC_Result_OK) {
667 ret = -EINVAL;
668 } else {
669 struct radeon_cac_tdp_table *cac_tdp_table =
670 rdev->pm.dpm.dyn_state.cac_tdp_table;
671 u32 default_pwr_limit =
672 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
673
674 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
675
676 ci_set_power_limit(rdev, default_pwr_limit);
677 }
678 }
679 }
680 } else {
681 if (pi->caps_power_containment && pi->power_containment_features) {
682 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
683 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
684
685 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
686 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
687
688 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
689 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
690 pi->power_containment_features = 0;
691 }
692 }
693
694 return ret;
695}
696
697static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
698{
699 struct ci_power_info *pi = ci_get_pi(rdev);
700 PPSMC_Result smc_result;
701 int ret = 0;
702
703 if (pi->caps_cac) {
704 if (enable) {
705 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
706 if (smc_result != PPSMC_Result_OK) {
707 ret = -EINVAL;
708 pi->cac_enabled = false;
709 } else {
710 pi->cac_enabled = true;
711 }
712 } else if (pi->cac_enabled) {
713 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
714 pi->cac_enabled = false;
715 }
716 }
717
718 return ret;
719}
720
721static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
722 bool enable)
723{
724 struct ci_power_info *pi = ci_get_pi(rdev);
725 PPSMC_Result smc_result = PPSMC_Result_OK;
726
727 if (pi->thermal_sclk_dpm_enabled) {
728 if (enable)
729 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
730 else
731 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
732 }
733
734 if (smc_result == PPSMC_Result_OK)
735 return 0;
736 else
737 return -EINVAL;
738}
739
740static int ci_power_control_set_level(struct radeon_device *rdev)
741{
742 struct ci_power_info *pi = ci_get_pi(rdev);
743 struct radeon_cac_tdp_table *cac_tdp_table =
744 rdev->pm.dpm.dyn_state.cac_tdp_table;
745 s32 adjust_percent;
746 s32 target_tdp;
747 int ret = 0;
748 bool adjust_polarity = false; /* ??? */
749
750 if (pi->caps_power_containment) {
751 adjust_percent = adjust_polarity ?
752 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
753 target_tdp = ((100 + adjust_percent) *
754 (s32)cac_tdp_table->configurable_tdp) / 100;
755
756 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
757 }
758
759 return ret;
760}
761
762void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
763{
764 struct ci_power_info *pi = ci_get_pi(rdev);
765
766 if (pi->uvd_power_gated == gate)
767 return;
768
769 pi->uvd_power_gated = gate;
770
771 ci_update_uvd_dpm(rdev, gate);
772}
773
774bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
775{
776 struct ci_power_info *pi = ci_get_pi(rdev);
777 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
778 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
779
780 /* disable mclk switching if the refresh is >120Hz, even if the
781 * blanking period would allow it
782 */
783 if (r600_dpm_get_vrefresh(rdev) > 120)
784 return true;
785
786 if (vblank_time < switch_limit)
787 return true;
788 else
789 return false;
790
791}
792
793static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
794 struct radeon_ps *rps)
795{
796 struct ci_ps *ps = ci_get_ps(rps);
797 struct ci_power_info *pi = ci_get_pi(rdev);
798 struct radeon_clock_and_voltage_limits *max_limits;
799 bool disable_mclk_switching;
800 u32 sclk, mclk;
801 int i;
802
803 if (rps->vce_active) {
804 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
805 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
806 } else {
807 rps->evclk = 0;
808 rps->ecclk = 0;
809 }
810
811 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
812 ci_dpm_vblank_too_short(rdev))
813 disable_mclk_switching = true;
814 else
815 disable_mclk_switching = false;
816
817 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
818 pi->battery_state = true;
819 else
820 pi->battery_state = false;
821
822 if (rdev->pm.dpm.ac_power)
823 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
824 else
825 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
826
827 if (rdev->pm.dpm.ac_power == false) {
828 for (i = 0; i < ps->performance_level_count; i++) {
829 if (ps->performance_levels[i].mclk > max_limits->mclk)
830 ps->performance_levels[i].mclk = max_limits->mclk;
831 if (ps->performance_levels[i].sclk > max_limits->sclk)
832 ps->performance_levels[i].sclk = max_limits->sclk;
833 }
834 }
835
836 /* XXX validate the min clocks required for display */
837
838 if (disable_mclk_switching) {
839 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
840 sclk = ps->performance_levels[0].sclk;
841 } else {
842 mclk = ps->performance_levels[0].mclk;
843 sclk = ps->performance_levels[0].sclk;
844 }
845
846 if (rps->vce_active) {
847 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
848 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
849 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
850 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
851 }
852
853 ps->performance_levels[0].sclk = sclk;
854 ps->performance_levels[0].mclk = mclk;
855
856 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
857 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
858
859 if (disable_mclk_switching) {
860 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
861 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
862 } else {
863 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
864 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
865 }
866}
867
868static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
869 int min_temp, int max_temp)
870{
871 int low_temp = 0 * 1000;
872 int high_temp = 255 * 1000;
873 u32 tmp;
874
875 if (low_temp < min_temp)
876 low_temp = min_temp;
877 if (high_temp > max_temp)
878 high_temp = max_temp;
879 if (high_temp < low_temp) {
880 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
881 return -EINVAL;
882 }
883
884 tmp = RREG32_SMC(CG_THERMAL_INT);
885 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
886 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
887 CI_DIG_THERM_INTL(low_temp / 1000);
888 WREG32_SMC(CG_THERMAL_INT, tmp);
889
890#if 0
891 /* XXX: need to figure out how to handle this properly */
892 tmp = RREG32_SMC(CG_THERMAL_CTRL);
893 tmp &= DIG_THERM_DPM_MASK;
894 tmp |= DIG_THERM_DPM(high_temp / 1000);
895 WREG32_SMC(CG_THERMAL_CTRL, tmp);
896#endif
897
898 rdev->pm.dpm.thermal.min_temp = low_temp;
899 rdev->pm.dpm.thermal.max_temp = high_temp;
900
901 return 0;
902}
903
904static int ci_thermal_enable_alert(struct radeon_device *rdev,
905 bool enable)
906{
907 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
908 PPSMC_Result result;
909
910 if (enable) {
911 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
912 WREG32_SMC(CG_THERMAL_INT, thermal_int);
913 rdev->irq.dpm_thermal = false;
914 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
915 if (result != PPSMC_Result_OK) {
916 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
917 return -EINVAL;
918 }
919 } else {
920 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
921 WREG32_SMC(CG_THERMAL_INT, thermal_int);
922 rdev->irq.dpm_thermal = true;
923 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
924 if (result != PPSMC_Result_OK) {
925 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
926 return -EINVAL;
927 }
928 }
929
930 return 0;
931}
932
933static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
934{
935 struct ci_power_info *pi = ci_get_pi(rdev);
936 u32 tmp;
937
938 if (pi->fan_ctrl_is_in_default_mode) {
939 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
940 pi->fan_ctrl_default_mode = tmp;
941 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
942 pi->t_min = tmp;
943 pi->fan_ctrl_is_in_default_mode = false;
944 }
945
946 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
947 tmp |= TMIN(0);
948 WREG32_SMC(CG_FDO_CTRL2, tmp);
949
950 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
951 tmp |= FDO_PWM_MODE(mode);
952 WREG32_SMC(CG_FDO_CTRL2, tmp);
953}
954
955static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
956{
957 struct ci_power_info *pi = ci_get_pi(rdev);
958 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
959 u32 duty100;
960 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
961 u16 fdo_min, slope1, slope2;
962 u32 reference_clock, tmp;
963 int ret;
964 u64 tmp64;
965
966 if (!pi->fan_table_start) {
967 rdev->pm.dpm.fan.ucode_fan_control = false;
968 return 0;
969 }
970
971 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
972
973 if (duty100 == 0) {
974 rdev->pm.dpm.fan.ucode_fan_control = false;
975 return 0;
976 }
977
978 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
979 do_div(tmp64, 10000);
980 fdo_min = (u16)tmp64;
981
982 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
983 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
984
985 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
986 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
987
988 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
989 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
990
991 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
992 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
993 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
994
995 fan_table.Slope1 = cpu_to_be16(slope1);
996 fan_table.Slope2 = cpu_to_be16(slope2);
997
998 fan_table.FdoMin = cpu_to_be16(fdo_min);
999
1000 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1001
1002 fan_table.HystUp = cpu_to_be16(1);
1003
1004 fan_table.HystSlope = cpu_to_be16(1);
1005
1006 fan_table.TempRespLim = cpu_to_be16(5);
1007
1008 reference_clock = radeon_get_xclk(rdev);
1009
1010 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1011 reference_clock) / 1600);
1012
1013 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1014
1015 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1016 fan_table.TempSrc = (uint8_t)tmp;
1017
1018 ret = ci_copy_bytes_to_smc(rdev,
1019 pi->fan_table_start,
1020 (u8 *)(&fan_table),
1021 sizeof(fan_table),
1022 pi->sram_end);
1023
1024 if (ret) {
1025 DRM_ERROR("Failed to load fan table to the SMC.");
1026 rdev->pm.dpm.fan.ucode_fan_control = false;
1027 }
1028
1029 return 0;
1030}
1031
1032static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1033{
1034 struct ci_power_info *pi = ci_get_pi(rdev);
1035 PPSMC_Result ret;
1036
1037 if (pi->caps_od_fuzzy_fan_control_support) {
1038 ret = ci_send_msg_to_smc_with_parameter(rdev,
1039 PPSMC_StartFanControl,
1040 FAN_CONTROL_FUZZY);
1041 if (ret != PPSMC_Result_OK)
1042 return -EINVAL;
1043 ret = ci_send_msg_to_smc_with_parameter(rdev,
1044 PPSMC_MSG_SetFanPwmMax,
1045 rdev->pm.dpm.fan.default_max_fan_pwm);
1046 if (ret != PPSMC_Result_OK)
1047 return -EINVAL;
1048 } else {
1049 ret = ci_send_msg_to_smc_with_parameter(rdev,
1050 PPSMC_StartFanControl,
1051 FAN_CONTROL_TABLE);
1052 if (ret != PPSMC_Result_OK)
1053 return -EINVAL;
1054 }
1055
1056 pi->fan_is_controlled_by_smc = true;
1057 return 0;
1058}
1059
1060static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1061{
1062 PPSMC_Result ret;
1063 struct ci_power_info *pi = ci_get_pi(rdev);
1064
1065 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1066 if (ret == PPSMC_Result_OK) {
1067 pi->fan_is_controlled_by_smc = false;
1068 return 0;
1069 } else
1070 return -EINVAL;
1071}
1072
1073int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1074 u32 *speed)
1075{
1076 u32 duty, duty100;
1077 u64 tmp64;
1078
1079 if (rdev->pm.no_fan)
1080 return -ENOENT;
1081
1082 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1083 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1084
1085 if (duty100 == 0)
1086 return -EINVAL;
1087
1088 tmp64 = (u64)duty * 100;
1089 do_div(tmp64, duty100);
1090 *speed = (u32)tmp64;
1091
1092 if (*speed > 100)
1093 *speed = 100;
1094
1095 return 0;
1096}
1097
1098int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1099 u32 speed)
1100{
1101 u32 tmp;
1102 u32 duty, duty100;
1103 u64 tmp64;
1104 struct ci_power_info *pi = ci_get_pi(rdev);
1105
1106 if (rdev->pm.no_fan)
1107 return -ENOENT;
1108
1109 if (pi->fan_is_controlled_by_smc)
1110 return -EINVAL;
1111
1112 if (speed > 100)
1113 return -EINVAL;
1114
1115 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1116
1117 if (duty100 == 0)
1118 return -EINVAL;
1119
1120 tmp64 = (u64)speed * duty100;
1121 do_div(tmp64, 100);
1122 duty = (u32)tmp64;
1123
1124 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1125 tmp |= FDO_STATIC_DUTY(duty);
1126 WREG32_SMC(CG_FDO_CTRL0, tmp);
1127
1128 return 0;
1129}
1130
1131void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1132{
1133 if (mode) {
1134 /* stop auto-manage */
1135 if (rdev->pm.dpm.fan.ucode_fan_control)
1136 ci_fan_ctrl_stop_smc_fan_control(rdev);
1137 ci_fan_ctrl_set_static_mode(rdev, mode);
1138 } else {
1139 /* restart auto-manage */
1140 if (rdev->pm.dpm.fan.ucode_fan_control)
1141 ci_thermal_start_smc_fan_control(rdev);
1142 else
1143 ci_fan_ctrl_set_default_mode(rdev);
1144 }
1145}
1146
1147u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1148{
1149 struct ci_power_info *pi = ci_get_pi(rdev);
1150 u32 tmp;
1151
1152 if (pi->fan_is_controlled_by_smc)
1153 return 0;
1154
1155 tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1156 return (tmp >> FDO_PWM_MODE_SHIFT);
1157}
1158
1159#if 0
1160static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1161 u32 *speed)
1162{
1163 u32 tach_period;
1164 u32 xclk = radeon_get_xclk(rdev);
1165
1166 if (rdev->pm.no_fan)
1167 return -ENOENT;
1168
1169 if (rdev->pm.fan_pulses_per_revolution == 0)
1170 return -ENOENT;
1171
1172 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1173 if (tach_period == 0)
1174 return -ENOENT;
1175
1176 *speed = 60 * xclk * 10000 / tach_period;
1177
1178 return 0;
1179}
1180
1181static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1182 u32 speed)
1183{
1184 u32 tach_period, tmp;
1185 u32 xclk = radeon_get_xclk(rdev);
1186
1187 if (rdev->pm.no_fan)
1188 return -ENOENT;
1189
1190 if (rdev->pm.fan_pulses_per_revolution == 0)
1191 return -ENOENT;
1192
1193 if ((speed < rdev->pm.fan_min_rpm) ||
1194 (speed > rdev->pm.fan_max_rpm))
1195 return -EINVAL;
1196
1197 if (rdev->pm.dpm.fan.ucode_fan_control)
1198 ci_fan_ctrl_stop_smc_fan_control(rdev);
1199
1200 tach_period = 60 * xclk * 10000 / (8 * speed);
1201 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1202 tmp |= TARGET_PERIOD(tach_period);
1203 WREG32_SMC(CG_TACH_CTRL, tmp);
1204
1205 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1206
1207 return 0;
1208}
1209#endif
1210
1211static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1212{
1213 struct ci_power_info *pi = ci_get_pi(rdev);
1214 u32 tmp;
1215
1216 if (!pi->fan_ctrl_is_in_default_mode) {
1217 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1218 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1219 WREG32_SMC(CG_FDO_CTRL2, tmp);
1220
1221 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1222 tmp |= TMIN(pi->t_min);
1223 WREG32_SMC(CG_FDO_CTRL2, tmp);
1224 pi->fan_ctrl_is_in_default_mode = true;
1225 }
1226}
1227
1228static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1229{
1230 if (rdev->pm.dpm.fan.ucode_fan_control) {
1231 ci_fan_ctrl_start_smc_fan_control(rdev);
1232 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1233 }
1234}
1235
1236static void ci_thermal_initialize(struct radeon_device *rdev)
1237{
1238 u32 tmp;
1239
1240 if (rdev->pm.fan_pulses_per_revolution) {
1241 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1242 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1243 WREG32_SMC(CG_TACH_CTRL, tmp);
1244 }
1245
1246 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1247 tmp |= TACH_PWM_RESP_RATE(0x28);
1248 WREG32_SMC(CG_FDO_CTRL2, tmp);
1249}
1250
1251static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1252{
1253 int ret;
1254
1255 ci_thermal_initialize(rdev);
1256 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1257 if (ret)
1258 return ret;
1259 ret = ci_thermal_enable_alert(rdev, true);
1260 if (ret)
1261 return ret;
1262 if (rdev->pm.dpm.fan.ucode_fan_control) {
1263 ret = ci_thermal_setup_fan_table(rdev);
1264 if (ret)
1265 return ret;
1266 ci_thermal_start_smc_fan_control(rdev);
1267 }
1268
1269 return 0;
1270}
1271
1272static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1273{
1274 if (!rdev->pm.no_fan)
1275 ci_fan_ctrl_set_default_mode(rdev);
1276}
1277
1278#if 0
1279static int ci_read_smc_soft_register(struct radeon_device *rdev,
1280 u16 reg_offset, u32 *value)
1281{
1282 struct ci_power_info *pi = ci_get_pi(rdev);
1283
1284 return ci_read_smc_sram_dword(rdev,
1285 pi->soft_regs_start + reg_offset,
1286 value, pi->sram_end);
1287}
1288#endif
1289
1290static int ci_write_smc_soft_register(struct radeon_device *rdev,
1291 u16 reg_offset, u32 value)
1292{
1293 struct ci_power_info *pi = ci_get_pi(rdev);
1294
1295 return ci_write_smc_sram_dword(rdev,
1296 pi->soft_regs_start + reg_offset,
1297 value, pi->sram_end);
1298}
1299
1300static void ci_init_fps_limits(struct radeon_device *rdev)
1301{
1302 struct ci_power_info *pi = ci_get_pi(rdev);
1303 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1304
1305 if (pi->caps_fps) {
1306 u16 tmp;
1307
1308 tmp = 45;
1309 table->FpsHighT = cpu_to_be16(tmp);
1310
1311 tmp = 30;
1312 table->FpsLowT = cpu_to_be16(tmp);
1313 }
1314}
1315
1316static int ci_update_sclk_t(struct radeon_device *rdev)
1317{
1318 struct ci_power_info *pi = ci_get_pi(rdev);
1319 int ret = 0;
1320 u32 low_sclk_interrupt_t = 0;
1321
1322 if (pi->caps_sclk_throttle_low_notification) {
1323 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1324
1325 ret = ci_copy_bytes_to_smc(rdev,
1326 pi->dpm_table_start +
1327 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1328 (u8 *)&low_sclk_interrupt_t,
1329 sizeof(u32), pi->sram_end);
1330
1331 }
1332
1333 return ret;
1334}
1335
1336static void ci_get_leakage_voltages(struct radeon_device *rdev)
1337{
1338 struct ci_power_info *pi = ci_get_pi(rdev);
1339 u16 leakage_id, virtual_voltage_id;
1340 u16 vddc, vddci;
1341 int i;
1342
1343 pi->vddc_leakage.count = 0;
1344 pi->vddci_leakage.count = 0;
1345
1346 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1347 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1348 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1349 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1350 continue;
1351 if (vddc != 0 && vddc != virtual_voltage_id) {
1352 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1353 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1354 pi->vddc_leakage.count++;
1355 }
1356 }
1357 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1358 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1359 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1360 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1361 virtual_voltage_id,
1362 leakage_id) == 0) {
1363 if (vddc != 0 && vddc != virtual_voltage_id) {
1364 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1365 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1366 pi->vddc_leakage.count++;
1367 }
1368 if (vddci != 0 && vddci != virtual_voltage_id) {
1369 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1370 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1371 pi->vddci_leakage.count++;
1372 }
1373 }
1374 }
1375 }
1376}
1377
1378static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1379{
1380 struct ci_power_info *pi = ci_get_pi(rdev);
1381 bool want_thermal_protection;
1382 enum radeon_dpm_event_src dpm_event_src;
1383 u32 tmp;
1384
1385 switch (sources) {
1386 case 0:
1387 default:
1388 want_thermal_protection = false;
1389 break;
1390 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1391 want_thermal_protection = true;
1392 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1393 break;
1394 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1395 want_thermal_protection = true;
1396 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1397 break;
1398 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1399 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1400 want_thermal_protection = true;
1401 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1402 break;
1403 }
1404
1405 if (want_thermal_protection) {
1406#if 0
1407 /* XXX: need to figure out how to handle this properly */
1408 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1409 tmp &= DPM_EVENT_SRC_MASK;
1410 tmp |= DPM_EVENT_SRC(dpm_event_src);
1411 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1412#endif
1413
1414 tmp = RREG32_SMC(GENERAL_PWRMGT);
1415 if (pi->thermal_protection)
1416 tmp &= ~THERMAL_PROTECTION_DIS;
1417 else
1418 tmp |= THERMAL_PROTECTION_DIS;
1419 WREG32_SMC(GENERAL_PWRMGT, tmp);
1420 } else {
1421 tmp = RREG32_SMC(GENERAL_PWRMGT);
1422 tmp |= THERMAL_PROTECTION_DIS;
1423 WREG32_SMC(GENERAL_PWRMGT, tmp);
1424 }
1425}
1426
1427static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1428 enum radeon_dpm_auto_throttle_src source,
1429 bool enable)
1430{
1431 struct ci_power_info *pi = ci_get_pi(rdev);
1432
1433 if (enable) {
1434 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1435 pi->active_auto_throttle_sources |= 1 << source;
1436 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1437 }
1438 } else {
1439 if (pi->active_auto_throttle_sources & (1 << source)) {
1440 pi->active_auto_throttle_sources &= ~(1 << source);
1441 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1442 }
1443 }
1444}
1445
1446static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1447{
1448 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1449 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1450}
1451
1452static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1453{
1454 struct ci_power_info *pi = ci_get_pi(rdev);
1455 PPSMC_Result smc_result;
1456
1457 if (!pi->need_update_smu7_dpm_table)
1458 return 0;
1459
1460 if ((!pi->sclk_dpm_key_disabled) &&
1461 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1462 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1463 if (smc_result != PPSMC_Result_OK)
1464 return -EINVAL;
1465 }
1466
1467 if ((!pi->mclk_dpm_key_disabled) &&
1468 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1469 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1470 if (smc_result != PPSMC_Result_OK)
1471 return -EINVAL;
1472 }
1473
1474 pi->need_update_smu7_dpm_table = 0;
1475 return 0;
1476}
1477
1478static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1479{
1480 struct ci_power_info *pi = ci_get_pi(rdev);
1481 PPSMC_Result smc_result;
1482
1483 if (enable) {
1484 if (!pi->sclk_dpm_key_disabled) {
1485 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1486 if (smc_result != PPSMC_Result_OK)
1487 return -EINVAL;
1488 }
1489
1490 if (!pi->mclk_dpm_key_disabled) {
1491 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1492 if (smc_result != PPSMC_Result_OK)
1493 return -EINVAL;
1494
1495 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1496
1497 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1498 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1499 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1500
1501 udelay(10);
1502
1503 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1504 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1505 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1506 }
1507 } else {
1508 if (!pi->sclk_dpm_key_disabled) {
1509 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1510 if (smc_result != PPSMC_Result_OK)
1511 return -EINVAL;
1512 }
1513
1514 if (!pi->mclk_dpm_key_disabled) {
1515 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1516 if (smc_result != PPSMC_Result_OK)
1517 return -EINVAL;
1518 }
1519 }
1520
1521 return 0;
1522}
1523
1524static int ci_start_dpm(struct radeon_device *rdev)
1525{
1526 struct ci_power_info *pi = ci_get_pi(rdev);
1527 PPSMC_Result smc_result;
1528 int ret;
1529 u32 tmp;
1530
1531 tmp = RREG32_SMC(GENERAL_PWRMGT);
1532 tmp |= GLOBAL_PWRMGT_EN;
1533 WREG32_SMC(GENERAL_PWRMGT, tmp);
1534
1535 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1536 tmp |= DYNAMIC_PM_EN;
1537 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1538
1539 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1540
1541 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1542
1543 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1544 if (smc_result != PPSMC_Result_OK)
1545 return -EINVAL;
1546
1547 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1548 if (ret)
1549 return ret;
1550
1551 if (!pi->pcie_dpm_key_disabled) {
1552 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1553 if (smc_result != PPSMC_Result_OK)
1554 return -EINVAL;
1555 }
1556
1557 return 0;
1558}
1559
1560static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1561{
1562 struct ci_power_info *pi = ci_get_pi(rdev);
1563 PPSMC_Result smc_result;
1564
1565 if (!pi->need_update_smu7_dpm_table)
1566 return 0;
1567
1568 if ((!pi->sclk_dpm_key_disabled) &&
1569 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1570 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1571 if (smc_result != PPSMC_Result_OK)
1572 return -EINVAL;
1573 }
1574
1575 if ((!pi->mclk_dpm_key_disabled) &&
1576 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1577 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1578 if (smc_result != PPSMC_Result_OK)
1579 return -EINVAL;
1580 }
1581
1582 return 0;
1583}
1584
1585static int ci_stop_dpm(struct radeon_device *rdev)
1586{
1587 struct ci_power_info *pi = ci_get_pi(rdev);
1588 PPSMC_Result smc_result;
1589 int ret;
1590 u32 tmp;
1591
1592 tmp = RREG32_SMC(GENERAL_PWRMGT);
1593 tmp &= ~GLOBAL_PWRMGT_EN;
1594 WREG32_SMC(GENERAL_PWRMGT, tmp);
1595
1596 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1597 tmp &= ~DYNAMIC_PM_EN;
1598 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1599
1600 if (!pi->pcie_dpm_key_disabled) {
1601 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1602 if (smc_result != PPSMC_Result_OK)
1603 return -EINVAL;
1604 }
1605
1606 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1607 if (ret)
1608 return ret;
1609
1610 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1611 if (smc_result != PPSMC_Result_OK)
1612 return -EINVAL;
1613
1614 return 0;
1615}
1616
1617static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1618{
1619 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1620
1621 if (enable)
1622 tmp &= ~SCLK_PWRMGT_OFF;
1623 else
1624 tmp |= SCLK_PWRMGT_OFF;
1625 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1626}
1627
1628#if 0
1629static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1630 bool ac_power)
1631{
1632 struct ci_power_info *pi = ci_get_pi(rdev);
1633 struct radeon_cac_tdp_table *cac_tdp_table =
1634 rdev->pm.dpm.dyn_state.cac_tdp_table;
1635 u32 power_limit;
1636
1637 if (ac_power)
1638 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1639 else
1640 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1641
1642 ci_set_power_limit(rdev, power_limit);
1643
1644 if (pi->caps_automatic_dc_transition) {
1645 if (ac_power)
1646 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1647 else
1648 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1649 }
1650
1651 return 0;
1652}
1653#endif
1654
1655static PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
1656{
1657 u32 tmp;
1658 int i;
1659
1660 if (!ci_is_smc_running(rdev))
1661 return PPSMC_Result_Failed;
1662
1663 WREG32(SMC_MESSAGE_0, msg);
1664
1665 for (i = 0; i < rdev->usec_timeout; i++) {
1666 tmp = RREG32(SMC_RESP_0);
1667 if (tmp != 0)
1668 break;
1669 udelay(1);
1670 }
1671 tmp = RREG32(SMC_RESP_0);
1672
1673 return (PPSMC_Result)tmp;
1674}
1675
1676static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1677 PPSMC_Msg msg, u32 parameter)
1678{
1679 WREG32(SMC_MSG_ARG_0, parameter);
1680 return ci_send_msg_to_smc(rdev, msg);
1681}
1682
1683static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1684 PPSMC_Msg msg, u32 *parameter)
1685{
1686 PPSMC_Result smc_result;
1687
1688 smc_result = ci_send_msg_to_smc(rdev, msg);
1689
1690 if ((smc_result == PPSMC_Result_OK) && parameter)
1691 *parameter = RREG32(SMC_MSG_ARG_0);
1692
1693 return smc_result;
1694}
1695
1696static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1697{
1698 struct ci_power_info *pi = ci_get_pi(rdev);
1699
1700 if (!pi->sclk_dpm_key_disabled) {
1701 PPSMC_Result smc_result =
1702 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1703 if (smc_result != PPSMC_Result_OK)
1704 return -EINVAL;
1705 }
1706
1707 return 0;
1708}
1709
1710static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1711{
1712 struct ci_power_info *pi = ci_get_pi(rdev);
1713
1714 if (!pi->mclk_dpm_key_disabled) {
1715 PPSMC_Result smc_result =
1716 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1717 if (smc_result != PPSMC_Result_OK)
1718 return -EINVAL;
1719 }
1720
1721 return 0;
1722}
1723
1724static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1725{
1726 struct ci_power_info *pi = ci_get_pi(rdev);
1727
1728 if (!pi->pcie_dpm_key_disabled) {
1729 PPSMC_Result smc_result =
1730 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1731 if (smc_result != PPSMC_Result_OK)
1732 return -EINVAL;
1733 }
1734
1735 return 0;
1736}
1737
1738static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1739{
1740 struct ci_power_info *pi = ci_get_pi(rdev);
1741
1742 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1743 PPSMC_Result smc_result =
1744 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1745 if (smc_result != PPSMC_Result_OK)
1746 return -EINVAL;
1747 }
1748
1749 return 0;
1750}
1751
1752static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1753 u32 target_tdp)
1754{
1755 PPSMC_Result smc_result =
1756 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1757 if (smc_result != PPSMC_Result_OK)
1758 return -EINVAL;
1759 return 0;
1760}
1761
1762#if 0
1763static int ci_set_boot_state(struct radeon_device *rdev)
1764{
1765 return ci_enable_sclk_mclk_dpm(rdev, false);
1766}
1767#endif
1768
1769static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1770{
1771 u32 sclk_freq;
1772 PPSMC_Result smc_result =
1773 ci_send_msg_to_smc_return_parameter(rdev,
1774 PPSMC_MSG_API_GetSclkFrequency,
1775 &sclk_freq);
1776 if (smc_result != PPSMC_Result_OK)
1777 sclk_freq = 0;
1778
1779 return sclk_freq;
1780}
1781
1782static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1783{
1784 u32 mclk_freq;
1785 PPSMC_Result smc_result =
1786 ci_send_msg_to_smc_return_parameter(rdev,
1787 PPSMC_MSG_API_GetMclkFrequency,
1788 &mclk_freq);
1789 if (smc_result != PPSMC_Result_OK)
1790 mclk_freq = 0;
1791
1792 return mclk_freq;
1793}
1794
1795static void ci_dpm_start_smc(struct radeon_device *rdev)
1796{
1797 int i;
1798
1799 ci_program_jump_on_start(rdev);
1800 ci_start_smc_clock(rdev);
1801 ci_start_smc(rdev);
1802 for (i = 0; i < rdev->usec_timeout; i++) {
1803 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1804 break;
1805 }
1806}
1807
1808static void ci_dpm_stop_smc(struct radeon_device *rdev)
1809{
1810 ci_reset_smc(rdev);
1811 ci_stop_smc_clock(rdev);
1812}
1813
1814static int ci_process_firmware_header(struct radeon_device *rdev)
1815{
1816 struct ci_power_info *pi = ci_get_pi(rdev);
1817 u32 tmp;
1818 int ret;
1819
1820 ret = ci_read_smc_sram_dword(rdev,
1821 SMU7_FIRMWARE_HEADER_LOCATION +
1822 offsetof(SMU7_Firmware_Header, DpmTable),
1823 &tmp, pi->sram_end);
1824 if (ret)
1825 return ret;
1826
1827 pi->dpm_table_start = tmp;
1828
1829 ret = ci_read_smc_sram_dword(rdev,
1830 SMU7_FIRMWARE_HEADER_LOCATION +
1831 offsetof(SMU7_Firmware_Header, SoftRegisters),
1832 &tmp, pi->sram_end);
1833 if (ret)
1834 return ret;
1835
1836 pi->soft_regs_start = tmp;
1837
1838 ret = ci_read_smc_sram_dword(rdev,
1839 SMU7_FIRMWARE_HEADER_LOCATION +
1840 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1841 &tmp, pi->sram_end);
1842 if (ret)
1843 return ret;
1844
1845 pi->mc_reg_table_start = tmp;
1846
1847 ret = ci_read_smc_sram_dword(rdev,
1848 SMU7_FIRMWARE_HEADER_LOCATION +
1849 offsetof(SMU7_Firmware_Header, FanTable),
1850 &tmp, pi->sram_end);
1851 if (ret)
1852 return ret;
1853
1854 pi->fan_table_start = tmp;
1855
1856 ret = ci_read_smc_sram_dword(rdev,
1857 SMU7_FIRMWARE_HEADER_LOCATION +
1858 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1859 &tmp, pi->sram_end);
1860 if (ret)
1861 return ret;
1862
1863 pi->arb_table_start = tmp;
1864
1865 return 0;
1866}
1867
1868static void ci_read_clock_registers(struct radeon_device *rdev)
1869{
1870 struct ci_power_info *pi = ci_get_pi(rdev);
1871
1872 pi->clock_registers.cg_spll_func_cntl =
1873 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1874 pi->clock_registers.cg_spll_func_cntl_2 =
1875 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1876 pi->clock_registers.cg_spll_func_cntl_3 =
1877 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1878 pi->clock_registers.cg_spll_func_cntl_4 =
1879 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1880 pi->clock_registers.cg_spll_spread_spectrum =
1881 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1882 pi->clock_registers.cg_spll_spread_spectrum_2 =
1883 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1884 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1885 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1886 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1887 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1888 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1889 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1890 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1891 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1892 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1893}
1894
1895static void ci_init_sclk_t(struct radeon_device *rdev)
1896{
1897 struct ci_power_info *pi = ci_get_pi(rdev);
1898
1899 pi->low_sclk_interrupt_t = 0;
1900}
1901
1902static void ci_enable_thermal_protection(struct radeon_device *rdev,
1903 bool enable)
1904{
1905 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1906
1907 if (enable)
1908 tmp &= ~THERMAL_PROTECTION_DIS;
1909 else
1910 tmp |= THERMAL_PROTECTION_DIS;
1911 WREG32_SMC(GENERAL_PWRMGT, tmp);
1912}
1913
1914static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1915{
1916 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1917
1918 tmp |= STATIC_PM_EN;
1919
1920 WREG32_SMC(GENERAL_PWRMGT, tmp);
1921}
1922
1923#if 0
1924static int ci_enter_ulp_state(struct radeon_device *rdev)
1925{
1926
1927 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1928
1929 udelay(25000);
1930
1931 return 0;
1932}
1933
1934static int ci_exit_ulp_state(struct radeon_device *rdev)
1935{
1936 int i;
1937
1938 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1939
1940 udelay(7000);
1941
1942 for (i = 0; i < rdev->usec_timeout; i++) {
1943 if (RREG32(SMC_RESP_0) == 1)
1944 break;
1945 udelay(1000);
1946 }
1947
1948 return 0;
1949}
1950#endif
1951
1952static int ci_notify_smc_display_change(struct radeon_device *rdev,
1953 bool has_display)
1954{
1955 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1956
1957 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1958}
1959
1960static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1961 bool enable)
1962{
1963 struct ci_power_info *pi = ci_get_pi(rdev);
1964
1965 if (enable) {
1966 if (pi->caps_sclk_ds) {
1967 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1968 return -EINVAL;
1969 } else {
1970 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1971 return -EINVAL;
1972 }
1973 } else {
1974 if (pi->caps_sclk_ds) {
1975 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1976 return -EINVAL;
1977 }
1978 }
1979
1980 return 0;
1981}
1982
1983static void ci_program_display_gap(struct radeon_device *rdev)
1984{
1985 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1986 u32 pre_vbi_time_in_us;
1987 u32 frame_time_in_us;
1988 u32 ref_clock = rdev->clock.spll.reference_freq;
1989 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1990 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1991
1992 tmp &= ~DISP_GAP_MASK;
1993 if (rdev->pm.dpm.new_active_crtc_count > 0)
1994 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1995 else
1996 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1997 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1998
1999 if (refresh_rate == 0)
2000 refresh_rate = 60;
2001 if (vblank_time == 0xffffffff)
2002 vblank_time = 500;
2003 frame_time_in_us = 1000000 / refresh_rate;
2004 pre_vbi_time_in_us =
2005 frame_time_in_us - 200 - vblank_time;
2006 tmp = pre_vbi_time_in_us * (ref_clock / 100);
2007
2008 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
2009 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
2010 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
2011
2012
2013 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
2014
2015}
2016
2017static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2018{
2019 struct ci_power_info *pi = ci_get_pi(rdev);
2020 u32 tmp;
2021
2022 if (enable) {
2023 if (pi->caps_sclk_ss_support) {
2024 tmp = RREG32_SMC(GENERAL_PWRMGT);
2025 tmp |= DYN_SPREAD_SPECTRUM_EN;
2026 WREG32_SMC(GENERAL_PWRMGT, tmp);
2027 }
2028 } else {
2029 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2030 tmp &= ~SSEN;
2031 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2032
2033 tmp = RREG32_SMC(GENERAL_PWRMGT);
2034 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2035 WREG32_SMC(GENERAL_PWRMGT, tmp);
2036 }
2037}
2038
2039static void ci_program_sstp(struct radeon_device *rdev)
2040{
2041 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2042}
2043
2044static void ci_enable_display_gap(struct radeon_device *rdev)
2045{
2046 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2047
2048 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2049 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2050 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2051
2052 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2053}
2054
2055static void ci_program_vc(struct radeon_device *rdev)
2056{
2057 u32 tmp;
2058
2059 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2060 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2061 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2062
2063 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2064 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2065 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2066 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2067 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2068 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2069 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2070 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2071}
2072
2073static void ci_clear_vc(struct radeon_device *rdev)
2074{
2075 u32 tmp;
2076
2077 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2078 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2079 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2080
2081 WREG32_SMC(CG_FTV_0, 0);
2082 WREG32_SMC(CG_FTV_1, 0);
2083 WREG32_SMC(CG_FTV_2, 0);
2084 WREG32_SMC(CG_FTV_3, 0);
2085 WREG32_SMC(CG_FTV_4, 0);
2086 WREG32_SMC(CG_FTV_5, 0);
2087 WREG32_SMC(CG_FTV_6, 0);
2088 WREG32_SMC(CG_FTV_7, 0);
2089}
2090
2091static int ci_upload_firmware(struct radeon_device *rdev)
2092{
2093 struct ci_power_info *pi = ci_get_pi(rdev);
2094 int i, ret;
2095
2096 for (i = 0; i < rdev->usec_timeout; i++) {
2097 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2098 break;
2099 }
2100 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2101
2102 ci_stop_smc_clock(rdev);
2103 ci_reset_smc(rdev);
2104
2105 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2106
2107 return ret;
2108
2109}
2110
2111static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2112 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2113 struct atom_voltage_table *voltage_table)
2114{
2115 u32 i;
2116
2117 if (voltage_dependency_table == NULL)
2118 return -EINVAL;
2119
2120 voltage_table->mask_low = 0;
2121 voltage_table->phase_delay = 0;
2122
2123 voltage_table->count = voltage_dependency_table->count;
2124 for (i = 0; i < voltage_table->count; i++) {
2125 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2126 voltage_table->entries[i].smio_low = 0;
2127 }
2128
2129 return 0;
2130}
2131
2132static int ci_construct_voltage_tables(struct radeon_device *rdev)
2133{
2134 struct ci_power_info *pi = ci_get_pi(rdev);
2135 int ret;
2136
2137 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2138 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2139 VOLTAGE_OBJ_GPIO_LUT,
2140 &pi->vddc_voltage_table);
2141 if (ret)
2142 return ret;
2143 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2144 ret = ci_get_svi2_voltage_table(rdev,
2145 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2146 &pi->vddc_voltage_table);
2147 if (ret)
2148 return ret;
2149 }
2150
2151 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2152 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2153 &pi->vddc_voltage_table);
2154
2155 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2156 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2157 VOLTAGE_OBJ_GPIO_LUT,
2158 &pi->vddci_voltage_table);
2159 if (ret)
2160 return ret;
2161 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2162 ret = ci_get_svi2_voltage_table(rdev,
2163 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2164 &pi->vddci_voltage_table);
2165 if (ret)
2166 return ret;
2167 }
2168
2169 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2170 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2171 &pi->vddci_voltage_table);
2172
2173 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2174 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2175 VOLTAGE_OBJ_GPIO_LUT,
2176 &pi->mvdd_voltage_table);
2177 if (ret)
2178 return ret;
2179 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2180 ret = ci_get_svi2_voltage_table(rdev,
2181 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2182 &pi->mvdd_voltage_table);
2183 if (ret)
2184 return ret;
2185 }
2186
2187 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2188 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2189 &pi->mvdd_voltage_table);
2190
2191 return 0;
2192}
2193
2194static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2195 struct atom_voltage_table_entry *voltage_table,
2196 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2197{
2198 int ret;
2199
2200 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2201 &smc_voltage_table->StdVoltageHiSidd,
2202 &smc_voltage_table->StdVoltageLoSidd);
2203
2204 if (ret) {
2205 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2206 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2207 }
2208
2209 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2210 smc_voltage_table->StdVoltageHiSidd =
2211 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2212 smc_voltage_table->StdVoltageLoSidd =
2213 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2214}
2215
2216static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2217 SMU7_Discrete_DpmTable *table)
2218{
2219 struct ci_power_info *pi = ci_get_pi(rdev);
2220 unsigned int count;
2221
2222 table->VddcLevelCount = pi->vddc_voltage_table.count;
2223 for (count = 0; count < table->VddcLevelCount; count++) {
2224 ci_populate_smc_voltage_table(rdev,
2225 &pi->vddc_voltage_table.entries[count],
2226 &table->VddcLevel[count]);
2227
2228 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2229 table->VddcLevel[count].Smio |=
2230 pi->vddc_voltage_table.entries[count].smio_low;
2231 else
2232 table->VddcLevel[count].Smio = 0;
2233 }
2234 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2235
2236 return 0;
2237}
2238
2239static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2240 SMU7_Discrete_DpmTable *table)
2241{
2242 unsigned int count;
2243 struct ci_power_info *pi = ci_get_pi(rdev);
2244
2245 table->VddciLevelCount = pi->vddci_voltage_table.count;
2246 for (count = 0; count < table->VddciLevelCount; count++) {
2247 ci_populate_smc_voltage_table(rdev,
2248 &pi->vddci_voltage_table.entries[count],
2249 &table->VddciLevel[count]);
2250
2251 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2252 table->VddciLevel[count].Smio |=
2253 pi->vddci_voltage_table.entries[count].smio_low;
2254 else
2255 table->VddciLevel[count].Smio = 0;
2256 }
2257 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2258
2259 return 0;
2260}
2261
2262static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2263 SMU7_Discrete_DpmTable *table)
2264{
2265 struct ci_power_info *pi = ci_get_pi(rdev);
2266 unsigned int count;
2267
2268 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2269 for (count = 0; count < table->MvddLevelCount; count++) {
2270 ci_populate_smc_voltage_table(rdev,
2271 &pi->mvdd_voltage_table.entries[count],
2272 &table->MvddLevel[count]);
2273
2274 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2275 table->MvddLevel[count].Smio |=
2276 pi->mvdd_voltage_table.entries[count].smio_low;
2277 else
2278 table->MvddLevel[count].Smio = 0;
2279 }
2280 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2281
2282 return 0;
2283}
2284
2285static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2286 SMU7_Discrete_DpmTable *table)
2287{
2288 int ret;
2289
2290 ret = ci_populate_smc_vddc_table(rdev, table);
2291 if (ret)
2292 return ret;
2293
2294 ret = ci_populate_smc_vddci_table(rdev, table);
2295 if (ret)
2296 return ret;
2297
2298 ret = ci_populate_smc_mvdd_table(rdev, table);
2299 if (ret)
2300 return ret;
2301
2302 return 0;
2303}
2304
2305static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2306 SMU7_Discrete_VoltageLevel *voltage)
2307{
2308 struct ci_power_info *pi = ci_get_pi(rdev);
2309 u32 i = 0;
2310
2311 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2312 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2313 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2314 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2315 break;
2316 }
2317 }
2318
2319 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2320 return -EINVAL;
2321 }
2322
2323 return -EINVAL;
2324}
2325
2326static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2327 struct atom_voltage_table_entry *voltage_table,
2328 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2329{
2330 u16 v_index, idx;
2331 bool voltage_found = false;
2332 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2333 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2334
2335 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2336 return -EINVAL;
2337
2338 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2339 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2340 if (voltage_table->value ==
2341 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2342 voltage_found = true;
2343 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2344 idx = v_index;
2345 else
2346 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2347 *std_voltage_lo_sidd =
2348 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2349 *std_voltage_hi_sidd =
2350 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2351 break;
2352 }
2353 }
2354
2355 if (!voltage_found) {
2356 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2357 if (voltage_table->value <=
2358 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2359 voltage_found = true;
2360 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2361 idx = v_index;
2362 else
2363 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2364 *std_voltage_lo_sidd =
2365 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2366 *std_voltage_hi_sidd =
2367 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2368 break;
2369 }
2370 }
2371 }
2372 }
2373
2374 return 0;
2375}
2376
2377static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2378 const struct radeon_phase_shedding_limits_table *limits,
2379 u32 sclk,
2380 u32 *phase_shedding)
2381{
2382 unsigned int i;
2383
2384 *phase_shedding = 1;
2385
2386 for (i = 0; i < limits->count; i++) {
2387 if (sclk < limits->entries[i].sclk) {
2388 *phase_shedding = i;
2389 break;
2390 }
2391 }
2392}
2393
2394static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2395 const struct radeon_phase_shedding_limits_table *limits,
2396 u32 mclk,
2397 u32 *phase_shedding)
2398{
2399 unsigned int i;
2400
2401 *phase_shedding = 1;
2402
2403 for (i = 0; i < limits->count; i++) {
2404 if (mclk < limits->entries[i].mclk) {
2405 *phase_shedding = i;
2406 break;
2407 }
2408 }
2409}
2410
2411static int ci_init_arb_table_index(struct radeon_device *rdev)
2412{
2413 struct ci_power_info *pi = ci_get_pi(rdev);
2414 u32 tmp;
2415 int ret;
2416
2417 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2418 &tmp, pi->sram_end);
2419 if (ret)
2420 return ret;
2421
2422 tmp &= 0x00FFFFFF;
2423 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2424
2425 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2426 tmp, pi->sram_end);
2427}
2428
2429static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2430 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2431 u32 clock, u32 *voltage)
2432{
2433 u32 i = 0;
2434
2435 if (allowed_clock_voltage_table->count == 0)
2436 return -EINVAL;
2437
2438 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2439 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2440 *voltage = allowed_clock_voltage_table->entries[i].v;
2441 return 0;
2442 }
2443 }
2444
2445 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2446
2447 return 0;
2448}
2449
2450static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2451 u32 sclk, u32 min_sclk_in_sr)
2452{
2453 u32 i;
2454 u32 tmp;
2455 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2456 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2457
2458 if (sclk < min)
2459 return 0;
2460
2461 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2462 tmp = sclk / (1 << i);
2463 if (tmp >= min || i == 0)
2464 break;
2465 }
2466
2467 return (u8)i;
2468}
2469
2470static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2471{
2472 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2473}
2474
2475static int ci_reset_to_default(struct radeon_device *rdev)
2476{
2477 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2478 0 : -EINVAL;
2479}
2480
2481static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2482{
2483 u32 tmp;
2484
2485 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2486
2487 if (tmp == MC_CG_ARB_FREQ_F0)
2488 return 0;
2489
2490 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2491}
2492
2493static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2494 const u32 engine_clock,
2495 const u32 memory_clock,
2496 u32 *dram_timimg2)
2497{
2498 bool patch;
2499 u32 tmp, tmp2;
2500
2501 tmp = RREG32(MC_SEQ_MISC0);
2502 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2503
2504 if (patch &&
2505 ((rdev->pdev->device == 0x67B0) ||
2506 (rdev->pdev->device == 0x67B1))) {
2507 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2508 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2509 *dram_timimg2 &= ~0x00ff0000;
2510 *dram_timimg2 |= tmp2 << 16;
2511 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2512 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2513 *dram_timimg2 &= ~0x00ff0000;
2514 *dram_timimg2 |= tmp2 << 16;
2515 }
2516 }
2517}
2518
2519
2520static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2521 u32 sclk,
2522 u32 mclk,
2523 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2524{
2525 u32 dram_timing;
2526 u32 dram_timing2;
2527 u32 burst_time;
2528
2529 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2530
2531 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2532 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2533 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2534
2535 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2536
2537 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2538 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2539 arb_regs->McArbBurstTime = (u8)burst_time;
2540
2541 return 0;
2542}
2543
2544static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2545{
2546 struct ci_power_info *pi = ci_get_pi(rdev);
2547 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2548 u32 i, j;
2549 int ret = 0;
2550
2551 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2552
2553 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2554 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2555 ret = ci_populate_memory_timing_parameters(rdev,
2556 pi->dpm_table.sclk_table.dpm_levels[i].value,
2557 pi->dpm_table.mclk_table.dpm_levels[j].value,
2558 &arb_regs.entries[i][j]);
2559 if (ret)
2560 break;
2561 }
2562 }
2563
2564 if (ret == 0)
2565 ret = ci_copy_bytes_to_smc(rdev,
2566 pi->arb_table_start,
2567 (u8 *)&arb_regs,
2568 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2569 pi->sram_end);
2570
2571 return ret;
2572}
2573
2574static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2575{
2576 struct ci_power_info *pi = ci_get_pi(rdev);
2577
2578 if (pi->need_update_smu7_dpm_table == 0)
2579 return 0;
2580
2581 return ci_do_program_memory_timing_parameters(rdev);
2582}
2583
2584static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2585 struct radeon_ps *radeon_boot_state)
2586{
2587 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2588 struct ci_power_info *pi = ci_get_pi(rdev);
2589 u32 level = 0;
2590
2591 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2592 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2593 boot_state->performance_levels[0].sclk) {
2594 pi->smc_state_table.GraphicsBootLevel = level;
2595 break;
2596 }
2597 }
2598
2599 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2600 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2601 boot_state->performance_levels[0].mclk) {
2602 pi->smc_state_table.MemoryBootLevel = level;
2603 break;
2604 }
2605 }
2606}
2607
2608static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2609{
2610 u32 i;
2611 u32 mask_value = 0;
2612
2613 for (i = dpm_table->count; i > 0; i--) {
2614 mask_value = mask_value << 1;
2615 if (dpm_table->dpm_levels[i-1].enabled)
2616 mask_value |= 0x1;
2617 else
2618 mask_value &= 0xFFFFFFFE;
2619 }
2620
2621 return mask_value;
2622}
2623
2624static void ci_populate_smc_link_level(struct radeon_device *rdev,
2625 SMU7_Discrete_DpmTable *table)
2626{
2627 struct ci_power_info *pi = ci_get_pi(rdev);
2628 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2629 u32 i;
2630
2631 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2632 table->LinkLevel[i].PcieGenSpeed =
2633 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2634 table->LinkLevel[i].PcieLaneCount =
2635 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2636 table->LinkLevel[i].EnabledForActivity = 1;
2637 table->LinkLevel[i].DownT = cpu_to_be32(5);
2638 table->LinkLevel[i].UpT = cpu_to_be32(30);
2639 }
2640
2641 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2642 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2643 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2644}
2645
2646static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2647 SMU7_Discrete_DpmTable *table)
2648{
2649 u32 count;
2650 struct atom_clock_dividers dividers;
2651 int ret = -EINVAL;
2652
2653 table->UvdLevelCount =
2654 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2655
2656 for (count = 0; count < table->UvdLevelCount; count++) {
2657 table->UvdLevel[count].VclkFrequency =
2658 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2659 table->UvdLevel[count].DclkFrequency =
2660 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2661 table->UvdLevel[count].MinVddc =
2662 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2663 table->UvdLevel[count].MinVddcPhases = 1;
2664
2665 ret = radeon_atom_get_clock_dividers(rdev,
2666 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2667 table->UvdLevel[count].VclkFrequency, false, &dividers);
2668 if (ret)
2669 return ret;
2670
2671 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2672
2673 ret = radeon_atom_get_clock_dividers(rdev,
2674 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2675 table->UvdLevel[count].DclkFrequency, false, &dividers);
2676 if (ret)
2677 return ret;
2678
2679 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2680
2681 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2682 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2683 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2684 }
2685
2686 return ret;
2687}
2688
2689static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2690 SMU7_Discrete_DpmTable *table)
2691{
2692 u32 count;
2693 struct atom_clock_dividers dividers;
2694 int ret = -EINVAL;
2695
2696 table->VceLevelCount =
2697 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2698
2699 for (count = 0; count < table->VceLevelCount; count++) {
2700 table->VceLevel[count].Frequency =
2701 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2702 table->VceLevel[count].MinVoltage =
2703 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2704 table->VceLevel[count].MinPhases = 1;
2705
2706 ret = radeon_atom_get_clock_dividers(rdev,
2707 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2708 table->VceLevel[count].Frequency, false, &dividers);
2709 if (ret)
2710 return ret;
2711
2712 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2713
2714 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2715 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2716 }
2717
2718 return ret;
2719
2720}
2721
2722static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2723 SMU7_Discrete_DpmTable *table)
2724{
2725 u32 count;
2726 struct atom_clock_dividers dividers;
2727 int ret = -EINVAL;
2728
2729 table->AcpLevelCount = (u8)
2730 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2731
2732 for (count = 0; count < table->AcpLevelCount; count++) {
2733 table->AcpLevel[count].Frequency =
2734 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2735 table->AcpLevel[count].MinVoltage =
2736 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2737 table->AcpLevel[count].MinPhases = 1;
2738
2739 ret = radeon_atom_get_clock_dividers(rdev,
2740 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2741 table->AcpLevel[count].Frequency, false, &dividers);
2742 if (ret)
2743 return ret;
2744
2745 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2746
2747 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2748 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2749 }
2750
2751 return ret;
2752}
2753
2754static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2755 SMU7_Discrete_DpmTable *table)
2756{
2757 u32 count;
2758 struct atom_clock_dividers dividers;
2759 int ret = -EINVAL;
2760
2761 table->SamuLevelCount =
2762 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2763
2764 for (count = 0; count < table->SamuLevelCount; count++) {
2765 table->SamuLevel[count].Frequency =
2766 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2767 table->SamuLevel[count].MinVoltage =
2768 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2769 table->SamuLevel[count].MinPhases = 1;
2770
2771 ret = radeon_atom_get_clock_dividers(rdev,
2772 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2773 table->SamuLevel[count].Frequency, false, &dividers);
2774 if (ret)
2775 return ret;
2776
2777 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2778
2779 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2780 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2781 }
2782
2783 return ret;
2784}
2785
2786static int ci_calculate_mclk_params(struct radeon_device *rdev,
2787 u32 memory_clock,
2788 SMU7_Discrete_MemoryLevel *mclk,
2789 bool strobe_mode,
2790 bool dll_state_on)
2791{
2792 struct ci_power_info *pi = ci_get_pi(rdev);
2793 u32 dll_cntl = pi->clock_registers.dll_cntl;
2794 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2795 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2796 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2797 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2798 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2799 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2800 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2801 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2802 struct atom_mpll_param mpll_param;
2803 int ret;
2804
2805 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2806 if (ret)
2807 return ret;
2808
2809 mpll_func_cntl &= ~BWCTRL_MASK;
2810 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2811
2812 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2813 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2814 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2815
2816 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2817 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2818
2819 if (pi->mem_gddr5) {
2820 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2821 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2822 YCLK_POST_DIV(mpll_param.post_div);
2823 }
2824
2825 if (pi->caps_mclk_ss_support) {
2826 struct radeon_atom_ss ss;
2827 u32 freq_nom;
2828 u32 tmp;
2829 u32 reference_clock = rdev->clock.mpll.reference_freq;
2830
2831 if (mpll_param.qdr == 1)
2832 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2833 else
2834 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2835
2836 tmp = (freq_nom / reference_clock);
2837 tmp = tmp * tmp;
2838 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2839 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2840 u32 clks = reference_clock * 5 / ss.rate;
2841 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2842
2843 mpll_ss1 &= ~CLKV_MASK;
2844 mpll_ss1 |= CLKV(clkv);
2845
2846 mpll_ss2 &= ~CLKS_MASK;
2847 mpll_ss2 |= CLKS(clks);
2848 }
2849 }
2850
2851 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2852 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2853
2854 if (dll_state_on)
2855 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2856 else
2857 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2858
2859 mclk->MclkFrequency = memory_clock;
2860 mclk->MpllFuncCntl = mpll_func_cntl;
2861 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2862 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2863 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2864 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2865 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2866 mclk->DllCntl = dll_cntl;
2867 mclk->MpllSs1 = mpll_ss1;
2868 mclk->MpllSs2 = mpll_ss2;
2869
2870 return 0;
2871}
2872
2873static int ci_populate_single_memory_level(struct radeon_device *rdev,
2874 u32 memory_clock,
2875 SMU7_Discrete_MemoryLevel *memory_level)
2876{
2877 struct ci_power_info *pi = ci_get_pi(rdev);
2878 int ret;
2879 bool dll_state_on;
2880
2881 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2882 ret = ci_get_dependency_volt_by_clk(rdev,
2883 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2884 memory_clock, &memory_level->MinVddc);
2885 if (ret)
2886 return ret;
2887 }
2888
2889 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2890 ret = ci_get_dependency_volt_by_clk(rdev,
2891 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2892 memory_clock, &memory_level->MinVddci);
2893 if (ret)
2894 return ret;
2895 }
2896
2897 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2898 ret = ci_get_dependency_volt_by_clk(rdev,
2899 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2900 memory_clock, &memory_level->MinMvdd);
2901 if (ret)
2902 return ret;
2903 }
2904
2905 memory_level->MinVddcPhases = 1;
2906
2907 if (pi->vddc_phase_shed_control)
2908 ci_populate_phase_value_based_on_mclk(rdev,
2909 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2910 memory_clock,
2911 &memory_level->MinVddcPhases);
2912
2913 memory_level->EnabledForThrottle = 1;
2914 memory_level->UpH = 0;
2915 memory_level->DownH = 100;
2916 memory_level->VoltageDownH = 0;
2917 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2918
2919 memory_level->StutterEnable = false;
2920 memory_level->StrobeEnable = false;
2921 memory_level->EdcReadEnable = false;
2922 memory_level->EdcWriteEnable = false;
2923 memory_level->RttEnable = false;
2924
2925 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2926
2927 if (pi->mclk_stutter_mode_threshold &&
2928 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2929 (pi->uvd_enabled == false) &&
2930 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2931 (rdev->pm.dpm.new_active_crtc_count <= 2))
2932 memory_level->StutterEnable = true;
2933
2934 if (pi->mclk_strobe_mode_threshold &&
2935 (memory_clock <= pi->mclk_strobe_mode_threshold))
2936 memory_level->StrobeEnable = 1;
2937
2938 if (pi->mem_gddr5) {
2939 memory_level->StrobeRatio =
2940 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2941 if (pi->mclk_edc_enable_threshold &&
2942 (memory_clock > pi->mclk_edc_enable_threshold))
2943 memory_level->EdcReadEnable = true;
2944
2945 if (pi->mclk_edc_wr_enable_threshold &&
2946 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2947 memory_level->EdcWriteEnable = true;
2948
2949 if (memory_level->StrobeEnable) {
2950 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2951 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2952 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2953 else
2954 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2955 } else {
2956 dll_state_on = pi->dll_default_on;
2957 }
2958 } else {
2959 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2960 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2961 }
2962
2963 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2964 if (ret)
2965 return ret;
2966
2967 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2968 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2969 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2970 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2971
2972 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2973 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2974 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2975 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2976 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2977 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2978 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2979 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2980 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2981 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2982 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2983
2984 return 0;
2985}
2986
2987static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2988 SMU7_Discrete_DpmTable *table)
2989{
2990 struct ci_power_info *pi = ci_get_pi(rdev);
2991 struct atom_clock_dividers dividers;
2992 SMU7_Discrete_VoltageLevel voltage_level;
2993 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2994 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2995 u32 dll_cntl = pi->clock_registers.dll_cntl;
2996 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2997 int ret;
2998
2999 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
3000
3001 if (pi->acpi_vddc)
3002 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
3003 else
3004 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
3005
3006 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
3007
3008 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
3009
3010 ret = radeon_atom_get_clock_dividers(rdev,
3011 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3012 table->ACPILevel.SclkFrequency, false, &dividers);
3013 if (ret)
3014 return ret;
3015
3016 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
3017 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3018 table->ACPILevel.DeepSleepDivId = 0;
3019
3020 spll_func_cntl &= ~SPLL_PWRON;
3021 spll_func_cntl |= SPLL_RESET;
3022
3023 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3024 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3025
3026 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3027 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3028 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3029 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3030